EXPERIMENT NO: 01

PULSE CODE MODULATION AND DEMODULATION

AIM:
To analyze a PCM system and interpret the modulated and demodulated waveforms .
APPARATUS:
1. PCM modulator trainer
2. PCM Demodulator trainer
3. C.R.O (30MHz)
4. Patch chords.

BLOCK DIAGRAM: PCM MODULATOR & DEMODULATOR

THEORY
Regulated power supply (68M & 68D):
This consists of a bridge rectifier followed by capacitor filters and three terminal
regulators 7805 and 7905 to provide regulated DC voltages of +5V and +12V @ 300Ma each to
the on board circuits. These supplies have been internally connected to the circuits, so no
external connections are required for operation.
Audio Frequency (AF) Signal generator (68M):
Sine wave signal of 200Hz is generated to use as a modulating (message or information)
signal to be transmitted. This is an Op-Amp based Wein bridge Oscillators using IC TL084. IC
TL084 is a FET input general purpose Operational Amplifier. Amplitude control is provided in
the circuit to vary the output amplitude of AF signal.
Clock generator/Timing circuit (68M & 68D):
A TTL compatible clock signal of 64 KHz and 4KHz frequency are provided on board to
use as a clock to the various circuits in the system. This circuit is a astable multivibrator using
555 timer followed by a buffer and frequency dividers.
DC source (68M):
A 0 to +5V variable DC voltage is provided on board to use as a modulating signal
instead of AF signal. This is useful to study step by operation of PCM modulation and
demodulation. This is a simple circuit consisting of potentiometer and fixed power supply.
Low pass filters (68D):
This is a series of simple RC networks provided on board to smoothen the output of the
D/A converter output (stair case signal). RC values are chosen such that the cutoff frequency
would be at 200Hz

Amplifiers (68D):
This is an Op-amp (IC TL084) based non-inverting variable gain amplifiers provided on
board to amplify the recovered message singles i.e. output of the Low pass filter to desired level.
Amplitude control is provided in circuit to vary the gain of the amplifier between 0 and 3.
AC/DC Switch facilitates to couple the input signal through capacitor or directly to the amplifier
input.

PCM Operation:
the block diagram of the PCM system. The modulating signal is applied to sample &
hold circuit. This applied signal will be super imposed by +2.5V DC so that the negative portion
the modulating signal will clamped to positive, this process is needed, because input of the A/D
Converter should be between 0 and +5V. After level shifting is done the signal will be passed to
sample & hold circuit. Sample & hold circuit will sample the input signal during on period of the
clock signal and will hold the sampled output till next pulse comes. Sampling rate is 4KHz in
this system.
So input of the A/D Converter is a stable voltage of certain level in between 0 and +5V.
A/D converter (encoder) will give a predetermined 8 bit code for the sampled input. This entire
conversion process will be made at a fast rate as ADC0808 is operating at high frequency clock
i.e. 1MHz. Coded output of the A/D converter is applied to input of the parallel in serial out
register through a latch (741s373). This shift register is operating at 64KHz (sampling frequency
is 4KHz, so to shift 8 bits from parallel to serial we need 64KHz). This output (PCM) is
transmitted through a co-axial cable which represents a communication channel.
PCM signal from modulator (encoder) is applied to serial to parallel register. This shift
register is also operating at 64KHz clock at which parallel to serial shift register is operating at
PCM modulator (these both the clock signals should be in synchronized with each other in order
to get proper decoded output). So the output of the serial to parallel register is a 8 bit code. This 8
bit code is applied to 8 bit D/A converter. Output of the D/A converter will be a staircase
signaling between 0 and +5V. This stair case signal is applied a low pass filter. This low pass
will smoothen the staircase signal so that we will get a recovered AF signal. We can use a
voltage amplifier at the output of the low pass filter to amplify the recovered AF signal to desired
voltage level.
EXPECTED WAVE FORMS:
WITH DC INPUT:

RESULT:

Thus the Pulse Code modulation and demodulation were performed .

 EXPERIMENT NO: 02
DPCM MODULATION & DETECTION

AIM:
To analyze a DPCM system and to interpret the modulated and demodulated waveforms for a
sampling frequency of 8 KHz.
APPRATUS:
1. DPCM Modulation and Demodulation Trainer Kit
2. Dual Trace oscilloscope
3. Digital Multimeter
4. C.R.O (30MHz)
5. Patch chords.
THEORY

THEORY:
Differential PCM is quite similar to ordinary PCM. However, each word in this system indicates
the difference in amplitude, positive or negative, between this sample and the previous sample.
Thus the relative value of each sample is indicated rather than, the absolute value as in normal
PCM. This unique system consists of
I. DPCM Modulator
1. Regulated power supply
2. Audio Frequency signal generator
3. Prediction Filter
4. Sample & Hold circuit
5. A/D Converter
6. Parallel –Serial Shift register
7. Clock generator / Timing circuit
8. DC source
II. DPCM Demodulator
1. Regulated Power Supply
2. Serial-Parallel Shift registers.
3. D/A converter.
4. Clock generator
5. Timing circuit
6. Prediction filter
7. Passive low pass filter
PROCEDURE:
1. Study the theory of operation thoroughly.
2. Connect the trainer (Modulator) to the mains and switch on the power supply.
3. Observe the output of the AF generator using CRO, it should be Sine wave of 400 Hz
frequency with 3V pp amplitude.
4. Verify the output of the DC source with multi-meter/scope; output should vary 0 to +290mV.
5. Observe the output of the Clock generator using CRO, they should be 64 KHz and 8 KHz
frequency of square with 5 Vpp amplitude.
6. Connect the trainer (De Modulator) to the mains and switch on the power supply.
7. Observe the output of the Clock generator using CRO; it should be 64 KHz square wave with
amplitude of 5 pp.
DPCM Operation (with DC input):
Modulation:
8. Keep CRO in dual mode. Connect one channel to 8 KHz signal (one which is connected to the
Shift register) and another channel to the DPCM output.
9. Observe the DPCM output with respect to the 8 KHz signal and sketch the waveform.
10. Note: Form this waveform you can observe that the LSB bit enters the output first.
11. Set DC source to some value say 1 V with the help of multi-meter and connect it to the A/D
converter input and observe the output LED’s.
12. Note down the digital code i.e. output of the A/D converter and compare with the theoretical
value Theoretical value can be obtained by:
 𝐴
𝐷𝑖𝑛𝑝𝑢𝑡 𝑣𝑜𝑙𝑡𝑎𝑔𝑒
=X(10) =Y(2)
1 𝐿𝑆𝐵 𝑉𝑎𝑙𝑢𝑒

1 LSB value = Vref / 2n

Since Vref = 290mV and n=
4 1 LSB Value = 18.125mV

Demodulation
1. Connect DPCM signal to the demodulator (S-P register) from the DPCM modulator with the
help of coaxial cable (supplied with the trainer).
2. Connect clock signal (64 KHz) from the transmitter to the receiver using coaxial cable.
3. Connect transmitter clock to the timing circuit.
4. Observe and note down the S-P shift register output data and compare it with the transmitted
data (i.e. output A/D converter at transmitter) notice that the output of the S-P shift register is
following the A/D converter output in the modulator.
5. Observe D/A converter output (demodulated output) using multi-meter/scope and compare it
with the original signal and can observe that there is no loss in information in process of
conversion and transmission.
DPCM Operation (with AC input):
Modulation:
6. Connect AC signal of 3VPP amplitude to positive terminal of the summer circuit.
Note: The output of the prediction filter is connected to the negative terminal of the summer
circuit and can observe the waveforms at the test points provided on the board.
7. The output of the summer is internally connected to the sample and hold circuit
8. Keep CRO in dual mode. Connect one channel to the AF signal and another channel to the
Sample and Hold output. Observe and sketch the sample & hold output
9. Connect the Sample and Hold output to the A/D converter and observe the DPCM output
using oscilloscope.
10. Observe DPCM output by varying AF signal voltage.
.

EXPECTED WAVEFORMS:
Draw the wave forms for the given DC input, corresponding binary data wave form, and for AC
input draw sample and hold waveform then D/A converter o/p and then reconstructed AC signal
 RESULT:
Thus the Differential Pulse code modulation and demodulation were performed.

EXPERIMENT NO: 03
DELTA MODULATION AND DEMODULATION

AIM:
To analyze a Delta modulation system. and interpret the modulated and demodulated waveforms
APPARATUS:
1. PCM Modulator trainer- AET-73M
2. PCM Demodulator trainer-AET-73D
3. C.R.O (30MHz)
4. Patch chords.

THEORY
DELTA MODULATOR & DEMODULATOR
 INTRODUCTION
Delta Modulation is a form of pulse modulation where a sample value is represented as a single
bit. This is almost similar to differential PCM, as the transmitted bit is only one per sample just
to indicate whether the present sample is larger or smaller than the previous one. The encoding,
decoding and quantizing process become extremely simple but this system cannot handle rapidly
varying samples. This increases the quantizing noise.
The trainer is a self sustained and well organized kit for the demonstration of delta modulation &
demodulation .

PROCEDURE:
DM Modulator:
1. Study the theory of operation
2. Connect the trainer (AET-73M) -
3. Observe the output of AF generator using CRO; it should be a Sine wave of 100 Hz frequency
with 3Vpp amplitude.
4. Verify the output of the DC source with multimeter/scope; output should vary 0 to +4V
5. Observe the output of the clock generator using Crotchety should be 4 KHz frequency of
square wave with 5 Up amplitude.
Note: This clock signal is internally connected to the up/down counter so no external connection
is required.

DM With DC Voltage as modulating signal:

6. Connect DC signal from the DC source to the inverting input of the comparator and set some
voltage says 3V.
7. Observe and plot the signals at D/A converter output (i.e. non-inverting input of the
comparator), DM signal using CRO and compare them with the waveforms given in figure.
8. Connect DM signal (from 73M) to the DM input of the demodulator.
9. Connect clock (4KHz) from modulator (73M) to the clock input of the demodulator (73D).
Connect clock input of UP/DOWN counter (in 73D) to the clock from transmitter with the help
of springs provided.
10. Observe digital output (LED indication) of the UP/DOWN counter (in 73 D) and compare it
with the output of the UP/DOWN (in 73M) .By this you can notice that the both the outputs are
same.
11. Observe and plot the output of the D/A converter and compare it with the waveforms given
in figure.
12. Measure the demodulated signal (i.e. output of the D/A converter 73D with the help of
multimeter and compare it with the original signal 73 M. From the above observation you can
notice that both the voltages are equal and there is no loss in process of modulation, transmission
and demodulation.
13. Similarly you can verify the DM operation for different values of modulating signal.

EXPECTED WAVE FORMS: FOR AC INPUT

RESULT:
Thus the Delta modulation and demodulation were performed and graphs were
plotted.

EXPERIMENT No. : 05

TIME DIVISION MULTIPLEXING SYSTEM

AIM: Study of Time Division Multiplexing System.

APPARATUS USED: 1. TDM Trainer Kit

2. C.R.O
3. Connecting leads
THEORY:
An important feature of pulse-amplitude modulation is a conservation of time. That is, for
a given message signal, transmission of the associated PAM wave engages the communication
channel for only a fraction of the sampling interval on a periodic basis. Hence, some of the time
interval between adjacent pulses of the PAM wave is cleared for use by the other independent
message signals on a time-shared basis. By so doing, we obtain a time-division multiplex system
(TDM), which enables the joint utilization of a common channel by a plurality of independent
message signals without mutual interference. Each input message signal is first restricted in
bandwidth by a low-pass pre-alias filter to remove the frequencies that are nonessential to an
adequate signal representation.

BLOCK DIAGRAM:

PROCEDURE:
MULTIPLEXER:
1. Observe the AF generator-1 output and note down the amplifier and frequency.
2. Observe the AF generator-2 output and note down the amplitude and frequency.

3. Observe the AF generator-2 output and note down the amplitude and frequency.

4. Connect the AF generator 1, 2and 3 outputs to CH1, CH2 & CH3 of TDM multiplexer.

5. Observe and connect the clock generator output to the control input of the TDM multiplexer
(it acts like selection line for MUX).

6. Observe the TDM output in storage oscilloscope.

DEMULTIPLEXER:
6. Using coaxial cable connect the TDM de-multiplexer.

7. Connect the clock generator output in de-multiplexer trainer to the control input of the TDM de-
multiplexer.

8. Observe the de-multiplexed signals at CH1,CH2 and CH3.

9. Connected the CH1, CH2 and CH3outputs to low pass filter and amplifier and note down
the outputs.
WAVEFORMS:
RESULT: Time Division Multiplexing System signal has been verified & observed
successfully.

EXPERIMENT NO: 06

FSK- GENERATION AND DETECTION

AIM:
To analyze a FSK modulation system. And interpret the modulated and demodulated waveforms

APPRATUS:
1. FSK Trainer Kit - AET-48
2. Dual Trace oscilloscope
3. Digital Multimeter
4. C.R.O (30MHz)
5. Patch chords.

BLOCK DIAGRAM:

THEORY:
In Frequency shift keying, the carrier frequency is shifted (i.e. from one frequency to another)
corresponding to the digital modulating signal. If the higher frequency is used to represent a data
‘1’ & lower frequency a data ‘0’, the resulting FSK waveform appears.
Thus
Data =1 High Frequency
Data =0 Low Frequency

It is also represented as a sum of two ASK signals. The two carriers have different frequencies &
the digital data is inverted. The demodulation of FSK can be carried out by a PLL. As known,

the PLL tries to ‘lock’ the input frequency. It achieves this by generating corresponding O/P
voltage to be fed to the VCO, if any frequency deviation at its I/P is encountered. Thus the PLL
detector follows the frequency changes and generates proportional O/P voltage. The O/P voltage
from PLL contains the carrier components. Therefore to remove this, the signal is passed through
Low Pass Filter. The resulting wave is too rounded to be used for digital data processing. Also,
the amplitude level may be very low due to channel attenuation.
FSK Modulator
The FSK modulator using IC XR 2206. IC XR 2206 is a VCO based monolithic function
generator capable of producing Sine, Square, Triangle signals with AM and FM facility. In this
trainer XR2206 is used generate FSK signal. Mark (Logic 1) and space (logic 0) frequencies can
be independently adjusted by the choice of timing potentiometers FO & Fl. The output is phase
continuous during transitions. The keying signals i.e. data signal is applied to pin 9.
FSK Demodulator:
FSK demodulator in a combination of PLL (LM565) and comparator (Op-amp). The frequency-
changing signal at the input to the PLL drives the phase detector to result in rapid change in the
error voltage, which is applied to the input of the comparator. At the space frequency, the error
voltage out of the phase detector is below the comparison voltage of the comparator. The
comparator is a non-inverting circuit, so its output level is also low. As the phase detector input
frequency shifts low (to the mark frequency), the error voltage steps to a high level, passing
through the comparison level, causing the comparator output voltage to go high. This error
voltage change will snap the comparator output voltage between its two output levels in manner
that duplicates the data signal input to the XR22OS modulator. The free running frequency of the
PLL (no input signal) is set midway between the mark and space frequencies. A space at 2025
Hz and mark at 2225 Hz will have a free running VCO frequency of 2125 Hz.
EXPECTED WAVE FORMS:
RESULT:
Thus the FSK modulation and demodulation were performed and required graphs were plotted.

EXPERIMENT NO: 07
PHASE SHIFT KEYING GENERATION & DETECTION

AIM:
To analyze a PSK modulation system. And interpret the modulated and demodulated waveforms.
APPRATUS:
1. BPSK Trainer Kit - AET-48
2. Dual Trace oscilloscope
3. Digital Multimeter
4. C.R.O (30MHz)
5. Patch chords.
BLOCK DIAGRAM:

PSK Modulator PSK

Demodulator

Theory:
Phase shift keying is a modulation/data transmitting technique in which phase of the carrier
signal is shifted between two distinct levels. In a simple PSK(ie binary PSK) unshifted carrier
Vcosω0t is transmitted to indicate a 1 condition, and the carrier shifted by 1800 ie – Vcosω0t is
transmitted to indicate as 0 condition.
PSK Modulator
Figure 6.2shows the PSK modulator. IC CD 4052 is a 4 channel analog multiplexer and is used
as an active component in this circuit. One of the control signals of 4052 is grounded so that
4052 will act as a two channel multiplexer and other control is being connected to the binary
signal ie data to be transmitted. Unshifted carrier signal is connected directly to CH1 and carrier
shifted by 1800 is connected to CH2.phase shift network is a unity gain inverting amplifier using
OP-amp (TL084).
When input data signal is 1 i.e. control signal is at high voltage, output of the 4052 is connected
to CH1 and unshifted (or 0 phase) carrier is passed on to output. Similarly When data signal is 0
i.e. control signal is at zero voltage output of 4052 is connected to CH2 and carrier shifted by
1800 is passed on to output.
PSK Demodulator:
Demodulation of PSK is achieved by subtracting the received carrier from a derived synchronous
reference carrier of constant phase. Figure shows the simple coherent(synchronous) PSK
modulator. Received PSK signal is converted to square wave using an op-amp(TL084) based
zero crossing detector and connected to EX-OR circuit. The derived reference carrier is
connected to other input of the EX-OR Gate through an op-amp based zero crossing detector. For
the simplicity same carrier is used at receiver as reference carrier (In practical communication
system reference carrier is generated at receiver).We can observe the exact operation of
demodulator with the help of waveforms at various nodes in the circuit. Received PSK signal is
converted to square wave using an op-amp(TL084) based zero crossing detector and connected
to EX-OR circuit. The derived reference carrier is connected to other input of the EX-OR Gate
through an op-amp based zero crossing
detector. For the simplicity same carrier is used at receiver as reference carrier (In practical
communication system reference carrier is generated at receiver).We can observe the exact
operation of demodulator with the help of waveforms at various nodes in the circuit.

PROCEDURE:
6.6 PROCEDURE
1. Connect the trainer to mains and switch on the power supply.
2. Measure the output of the regulated power supply ie +5V and -5V with the help of digital
multimeter.
3. Observe the output of the carrier generator using CRO, it should be an 8KHZ sine with 5Vpp
amplitude.
4. Observe the various data signals(1KHZ,2KHZ and 4KHZ0 using CRO
6.6.1 Modulation:
5. Connect carrier signal to carrier input of the PSK modulator.
6. Connect data signal say 4KHZ from data source to data input of the modulator.
7. Keep CRO in dual mode and connect CH1 input of the CRO to data signal and CH2 to the
output of the PSK modulator.
8. Observe the PSK output signal with respect to data signal and plot the waveforms.
6.6.2 Demodulation:
9. Connect the PSK output to the PSK input of the demodulator.
10. Connect carrier to the carrier input of the PSK demodulator.
11. Keep CRO in dual mode and connect CH1 to data signal(at modulator) and CH2 to the
output of the demodulator.
12. Compare the demodulated signal with the original signal. By this we can notice that there is
no loss in modulation and demodulation process
13. Repeat the steps 6 to 12 with different data signals ie 2KHZ and 1KHZ

EXPECTED GRAPHS:
RESULT:
Thus the PSK modulation and demodulation were performed .

EXPERIMENT NO-08

ASK MODULATION AND DEMODULATION

AIM: To study the process of ASK modulation& demodulation and study various data
formatting modulation and demodulation techniques.

APPRATUS: 1. ASK MODULATION &DEMODULATION Trainer.

2. CRO 30MHz Dual Channel.

3. Patch Chords.

THEORY:-

Modulation also allows different data streams to be transmitted over the same channel.
This process is called as ‘Multiplexing’ & result in a considerable saving in bandwidth no of
channels to be used. Also it increases the channel efficiency. The variation of particular
parameter variation of the carrier wave gives rise to various modulation techniques. Some of the
basic modulation techniques are described as under. ASK:- In this modulation involves the
variation of the amplitude of the carrier waves in accordance with the data stream. The simplest
method of modulating a carrier with a data stream is to change the amplitude of the carrier wave
every time the data changes. This modulation technique is known as amplitude shift keying. The
simplest way of achieving amplitude shift keying is ‘ON’ the carrier whenever the data bit is
‘HIGH’ & switching ‘OFF’ when the data bit is low i.e. the transmitter outputs the carrier for
HIGH & totally suppresses the carrier for low. This technique is known as ON-OFF keying Fig.
illustrates the amplitude shift keying for the given data stream. Thus, DATA = HIGH CARRIER
TRANSMITTED DATA = LOW CARRIER SUPPRESSED The ASK waveform is generated
by a balanced modulator circuit, also known as a linear multiplier, As the name suggests, the
device multiplies the instantaneous signal at its two inputs, the output voltage being product of
the two input voltages at any instance of time. One of the inputs is a/c coupled ‘carrier’ wave of
high frequency. Generally the carrier wave is a sine wave since any other waveform would
increase the bandwidth imparting any advantages requirement without improving or to it. The
other i/p which is the information signal to be transmitted, is D.C. coupled. It is known as
modulating signal

In order to generate ASK waveform it is necessary to apply a sine wave at carrier input &
the digital stream at modulation input. The double balanced modulator is shown in fig.
BLOCK DIAGRAMS:

AF SIGNAL
ASK MODULATOR ASK DEMODULATOR

DATA/CLOCK GENERATOR

The data stream applied is uniploar i.e. 0Volt at logic LOW & +4.5Volts at logic HIGH. The
output of balanced modulator is a sine wave, unchanged in phase when a data bit ‘HIGH’ is
applied to it. In this case the carrier is multiplied with a positive constant voltage when the data
bit LOW is applied, the carrier is multiplied by 0 Volts, giving rise to 0Volt signal at modulator’s
o/p. The ASK modulation results in a great simplicity at the receiver. The method to demodulate
the ASK waveform is to rectify it, pass it through the filter &’square up’ the resulting waveform.
The o/p is the original digital data stream. Fig. shows the functional blocks required in order to
demodulate the ASK waveform at receiver

PROCEDURE:
Modulation:-

1. Connect the sine wave 500 KHz from the carrier generator TP1 to the carrier input of the
modulator TP7.

2. And also connect data clock D1 i.e., modulation signal TP3 to the modulation input TP8. 3.
Switch ON the power supply.

4. Observe the output at TP9.

5. By varying the gain pot P3 observe the ASK output at TP10.

6. Adjusting the carrier offset and modulation offset we can observe the ASK output.

7. By changing the carrier signal 1MHz and different data clocks D2, D3, D4 observe the
output.
Demodulation:-

1. Connect ASK output TP10 to the rectifier input TP12 and observe the waveform.

2. Now connect rectifier output TP13 to the low pass filter input TP14 and observe the output at
TP15.

3. CONNECT LPF output TP15 to the data squaring circuit input TP16 and observes the
demodulation output waveform at TP17.

4. By changing the different data clocks and observe the demodulation output.

EXPECTED WAVEFORMS:
RESULT: Thus the ASK modulation and demodulation were performed .
 EXPERIMENT NO: 09
DPSK GENERATION & DETECTION

AIM: Study the characteristics of differential phase shift keying

APPRATUS:
1. DPSK Trainer Kit
2. Dual Trace oscilloscope
3. Digital Multimeter
4. C.R.O (30MHz)
5. Patch chords.

BLOCK DIAGRAM:
 THEORY:
DPSK: Phase Shift Keying requires a local oscillator at the receiver which is accurately
synchronized in phase with the un-modulated transmitted carrier, and in practice this can be
difficult to achieve. Differential Phase Shift Keying (DPSK) over comes the difficult by
combining two basic operations at the transmitter (1) differential encoding of the input binary
wave and (2) phase shift keying – hence the name differential phase shift keying. In other words
DPSK is a non-coherent version of the PSK.
The differential encoding operation performed by the modulator is explained below Let b (t) be the
binary message to be transmitted. An encoded message stream b(t) is generated from b’(t) by using a
logic circuit The first bit in b(t) is arbitrary which may be chosen as 1 or 0 . The subsequent bits in
b(t) are determined on the basis of the rule that when b’(t) is 1 b(t)does not change its value. In the
first bit stream, the initial bit (arbitrary) is 1 and in the second bit stream, the initial bit is 0 EX-NOR
gate can be used to perform this operation as its output is a 1 when both the input are same, and a 0
when the inputs are different.

b’(t) 0 1 1 0 0
b(t) 1 0 0 0 1 0
Phase 00 1800 1800 1800 00 1800

B(t) 0 1 1 1 0 1
Phase 180 0
0 0
00 00 1800 00
EXPECTED WAVEFORMS:

RESULT:
Thus the DPSK modulation and demodulation were performed .
 EXPERIMENT NO: 10
QPSK GENERATION & DETECTION

AIM: To study modulation and demodulation of QPSK and sketch the relevant waveforms.

APPRATUS:
1. QPSK Trainer Kit
2. Dual Trace oscilloscope
3. Digital Multimeter
4. C.R.O (30MHz)
5. Patch chords.

BLOCK DIAGRAM: QPSK MODULATOR & DEMODULATOR

THEORY:

Quadrature Phase Shift Keying

Phase of the carrier takes on one of four equally spaced values such as π/4, 3π/4, 5π/4,7π/4.
Si(t) = √2E/ Tb cos {2 πƒct + (2i – 1) π/4} , 0≤ t ≤ Tb
0, , elsewhere
Where i = 1,2,3,4, & E= Tx signal energy per symbol
Tb = symbol duration
PROCEDURE:

1. Connect and switch on the power supply.

2. QPSK is selected by default and LEDs of corresponding technique will glow.
3. Select the bit pattern using push button i.e. 8 bit or 16 bit or 32 bit or 64 bit. Observe bit
pattern on TP-2.
4. Select data rate using push button i.e. 2 KHz or 4 KHz or 8 KHz 16 KHz.

Modulation:
5. Observe the input bit pattern at TP-2 by varying bit pattern using respective push button.
6. Observe the data rate at TP-1 by varying data rate using respective push button.
7. Observe the Two- bit encoding i.e. I-Channel (TP-3) and Q-Channel (TP-4).
8. Observe carrier signal i.e. cosine wave (TP-5) and sine wave (TP-6). Frequency of carrier
signal will change with respect to data rate.
9. Observe I-Channel (TP-7) and Q-Channel (TP-8) modulated signal.
10. Observe QPSK modulated signal at TP-9.

Demodulation:
11. Apply the QPSK modulated output to the demodulator input.
12. Observe the multiplied signal of QPSK and carrier signal, cosine at TP-12 and also observe
the multiplied signal of QPSK and carrier signal, sine at TP-13.
13. Observe the integrated output at I-channel (TP-14) and Q-channel (TP-15).

Input Bits Phase of Co –ordinates of message signal

QPSK signal S1 S2
10 π/4 √𝑬/𝟐 −√𝑬/𝟐
00 3π/4 −√𝑬/𝟐 −√𝑬/𝟐
01 5π/4 −√𝑬/𝟐 +√𝑬/𝟐
11 7π/4 +√𝑬/𝟐 +√𝑬/𝟐
EXPECTED WAVE FORMS:

RESULT: QPSK modulation and demodulation wave forms are observed.