CHAPTER 3

A CLOSED-LOOP CAPACITANCE-TO-FREQUENCY
CONVERTER FOR SINGLE-ELEMENT AND
DIFFERENTIAL CAPACITIVE SENSORS

3.1 INTRODUCTION

In chapter-2, an interference-insensitive switched-capacitor capacitance-to-digital

converter (SC-CDC) is presented. Such a CDC is very useful in capacitive sensing

applications that use unshielded or partially-shielded electrodes. However, the

SC-CDC, that provides an interference-insensitive digital output, is compatible with

only single-element capacitive sensors, and not differential capacitive sensors (DCS)

which constitute another important category of capacitive sensors. DCS is used in a

range of applications such as touch sensing [68], and determining position [69],

displacement [70], acceleration [71], differential pressure [9], and permittivity

distribution in the area of interest [72]. It consists of two sensing capacitances, say, 𝐶1

and 𝐶2 , with a common electrode. 𝐶1 and 𝐶2 vary with the parameter being sensed.

𝐶1 = 𝐶2 = 𝐶0 when the measurand is zero. The change in 𝐶1 due to the measurand is

opposite to that in 𝐶2 , causing these sensors to be popularly known as push-pull type

capacitive sensors. The change in capacitance with respect to the measurand, x, can be

linear or non-linear (inverse) as given in (1.2) and (1.3), respectively, where 𝑘 is the

sensor constant, and 𝐶0 is the nominal capacitance of the sensor [23]. The characteristic

is linear, as in (1.2), in the case of the widely used parallel-plate arrangement of the

electrodes which utilize the change in the area of overlap between the plates, or change

in the dielectric constant, with respect to the measurand. It has an inverse characteristic,

as in (1.3), if the change in capacitance is caused by the change in the distance between

the plates. Similarly, the linear single-element sensors can be represented as 𝐶1 in (1. 2)

while the inverse ones can be represented using 𝐶2 given in (1.3).

The general approaches for output digitization in single-element capacitive sensors

begin with the conversion of capacitance to an equivalent voltage signal [73], [74]. This

signal is then given to an analog-to-digital converter. Other approaches include

obtaining number of transitions [38], frequency [75] - [77] or time period [62] as a

function of the capacitance, following which a corresponding digital value is derived.

Similar approaches are employed to get a digital output from differential capacitive

sensors. For instance, [36] is a commercially available - based converter for

capacitive sensors. This does not provide ratio-metric output directly. Also, it has

limited ranges for the sensor and acceptable magnitude of parasitic capacitance. The

circuit in [33] uses capacitance-to-pulse-width conversion. Its output is parasitic-

insensitive but requires two capacitance-to-voltage converters, followed by a voltage-

to-pulse-width converter, and operates in an open-loop configuration. In [78], a

switched-capacitor-based dual-slope capacitance-to-digital converter (CDC) is

presented, but the update rate is relatively low. A low power CDC using successive

approximation register (SAR)-based conversion is reported in [34]. A ratio-metric

output [78] is preferred for DCS instead of a difference output [34]. A synchronous

demodulator-based scheme is presented in [79]. It needs ac excitation, and provides an

analog output. In [80] a switch-bridge-based circuit is presented for the DCS. This

design avoids the limitations of its diode counterpart, but requires an ac source and the

output voltage is not ratio-metric.

The measurement circuits given in [64], [75], and [81] adopt a closed-loop approach.

The circuit in [75] is a closed-loop SC-CFC for a single-element capacitive sensor.

Though it exhibits a high update rate, it is not suitable for interfacing differential

capacitive sensors. The schemes proposed in [64] and [81] deal with differential

capacitive sensors. They are auto-balanced bridge circuits which require a precise
49
sinusoidal AC excitation and have a complex design involving a synchronous

demodulator. They use two multipliers in its feedback path, one of which is used to

realize a voltage-controlled resistor (VCR). The worst-case error of the analog

multiplier employed is typically high, e.g. 2% in the case of AD633, used in [64], [81].

Thus, the use of such components in the design limits its linearity and accuracy. In

addition, this circuit provides an analog output (while digital is preferred) which is

sensitive to parasitic capacitances.

The proffered measurement scheme, for single-element and differential capacitive

sensors, is a closed-loop switched-capacitor capacitance-to-frequency converter (SC-

CFC) circuit. It uses dc excitation, and achieves high accuracy and a relatively high

update rate. In the case of differential capacitive sensors, the ratio-metric output from

the scheme ensures a linear characteristic irrespective of the sensor characteristic being

linear or inverse. Moreover, the final output does not depend on the nominal

capacitance value of the sensor, enabling easy interfacing of the sensor to the

measurement circuit. The same SC-CFC is suitable for single-element capacitive

sensors, possessing either linear or inverse characteristic, and gives a linear ratio output

directly, independent of the nominal capacitance. The proposed CFC is simple and

relatively inexpensive to realize. Since a switched-capacitor approach has been

employed in its implementation, this circuit is suitable for IC fabrication. The design

and operation of this new closed-loop SC-CFC and its evaluation based on a hardware

prototype are presented in the subsequent sections.

3.2 CAPACITANCE-TO-FREQUENCY CONVERTER

The circuit of the proposed SC-CFC is shown in Fig. 3.1. The scheme is presented first

for differential capacitive sensor, followed by single-element capacitive sensor.

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3.2.1 Differential Capacitive Sensor

The variable capacitors 𝐶1 and 𝐶2 represent the differential capacitive sensor. 𝑉𝑅 is a dc

reference voltage, and it is connected to the single-pole double-throw (SPDT) switches

S1 and S2. When clock φsw is high, the output of S1 is at +𝑉𝑅 and that of S2 is at −𝑉𝑅 .

The outputs of these SPDT switches will be flipped when φsw is low. The switch S3

controlled by the clock signal φ1, the operational amplifier OA1, and capacitors 𝐶𝑎 , 𝐶𝐹1

constitute an SC integrator. φ1 is a fixed clock whose frequency 𝑓1 is much higher than

the frequency 𝑓𝑠𝑤 of φsw. When φsw is high, for every clock cycle of φ1 the voltage 𝑣𝑜𝑖1

decreases by 𝑉𝑅 𝐶𝑎 ⁄𝐶𝐹1 . On the other hand, when φsw is low, 𝑣𝑜𝑖1 increases by the same

amount for each clock cycle of φ1. This process synthesizes a triangular voltage 𝑣𝑜𝑖1 as

input to the capacitor 𝐶1 . This is illustrated in Fig. 3.2. Similarly, switch S4, capacitors

𝐶𝑏 , 𝐶𝐹2 , and opamp OA2 forms another SC integrator with output 𝑣𝑜𝑖2 . The polarity of

the slope of the triangular wave 𝑣𝑜𝑖2 will be opposite to that of 𝑣𝑜𝑖1 as, at any instant of

time, the outputs of S1 and S2 have opposing signs. S4 is operated using φ2, which is the

output of the voltage-to-frequency converter (VFC). φ2, with a frequency 𝑓2

corresponding to the voltage fed into the VFC, is used together with switched-capacitor

integrator to realize the auto-balancing mechanism which forms the core of the

proposed closed-loop circuit.

The currents 𝐼1 and 𝐼2 , indicated in Fig. 3.1, combine at node 𝑐, and the resultant current

𝐼3 flows into the SPDT switch S5. S5 is controlled by φsw, which is the same signal that

controls S1 and S2. In the absence of S5, the output 𝑣𝑜𝑖3 of the integrator, consisting of

feedback capacitor 𝐶𝐹3 , and opamp OA3, would always tend to zero since 𝐼3 is a bipolar

signal when 𝐶1  𝐶2 , before the circuit reaches steady state, as shown in Fig. 3.2(b). The

presence of S5 ensures that the current 𝐼CF3 through 𝐶𝐹3 is unidirectional (refer

51
Fig. 3.2(b)), and hence 𝑣𝑜𝑖3 monotonously accumulates, and achieves auto-balancing

at a different voltage for each set of values of 𝐶1 and 𝐶2 .

Let 𝐶𝐹1 = 𝐶𝐹2 = 𝐶𝐹 , and 𝐶𝑎 = 𝐶𝑏 = 𝐶. In this case, the slopes of 𝑣𝑜𝑖1 and 𝑣𝑜𝑖2 , namely

𝜕𝑣𝑜𝑖1 𝜕𝑣𝑜𝑖2
and , have the same magnitude but opposite polarity, as shown in Fig. 3.2.
𝜕𝑡 𝜕𝑡

When φsw is high the slope of 𝑣𝑜𝑖1 is negative, whereas that of 𝑣𝑜𝑖2 is positive. Thus,

𝐼1 , 𝐼2 and 𝐼3 can be expressed by (3.1), (3.2) and (3.3), respectively. If 𝐶1 = 𝐶2 , 𝐼1 and

𝐼2 will be of equal magnitude and opposite polarity. Thus, 𝐼3 and 𝐼CF3 (= 𝐼3 /2) are zero,

producing an output 𝑣𝑜𝑖3 = 0. The expression for 𝑣𝑜𝑖3 is given in (3.4). The VFC is

configured such that when 𝑣𝑜𝑖3 is zero, the frequency output, 𝑓2 will be the same as the

fixed frequency 𝑓1 .

𝜕𝑣𝑜𝑖1 𝑉𝑅 𝐶
𝐼1 = −𝐶1 = −𝐶1 𝑓1 (3.1)
𝜕𝑡 𝐶𝐹

𝜕𝑣𝑜𝑖2 𝑉𝑅 𝐶
𝐼2 = 𝐶2 = 𝐶2 𝑓2 (3.2)
𝜕𝑡 𝐶𝐹

𝑉𝑅 𝐶
𝐼3 = 𝐼1 + 𝐼2 = [ 𝐶2 𝑓2 − 𝐶1 𝑓1 ] (3.3)
𝐶𝐹

1 𝑉 𝐶
𝑣𝑜𝑖3 = − 𝐶 ∫ 𝐼CF3 𝑑𝑡 = [𝐶1 𝑓1 − 𝐶2 𝑓2 ] 2𝐶 𝑅𝐶 t (3.4)
𝐹3 𝐹 𝐹3

Now, when 𝑓1 = 𝑓2 , let 𝐶1 and 𝐶2 be changed such that 𝐶1  𝐶2 . Then, 𝐶1 𝑓1  𝐶2 𝑓2 .

This causes a non-zero 𝐼3 (actually, 𝐼3 < 0 since 𝐼1 is a negative quantity) to flow

through 𝐶𝐹3 increasing 𝑣𝑜𝑖3 as per (3.4). Thus, the VFC delivers an increased output

𝜕𝑣𝑜𝑖2
frequency 𝑓2 , leading to an increase in , as shown in Fig. 3.2.
𝜕𝑡

52
53
Fig. 3.1 Functional block diagram of the proposed SC-CFC. In the circuit, 𝐶𝐹1 = 𝐶𝐹2 = 𝐶𝐹 and 𝐶𝑎 = 𝐶𝑏 = 𝐶. VFC represents a
voltage-to-frequency converter, and CLU is a control and logic unit.
54
Fig. 3. 2 (a) Important waveforms of the proposed CFC for different conditions of 𝐶1 and 𝐶2 . φ1 and φ2 are at a much higher
frequency compared to φsw. 𝑣𝑜𝑖1 and 𝑣𝑜𝑖2 increment and decrement, in steps, as they are outputs of SC integrators.
The individual steps become less visible as they get smaller. (b) Pictorial representation of the waveforms of the
currents for 𝐶1 > 𝐶2 , before reaching the steady state of the circuit. The currents, once the circuit is in steady state,
are given in (c). ICF3 is not shown in (c) as it is zero.
 𝜕𝑣𝑜𝑖1 𝜕𝑣𝑜𝑖2
As 𝑓1 , and hence , remain constant, the increase in reduces |𝐼3 |. This goes on
𝜕𝑡 𝜕𝑡

until |𝐼1 |= |𝐼2 | following which 𝑣𝑜𝑖3 ceases to vary. In this condition, (3.5) can be

obtained from (3.4).

𝐶1 𝑓1 = 𝐶2 𝑓2 (3.5)

or 𝐶1/ 𝐶2 = 𝑓2 / 𝑓1 (3.6)

If instead 𝐶1 < 𝐶2 , when 𝑓1 = 𝑓2 , then |𝐼1 | < |𝐼2 |, and 𝑣𝑜𝑖3 decreases until 𝑓2 is

𝜕𝑣𝑜𝑖2
sufficiently decreased such that |𝐼1 | = |𝐼2 |. The decrease in due to the decreased
𝜕𝑡

𝑓2 is also shown in Fig. 3.2.

The ratio of the capacitances 𝐶1 and 𝐶2 can be estimated using (3.6). However, if a

ratio-metric computation of 𝑓1 and 𝑓2 , as in (3.7), is performed, the ratio-metric output

due to 𝐶1 and 𝐶2 is obtained. In (3.7), the output follows a linear relation with the

measurand 𝑥, where 𝑘 is the sensor constant. Thus, the measurand can be linearly

estimated for sensors possessing either linear or inverse characteristic. Polarity of 𝑥 is

taken as positive if 𝑓1  𝑓2 , and negative for 𝑓1  𝑓2 .

(𝑓2 − 𝑓1 ) (𝐶 − 𝐶 )
= (𝐶1+ 𝐶2) = ±𝑘𝑥 (3.7)
(𝑓2 + 𝑓1 ) 1 2

3.2.2 Single-Element Capacitive Sensor

To interface a single-element capacitive sensor, either 𝐶1 or 𝐶2 (refer to Fig. 3.1) is set

as the sensor capacitance, keeping the other as the reference capacitor. If the sensor 𝐶𝑥

possesses a linear characteristic as 𝐶𝑥 = 𝐶0 (1 ± 𝑘𝑥), it is connected in place of 𝐶1 .

Then, 𝐶2 is set as 𝐶0 . In this case, from (3.6), (3.8) is obtained.

(𝑓2 − 𝑓1 ) 𝐶0 (1± 𝑘𝑥)

= − 1 = ±𝑘𝑥 (3.8)
𝑓1 𝐶0

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To interface single-element sensor 𝐶𝑥 that follows inverse characteristic, i.e.,

𝐶𝑥 = 𝐶0 /(1 ± 𝑘𝑥), it should be connected in place of 𝐶2 and 𝐶1 set as 𝐶0 in Fig. 3.1. In

such case, a linear final output is obtained, i.e., (3.8) holds true for both types of single-

element sensors.

3.2.3 Measurement of 𝒇𝟐

Since 𝑓1 is known and 𝑓2 can be measured using a frequency counter, the output

estimated using (3.7) or (3.8) is available in digital domain. The frequency counter is

part of the Control and Logic Unit (CLU) in Fig. 3.1. To measure 𝑓2 , it counts the

number pulses 𝑛𝑡 of φ2 within a gate time 𝑇𝐺 . The counter is set such that its output

increments by one for every cycle of φ2. Then, 𝑓2 is computed as 𝑓2 = (𝑛𝑡 /𝑇𝐺 ). For an

update rate higher than the one achieved using the frequency counter, the measurement

unit could be modified to measure the time period T2 of φ2. Then 𝑓1 can be replaced by

1⁄𝑇1, where 𝑇1 is the time period of φ1, and 𝑓2 by 1⁄𝑇2 in (3.7) or (3.8), to obtain the

ratio-metric or ratio outputs in terms of the respective time periods. However, due to

limitations in the highest achievable frequency of the reference clock signal of the CLU,

this approach has lower resolution and SNR than the frequency counter method. To

improve these parameters the time-domain values can be averaged, for a given window

size. Thus, the choice of output in the time-domain or frequency counter methods is

essentially based on a tradeoff between update rate and resolution. In the prototype

developed, the frequency counter has been used to perform the measurement.

3.2.4 Effect of Mismatch and a Correction Method

In the derivation of (3.6), it is assumed that 𝐶𝐹1 = 𝐶𝐹2 = 𝐶𝐹 , and 𝐶𝑎 = 𝐶𝑏 = 𝐶. However,

in practice there can be mismatch in the values of these components, which can impact

the final output as explained below. Let,

56
 𝐶𝐹1 = 𝐶𝐹2 (1 +∈1 ) and 𝐶𝑎 = 𝐶𝑏 (1 +∈2 ), (3.9)

where ∈1 = ∆𝐶𝐹2 ⁄𝐶𝐹2 and ∈2 = ∆𝐶𝑏 ⁄𝐶𝑏 . Substituting (3.9) in (3.1) gives (3.10), while

𝑉𝑅 𝐶𝑏
𝐼2 = 𝐶2 𝑓2 . Under this condition, (3.7) will get modified as in (3.11).
𝐶𝐹2

𝑉𝑅 𝐶𝑏 (1+∈2 )
𝐼1 = −𝐶1 𝑓1 (3.10)
𝐶𝐹2 (1+∈1 )

𝑓2 /𝑓1 = (𝐶1 (1 +∈2 ))/ (𝐶2 (1 +∈1 )) (3.11)

Defining the ratio (1 +∈2 )⁄(1 +∈1 ) = 𝑘∈ , (3.11) can be re-written as in (3.12). This

shows that the mismatch introduces a gain error in 𝑓2 .

𝑓2 /𝑓1 = 𝑘∈ (𝐶1/ 𝐶2 ) (3.12)

From (3.12), it is evident that (𝐶1/𝐶2 ) can be obtained by measuring 𝑘∈ , and taking the

ratio of (𝑓2 /𝑘∈ ) and 𝑓1 as in (3.13).

(𝑓2 / 𝑘∈ )/ 𝑓1 = ( 𝐶1 / 𝐶2 ) (3.13)

The factor 𝑘∈ can be obtained by noting down 𝑓2 for 𝑥 = 0, i.e., by setting 𝐶1 = 𝐶2 .

Under this condition, 𝑘∈ = 𝑓2 /𝑓1 . This is a one-time measurement. From then onwards,

for any new measurement, a corrected output frequency 𝑓2cal = (𝑓2 /𝑘∈ ) can be

computed from the measured frequency 𝑓2 . Now, if 𝑓2 is replaced by 𝑓2cal in (3.7), the

ratio-metric output given by (3.14) will remain unaffected due to the mismatch, which

is a major advantage. The same correction can be incorporated in (3.8), when a single-

element sensor is interfaced. These computations can be realized using the CLU shown

in Fig. 3.1. This corrects the effect mismatch but there will be an effect if there is drift.

(𝑓2𝑐𝑎𝑙 − 𝑓1 ) (𝐶 − 𝐶 )
= (𝐶1+ 𝐶2) = 𝑘𝑥 (3.14)
(𝑓2𝑐𝑎𝑙 + 𝑓1 ) 1 2

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3.2.5 Range of the Sensor Capacitance

The ranges of 𝐶1 and 𝐶2 for which (3.6) is applicable is limited by the operating ranges

of the opamps and VFC used to realize the circuit given in Fig. 3.1. The maximum

output current, 𝐼𝑂1𝑚𝑎𝑥 , of OA1 will limit the maximum acceptable value, 𝐶1𝑚𝑎𝑥 , of 𝐶1 ,

𝐶𝐹
for a given 𝐶𝑎 (= 𝐶𝑏 = 𝐶), 𝐶𝐹1 (= 𝐶𝐹2 = 𝐶) and 𝑓1 , such that 𝐶1𝑚𝑎𝑥 < 𝐼𝑜1𝑚𝑎𝑥 𝑉 .
𝑅 𝐶𝑓1

𝐶𝐹
Similarly, 𝐶2𝑚𝑎𝑥 < 𝐼𝑜2𝑚𝑎𝑥 𝑉 , where 𝐶2𝑚𝑎𝑥 is the maximum value of 𝐶2 and 𝐼𝑜2𝑚𝑎𝑥
𝑅 𝐶𝑓2

is the maximum output current of OA2. The maximum output frequency, 𝑓2𝑚𝑎𝑥 ,

possible for the VFC corresponding to the maximum (less than saturation) output

voltage 𝑣𝑜𝑖3𝑚𝑎𝑥 of OA3 will introduce another limiting factor for the maximum change

Δ𝐶𝑚𝑎𝑥 possible for 𝐶1 and 𝐶2 , i. e., Δ𝐶𝑚𝑎𝑥 = 2𝐶0 (𝑓2𝑚𝑎𝑥 − 𝑓1 )/(𝑓2𝑚𝑎𝑥 + 𝑓1 ).

Considering the above factors, for sensors following (1.2)

𝐶𝐹 𝑓2𝑚𝑎𝑥 −𝑓1
𝐶𝑖𝑚𝑎𝑥 < min [𝐼𝑜𝑖𝑚𝑎𝑥 , 𝐶0 (1 + )],
𝑉𝑅 𝐶𝑓𝑖 𝑓2𝑚𝑎𝑥 +𝑓1

and for those satisfying (1.3),

𝐶𝐹 𝑓 −𝑓
𝐶𝑖𝑚𝑎𝑥 < min [𝐼𝑜𝑖𝑚𝑎𝑥 𝑉 , 𝐶0 ⁄(1 − 𝑓2𝑚𝑎𝑥 +𝑓1)]
𝑅 𝐶𝑓𝑖 2𝑚𝑎𝑥 1

where i = 1or 2. For the prototype developed, for sensors with linear characteristic, the

𝐶𝑖𝑚𝑎𝑥 works out to be 1.66 𝐶0 when 𝑓2𝑚𝑎𝑥 = 500 kHz and 𝑓1 = 100 kHz. In case of

sensors satisfying (1.3). 𝐶𝑖𝑚𝑎𝑥 = 3𝐶0 . For both cases, the resulting maximum 𝑘𝑥 is 0.66,

which is sufficient for many applications of differential capacitive sensors [68], [72],

[82]. To achieve a larger 𝑘𝑥 range, 𝑓1 can be reduced keeping the same 𝑓2max or a more

suitable VFC can be selected.

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3.2.6 Sensitivity of the Interface

In the case of the differential capacitive sensor, when 𝐶1 = 𝐶2 , 𝑓2 = 𝑓1 . When

𝐶1 = 𝐶0 + ∆𝐶 and 𝐶2 = 𝐶0 − ∆𝐶, (3.6) becomes

𝐶0 +∆𝐶 𝑓1 +∆𝑓
= . (3.15)
𝐶0 −∆𝐶 𝑓1

∆𝑐
1+ ∆𝑓
𝑐0
or ∆𝑐 = 1+ (3.16)
1− 𝑓1
𝑐0

∆𝐶 ∆𝐶 ∆𝑓
For ≪ 1, (3.16) can be approximated as 1 + 2 𝐶 ≈ 1+ , or
𝐶0 0 𝑓1

∆𝑓 2𝑓1
≈ , (3.17)
∆𝐶 𝐶0

which gives the sensitivity of the proposed CFC. For the single-element, the right-hand

𝑓
side of (3.17) reduces to 𝐶1 .
0

3.3 EFFECT OF NON-IDEALITIES

This section analyses the effect of circuit non-idealities on the final output of the

proposed SC-CFC. The non-idealities considered are the input offset voltages and bias

currents of opamps, mismatch between dc excitation voltages, variations in the switch

control signals φsw and φ1, charge injection, and ON-resistance of switches, and parasitic

capacitances associated with the differential capacitive sensor. Here, let 𝐶𝐹1 = 𝐶𝐹2 = 𝐶𝐹 ,

and 𝐶𝑎 = 𝐶𝑏 = 𝐶.

3.3.1 Input Offset Voltages and Input Bias Currents of Opamps

Let 𝑉𝑂𝑆1, 𝑉𝑂𝑆2, and 𝑉𝑂𝑆3 be the input offset voltages at the non-inverting terminals of

OA1, OA2, and OA3, respectively. Since S5 is used only to connect and disconnect

59
node 𝑐 to the input of OA3, 𝑣𝑜𝑖3 , due to 𝑉𝑂𝑆3, will be 𝑉𝑂𝑆3 alone, with no other

integrating components. Hence the effect of 𝑉𝑂𝑆3 at the output of OA3 can be

compensated by appropriately designing the VFC. This is required to maintain 𝑓1 = 𝑓2 ,

when 𝐶1 = 𝐶2 .

𝑉𝑂𝑆1 and 𝑉𝑂𝑆2 contribute an additional voltage step in 𝑣𝑜𝑖1 and 𝑣𝑜𝑖2 , respectively. The

impact of 𝑉𝑂𝑆1 in 𝑣𝑜𝑖1 and that of 𝑉𝑂𝑆2 in 𝑣𝑜𝑖2 , at any instant 𝑛, are given by (3.18) and

(3.19), respectively, where 𝑚 = 1 if φsw is high and 𝑚 = −1, otherwise. Also,

𝑣𝑜𝑖1 (𝑛) = 𝑉𝑂𝑆1, and 𝑣𝑜𝑖2 (𝑛) = 𝑉𝑂𝑆2, when 𝑛 = 0.

𝑣𝑜𝑖1 (𝑛 + 1) = 𝑣𝑜𝑖1 (𝑛) + 𝑉𝑂𝑆1 𝐶 ⁄𝐶𝐹 − 𝑚 𝑉𝑅 𝐶 ⁄𝐶𝐹 (3.18)

𝑣𝑜𝑖2 (𝑛 + 1) = 𝑣𝑜𝑖2 (𝑛) + 𝑉𝑂𝑆2 𝐶 ⁄𝐶𝐹 + 𝑚 𝑉𝑅 𝐶 ⁄𝐶𝐹 (3.19)

Thus, for φsw = high, when 𝐼1 = − 𝐼2 ,

(𝐶1 (𝑉𝑂𝑆1 −𝑉𝑅 ) 𝐶 ⁄𝐶𝐹 ) 𝑓1 = (𝐶2 (𝑉𝑂𝑆2 +𝑉𝑅 ) 𝐶 ⁄𝐶𝐹 ) 𝑓2 . (3.20)

Rearranging (3.20), gives

(𝑉 +𝑉 )
( 𝐶1/ 𝐶2 ) = | (𝑉𝑂𝑆2 −𝑉𝑅 ) | (𝑓2 /𝑓1 ) (3.21)
𝑂𝑆1 𝑅

Assuming 𝑉𝑂𝑆1 , 𝑉𝑂𝑆2 , 𝑉𝑅 to be not time varying, (3.21) can be re-written as

( 𝐶1/ 𝐶2 ) = 𝑘𝑂𝑆 (𝑓2 /𝑓1 ). (3.22)

In the case of the prototype of the proffered circuit, the maximum value of both 𝑉𝑂𝑆1

and 𝑉𝑂𝑆2 is 75 µV. Substituting these in (3.21) shows that 𝑉𝑂𝑆1, 𝑉𝑂𝑆2 ≪ 𝑉𝑅 (= 2.5 V)

and so, in the developed prototype, input offset voltage has a negligible impact. Thus,

as long as the opamps used in the proposed circuit are chosen such that 𝑉𝑂𝑆1 and

60
𝑉𝑂𝑆2 ≪ 𝑉𝑅 , and the VFC designed to compensate for 𝑉𝑂𝑆3 , the impact of the input

offset voltages in the final output is negligible.

Let 𝐼𝐵1 , 𝐼𝐵2 , and 𝐼𝐵3 be the input bias currents at the inverting terminals of OA1, OA2,

and OA3 respectively. The presence of 𝐼𝐵1 will change 𝑣𝑜𝑖1 by 𝐼𝐵1 𝑇1 /𝐶𝐹 in each cycle
𝐼𝐵1 𝑇1
of φ1. However, in practice, ≪ 𝑉𝑅 𝐶 ⁄𝐶𝐹 . Hence the effect of 𝐼𝐵1 in 𝐼1 is negligible.
𝐶𝐹

Similarly, the effect of 𝐼𝐵2 in 𝐼2 is not significant. However, since the bias current is

flowing continuously in the same direction, 𝑣𝑜𝑖1 and 𝑣𝑜𝑖2 will go into saturation. To

prevent this, resistors of appropriate values (20 M) are connected in parallel to

𝐶𝐹1 and 𝐶𝐹2 , respectively. Since this resistor is in the feedback-path of OA1 and OA2,

it can be implemented using relatively low-value resistors, say the largest being in

100 kΩ range, connected in a T- network. It has been reported that the leakage

resistance of on-chip capacitors is in the range of few mega ohms [83]. In such a case,

the additional resistor in parallel, as in the prototype, may not be necessary. In case the

above options are not feasible, keeping these resistors external to the IC can be

considered, to save the chip area, when an IC is designed.

In the ideal condition, at steady state, 𝐼3 /2 = 𝐼CF3 = 0. Due to the presence of 𝐼𝐵3 , at the

input of OA3, at steady state

(𝐼3 )/2 = 𝐼CF3 = −𝐼𝐵3 . (3.23)

Substituting (3.1) and (3.3) in (3.23) with 𝑓2 replaced with 𝑓2′ , to indicate the new

condition 𝐼CF3 = −𝐼𝐵3 , and rearranging, (3.24) is obtained.

( −𝐼𝐵3 𝐶𝐹 ⁄𝑉𝑅 𝐶 ) 𝐶
𝑓2′ = + (𝐶1) 𝑓1 (3.24)
𝐶2 2

Substituting the values from the prototype of the proposed circuit ( 𝐼𝐵3 = 30 pA,
61
𝐶𝐹 = 2 nF, 𝐶 = 20 pF, 𝑉𝑅 = 2.5 V, 𝑓1 = 100 kHz, along with the smallest value of 𝐶2

used, 100 pF, and the corresponding 𝐶1 = 400 pF) in (3.24), the relative error in 𝑓2′ , with

respect to 𝑓2 , obtained is −0.003%. Thus, as long as OA1, OA2, and OA3 are chosen

𝐼𝐵1 𝑇1 𝐼𝐵2 𝑇1 ( −𝐼𝐵3 𝐶𝐹 ⁄𝑉𝑅 𝐶 ) 𝐶

such that , ≪ 𝑉𝑅 𝐶 ⁄𝐶𝐹 and ≪ (𝐶1) 𝑓1 , in the proffered circuit,
𝐶𝐹 𝐶𝐹 𝐶2 2

the impact of bias current in the final output is negligible.

3.3.2 Mismatch between +VR and −VR

Let the positive dc excitation be +𝑉𝑅 , whereas the negative be −𝑉𝑅 (1 +∈𝑉 ), where ∈𝑉

is the relative mismatch between the magnitudes of the 𝑉𝑅 and −𝑉𝑅 . ∈𝑉 = 0, in an ideal

case. This voltage mismatch contributes to 𝐼𝐶𝐹3 when φsw = 1. In this condition, 𝐼2 and

𝐼3 given in (3.2) and (3.3) will get modified as (3.25) and (3.26), respectively.

𝜕𝑣𝑜𝑖2 𝑉𝑅 (1+∈𝑉 )𝐶
𝐼2 = 𝐶2 = 𝐶2 𝑓2 (3.25)
𝜕𝑡 𝐶𝐹

𝑉𝑅 𝐶 𝑉𝑅 𝐶
𝐼3 = 𝐼1 + 𝐼2 = (𝐶2 𝑓2 − 𝐶1 𝑓1 ) + 𝐶2 ∈𝑉 𝑓2 (3.26)
𝐶𝐹 𝐶𝐹

In a balanced condition, 𝐼𝐶𝐹3 = 𝐼3 = 0. Then, the condition (3.27) can be obtained from

(3.26).

𝐶1 𝑓2
= 𝑘𝑉 (3.27)
𝐶2 𝑓1

Comparing (3.27) with (3.6), it can be seen that the mismatch in reference voltages

results in a multiplication factor 𝑘𝑉 = (1 +∈𝑉 ). The value of 𝑘𝑉 can be calculated, to

correct the measurement, by setting 𝐶1 = 𝐶2 and comparing the 𝑓2𝑚𝑒𝑎𝑠 measured to the

𝑓1
expected 𝑓2 (= 𝑓1 ), i.e. 𝑘𝑉 = . If there is a drift in ∈𝑉 , a periodic
𝑓2𝑚𝑒𝑎𝑠

calibration/correction will be required.

62
3.3.3 Variations in the Switch Control Signals φsw and φ1

A change in the frequency fsw of φsw, will change the duration for which φsw is high.

During the operation, the step change in 𝑣𝑜𝑖2 is 𝑉𝑅 𝐶 ⁄𝐶𝐹 . The maximum number of such

steps, expected, when φsw is high is (𝑓2𝑚𝑎𝑥 )/(2𝑓𝑠𝑤 ). Let us say that the maximum output

voltage swing of OA2 is 2(𝑉𝑆𝐴𝑇 − 1), where 𝑉𝑆𝐴𝑇 is the saturation voltage of opamp.

This means [(𝑓2𝑚𝑎𝑥 )/(2𝑓𝑠𝑤 )] < [2(𝑉𝑆𝐴𝑇 − 1)/(𝑉𝑅 𝐶 ⁄𝐶𝐹 )], or the design should satisfy

the condition,

(𝑓2𝑚𝑎𝑥 𝑉𝑅 𝐶)
< 𝑓𝑠𝑤(𝑚𝑖𝑛) ,
4(𝑉𝑆𝐴𝑇 −1)𝐶𝐹

where 𝑓𝑠𝑤(𝑚𝑖𝑛) in the minimum value of fsw expected. Any change in the frequency of

φ1 will impact the accuracy of the measurement. In the proposed CFC, the value of 𝑓1

was found to be stable and accurate during the measurement time. However, it is

advisable to measure 𝑓1 periodically, using the same counter/timer, and use in (3.7) or

(3.8), to ensure that the accuracy of the measurement of 𝑘𝑥 is not affected.

3.3.4 Charge Injection and ON-resistance of Switches

To analyze the effect of charge injection, each SPDT switch in Fig. 3.1 can be replaced

by the charge injection model given in [50]. The charge injected at the output of each

switch is a combination of charges generated during breaking of a contact, say

position ‘1’, and making of the next, say position ‘0’. S3, S4, and S5 inject charges into

𝐶𝐹1 , 𝐶𝐹2 , and 𝐶𝐹3 , respectively, changing 𝑣𝑜𝑖1 , 𝑣𝑜𝑖2 , and 𝑣𝑜𝑖3 , respectively, thereby

affecting the final output of the proposed CFC. To realize the switches, IC MAX4709

from Maxim Integrated has been used. This IC is so designed that the switches inject

zero charges during the making and breaking of the input-output connections. The

functional diagram can be found in [50] and [84]. The implementation of these ICs on

63
the silicon substrate is done using the CMOS process [50]. As this is a zero-charge

injection switch, the associated error will be negligible.

The impact of the switch ON-resistances can be analyzed by replacing the switches

S1-S4 by the corresponding resistances 𝑅𝑂𝑁1, 𝑅𝑂𝑁2, 𝑅𝑂𝑁3, and 𝑅𝑂𝑁4, respectively.

Consider first that φsw = high. If for φ1 = 0, φ2 = 0, as long as (𝑅𝑂𝑁1 + 𝑅𝑂𝑁3)𝐶𝑎 <<

(1/𝑓1 ) and (𝑅𝑂𝑁2 + 𝑅𝑂𝑁4)𝐶𝑏 << (1/𝑓2 ), 𝐶𝑎 and 𝐶𝑏 get fully charged to +𝑉𝑅 and −𝑉𝑅 ,

respectively, and vice-versa for φsw = low. For φ1 = 1, φ2 = 1, the outputs of OA1 and

OA2 will be negligibly affected by the ON-resistances while 𝑅𝑂𝑁3 𝐶𝑎 << (1/𝑓1 ) and

𝑅𝑂𝑁4 𝐶𝑏 << (1/𝑓2 ) holds true.

3.3.5 Parasitic Capacitances

Parasitic capacitance to ground will be present when shielded cables, with shield

connected to ground, are used to connect the capacitive sensor to the interface circuit.

Similarly, there will be parasitic capacitance between the ground plane and traces of

the printed circuit board or lines of the bread-board. The equivalent lumped model of

the parasitic capacitances is shown as 𝐶𝑃1 , 𝐶𝑃2 , and 𝐶𝑃3 in Fig. 3.3. 𝐶𝑃1 and 𝐶𝑃2 do not

impact the performance of the proposed circuit as long as the outputs of the opamps

OA1 and OA2 are not overloaded by them. 𝐶𝑃3 is inactive as one end of it is connected

to the virtual ground or ground while the other is always at ground. Hence, it has no

impact on the final output.

VFC is an important unit of the proposed CFC. A VFC that can be set to give 𝑓1 when

𝑣𝑜𝑖3 is zero is required. A drift free VFC with linear characteristic is preferred for the

ease of design, optimal use of the full range of the circuit and high accuracy.

64
 Fig. 3.3 The parasitic capacitances 𝐶𝑃1 , 𝐶𝑃2 and 𝐶𝑃3 , associated with the
differential capacitive sensor consisting of 𝐶1 and 𝐶2 , are indicated.

3.4 EXPERIMENTAL SETUP AND RESULTS

The hardware prototype of the proposed closed-loop SC-CFC, given in Fig. 3.1, was

realized using the components and ICs listed in Table 3.1. In the prototype, the clock

signals φsw and φ1 were set using a function generator to 𝑓𝑠𝑤 = 1 kHz and 𝑓1 = 100 kHz,

respectively. Since these are generated from the same dual-channel function generator,

they are in synchronization. Alternatively, the synchronization can be maintained by

generating φsw and φ1 using the timer/counter unit of a microcontroller, with appropriate

pre-scaler. As 𝑓2 need not be an integral multiple of 𝑓𝑆𝑊 , there will be partial transfer

of charge from Cb to CF2 when there is a transition in 𝑆𝑊 . We have analysed the effect

using simulation and observed that it is negligible when we keep 𝑓1 = 100𝑓𝑆𝑊 or higher.

In the prototype, ADVFC32 was employed. It has high linearity, e.g., 0.05% in the 100

kHz range and 0.2% in the 500 kHz range. The VFC was set to output 𝑓2 = 𝑓1 , for x = 0,

by selecting the values of the resistors and capacitors in accordance with the design

calculations given in [85]. Also, the VFC was configured to handle both positive and

negative values of 𝑣𝑜𝑖3 .

65
 Table 3.1 Components and ICs used in the CFC Prototype

Component Part/Value Component Part/Value

𝑉𝑅 Using 𝐶𝑎 , 𝐶𝑏 20 pF
LM385-2.5
𝑆1 - 𝑆5 MAX4709 𝐶𝐹1 , 𝐶𝐹2 2 nF
VFC ADVFC32 𝐶𝐹3 2 nF
OA1, OA2 OPA227 ∆𝐶 ±150 pF
OA3 LF357 fsw 1 kHz
CLU ATSAM3X8E 𝑓1 100 kHz

Frequency 𝑓2 corresponding to 𝐶1 = 𝐶2 , was used to determine the mismatch correction

factor, 𝑘∈ as in (3.12). The prototype was then tested using two identical standard

variable capacitance boxes, with high leakage resistances, representing 𝐶1 and 𝐶2 , set

to the nominal capacitance value, 𝐶0 = 250 pF. The final ratio-metric output, as per

(3.14), was obtained after applying the corrections for mismatch discussed in

section 3.2.4. The counter in the CLU was programmed to measure 𝑓2 for a gate time

of 10 ms. This was used in the CLU to compute the final output applying (3.13). The

important waveforms from the prototype were observed using MSO 2014, Mixed

Signal Oscilloscope, during the test. A snapshot of the waveforms, from the

oscilloscope, for 𝐶1 > 𝐶2 is given in Fig. 3.4.

As proof-of-concept, the prototype was implemented with discrete components and ICs

and, hence, it was not optimised for low power consumption. In this prototype, the

power consumption of the opamps, VFC, switches and VR were, POA = 110 mW,

PVFC = 80 mW, PSW = 6 mW and PVR = 50 W, respectively.

66
67
Fig. 3.4 A snapshot of the integrator waveforms, from the prototype, for 𝐶1 > 𝐶2 .
The clock is generated in the prototype by a function generator, but in practice it can be

generated by the microcontroller. When the microcontroller is used to generate φSW and

φ1, in addition to measuring 𝑓2 , the power PµC taken was about PµC  3 mW. Thus the

total power = POA + PVFC + PSW + PVR + PµC  200 mW. If the entire unit is designed

and fabricated as a single chip, the overall power consumption could be reduced to as

low as that of a dual-slope ADC ( 10 mW [86]).

3.4.1 Testing the Effectiveness of the Mismatch Correction

To test the effectiveness of the correction mechanism against component mismatch,

discussed in section 3.2.4, a test was conducted by intentionally introducing a mismatch

between 𝐶𝑎 and 𝐶𝑏 by setting 𝐶𝑏 = 𝐶𝑎 /2. The error percentage in the VFC output before

and after correction for different values of ∆𝐶 (deviation of 𝐶1 from the nominal

capacitance) is given in Table 3.2. As can be seen, the correction mechanism almost

completely removes the effect of the mismatch. The same test was conducted by

similarly introducing a mismatch between the 𝐶𝐹1 and 𝐶𝐹2 , and the correction was also

found to be effective.

Table 3.2 Effectiveness of the Mismatch Correction in the CFC

∆𝐶 (pF) -10 -5 0 +5 +10

% Error before
48.39 48.32 48.40 48.00 48.48
correction

% Error after
0.01 0.15 0.00 0.17 0.15
correction

3.4.2 Testing Linearity and Sensitivity

In this test, the values of 𝐶1 and 𝐶2 were first set to nominal capacitance 𝐶0 = 250 pF.

Then they were varied in steps of 10 pF in opposing directions, for 15 steps in either
68
direction. This process emulates a differential capacitive sensor with a linear

characteristic as in (1.2), with a full-scale change kxFS = 0.6. The CLU provided the

output as per (3.13), for each step. In this manner, the output was recorded for a range

of capacitance, ∆𝐶 = ±150 pF, from nominal value. The results are presented in Fig. 3.5.

This corresponds to a full-scale 𝑘𝑥 = ± 0.6. This tested range covers the range of

measurement in several applications, e.g., 0.35 [68], 0.536 [72] and 0.6 [82]. This is

within the possible range discussed in section 3.2.5.

To obtain the maximum non-linearity error (NLE), the recorded output-data was first

plotted. A trend-line of the same was then obtained using the Least Squares Algorithm.

Subsequently, the values of the y-axis were determined by substituting the

corresponding x-axis data in the trend-line equation. These values are taken as the

expected output values, had the system been linear. Each measured value was

subtracted from the corresponding expected value, for the full measurement range. This

gives the NLE in each measurement. The % with respect to the full-scale (kxFS = 0.6)

gave the % NLE. The maximum NLE observed was 0.24%.

In addition, the linearity was tested for the single-element capacitive sensor. For this

test the same value of 𝐶0 was used and the value of 𝐶1 alone varied in steps of 10 pF

from 100 pF to 400 pF. The worst-case %NLE found in this test was 0.19 %. The

linearity of the prototype circuit has also been verified for single-element and

differential capacitive sensors that follow inverse characteristic as in (1.3).

The sensitivity of the frequency output 𝑓2 with respect to ∆𝐶 was computed using

(3.17). For the prototype developed 𝑓1 = 100 kHz and 𝐶0 = 250 pF. The resulting

∆𝑓
sensitivity is ≈ 0.8 kHz/pF. The same has been verified practically from the
∆𝐶

prototype. For the single-element capacitive sensor, this was found to be ≈ 0.4 kHz/pF.
69
70
Fig. 3.5 Results from the prototype by varying 𝐶1 and 𝐶2 . The output and the
percentage non-linearity error obtained are shown.
3.4.3 Testing Resolution, Signal-to-Noise Ratio (SNR) and Repeatability

The prototype CFC was operated for ∆𝐶 = 5 pF, and the ratio-metric output,

(𝑓2 − 𝑓1 )⁄(𝑓2 + 𝑓1 ), was recorded 30 times and tabulated. The formulae given in Table

3.3, based on the approach given in [58], were used to determine the parameters, given

in the same table. The proffered circuit shows a resolution of 12.59 bits (ENOB), signal-

to-noise ratio (SNR) of 77.56 dB and repeatability error of 0.01%. The corresponding

smallest capacitance that can be measured is 2 fF and expected error is less than 0.25%.

Table 3.3 Repeatability Study for the CFC

Parameter Formula Value

Signal-to-noise ∑𝑀𝑖=1 𝑋(𝑖)
2
𝑆𝑁𝑅 = 10 𝑙𝑜𝑔 77.56 dB
ratio (SNR) ∑𝑀 ̅2
𝑖=1[𝑋(𝑖) − 𝑋 ]

Standard ∑𝑀 ̅2
𝑖=1[𝑋(𝑖) − 𝑋 ]
𝜎= √ 4.33 × 10-5
Deviation, 𝜎 𝑀−1

Resolution (𝑆𝑁𝑅 − 1.76)

𝑛= 12.59 bits
(ENOB), 𝑛 bits 6.02
∆
Repeatability, 𝑑𝑅 𝑑𝑅 = 𝑋𝑟𝑚𝑎𝑥 × 100% 0.01%
−𝑋
𝑢 𝑙

𝑋(𝑖) = ith measurement; 𝑋̅ = average value of the measured data

𝑀 = total number of measurements
𝑋𝑢 , 𝑋𝑙 = upper and lower limits of CFC
∆𝑟𝑚𝑎𝑥 = maximum difference between repeated measurements

3.4.4 Testing Step Response

To ascertain the rise time of the proffered CFC, initially, the sensor capacitance was set

to its mid-scale and then a sudden change in capacitance was introduced, in parallel,

using a switching arrangement controlled by the signal 𝑣𝑠𝑡𝑒𝑝 . When 𝑣𝑠𝑡𝑒𝑝 = 0, an

additional capacitance of 10 pF was introduced in parallel to 𝐶1 , using a capacitance

box, with negligible leakage conductance, from Rohde and Schwarz. The rise time was

6 ms for 𝑓𝑠𝑤 = 1 kHz and 𝑓1 = 100 kHz. Fig. 3. 6 is a snapshot of the corresponding

71
72
Fig. 3.6 Rise time of the CFC for 𝑓𝑠𝑤 = 1 kHz, 𝑓1 = 100 kHz.
waveforms. As mentioned in section 3.2.3, 𝑓2 is measured using a counter. In the

prototype, a change in the measurand will be correctly reflected in the output, at steady

state, after about 16 ms, considering the rise time of 6 ms, and the gate time of 10 ms.

To verify the impact of the values of the operating frequencies in the rise time of the

prototype SC-CFC, both 𝑓𝑠𝑤 and 𝑓1 were decreased to 100 Hz and 10 kHz, respectively.

Then, the rise time was 65 ms. The results in both cases showed that the rise time

improved by approximately ten times when the operating frequencies 𝑓𝑠𝑤 and 𝑓1 were

increased tenfold.

3.5 DISCUSSION

The main features of the new scheme have been analyzed in comparison with the best

ten of the existing schemes, and presented in Table 3.4. The proposed scheme is suitable

for single-element and differential capacitive sensors (DCS), which is a main difference

as can be seen in Table 3.4. The CFCs [75] - [77] presented in Table 3.4 are suitable

only for single-element capacitive sensor. The presented approach provides a linear

output, without any additional computation or correction, even for single-element

sensor that follows an inverse characteristic which is another specialty.

Other important factors of the proposed approach are: (a) It uses a closed-loop

approach. Differential capacitance-to-frequency converter with this feature has not

been sufficiently explored before. Closed-loop approach has been used to realize self-

balancing bridges in [64], [81]. However, the outputs of these bridge schemes are

sensitive to parasitic capacitance. In addition, they need a precise sinusoidal ac

excitation. These designs have limited linearity and accuracy due to the use of analog

multipliers, with high error (as large as 2%), in them. (b) Excitation is derived from a

73
 Table 3.4. Comparison Table for the CFC

74
simple dc reference source. (c) Since it uses switched-capacitor circuit, it is relatively

easy to design and fabricate its IC. (d) Insensitive to parasitic capacitance and mismatch

in values of components used. (e) Ratio-metric output for DCS and ratio output for

single-element capacitive sensor. Hence a linear output is obtained independent of the

sensor characteristic, and nominal capacitance. Some of the existing schemes have only

some of the features of the proposed scheme as can be seen in Table 3.4.

The proposed design does not rely on voltage-controlled resistors to realize auto-

balancing [64], [81]. Instead, a VFC, together with a switched-capacitor mechanism,

effectively realizes the auto-balancing. It is important to select a VFC with sufficient

linearity. VFCs with very high linearity, as the one used in the prototype, are available

[85].

3.6 CONCLUSION

The design, development, and realization of a new closed-loop switched-capacitor

capacitance-to-frequency converter (CFC) have been presented in this chapter. The

developed CFC is suitable for single-element and differential capacitive sensors. The

scheme provides a linear output, irrespective of the sensor characteristic being linear or

inverse. The output is independent of the value of the nominal capacitance, and

insensitive to the parasitic capacitances, which enhance the ease of interfacing. Thus,

the presented circuit is compatible for integration with a wide variety of single-element

and differential capacitive sensors. It uses a simple dc excitation source, as opposed to

complex ac sinusoidal excitation which needs precise amplitude stabilization and very

low total harmonic distortion. As the scheme is realized using switched-capacitor

circuit, the presented CFC is suitable for IC fabrication.

The prototype of the proposed CFC possesses desirable features such as a low

maximum non-linearity error (NLE) of 0.24%, a resolution of 12.59 bits (ENOB),

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signal-to-noise ratio (SNR) of 77.56 dB, and rise time of 6 ms. The range of the

prototype CFC developed is ±60% of the nominal capacitance of the sensor. The range

and measurement time can be modified by suitably selecting the frequency of clock

signals, components, and ICs. The design presented specifies criteria to minimize the

impact of circuit non-idealities such as input offset voltage and input bias current of

opamp, and mismatch between the magnitudes of the dc reference voltages.

The CFC in this chapter presents a novel auto-balancing capacitance measurement

scheme, especially for the DCS. However, it is reliant on a voltage-to-frequency

converter, which increases the cost and complexity of the interfacing circuit. Also, it

cannot be used with capacitive sensors that employ sinusoidal ac excitation. Another

auto-balancing quasi-digital scheme, with all the advantages of the CFC, yet does not

have the additional cost and complexity of analog blocks like the VFC, and uses a

sinusoidal excitation source, is presented in the next chapter.

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