C DA D P D - T G: Lass Udio River With Recision EAD IME Enerator
C DA D P D - T G: Lass Udio River With Recision EAD IME Enerator
C DA D P D - T G: Lass Udio River With Recision EAD IME Enerator
Features
0.5 A peak output (Si8241) Input to output isolation for low noise
4.0 A peak output (Si8244) (up to 2500 V)
Up to 8 MHz operation
PWM input
Wide operating range
High-precision linear programmable
–40 to +125 °C
dead-time generator
0.4 ns to 1 µs
Transient immunity >45 kV/µs
High latchup immunity >100 V/ns
RoHS-compliant
SOIC-16 narrow body
Up to 1500 Vrms output-output
isolation, supply voltage of ±750 V
Applications
Ordering Information:
Class D audio amplifiers See page 27
Description
Pin Assignments
The Si824x isolated driver family combines two isolated drivers in a single
package. The Si8241/44 are high-side/low-side drivers specifically targeted at
high-power (>30 W) audio applications. Versions with peak output currents of
0.5 A (Si8241) and 4.0 A (Si8244) are available. All drivers operate with a
SOIC-16 (Narrow)
maximum supply voltage of 24 V. PWM 1 16 VDDA
Based on proprietary isolation technology, the Si824x audio drivers incorporate
input-to-output and output-to-output isolation, which enables level-translation of NC 2 15 VOA
signals without additional external circuits as well as use of bipolar supply voltage VDDI 3 14 GNDA
up to ±750 V. The Si824x audio drivers feature an integrated dead-time generator
that provides highly precise control for achieving optimal THD. These products GNDI 4 13 NC
Si8241/44
also have overlap protection that safeguards against shoot-through current DISABLE 5 12 NC
damage. The CMOS-based design also provides robust immunity from latch-up
and high-voltage transients. The extremely low propagation delays enable faster DT 6 11 VDDB
modulation frequencies for an enhanced audio experience. The TTL level NC 7 10 VOB
compatible inputs with >400 mV hysteresis are available in PWM input
configuration; other options include UVLO levels of 8 V or 10 V. These products VDDI 8 9 GNDB
are available in narrow body SOIC packages.
Functional Block Diagram Patents Pending
PWM
VDDA
Isolation
VOA
DT
GNDA
VDDI Programmable Dead
Time, Control Gating
UVLO
VDDB
Isolation
DISABLE VOB
GNDB
GNDI
Si8241/44
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TA B L E OF C ONTENTS
Section Page
1. Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. Typical Performance Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2. Typical Performance Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3. Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . . . . . . . . 17
3.4. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.7. Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . . 22
4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1. Class D Digital Audio Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1. Si824x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 28
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Si 824x
1. Top-Level Block Diagram
VDDI
VDDA
PWM
ISOLATION
LPWM
VOA
UVLO
GNDA
DT CONTROL
&
DT OVERLAP
PROTECTION
VDDI
VDDI
VDDI VDDB
ISOLATION
UVLO
VOB
UVLO
DISABLE
GNDB
LPWM
GNDI
Si8241/44
Figure 1. Si8241/44 Single-Input High-Side/Low-Side Isolated Drivers
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2. Electrical Specifications
Input Supply Active Current IDDI PWM freq = 500 kHz — 2.5 — mA
Output Supply Active Current IDDO PWM freq = 500 kHz — 3.6 — mA
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Table 1. Electrical Characteristics1 (Continued)
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
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Si824x
2.1. Test Circuits
Figures 2 and 3 depict sink current and source current test circuits.
VDDA = VDDB = 15 V
VDDI
VDD
10
IN OUT
INPUT Si824x
SCHOTTKY +
VSS 1 µF 100 µF 8V _
1 µF 10 µF
Measure
CER EL
RSNS
50 ns 0.1
VDDI
GND
200 ns
INPUT WAVEFORM
VDDA = VDDB = 15 V
VDDI
VDD
10
IN OUT
INPUT Si824x
SCHOTTKY
5.5 V +
VSS 1 µF 100 µF _
1 µF 10 µF
Measure
CER EL
RSNS
50 ns 0.1
VDDI
GND
200 ns
INPUT WAVEFORM
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Si 824x
12 V
Supply
Si824x
VDDI VDDA
Input Signal
INPUT VOA
Switch
5V DISABLE GNDA
Isolated
Supply DT VDDB Oscilloscope
100k VOB
GNDI GNDB
Isolated
Ground High Voltage Output
Input Differential
Probe
Vcm Surge
Output
High Voltage
Surge Generator
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60
Safety-Limiting Current (mA)
50
VDDI = 5.5 V
40 VDDA, VDDB = 24 V
30
20
10
0
0 50 100 150 200
Case Temperature (ºC)
Figure 5. NB SOIC-16, Thermal Derating Curve, Dependence of Safety Limiting Values with Case
Temperature per DIN EN 60747-5-2
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Si 824x
3. Functional Description
The operation of an Si824x channel is analogous to that of an opto coupler and gate driver, except an RF carrier is
modulated instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si824x channel is shown in
Figure 6.
VDD
Dead Semiconductor-
Based Isolation B
A Time Modulator Demodulator
Generator Barrier 0.5 to 4 A
peak
Gnd
Input Signal
Modulation Signal
Output Signal
Figure 7. Modulation Scheme
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3.1. Typical Performance Characteristics (0.5 Amp)
The typical performance characteristics depicted in Figures 8 through 19 are for information purposes only. Refer
to Table 1 on page 5 for actual specification limits.
10
25 4
H-L
3
20 VDDA = 15V,
f = 250kHz, CL = 0 pF
L-H 2 Duty Cycle = 50%
15 2 Channels Switching
VDD=12V, 25°C 1
CL = 100 pF
-50 0 50 100
10
Temperature (°C)
9 12 15 18 21 24
VDDA Supply (V)
3.3 V
Figure 9. Propagation Delay vs. Supply Voltage 3.3
Figure 12. Supply Current vs. Temperature V
40
35
4 Trise
Duty Cycle = 50% 30
Rise/Fall Time (ns)
VDDA Supply Current (mA)
3.5 CL = 0 pF
1 Channel Switching 1MHz 25
3
20 Tfall
2.5 500kHz
15
2 100kHz 10
1.5 5
50 kHz VDD=12V, 25°C
1 0
9 14 19 24 0.0 0.5 1.0 1.5 2.0
VDDA Supply Voltage (V) Load (nF)
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Si 824x
50 4
45 3.75
Propagation Delay (ns)
40 3.5
30 3
H-L
25 2.75
20 2.5
15 2.25
VDD=12V, 25°C VDD=12V, Vout=VDD-5V
10 2
0.0 0.5 1.0 1.5 2.0 10 15 20 25
Load (nF) Supply Voltage (V)
3.3
Figure 14. Propagation Delay vs. Load V 3.3 V
Figure 17. Output Source Current vs. Supply
Voltage
30
7
6.75
Propagation Delay (ns)
25 6.5
L-H 6.25
3.3 V
Figure 15. Propagation Delay vs. Temperature
Temperature (°C)
3.3 V
Figure 18. Output Sink Current vs. Temperature
9
3.5
8
3.25
Sink Current (A)
7
3
6 2.75
2.5
5
3.3
Figure 16. Output Sink Current vs. Supply V Temperature (°C)
Voltage 3.3
Figure 19. Output Source Current vs. V
Temperature
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3.2. Typical Performance Characteristics (4.0 Amp)
The typical performance characteristics depicted in Figures 20 through 31 are for information purposes only. Refer
to Table 1 on page 5 for actual specification limits.
10
Tfall 10
8 500kHz
6
6
Trise
4 100kHz
4
2
50 kHz
0
2 9 14 19 24
VDD=12V, 25°C
CL = 100 pF VDDA Supply Voltage (V)
0
9 12 15 18 21 24
Figure 23. Supply Current vs. Supply Voltage
VDDA Supply (V)
10
Figure 20. Rise/Fall Time vs. Supply Voltage
30 6
4 VDDA = 15V,
Propagation Delay (ns)
f = 250kHz, CL = 0 pF
25
Duty Cycle = 50%
2
2 Channels Switching
L-H
0
20
-50 0 50 100
15
VDD=12V, 25°C Figure 24. Supply Current vs. Temperature
CL = 100 pF
10
40
9 12 15 18 21 24
VDDA Supply (V) 35
Trise
30
Rise/Fall Time (ns)
15
CL = 0 pF
12 1MHz
1 Channel Switching 5
10 VDD=12V, 25°C
0
8
500kHz 0 1 2 3 4 5 6 7 8 9 10
6
4
Load (nF)
100kHz
2
50 kHz
Figure 25. Rise/Fall Time vs. Load
0
9 14 19 24
VDDA Supply Voltage (V)
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Si 824x
50 4
45 3.75
H-L
Propagation Delay (ns)
40 3.5
30 7
6.75
6.5
Propagation Delay (ns)
25 H-L
6.25
Sink Current (A)
6
L-H 5.75
20 5.5
5.25
5
15 4.75
4.5
VDD=12V, Load = 200pF 4.25 VDD=12V, Vout=5V
10 4
-40 -20 0 20 40 60 80 100 120 -40 -10 20 50 80 110
Temperature (°C) Temperature (°C)
Figure 27. Propagation Delay vs. Temperature Figure 30. Output Sink Current vs. Temperature
9 3.5
3.25
8
Source Current (A)
Sink Current (A)
3
7
2.75
6
2.5
5
2.25
VDD=12V, Vout=5V
VDD=12V, Vout=VDD-5V
4 2
10 12 14 16 18 20 22 24 -40 -10 20 50 80 110
Supply Voltage (V) Temperature (°C)
Figure 28. Output Sink Current vs. Supply Figure 31. Output Source Current vs.
Voltage Temperature
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3.3. Family Overview and Logic Operation During Startup
The Si824x family of isolated drivers consists of high-side, low-side, and dual driver configurations.
3.3.1. Products
Table 9 shows the configuration and functional overview for each product in this family.
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3.4. Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these
supplies must be placed as close to the VDD and GND pins of the Si824x as possible. The optimum values for
these capacitors depend on load current and the distance between the chip and the regulator that powers it. Low
effective series resistance (ESR) capacitors, such as Tantalum, are recommended.
3.5. Power Dissipation Considerations
Proper system design must assure that the Si824x operates within safe thermal limits across the entire load range.
The Si824x total power dissipation is the sum of the power dissipated by bias supply current, internal switching
losses, and power delivered to the load. Equation 1 shows total Si824x power dissipation. In a non-overlapping
system, such as a high-side/low-side driver, n = 1.
2 2
P D = V DDI I DDI + 2 V DDO I QOUT + C int V DDO F + 2n C L V DDO F
where:
P D is the total Si824x device power dissipation (W)
I DDI is the input-side maximum bias current (3 mA)
I QOUT is the driver die maximum bias current (2.5 mA)
C int is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)
V DDI is the input-side VDD supply voltage (4.5 to 5.5 V)
V DDO is the driver-side supply voltage (10 to 24 V)
F is the switching frequency (Hz)
n is the overlap constant (max value = 2)
Equation 1.
The maximum power dissipation allowable for the Si824x is a function of the package thermal resistance, ambient
temperature, and maximum allowable junction temperature, as shown in Equation 2:
T jmax – T A
P Dmax ---------------------------
ja
where:
P Dmax = Maximum Si824x power dissipation (W)
T jmax = Si824x maximum junction temperature (150 °C)
T A = Ambient temperature (°C)
ja = Si824x junction-to-air thermal resistance (105 °C/W)
F = Si824x switching frequency (Hz)
Equation 2.
Substituting values for PDmax Tjmax, TA, and ja into Equation 2 results in a maximum allowable total power
dissipation of 1.19 W. Maximum allowable load is found by substituting this limit and the appropriate datasheet
values from Table 1 on page 5 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and
Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V.
–3
1.4 10 – 11
C L(MAX) = -------------------------- – 7.5 10
F
Equation 3.
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–3
1.4 10 – 10
C L(MAX) = -------------------------- – 3.7 10
F
Equation 4.
Equation 1 and Equation 2 are graphed in Figure 32 where the points along the load line represent the package
dissipation-limited value of CL for the corresponding switching frequency.
1 6 ,0 0 0
1 4 ,0 0 0 0 . 5 A D r i ve r ( p F )
4 A D r ive r ( p F )
1 2 ,0 0 0
1 0 ,0 0 0
Max Load (pF)
8 ,0 0 0
Ta = 25 °C
6 ,0 0 0
4 ,0 0 0
2 ,0 0 0
0
100
150
200
250
300
350
400
450
500
550
600
650
700
F re q u e n c y (K h z )
20
VDDA Supply Current (mA)
CL = 1000pF
15
10 CL = 500pF
CL = 200pF
5
VDD=15V, 25°C
0
0 200 400 600 800 1000
Switching Frequency (kHz)
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3.6. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si824x VDD lines. Care must be taken to
minimize parasitic inductance in these paths by locating the Si824x as close to the device it is driving as possible.
In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and
ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for
power devices and small signal components provides the best overall noise performance.
3.7. Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 34, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low
when input side power supply (VDDI) is not present.
3.7.1. Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period
tSTART. Following this, the outputs follow the states of inputs VIA and VIB.
3.7.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. The input (control) side, Driver A and Driver B, each have
their own undervoltage lockout monitors.
The Si824x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver
outputs, VOA and VOB, remain low when the input side of the Si824x is in UVLO and their respective VDD supply
(VDDA, VDDB) is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA
unconditionally enters UVLO when VDDA falls below VDDAUV– and exits UVLO when VDDA rises above
VDDAUV+.
UVLO+
VDD HY S
UVLO-
VDDI
UVLO+
VDD H YS
UVLO-
VDDA
PW M
DISABLE
tSD tSD tRESTART tPHL tPLH
tSTART tSTART tSTART
VO A
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3.7.3. Undervoltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 35
and 36, upon power up, the Si824x is maintained in UVLO until VDD rises above VDDUV+. During power down, the
Si824x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+ – VDDHYS).
6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5
Supply Voltage (V DD - V SS ) (V) Supply Voltage (V DD - VSS ) (V)
Figure 35. Si824x UVLO Response (8 V) Figure 36. Si824x UVLO Response (10 V)
3.7.4. Control Inputs
PWM inputs are high-true, TTL level-compatible logic inputs. VOA is high and VOB is low when the PWM input is
high, and VOA is low and VOB is high when the PWM input is low.
3.7.5. Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of input.
Device operation terminates within tSD after DISABLE = VIH and resumes within tRESTART after DISABLE = VIL.
The DISABLE input has no effect if VDDI is below its UVLO level (i.e. VOA, VOB remain low). The DISABLE input
is typically connected to external protection circuitry to unconditionally halt driver operation in the event of a fault.
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3.8. Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si8241/4) include programmable overlap protection to prevent outputs VOA and
VOB from being high at the same time. These devices also include programmable dead time, which adds a user-
programmable delay between transitions of VOA and VOB. When enabled, dead time is present on all transitions,
even after overlap recovery. The amount of dead time delay (DT) is programmed by a single resistor (RDT)
connected from the DT input to ground per Equation 5. Minimum dead time (approximately 400 ps) can be
achieved by connecting the DT pin to VDDI. Note that dead time accuracy is limited by the resistor’s (RDT)
tolerance and temperature coefficient. See Figures 37 and 38 for additional information about dead time operation.
DT 10 RDT
where:
DT = dead time (ns)
and
RDT = dead time programming resistor (k
Equation 5.
1000 100
900 90 RDT = 10k
800 80
700 70 RDT = 6k
Dead-time (ns)
Dead-time (ns)
600 60 RDT = 5k
500 50
RDT = 4k
400 40
300 RDT = 3k
30
200 20 RDT = 2k
100 10 RDT = 1k
0 RDT = 0
0
0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 120
:)
Dead-time Resistance (k: Temperature (°C)
Figure 37. Dead Time vs.Resistance (RDT) Figure 38. Dead Time vs.Temperature
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Si824x
4. Applications
The following examples illustrate typical circuit configurations using the Si824x.
4.1. Class D Digital Audio Driver
Figures 39 and 40 show the Si8241/4 controlled by a single PWM signal. Supply can be unipolar (0 to 1500 V) or
bipolar (± 750 V).
VDD2 D1
VDDI
C2
VDDI 1 µF
C1
1500 V max
1uF
GNDI VDDA
CB
PWMOUT PWM Q1
VOA
DT GNDA
CONTROLLER RDT
Si8241/4
VDDB
VDDB
C3
10uF
I/O DISABLE
GNDB
Q2
VOB
VDD2 D1
VDDI
C2
VDDI 1 µF
C1
+750 V max
1uF
GNDI VDDA
CB
PWMOUT PWM Q1
VOA
DT GNDA
CONTROLLER
RDT
Si8241/4
VDDB
VDDB
C3
10uF
I/O DISABLE
GNDB
Q2
VOB
-750 V max
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Si 824x
5. Pin Descriptions
SOIC-16 (Narrow)
PWM 1 16 VDDA
NC 2 15 VOA
VDDI 3 14 GNDA
GNDI 4 13 NC
Si8241/44
DISABLE 5 12 NC
DT 6 11 VDDB
NC 7 10 VOB
VDDI 8 9 GNDB
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Si824x
6. Ordering Guide
The currently available OPNs are listed in Table 12.
Isolation
Ordering Part Drive UVLO Rating
Input Type Package Output
Number (OPN) Strength Voltage (Input to
Output)
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Si 824x
7. Package Outline: 16-Pin Narrow Body SOIC
Figure 41 illustrates the package details for the Si824x in a 16-pin narrow-body SOIC (SO-16). Table 13 lists the
values for the dimensions shown in the illustration.
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Si824x
8. Land Pattern: 16-Pin Narrow Body SOIC
Figure 42 illustrates the recommended land pattern details for the Si824x in a 16-pin narrow-body SOIC. Table 14
lists the values for the dimensions shown in the illustration.
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Si 824x
9. Top Marking: 16-Pin Narrow Body SOIC
9.1. Si824x Top Marking (16-Pin Narrow Body SOIC)
Si824YUV
e4 YYWWTTTTTT
9.2. Top Marking Explanation (16-Pin Narrow Body SOIC)
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Si824x
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Deleted Table 3.
Added Tables 2 through 7.
Added Figure 5.
Updated common-mode transient immunity
specification throughout.
Revision 0.2 to Revision 0.3
Updated Figures 2 and 3 on page 7.
Added Figure 4 on page 8.
Updated Table 12 on page 25.
Revision 0.3 to Revision 1.0
Updated Table 12, Ordering Part Numbers.
Added Revision D Ordering Part Numbers.
Removed all Ordering Part Numbers of previous
revisions.
Removed moisture sensitivity level table notes.
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Connecting Everyone
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