SC1XHW v15

IPC@CHIP SC11/SC12/SC13
Hardware Manual V1.5 [01.04.2004]
Hardware Manual
IPC@CHIP Embedded Controller Family
SC11/SC12/SC13
High Performance, 80186- and 80188-Compatible,

16-Bit Embedded Microcontroller
Single Chip PC with Flash, RAM, Watchdog
Ordering No. IPC @CHIP

Embedded Controller SC11: 538428
©2000-2004 BECK IPC GmbH Page 1 of 34

Table of Contents
1. BASIC SPECIFICATIONS ........................................................................................................3
2. PHYSICAL DIMENSIONS.........................................................................................................5
3. PIN CONFIGURATION .............................................................................................................7
4. PIN FUNCTIONS ......................................................................................................................8
4.1 Address / Data bus.......................................................................................................8
4.2 Programmable I/O Pins ................................................................................................9
4.3 Programmable Chip Selects ......................................................................................10
4.4 Interrupts ....................................................................................................................10
4.5 Timer ..........................................................................................................................11
4.6 10/100Base-T Interface..............................................................................................11
4.7 Asynchronous Serial Ports.........................................................................................12
4.8 DMA............................................................................................................................12
4.9 Reset, Power Fail Generator......................................................................................13
4.10 NMI-reset-traffic LED sequence SC12.......................................................................14
4.11 NMI-reset-traffic LED sequence SC13.......................................................................15
4.12 Startup Pin configuration ............................................................................................16
5. MUTUAL EXCLUSIVE FUNCTIONS ......................................................................................17
6. ETHERNET 10/100BASE-T....................................................................................................18
6.1 10Base-T Media Filter Placement and Termination for SC12 ...................................18
6.2 Magnetics approved for use for 10Base-T application...............................................18
6.3 Routing and placement rules for SC13 and Ethernet components............................19
6.4 Suggested Magnetics.................................................................................................19
7. SYSTEM OVERVIEW .............................................................................................................20
7.1 Memory map ..............................................................................................................20
7.2 System interrupts .......................................................................................................21
7.3 Watchdog ...................................................................................................................21
8. CHARACTERISTICS ..............................................................................................................22
8.1 ABSOLUTE MAXIMUM RATINGS.............................................................................22
8.2 OPERATING RANGES ..............................................................................................22
8.3 DC-CHARACTERISTICS ...........................................................................................23
8.3.1 SC12 DC-Characteristics ...........................................................................................23
8.3.2 SC13/SC11 DC-Characteristics .................................................................................23
8.4 AC-CHARACTERISTICS ...........................................................................................24
8.4.1 SC12-Read Cycle.......................................................................................................24
8.4.2 SC12-Write Cycle.......................................................................................................25
8.4.3 SC13/SC11 Read Cycle.............................................................................................26
8.4.4 SC13/SC11 Write Cycle .............................................................................................27
9. APPLICATION EXAMPLES ....................................................................................................28
9.1 NMI / Reset-in / Link-LED ..........................................................................................28
9.2 Link-LED / Reset ........................................................................................................29
9.3 256x 8bit I/O-Extension using 74HCT573/245...........................................................29
9.4 Connect 10Base-T Ethernet to the SC12...................................................................30
9.5 Connect 10/100Base-T Ethernet to the SC13 ...........................................................31
9.6 I²C-Bus Example ........................................................................................................32
9.7 SPI-Bus Example .......................................................................................................32
9.8 Other Examples..........................................................................................................32
10. CHANGE LIST ........................................................................................................................33
11. CONTACT ...............................................................................................................................34

1. BASIC SPECIFICATIONS
@CHIP CPU RAM FLASH Ethernet

SC11 BECK 186 40MHz 512 Kbytes 512 Kbytes -
SC12 AMD 186ED 20MHz 512 Kbytes 512 Kbytes 10Base-T
SC13 BECK 186 40MHz 512 Kbytes 512 Kbytes 10/100Base-T
IPC@CHIP® family 80186- and 80188-compatible microcontroller with up to 512KB RAM, 512KB
Flash and Ethernet on Chip
- Lower system cost with higher performance
High performance
- up to 40MHz operating frequency
- 1 Mbyte internal memory space
- 6 x 256-byte I/O space
- Low-power CMOS process with single 5V power supply
Enhanced integrated peripherals

- Up to 14 programmable I/O (PIO) pins
- Two full-featured asynchronous serial ports allow full-duplex, 7-bit or 8-bit data transfers, Serial port
hardware handshaking with CTS and RTS selectable for each port
Independent serial port baud rate generators
DMA to and from the serial ports
- Ethernet controller IEEE 802.3 10Base-T/100Base-TX1
Autonegotiation : 10/100, Full/Half Duplex2
- Watchdog timer
- Pulse-width demodulation option
Familiar 80C186 peripherals

- Two independent DMA channels
- Programmable interrupt controller with up to six external interrupts
- Two programmable 16-bit timers, interrupt capable
- Programmable memory and peripheral chip-select logic
Software-compatible with the 80C186 and 80C188 microcontrollers with widely available native
development tools, applications, and system software
Pre-installed Real Time Operating System (@CHIP RTOS)
Available in the following packages:

- 32-pin, plastic pack (DIL32)
The Beck IPC@CHIP® family of System on Chip microcontrollers and microprocessors is based on
the x86 architecture. The IPC@CHIP family microcontroller is the ideal solution for new designs
requiring Ethernet TCP/IP communication over twisted pair and/or through the serial port. The
compatibility with the 80C186/188 family makes it also an ideal upgrade for systems based upon this
processor range but requiring increased performance, serial communications, Ethernet
communications, a direct bus interface, or more than 64K of memory.
The IPC@CHIP family microcontrollers integrate up to 512Kbyte RAM with increased performance
and up to 512Kbyte FLASH, reducing memory subsystem costs.
The minimum endurance of the Flash memory is 10,000 cycles (depending on environmental stress
e.g. temperature).
1
10/100BASE-T only for SC13
2
Autonegotiation only for SC13

The IPC@CHIP family microcontrollers also integrate the functions of the CPU, multiplexed address
bus, three timers, watchdog timer, chip selects, interrupt controller, two DMA controllers, two
asynchronous serial ports, and programmable I/O (PIO) pins on one chip.
It also supports I²C-Bus and SPI (Serial Peripheral Interface) at any PIO pins via software emulation.
The IPC@CHIP microcontroller is a highly integrated design that provides all Media Access Control
(MAC) and Encode-Decode (ENDEC) functions in accordance with the IEEE 802.3 standard. Network
interfaces including 10/100Base-T via the Twisted-pair. The integrated 10/100Base-T transceiver
makes IPC@CHIP more cost-effective.
Compared to the 80C186/188 microcontrollers, the IPC@CHIP family microcontrollers
enable designers to reduce the size, power consumption, and cost of embedded systems, while
increasing reliability, functionality and performance.
The IPC@CHIP family microcontrollers have been designed to meet the most common requirements
of embedded products developed for the communications, office automation, mass storage, and
general embedded markets. Specific applications including industrial controls, data collection, protocol
conversion, process monitoring and internet connectivity.
IPC@CHIP family microcontroller block diagram
8 Bit Address-/Databus
Oscillator CPU AD[0..7], ALE
80186 A[0..2], RD#, WR#
INT[0,2..6], INTA#
10/100BASE-T
Ethernet Ethernet
TPTX+, TPTX-
MAC PHY*
TPRX+, TPRX-
Traffic LED
Flash UART TxD[0..1], RxD[0..1]

512Kx8 CTS[0..1], RTS[0..1]
RAM DMA DRQ[0..1]

512Kx8
Programmable I/O
PIO[0..13]
WATCH CORE PCS[0..3, 5..6]
DOG LOGIC TMRIN[0..1]
TMROUT[0..1]
RESET#, NMI
Picture 1.1: Access to hardware components via API functions.
* SC12 and SC13 only

2. PHYSICAL DIMENSIONS
The package is physically identical for SC11, SC12 and SC13.
Picture 2.1: IPC@CHIP physical dimensions

3. Design and handling guidlines
The IPC@CHIP should be used together with a DIL32 socket.
Electrostatic Sensitive Device

4. PIN CONFIGURATION
PIO7 / RXD0 1 32 VCC

PIO8 / TXD0 2 31 DRQ1 / INT6 / PIO0
PIO9 / CTS0 3 30 DRQ0 / INT5 / PIO1
PIO10 / RTS0 4 29 A2 / PCS6# / PIO2
PIO11 / TXD1 5 28 A1 / PCS5# / TMRIN1 / TMROUT1 / PIO3
PIO12 / INT3 / RXD1 6 IPC@CHIP 27 A0 / PCS1# / TMRIN0 / PIO4
PIO13 / INT0 / TMROUT0 7 26 RTS1 / PCS3# / INT4 / PIO5
AD0 8 25 CTS1 / PCS2# / INT2 / PWD / INTA# / PIO6
AD1 9 24 ALE / PCS0#
AD2 10 23 WR#
AD3 11 22 RD#
AD4 12 21 TPRX-
AD5 13 20 TPRX+
AD6 14 19 TPTX-
AD7 15 18 TPTX+
3 4
GND 16 17 RESET# / NMI / (TRAFFIC_LED) / (LINK)
Picture 4.1: IPC@CHIP pin configuration
Note: Locate decoupling capacitors as close to VCC Pin as physically possible.
3
Traffic only SC12 and SC13
4
Link status only SC12

5. PIN FUNCTIONS
Pin Terminology
The following terms are used to describe the pins:
Input (I) - An input-only pin.
Input (IS) - An input-only pin with Schmitt Trigger.
Output (O) - An output-only pin.
Input/Output (I/O) - A pin that can be either input or output.
5.1 Address / Data bus
Pin Name Type Function

A[0..2] O Address Bus (output, three-state)
These pins supply nonmultiplexed memory or I/O addresses to the system.
During a bus hold or reset condition, the address bus is in a high-
impedance state.
A0–A2 will serve as the nonmultiplexed address bus for external
peripherals. A0-A2 covers an address range of 8 Bytes max.
AD[0..7] I/O Multiplexed Address and Data Bus (input/output, three-state, level-
sensitive)
These time-multiplexed pins supply partial memory or I/O addresses, as
well as data, to the system. This bus supplies the low-order 8 bits of an
address to the system during the first period of a bus cycle (t1), and it
supplies data to the system during the remaining periods of that cycle (t2 ,
t3 , and t4). In 8-bit mode, AD7–AD0 supplies the data for both high and low
bytes.
During a bus hold or reset condition, the address and data bus is in a high-
impedance state.
ALE O Address Latch Enable (output)

This pin indicates to the system that an address appears on the address
and data bus (AD7–AD0). The address is guaranteed to be valid on the
trailing edge of ALE.
ALE is three-stated and held resistively Low during a bus hold condition. In
addition, ALE has a weak internal pulldown resistor that is active during
reset, when it is enabled by software.
RD# O Read Strobe (output, three-state)
This pin indicates to the system that the microcontroller is performing a
memory or I/O read cycle. RD is guaranteed to not be asserted before the
address and data bus is floated during the address-to-data transition. RD
floats during a bus hold condition.
WR# O Write Strobe (output)
This pin indicates to the system that the data on the bus is to be written to a
memory or I/O device. WR floats during a bus hold or reset condition.

5.2 Programmable I/O Pins
Pin Name
Type Function
PIO[0..13] I/O Programmable I/O Pins (input/output, open-drain)
The IPC@CHIP family microcontroller provides 14 individually
programmable I/O pins. Each PIO can be programmed with the
following attributes: PIO function (enabled/disabled), direction
(input/output), and weak pullup or pulldown.
PIO# After power-on reset, the PIO pin Programmable as

defaults to Input with
0 Input without pullup
1 Input without pullup
2 Input with pullup pullup
3 Input with pullup pullup / pulldown
7 RxD0 pullup
8 TxD0 pullup
11 TxD1 pullup
12 RxD1 pullup
13 Input with pulldown pulldown
Internal Pullup and Pulldown is approximately 7-10kOhm.

5.3 Programmable Chip Selects

PCS[0..3] O Peripheral Chip Selects (output)
These pins indicate to the system that an I/O memory access is in
progress to the corresponding region of the peripheral memory.
PCS0–PCS3 are three-stated and held resistively High during a bus
hold condition. In addition, PCS0–PCS3 each have a weak internal
pullup resistor that is active during reset. The PCS outputs assert with
the multiplexed AD address bus. Note also that each peripheral chip
select asserts over a 256-byte address range.
PCS[5..6] O Peripheral Chip Selects (output)
These pins indicate to the system that an I/O memory access is in
progress to the corresponding region of the peripheral memory.
PCS5–PCS6 are three-stated and held resistively High during a bus
hold condition. In addition, PCS5–PCS6 each have a weak internal
pullup resistor that is active during reset. The PCS outputs assert with
the multiplexed AD address bus. Note also that each peripheral chip
select asserts over a 256-byte address range.
5.4 Interrupts

INT[0,2-6] I Maskable Interrupt Request (input)
These pins indicate to the microcontroller that an interrupt request has
occurred. If the INT pin is not masked, the microcontroller transfers program
execution to the location specified by the corresponding INT vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronised internally and can be edge-triggered or
level-triggered. To guarantee interrupt recognition, the requesting device
must continue asserting INT until the request is acknowledged. INT2
becomes INTA# when INT0 is configured in cascade mode.
INTA# O Interrupt Acknowledge (output)
When the microcontroller interrupt control unit is operating in cascade
mode, this pin indicates to the system that the microcontroller needs an
interrupt type to process the interrupt request on INT0. The peripheral
issuing the interrupt request must provide the microcontroller with the
corresponding interrupt type.
PWD IS Pulse Width Demodulator (input, Schmitt trigger)
If pulse width demodulation is enabled, PWD processes the signal through
a Schmitt trigger. PWD is used internally to drive TMRIN0 and INT2, and
PWD is inverted internally to drive TMRIN1 and INT4. If INT2 and INT4 are
enabled and timer 0 and timer 1 are properly configured, the pulse width of
the alternating PWD signal can be calculated by comparing the values in
timer 0 and timer 1.
In PWD mode, the signals TMRIN0, TMRIN1 and INT4 can be used as
PIOs. If they are not used as PIOs, they are ignored internally.

5.5 Timer
Timer can be clocked internally or externally. Maximum frequency is ¼ CPU clock. If the timer will be
clocked internally the timer out pin (TMROUT) may be used. External clock at Input and output at the
same time with same timer is not possible.

TMRIN[0..1] I Timer Input (input, edge-sensitive)
These pins supply a clock or control signal to the internal microcontroller
timer 0 and 1. After internally synchronising a Low-to-High transition on
TMRIN, the microcontroller increments the corresponding timer. TMRIN
must be tied High if not being used. When PIO is enabled, TMRIN is pulled
High internally.
TMRIN0 is driven internally by INT2/PWD when pulse width demodulation
mode is enabled. The TMRIN0 pin can be used as a PIO when pulse width
demodulation mode is enabled.
TMROUT[0..1] O Timer Output (output)
These pins supply the system with either a single pulse or a continuous
waveform with a programmable duty cycle.
5.6 10/100Base-T Interface

TPTX[+,-] O Twisted Pair Driver (outputs)
TPRX[+,-] I Twisted Pair Receive (inputs).
TRAFFIC LED O Traffic LED Driver (output)
(LINK LED)5 This pin indicates network traffic by sinking voltage to 3V. It is generated
through an open-collector low mode for a short impulse to indicate the
presence of traffic on the network. Note that this pin is not able to source
any current!
5
Link status only SC12

5.7 Asynchronous Serial Ports
All asynchronous port pins are TTL level. To provide RS232 or RS485 level external drivers must be
connected (like MAX232). The following modes can be provided:
Full-Duplex Operation with 7-bit or 8-bit, odd, even or no parity. Error detection is possible with parity
errors, framing errors, overrun errors and break character recognition. Hardware handshaking (Clear-
to-send CTS and Request-to-send RTS) is possible.
To get a definite baud rate, a baud rate divider must be provided. A general formula for the baud rate
divisor is: BAUDDIV = (CPU clock / (16 x Baud Rate)). We recommend to using the RTOS function
“Get Frequencies”.
The maximum baud rate is achieved by setting BAUDDIV=0001h. This results in a baud rate of
1250Kbit for SC12 and 2500 Kbit for SC11/SC13. A BAUDDIV setting of zero results in no
transmission or reception of data.
The serial port receiver tolerance depends on the used settings:
SC11/SC13 SC12
9 Bits ± 3.47% + 3.0%
10 Bits ± 3.125% - 2.5%
11 Bits ± 2.84%
The two ports can operate at different rates.

TxD[0..1] O Transmit Data (output)
These pins supply asynchronous serial transmit data to the system from
serial port 0 and 1.
RxD[0..1] I Receive Data (input)
These pins supply asynchronous serial receive data from the system to
asynchronous serial ports 0 and 1.
CTS[0..1] I Clear-to-Send (input)
These pins provide the Clear-to-Send signal for asynchronous serial port 0
and 1 when hardware flow control is enabled for the port. The CTS signals
gate the transmission of data from the associated serial port transmit
register. When CTS is asserted, the transmitter begins transmission of a
frame of data, if any is available. If CTS is deasserted, the transmitter holds
the data in the serial port transmit register. The value of CTS is checked
only at the beginning of the transmission of the frame.
RTS[0..1] O Request-to-Send 0 (output)
These pins provide the Request-to-Send signal for asynchronous serial
ports 0 and 1 when hardware flow control is enabled for the port. The RTS
signals are asserted when the associated serial port transmit register
contains data that has not been transmitted.
5.8 DMA

DRQ[0..1] I DMA Request (input, level-sensitive)
These pins indicate to the microcontroller that an external device is ready
for DMA channel 0 or 1 to perform a transfer. DRQ is level-triggered and
internally synchronised. DRQ is not latched and must remain active until
serviced.

5.9 Reset, Power Fail Generator
Note that RESET# pin shares 3(4) functions: RESET and NMI as described here, as well as network
traffic (and link status for SC12) as described in the corresponding chapters.
This is a voltage-multiplexed pin that internally sinks current in the case of a ethernet packet
send/receive. All peripheral logic asserted to this pin must be open-collector to prevent the internal
logic from sinking too high current. The pin is already provided with an internal pullup resistor.
Rpullup
SC11 4.7 kOhm
SC12 1 kOhm
SC13 4.7 kOhm

RESET# I Reset (input/level-sensitive)
If voltage on this pin goes below 0.8V the microcontroller will perform a reset.
In that case the microcontroller immediately terminates its present activity,
clears its internal logic, and transfers CPU control to the reset address.
NMI I Nonmaskable Interrupt (input, level-sensitive)
If voltage on this pin goes down below VNMIRT (see DC CHARACTERISTICS)
it indicates to the microcontroller that an interrupt request has occurred. The
NMI signal is the highest priority hardware interrupt and, unlike the INT6–INT0
pins, cannot be masked. The microcontroller always transfers program
execution to the location specified by the nonmaskable interrupt vector in the
microcontroller interrupt vector table when NMI is asserted.
The NMI is for detecting low supply power and the following data backup only.
A reset has to follow after the NMI. To guarantee that the interrupt is
recognised, the NMI condition must be asserted to the pin until reset.
The following schematic delivers a principle insight of pin 17.
IPC@CHIP
VCC
Rpullup
17

5.10 NMI reset traffic LED sequence SC12
VCC
V
5
5V
4.7 V 4.65 V
4
tPower tREM = Time to save the retentive data tREM
e. g. 1 kByte = 120ms
3 2 kByte = 200ms
Retentive data must be one block.
If it is not, it takes more time to save.
2 tPower OK = max. 200ms
200 400 600 800 1000 1200 1400 1600 t on / off

ms
Pin17
V
50ms traffic impulses
5
4
Link tREM
3,0 V Link
3 NMI
80ms pause
2
VNMIRTMin
VNMIRTMax
1
0.8 V 0.8 V
Reset
200 400 600 800 1000 1200 1400 1600 t on / off

ms
To implement time to save the retentive data keep Pin 17 at VNMIRT6 and VCC at 5V for tREM with
external capacitors. If Pin 17 goes below 0.8V IPC@CHIP will be in reset state.
6
see DC-Characteristics

5.11 NMI reset traffic LED sequence SC13
VCC
V
5 5V
4.7 4.65 V
4 tPower tREM = Time to save the retentive data tREM
e. g. 1 kByte ≈ 120ms
2 kByte ≈ 200ms
3 Retentive data must be one Block.
If it is not, it takes more time to save.
tPower OK = max. 200ms
2
200 400 600 800 1000 1200 1400 1600 t on / off

ms
Pin17
V
4
tREM
3.0 V
3 80-105ms traffic pulses
VNMIRTMin
2 NMI VNMIRTMax
1 0.8 V 0.8 V
Reset
200 400 600 800 1000 1200 1400 1600 t on / off

ms
To implement time to save the retentive data keep Pin 17 at VNMIRT7 and VCC at 5V for tREM with
external capacitors. If Pin 17 goes below 0.8V IPC@CHIP will be in reset state.
7
see DC Characteristics

5.12 Startup Pin configuration
At turn-on the IPC@Chip I/O pins are configured as follows:

Pin1: RXD0/PIO7 = RXD0
Pin2: TXD0/PIO8 = TXD0
Pin3: CTS0/PIO9 = Input pullup
Pin4: RTS0/PIO10 = Input pullup
Pin5: TXD1/PIO11 = TXD1
Pin6: RXD1/PIO12 = RXD1
Pin7: TMROUT0/INT0/PIO13 = Input pulldown
Pin17: RESET/NMI/TRAFFIC = Input
Pin24: ALE/PCS0 = Output, value 1
Pin25: CTS1/PCS2/PIO6/INT2 = Input pullup
Pin26: RTS1/PCS3/PIO5/INT4 = Input pullup
Pin27: PCS1/PIO4/TMRIN0/A0 = Input pullup
Pin28: PCS5/PIO3/TMROUT1/TMRIN1/A1 = Input pullup
Pin29: PCS6/PIO2/A2 = Input pullup
Pin30: INT5/PIO1 = Input
Pin31: INT6/PIO0 = Input

6. MUTUALLY EXCLUSIVE FUNCTIONS
The IPC@CHIP family microcontroller provides a lot of different functions by several multi-function
pins. Choosing one function will result in disabling other functions. The following table shows, which
functions are mutually exclusive.
Pin Name Function Exclusion

A0 nonmultiplexed address A0 PIO4, PCS1#, TMRIN0
A[1..2] nonmultiplexed address A[1..2] PIO[2..3], PCS[5..6], Timer 1
ALE Address / Data bus PCS0#
CTS0 hardware flow control Serial Port 0 PIO9
CTS1 hardware flow control Serial Port 1 PIO6, PCS2#, INT2, INTA#, PWD
DRQ0 DMA Request 0 PIO1, INT5
DRQ1 DMA Request 1 PIO0, INT6
INT0 Interrupt Request 0 PIO13, TMROUT0, cascaded Interrupt Controller
INT2 Interrupt Request 2 PIO6, PCS2#, INTA#, PWD, hardware flow control Serial
Port 1
INT3 Interrupt Request 3 PIO12, Serial Port 1
INT4 Interrupt Request 4 PIO5, PCS3#, SPI, hardware flow control Serial Port 1
INT5 Interrupt Request 5 PIO1, DRQ0
INT6 Interrupt Request 6 PIO0, DRQ1
INTA# cascaded Interrupt Controller PIO6, PIO13, INT0, INT2, PCS2#, PWD, TMROUT0, HW
flow control Serial Port 1
PWD Pulse Width Demodulator PIO6, PCS2, INT2, INT4, TMROUT[0..1], TMRIN[0..1],
INTA#, cascaded Interrupt Controller, HW flow control
Serial Port 1
PCS0# programmable chip select 0 Address/Data bus
PCS1# programmable chip select 1 A0, PIO4, TMRIN0
PCS2# programmable chip select 2 PIO6, INT2, INTA#, PWD, HW flow control Serial Port 1,
cascaded Interrupt Controller
PCS3# programmable chip select 3 PIO5, INT4, hardware flow control Serial Port 1
PCS5# programmable chip select 5 A[1..2], PIO3, Timer 1
PCS6# programmable chip select 6 A[1..2], PIO2
PIO0 Programmable I/O DRQ1, INT6
PIO1 Programmable I/O DRQ0, INT5
PIO2 Programmable I/O A2, PCS6#
PIO3 Programmable I/O A1, PCS5#, Timer 1
PIO4 Programmable I/O A0, PCS1#, TMRIN0
PIO5 Programmable I/O PCS3#, INT4, hardware flow control Serial Port 1
PIO6 Programmable I/O PCS2#, INT2, cascaded Interrupt Controller, PWD, HW
flow control Serial Port 1
PIO7 Programmable I/O Serial Port 0
PIO9 Programmable I/O Hardware flow control Serial Port 0
PIO10 Programmable I/O Hardware flow control Serial Port 0
PIO12 Programmable I/O Serial Port 1, INT3
PIO13 Programmable I/O INT0, cascaded Interrupt Controller, TMROUT0
RxD0, TxD0 Serial Port 0 w/o HW flow control PIO[7..8]
RxD0, TxD0 Serial Port 0 with HW flow control PIO[7..10]
CTS0, RTS0
RxD1, TxD1 Serial Port 1 w/o PIO[11..12], INT3
HW flow control
RxD1, TxD1 Serial Port 1 with HW flow control PIO[5..6,11..12], INT3, PCS[2..3]#, INT2, INT4, PWD,
CTS1, RTS1 cascaded Interrupt Controller

7. ETHERNET 10/100BASE-T
7.1 10Base-T Media Filter Placement and Termination for SC12
Placement of the termination components TPTX+ and TPTX- should be located as physically close to
the media filter as possible.
The media filter should also placed as physically close to the RJ-45 connector as possible to minimise
stray EMI transfer to the media. The trace routing is to keep the area enclosed by a circuit loop as
small as possible to minimise the incidence of magnetic coupling. However this can conflict with the
general rule of keeping trace lengths to a minimum. For example, if circuit components are positions
along the same sides of a square, the best return is back along the same three sides of the square,
NOT directly back along the fourths side. This rule must be strictly adhered to. Furthermore, there
should never be an unnecessary feed-through inside the circuit loop. This also implies that the circuit
loop should never encircle the power/ground planes (i.e. part of the circuit loop above and part of
circuit loop below these planes).
Incorrect Layout Correct Layout
The two traces of the pair should always be routed in adjacent channels and should be of same
length. To reduce capacitive coupling, each circuit loop should be separated from the others. Circuit
loops can be separated either by physical space (if located on the same layer) or by placement of
signal layers on the opposite side of the power/ground planes. The following signal groups should be
isolated from each other. Width of receiver trace should be 25 mil minimum to achieve 50Ohm
impedance characteristic at 10MHz. Width of transmitter trace should be 10 mil minimum to achieve
25Ohm impedance characteristic at 10MHz
To achieve optimum performance the designer must protect the magnetics from the environment. It
should be isolated from the power and ground planes.
7.2 Magnetics approved for use for 10Base-T application
Through-Hole PCB:
BEL FUSE, Inc. part no. 0556-5999-19 (http://www.belfuse.com)

Halo Electronics, Inc. Part no. FS22-101Y4 (http://www.haloelectronics.com)
BECK-IPC GmbH Part no. FS22-101Y4 (online shop ordering number 20003276)
Valor, Inc. part no. FL1012/1066 (http://www.valorinc.com/)
Surface-Mount PCB:
Valor, Inc. part no. SF1012 (http://www.valorinc.com/)

7.3 Routing and placement rules for SC13 and Ethernet components
1. Place the RJ45 connector, the magnetics and the SC13 as close together as possible.
2. If No. 1 is not possible, keep the RJ45 and the magnetics as close as possible. This will allow
remote placement of the SC13.
3. Select and place the magnetics as the best routing scheme from the SC13 to the magnetics to the
RJ45 connector.
4. Place the 49.9Ω TX termination pull-ups (TPTX+/TPTX-, pin 18/19) as close to the magnetics as
possible.
5. Place the two 24.9Ω RX series resistors as close to the magnetics as possible.
6. Place the two 24.9Ω RX termination resistors and the 10 nF capacitor ( TPRX+, pin 20 & TPRX-,
pin 21) as close to the SC13 as possible.
7. Place the 75Ω cable side center tap termination resistors and the 1nF capacitor as close to the
magnetics as possible.
8. Place the Unused Wire Pair termination resistors and the 1nF capacitor as close to the RJ45
connector as possible.
9. The traces connecting the transmit outputs (TPTX+, pin 18) & (TPTX-, pin 19) to the magnetics
must be run as differential pairs. The differential impedance should be 100 ohms.
10. The traces connecting the transmit outputs from the magnetics to pins 1 & 2 on the RJ45
connector must be run as differential pairs. The differential impedance should be 100 ohms.
11. The traces connecting the receive inputs (TPRX+, pin 20) & (TPRX-, pin 21) from the magnetics
12. The traces connecting the receive inputs on the magnetics from pins 3 & 6 on the RJ45 connector
13. Typically, all planes are cleared out from under the differential pairs connecting the RJ45 and the
magnetics. The plane clear out boundary is usually halfway through the magnetics.
14. Trace impedance depends upon many variables (PCB construction, trace width, trace spacing,
etc.). The electrical engineer needs to work with the PCB designer to determine all these
variables.
15. Try to keep all other signals out of the Ethernet front end (RJ45 through the magnetics to the
IPC@CHIP). Any noise from other traces may couple into the Ethernet section and cause
problems.
7.4 Suggested Magnetics
Surface-Mount PCB:
BECK-IPC GmbH Part no. Magnetic FS23 (online shop ordering number: 538431)
Halo Electronics, Inc. Part no.TG110-S050N2 (http://www.haloelectronics.com)
Through-Hole PCB:
BECK-IPC GmbH Part no. Magnetic Module FM23 (online shop ordering number: 538430)

8. SYSTEM OVERVIEW
8.1 Memory map
IPC@CHIP Memory I/0 map
FFFFFh Bootloader FFFFh

FEFFFh Reserved
0700h
Flash Disk 06FFh
PCS6#
XXXXXh* 0600h
XXXXXh* 05FFh
PCS5#
@CHIP RTOS 0500h
04FFh
80400h Reserved
80000h Reserved 0400h
7FFFFh 03FFh
PCS3#
0300h
02FFh
PCS2#
Working Memory 0200h
512Kbyte RAM 01FFh
PCS1#
0100h
00FFh
PCS0#
00000h 0000h
picture 8.1: IPC@CHIP memory map
* depends on the CHIP-RTOS version, see “Scaled @Chip-RTOS versions” in @CHIP-RTOS API
Documentation

8.2 System interrupts
Source Sensitivity
INT0 (external) Edge / Level
Network controller (internal)
INT5 (external) / DMA Interrupt Channel 0 (if DMA is used) Edge
INT6 (external) / DMA Interrupt Channel 1 (if DMA is used) Edge
Reserved
Timer0 (internal)
Timer1 (internal)
Timer 1ms (internal) (*)
Serial port 0 (internal) (*)
Serial port 1 (internal) (*)
NMI (internal/external)
(*) Internal used by @CHIP-RTOS, not available for user

interrupt service functions
When an interrupt occurs all interrupts are disabled until the interrupts are released by setting IF Flag
in the interrupt service routine. Interrupts of the same source are masked until the corresponding Bit in
interrupt service register is cleared.
Level sensitive interrupts are triggered by a high level, edge sensitive interrupts by the rising edge.
8.3 Watchdog
The IPC@CHIP provides a true watchdog timer function. The watchdog can be used to regain control
of the system when software fails to respond as expected. The watchdog is active after reset. The
watchdog timeout period is about 838 ms. The mode can set to trigger the watchdog by the user
program or by the CHIP-RTOS (default). In CHIP-RTOS mode, the CHIP-RTOS performs the
watchdog strobing provided that the system's timer interrupt is allowed to execute. Beware that
excessive interrupt masking periods can lead to system resets.

9. CHARACTERISTICS
9.1 ABSOLUTE MAXIMUM RATINGS
SC11 SC12 SC13

Storage temperature -25°C to +100°C -25°C to +100°C -25°C to +100°C
Supply voltage (VCC) -0.3V to +6.0V -0.3V to +6.0V -0.3V to +6.0V
Supply current (VCC = 5.25V) 240mA 220 mA 400 mA
Voltage on any pin with -0.3V to VCC + 0.3V -0.3V to VCC + 0.3V -0.3V to VCC + 0.3V
respect to ground
9.2 OPERATING RANGES
SC11 SC12 SC13

Operating temperature 0°C to +70°C 0°C to +70°C 0°C to +70°C
(Ambient TA)
Supply voltage (VCC) 5.0V +/- 5% 5.0V +/- 5% 5.0V +/- 5%
Typical power supply current 180mA 180mA 300mA
(at VCC)
Note: Exposure to conditions beyond those listed here may adversely affect the lifetime and reliability
of the device.

9.3 DC CHARACTERISTICS
(Under operating ranges unless otherwise noted)
9.3.1 SC12 DC Characteristics
Symbol Parameter Description Test Condition MIN. TYP. MAX. Unit

ICC Current into VCC 180 220 mA
VOL Voltage Output Low IOL = 2.0mA - 0.45 V
VOH Voltage Output High IOH = -0.4mA 2.4 - V
VILO Voltage Input Low - - 0.8 V
VIHI Voltage Input High - 2.0 - V
VRT Reset Threshold 4.5 4.65 4.75 V
Reset Threshold Hysteresis 0.04 V
VRESLO IN Voltage Reset active 0 0.8 V
VRESOL OUT Voltage Reset Low IOL = -9mA 0.8 V
VNMIRT NMI Threshold VCC = 5V 1.3 1.5 V
Clout External Load on AD[0..7], RD#, WR# 20 PF
External Load on the other pins 30 PF
Clin Input Capacitance 30 PF
RPIO Internal Pullup/-down Resistor 10K Ω
9.3.2 SC13/SC11 DC Characteristics
Symbol Parameter Description Test Condition MIN. TYP. MAX. Unit

ICC Current into VCC SC11 180 220 mA
ICC Current into VCC SC13 300 400 mA
VOL Voltage Output Low IOL = 4.0mA - 1.5 V
VOH Voltage Output High IOH = -4.0mA 3.5 - V
VILO Voltage Input Low - - 1.5 V
VIHI Voltage Input High - 3.5 - V
VRT Reset Threshold 4.5 4.65 4.75 V
Reset Threshold Hysteresis 0.04 V
VRESLO IN Voltage Reset active 0 0.8 V
VRESOL OUT Voltage Reset Low IOL = -4mA 0.8 V
VNMIRT NMI Threshold VCC = 5V 1.3 1.8 V
Clout External Load on AD[0..7], RD#, WR# 20 PF
External Load on the other pins 30 PF
Clin Input Capacitance 30 PF
RPIO Internal Pullup/-down Resistor 7K 10K Ω

9.4 AC CHARACTERISTICS
(Under operating ranges unless otherwise noted)
9.4.1 SC12-Read Cycle
TA = 25°C
No. Symbol Description Min Max Unit

General Timing Requirements
1a tRLDV Read Valid to Data Valid (PCS0#..PCS3#) 65 65 + X(1) ns
1b tRLDV Read Valid to Data Valid (PCS5#, PCS6#) 215 ns
59 tRHDX Read Inactive to Data Hold on AD Bus 0 ns
General Timing Responses
10 tLHLL ALE Width 40 ns
12 tAVLL AD Address Valid to ALE Low 23 ns
13 tLLAX AD Address Hold from ALE Inactive 23 ns
17 tCXCSX PCSx# Hold from Read Inactive 23 ns
23 tLHAV ALE High to Address Valid 20 ns
99 tPLAL PCSx# Active to ALE Inactive 15 28 ns
Read Cycle Timing Responses
24 tAZRL AD Address Float to Read Active 0 ns
26a tRLRH Read Pulse Width (PCS0#..PCS3#) 85 + X(1) ns
26b tRLRH Read Pulse Width (PCS5#, PCS6#) 235 ns
28 tRHLH Read Inactive to ALE High 22 ns
29 tRHAV Read Inactive to AD Address Active 40 ns
(1)
X depends on wait states of PCS0#..PCS3# and can be 0..750ns (see @CHIP-RTOS Doc.)
29
23 13 1 59
AD0..AD7 Address Data
12
10
99 28
ALE
24
26
RD#
17
PCSx#
*) the falling edge of PCS0# is 50ns delayed internally

9.4.2 SC12 Write Cycle
TA = 25°C

17 TCXCSX PCSx# Hold from Read Inactive 23 ns
23 TLHAV ALE High to Address Valid 20 ns
99 TPLAL PCSx# Active to ALE Inactive 15 28 ns
Write Cycle Timing Responses
32a TWLWH Write Pulse Width (PCS0#..PCS3#) 90 + X(1) ns
32b TWLWH Write Pulse Width (PCS5#, PCS6#) 240 ns
33 TWHLH Write Inactive to ALE High 23 ns
34 TWHDX Data Hold after Write Inactive 40 ns
(1)
X depends on wait states of PCS0#..PCS3# and can be 0..750ns (see @CHIP-RTOS Doc.)
23 13 34
12
10
99 33
ALE
32
WR#
17
PCSx#

9.4.3 SC13/SC11 Read Cycle
TA = 25°C

General Timing Requirements
1a tRLDV Read Valid to Data Valid (PCS0#..PCS3#) 12 12 + X(1) ns
1b tRLDV Read Valid to Data Valid (PCS5#, PCS6#) 12 12 + X(1) ns
59 tRHDX Read Inactive to Data Hold on AD Bus 0 ns
17 tCXCSX PCSx# Hold from Command Inactive 20 ns
Read Cycle Timing Responses
24 tAZRL AD Address Float to Read Active 0 ns
26a tRLRH Read Pulse Width (PCS0#..PCS3#) 20 + X(1) ns
26b tRLRH Read Pulse Width (PCS5#, PCS6#) 20 + X(1) ns
28 tRHLH Read Inactive to ALE High 10 ns
29 tRHAV Read Inactive to AD Address Active 20 ns
(1)
X depends on wait states and can be 0.. 6375ns. (see @CHIP-RTOS Doc)
29
23 13 1 59
12
10
99 28
ALE
24
26
RD#
17
PCSx#

9.4.4 SC13/SC11 Write Cycle
TA = 25°C

17 tCXCSX PCSx# Hold from Command Inactive 20 ns
Write Cycle Timing Responses
32a TWLWH Write Pulse Width (PCS0#..PCS3#) 20 + X(1) ns
32b TWLWH Write Pulse Width (PCS5#, PCS6#) 20 + X(1) ns
33 TWHLH Write Inactive to ALE High 10 ns
34 TWHDX Data Hold after Write Inactive 15 ns
(1)
X depends on waitstates and can be 0.. 6375ns. (see @CHIP-RTOS Doc)
23 13 34
12
10
99 33
ALE
32
WR#
17
PCSx#

10. APPLICATION EXAMPLES
The following pages contain schematics showing the IPC@CHIP family microcontroller. It gives you
suggestions, how to handle the multi-function pin 17 RESET# / NMI / LINK-LED and how
to expand the IPC@CHIP.
10.1 NMI / Reset-in / Link-LED
External sample circuitry /Reset + NMI + Link LED

* R147 is for understanding the circuitry only. The IPC@CHIP has
already build in pullup resistor.
VCC IPC@CHIP
* 17 RESET_PFAIL_LILED
680R
4k7
R147
R10
LED1
LED3mm 3
Link U17
7
+
390R 1 VCC
C11
6 3.32V 12GND
-
1% !
R12 LM339
27k
R197
IC45A 4 -
330R
12
470p
R188
D39 GND 2 LED2

24V 5 + LED3mm
2,5V LM339 Power
1% !
IC45B
R198
LL4148
100k
10k
GND VCC
3 3 VCC
R182
12
R9
The LM339 limits U17 to

390R
9 approx. 4V
+
10 - 14
13 8 - Q8
0.1uF
K 11 + LM339 BC817-25L_1
C11
LM339 IC45C
12 22k
3 IC45D GND
20k
C64 3
R11
R187 IC8
LM385-2,5
RD 0.1uF R199 1 4
1 3 4 RESET# GND 2 NC Y
A 22k IN
GND GND GND GND VCC IC10B NC7S14P5X
74HCT14
*) LM339 is an open collector operational amplifier
8
Picture 10.1: Example of using NMI, reset, traffic, (link ) at pin 17
See also DK50 schematic.
8
only SC12

10.2 Link-LED / Reset
IPC@CHIP
Vcc Vcc
3,5..4V
Rpullup
-
17
GND GND
<0,8V RESET =
GND 4..9mA
(static)
GND
GND
Picture 10.2: Link/traffic-LED / reset example
10.3 256x 8bit I/O Extension using 74HCT573/245
U4 U3 74HC573
18 VC GN 8 2 19 A0
19 TPTX+ C D AD0 9 3 1D 1Q 18 A1
20 TPTX- AD1 10 4 2D 2Q 17 A2
21 TPRX+ AD2 11 5 3D 3Q 16 A3
TPRX- AD3 12 6 4D 4Q 15 A4
1 AD4 13 7 5D 5Q 14 A5
2 RXD0 PIO7 AD5 14 8 6D 6Q 13 A6
3 TXD0 PIO8 AD6 15 9 7D 7Q 12 A7
4 CTS0 PIO9 AD7 8D 8Q
RTS0 PIO10 24 11
5 ALE 22 1 LE
6 TXD1 PIO11 /RD 23 OE
25 RXD1 PIO12 INT3 /WR GND
26 CTS1 PIO6 INT2 /PCS2 31
RTS1 PIO5 INT4 /PCS3 PIO0 INT6 DRQ1 30
PIO1 INT5 DRQ0 29 U1
A2 PIO2 /PCS6 28 2 18 D0
A1 PIO3 TMRIN1 TMROUT1 /PCS5 27 3 A1 B1 17 D1
A0 PIO4 TMRIN0 /PCS1 7 4 A2 B2 16 D2
17 PIO13 INT0 TMROUT0 5 A3 B3 15 D3
/RESET NMI LinkLED 6 A4 B4 14 D4
7 A5 B5 13 D5
IPC@CHIP 8 A6 B6 12 D6
9 A7 B7 11 D7
A8 B8
/PCS1 19
/RD 1 G
DIR
74HC245
/PCS1
/RD
/WR
Picture 10.3: Example of a demultiplexed 8 bit A/D-Bus.

10.4 Connect 10Base-T Ethernet to the SC12
IC1
20 1 IPC@CHIP SC12
NC NC
19 2 18
19 2 TPTX+
18 3
17 18 3 4 19
ST1 17 4 TPTX-
16 5
1 15 NC NC 6
2 NC NC
3 14 7 20
TP 4 13 14 7 8
TPRX+
5 12 13 8 9 21
6 12 9 TPRX-
7 11 10
8 NC NC R1 R2
47R 47R
RJ45 SF1012
VALORSMD
C1 C2
10nF 10nF
GND GND
picture 10.4: Example of connecting 10Base-T to SC12 with SF1012
U1 IPC@CHIP SC12
ST2
1 16 1 18
1 16 1 TPTX+
2 2
2 3 14 2 3 19
10BASET
3 14 3 TPTX-
4
4 5
5 6 11 6 20
6 11 6 TPRX+
7 7
7 8 9 7 8 21
8 9 8 TPRX-
RJ45 FL1066 VALOR
R8
R7
47R
47R
C6 C5
10nF 10nF
GND
GND
picture 10.5: Example of connecting 10Base-T to SC12 with FL1066
FS22-101Y 4 IPC@CHIP SC12

U1
JP1
9 1 18
1 TX+ TPTX+ TPTX+
2 10 2 19
3 TX- TPTX- TPTX-
4 7 3 20
5 RX+ TPRX+ TPRX+
6 8 4 21
SHLD
7 RX- TPRX- TPRX-

8
RJ45
R1
5
47R R2
C1 47R
10n
C2
GND
10n
GND
picture 10.6: Example of connecting 10Base-T to SC12 with FS22

10.5 Connect 10/100Base-T Ethernet to the SC13
SC13 ethernet
Vcc
bl 1
U3
5 +3,3V
Vin Vout
C4 GN 3
22µ + D ON/OFF 4 + C3
C5 N.C. C6 10n / 50V 10%
100n LP2981 100n C7
2 22µ
49, 49, 24, 24,
R3 R49 R59 R69
9
GND
100BASET2
TR1
TX+ 1 16
1 TX- 2 15
2 RX+ 3 14
3
4 4 13
5 RX- 5 12 U4 SC13
6 18 8
7 6 11 R7 19 TPTX+ AD0 9
8 24,9 TPTX- AD1
7 10 20 10
8 9 R8 21 TPRX+ AD2 11
RJ45 24,9 TPRX- AD3 12
1 AD4 13
75, 75, 75, BECK-FS23 2 RXD0 PIO7 AD5 14
75, R1 TXD0 PIO8 AD6
R90 R1 0 R10 3 15
0 1 CTS0 PIO9 AD7
0 2 4
RTS0 PIO10 24
5 ALE 22
C8 6 TXD1 PIO11 /RD 23
1n/2kV 25 RXD1 PIO12 INT3 /WR
26 CTS1 PIO6 INT2 /PCS2 30
GND RTS1 PIO5 INT4 /PCS3 PIO1 INT5 DRQ0 31
17 PIO0 INT6 DRQ1 29
32 /RESET NMI LinkLED A2 PIO2 /PCS6 28
VCC A1 PIO3 TMRIN1 TMROUT1 /PCS5 27
A0 PIO4 TMRIN0 /PCS1 7
16 PIO13 INT0 TMROUT0
GND
picture 10.7: Example of connecting 10/100Base-T to SC13 with FS23
* 5V
U1 FM23 IPC@CH IP SC13

11
JP1
9 1 18
1 TX+ TPTX+ TPTX+
VCC_ PAD
2 10 2 19
3 TX- TPTX- TPTX-
4 7 3 20
5 RX+ TPRX+ TPRX+
6 8 4 21
7 RX- TPRX- TPRX-
8 *
5V
SHLD
RJ45 option al Vcc-input ,

Vcc
intern al connected R1
47R R2
with p in 6
47R
6
C2
C1
10n
10n
GND GND
picture 10.8: Example of connecting 10/100Base-T to SC13 with FM23

(convert SC12 schematic to fit SC13, see also picture 10.6)

10.6 I²C-Bus Example
To use PIO pins for I²C-Bus, connect a 10kΩ resistor to each PIO pin that is defined for I²C-Bus.
The definition of initializing I²C-Bus is described in the @CHIP RTOS documentation.
V cc
IC1
IPC@CHIP
18 32
19 TPTX+ V CC
20 TPTX-
21 TPRX+ 8
TPRX- A D0 9
A D1 10
A D2 11
A D3 12
2 A D4 13
1 TXD0/P8 A D5 14
RXD0/P7 A D6 15
3 A D7
4 CTS0/P9
RTS0/P10
22
RD 23
WR
27
PCS1/P4/TMRIN0/A 0 28
PCS5/P3/TMROUT1/TMRIN1/A 1 29
V cc V cc V cc PCS6/P2/A 2
5 24
IC2 6 TXD1/P11 A LE/PCS0
RXD1/INT3/P12
1 7 R1 R2 25
OSCI INT 10K 10K 26 CTS1/PCS2/P6/INT2/INTA /PWD
Y1 3 RTS1/PCS3/P5/INT4
A0
32768Hz 2 6 31
OSCO SCL 5 30 I2CCLK/DRQ1/INT6/P0
SDA I2CDAT/DRQ0/INT5/P1
17
RESET_PFA IL_LILED
PCF8583 16 7
GND TMROUT0/INT0/P13
GND
picture 10.9: Example of connecting a PCF8583 over I²C-Bus to the IPC@CHIP
10.7 SPI-Bus Example
To use PIO pins for SPI-Bus, see SPI serial data flash example at Beck IPC Website and @CHIP
RTOS documentation.
10.8 Other Examples
More examples are available at the download section of the Beck-IPC Website.

11. CHANGE LIST
Whole document
Added documentation for SC11/SC13. Some scribal errors corrected.

12. CONTACT
BECK IPC GmbH

Garbenheimer Strasse 36 – 38
D-35578 Wetzlar
Germany
Phone: +49 (0)6441-905-0
Fax: +49 (0)6441-905-245
Internet: www.beck-ipc.com
E-Mail: info@beck-ipc.com
©BECK IPC GmbH All rights reserved. No part of this Life critical applications — These products are not designed for
document may be copied or reproduced in any form or by any use in life support appliances, aeronautical applications or
means without the prior written consent of BECK IPC GmbH. devices or systems where malfunction of these products can
The information in this document is subject to change without reasonably be expected to result in personal injury.
notice. Devices sold by BECK IPC GmbH. Are covered by Right to make changes — BECK IPC GmbH reserves the right
warranty and patent indemnification provisions appearing in to make changes, without notice, in the products, including
BECK IPC GmbH. Terms and Conditions of Sale only. BECK software, described or contained herein in order to improve
IPC GmbH MAKES NO WARRANTY, EXPRESS, design and/or performance. Beck IPC GmbH assumes no
STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING responsibility or liability for the use of any of these products.
THE INFORMATION SET FORTH HEREIN OR REGARDING
THE FREEDOM OF THE DESCRIBED DEVICES FROM
INTELLECTUAL PROPERTY INFRINGEMENT. BECK IPC
GmbH MAKES NO WARRANTY OF MERCHANTABILITY OR
FITNESS FOR ANY PURPOSE.
BECK IPC GmbH Shall not be responsible for any errors that
may appear in this document. BECK IPC GmbH makes no
commitment to update or keep current the information
contained in this document.

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IPC@CHIP SC11/SC12/SC13

Hardware Manual V1.5 [01.04.2004]

High Performance, 80186- and 80188-Compatible,

Ordering No. IPC @CHIP

©2000-2004 BECK IPC GmbH Page 1 of 34

©2000-2004 BECK IPC GmbH Page 2 of 34

@CHIP CPU RAM FLASH Ethernet

Enhanced integrated peripherals

Familiar 80C186 peripherals

Pre-installed Real Time Operating System (@CHIP RTOS)

Available in the following packages:

©2000-2004 BECK IPC GmbH Page 3 of 34

IPC@CHIP family microcontroller block diagram

Flash UART TxD[0..1], RxD[0..1]

RAM DMA DRQ[0..1]

©2000-2004 BECK IPC GmbH Page 4 of 34

The package is physically identical for SC11, SC12 and SC13.

Picture 2.1: IPC@CHIP physical dimensions

©2000-2004 BECK IPC GmbH Page 5 of 34

3. Design and handling guidlines

The IPC@CHIP should be used together with a DIL32 socket.

Electrostatic Sensitive Device

©2000-2004 BECK IPC GmbH Page 6 of 34

PIO7 / RXD0 1 32 VCC

Picture 4.1: IPC@CHIP pin configuration

Note: Locate decoupling capacitors as close to VCC Pin as physically possible.

©2000-2004 BECK IPC GmbH Page 7 of 34

5.1 Address / Data bus

Pin Name Type Function

ALE O Address Latch Enable (output)

©2000-2004 BECK IPC GmbH Page 8 of 34

5.2 Programmable I/O Pins

PIO# After power-on reset, the PIO pin Programmable as

Internal Pullup and Pulldown is approximately 7-10kOhm.

©2000-2004 BECK IPC GmbH Page 9 of 34

5.3 Programmable Chip Selects

Pin Name Type Function

Pin Name Type Function

©2000-2004 BECK IPC GmbH Page 10 of 34

Pin Name Type Function

5.6 10/100Base-T Interface

Pin Name Type Function

©2000-2004 BECK IPC GmbH Page 11 of 34

5.7 Asynchronous Serial Ports

The two ports can operate at different rates.

Pin Name Type Function

©2000-2004 BECK IPC GmbH Page 12 of 34

5.9 Reset, Power Fail Generator

Pin Name Type Function

The following schematic delivers a principle insight of pin 17.

©2000-2004 BECK IPC GmbH Page 13 of 34

5.10 NMI reset traffic LED sequence SC12

200 400 600 800 1000 1200 1400 1600 t on / off

200 400 600 800 1000 1200 1400 1600 t on / off

©2000-2004 BECK IPC GmbH Page 14 of 34

5.11 NMI reset traffic LED sequence SC13

200 400 600 800 1000 1200 1400 1600 t on / off

200 400 600 800 1000 1200 1400 1600 t on / off

©2000-2004 BECK IPC GmbH Page 15 of 34