New Zero Voltage Switching Bridgeless PF
New Zero Voltage Switching Bridgeless PF
New Zero Voltage Switching Bridgeless PF
org
Published in IET Power Electronics
Received on 10th January 2010
doi: 10.1049/iet-pel.2010.0150
ISSN 1755-4535
Abstract: This study presents a new zero-voltage-switching (ZVS) single-phase bridgeless PFC, using an improved auxiliary
circuit to achieve ZVS for all main switches and diodes. Compared to other ZVS bridgeless PFC converters with no extra
voltage and/or current stresses, the converter presented here uses lower component count. Since the presented PFC uses a
bridgeless rectifier, there are only two semiconductor components in the main current path instead of three in conventional
single-switch configurations. This property decreases the conduction losses, significantly. Moreover, ZVS removes switching
loss of all main switches and diodes. Furthermore, since resonant current passes only through the auxiliary circuit, there is no
extra current and/or voltage stress on the main switches and diodes. The auxiliary switch operates in zero-current conditions;
therefore it does not introduce any switching loss. The presented converter just needs a simple non-isolated gate drive
circuitry to drive all switches. Nine stages are explained for each ZVS switching period. Design considerations and a control
strategy are also explained. Finally, the converter operation is verified by simulation and experimental results.
732 IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0150
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the auxiliary switch (AXsw) which is an IGBT, operates in the output voltage and input current is constant during one
ZCS condition. Therefore the switching loss of all switches and switching period. Therefore we can model the input current
diodes are removed. In subsequent sections, after analysing the with a dc current source and output voltage with a dc voltage
converter, a design strategy is presented. Finally, these analysis source, as illustrated in Fig. 2b. Also assume that when the
and designs are verified by simulation and experimental results. main switch is on, all auxiliary capacitor voltages and
inductor currents are zero.
Stage 4 [Fig. 3d, t3 – t4]: This stage starts when AXsw is and the Cr3 voltage form beginning of this stage until (t7 ) is
turned on. Owing to series inductors Lr1 , Lr2 , the switch v t
current raises, gradually. So, AXsw turns on in zero-current VCr3 = 2VO sin 1 (7)
condition. Owing to resonant among Lr2 , Cr3 , the resonance 2
current increases to its maximum and starts decreasing. The 1
output voltage is applied on the resonant inductor Lr1 and v1 = (8)
Lr2 Cr3
its current increases linearly, which decreases D3 current
with the same rate. This stage ends when Lr1 current Stage 5 [Fig. 3e, t4–t5]: This stage starts when the Lr1 current
reaches the input current. The time duration of this stage is reaches to input current and diode D3 turns off. Then, a resonant
occurs among Cr1 and Lr1 , and the Lr1 current increases to its
iin× Lr1 maximum, owing to the voltage across Cr1 . The Cr1 voltage
t3 − t4 = (2)
vo decreases to zero and the voltage across diode D3 increases
with the same rate and reaches the output voltage.
and Lr1 , Lr2 and AXsw currents are At this instant the body diode of MOS1 turns on, which is
the end of this stage. During this stage, the Cr3 voltage
Vo reaches to its peak value of (2Vo ) and then starts
iLr1 = t (3) decreasing. The resonant current among Lr2 , Cr3 becomes
Lr1
reversed. The AXsw current, which is the sum of the
Vo Lr1 , Lr2 currents, starts decreasing, but it is still positive. At
iLr2 = sin(v1 t) (4) this stage, the Lr1 current is
Zr1
vO
iLr1 = sin(v0 t) + iin (9)
Lr2 Zr0
Zr1 = (5)
Cr3
Lr1
Zr0 = , C = Cr2 (10)
iAxsw = iLr1 + iLr2 (6) Cr1 r1
734 IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0150
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diode and D7 turn on in zero-voltage condition. The Lr1
freewheeling current flows through body diodes of MOS1,2 ,
D6 , D7 , Lr1 , AXsw . So, the MOS1 can be turned on in zero-
voltage – zero-current (ZVZCS) conditions. The resonant
current of Lr2 , Cr3 continues to rises in the negative
direction. This stage ends, when the sum of Lr1 and Lr2
currents which is the AXsw current reaches zero for the first
time. The time duration of this stage and the Lr1
freewheeling current amount can be described as
1 iin + (vo /Zr0 ) p i × Lr1
t6−t5 = −1
sin − − − in (13)
v1 vo /zr1 2v0 vo
vO
iLr1f = + iin (14)
Zr0
Vo V
iAXsw = iin + + o sin(v1 t) (15)
Zr0 Zr1
At the end of this stage, the AXsw voltage reaches the output where
voltage. Thus, the converter returns to the first stage of the
next switching cycle. Vo
iZr1 , max = (31)
Zr1
3 Design steps
So, Lr2 and Cr3 can be designed using (27) and (32).
The PFC converter can be designed in a four-step procedure.
Step 1: Input voltage, output voltage and output current Lr2 vo
should be given. The rms of input voltage of this converter , (32)
Cr3 iin, max + (vo /zr0 )
varies between 96– 265 V, the output dc voltage is 400 V
and maximum output power is 1000 W.
Step 2: The switching frequency should be selected much Using the above equations, Cr1,2 , Cr3 , Lr1 and Lr2 are
higher than the input voltage frequency, to reduce input calculated as 5 × 10−9 (F), 20 × 10−9 (F), 40 × 10−6 (H)
current low-frequency distortion. For this converter the and 10 × 10−6 (H), respectively. Values here are over-
switching frequency is chosen at 80 kHz, which is high designed to show the results, clearly. The maximum
enough to satisfy the IEC 61000-3-2 standard (higher voltage stress across the AXsw is Vo and its maximum
frequencies can result in more losses as a result of more current is
wires skin effect). By selecting the maximum input current
ripple of 10%, we can calculate the maximum input current Vo V
which is the maximum current stress of the switches iAXsw, max = iin, max + + o (33)
Zr0 Zr1
MOS1,2 and diodes D3,4
√ The peak current of diodes D6,7 is the same as that of iLr1 ,
2p0. max Diin and their maximum voltage is Vo . D5 ’s maximum voltage
iin. max = + (26)
vin. max 2 is 2Vo and its maximum current is the same as that of iLt
in (23).
The maximum voltage stress of these switches and diodes is Step 4: One of the design possibilities of this converter
equal to the output voltage, which is an advantage of this is to operate in continuous current mode (CCM) that
736 IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0150
www.ietdl.org
Fig. 5
a Simplified diagram of peak current controller
b Real controller used for control experimental results
reduces the amount of high-frequency distortions, and minimising the output voltage ripple, using [27], Lin and Co
consequently EMI filter size (other modes have their own are calculated as Lin = 650 mH and Co = 940 mF,
features). So by choosing 10% input current ripple and respectively.
738 IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0150
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output is used as the input of a simple logic circuit to (35) the durations tdelay and Ton,AXsw are selected to be
produce the switching signals of MOS1 and AXsw . The 2.2 × 1026 s and 2.1 × 1026 s, respectively. The applied
main switches’ (MOS1,2) must be turned on after an control circuit diagram is shown Fig. 5b.
appropriate delay from the AXsw switch on-signal, to let
stages 4 and 5 passed. This delay is produced by a time
delay block in the controller, as shown in Fig. 5. MOS1,2 5 Simulation results
stay in the ZVS condition, until the end of the stage 7. On
the other hand, during stage 7, the AXsw is in the ZVZCS The proposed converter is simulated; using power SIM
conditions and is ready to be turned off. Therefore the (PSIM) (the simulated circuit diagram is shown in Fig. 6).
required time delay for MOS1,2 and the AXsw on-time The parameters settings are set as calculated in Section
duration can be determined by 3. The simulation parameters and quantities are chosen as:
step size: 1 × 1028 s; input voltage: 120 Vrms , 50 HZ; the
output voltage 400 V DC; the output power: 400 W; and
(t5 − t3 ) , tdelay , (t7 − t3 ) (34)
the switching frequency fsw: 80 kHz. The converter wave-
forms are shown in Fig. 7. Fig. 7a shows that the input
(t6 − t3 ) , Ton,AXsw , (t7 − t3 ) (35) current is very close to sinusoidal and is in phase with the
input voltage. Fig. 7b shows the input current harmonics
The AXsw gating on-signal (Ton,AXsw) is produced by a that are below the ‘IEC 6 1000-3-2 class A’ requirements
rising-edge monostable. The minimum durations of the [29]. Fig. 7c and d show soft-switching of the main diode
tdelay and Ton,AXsw occur when the rms input voltage is at and switch, respectively. The main switch turns off in
its minimum (i.e. 96 V) and consequently, the input ZVS condition and turns on in ZVZCS conditions. Fig. 7e
current is at its maximum (i.e. 16.5 A). According to (34), shows the AXsw voltage, current, its ZCS turn on and its
740 IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0150
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17 Kim, I.D., Nho, E.C., Choi, S.H., Lai, J.S.: ‘Simple ZVT PWM single- This is the sum of the time durations of stages 4 – 6. Therefore
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24 Mahdavi, M., Farzanehfard, H.: ‘Zero-current-transition bridgeless PFC PFC (Fig. 1), during the duty cycle (DT) of the main
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26 Hua, G., Leu, C.S., Lee, F.C.: ‘Novel zero-voltage-transition PWM resistances losses which are equal for both configurations),
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(University of Colorado, Boulder, Colorado, 2nd edn.) Wcl = [(2Vd + Vs )D + (3Vd )D′ ]T , iin .T (39)
29 International Electro Technical Commission Geneve, IEC 61000-3-2,
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