En25qh64a Eon

EN25QH64A
EN25QH64A preliminary
64 Megabit 3V Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
 Single power supply operation  Software and Hardware Write Protection:
- Full voltage range: 2.7-3.6 volt - Write Protect all or portion of memory via
software
 Serial Interface Architecture
- Enable/Disable protection with WP# pin
- SPI Compatible: Mode 0 and Mode 3
 Software and Hardware Reset
 64 M-bit Serial Flash
- 64 M-bit / 8,192 KByte /32,768 pages  High performance program/erase speed
- 256 bytes per programmable page - Page program time: 0.5ms typical
- Sector erase time: 40ms typical
 Standard, Dual or Quad SPI
- Half Block erase time 200ms typical
- Standard SPI: CLK, CS#, DI, DO, WP#,
- Block erase time 300ms typical
HOLD#/RESET#
- Chip erase time: 30 Seconds typical
- Dual SPI: CLK, CS#, DQ0, DQ1, WP#,
HOLD#/RESET#  Volatile Status Register Bits.
- Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3  Lockable 512 byte OTP security sector
- Configurable dummy cycle number  Read Unique ID Number
 High performance  Minimum 100K endurance cycle
- Normal read  Data retention time 20 years
- 83MHz  Package Options
- Fast read - 8 pins SOP 200mil body width
- Standard SPI: 104MHz with 1 dummy bytes - 8 contact VDFN / WSON (6x5mm)
- Dual SPI: 104MHz with 1 dummy bytes - 8 pins PDIP
- Quad SPI: 104MHz with 3 dummy bytes - 16 pins SOP 300mil body width
 Low power consumption - 24 balls TFBGA (6x8mm)
- 5 mA typical active current - 8 contact VDFN / WSON (8x6mm)
- 1A typical power down current - 8 contact USON (4x3x0.55mm)
 Uniform Sector Architecture: - All Pb-free packages are compliant RoHS,
- 2048 sectors of 4-Kbyte Halogen-Free and REACH.
- 256 blocks of 32-Kbyte  Industrial temperature Range
- 128 blocks of 64-Kbyte
- Any sector or block can be erased individually
GENERAL DESCRIPTION
The EN25QH64A is a 64 Megabit (8,192K-byte) Serial Flash memory, with advanced write protection
mechanisms. The EN25QH64A supports the single bit and four bits serial input and output commands
via standard Serial Peripheral Interface (SPI) pins: Serial Clock, Chip Select, Serial DQ 0 (DI) and
DQ1(DO), DQ2(WP#) and DQ3(HOLD#/RESET#). SPI clock frequencies of up to 104MHz are supported
allowing equivalent clock rates of 416MHz (104Mhz x 4) for Quad Output while using the Quad Output
Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The EN25QH64A also offers a sophisticated method for protecting individual blocks against erroneous
or malicious program and erase operations. By providing the ability to individually protect and unprotect
blocks, a system can unprotect a specific block to modify its contents while keeping the remaining
blocks of the memory array securely protected. This is useful in applications where program code is
patched or updated on a subroutine or module basis or in applications where data storage segments
need to be modified without running the risk of errant modifications to the program code segments.
The EN25QH64A is designed to allow either single Sector/Block at a time or full chip erase operation.
The EN25QH64A can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions 1 Elite Semiconductor Memory Technology Inc.
or modifications due to changes in technical specifications.
Rev. I, Issue Date: 2018/12/13
EN25QH64A
Figure.1 CONNECTION DIAGRAMS preliminary
CS# 1 8 VCC
DO (DQ1) 2 7 HOLD#/RESET# (DQ3)

WP# (DQ2) 3 6 CLK
VSS 4 5 DI (DQ0)
8 - LEAD SOP / PDIP
CS# 1 8 VCC
DO (DQ1) 2 7 HOLD#/RESET# (DQ3)
WP# (DQ2) 3 6 CLK
VSS 4 5 DI (DQ0)
8 - LEAD VDFN / WSON
16 - LEAD SOP
EN25QH64A
preliminary
Top View, Balls Facing Down
24 - Ball TFBGA
Table 1. Pin Names
Symbol Pin Name

CLK Serial Clock Input
*1
DI (DQ0) Serial Data Input (Data Input Output 0)
*1
DO (DQ1) Serial Data Output (Data Input Output 1)
CS# Chip Enable
*2
WP# (DQ2) Write Protect (Data Input Output 2)
HOLD# or RESET# pin
HOLD#/RESET# (DQ3) *2
(Data Input Output 3)
Vcc Supply Voltage (2.7-3.6V)
Vss Ground
NC No Connect
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ0 ~ DQ3 are used for Quad instructions,
WP# & HOLD# (or RESET#) functions are only available for Standard/Dual SPI.
EN25QH64A
preliminary
Figure 2. BLOCK DIAGRAM
Flash
Address X-Decoder
Memory
Buffer
And
Latches
Y-Decoder
I/O Buffers
Control Logic and
Data Latches
Serial Interface
CS# CLK DI (DQ0) DO (DQ1) WP# (DQ2) HOLD# / RESET#

(DQ3)
Note:
1. DQ0 and DQ1 are used for Dual instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
EN25QH64A
preliminary
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3)
The EN25QH64A support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (SR.5, SR.4, SR.3, SR.2) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ2) for Quad I/O operation.
HOLD (HOLD#)
The HOLD# pin allows the device to be paused while it is actively selected. When WXDIS bit is “0”
(factory default) and HRSW bit is ‘0’ (factory default is ‘0’), the HOLD# pin is enabled. When HOLD# is
brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins
will be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same
SPI signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during
Quad SPI, this pin is the Serial Data IO (DQ3) for Quad I/O operation.
RESET (RESET#)
The RESET# pin allows the device to be reset by the controller. When WXDIS bit is “0” (factory default)
and HRSW bit is ‘1’ (factory default is ‘0’), the RESET# pin is enabled. The Hardware Reset function is
only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ3) for Quad I/O operation. Set RESET# to low for a minimum period 1us (tHRST) will
interrupt any on-going instructions to have the device to initial state. The device can accept new
instructions again in 28us (tHRSL) after RESET# back to high.
EN25QH64A
preliminary
MEMORY ORGANIZATION
The memory is organized as:
 8,388,608 bytes
 Uniform Sector Architecture
128 blocks of 64-Kbyte
256 blocks of 32-Kbyte
2,048 sectors of 4-Kbyte
32,768 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
EN25QH64A
preliminary
Table 2. Uniform Block Sector Architecture
64K 32K 64K 32K

Sector Address range Sector Address range
Block Block Block Block
255 2047 7FF000h 7FFFFFh 223 1791 6FF000h 6FFFFFh
….
….
….
….
….
….
127 111
254 2032 7F0000h 7F0FFFh 222 1776 6F0000h 6F0FFFh
253 2031
…. 7EF000h 7EFFFFh 221 1775 6EF000h 6EFFFFh
….
….
….
….
….
126 110
252 2016 7E0000h 7E0FFFh 220 1760 6E0000h 6E0FFFh
251 2015 7DF000h 7DFFFFh 219 1759 6DF000h 6DFFFFh
….
….
….
….
….
….
125 109
250 2000 7D0000h 7D0FFFh 218 1744 6D0000h 6D0FFFh
….
….
….
….
….
….
….
….
….
….
229 1839 72F000h 72FFFFh 197 1583 62F000h 62FFFFh
….
….
….
….
….
….
114 98
228 1824 720000h 720FFFh 196 1568 620000h 620FFFh
227 1823 71F000h 71FFFFh 195 1567 61F000h 61FFFFh
….
….
….
….
….
….
113 97
226 7952 1F10000h 1F10FFFh 194 1552 610000h 610FFFh
225 7951 1F0F000h 1F0FFFFh 193 1551 60F000h 60FFFFh
….
….
….
….
….
….
112 96
224 1972 700000h 700FFFh 192 1536 600000h 600FFFh
…......
…......
…......
64K 32K 64K 32K
Sector Address range Sector Address range
Block Block Block Block
63 511 01FF000h 01FFFFFh 31 255 00FF000h 00FFFFFh
….
….
….
….
….
….
31 15
62 496 01F0000h 01F0FFFh 30 240 00F0000h 00F0FFFh
61 495 01EF000h 01EFFFFh 29 239 00EF000h 00EFFFFh
….
….
….
….
….
….
30 14
60 480 01E0000h 01E0FFFh 28 224 00E0000h 00E0FFFh
59 479 01DF000h 01DFFFFh 27 223 00DF000h 00DFFFFh
….
….
….
….
….
….
29 13
58 464 01D0000h 01D0FFFh 26 208 00D0000h 00D0FFFh
….
….
….
….
….
….
….
….
….
….
37 303 012F000h 012FFFFh 5 47 002F000h 002FFFFh

….
….
….
….
….
….
18 2
36 288 0120000h 0120FFFh 4 32 0020000h 0020FFFh
35 287 011F000h 011FFFFh 3 31 001F000h 001FFFFh
….
….
….
….
….
….
17 1
34 272 0110000h 0110FFFh 2 16 0010000h 0010FFFh
33 271 010F000h 010FFFFh 1 15 000F000h 000FFFFh
….
….
….
….
….
….
16 0
32 256 0100000h 0100FFFh 0 0 0000000h 0000FFFh
EN25QH64A
preliminary
OPERATING FEATURES
Standard SPI Modes

The EN25QH64A is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation
Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as
shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby
and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For
Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising
edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
Figure 3. SPI Modes
Dual SPI Instruction

The EN25QH64A supports Dual SPI operation when using the “ Dual Output Fast Read and Dual I/ O
FAST_READ “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from
the Serial Flash memory at two to three times the rate possible with the standard SPI. The Dual Read
instructions are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing)
or for application that cache code-segments to RAM for execution. The Dual output feature simply
allows the SPI input pin to also serve as an output during this instruction. When using Dual SPI
instructions the DI and DO pins become bidirectional I/O pins; DQ 0 and DQ1. All other operations use
the standard SPI interface with single output signal.
Quad I/O SPI Modes

The EN25QH64A supports Quad output operation when using the Quad I/O Fast Read (EBh).This
instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate
possible with the standard SPI. The Quad Read instruction offer a significant improvement in continuous
and random access transfer rates allowing fast code-shadowing to RAM or for application that cache
code-segments to RAM for execution. When using Quad I/O SPI instructions, the DI and DO pins
become bidirectional I/O pins; DQ0 and DQ1, and the WP# and HOLD#/RESET# pins become DQ2 and
DQ3 respectively.
EN25QH64A
preliminary
Figure 4. Quad SPI Modes
Full Quad SPI Modes (QPI)
The EN25QH64A also supports Full Quad SPI Mode (QPI) function while using the Enable Quad
Peripheral Interface mode (EQPI) (38h). When using Quad SPI instruction the DI and DO pins become
bidirectional I/O pins; DQ0 and DQ1, and the WP# and HOLD#/RESET# pins become DQ2 and DQ3
respectively.
Figure 5. Full Quad SPI Modes
EN25QH64A
preliminary
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and
a Page Program (PP) or Quad Input Page Program (QPP) sequence, which consists of four bytes plus
data. This is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) or Quad Input Page Program (QPP) instruction allows
up to 256 bytes to be programmed at a time (changing bits from 1 to 0) provided that they lie in
consecutive addresses on the same page of memory.
Sector Erase, Half Block Erase, Block Erase and Chip Erase
The Page Program (PP) or Quad Input Page Program (QPP) instruction allows bits to be reset from 1 to
0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can
be achieved a sector at a time, using the Sector Erase (SE) instruction, half a block at a time using the
Half Block Erase (HBE) instruction, a block at a time using the Block Erase (BE) instruction or
throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle
(of duration tSE, tHBE, tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN)
instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP, QPP) or Erase (SE,
HBE, BE or CE) can be achieved by not waiting for the worst case delay (tW , tPP, tSE, tHBE, tBE or tCE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program can
monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is
complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, Write Status Register). The device then goes into the Stand-by
Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in
this mode until another specific instruction (the Release from Deep Power-down Mode and Read Device
ID (RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
EN25QH64A provides the following data protection mechanisms:
 Power-On Reset and an internal timer (tPUW ) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
 Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
 All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the
Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP), Quad Input Page Program (QPP) instruction completion
or Sector Erase (SE) instruction completion or Half Block Erase (HBE) / Block Erase (BE)
instruction completion or Chip Erase (CE) instruction completion
– Software/Hardware Reset completion
 The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
 The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
 In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
EN25QH64A
preliminary
Table 3. Protected Area Sizes Sector Organization
Status Register Content Memory Content

T/B SR.5 SR.4 SR.3 SR.2
Protect Areas Addresses Density(KB) Portion
Bit Bit Bit Bit Bit
0 0 0 0 0 None None None None
0 0 0 0 1 Block 127 7F0000h-7FFFFFh 64KB Upper 1/128
0 0 0 1 0 Block 126 to 127 7E0000h-7FFFFFh 128KB Upper 2/128
0 0 0 1 1 Block 124 to 127 7C0000h-7FFFFFh 256KB Upper 4/128
0 0 1 0 0 Block 120 to 127 780000h-7FFFFFh 512KB Upper 8/128
0 1 1 1 0 All 000000h-7FFFFFh 8192KB All
1 0 0 0 0 None None None None
1 0 0 0 1 Block 0 000000h-00FFFFh 64KB Lower 1/128
1 0 0 1 0 Block 0 to 1 000000h-01FFFFh 128KB Lower 2/128
1 0 1 0 1 Block 0 to 15 000000h-0FFFFFh 1024KB Lower 16/128
1 1 0 1 1 Block 0 to 123 000000h-7BFFFFh 7936KB Lower 124/128
1 1 1 0 0 Block 0 to 125 000000h-7DFFFFh 8064KB Lower 126/128
1 1 1 0 1 Block 0 to 126 000000h-7EFFFFh 8128KB Lower 127/128
EN25QH64A
preliminary
Enable Boot Lock
The Enable Boot Lock feature enables user to lock the 64KB-block/sector on the top/bottom of the
device for protection. This feature is activated by configuring 64KB-Block/Sector switch, TB bits and
programming EBL bit to ‘1’. The TB bit and 64KB-Block/Sector switch bit can only be programmed once.
The bits’ definitions are described in the following table.
Table 4. The Enable Boot Lock feature

Type Register Description Function
0 (default)
Non-volatile/
SR.6 Enable 64KB-block/Sector Boot lock 1 : Lock selected
Volatile bit
64KB-Block/Sector
0 : Top (default)
SR.3 Top/Bottom Protect
OTP/Volatile 1 : Bottom
bit 0 : 64KB-Block (default)
SR.4 64KB-Block/Sector switch
1 : Sector
EN25QH64A
preliminary
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven
Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on
Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 5. Every instruction sequence starts with a one-byte instruction code.
Depending on the instruction, it might be followed by address bytes, or data bytes, or both or none. Chip
Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the
case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Dual Output Fast
Read (3Bh), Dual I/O Fast Read (BBh), Quad Output Fast Read (6Bh), Quad Input/Output FAST_READ
(EBh), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI)
instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#)
can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a write instruction, Chip Select (CS#) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High
when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight.
For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be
reset.
In the case of multi-byte commands of Page Program (PP), Quad Input Page Program (QPP), and
Release from Deep Power Down (RES ) minimum number of bytes specified has to be given,
without which, the command will be ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and HBE / BE, exact 24-bit address is a must,
any less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
EN25QH64A
preliminary
Table 5A. Instruction Set
Instruction Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes

Code
RSTEN 66h
RST(1) 99h
EQPI 38h
RSTQPI(2) FFh
Write Enable (WERN) 06h
Volatile Status Register
50h
Write Enable (3)
Write Disable (WRDI)/
04h
Exit OTP mode
Read Status Register
(RDSR)
05h (S7-S0)(4) continuous(5)
Write Status Register
01h S7-S0
(WRSR)
Read Status Register 3
(RDSR3)
95h (S7-S0)(4)
Write Status Register 3
C0h S7-S0
(WRSR3)
Deep Power-down B9h
Release from Deep (6)
Power-down, and read dummy dummy dummy (ID7-ID0)
Device ID (RES) ABh
Release from Deep
Power-down (RDP)
Manufacturer/ 00h (M7-M0) (ID7-ID0) (7)
Device ID 90h dummy dummy
01h (ID7-ID0) (M7-M0)
Read Identification (ID15- (ID7-ID0) (8)
9Fh (M7-M0)
(RDID) ID8)
Enter OTP mode 3Ah
Read SFDP mode and (Next Byte)
5Ah A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Unique ID Number continuous
Notes:
1. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
2. Release Full Quad SPI or Fast Read Enhanced mode. Device accepts eight-clocks command in Standard SPI mode, or two-
clocks command in Full Quad SPI mode.
3. Volatile Status Register Write Enable command must precede WRSR command without any intervening commands to write
data to Volatile Status Register.
4. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the
device on the DO pin.
5. The Status Register contents will repeat continuously until CS# terminate the instruction.
6. The Device ID will repeat continuously until CS# terminates the instruction.
7. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.
8. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity.
EN25QH64A
preliminary
Table 5B. Instruction Set (Read Instruction)
Address Dummy bits / Clocks

Instruction Name OP Code Data Out Remark
bits (Default)
(Next Byte)
Read Data 03h 24 bits 0 (D7-D0, …)
continuous
(Next Byte)
Fast Read 0Bh 24 bits 8 bits / 8 clocks (D7-D0, …)
continuous
(one byte
Dual Output Fast Read 3Bh 24 bits 8 bits / 8 clocks (D7-D0, …) Per 4 clocks,
continuous)
(one byte
Dual I/O Fast Read BBh 24 bits 8 bits / 4 clocks (D7-D0, …) Per 4 clocks,
continuous)
(one byte
Quad I/O Fast Read EBh 24 bits 24 bits / 6 clocks (D7-D0, …) per 2 clocks,
continuous)
(one byte
Quad Output Fast Read 6Bh 24 bits 8 bits / 8 clocks (D7-D0, …) per 2 clocks,
continuous)
Table 5C. Instruction Set (Program Instruction)
Address Dummy bits Clocks

Instruction Name OP Code Data In Remark
bits (Default)
(Next Byte)
Page Program (PP) 02h 24 bits 0 (D7-D0, …)
continuous
(one byte
Quad Input Page Program
32h 24 bits 0 (D7-D0, …) per 2 clocks,
(QPP) continuous)
Table 5D. Instruction Set (Erase Instruction)
Address Dummy bits Clocks

Instruction Name OP Code Data In Remark
bits (Default)
Sector Erase (SE) 20h 24 bits 0 (D7-D0, …)
32K Half Block

52h 24 bits 0 (D7-D0, …)
Erase (HBE)
64K Block Erase (BE) D8h 24 bits 0 (D7-D0, …)
Chip Erase (CE) C7h/ 60h 24 bits 0 (D7-D0, …)
EN25QH64A
preliminary
Table 5E. Instruction Set (Read Instruction support mode and apply dummy cycle setting)
(1) (2)
Start From SPI/QPI Dummy Byte
Instruction Name OP Code
SPI QPI Start From SPI Start From QPI
Read Data 03h Yes No N/A N/A
Fast Read 0Bh Yes Yes 8 clocks By SR3.4~5
Dual Output Fast Read 3Bh Yes No 8 clocks N/A
Dual I/O Fast Read BBh Yes No 4 clocks N/A
Quad Output Fast Read 6Bh Yes No 8 clocks N/A
Quad I/O Fast Read EBh Yes Yes By SR3.4~5 By SR3.4~5
Note:
1. ‘Start From SPI/QPI' means if this command is initiated from SPI or QPI mode.
2. Note: The dummy byte settings please refer to table 9.
Table 6. Manufacturer and Device Identification
OP Code (M7-M0) (ID15-ID0) (ID7-ID0)
ABh 16h
90h 1Ch 16h
9Fh 1Ch 7017h
Reset-Enable (RSTEN) (66h) and Reset (RST) (99h)

The Reset operation is used as a system (software) reset that puts the device in normal operating
Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST).
To reset the EN25QH64A the host drives CS# low, sends the Reset-Enable command (66h), and drives
CS# high. Next, the host drives CS# low again, sends the Reset command (99h), and drives CS# high.
The Reset operation requires the Reset-Enable command followed by the Reset command. Any
command other than the Reset command after the Reset-Enable command will disable the Reset-
Enable.
A successful command execution will reset the status registers, see Figure 6 for SPI Mode and Figure
6.1 for Quad Mode. A device reset during an active Program or Erase operation aborts the operation,
which can cause the data of the targeted address range to be corrupted or lost. Depending on the prior
operation, the reset timing may vary. Recovery from a Write operation requires more software latency
time ( tSR) than recovery from other operations.
EN25QH64A
preliminary
Figure 6. Reset-Enable and Reset Sequence Diagram
Figure 6.1 . Reset-Enable and Reset Sequence Diagram in QPI Mode
EN25QH64A
Software Reset Flow preliminary
Initial
No
Command
= 66h ?
Yes
Reset enable
No
Command
= 99h ?
Yes
Reset start
No
Embedded
WIP = 0 ?
Reset Cycle
Yes
Reset done
Note:
1. Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) commands need to match standard SPI or
EQPI (quad) mode.
2. Continue (Enhance) EB mode need to use quad Reset-Enable (RSTEN) (66h) and quad Reset (RST)
(99h) commands.
3. If user is not sure it is in SPI or Quad mode, we suggest to execute sequence as follows:
Quad Reset-Enable (RSTEN) (66h) -> Quad Reset (RST) (99h) -> SPI Reset-Enable (RSTEN) (66h)
-> SPI Reset (RST) (99h) to reset.
4. The reset command could be executed during embedded program and erase process, QPI mode,
Continue EB mode to back to SPI mode.
5. This flow can release the device from Deep power down mode.
6. The Status Register Bit will reset to default value after reset done.
7. If user reset device during erase, the embedded reset cycle software reset latency will take about
28us in worst case.
EN25QH64A
Enable Quad Peripheral Interface mode (EQPI) (38h) preliminary

The Enable Quad Peripheral Interface mode (EQPI) instruction will enable the flash device for Quad SPI
bus operation. Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed
input/output until a power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 7. The
device did not support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh), Dual
Input/Output FAST_READ (BBh) and Quad Input Page Program (32h) modes while the Enable Quad
Peripheral Interface mode (EQPI) (38h) turns on.
Figure 7. Enable Quad Peripheral Interface mode Sequence Diagram
Reset Quad I/O (RSTQIO) (FFh)

The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset
Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then,
drives CS# high. This command can’t be used in Standard SPI mode.
User also can use the FFh command to release the Quad I/O Fast Read Enhancement Mode. The
detail description, please see the Quad I/O Fast Read Enhancement Mode section.
Note:
If the system is in the Quad I/O Fast Read Enhance Mode in QPI Mode, it is necessary to execute FFh
command by two times. The first FFh command is to release Quad I/O Fast Read Enhance Mode, and
the second FFh command is to release EQPI Mode.
Write Enable (WREN) (06h)

The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Quad Input Page Program (QPP),
Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
The instruction sequence is shown in Figure 10.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
EN25QH64A
preliminary
Figure 8. Write Enable Instruction Sequence Diagram
Volatile Status Register Write Enable (50h)
This feature enable user to change memory protection schemes quickly without waiting for the typical
non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The
Volatile Status Register Write Enable (50h) command won’t set the Write Enable Latch (WEL) bit, it is
only valid for ‘Write Status Register’ (01h) command to change the Volatile Status Register bit values.
To write to Volatile Status Register, issue the Volatile Status Register Write Enable (50h) command
prior issuing WRSR (01h). The Status Register bits will be refresh to Volatile Status Register (SR[7:2])
within tSHSL2 (50ns). Upon power off or the execution of a Software/Hardware Reset, the volatile
Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored.
The instruction sequence is shown in Figure 9.
Figure 9. Volatile Status Register Write Enable Instruction Sequence Diagram
EN25QH64A
Write Disable (WRDI) (04h) preliminary

The Write Disable instruction (Figure 10) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write
Status Register, Page Program, Sector Erase, Half Block Erase (HBE), Block Erase (BE) and Chip
Erase instructions.
Figure 10. Write Disable Instruction Sequence Diagram
Figure 10.1 Write Enable/Disable Instruction Sequence in QPI Mode
EN25QH64A
preliminary
Read Status Register (RDSR) (05h)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register
continuously, as shown in Figure 11.
Figure 11. Read Status Register Instruction Sequence Diagram
Figure 11.1 Read Status Register Instruction Sequence in QPI Mode
EN25QH64A
preliminary
Table 7. Status Register Bit Locations
SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0

EBL bit
SRP bit (Enable boot BP3 bit BP2 bit BP1 bit BP0 bit
lock)
WEL bit WIP bit
64KB-
OTP_LOCK bit WXDIS bit HRSW bit Block/Sector TB bit Reserved
(Top / Bottom Protect)
switch bit
Table 7.1 Status Register Bit Locations (In Normal mode)

SRP EBL bit WEL bit WIP bit
BP3 bit BP2 bit BP1 bit BP0 bit
Status Register (Enable Boot (Write Enable (Write In Progress
(Block Protect) (Block Protect) (Block Protect) (Block Protect)
Protect Lock) Latch) bit)
1 = Lock selected 1 = write enable 1 = write operation

1 = status register
64KB- (note 2) (note 2) (note 2) (note 2) 0 = not write 0 = not in write
write disable
Block/Sector enable operation
Non-volatile/ Non-volatile/ Non-volatile/ Non-volatile/ Non-volatile/ Non-volatile/

indicator bit indicator bit
Volatile bit Volatile bit Volatile bit Volatile bit Volatile bit Volatile bit
Table 7.2 Status Register Bit Locations (In OTP mode)

WXDIS bit
HRSW bit TB bit WEL bit WIP bit
(WP# and 64KB-Bloc/Sector
OTP_LOCK bit (HOLD#/RESET# (Top / Bottom (Write Enable (Write In Progress
HOLD#/RESET# switch bit
switch) Protect) Latch) bit)
disabled)
1 = WP# and
HOLD#/RESET# 1 = RESET# Reserved
disable enable 1 = Sector 1 = Bottom bit 1 = write enable 1 = write operation
1 = OTP sector is
0 = WP# and 0 = HOLD# 0 = 64KB-Block 0 = Top 0 = not write 0 = not in write
protected
HOLD#/RESET# enable (default 0) (default 0) enable operation
enable (default 0)
(default 0)
OTP bit OTP / Volatile bit OTP / Volatile bit OTP / Volatile bit OTP / Volatile bit indicator bit indicator bit
Note
1. In OTP mode, SR.7 bit is served as OTP_LOCK bit; SR.6 bit is served as WXDIS bit; SR.5 bit is served
as HRSW bit; SR.4 bit is served as 64KB-Block/Sector switch bit; SR.3 bit is served as TB bit; SR.1 bit
is served as WEL bit and SR.0 bit is served as WIP bit.
2. See the table 3 “Protected Area Sizes Sector Organization”.
3. When executed the (RDSR) (05h) command, the WIP (SR.0) value is the same as WIP (SR2.0) in
table 8.
EN25QH64A
preliminary
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,
BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected
against Page Program (PP), Quad Input Page Program (QPP), Sector Erase (SE) and , Half Block Erase
(HBE), Block Erase (BE) instructions. The Block Protect (BP3, BP2, BP1, BP0) bits can be written and
provided that the Hardware Protected mode has not been set. The Chip Erase (CE) instruction is
executed if and only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0 and EBL bit is 0.
EBL bit. The Enable Boot Lock (EBL) bit is used to enable the Boot Lock feature. When this bit is
programmed to ‘1’, the sector/block selected by the TB bit and 64KB-Block/Sector switch bit will be
locked.
SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)
signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to
be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and
Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, SR.5,
SR.4, SR.3, SR.2) become read-only bits and the Write Status Register (WRSR) instruction is no longer
accepted for execution.
In OTP mode, SR.7, SR.6, SR.5, SR.4, SR.3, SR.1 and SR.0 are served as OTP_Lock bit, WXDIS bit,
HRSW bit, 64KB-Block/Sector switch bit, TB bit, WEL bit and WIP bit.
TB bit. The Top/Bottom Protect Bit (TB) controls if the Block Protect Bits (BP3, BP2, BP1, BP0) protect
from the Top (TB = 0) or the Bottom (TB = 1) of the array as shown in the Status Register Memory
Protection table. It also controls if the Top (TB=0) or the Bottom (TB=1) 64KB-block/sector is protected
when Boot Lock feature is enabled. The factory default setting is TB = 0. The TB bit can be set with the
Write Status Register instruction in OTP mode.
64KB-Block/Sector switch bit, The 64KB-Block/Sector switch bit is set by WRSR command in OTP
mode. It is used to set the protection area size as block (64KB) or sector (4KB).
WXDIS bit. The WP# and HOLD#/RESET# Disable bit (WXDIS bit), OTP / Volatile bit, it indicates the
WP# and HOLD#/RESET# are enabled or not. When it is “0” (factory default), the WP# and
HOLD#/RESET# are enabled. On the other hand, while WXDIS bit is “1”, the WP# and HOLD#/RESET#
are disabled. If the system executes Quad mode commands, this WXDIS bit becomes no affection
since WP# and HOLD#/RESET# function will be disabled by Quad mode commands.
HRSW bit. The HOLD#/RESET# switch bit (HRSW bit), OTP / Volatile bit, the HRSW bit is used to
determine whether HOLD# or RESET# function should be implemented on the hardware pin. When it is
“0” (factory default), the pin acts as HOLD#; when it is “1”, the pin acts as RESET#. However, HOLD# or
RESET# functions are only available when WXDIS bit is “0”. If WXDIS bit is set to “1”, the HOLD# and
RESET# functions are disabled, the pin acts as a dedicated data I/O pin.
OTP_LOCK bit. This bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector
while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command, the OTP sector is
protected from program and erase operation. The OTP_LOCK bit can only be programmed once.
Reserved bit. Status Register bit locations SR.2 in OTP mode is reserved for future use.
EN25QH64A
preliminary
Read Status Register 3 (RDSR 3) (95h)
The Read Status Register 3 (RDSR3) instruction allows the Status Register 3 to be read. The Status
Register 3 may be read at any time. When one of these bytes is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Read Status Register 3 continuously, as shown in Figure 12.
Figure 12. Read Status Register 3 Instruction Sequence Diagram
Figure 12.1 Read Status Register 3 Instruction Sequence in QPI Mode
EN25QH64A
The status and control bits of the Status Register 3 are as follows: preliminary
Output Drive Strength. The Output Drive Strength (SR3.3 and SR3.2) bits indicate the status of output
Drive Strength in I/O pins.
Dummy Byte. The Dummy Byte (SR3.5 and SR3.4) bits indicate the status of the number of dummy
byte in high performance read.
Reserved bit. SR3.7, SR3.6, SR3.1 and SR3.0 are reserved for future use.
Table 8. Status Register 3 Bit Locations
SR3.7 SR3.6 SR3.5 SR3.4 SR3.3 SR3.2 SR3.1 SR3.0

(1)
Dummy Byte Output Drive
Default = 00 Strength
00 = 67% (2/3) Drive
Reserved Reserved 00 = 3 Bytes Reserved Reserved
(default)
01 = 2 Bytes
01 = 100% (Full) Drive
10 = 4 Bytes
10 = 50% (1/2) Drive
11 = 5 Bytes
11 = 33% (1/3) Drive
volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit
Note:
1. 2 Bytes (4 clocks in Quad mode), 3 Bytes (6 clocks in Quad mode),
4 Bytes (8 clocks in Quad mode), 5 Bytes (10 clocks in Quad mode)
Table 9. SR3.4 and SR3.5 Status (for Dummy Bytes)
Start Dummy Byte settings

Instruction Name Op Code (1)
Address <=104MHz
Byte 3
Fast Read 0Bh Word 2
Dword 2
Byte 3
Quad IO Fast Read EBh Word 2
Dword 2
Note 1:
“Dword” means the start address is 4-byte aligned (i.e. Start Address is 0, 4, 8...), “Word” means the
start address is 2-byte aligned (i.e. Start Address is 0, 2, 4, 8...) and “Byte” means the start address can
be anywhere without 2-byte or 4-byte aligned.
EN25QH64A
preliminary
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write
Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 13. The Write Status Register (WRSR) instruction has no
effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of
the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose duration
is tW ) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during
the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed,
the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware
Protected Mode (HPM) is entered.
NOTE :
In the OTP mode without enabling Volatile Status Register function (50h), WRSR command is used to
program OTP_LOCK bit, WXDIS bit, HRSW bit, TB bit and 64KB-Block/Sector switch bit to ‘1‘, but these
bits can only be programmed once.
Figure 13. Write Status Register Instruction Sequence Diagram
EN25QH64A
preliminary
Figure 13.1 Write Status Register Instruction Sequence in QPI Mode
Read Data Bytes (READ) (03h)

The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum frequency f R, during the falling edge of
Serial Clock (CLK).
The instruction sequence is shown in Figure 14. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the
highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to
be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select
(CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while
an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that
is in progress.
Figure 14. Read Data Instruction Sequence Diagram
EN25QH64A
preliminary
Read Data Bytes at Higher Speed (FAST_READ) (0Bh)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory
contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a
maximum frequency FR, during the falling edge of Serial Clock (CLK).
The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes
at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 15. Fast Read Instruction Sequence Diagram
EN25QH64A
preliminary
Figure 15.1 Fast Read Instruction Sequence in QPI Mode
Dual Output Fast Read (3Bh)

The Dual Output Fast Read (3Bh) is similar to the standard Fast Read (0Bh) instruction except that data
is output on two pins, DQ0 and DQ1, instead of just DQ0. This allows data to be transferred from the
EN25QH64A at twice the rate of standard SPI devices. The Dual Output Fast Read instruction is ideal
for quickly downloading code from to RAM upon power-up or for applications that cache code-segments
to RAM for execution.
Similar to the Fast Read instruction, the Dual Output Fast Read instructions can operation at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy clocks after the 24-bit address as shown in Figure 16. The dummy clocks allow the device’s
internal circuits additional time for setting up the initial address. The input data during the dummy clock
is “don’t care”. However, the DI pin should be high-impedance prior to the falling edge of the first data
out clock.
EN25QH64A
preliminary
Figure 16. Dual Output Fast Read Instruction Sequence Diagram
Dual Input / Output FAST_READ (BBh)

The Dual I/O Fast Read (BBh) instruction allows for improved random access while maintaining two IO
pins, DQ0 and DQ1. It is similar to the Dual Output Fast Read (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
The Dual I/O Fast Read instruction enable double throughput of Serial Flash in read mode. The address
is latched on rising edge of CLK, and data of every two bits (interleave 2 I/O pins) shift out on the falling
edge of CLK at a maximum frequency. The first address can be at any location. The address is
automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single Dual I/O Fast Read instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing Dual I/O Fast Read instruction, the following
address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 17.
EN25QH64A
preliminary
Figure 17. Dual Input / Output Fast Read Instruction Sequence Diagram
Quad Output Fast Read (6Bh)

The Quad Output Fast Read (6Bh) instruction is similar to the Dual Output Fast Read (3Bh) instruction
except that data is output through four pins, DQ0, DQ1, DQ2 and DQ3 and eight dummy clocks are
required prior to the data output. The Quad Output dramatically reduces instruction overhead allowing
faster random access for code execution (XIP) directly from the Quad SPI.
The Quad Output Fast Read (6Bh) address is latching on rising edge of CLK, and data of every four bits
(interleave on 4 I/O pins) shift out on the falling edge of CLK at a maximum frequency F R. The first
address can be any location. The address is automatically increased to the next higher address after
each byte data is shifted out, so the whole memory can be read out at a single Quad Output Fast Read
instruction. The address counter rolls over to 0 when the highest address has been reached.
The sequence of issuing Quad Output Fast Read (6Bh) instruction is: CS# goes low -> sending Quad
Output Fast Read (6Bh) instruction -> 24-bit address on DQ0 -> 8 dummy clocks -> data out interleave
on DQ3, DQ2, DQ1 and DQ0 -> to end Quad Output Fast Read (6Bh) operation can use CS# to high at
any time during data out, as shown in Figure 18. The WP#(DQ2) and HOLD#/RESET#(DQ3) need to
drive high before address input if WXDIS bit in Status Register is 0.
EN25QH64A
preliminary
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK
Command 3 Address bytes

(24 clocks)
DQ0 6Bh A23 A22 A21 A3 A2 A1 A0
High Impedance *
DQ1
High Impedance
DQ2
High Impedance
DQ3
* = MSB
CS#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
CLK
Dummy Byte DQ0 switches from
Input to Output
High Impedance
DQ0 A0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4
High Impedance
DQ1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5
High Impedance
DQ2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6
High Impedance
DQ3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7
Data Data Data Data Data

Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
Figure 18. Quad Output Fast Read Instruction Sequence Diagram
Quad Input / Output FAST_READ (EBh)

The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)
instruction except that address and data bits are input and output through four pins, DQ0, DQ1, DQ2 and
DQ3 and six dummy clocks are required prior to the data output. The Quad I/O dramatically reduces
instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read
mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O
pins) shift out on the falling edge of CLK at a maximum frequency F R. The first address can be any
location. The address is automatically increased to the next higher address after each byte data is
shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform
as 4-bit instead of previous 1-bit.
The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low -> sending
Quad Input/Output FAST_READ (EBh) instruction -> 24-bit address interleave on DQ3, DQ2, DQ1 and
DQ0 -> 6 dummy clocks -> data out interleave on DQ3, DQ2, DQ1 and DQ0 -> to end Quad Input/Output
EN25QH64A
preliminary
FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown in Figure 19.
Figure 19. Quad Input / Output Fast Read Instruction Sequence Diagram
Figure 19.1. Quad Input / Output Fast Read Instruction Sequence in QPI Mode
EN25QH64A
preliminary
Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in
random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit
address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4 dummy
clocks -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low (reduce
Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit random access address, as shown in
Figure 20.
In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,
F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)
instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. These
commands will reset the performance enhance mode. And afterwards CS# is raised or issuing FFh
command (CS# goes high -> CS# goes low -> sending FFh -> CS# goes high) instead of no toggling,
the system then will escape from performance enhance mode and return to normal operation.
While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)
instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.
EN25QH64A
preliminary
Figure 20. Quad Input/Output Fast Read Enhance Performance Mode Sequence Diagram
EN25QH64A
preliminary
Figure 20.1 Quad Input/Output Fast Read Enhance Performance Mode Sequence in QPI Mode
EN25QH64A
Write Status Register 3 (C0h) preliminary

The Write Status Register 3 (C0h) command can be used to set output drive strength in I/O pins and the
number of dummy byte in high performance read. To set the output drive strength and the number of
dummy byte to host driver CS# low, sends the Write Status Register 3 (C0h) and one data byte, then
drivers CS# high, After power-up or reset, the output drive strength is set to full drive (00b) and the
dummy byte is set to 3 bytes (00b), please refer to Table 9 for Status Register 3 data and Figure 21 for
the sequence. In QPI mode, a cycle is two nibbles, or two clocks, long, most significant nibble first.
The instruction sequence is shown in Figure 21.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
Command 1 data byte
DI C0h D7 D6 D5 D4 D3 D2 D1 D0
*
High Impedance
DO
* = MSB
Figure 21. Write Status Register 3 Instruction Sequence Diagram
Figure 21.1 Write Status Register 3 Instruction Sequence Diagram in QPI mode
EN25QH64A
Page Program (PP) (02h) preliminary

The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the in-
struction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least
significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the same page (from the address whose 8 least
significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 22. If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor-
rectly within the same page. If less than 256 Data bytes are sent to device, they are correctly pro-
grammed at the requested addresses without having any effects on the other bytes of the same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven high, the self-timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page
Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
Figure 22. Page Program Instruction Sequence Diagram
EN25QH64A
preliminary
Figure 22.1 Program Instruction Sequence in QPI Mode
Quad Input Page Program (QPP) (32h)

The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed at
previously erased (FFh) memory locations using four pins: DQ0, DQ1, DQ2 and DQ3. The Quad Page
Program can improve performance for PROM Programmer and applications that have slow clock
speeds < 5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page
Program instruction since the inherent page program time is much greater than the time it take to clock-
in the data.
To use Quad Page Program (QPP) the WP# and HOLD#/RESET# Disable (WXDIS) bit in Status
Register must be set to 1. A Write Enable instruction must be executed before the device will accept the
Quad Page Program (QPP) instruction (SR.1, WEL=1). The instruction is initiated by driving the CS# pin
low then shifting the instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data
byte, into the IO pins. The CS# pin must be held low for the entire length of the instruction while data is
being sent to the device. All other functions of Quad Page Program (QPP) are identical to standard
Page Program. The Quad Page Program (QPP) instruction sequence is shown in Figure 23.
EN25QH64A
preliminary
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK
Command 3 Address bytes

(24 clocks)
DQ0 32h A23 A22 A21 A3 A2 A1 A0
*
DQ1
DQ2
DQ3
* = MSB
CS#
31 32 33 34 35 36 37 534 535 536 537 538 539 540 541 542 543
CLK
Data Data Data Data Data Data Data Data
Byte Byte Byte Byte Byte Byte Byte Byte
1 2 3 252 253 254 255 256
DQ0 A0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
DQ1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
* * * * * * * *
Figure 23. Quad Input Page Program Instruction Sequence Diagram (SPI Mode only)
EN25QH64A
preliminary
Sector Erase (SE) (20h)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the in-
struction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see
Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 24. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose du-
ration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-
timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) or Boot Lock feature will be ignored.
Figure 24. Sector Erase Instruction Sequence Diagram
32KB Half Block Erase (HBE) (52h)

The Half Block Erase (HBE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
The Half Block Erase (HBE) instruction is entered by driving Chip Select (CS#) Low, followed by the in-
struction code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see
Table 2) is a valid address for the Half Block Erase (HBE) instruction. Chip Select (CS#) must be driven
Low for the entire duration of the sequence.
bit of the last address byte has been latched in, otherwise the Half Block Erase (HBE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Half Block Erase cycle (whose
duration is tHBE) is initiated. While the Half Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during
the self-timed Half Block Erase cycle, and is 0 when it is completed. At some unspecified time before
the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Half Block Erase (HBE) instruction applied to a block which is protected by the Block Protect (BP3,
BP2, BP1, BP0) bits (see Table 3) or Boot Lock feature will be ignored.
EN25QH64A
The instruction sequence is shown in Figure 26.1 while using the Enable Quad preliminary
Peripheral Interface
mode (EQPI) (38h) command.
Figure 25. 32KB Half Block Erase Instruction Sequence Diagram
64K Block Erase (BE) (D8h)

The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see Table 2) is a
valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low for the entire
duration of the sequence.
bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose du-
ration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-
timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) or Boot Lock feature will be ignored.
EN25QH64A
preliminary
Figure 26. 64K Block Erase Instruction Sequence Diagram
Figure 26.1 Block/Sector Erase Instruction Sequence in QPI Mode
EN25QH64A
preliminary
Chip Erase (CE) (C7h/60h)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not executed. As
soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose duration is tCE) is
initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0
and EBL bit is 0. The Chip Erase (CE) instruction is ignored if one or more blocks are protected.
Figure 27. Chip Erase Instruction Sequence Diagram
EN25QH64A
preliminary
Figure 27.1 Chip Erase Sequence in QPI Mode
Deep Power-down (DP) (B9h)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest con-
sumption mode (the Deep Power-down mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep
Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce
the standby current (from ICC1 to ICC2, as specified in Table 17.)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down, Read Device ID (RDI) and Software Reset instruction which release
the device from this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction
also allows the Device ID of the device to be output on Serial Data Output (DO).
The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in
the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the
entire duration of the sequence.
bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not
executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP before the supply
current is reduced to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
EN25QH64A
preliminary
Figure 28. Deep Power-down Instruction Sequence Diagram
Release from Deep Power-down and Read Device ID (RDI)

Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes
the device out of the Deep Power-down mode.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that
is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for
reasons of backward compatibility, only, and should not be used for new designs. New designs should,
instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.
When used only to release the device from the power-down state, the instruction is issued by driving the
CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 29. After the
time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other
instructions will be accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 30. The Device ID value for the EN25QH64A are listed in Table 6. The Device ID can be read
continuously. The instruction is completed by driving CS# high.
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was
not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate.
If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power
mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2 (max), as
specified in Table 19. Once in the Stand-by Power mode, the device waits to be selected, so that it can
receive, decode and execute instructions.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep
Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the
device, and can be applied even if the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or
Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
EN25QH64A
preliminary
Figure 29. Release Power-down Instruction Sequence Diagram
Figure 30. Release Power-down / Device ID Instruction Sequence Diagram
Read Manufacturer / Device ID (90h)

The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Eon (1Ch)
and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in Figure 31. The Device ID values for the EN25QH64A are listed in Table 6. If the 24-bit address
is initially set to 000001h the Device ID will be read first
EN25QH64A
preliminary
Figure 31. Read Manufacturer / Device ID Diagram
Figure 31.1. Read Manufacturer / Device ID Diagram in QPI Mode
EN25QH64A
Read Identification (RDID) (9Fh) preliminary

The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read,
followed by two bytes of device identification. The device identification indicates the memory type in the
first byte , and the memory capacity of the device in the second byte .
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction
should not be issued while the device is in Deep Power down mode.
The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the instruction
is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out
on Serial Data Output , each bit being shifted out during the falling edge of Serial Clock . The instruction
sequence is shown in Figure 32. The Read Identification (RDID) instruction is terminated by driving Chip
Select High at any time during data output.
When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
Figure 32. Read Identification (RDID)
EN25QH64A
preliminary
Figure 32.1. Read Identification (RDID) in QPI Mode
Enter OTP Mode (3Ah)

This Flash support OTP mode to enhance the data protection, user can use the Enter OTP mode (3Ah)
command for entering this mode. In OTP mode, the Status Register S7 bit is served as OTP_LOCK bit,
S6 bit is served as WXDIS bit, S5 bit is served as HRSW bit, S4 bit is served as 64KB-Block/Sector
switch bit, S3 bit is served as TB bit, S1 bit is served as WEL bit and S0 bit is served as WIP bit. They
can be read by RDSR command.
This Flash has an extra 512 bytes OTP sector, user must issue ENTER OTP MODE command to read,
program or erase OTP sector. After entering OTP mode, the OTP sector is mapping to sector 2047,
SRP bit becomes OTP_LOCK bit. The Chip Erase, Block Erase and Half Block Erase commands are
also disabled.
In OTP mode, user can read other sectors, but program/erase other sectors only allowed when they are
not protected by Block Protect (BP3, BP2, BP1, BP0) bits and Block Lock feature. The OTP sector can
only be erased by Sector Erase (20h) command. The Chip Erase (C7h/ 60h), 64K Block Erase (D8h)
and 32K Half Block Erase (52h) commands are disable in OTP mode.
Table 10. OTP Sector Address
Sector Sector Size Address Range
2047 512 byte 7FF000h – 7FF1FFh
Note: The OTP sector is mapping to sector 2047
WRSR command is used to program OTP_LOCK bit, TB bit, 64KB-Block/Sector switch bit to ‘1‘, but
these bits only can be programmed once. User can use WRDI (04h) command to exit OTP mode.
EN25QH64A
preliminary
Figure 33. Enter OTP Mode
Figure 33.1 Enter OTP Mode Sequence in QPI Mode
EN25QH64A
preliminary
Read SFDP Mode and Unique ID Number (5Ah)
Read SFDP Mode

EN25QH64A features Serial Flash Discoverable Parameters (SFDP) mode. Host system can retrieve
the operating characteristics, structure and vendor specified information such as identifying information,
memory size, operating voltage and timing information of this device by SFDP mode.
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read SFDP
Mode is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum frequency FR, during the falling edge of
Serial Clock (CLK).
The whole memory can, therefore, be read with a single Serial Flash Discoverable Parameters (SFDP)
instruction. When the highest address is reached, the address counter rolls over to 0x00h, allowing the
read sequence to be continued indefinitely. The Serial Flash Discoverable Parameters (SFDP)
instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any
time during data output. Any Read Data Bytes at Serial Flash Discoverable Parameters (SFDP)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure 34. Read SFDP Mode Instruction Sequence Diagram
EN25QH64A
preliminary
Table 11. Serial Flash Discoverable Parameters (SFDP) Signature and Parameter Identification
Data Value (Advanced Information)
Address (h)
Description Address (Bit) Data Comment
(Byte Mode)
00h 07 : 00 53h
01h 15 : 08 46h Signature [31:0]:
SFDP Signature
02h 23 : 16 44h Hex: 50444653
03h 31 : 24 50h
SFDP Minor Revision Number 04h 07 : 00 00h Star from 0x00
SFDP Major Revision Number 05h 15 : 08 01h Star from 0x01
Number of Parameter Headers (NPH) 06h 23 : 16 00h 1 parameter header
Unused 07h 31 : 24 FFh Reserved
ID Number 08h 07 : 00 00h JEDEC ID
Parameter Table Minor Revision
09h 15 : 08 00h Star from 0x00
Number
Parameter Table Major Revision
0Ah 23 : 16 01h Star from 0x01
Number
Parameter Table Length (in DW) 0Bh 31 : 24 09h 9 DWORDs
0Ch 07 : 00 30h
Parameter Table Pointer (PTP) 0Dh 15 : 08 00h 000030h
0Eh 23 : 16 00h
Unused 0Fh 31 : 24 FFh Reserved
EN25QH64A
preliminary
Table 12. Parameter ID (0) (Advanced Information) 1/9
Address (h) Address

Description Data Comment
(Byte Mode) (Bit)
00 00 = reserved
Block / Sector Erase sizes
01 = 4KB erase
Identifies the erase granularity for all Flash 01b
10 = reserved
Components 01 11 = 64KB erase
Write Granularity 02 1b 0 = No, 1 = Yes
Write Enable Instruction Required for
30h 03 00 = N/A
Writing to Volatile Status Register
01b 01 = use 50h opcode
Write Enable Opcode Select for Writing to
04 11 = use 06h opcode
Volatile Status Register
05
Unused 06 111b Reserved
07
08
09
10
11 4 KB Erase Support
4 Kilo-Byte Erase Opcode 31h 20h
12 (FFh = not supported)
13
14
15
Supports (1-1-2) Fast Read
0 = not supported
Device supports single input opcode & address 16 1b
1 = supported
and dual output data Fast Read
00 = 3-Byte
17 01 = 3- or 4-Byte (e.g.
Address Byte defaults to 3-Byte
Number of bytes used in addressing for flash 00b mode; enters 4-Byte
array read, write and erase. 18 mode on command)
10 = 4-Byte
11 = reserved
Supports Double Data Rate (DDR) Clocking
0 = not supported
Indicates the device supports some type of 32h 19 0b
1 = supported
double transfer rate clocking.
0 = not supported
Device supports single input opcode, dual input 20 1b
1 = supported
address, and dual output data Fast Read
0 = not supported
Device supports single input opcode, quad 21 1b
1 = supported
input address, and quad output data Fast Read
0 = not supported
Device supports single input opcode & address 22 0b
1 = supported
and quad output data Fast Read
Unused 23 1b Reserved
24
25
26
27
Unused 33h FFh Reserved
28
29
30
31
EN25QH64A
Table 12. Parameter ID (0) (Advanced Information) 2/9 preliminary

Address (h) Address
(Byte Mode) (Bit)
Flash Memory Density 37h : 34h 31 : 00 3FFFFFFh 64 Mbits
Address (h) Address

(Byte Mode) (Bit)
00
(1-4-4) Fast Read Number of Wait states 01
(dummy clocks) needed before valid 02 1Fh Configurable
output 03
38h
04
05
Quad Input Address Quad Output (1-4-4)
06 010b 8 mode bits
Fast Read Number of Mode Bits
07
08
09
10
(1-4-4) Fast Read Opcode 11
Opcode for single input opcode, quad input 39h EBh
12
address, and quad output data Fast Read.
13
14
15
16
(dummy clocks) needed before valid 18 00000b Not supported
output 19
3Ah 20
21
(1-1-4) Fast Read Number of Mode Bits 22 000b Not supported
23
(1-1-4) Fast Read Opcode
Opcode for single input opcode & address 3Bh 31 : 24 6Bh
and quad output data Fast Read.
EN25QH64A

Address (h) Address
(Byte Mode) (Bit)
00
(dummy clocks) needed before valid 02 01000b 8 dummy clocks
output 03
3Ch
04
05
07
Opcode for single input opcode & address 3Dh 15 : 08 3Bh Not supported
and dual output data Fast Read.
16
(dummy clocks) needed before valid 18 00100b 4 dummy clocks
output 19
3Eh
20
21
23
Opcode for single input opcode, dual input 3Fh 31 : 24 BBh Not supported
address, and dual output data Fast Read.
Address (h) Address

(Byte Mode) (Bit)
0 = not supported
Device supports dual input opcode & 00 0b
1 = supported
address and dual output data Fast Read.
01
Reserved. These bits default to all 1’s 02 111b Reserved
03
40h
Supports (4-4-4) Fast Read 0 = not supported
Device supports Quad input opcode & 04 1b 1 = supported
address and quad output data Fast Read. (EQPI Mode)
05
Reserved. These bits default to all 1’s 06 111b Reserved
07
Reserved. These bits default to all 1’s 43h : 41h 31 : 08 FFh Reserved
EN25QH64A

Address (h) Address
(Byte Mode) (Bit)
16
(dummy clocks) needed before valid 18 00000b Not supported
output 19
46h 20
21
23
Opcode for dual input opcode & address 47h 31 : 24 FFh Not supported
and dual output data Fast Read.
Address (h) Address

(Byte Mode) (Bit)
16
(dummy clocks) needed before valid 18 1Fh Configurable
output 19
4Ah 20
21
(4-4-4) Fast Read Number of Mode Bits 22 010b 8 mode bits
23
Must Enter EQPI
Opcode for quad input opcode/address, 4Bh 31 : 24 EBh
Mode firstly
quad output data Fast Read.
Address (h) Address

(Byte Mode) (Bit)
Sector Type 1 Size 4Ch 07 : 00 0Ch 4 KB
Sector Type 1 Opcode 4Dh 15 : 08 20h
Sector Type 2 Size 4Eh 23 : 16 0Fh 32 KB
Sector Type 2 Opcode 4Fh 31 : 24 52h
Address (h) Address

(Byte Mode) (Bit)
Sector Type 3 Size 50h 07 : 00 10h 64 KB
Sector Type 3 Opcode 51h 15 : 08 D8h
Sector Type 4 Size 52h 23 : 16 00h Not Supported
Sector Type 4 Opcode 53h 31 : 24 FFh Not Supported
EN25QH64A
preliminary
Read Unique ID Number
The Read Unique ID Number instruction accesses a factory-set read-only 96-bit number that is unique
to each EN25QH64A device. The ID number can be used in conjunction with user software methods to
help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the
CS# pin low and shifting the instruction code “5Ah” followed by a three bytes of addresses, 0x80h, and
one byte of dummy clocks. After which, the 96-bit ID is shifted out on the falling edge of CLK.
Table 13. Unique ID Number
Address (h) Address

(Byte Mode) (Bit)
Unique ID Number 80h : 8Bh 95 : 00 By die
EN25QH64A
Power-up Timing preliminary

All functionalities and DC specifications are specified for a VCC ramp rate of greater than 1V per 100 ms
(0V to 2.7V in less than 270 ms). See Table 16 and Figure 35 for more information.
Figure 35. Power-up Timing
Table 14. Power-Up Timing
Symbol Parameter Min. Unit

(1)
TPU-READ VCC Min to Read Operation 100 µs
(1)
TPU-WRITE VCC Min to Write Operation 100 µs
Note:
1. This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
.
INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The
Status Register contains 00h (all Status Register bits are 0).
EN25QH64A
Table 15. DC Characteristics preliminary

(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ILI Input Leakage Current 1 ±2 µA

ILO Output Leakage Current 1 ±2 µA
CS# = VCC, VIN = VSS or
ICC1 Standby Current 20 µA
VCC
Deep Power-down CS# = VCC, VIN = VSS or
ICC2 20 µA
Current VCC
CLK = 0.1 VCC / 0.9 VCC at
10 25 mA
104MHz, DQ = open
5 12 mA
33MHz, DQ = open
ICC3 Operating Current (READ) CLK = 0.1 VCC / 0.9 VCC at
104MHz, Quad Output Read, 14 35 mA
DQ = open
33MHz, Quad Output Read, 7 17 mA
DQ = open
ICC4 Operating Current (PP) CS# = VCC 9 30 mA
ICC5 Operating Current CS# = VCC 25 mA

(WRSR)
ICC6 Operating Current (SE) CS# = VCC 13 25 mA
ICC7 Operating Current (BE) CS# = VCC 15 25 mA
VIL Input Low Voltage – 0.5 0.2 VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 100 µA, Vcc=Vcc Min. 0.3 V
IOH = –100 µA , Vcc=Vcc
VOH Output High Voltage VCC-0.2 V
Min.
Table 16. AC Measurement Conditions

Symbol Parameter Min. Max. Unit
CL Load Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Reference Voltages VCC / 2 V
Figure 36. AC Measurement I/O Waveform
EN25QH64A
Table 17. AC Characteristics preliminary

(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol Alt Parameter Min Typ Max Unit
Serial SDR SPI Clock Frequency for:
PP, QPP, SE, HBE, BE, CE, DP, RES, RDP, D.C. 104 MHz
WREN, WRDI, WRSR, WRSR3, Fast Read
Serial SDR SPI Clock Frequency for:
D.C. 104 MHz
RDSR, RDSR3, RDID
FR fC
Serial SDR Dual/Quad Clock Frequency for:
PP, QPP, SE, HBE, BE, CE, DP, RES, RDP,
WREN, WRDI, WRSR, WRSR3, RDSR, RDSR3, D.C. 104 MHz
RDID, Fast Read, Dual Output Fast Read,
Dual I/O Fast Read, Quad I/O Fast Read
fR Serial Clock Frequency for READ D.C. 83 MHz
tCH 1 Serial Clock High Time for SDR 3.5 ns
tCL1 Serial Clock Low Time for SDR 3.5 ns
tCLCH2 Serial Clock Rise Time (Slew Rate) 0.1 V / ns
tCHCL 2 Serial Clock Fall Time (Slew Rate) 0.1 V / ns
tSLCH tCSS CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL tCSH CS# High Time 30 ns
tSHSL2 tCSH Volatile Register Write Time 50 ns

tSHQZ 2 tDIS Output Disable Time 6 ns
tCLQX tHO Output Hold Time 0 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 3 ns
tHLCH HOLD# Low Setup Time ( relative to CLK ) 5 ns
tHHCH HOLD# High Setup Time ( relative to CLK ) 5 ns
tCHHH HOLD# Low Hold Time ( relative to CLK ) 5 ns
tCHHL HOLD# High Hold Time ( relative to CLK ) 5 ns
tCLQV tV Output Valid from CLK for SDR 7 ns
tWHSL 3
Write Protect Setup Time before CS# Low 20 ns
tSHWL 3
Write Protect Hold Time after CS# High 100 ns
tDP 2
CS# High to Deep Power-down Mode 3 µs
tRES1 2 CS# High to Standby Mode without Electronic

3 µs
Signature read
tRES2 2 CS# High to Standby Mode with Electronic
1.8 µs
Signature read
tW Write Status Register Cycle Time 10 50 ms
tPP Page Programming Time 0.5 3 ms
tSE Sector Erase Time 0.04 0.3 s
tHBE Half Block Erase Time 0.2 1 s
tBE Block Erase Time 0.3 2 s
tCE Chip Erase Time 30 100 s
tHRST RESET# low period to reset the device 1 µs
tHRSL RESET# high to next instruction 28 µs
tSHRV Deselect to RESET# valid in quad mode 8 ns
EN25QH64A
tSR Software Reset WIP = write operation preliminary

28 µs
Latency WIP = not in write operation 0 µs
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
Figure 37. Serial Output Timing
Figure 38. Input Timing
Figure 39. Hold Timing
EN25QH64A
preliminary
CS#
CLK
tSHRV
RESET#
tHRST
tHRSL
Figure 40. Reset Timing
ABSOLUTE MAXIMUM RATINGS

Stresses above the values so mentioned above may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions up
to or above these values. Exposure of the device to the maximum rating values for extended periods of
time may adversely affect the device reliability.
Parameter Value Unit

Storage Temperature -65 to +150 °C
Plastic Packages -65 to +125 °C
1
Output Short Circuit Current 200 mA
Input and Output Voltage

2 -0.5 to Vcc+0.5 V
(with respect to ground)
Vcc -0.5 to Vcc+0.5 V
Notes:
1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V.
During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods up to 20ns. See figure below.
RECOMMENDED OPERATING RANGES 1

Parameter Value Unit
Ambient Operating Temperature

-40 to 85 °C
Industrial Devices
Operating Supply Voltage

Full: 2.7 to 3.6 V
Vcc
Notes:
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
EN25QH64A
preliminary
Vcc
+1.5V
V
Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform
Table 18. CAPACITANCE
( VCC = 2.7-3.6V)
Parameter Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 pF
COUT Output Capacitance VOUT = 0 8 pF
Note : Sampled only, not 100% tested, at TA = 25°C and a frequency of 20MHz.
EN25QH64A
preliminary
PACKAGE MECHANICAL
Figure 41. SOP 200 mil ( official name = 208 mil )
DIMENSION IN MM
SYMBOL
MIN. NOR MAX
A 1.75 1.975 2.20
A1 0.05 0.15 0.25
A2 1.70 1.825 1.95
D 5.15 5.275 5.40
E 7.70 7.90 8.10
E1 5.15 5.275 5.40
e --- 1.27 ---
b 0.35 0.425 0.50
C 0.19 0.200 0.25
L 0.5 0.65 0.80
θ 00 40 80
Note : 1. Coplanarity: 0.1 mm
2. Max. allowable mold flash is 0.15 mm
at the pkg ends, 0.25 mm between leads.
EN25QH64A
preliminary
Figure 42. VDFN / WSON 8 ( 6x5mm )
DIMENSION IN MM
SYMBOL
MIN. NOR MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.04
A2 --- 0.20 ---
D 5.90 6.00 6.10
E 4.90 5.00 5.10
D2 3.30 3.40 3.50
E2 3.90 4.00 4.10
e --- 1.27 ---
b 0.35 0.40 0.45
L 0.55 0.60 0.65
Note: 1. Coplanarity: 0.1 mm
EN25QH64A
preliminary
Figure 43. PDIP8
DIMENSION IN INCH
SYMBOL
MIN. NOR MAX
A --- --- 0.210
A1 0.015 --- ---
A2 0.125 0.130 0.135
D 0.355 0.365 0.400
E 0.300 0.310 0.320
E1 0.245 0.250 0.255
L 0.115 0.130 0.150
eB 0.310 0.350 0.375
Θ0 0 7 15
EN25QH64A
preliminary
Figure 44. 16 LEAD SOP 300 mil
DIMENSION IN MM
SYMBOL
MIN. NOR MAX
A --- --- 2.65
A1 0.10 0.20 0.30
A2 2.25 --- 2.40
C 0.20 0.25 0.30
D 10.10 10.30 10.50
E 10.00 --- 10.65
E1 7.40 7.50 7.60
e --- 1.27 ---
b 0.31 --- 0.51
L 0.4 --- 1.27
θ 00 50 80
EN25QH64A
preliminary
Figure 45. 24-ball Thin Profile Fine-Pitch Ball Grid Array (6 x 8 mm) Package
DIMENSION IN MM
SYMBOL
MIN. NOR MAX
A --- --- 1.20
A1 0.27 --- 0.37
A2 0.21 REF
A3 0.54 REF
D 6 BSC
E 8 BSC
D1 --- 3.00 ---
E1 --- 5.00 ---
e --- 1.00 ---
b --- 0.40 ---
EN25QH64A
preliminary
Figure 46. VDFN / WSON 8 ( 8x6mm )
Notice:
1. This package can’t contact to metal

trace or pad on board due to expose
metal pad underneath the package.
2. Expose metal pad will be removed
from new assembly parts from 2019.
DIMENSION IN MM
SYMBOL
MIN. NOR MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A2 --- 0.20 ---
D 7.90 8.00 8.10
E 5.90 6.00 6.10
D1 3.35 3.40 3.45
E1 4.25 4.30 4.35
e --- 1.27 ---
b 0.35 0.40 0.48
L 0.4 0.50 0.60
EN25QH64A
preliminary
Figure 47. VDFN / WSON 8 ( 8x6mm ) without Expose metal pad
Pin# 1 index side

D
A
E
A1
DETAIL A
"A"
b
e
DETAIL B
"B"
Symbol Dimension in mm Dimension in inch

Min Min Min Min Norm Max
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.35 0.40 0.45 0.014 0.016 0.018
D 7.90 8.00 8.10 0.311 0.315 0.319
E 5.90 6.00 6.10 0.232 0.236 0.240
e 1.27 BSC 0.050 BSC
L 0.40 0.50 0.60 0.016 0.020 0.024
Controlling dimension : millimeter

(Revision date : Apr 25 2018)
EN25QH64A
preliminary
Figure 48. USON (8L 4x3x0.55 mm )
Pin#1 index side

D
A
E
A2
A1
"A" DETAIL A
L
D1 D2
E1
D3 D4
b
"B"
DETAIL B
e
Symbol Dimension in mm Dimension in inch

Min Min Min Min Norm Max
A 0.50 0.55 0.60 0.020 0.022 0.024
A1 0.00 0.02 0.05 0.000 0.001 0.002
A2 -- 0.15 -- -- 0.006 --
b 0.25 0.30 0.35 0.010 0.012 0.014
D 3.90 4.00 4.10 0.154 0.157 0.161
D1 0.70 0.80 0.90 0.028 0.031 0.035
D2 0.70 0.80 0.90 0.028 0.031 0.035
D3 0.70 0.80 0.90 0.028 0.031 0.035
D4 0.70 0.80 0.90 0.028 0.031 0.035
E 2.90 3.00 3.10 0.114 0.118 0.122
E1 0.10 0.20 0.30 0.004 0.008 0.012
e 0.80 BSC 0.031 BSC
L 0.55 0.60 0.65 0.022 0.024 0.026
Controlling dimension : millimeter
(Revision date : Apr 25 2018)
EN25QH64A
preliminary
ORDERING INFORMATION
EN25QH64A - 104 H I P
PACKAGING CONTENT
P = RoHS, Halogen-Free and REACH compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
H = 8-pin 200mil SOP
W = 8-pin VDFN / WSON (6x5mm)
Q = 8-pin PDIP
F = 16-pin 300mil SOP
BB = 24-ball TFBGA (6 x 8 x 1.2mm)
Y = 8-pin VDFN / WSON (8x6mm)
XB = 8 contact USON (4x3x0.55mm)
SPEED
104 = 104 MHz
BASE PART NUMBER

EN = Eon Silicon Solution Inc.
25QH = 3V Serial Flash with 4KB Uniform-Sector
64 = 64 Megabit (8192K x 8)
A = version identifier
EN25QH64A
Revisions List preliminary
Revision No Description Date

A Initial Release 2014/10/01
1. Add RESET# pin
2. Add Quad Output Fast Read (6Bh) command
3. Add write volatile register (50h) command
4. Remove burst read (0Ch) command
5. Remove write status register-2 (07h) command
6. Modify status register bit locations(SR6, SR5, SR4, SR3, SR2)
7. Add dummy setting for fast read (0Bh) command while in QPI mode
B (Table 5E) 2015/08/13
8. Remove DPB bits at SR2.1
9. Remove burst length bits at SR3.1, SR3.0
10. Modify dummy byte at SR3.4, SR3.5
11. Modify tPP, tSE, tBE typical time and tSE max time
12. Modify power up timing at Figure 28 and Table 15
13. Add read current(Icc3) for 133Mhz
14. Modify figure 29. AC measurement I/O waveform
C 1. Modify 133Mhz to 104Mhz 2015/10/26
D Add VDFN 6x8mm 2015/11/18
E Modify the tail 2016/03/24
1. Delete "Write Suspend and Write Resume" and "Read Status
Register 2 (RDSR2)" function
F 2017/03/31
2. Modify the specification output driving strength
3 Modify the specification of tSHSL
G Modify VDFN 8 ( 6x8 mm) PACKING DIMENSIONS 2018/01/24
H Add 8-contact USON (8L 4x3x0.55 mm ) package 2018/08/23
1. Modify the packing dimension of SOP 200 mil ( official name = 208 mil )
I 2. Modify the packing dimension of VDFN/WSON 8 ( 6x8 mm )
2018/12/13

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EN25QH64A

Figure.1 CONNECTION DIAGRAMS preliminary

DO (DQ1) 2 7 HOLD#/RESET# (DQ3)

8 - LEAD SOP / PDIP

DO (DQ1) 2 7 HOLD#/RESET# (DQ3)

WP# (DQ2) 3 6 CLK

8 - LEAD VDFN / WSON

Symbol Pin Name

CS# CLK DI (DQ0) DO (DQ1) WP# (DQ2) HOLD# / RESET#

Serial Clock (CLK)

Chip Select (CS#)

Write Protect (WP#)

64K 32K 64K 32K

37 303 012F000h 012FFFFh 5 47 002F000h 002FFFFh

Standard SPI Modes

Figure 3. SPI Modes

Dual SPI Instruction

Quad I/O SPI Modes

Full Quad SPI Modes (QPI)

Figure 5. Full Quad SPI Modes

Status Register Content Memory Content

The bits’ definitions are described in the following table.

Table 4. The Enable Boot Lock feature

Instruction Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes

Address Dummy bits / Clocks

Table 5C. Instruction Set (Program Instruction)

Address Dummy bits Clocks

Table 5D. Instruction Set (Erase Instruction)

Address Dummy bits Clocks

Sector Erase (SE) 20h 24 bits 0 (D7-D0, …)

32K Half Block

Table 6. Manufacturer and Device Identification

OP Code (M7-M0) (ID15-ID0) (ID7-ID0)

90h 1Ch 16h

9Fh 1Ch 7017h

Reset-Enable (RSTEN) (66h) and Reset (RST) (99h)

Figure 6. Reset-Enable and Reset Sequence Diagram

Figure 6.1 . Reset-Enable and Reset Sequence Diagram in QPI Mode

Software Reset Flow preliminary

Enable Quad Peripheral Interface mode (EQPI) (38h) preliminary

Figure 7. Enable Quad Peripheral Interface mode Sequence Diagram

Reset Quad I/O (RSTQIO) (FFh)

Write Enable (WREN) (06h)

Figure 8. Write Enable Instruction Sequence Diagram

Volatile Status Register Write Enable (50h)

Figure 9. Volatile Status Register Write Enable Instruction Sequence Diagram

Write Disable (WRDI) (04h) preliminary

Figure 10. Write Disable Instruction Sequence Diagram

Figure 10.1 Write Enable/Disable Instruction Sequence in QPI Mode

Figure 11. Read Status Register Instruction Sequence Diagram

Figure 11.1 Read Status Register Instruction Sequence in QPI Mode

SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0

Table 7.1 Status Register Bit Locations (In Normal mode)

SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0

1 = Lock selected 1 = write enable 1 = write operation

Non-volatile/ Non-volatile/ Non-volatile/ Non-volatile/ Non-volatile/ Non-volatile/

Table 7.2 Status Register Bit Locations (In OTP mode)

SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0