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KSZ8041NL Eval Board Revision 1.0

REVISION HISTORY Table of Contents

D D

PAGE 01: Revision History

DATE DESCRIPTION REVISION PAGE 02: KSZ8041NL Board -- Block Diagram
PAGE 03: KSZ8041NL Device
1/4/07 Initial Release 1.0

4/27/07 Added 100pF capacitor (C53) on REXT (pin 10) of KSZ8041NL. 1.1

C C

B B

A A

CONFIDENTIAL & PROPRIETARY

Title
KSZ8041NL Eval Board
Size Document Number Rev
Revision History 1.1

Date: Friday, April 27, 2007 Sheet 1 of 3

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KSZ8041NL EVAL BOARD - BLOCK DIAGRAM

D D

3.3V
LDO 5V DC
INPUT

C C

MII / RMII Port Connector

KSZ8041NL
TX / RX pairs MII / RMII
Signals

10Base-T / 100Base-TX
Integrated Magnetic RJ-45 Jack
25 MHz XTAL
(MII mode)
B B

50 MHz REF_CLK from MAC

(RMII mode)
Port Status
LED RESET Configuration
Indicators Headers

A A

CONFIDENTIAL & PROPRIETARY

Title
KSZ8041NL Eval Board
Size Document Number Rev
KSZ8041NL Board -- Block Diagram 1.1

Date: Friday, April 27, 2007 Sheet 2 of 3

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Notes: 3.3V_NL STEWARD

3.3A_NL 3.3V_NL R1 100K 5V_NL
HI1206N101R-00
Power_ON +5V DC
1. KSZ8041NL has a Paddle Ground on bottom side of chip. Reset U2 Power Input
FB1
Refer to datasheet for mechanical dimensions.
Push 2 1 5 OUT VIN 1

2
2. KSZ8041NL provides the 1.8VPLL supply for VDDPLL_1.8 Button
3.3A_NL R2 D1 FBEAD 2
(pin 2). Decouple 1.8VPLL power rail as shown. GND
Reset + +
3. Place components (Y1, C16, C17, C53, R14, R15) and (R10, 10K 1N4148 + 4 3
S1 C4 C1 BYP EN C5 C2
R11, R12, R13, C13, C15) close to respective pins of U1. C3 0.1uF 47uF 0.1uF 47uF

1
1 2
D + 3 4 22uF MIC5216-3.3BM5 D

SW PUSHBUTTON + C8 C7
C6 10uF 0.1uF
10uF
J1
RJ-45
TDK TLA-6T718 Magnetic Jack 3.3V_NL
TX+_NL
3.3A_NL 1.8VPLL_NL LED0_NL
TD+ 1
LED1_NL TP1 R3
CT 3
4.7K
1 TX-_NL RST#_NL
2 +
2 TD-
3 RX+_NL C10 C9 C11
J2

32
31
30
29
28
27
26
25
4 RD+ 4
0.1uF 10uF 0.1uF 20 40
5 CRS_NL VCC VCC
6 R4 33 19 39

CRS
RST#
LED1
LED0

COL
TXD3
TXD2
TXD1
6 CT COL_NL CRS NC
R5 33 18 38
7 RX-_NL TXD3_NL COL NC
8 RD- 5 17 TXD3 NC 37
TXD2_NL 16 36
TXD1_NL TXD2 NC
75 75 75 75 15 35
TXD0_NL TXD1 NC
NC 7 1 GND TXD0 24 14 TXD0 NC 34
TXEN_NL
SHIELD
SHIELD

2 VDDPLL_1.8 TXEN 23 13 TX_EN NC 33

8 3 22 TXC_NL R6 33 12 32
CHS_GND RX-_NL VDDA_3.3 TXC INTRP_NL TX_CLK NC
1000pF 4 RX- INTRP 21 11 TX_ER NC 31
RX+_NL 5 20 RXER_NL R7 33 10 30
TX-_NL RX+ RXER RXC_NL R8 33 RX_ER NC
6 19 9 29
10

TX+_NL TX- RXC RXDV_NL R9 33 RX_CLK NC

9

C 7 TX+ RXDV 18 8 RX_DV NC 28 C

CHASSIS_GND_NL 8 17 7 27
XO VDDIO_3.3 RXD0 NC
6 RXD1 NC 26
C12 5 25
C13 RXD2 NC
TX+_NL
3.3V_NL 4 RXD3 NC 24

RXD3
RXD2
RXD1
RXD0
REXT
MDIO
0.1uF R10 49.9 0.1uF 3 23

MDC
MDC NC
2 22

XI
R11 49.9 TX-_NL MDIO NC
1 VCC VCC 21
C14 XO_NL

10
11
12
13
14
15
16
C15

9
1000pF / 2kV 0.1uF R12 49.9 RX+_NL XI_NL
U1 Male MII Connector

R13 49.9 RX-_NL C16 C17

KSZ8041NL MII / RMII Port
SIGNAL_GND_NL
3.3V_NL
22pF
Y1 22pF
25MHz C53 R15
RXD0_NL R16 33 TP2 TP3
100pF 6.49K RXD1_NL R17 33 R18 R19
RXD2_NL R20 33
RXD3_NL R21 33 4.7K NC
Place SIGNAL_GND return of C14 Route both traces of each differential pair MDC_NL
MDIO_NL
close to SIGNAL_GND at 5V input as identical to each other as possible at 6mil
power to board. width/6mil parallel spacing, and at least 18
mils away from all other signals.
R14 NC

B C53 is an additional component to the PCB. B

Rework C53 in parallel with R15 (as shown) at

LED Mode
[00] [01]
location R15 of PCB.
LED0 LINK/ACT LINK

LED1 SPEED ACT

RMII Mode (option) KSZ8041NL KSZ8893MQL 3.3V_NL
Strapping Options (Refer to Datasheet for descriptions) 3.3V_NL PHY RMII Signals MAC RMII Signals
The RMII signal connections between KSZ8041NL LED1
PHY and external MAC are shown in the table to Name Pin # Type Name Type
PHYAD0 RXD3_NL J3 JUMPER R23 1K 1 2 R22 220 LED0_NL
the right.
PHYAD1 RXD2_NL J4 JUMPER R25 4.7K REFCLK 9 Input REF_CLK Input 3 4 R24 220 LED1_NL

PHYAD2 RXD1_NL J5 JUMPER R26 4.7K For RMII mode,

TX_EN 23 Input CRS_DV Output LEDx2

CONFIG0 COL_NL J6 JUMPER R27 4.7K

1. Remove crystal circuit (Y1, C16, C17) and TXC
termination (R6). TXD[1] 25 Input RXD[1] Output
CONFIG1 CRS_NL J7 JUMPER R28 4.7K

CONFIG2 RXDV_NL J8 JUMPER R29 4.7K 2. Populate R14 with 0 Ohm and R19 with 33 Ohm TXD[0] 24 Input RXD[0] Output
to connect 50MHz Reference Clock (provided by
A A
ISO RXER_NL J9 JUMPER R30 4.7K
MAC side via J2 pin 12) to U1 pin 9 (XI input).
CRSDV 18 Output TX_EN Input

NWAYEN LED0_NL J10 JUMPER R31 1K

3. Select RMII mode by setting strapping pins CONFIDENTIAL & PROPRIETARY
RXD[1] 15 Output TXD[1] Input
CONFIG[2:0] to '001'.
SPEED LED1_NL J11 JUMPER R32 1K
RXD[0] 16 Output TXD[0] Input Title
DUPLEX RXD0_NL J12 JUMPER R33 1K
4. Connect J2 (RMII Port) to board with RMII MAC
(e.g. Micrel KSZ8893MQL Eval Board).
KSZ8041NL Eval Board
RX_ER 20 Output TX_ER Input Size Document Number Rev
KSZ8041NL Device 1.1

Date: Friday, April 27, 2007 Sheet 3 of 3

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