Tas 5630
Tas 5630
Tas 5630
1FEATURES APPLICATIONS
23 • PurePath™ HD Enabled Integrated Feedback • Mini Combo System
Provides: • AV Receivers
– Signal Bandwidth up to 80 kHz for • DVD Receivers
High-Frequency Content From HD Sources • Active Speakers
– Ultralow 0.03% THD at 1 W into 4 Ω
– Flat THD at all Frequencies for Natural DESCRIPTION
Sound The TAS5630 is a high-performance analog-input
– 80-dB PSRR (BTL, No Input Signal) class-D amplifier with integrated closed-loop
feedback technology (known as PurePath HD
– >100-dB (A-weighted) SNR
technology) with the ability to drive up to 300 W (1)
– Click- and Pop-Free Start-Up stereo into 4-Ω to 8-Ω speakers from a single 50-V
• Multiple Configurations Possible on the Same supply.
PCB With Stuffing Options: PurePath HD technology enables traditional
– Mono Parallel Bridge-Tied Load (PBTL) AB-amplifier performance (<0.03% THD) levels while
– Stereo Bridge-Tied Load (BTL) providing the power efficiency of traditional class-D
amplifiers.
– 2.1 Single-Ended Stereo Pair and
Bridge-Tied Load Subwoofer Unlike traditional class-D amplifiers, the distortion
curve only increases once the output levels move into
– Quad Single-Ended Outputs
clipping. PurePath HD™
• Total Output Power at 10% THD+N
PurePath HD technology enables lower idle losses,
– 600 W in Mono PBTL Configuration making the device even more efficient. Coupled with
– 300 W per Channel in Stereo BTL TI’s class-G power-supply reference design for
Configuration TAS563x, industry-leading levels of efficiency can be
– 145 W per Channel in Quad Single-Ended achieved.
Configuration 3 ´ OPA1632
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PurePath HD is a trademark of Texas Instruments.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TAS5630
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
The TAS5630 is available in two thermally enhanced packages:
• 64-Pin QFP (PHD) power package
• 44-Pin PSOP3 package (DKD)
The package types contain heat slugs that are located on the top side of the device for convenient thermal
coupling to the heat sink.
PHD PACKAGE DKD PACKAGE
(TOP VIEW) (TOP VIEW)
PSU_REF
GVDD_B
GVDD_A
PVDD_A
PVDD_A
GND_A
OUT_A
OUT_A
BST_A
GND
GND
VDD
NC
NC
NC
NC
PSU_REF 1 44 GVDD_AB
VDD 2 43 BST_A
OC_ADJ 3 42 PVDD_A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RESET 4 41 PVDD_A
OC_ADJ 1 48 GND_A
RESET C_STARTUP 5 40 OUT_A
2 47 GND_B
C_STARTUP 3 46 GND_B INPUT_A 6 39 OUT_A
INPUT_A 4 45 OUT_B INPUT_B 7 38 GND_A
INPUT_B 5 44 OUT_B VI_CM 8 37 GND_B
VI_CM 6 43 PVDD_B
GND 9 36 OUT_B
44 pins PACKAGE
GND 7 42 PVDD_B
AGND 8 41 BST_B AGND 10 35 PVDD_B
(TOP VIEW)
VREG 9 40 BST_C VREG 11 34 BST_B
INPUT_C 10 39 PVDD_C
INPUT_D 11 38 PVDD_C INPUT_C 12 33 BST_C
FREQ_ADJ 12 37 OUT_C INPUT_D 13 32 PVDD_C
OSC_IO+ 13 36 OUT_C FREQ_ADJ 14 31 OUT_C
OSC_IO- 14 35 GND_C
SD 15 34 GND_C OSC_IO+ 15 30 GND_C
64-pins QFP package
OTW1 16 33 GND_D OSC_IO- 16 29 GND_D
26
17
18
19
20
21
22
23
24
25
27
28
29
30
31
32
SD 17 28 OUT_D
OTW 18 27 OUT_D
READY 19 26 PVDD_D
OTW2
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
CLIP
M1 20 25 PVDD_D
M2 21 24 BST_D
M3 22 23 GVDD_CD
Electrical Pin 1
Pin 1 Marker
White Dot
(1) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND).
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
(3) Failure to follow good anti-static ESD handling during manufacture and rework contributes to device malfunction. Ensure operators
handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
PIN FUNCTIONS
PIN
Function (1) DESCRIPTION
NAME PHD NO. DKD NO.
AGND 8 10 P Analog ground
BST_A 54 43 P HS bootstrap supply (BST), external 0.033-mF capacitor to OUT_A required.
BST_B 41 34 P HS bootstrap supply (BST), external 0.033-mF capacitor to OUT_B required.
BST_C 40 33 P HS bootstrap supply (BST), external 0.033-mF capacitor to OUT_C required.
BST_D 27 24 P HS bootstrap supply (BST), external 0.033-mF capacitor to OUT_D required.
CLIP 18 — O Clipping warning; open drain; active-low
C_STARTUP 3 5 O Start-up ramp requires a charging capacitor of 4.7 nF to AGND in BTL mode
FREQ_ADJ 12 14 I PWM frame-rate-programming pin requires resistor to AGND
7, 23, 24, 57,
GND 9 P Ground
58
GND_A 48, 49 38 P Power ground for half-bridge A
GND_B 46, 47 37 P Power ground for half-bridge B
GND_C 34, 35 30 P Power ground for half-bridge C
GND_D 32, 33 29 P Power ground for half-bridge D
GVDD_A 55 — P Gate-drive voltage supply requires 0.1-mF capacitor to GND_A
GVDD_B 56 — P Gate drive voltage supply requires 0.1-mF capacitor to GND_B
GVDD_C 25 — P Gate drive voltage supply requires 0.1-mF capacitor to GND_C
GVDD_D 26 — P Gate drive voltage supply requires 0.1-mF capacitor to GND_D
GVDD_AB — 44 P Gate drive voltage supply requires 0.22-mF capacitor to GND_A/GND_B
GVDD_CD — 23 P Gate drive voltage supply requires 0.22-mF capacitor to GND_C/GND_D
INPUT_A 4 6 I Input signal for half-bridge A
INPUT_B 5 7 I Input signal for half-bridge B
INPUT_C 10 12 I Input signal for half-bridge C
INPUT_D 11 13 I Input signal for half-bridge D
M1 20 20 I Mode selection
M2 21 21 I Mode selection
M3 22 22 I Mode selection
NC 59–62 – — No connect; pins may be grounded.
Analog overcurrent-programming pin requires resistor to AGND. 64-pin
OC_ADJ 1 3 O
package (PHD) = 22 kΩ. 44-pin PSOP3 (DKD) = 24 kΩ
OSC_IO+ 13 15 I/O Oscillator master/slave output/input
OSC_IO– 14 16 I/O Oscillator master/slave output/input
OTW — 18 O Overtemperature warning signal, open-drain, active-low
OTW1 16 — O Overtemperature warning signal, open-drain, active-low
OTW2 17 — O Overtemperature warning signal, open-drain, active-low
OUT_A 52, 53 39, 40 O Output, half-bridge A
OUT_B 44, 45 36 O Output, half-bridge B
OUT_C 36, 37 31 O Output, half-bridge C
OUT_D 28, 29 27, 28 O Output, half-bridge D
PSU_REF 63 1 P PSU reference requires close decoupling of 330 pF to AGND.
Power-supply input for half-bridge A requires close decoupling of 0.01-mF
PVDD_A 50, 51 41, 42 P
capacitor in parallel with 2.2-mF capacitor to GND_A.
Power-supply input for half-bridge B requires close decoupling of 0.01-mF
PVDD_B 42, 43 35 P
capacitor in parallel with 2.2-mF capacitor to GND_B.
Power-supply input for half-bridge C requires close decoupling of 0.0- mF
PVDD_C 38, 39 32 P
capacitor in parallel with 2.2-mF capacitor to GND_C.
/RESET
PSU_REF
VI_CM
/CLIP
READY
C_STARTUP
/SD
Synchronization Bootstrap
OSC_IO-
BST_B Caps
nd
INPUT_A OUT_A 2 Order
ANALOG_IN_A Input DC L-C Output
Input Output 2
Blocking Filter for
INPUT_B H-Bridge 1 H-Bridge 1 OUT_B
ANALOG_IN_B Caps each
2
H-Bridge
Hardwire
PWM Frame 2-CHANNEL
Rate Adjust
FREQ_ADJ
H -BRIDGE
& BTL MODE
Master/Slave
Mode
nd
INPUT_C 2 Order
ANALOG_IN_C Input DC OUT_C
Input Output L-C Output
Blocking 2
Filter for
INPUT_D H-Bridge 2 H-Bridge 2 OUT_D
ANALOG_IN_D Caps each
2
H-Bridge
M1 BST_C
GVDD_A, B, C, D
PVDD_A, B, C, D
Hardwire
GND_A, B, C, D
M2 Bootstrap
Mode
M3 BST_D Caps
OC_ADJ
Control
VREG
AGND
GND
VDD
8 8 4
VAC
/CLIP
READY
/OTW1
/OTW2
/SD
M1
M3
POWER-UP
UVP VREG VREG
RESET
/RESET
AGND
TEMP GVDD_A GVDD _C
STARTUP SENSE
GND
CONTROL GVDD_B GVDD_D
C_STARTUP
OVER-LOAD CURRENT
CB3C OC_ADJ
PROTECTION SENSE
OSC_SYNC_IO+
4
OSC_SYNC_IO- OSCILLATOR PVDD_X
4
PPSC OUT_X
4
FREQ_ADJ GND_X
GVDD_A
PWM
ACTIVITY BST_A
DETECTOR
4
PSU_REF PVDD_X PVDD_A
PSU_FF
VI_CM GND
PWM TIMING
CONTROL GATE-DRIVE OUT_A
RECEIVER CONTROL
GND_A
GVDD_B
-
BST_B
ANALOG
LOOP FILTER
+
INPUT_A
PVDD_B
+ PWM TIMING
CONTROL GATE-DRIVE OUT_B
ANALOG RECEIVER CONTROL
LOOP FILTER
-
INPUT_B
GND_B
ANALOG COMPARATOR MUX
ANALOG INPUT MUX
GVDD_C
BST_C
-
INPUT_C PVDD_C
ANALOG
LOOP FILTER +
PWM TIMING
CONTROL GATE-DRIVE OUT_C
RECEIVER CONTROL
+
INPUT_D GND_C
ANALOG
LOOP FILTER
-
GVDD_D
BST_D
PVDD_D
PWM TIMING
CONTROL GATE-DRIVE OUT_D
RECEIVER CONTROL
GND_D
ELECTRICAL CHARACTERISTICS
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG VDD = 12 V 3 3.3 3.6 V
node, VREG
VI_CM Analog comparator reference node, VI_CM 1.5 1.75 1.9 V
Operating, 50% duty cycle 22.5
IVDD VDD supply current mA
Idle, reset mode 22.5
50% duty cycle 12.5
IGVDD_X GVDD_x gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle with recommended output
13.3 mA
IPVDD_X Half-bridge supply current filter
Reset mode, No switching 870 mA
ANALOG INPUTS
RIN Input resistance READY = HIGH 33 kΩ
VIN Maximum input voltage swing 5 V
IIN Maximum input current 342 mA
G Voltage gain (VOUT/VIN) 23 dB
OSCILLATOR
Nominal, master mode 3.85 4 4.15
fOSC_IO+ AM1, master mode FPWM × 10 3.15 3.33 3.5 MHz
AM2, master mode 2.6 3 3.35
VIH High level input voltage 1.86 V
VIL Low level input voltage 1.45 V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) TJ = 25°C, excludes metallization 60 100 mΩ
RDS(on)
Drain-to-source resistance, high side (HS) resistance, GVDD = 12 V 60 100 mΩ
5 THD+N at 10%
300 4W
280
2 260
PO - Output Power - W
1 240
220 6W
0.5 200
180 8W
0.2 4W 160
140
0.1 6W
120
0.05 100
80
0.02 8W 60
40
0.01
20
0.005 0
20m 100m200m 1 2 5 10 20 50 100 400 25 30 35 40 45 50
PO - Output Power - W PVDD - Supply Voltage - V
Figure 1. Figure 2.
70
200 65
6W
Efficiency - %
180 60
160 55
50
140 8W
45
120 40
100 35
30
80 25
60 20
15 TC = 25°C
40
10 THD+N at 10%
20 5
0 0
25 30 35 40 45 50 0 100 200 300 400 500 600 700
PVDD - Supply Voltage - V 2 Channel Output Power - W
Figure 3. Figure 4.
PO - Output Power - W
55 240
220
Power Loss - W
50 8W
200
45
180
40 6W
160
35
140
30
120
25 100
20 80
15 60
10 8W 40 THD+N at 10%
5 20
0 0
0 100 200 300 400 500 600 10 20 30 40 50 60 70 80 90 100 110 120
2 Channel Output Power - W TC - Case Temperature - °C
Figure 5. Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
+0
-10 TC = 75°C,
-20 VREF = 31.9 V,
-30 Sample Rate = 48 kHz,
FFT Size = 16384
-40
Noise Amplitude - dB
-50
-60
-70
-80
-90
-100
-110
-120
-130 4W
-140
-150
-160
0k 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k
f - Frequency - Hz
Figure 7.
160 TC = 75°C
5 4W
150 THD+N at 10%
2W
140
2 3W 130
PO - Output Power - W
1 120 3W
110
0.5 2W
100
90 4W
0.2 80
0.1 70
60
0.05 50
40
0.02 30
20
0.01
10
0.005 0
20m 200m 1 2 5 10 20 50 100 25 30 35 40 45 50
PO - Output Power - W PVDD - Supply Voltage - V
Figure 8. Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
180
170 2W
160
150
140
130 3W
PO - Output Power - W
120
110
100
90
80
70 4W
60
50
40
30
20 THD+N at 10%
10
0
10 20 30 40 50 60 70 80 90 100 110 120
TC - Case Temperature - °C
Figure 10.
TC = 75°C TC = 75°C
5 2W 600 2W
THD+N at 10%
550
3W
2 3W
500
PO - Output Power - W
1 4W 450
4W
0.5 400
6W 6W
350
0.2 8W 8W
300
0.1 250
0.05 200
150
0.02
100
0.01 50
0.005 0
20m 100m 200m 1 2 5 10 20 50 100 200 700 25 30 35 40 45 50
PO - Output Power - W PVDD - Supply Voltage - V
Figure 11. Figure 12.
OUTPUT POWER
vs
CASE TEMPERATURE
700
650 2W THD+N at 10%
600
550
500
PO - Output Power - W
3W
450
400 4W
350
300
6W
250
8W
200
150
100
50
0
10 20 30 40 50 60 70 80 90 100 110 120
TC - Case Temperature - °C
Figure 13.
APPLICATION INFORMATION
GVDD/VDD (+12V)
R30 PVDD
C64
3.3R
R31 1000uF
C40
33nF
3.3R
C25 C26 L10
10uF 100nF 7uH GND
C30 C31 OUT_LEFT_M
100nF 100nF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
GND 10nF
R19 -
NC
NC
NC
NC
R18 47k
VDD
GND
GND
BST_A
/RESET
OUT_A
OUT_A
GND_A
+
PVDD_A
PVDD_A
GVDD_B
GVDD_A
PSU_REF
100R C18 C75 GND
OSC_IO+
-
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
C77 GND +
10nF
/SD
17
18
19
20
21
22
23
24
25
26
28
29
30
31
32
27
GND
/OTW1
C63 C53 C73 R73
/OTW2
2.2uF 680nF 1nF 3.3R
L13
/CLIP
GND 7uH
READY
OUT_RIGHT_P
VREG
PVDD
C43 C67
33nF 1000uF
R32
GND
3.3R GND
R33
GVDD/VDD (+12V)
3.3R
C33 C32
100nF 100nF
GND GND
17
18
TAS5630
3.3R
VDD (+12V) GVDD (+12V)
3.3R
PVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
100pF GND
1000uF
NC
NC
NC
NC
63V
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010
VDD
GND
GND
BST_A
OUT_A
OUT_A
GND_A
PVDD_A
PVDD_A
GVDD_B
GVDD_A
PSU_REF
GND 22.0k
GND
100R 1 48
OC_ADJ GND_A
IN_P GND 4.7nF 2 47
10uF /RESET GND_B OUT_LEFT_M
100pF
3 C_STARTUP GND_B 46
GND 7uH
GND 4 45
INPUT_A OUT_B
3.3R
100R GND 5 44
INPUT_B OUT_B 1uF
2.2uF
IN_N 33nF
6 43 100V 250V
10uF VI_CM PVDD_B
100pF
1nF 7 42 1nF 10nF
GND PVDD_B
GND 100V 100V
100nF VREG 8 41 -
AGND BST_B
GND
GND 9
TAS5630PHD 40
VREG BST_C
VREG +
GND 10 39 GND 1nF 10nF GND
INPUT_C PVDD_C
100V 100V
11 INPUT_D PVDD_C 38
10k 2.2uF 1uF
33nF
12 37 100V 250V
FREQ_ADJ OUT_C
GND 7uH
3.3R
13 OSC_IO+ OUT_C 36
GND
14 35
OSC_IO- GND_C
15 34 OUT_LEFT_P
/SD GND_C
GND
16 33
/OTW1 GND_D
1000uF
63V
17
18
19
20
21
22
23
24
25
26
28
29
30
31
32
27
OSC_IO+
OSC_IO-
2.2uF GND
100V
/SD PVDD
GND GND
1000uF
/OTW1
VREG 7uH 63V
/OTW2
33nF
/CLIP
3.3R GND
READY
3.3R
GVDD (+12V)
100nF 100nF
GND GND
Figure 15. Typical Differential (2N) PBTL Application With BD Modulation Filters
www.ti.com
3.3R
GVDD (+12V)
100nF 100nF
10uF 100nF 33nF 15uH
A
www.ti.com
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
100pF GND
NC
NC
NC
NC
VDD
GND
GND
BST_A
OUT_A
OUT_A
GND_A
PVDD_A
PVDD_A
GVDD_B
GVDD_A
PSU_REF
GND 22.0k
100R 1 48
OC_ADJ GND_A
IN_A 10nF
GND 2 47
10uF /RESET GND_B
100pF
3 46
C_STARTUP GND_B GND 15uH
GND 4 45
INPUT_A OUT_B B
100R GND 5 44
INPUT_B OUT_B
IN_B 2.2uF 33nF
6 43
10uF VI_CM PVDD_B
100pF
1nF 7 42
GND PVDD_B PVDD
GND
100nF VREG 8 41
AGND BST_B 3.3R
GND
100R GND 9
TAS5630PHD 40 47uF
VREG BST_C 2.2uF
63V
IN_C
GND 10 39
INPUT_C PVDD_C 10nF
10uF
100pF
11 38
INPUT_D PVDD_C
10k 2.2uF 33nF
12 37
FREQ_ADJ OUT_C 15uH GND GND GND
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
17
18
19
20
21
22
23
24
25
26
28
29
30
31
32
27
OSC_IO+
OSC_IO-
2.2uF
/SD PVDD
GND
/OTW1
VREG 15uH
/OTW2 D
33nF
/CLIP
GND 3.3R
READY GVDD (+12V)
3.3R
100nF 100nF
10nF 10nF
100V GND GND 100V
100nF 100nF
R_COMP R_COMP
100V - 100V -
470nF 470nF
10k 10k
PVDD 250V PVDD 250V
+ +
470uF 10k 100nF GND 470uF 10k 100nF GND
50V 1% 100V 50V 1% 100V
OUT_A_P OUT_B_P
470uF 10k 470uF 10k
PVDD R_COMP 50V 1% 50V 1%
3.3R 3.3R
OUT_C_M OUT_D_M
C D
100nF 100nF
R_COMP R_COMP
100V - 100V -
470nF 470nF
10k 10k
PVDD 250V PVDD 250V
+ +
470uF 10k 100nF GND 470uF 10k 100nF GND
50V 1% 100V 50V 1% 100V
GND GND
100V 100V
10nF GND 10nF GND
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010
TAS5630
19
20
TAS5630
GVDD (+12V)
PVDD
3.3R
1000uF
VDD (+12V)
63V
3.3R
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
100pF GND -
NC
NC
NC
NC
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010
VDD
GND
GND
+
BST_A
OUT_A
OUT_A
GND_A
GND 1nF 10nF GND
PVDD_A
PVDD_A
GVDD_B
GVDD_A
GND 100V 100V
PSU_REF
22.0k
100R 1 48 680nF
OC_ADJ GND_A 250V
IN_CENTER_P 10nF
GND 2 47
/RESET GND_B 3.3R
10uF
100pF
3 C_STARTUP GND_B 46
GND 7uH
GND 4 45
INPUT_A OUT_B
OUT_CENTER_P
100R GND 5 44
INPUT_B OUT_B 2.2uF
IN_CENTER_N 100V 33nF
6 43
VI_CM PVDD_B
10uF 100pF
1nF 7 42
GND PVDD_B PVDD
GND
100nF VREG 8 41
AGND BST_B 3.3R
GND
100R GND 9
TAS5630PHD 40 1000uF 47uF 2.2uF
VREG BST_C
63V 63V 100V 10nF
IN_LEFT
GND 10 39 10nF 100V
INPUT_C PVDD_C
10uF 100pF 100V
11 38
INPUT_D PVDD_C 2.2uF
10k 33nF 3.3R
12 37 100V GND GND GND GND
FREQ_ADJ OUT_C 15uH GND
100R GND 13 36 OUT_LEFT_M
GND OSC_IO+ OUT_C
IN_RIGHT
14 35
OSC_IO- GND_C
10uF 100nF
100pF R_COMP
15 34 100V -
/SD GND_C
GND 470nF
10k
16 33 PVDD 250V
/OTW1 GND_D
+
GND 470uF 10k 100nF GND
50V 1% 100V
OUT_LEFT_P
470uF 10k
3.3R
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
50V 1%
27
OSC_IO+ 100V
GND GND 10nF
OSC_IO-
2.2uF
VREG 100V 10nF
100V
/SD
GND GND
/OTW1
3.3R
15uH GND
/OTW2
OUT_RIGHT_M
33nF
/CLIP
3.3R
100nF
READY R_COMP
3.3R 100V -
470nF
10k
PVDD 250V
+
470uF 10k 100nF GND
100nF 100nF
50V 1% 100V
OUT_RIGHT_P
470uF 10k
3.3R
GND GND 50V 1%
100V
GND GND 10nF
PVDD
GVDD (+12V)
Figure 17. Typical 2.1 System Differential-Input BTL and Unbalanced-Input SE Application
www.ti.com
R34
GVDD (+12V)
1.5R
1000uF
VDD (+12V) 63V
GND
C44 C35
10uF 100nF 7uH GND
OUT_LEFT_M
GND GND
C86 3.3R
VREG 680nF
GND
250V
330pF
PVDD
1.5R 1000uF
63V
R31
100nF 100nF
C89 C84 GND
GVDD (+12V)
GND
21
TAS5630
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5630 needs only a 12-V supply in addition to the (typical) 50-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and
output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2-mF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5630 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5630 is fully protected against
erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
Powering Up
The TAS5630 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically
required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
Powering Down
The TAS5630 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).
OTW2,
SD OTW1 DESCRIPTION
OTW
0 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
0 0 1
warning)
0 1 1 Overload (OLP) or undervoltage (UVP)
1 0 0 Junction temperature higher than 125°C (overtemperature warning)
1 0 1 Junction temperature higher than 100°C (overtemperature warning)
1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics table of this data sheet for further specifications).
Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.
filter. The typical duration is <15 ms/mF. While the PPSC detection is in progress, SD is kept low, and the device
does not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and
SD is released, a device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and
PBTL output configurations; the detection is not performed in SE mode. To make sure the PPSC detection
system is not tripped, it is recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options have individual overtemperature protection schemes.
PHD Package:
The TAS5630 PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package:
The TAS5630 DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD
output; i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after
an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the
falling edge of SD.
OSCILLATOR
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower-value switching frequencies together result in the fewest cases of interference throughout the AM band,
and can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode.
For slave-mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the
OSC_I/O pins as inputs, which must be slaved from an external clock.
Note T1: PVDD bulk decoupling capacitors C60–C64 should be as close as possible to the PVDD_X and GND_X
pins; the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins
and without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink must have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range, preferably metal film types.
Note B1: It is important to have a direct-low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short, low-inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors
REVISION HISTORY
www.ti.com 30-Sep-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TAS5630DKD LIFEBUY HSSOP DKD 44 29 RoHS & Green NIPDAU Level-4-260C-72 HR 0 to 70 TAS5630
TAS5630DKDR LIFEBUY HSSOP DKD 44 500 RoHS & Green NIPDAU Level-4-260C-72 HR 0 to 70 TAS5630
TAS5630PHD NRND HTQFP PHD 64 90 RoHS & Green NIPDAU Level-5A-260C-24 HR 0 to 70 TAS5630
TAS5630PHDR NRND HTQFP PHD 64 1000 RoHS & Green NIPDAU Level-5A-260C-24 HR 0 to 70 TAS5630
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 30-Sep-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TUBE
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TRAY
Pack Materials-Page 4
GENERIC PACKAGE VIEW
PHD 64 HTQFP - 1.2 mm max height
14 x 14, 0.8 mm pitch PLASTIC QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224851/B
www.ti.com
PACKAGE OUTLINE
PHD0064B HTQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
14.05
13.95 B
PIN 1 NOTE 3
INDEX AREA 8.00
64 6.68 49
48
1
THERMAL PAD
NOTE 4
16
33
17 32
A 60 X 0.8 64 X 0.40
0.30
4 X 12 0.2 C A B
SEE DETAIL A
C
1.2 MAX
SEATING PLANE
(0.127) TYP
17 32
16 33
0.25
GAGE PLANE
1.05
0.95
0°-7°
0.15
0.75 0.05
0.1 C
0.45
DETAIL A
TYPICAL
1 48
64 49 4224850/B 05/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. See technical brief. PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
(www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004) for information regarding recommended board layout.
www.ti.com
EXAMPLE BOARD LAYOUT
PHD0064B HTQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
SYMM
64 49
64 X (1.5)
1
48
64 X (0.55)
60 X (0.8)
SYMM
(15.4)
33
(R0.05) TYP 16
17 32
(15.4)
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PHD0064B HTQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
SYMM
64 49
64 X (1.5)
1
48
64 X (0.55)
60 X (0.8)
SYMM
(15.4)
33
(R0.05) TYP 16
17 32
(15.4)
4224850/B 05/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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