Circuit Note

CN-0336
Devices Connected/Referenced
Circuits from the Lab® reference designs are engineered and Precision, Low Noise, CMOS, Rail-to-Rail
AD8606
tested for quick and easy system integration to help solve today’s Input/Output Op Amp
analog, mixed-signal, and RF design challenges. For more AD7091R 1 MSPS, Ultralow Power, 12-Bit ADC
information and/or support, visit www.analog.com/CN0336.
4-Channel, 2.5 kV Isolators with
ADuM5401
Integrated DC-to-DC Converter

12-Bit, 300 kSPS, Single-Supply, Fully Isolated, Data Acquisition System for 4-20 mA
Inputs
EVALUATION AND DESIGN SUPPORT The system processes 4 mA to 20 mA input signals using a single
3.3 V supply. The total error after room temperature calibration
Circuit Evaluation Boards
is ±0.06% FSR over a ±10°C temperature change, making it ideal
CN0336 Circuit Evaluation Board (EVAL-CN0336-PMDZ)
for a wide variety of industrial measurements
SDP/PMD Interposer Board (SDP-PMD-IB1Z)
System Demonstration Platform (EVAL-SDP-CB1Z) The small footprint of the circuit makes this combination an
Design and Integration Files industry-leading solution for 4 mA to 20 mA data acquisition
Schematics, Layout Files, Bill of Materials systems where the accuracy, speed, cost, and size play a critical
role. Both data and power are isolated, thereby making the
CIRCUIT FUNCTION AND BENEFITS
circuit robust to high voltages and also ground-loop interference
The circuit shown in Figure 1 is a completely isolated 12-bit, often encountered in harsh industrial environments.
300 kSPS data acquisition system utilizing only three active devices.
U1B
1/2 AD8606
VREF U2
2.5V ADuM5401
(C-GRADE)
+3.3V
+3.3V +3.3V VISO VDD1 +3.3V_IN
R4 GNDISO GND1 GND
J2 5.11kΩ
D1 TP1 REFOUT VDD VOA VIA SS
0.1V TO 2.4V CS
IIN 1N4148 R1 U1A
1/2 AD8606 SCLK VOB VIB SCK
U3
INPUT VIN AD7091R CONVST VOC VIC CONVST
C10 R2
4mA TO 20mA C11 VID VOD MISO
51Ω 4.7nF
SDO
R3 GND REGCAP VDRIVE +3.3V VSEL RCOUT
120Ω GND_ISO GND_ISO
GNDISO GND1 GND
GND_ISO C8
R5 1µF PMOD CON
R6 1kΩ GND_ISO 12-PIN
124kΩ J1

11650-001
GND_ISO
GND_ISO
GND_ISO

Figure 1. 4 mA to 20 mA Single Supply Analog to Digital Conversion with Isolation (All Connections and Decoupling Not Shown)

Rev. A
Circuits from the Lab® reference designs from Analog Devices have been designed and built by Analog
Devices engineers. Standard engineering practices have been employed in the design and
construction of each circuit, and their function and performance have been tested and verified in a lab
environment at room temperature. However, you are solely responsible for testing the circuit and
determining its suitability and applicability for your use and application. Accordingly, in no event shall One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due Tel: 781.329.4700 www.analog.com
toanycausewhatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage) Fax: 781.461.3113 ©2014 Analog Devices, Inc. All rights reserved.
CN-0336 Circuit Note
CIRCUIT DESCRIPTION The total power dissipation of the circuit (excluding the
The circuit consists of an input current-to-voltage converter, a ADuM5401 isolator) is approximately 10.4 mW when
level shifting circuit, an ADC stage, and an output isolation operating on a 3.3 V supply.
stage. The 4 mA to 20 mA input signal is converted to a voltage Galvanic isolation is provided by the ADuM5401 (C-Grade)
by resistor R3. For R3 = 120Ω and an input current of 4 mA to quad channel digital isolator. In addition to the isolated output
20 mA, the input voltage to the level shifting circuit is: 0.48 V to data, the ADuM5401 also provides isolated +3.3 V for the
2.4 V. The diode D1 is used for protection against an accidental circuit. The ADuM5401 is not required for normal circuit
reverse connection of the input current source. operation unless isolation is needed. The ADuM5401 quad-
The voltage across R3 is level shifted and attenuated by the channel, 2.5 kV isolators with integrated dc-to-dc converter, is
U1A op amp that is one-half of the dual AD8606. The output of available in a small 16-lead SOIC. Power dissipation of the
the op amp is 0.1 V to 2.4 V which matches the input range of ADuM5401 with a 7 MHz clock is approximately 140 mW.
the ADC (0 V to 2.5 V) with 100 mV headroom to maintain The AD7091R requires a 50 MHz serial clock (SCLK) to achieve
linearity. The buffered voltage reference (VREF = 2.5 V) from the a 1 MSPS sampling rate. However, the ADuM5401 (C-grade)
AD7091R ADC is used to generate the required offset. Resistor isolator has a maximum data rate of 25 Mbps that corresponds
values can be modified to accommodate other popular input to a maximum serial clock frequency of 12.5 MHz. In addition,
ranges as described later in this circuit note. the SPI port requires that the trailing edge of the SCLK clock
The circuit design allows single-supply operation. The the output data into the processor, therefore the total round-trip
minimum output voltage specification of the AD8606 is 50 mV propagation delay through the ADuM5401 (120 ns maximum)
for a 2.7 V power supply and 290 mV for 5 V power supply with limits the upper clock frequency to 1/120 ns = 8.3 MHz.
10 mA load current, over the temperature range of -40°C to Even though the AD7091R is a 12-bit ADC, the serial data is
+125°C. A minimum output voltage of 45 mV to 60 mV is a formatted into a 16-bit word to be compatible with the processor
conservative estimate for a 3.3 V power supply, a load current serial port requirements. The sampling period, TS, therefore
less than 1 mA, and a narrower temperature range. consists of the AD7091R 650 ns conversion time plus 58 ns
Considering the tolerances of the parts, the minimum output (extra time required from data sheet, t1 delay + tQUIET delay) plus
voltage (low limit of the range) is set to 100 mV to allow for a 16 clock cycles for the SPI interface data transfer.
safety margin. The upper limit of the output range is set to 2.4 V TS = 650 ns + 58 ns + 16 × 120 ns = 2628 ns
in order to give 100 mV headroom for the positive swing at the fS = 1/TS = 1/2628 ns = 380 kSPS
ADC input. Therefore, the nominal output voltage range of the
input op amp is 0.1 V to 2.4 V. In order to provide a safety margin, a maximum SCLK of 7 MHz
and a maximum sampling rate of 300 kSPS is recommended.
The second half of the AD8606 (U1B) is used to buffer the The digital SPI interface can be connected to the microprocessor
internal 2.5 V voltage reference of the AD7091R (U3) ADC. evaluation board using the 12-pin, Pmod-compatible connector
The AD8606 is chosen for this application because of its low (Digilent Pmod Specifications).
offset voltage (65 μV maximum), low bias current (1 pA Circuit Design
maximum) and low noise (12 nV/√Hz maximum). Power
The circuit shown in Figure 2 provides the proper gain and level
dissipation is only 9.2 mW on a 3.3 V supply.
shifting to shift the 0.48 V to 2.4 V signal to the ADC input
A single-pole RC filter (R2/C11) follows the op amp output range of 0.1 V to 2.4 V.
stage to reduce the out-of-band noise. The cutoff frequency of +3.3V
the RC filter is set to 664 kHz. An optional filter (R1/C10) can
IIN
be added to reduce the filter cutoff frequency even further in U1A
1/2 AD8606
case of low frequency industrial noise. In such case, the INPUT VREF
2.5V
4mA TO 20mA R3 OUTPUT
sampling rate of the AD7091R can be reduced because of the 120Ω 0.1V TO 2.4V
0.1% R4
lower signal bandwidth. 5.11kΩ
GND
1%
The AD7091R 12-bit 1 MSPS SAR ADC is chosen because of its R5
R6
11650-002

ultralow power 349 μA at 3.3 V (1.2 mW) which is significantly 124kΩ 1kΩ
1% 1%
GND_ISO
lower than any competitive ADC currently available in the market.
The AD7091R also contains an internal 2.5 V reference with Figure 2. Current-to-Voltage Converter and Level Shifting Circuit
±4.5 ppm/oC typical drift. The input bandwidth is 7.5 MHz,
and the high speed serial interface is SPI compatible. The
AD7091R is available in a small footprint 10-lead MSOP.

Rev. A | Page 2 of 7
Circuit Note CN-0336
The transfer function is obtained from the superposition principle. If these values are chosen carefully, the overall error due to
substituting standard value resistors can be made less than a few
 R5  R5
V OUT = I IN R3  1 + − V REF = percent. However, Equation 1 should be used to re-calculate the
 R4||R6  U1A op amp output for 4 mA and 20 mA input currents to
 R4
 ensure that the required headroom is preserved.
 R5   R5 R5
I * IN R3  1 + + 4 mA × R3  1 +  −V
The absolute accuracy in this type of circuit is primarily
 
R4||R6    REF
  R4||R6  R4
determined by the resistors, and therefore gain and offset
(1) calibration is required to remove the error due to standard value
where: substitution and resistor tolerances.
I IN = I IN
*
+ 4 mA (2) Effect of Resistor Temperature Coefficients on Overall Error
*
I IN = 0 mA to 16 mA (3) Equation 1 shows that the output voltage is a function of four
resistors: R3, R4, R5, and R6. The sensitivity of the full-scale
and R4 R6 = R4R6 (4) output voltage at TP1 to small changes in each of the four
R4 + R6 resistors was calculated using a simulation program. The input
current to the circuit was 20 mA. The individual sensitivities
Calculation of the Gain and the Resistor Values
calculated were SR3 = 1.2, SR4 = 0.01, SR5 = 0.00, SR6 = 0.01.
The gain of the circuit is: Assuming the individual temperature coefficients combine in a
∆V OUT ( 2.4 − 0.1 ) V 2.3 V  V  root-sum-square (rss) manner, then the overall full-scale drift
GAIN = = = = 143.75   using a 25 ppm/°C resistor for R3 and 100 ppm/°C resistors for
∆I IN (I *
) MAX 16 mA  mA  (5)
IN
R4, R5, and R6 is approximately:
 R5 
= R3  1 +  Full scale drift
 
 R4||R6  = 100 ppm/°C√[(0.25 × SR3)2 + SR42 + SR52 + SR62)]
In case of an input range from 0 mA to 20 mA, the circuit does = 100 ppm/°C√[(0.25 × 1.2)2 + 0.012 + 0.002 + 0.012)]
not need level shifting, and the op amp operates as follower. Then,
= 30 ppm/°C
the voltage drop on R3 must not exceed the upper limit (2.4 V)
of the output range, and can be calculated from the equation: The full-scale drift of 30 ppm/°C corresponds to 0.003%FSR/°C.
R3 × ( I IN ) MAX = R3 × 20 mA ≤ 2.4 V (6) Effect of Active Component Temperature Coefficients on
Overall Error
If R3 = 120 Ω, the ratio R5/(R4||R6) can be calculated from
The dc offsets of the AD8606 op amps and the AD7091R ADC
Equation 5:
are eliminated by the calibration procedure.
R5
=
GAIN
−1 =
143.75
− 1 = 0.198 (7) The offset drift of the ADC AD7091R internal reference is
R 4 R6 R3 120
4.5 ppm/°C typical and 25 ppm/°C maximum.
The output offset of the circuit can be derived from Equation 1 The offset drift of the AD8606 op amp is 1 μV/°C typical and
for IIN = 4 mA: 4.5 μV/°C maximum.
OFFSET = (8) The error due to the input offset of the U1A AD8606 is
V OUT ( I IN = 4 mA) = 0.1 V referenced to the input voltage range of 2.4 V – 0.48 V = 1.92 V,
  and is therefore 2.3 ppm/°C. The error due to the U1B reference
= 4 mA × R3  1 +  −V
R5 R5
  REF buffer is referenced to 2.5 V and is also approximately 2 ppm/°C.
 R4 R6  R4
The total drift error is summarized in Table 1. These errors do
Substituting Equation 7 into Equation 8 and solving for R5/R4: not include the ±1 LSB integral nonlinearity error of the AD7091R.

1    
(9) Table 1. Error Due to Temperature Drift
4 mA × R3  1 +  − 0.1 V  = 0.19
R5 R5
=
    Error Source Total Error
R4 V REF   R4 R6   Resistors (1%, 100 ppm/°C) ±0.0030 %FSR/°C
Resistors R4, R5, and R6 can now be calculated from Equations AD7091R (∆VVREF/∆T = 25 ppm/°C) ±0.0025 %FSR/°C
7 and 9, if a value to one of them is given. For example if R5 = AD8606, U1A (∆VOS/∆T = 4.5 μV/°C), 2 ppm/°C, ±0.0002 %FSR/°C
1000 Ω, then R4 = 5,263 Ω, and R6 = 125,310 Ω. Referenced to 1.92 V
AD8606, U1B (∆VOS/∆T = 4.5 μV/°C), 2 ppm/°C, ±0.0002 %FSR/°C
In the actual circuit the nearest available standard resistor Referenced to 2.5 V
values were chosen for R4 and R6. The values selected were R4 Total FSR Error Temperature Coefficient ±0.0059 %FSR/°C
= 5.11kΩ and R6 = 124 kΩ. Total %FSR Error for ∆T = ±10°C ±0.059 %FSR

Rev. A | Page 3 of 7
CN-0336 Circuit Note
Test Data Before and After Two-Point Calibration capacitors to properly suppress noise and reduce ripple. Place the
To perform the two-point calibration, 4 mA is first applied to capacitors as close to the device as possible with the low ESR value,
the input, and the ADC output code is recorded as Code_1. 0.1 μF capacitor. Ceramic capacitors are advised for all high
Then 20 mA is applied to the input, and the ADC output code frequency decoupling. Power supply lines must have as large trace
is recorded as Code_2. The gain factor is calculated by width as possible to provide low impedance path and reduce glitch
effects on the supply line. The ADuM5401 isoPower integrated
16 mA . (10) dc-to-dc converter requires power supply bypassing at the input
GF =
Code_2 − Code_1 and output supply pins. Note that low ESR bypass capacitors are
required between Pin 1 and Pin 2 and between Pin 15 and Pin
The input current can now be calculated corresponding to any
16, as close to the chip pads as possible.
output code, Code_x, using the equation:
To suppress noise and reduce ripple, a parallel combination of at
I IN = 4 mA + GF ( Code_x − Code_1) . (11)
least two capacitors is required. The recommended capacitor
The error before calibration is obtained by comparing the ideal values are 0.1 μF and 10 μF for VDD1 and VISO. The smaller
transfer function calculated using the nominal values of the capacitor must have a low ESR; for example, use of a ceramic
components, and real circuit transfer function without calibration. capacitor is advised. The total lead length between the ends of
The tested circuits have been built with resistors having ±1% the low ESR capacitor and the input power supply pin must not
tolerance. The test results do not include temperature changes. exceed 2 mm. Installing the bypass capacitor with traces more
The graph in Figure 3 shows test results for percent error (FSR) than 2 mm in length may result in data corruption. Consider
before and after calibration at ambient temperature. As it is bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin
shown, the maximum error before calibration is about 0.25% 16 unless both common ground pins are connected together
FSR. After calibration, the error decreases to ±0.02% FSR, close to the package. For more information, see the ADuM5401
which approximately corresponds to 1 LSB error of the ADC. data sheet.
0.30 A complete documentation package including schematics,
board layout, and bill of materials (BOM) can be found at
0.25
ERROR BEFORE CALIBRATION
www.analog.com/CN0336-DesignSupport.
0.20 High Voltage Capability
ERROR (% FSR)

This PCB is designed in adherence with 2500 V basic insulation

0.15
practices. High voltage testing beyond 2500 V is not recommended.
0.10 Appropriate care must be taken when using this evaluation
board at high voltages, and the PCB should not be relied on for
0.05 safety functions because it has not been high potential tested
ERROR AFTER CALIBRATION
(also known as hipot tested or dielectric withstanding voltage
0
tested) or certified for safety.
11650-003

–0.05
0 5 10 15 20
COMMON VARIATIONS
INPUT CURRENT (mA) The circuit is proven to work with good stability and accuracy
Figure 3. Circuit Test Error Before and After Room Temperature Calibration with component values shown. Other precision op-amps and
PCB Layout Considerations other ADCs can be used in this configuration to convert the
4 mA-to-20 mA input to a digital output and for other various
In any circuit where accuracy is crucial, it is important to consider
applications for this circuit.
the power supply and ground return layout on the board. The
PCB should isolate the digital and analog sections as much as The circuit in Figure 1 can be recalculated for other than 4 mA-
possible. The PCB for this system was constructed in a simple to-20 mA input current range, following the recommendations,
2-layer stack up, but 4-layer stack up gives better EMS. See the given in the Circuit Design section. In these cases, when the low
MT-031 Tutorial for information on layout and grounding and the limit of the range is zero (0 mA to 20 mA, 0 mA to10 mA, 0 mA
MT-101 Tutorial for information on decoupling techniques. to 5 mA), the conversion does not require level shifting, and the
Decouple the power supply to the AD8606 with 10 μF and 0.1 μF input circuit can be simplified, as is shown in Figure 4.

Rev. A | Page 4 of 7
Circuit Note CN-0336
U2
ADuM5401
(C-GRADE)
+3.3V
+3.3V VISO VDD1 +3.3V_IN
GNDISO GND1 GND
TP1
J2 0.1V TO 2.4V REFOUT VDD CS VOA VIA SS
D1
IIN 1N4148 SCLK VOB VIB SCK
U3
VIN AD7091R CONVST VOC VIC CONVST
R2 C11
INPUT 51Ω SDO VID VOD MISO
4.7nF
0mA TO 20mA +3.3V VSEL RCOUT
GND REGCAP VDRIVE
R3
120Ω GNDISO GND1 GND
GND_ISO C8
1µF PMOD CON
GND_ISO 12-PIN
J1

11650-004
GND_ISO GND_ISO

Figure 4. 0 mA-to-20 mA Single Supply Analog to Digital Conversion with Isolation (All Connections and Decoupling Not Shown)

The AD7091 is similar to the AD7091R, but without the voltage • Current calibrator (4 mA to 20mA current source)
reference output, and the input range is equal to the power
Getting Started
supply voltage. The AD7091 can be used with a 2.5 V ADR391
reference. The ADR391 does not require buffering, therefore a Load the evaluation software by placing the CN0336 evaluation
single AD8605 can be used in the circuit. software disc in the CD drive of the PC. You also can download
the most up to date copy of the evaluation software from
The ADR391 is a precision 2.5 V band gap voltage reference,
CN0336 evaluation software. Using My Computer, locate the
featuring low power and high precision (9 ppm/°C of temperature
drive that contains the evaluation software disc and open the
drift) in a tiny TSOT package.
Readme file. Follow the instructions in the readme file for
The AD8608 is a quad version of the AD8605 and can be used installing and using the evaluation software.
as a substitute for the AD8606, if additional precision op-amps
Functional Block Diagram
are needed.
Figure 5 shows a functional block diagram of the test setup.
The AD8601, AD8602, and AD8604 are single, dual, and quad
rail-to-rail, input and output, single-supply amplifiers featuring Setup
very low offset voltage and wide signal bandwidth, that can be • Connect the EVAL-CFTL-6V-PWRZ (+6 V dc power
used in place of AD8605, AD8606, and AD8608. supply) to SDP-PMD-IB1Z Interposer Board via the dc
The AD7457 is a 12-bit, 100 kSPS, low power, SAR ADC, and barrel jack.
can be used in combination with the ADR391 voltage reference • Connect the SDP-PMD-IB1Z (interposer board) to EVAL-
in place of AD7091R, when a 300 kSPS throughput rate is not SDP-CB1Z SDP board via the 120-pin Con A connector.
needed. • Connect the EVAL-SDP-CB1Z (SDP board) to the PC via
the USB cable.
CIRCUIT EVALUATION AND TEST
• Connect the EVAL-CN0336-PMDZ evaluation board to
This circuit uses the EVAL-CN0336-PMDZ circuit board, the the SDP-PMD-IB1Z Interposer Board via the 12-pin
SDP-PMD-IB1Z, and the EVAL-SDP-CB1Z system demonstration header Pmod connector.
platform (SDP) evaluation board. The interposer board SDP- • Connect the 4 mA to 20 mA current source (current
PMD-IB1Z and the SDP board EVAL-SDP-CB1Z have 120-pin calibrator) to the EVAL-CN0336-PMDZ evaluation board
mating connectors. The interposer board and the EVAL- via the terminal block J2.
CN0336-PMDZ board have 12-pin Pmod matching connectors,
allowing quick setup and evaluation of the circuit’s performance. Test
The EVAL-CN0336-PMDZ board contains the circuit to be Launch the evaluation software. The software can communicate
evaluated, as described in this note and the SDP evaluation to the SDP board if the Analog Devices System Development
board is used with the CN0336 evaluation software to capture Platform drivers are listed in the Device Manager. Once USB
the data from the EVAL-CN0336-PMDZ circuit board. communications are established, the SDP board can be used to
Equipment Needed send, receive, and capture serial data from the EVAL-CN0336-
PMDZ board. Data can be saved in the computer for various
• PC with a USB port Windows® XP or Windows Vista® (32-
values of input current.Information and details regarding how
bit), or Windows® 7/8 (64- or 32-bit)
to use the evaluation software for data capturing can be found
• EVAL-CN0336-PMDZ circuit evaluation board in the CN0336 Software User Guide. Information and details
• EVAL-SDP-CB1Z SDP evaluation board on the SDP board can be found in the SDP User Guide.
• SDP-PMD-IB1Z interposer board
A photo of the EVAL-CN0336-PMDZ evaluation board is
• CN0336 evaluation software
shown in Figure 6.
Rev. A | Page 5 of 7
CN-0336 Circuit Note
EVAL-CFTL-6V-PWRZ
6V WALL WART

EVAL-SDP-CB1Z
J1 SDP-B BOARD
EVAL-CN0336-PMDZ
4mA TO 20mA 120-PIN
J1 J3 CON A
CURRENT J2 J4
PMOD PMOD
SOURCE

SDP-PMD-IB1Z USB
INTERPOSER BOARD

11650-005
PC

Figure 5. Test Setup Functional Block Diagram

11650-006
Figure 6. Photo of EVAL-CN0336-PMDZ Board

Rev. A | Page 6 of 7
Circuit Note CN-0336
LEARN MORE Data Sheets and Evaluation Boards
CN0336 Design Support Package: AD8606 Data Sheet
http://www.analog.com/CN0336-DesignSupport AD7091R Data Sheet
Chen, Baoxing, John Wynne, and Ronn Kliger. High Speed ADuM5401 Data Sheet
Digital Isolators Using Microscale On-Chip Transformers,
Analog Devices, 2003 REVISION HISTORY
3/14—Rev. 0 to Rev. A
Chen, Baoxing. iCoupler® Products with isoPower™ Technology:
Signal and Power Transfer Across Isolation Barrier Using Change to Circuit Function and Benefits Section ........................ 1
Microtransformers, Analog Devices, 2006 2/14—Revision 0: Initial Version
Ghiorse, Rich. Application Note AN-825, Power Supply
Considerations in iCoupler® Isolation Products, Analog
Devices
Krakauer, David. “Digital Isolation Offers Compact, Low-Cost
Solutions to Challenging Design Problems.”Analog Dialogue.
Volume 40, December 2006.
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of "AGND" and "DGND," Analog Devices
MT-101 Tutorial, Decoupling Techniques, Analog Devices
Wayne, Scott. “iCoupler® Digital Isolators Protect RS-232, RS-
485, and CAN Buses in Industrial, Instrumentation, and
Computer Apps, Analog Dialogue, Volume 39, Number 4,
2005.

(Continued from first page) Circuits from the Lab reference designs are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors.
While you may use the Circuits from the Lab reference designs in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual
property by application or use of the Circuits from the Lab reference designs. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the
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noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties
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©2014 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
CN11650-0-3/14(A)

Rev. A | Page 7 of 7