984 Systemmanual
984 Systemmanual
984 Systemmanual
Programmable
Controller
Systems Manual
GM--0984--SYS Rev. B
May, 1991
DOK- 1
2 DOK-
Table of Contents
Programming Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
The P230 .............................................. 16
The P190 Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Using Industry-standard PCs as Programming Panels . . . . . . . . . . . . . . . 17
The P965 Data Access Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
How the P965 Can Be Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
The Hot Standby Option Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
How a Hot Standby System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Controller Compatibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
The Coprocessing Option Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
The C986 Copro for Chassis Mount 984s . . . . . . . . . . . . . . . . . . . . . . . . . . 22
The C996 Copros for Slot Mount 984s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Enhancing Your Processing Environment with a Copro . . . . . . . . . . . . . . . . 24
Application Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Immediate DX Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Deferred DX Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Optional Communication Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I/O Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Input and Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I/O Module Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Local and Remote I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Local I/O ................................................ 32
Remote I/O ................................................ 33
Remote I/O Drop Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ASCII Communication at the Remote I/O Drops . . . . . . . . . . . . . . . . . . . . . . 34
RIO Interfaces that Support ASCII Communication . . . . . . . . . . . . . . . . . . 34
ASCII Device Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
The ASCII Operator Keypad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Overview of I/O Support for 984 Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . 36
800 Series I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
800 Series Discrete Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
800 Series Discrete Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
800 Series Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
800 Series Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
800 Series Special Purpose I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 39
800 Series Intelligent I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
800 Series MMI Operator Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power Supplies for Local and Remote 800 Series I/O Drops . . . . . . . . . . . 41
200 Series I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
200 Series Discrete Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
200 Series Discrete Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
200 Series Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
200 Series Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
200 Series Special Purpose I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 43
500 Series I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
500 Series Discrete Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
500 Series Discrete Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
500 Series Special Purpose I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 45
A120 Series I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
A120 Discrete Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
A120 Discrete Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
A120 Combo Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
A120 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
A120 Analog Output Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Modbus Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
The Modbus Port Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Modbus Port Pinouts for the P230 Programming Panel . . . . . . . . . . . . . . . . 54
Modbus Port Pinouts for the P190 Programming Panel . . . . . . . . . . . . . . . . 55
Modbus Port Pinouts for an IBM-XT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Modbus Port Pinouts for a Modicon Comm Modem . . . . . . . . . . . . . . . . . . . 57
A Modbus Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Network Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Communication Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Communication Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
A Modbus Plus Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Network Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
The Logical Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
The Physical Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Adding and Deleting Nodes from the Network . . . . . . . . . . . . . . . . . . . . . . 61
Joining Modbus Plus Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
A Modbus II Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Modbus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Distributed Control Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Distributed Control Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Network Topology Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SKP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
A Simple SKP Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
CKSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
The data and illustrations found in this book are not binding. We reserve the
right to modify our products in line with our policy of continuous product
improvement. Information in this document is subject to change without notice
and should not be construed as a commitment by Modicon, Inc., Industrial
Automation Systems. Modicon, Inc. assumes no responsibility for any errors
that may appear in this document.
No part of this document may be reproduced in any form or by any means,
electronic or mechanical, without the express written permission of Modicon,
Inc., Industrial Automation Systems. All rights reserved.
The following are trademarks of Modicon, Inc.:
The family approach to 984 controller design allows you to make choices based
on controller capacity (the number of discrete and analog/register points available
for application programming, the number of I/O drops it supports), throughput (the
rate at which it solves logic and updates I/O modules), and environmental hard-
ness (the design standards its hardware implementation must meet).
The 984 instruction set (the functional capabilities of the controller, part of the sys-
tem firmware stored in executive PROM) comprises logic functions common to
other 984s. This means that user logic created on a midrange or high-perform-
ance unit such as a 984-685 or a 984B can be relocated to a smaller controller
such as a 984-145 (assuming sufficient memory in the smaller machine) and that
logic created on a smaller controller is upwardly compatible to a larger unit. As
your application requirements increase, it is relatively easy to upgrade your con-
troller hardware without having to rewrite control logic.
Also, training costs and learning curves can be reduced, since users familiar with
one 984 model automatically have a strong understanding of others.
The table on the following page gives you an overview of 984 programmable con-
troller characteristics. The 984 controller models are listed by capacity in de-
scending order, the 24 bit CPUs first, followed by the 16 bit CPUs. The capacity
of a controller is a function of the number of discrete and register points available
in state RAM—a discrete point uses one bit while a register/analog point requires
16 bits.
Notice that the discretes and registers are implemented in two different areas of
system memory—in state RAM and in real-world I/O locations as defined by the
984 traffic cop. The registers and discretes available in state RAM may be used
for programming I/O, internal coils, and data registers; the registers and discretes
available through the traffic cop can be used only for programming local or remote
I/O points. In some of the smaller-cpacity controllers, the traffic cop limits the
maximum number of I/O bits and the total number of discrete I/O points to num-
bers below what is available in state RAM. The additional discretes and registers
from state RAM may be used in the logic program for internal coils and data stor-
age buffers, but they cannot be mapped to I/O points.
984 Hardware Logic Solve CPU User State RAM Maximum I/O Maximum I/O Total Max. Drops
Model Implementation (ms/Kword) Size Logic Size** Regs Discretes Bits per Drop Bits/System Discrete I/O per System
984B Chassis mount 0.75 24 bits 32K/64K* 9999 8192*** 1024 in/1024 out 32768 in/32768 out 8192 in/8192 out 32 R (S908)
256 in/256 out 4096 in/4096 out 4096 in/4096 out 16 R (S901)
984--780/--785 Slot mount 1.5 24 bits 16K/32K 9999 8192*** 512 in/512 out 16384 in/16384 out 8192 in/8192 out 1 L, 31 R
Q984 Host Based 2.0 24 bits 12K 9999 8192*** 512 in/512 out 3584 in/3584 out 3584 any mix 7R
984A Chassis mount 0.75 16 bits 16K/32K 1920 2048 any mix 1024 in/1024 out 32768 any mix 2048 any mix 32 R (S908)
256 in/256 out 4096 in/4096 out 2048 any mix 16 R (S901)
984X Chassis mount 0.75 16 bits 8K 1920 2048 any mix 512 in/512 out 3584 in/3584 out 2048 any mix 1 L, 6 R
984--685 Slot mount 2.0 16 bits 8K/16K 4096**** 2048 any mix 512 in/512 out 16384 in/16384 out 2048 any mix 1 L, 31 R
984--680 Slot mount 3.0 16 bits 8K/16K 4096**** 2048 any mix 512 in/512 out 16384 in/16384 out 2048 any mix 1 L, 31 R
AT--984 Host Based 1.5 16 bits 8K 1920 2048 any mix 512 in/512 out 3584 in/3584 out 2048 any mix 7R
MC--984 Host Based 1.5 16 bits 8K 1920 2048 any mix 512 in/512 out 3584 in/3584 out 2048 any mix 7R
984--485 Slot mount 3.0 16 bits 4K/8K 1920 2048 any mix 512 in/512 out 3584 in/3584 out 1024 any mix 1 L, 6 R
984--480 Slot mount 5.0 16 bits 4K/8K 1920 2048 any mix 512 in/512 out 3584 in/3584 out 1024 any mix 1 L, 6 R
984--385 Slot mount 3.0 16 bits 4K/6K 1920 2048 any mix 512 in/512 out 512 in/512 out 512 any mix 1L
984--381 Slot mount 5.0 16 bits 1.5K/4K/6K 1920 2048 any mix 512 in/512 out 512 in/512 out 512 any mix 1L
984--380 Slot mount 5.0 16 bits 1.5K/4K/6K 1920 2048 any mix 512 in/512 out 512 in/512 out 256 any mix 1L
984--145 Compact 4.25 16 bits 8K 1920 2048 any mix 512 in/512 out 512 in/512 out 256 any mix 1L
984--130 Compact 4.25 16 bits 4K 1920 2048 any mix 512 in/512 out 512 in/512 out 256 any mix 1L
984--120 Compact 4.25 16 bits 1.5K 1920 2048 any mix 512 in/512 out 512 in/512 out 256 any mix 1L
Micro--984 Micro 5.0 16 bits 4K 1920 2048 any mix 64 in/64 out 64 in/64 out 112 any mix 1L
(112 total) (112 total)
R = Remote, L = Local
* The 984B offers extended memory (XMEM) in 32K, 64K, and 96K sizes; total
memory can be up to 128K, with up to 64K devoted to user logic (UL):
• 32K = 32K UL
• 64K = 64K UL or 32K UL/32K XMEM
• 96K = 32K UL/64K XMEM or 64K UL/32K XMEM
• 128K = 32K UL/96K XMEM or 64K UL/64K XMEM *** State RAM in these 24 bit CPUs may be allocated as 8192 discrete I/O
+ 9999 registers or as (8192 discrete in/8192 discrete out + 8500 registers).
** Approximately 1K words of user logic are used for system overhead; utilizes
one word/node for user logic—e.g., a normally open contact uses one word ****4096 registers are available if you use an Extended Register cartridge
of user logic memory. (AS--E685--914 or AS--E680--914); otherwise, 1920 registers are available.
4
1.3 How a 984 System Provides
Application Control
All controllers in the 984 family share a common processing architecture, which
comprises:
A memory section that stores user logic, state RAM, and system overhead in
battery-backed CMOS RAM and holds the system’s Executive firmware in
nonvolatile ROM
A CPU section that solves the user logic program based on the current input
values in state RAM, then updates the output values in state RAM
An I/O processing section that directs the flow of signals from input modules to
state RAM and provides a path over which output signals from the CPU’s logic
solve are sent to the output modules
A communications section that provides one or more port interfaces. These in-
terfaces allow the controller to communicate with programming panels, host
computers, hand-held diagnostic tools, and other peripheral (master) devices
as well as with additional controllers and other nodes on a communications
network
CPU
Memory
to
Application
Communications Processor Switching
Devices
Modicon designs fault protection and isolation features into all 984 controllers.
Orderly system startup and shutdown procedures help protect system memory,
state RAM, and system hardware from damage due to external power failures.
Long-life lithium batteries back up system memory and state RAM in the event of
an unexpected power failure. When power has been restored, a series of internal
controller checksum diagnostics validate that RAM data are consistent with the
values that were active at the time of power-down.
* There is no editor feature comparable to the Annotated Ladder Lister in the P190 Panel
Software package.
* Advanced math functions include log, antilog, square root, process square root,
and double precision math; advanced DX functions include table-to-block and
block-to-table moves and checksum.
** PID2, MSTR, and the advanced math DX functions are provided as loadables for the
chassis mount controllers only; comparable functionality is provided as standard in
other controllers (see Section 1.6).
For more details on the loadable software packages, see Chapter 21.
SFC is an optional feature that allows you to generate new programs arranged in
blocks rather than the linear sequence of straight ladder logic. A sequential func-
tion chart can solve multiple networks in a parallel link block or one in a choice of
several networks in a selective link block.
Initial Step
S011 S = Step
1 T = Transition
T 011
Parallel Link
T 021
S031
1
Selective Link
T 031 T 032 T 033
S041 S042 S043
6 3 1
T 041 T 042 T 043
MODSOFT provides a macro feature that can simplify the task of generating and
updating large number of repetitive network structures. Using the macro feature,
you can create the repeating structure once, then specify the node values using
macro parameters rather than standard 984 reference numbers. Each macro can
contain up to 66 macro parameters—by using ∗ wild card characters in your nam-
ing scheme, you can actually create thousands of parameters/macro.
Online, where the application is communicating with the controller and any
changes made to the program are reflected in the controller
Debug, where any changes made to the logic program are saved simulta-
neously in the 984 controller and in the offline program file and where SFC can
be monitored for power flow
Instruction Meaning
Calculations Functions
ADD Addition
SUB Subtraction, greater than, less than, and equal to
MUL Multiplication
DIV Division
DX Matrix Functions
AND Logical AND of two matrices
OR Logical inclusive OR of two matrices
XOR Logical exclusive OR of two matrices
COMP Logical complement of one matrix
CMPR Logical compare of two matrices
MBIT Logical bit modify
SENS Logical bit sense
BROT Logical bit rotate
SKP A skip function
TBLK Moves a block of data from a table to another specified block area
BLKT Moves a block of registers to specified locations in a table
PID2 Performs proportional-integral-derivative control functions
Programming Panels
Monitor the register and discrete values in user memory and state RAM
The AS-P230-000 is a portable programming panel with a 40 Mbyte hard disk for-
matted and installed with MS-DOS and GW-BASIC interpreter software. It sup-
ports both MODSOFT and P190 emulation software, either of which may be
loaded from the unit’s a 3.5 in disk drive. The P230 power supply is 115/230 VAC
user-selectable.
A set of 5.25 in and 3.5 in disks is available to emulate the P190 software on a
standard DOS-based PC, and the integrated MODSOFT package is also available
on both 5.25 in and 3.5 in distribution disks. These software packages can be run
on any IBM-AT or true AT-compatible PC.
The P965 DAP is a lightweight device with a 64-character liquid crystal display
(LCD) screen and a keypad with alphanumeric and function keys.
A P965 DAP is a very effective tool for monitoring and troubleshooting the control-
ler. With it, you can
Monitor the register and discrete values in user memory and state RAM
The P965 can be used on the shop floor to monitor the status of a 984 program-
mable controller by accessing the STAT block. (Procedures for accessing the
STAT block are described in Sections 14.4 and 14.10; the types of statistics avail-
able from the STAT block are described in detail in Section 14.5 ... 14.7 for an
S901 RIO network and Sections 14.11 ... 14.13 for other 984 I/O networks.
The Hot Standby capability has been designed for applications that demand
fault-tolerant, high-availability performance. Two identically configured 984 con-
trollers communicate with each other through two Hot Standby option modules,
one in each controller. Each controller has the HSBY loadable software function
block installed in the first segment of ladder logic (described in Chapter 21).
AM-R911-000 Hot Standby option modules are designed for use in a system in-
volving two identically configured chassis mount controllers. AS-S911-800 Hot
Standby option modules are designed for use in a system involving two identically
configured 984-680, -685, -780, or -785 slot mount controllers.
Upon powering up a 984 Hot Standby system, one of the two identically confi-
gured 984 controllers acts as the primary controller—it reads input data from re-
mote I/O drops, executes the stored user programs from memory, and sends ap-
propriate output commands to the drops. The primary controller updates the
standby controller with current system and state RAM status information at the
end of each scan.
The standby controller only reads this information—it does not execute control
functions and does not interfere with primary control operations. It will assume
primary system control in 13 ... 48 ms if the primary controller fails.
The S911 and R911 Hot Standby modules are devices designed to be installed in
option slots with their host controllers. They work in conjunction with 984 control-
lers that use S908 Remote I/O Processor modules. The R911 modules work with
the 984A, 984B, and 984X chassis mount Controllers; the S911 modules work
with 984-68x and 984-78x slot mount Controllers. All hardware and firmware in
the primary and standby controllers must be identical.
S S/R S S/R
984 Control- 9 9 984 Control- 9 9
ler 0 1 ler 0 1
(Primary) 8 1 (Standby) 8 1
W911
Coax
J 800
8 Series
9 I/O
0
Modicon offers two types of integrated control processors (Copros)—the C986 for
use with chassis mount 984 controllers and the C996 for use with slot mount 984
controllers that support option modules. These option modules extend the pro-
cessing capabilities of your controller, providing alternative programming solutions
for problems that are difficult or inefficient to handle via ladder logic.
The AM-C986-004 Copro resides in a single option slot in a 984A, 984B, or 984X
chassis. It uses the flexible, multitasking VRTX Operating System, which allows
it to perform parallel application processing, immediate DX processing, and
deferred DX processing (see Section 2.5). Programs developed in Microsoft C,
either by you or by Modicon, can be downloaded to the Copro and run in parallel
with the 984 CPU.
Two coprocessor models are available for use with slot mount controllers—the
AM-C996-802 Copro with two expansion slots and the AM-C996-804 Copro with
four expansion slots. These copros are DOS-based computer systems with a pro-
prietary high speed interface to 984 controller memory. The C996 Copros can
perform parallel application processing and immediate DX processing, but not def-
erred DX processing (see Section 2.5).
The AM-C996-802 consumes one and a half slots in a slot mount controller hous-
ing, and the AM-C996-804 consumes two and a half slots in the housing.
AM-C996-802 AM-C996-804
The expansion slots can support various commercially available option cards.
The depth dimension of the C996 expansion slots limits your choice of option
cards to half-size IBM-XT cards.
Both the VRTX-based C986 Copro and the DOS-based C996 Copros can com-
municate with the controller in two different modes—application mode and imme-
diate DX mode. Only the C986 Copro can communicate with the controller in
deferred DX mode.
The C986 and C996 Copros can run programs in application mode in parallel with
the 984 CPU, exchanging data with the controller at the end of scan (EOS):
SCAN 1 SCAN 2
EOS
COPRO
Logic Application
Scanning Processing
How a Copro Handles Application Processing in Parallel with the 984 CPU
The C986 and C996 Copros can run standard and customized C routines that are
initiated, or called, by ladder logic—a loadable CALL function block (described in
Chapter 21) is provided for this purpose.
SCAN 1 SCAN 2
CALL
to EOS
IMMDX
984
CPU
COPRO
In deferred DX mode, DX processing begins with a call and continues until it is fin-
ished, even if its processing runs longer than one scan. A typical deferred DX
function might be reading bar code input to a serial port.
SCAN 1 SCAN 2
CALL
to EOS
DEFDX
984
CPU
COPRO
984 Controllers may be interconnected in various kinds of local area (and in some
cases long distance) networks. The following 984 controller option modules that
allow you to establish the network connections are described here; overall net-
working capabilities are described in more detail in Chapter 4.
The AM-S978-000 Dual Modbus Modem is an option module that allows a chassis
mount 984 controller to be used as a slave processor in a Modbus network. The
AS-J878-000 is an option module that provides similar capability in a slot mount
984 controller. These Modbus modems allow you to create Modbus networks up
to 15,000 ft (4572 m) long and comprising up to 247 slave nodes.
These modems are electrically compatible with all Modbus products and are sized
to fit in one slot (in a 984 chassis in the case of the S978 and in an 800 Series I/O
primary housing in the case of the J878). The S978 module contains two mo-
dems, which are connected via cable to Modbus ports on the comm processor
module in the controller; the J878 module contains one modem.
An S978 Modem accepts digital data from the slave controller in which it resides
and modulates the data into an FM analog signal—a form of transmission suited
to four-wire cable. It transmits the analog FM signal to the host’s Modbus Master
device, where it is demodulated to digital data. Conversely, the Modbus Master
transmits digital data, which is modulated to an FM analog signal on its way back
to the S978 Modem. The S978 demodulates the analog signal to digital data and
sends the data to the slave controller in which it resides.
For more information about Modbus network capabilities, see Section 4.6.
The S975 Modbus II Interfaces are option modules that allows a 984 controllers to
be used as a processing node in the Modbus II network. The AM-S975-100 mod-
Special software must be loaded into the controller to program Modbus II commu-
nications in ladder logic. Two loadable function blocks—MBUS and PEER (de-
scribed in Chapter 21)—are used to initiate communications. MBUS writes infor-
mation to or reads information from a single controller. PEER writes register
information to up to 16 controllers simultaneously.
Several 984 controllers have a Modbus Plus capability built directly into the con-
troller—i.e, the slot mount 984-385, 984-485, 984-685, and 984-785 Controllers,
the Compact 984-145 Controller, and the host based AT-984 and MC-984
Controllers.
For the chassis mount controllers and for the slot mount controllers that accept
option modules (the 984-68x and -78x ), various S985 Modbus Plus Adapter
cards are available as option modules. An S985 comes with a loadable version of
the MSTR function block (described in Chapter 17), which allows you to initiate
Modbus Plus communication functions; in 984 controllers with built-in Modbus
Plus capabilities, the MSTR function is part of the standard executive firmware.
The AM-S985-000 card is used with a 984X Controller, the AM-S985-020 is used
with a 984A Controller (with an S908 RIOP), and the AM-S985-040 is used with
the 984B Controller (with an S908 RIOP).
I/O Subsystems
Local I/O
Remote I/O
Power Supplies for Local and Remote 800 Series I/O Drops
The application logic that is stored in and solved by the controller is implemented
on the factory floor by input and output modules. These I/O modules are field-
wired to sensing or switching devices on the shop floor and linked to the controller
over an I/O bus to create a complete control system. Modicon provides several
series of I/O modules that may be implemented by different 984 controllers.
An input module accepts electrical signals from field sensing devices, isolates
these signals from the controller, and converts them into acceptable voltage levels
that update the controller’s State RAM.
An output module accepts electrical signals from the controller’s state RAM, iso-
lates these signals from the field, and converts them into voltage or current levels
necessary to activate working devices or indicator displays on the factory floor.
Input and output modules are wired to industrial field devices that send or receive
application data. When you plan your I/O layout, match the electrical signal used
in the I/O modules with the signal used by the field device to which it is wired.
Modicon offers a wide range of I/O modules:
Discrete in, which convert signals coming from field input devices such as pres-
sure switches, limit and proximity switches, or photo sensors into voltage levels
that can be used by the controller
Discrete out, which convert voltage levels generated by the controller’s logic
solving into output signals used by output field sensing devices such as relays,
lamps, or solenoids
Discrete input and output modules are available to support AC, DC, and TTL
field input devices
Analog in, which convert analog input signals coming from field input devices
such as pressure, level, temperature, or weight sensors into numerical data
30 984 I/O Subsystems GM--0984--SYS
that can be used by the controller—this numerical data ranges from 0000 to
4095
Analog out, which convert numerical data generated by the controller’s logic
solving into analog output signals to be used by output field devices—such as
heaters or pumps
When local I/O is supported, it consists of one drop only, always designated as
drop #1 in your system configuration. Your controller restricts you to one specific
series of I/O modules at the local drop.
984-780, -785 800 Series I/O In the primary 800 Up to five housings
Series I/O housing supported
with controller
984-680, -685 800 Series I/O In the primary 800 Up to five housings
Series I/O housing supported
with controller
984-480, -485 800 Series I/O In the primary 800 Up to two housings
Series I/O housing supported
with controller
984-380, -381, -385 800 Series I/O In the primary 800 Up to two housings
Series I/O housing supported
with controller
984-120, -130, -145 A120 Series I/O In primary DTA hous- Up to 18 I/O
ing with controller modules supported
in up to four DTA
housings
* Because the I/O modules reside in a separate housing from the 984X Controller, the I/O
modules must receive their power from one or more independent slot mount power sup-
ply modules.
When remote I/O is supported, the 984 controller may support several drops—in
some cases as many as 32. In a remote I/O configuration, an RIO processor in
the controller is connected via a coaxial cable system to an RIO interface device
at each remote drop.
All 984 controllers that support remote I/O have been designed to drive 800 Se-
ries I/O at the remote drops. Several option modules and/or field modification kits
are available that allow you to drive installed bases of 200 and 500 Series I/O at
remote drops as well.
At each remote drop is a remote I/O (RIO) interface device that communicates
over the coaxial cable with the RIO processor in the controller. The RIO interface
passes data to and from the I/O modules in the drop over the I/O housing back-
plane and passes data to and from the 984 controller over the RIO cable system.
An RIO interface also contains a set of switches that you use to address all the
drops in your system.
There are various kinds of RIO Interfaces you can use, depending on the I/O Se-
ries in the drop and the type of RIO processor in the controller. According to your
application requirements, you may select RIO Interfaces that provide the drop with
ASCII device support.
For a detailed discussion of the planning, installing, and testing an RIO cable sys-
tem, refer to the Modicon Remote I/O Cable System Planning Guide
(GM-0984-RIO).
A 984 Controller that communicates with remote I/O allows you to connect ASCII
data entry and data display devices at as many as 16 drop sites. Special types of
remote I/O interface devices must be used at drops when ASCII devices are used.
The J812 and J892 Remote I/O Interfaces (for 800 Series I/O) and P453 Remote
I/O Interface (for 200 and 500 Series I/O) have 25-pin female ASCII ports; the
P892 RIO Interface (for 800 Series I/O) has 9-pin female ASCII ports:
Each of these RIO Interface devices can support two ASCII devices. As many as
32 ASCII devices can be run from a 984 controller, two/drop from up to 16 drops.
984 Controller
with S908
J
P/S 8 800 Series I/O
9
2
P
8
200 Series I/O 800 Series I/O
9
2
An ASCII editor in your panel software allows you to create, edit, and manage a li-
brary of ASCII messages to be read or written over the RIO communication link.
These ASCII messages reside in a table that occupies space in user logic
memory.
*The B881 Module must be addressed as one register IN (3x) and one register OUT (4x).
Intelligent I/O modules perform tasks that require special on-board processing
capabilities.
Two types of 32 Element Pushbutton Panels may be installed and traffic copped
like I/O at remote S908/S929 drops. The MM-32SD-000 Panel is connected via a
W801 cable to an 800 Series I/O drop being driven by an S908-compatible RIO
interface device. By adding an MM-32PR-000 Primary Option board to this opera-
tor panel, you create a primary device that can be connected directly to the S908
RIO network.
A PanelMate Plus Video Control Panel may also be installed as a drop on an RIO
network. PanelMate Plus is traffic copped like a D908 Distributed Control Proces-
sor (see Section 4.10).
To determine the power requirements of a drop, add the individual power draws of
each module in the drop. A primary power supply is required in the first slot of the
primary housing in a remote I/O drop; an auxiliary power supply may be installed
in the first slot of a secondary housing:
Power Supplies for a Remote 800 Series I/O Drop
* Total maximum of +5V I/O, +4.3V I/O, and +5V Interface cannot exceed 13500 mA
** Total maximum of +5V I/O and +4.3V I/O cannot exceed 5000 mA
*** Total maximum of +5V I/O, +4.3V I/O, and +5V Interface cannot exceed 16100 mA
# Total maximum of +5V I/O and +4.3V I/O cannot exceed 3000 mA
## Total maximum of +5V I/O and +4.3V I/O cannot exceed 6000 mA
A slot mount 984 controller provides the primary power supply for its local I/O
drop; auxiliary power supplies listed above may be used in secondary housings:
Primary Power Supplies for a Local 800 Series I/O Drop
200 Series I/O modules may be used at remote I/O drops in conjunction with any
chassis mount, slot mount, or host based 984 controller; they cannot be used at
local drops. The 200 Series provides discrete in, discrete out, analog in, analog
out, and special purpose I/O modules.
Application Number
Model Range of Channels Words(I/O)
AS-B243-105 1...5VDC, 4 4/0
4...20MADC,
AS-B243-110 0...10VDC, 4 4/0
-10...+10VDC
Application Number
Model Range of Channels Words(I/O)
AS-B260-005 1...5VDC 4 0/4
AS-B260-010 0...10VDC 4 0/4
AS-B262-001 1...5VDC, 4...20VDC 4 0/4
Number
Model Description of Inputs Words(I/O)
AS-B239-001 Dual High Speed 2 2/2
Counter
AS-B258-101 16-to-1 Analog 16 0/1
MUX (used with a
B243 Module)
AS-B281-001 Thermocouple 10 10/0
Module
AS-B283-001 RTD Input 8 8/0
Module
500 Series I/O modules may be used at remote I/O drops in conjunction with any
chassis mount, slot mount, or host based 984 controller; they cannot be used at
local drops. The 500 Series provides discrete in, discrete out, and special pur-
pose I/O modules.
Number
Model Description of Inputs Words(I/O)
AS-B570-001 Output Register MUX 16 0/8 0r 0/16
(16 three-digit,
Latch-on-High LEDs)
AS-B571-001 Input Register MUX 16 8/0 or 16/0
(16 three-digit, 9’s
complement Thumbwheels)
AS-B572-001 D/A Converter 2 0/2
0...10V
AS-B581-001 Absolute Encoder 12 bits 1/0
Module
A120 Series I/O modules are used as local I/O with the -120, -130, and -145 Com-
pact 984 Controllers; they cannot be used in remote I/O configurations. The A120
Series provides discrete in, discrete out, analog in, analog out, and special pur-
pose I/O modules.
300 Series I/O modules are used in conjunction with the Micro-984 Controller.
The 300 Series provides discrete in, discrete out, analog, and BCD register I/O
modules.
Voltage Number
Model Range of Inputs
AS-B351-001 115VAC 8
AS-B353-001 24VDC (True Low) 8
AS-B355-001 220VAC 8
AS-B357-001 24VDC (True High) 8
AS-B359-001 24VAC 8
Voltage Number
Model Range of Outputs
AS-B350-001 115VAC 8
AS-B352-001 24VDC (True Low) 8
AS-B354-001 220VAC 8
AS-B356-001 24VDC (True High) 8
AS-B358-001 24VAC 8
AS-B360-001 Dry Contact (Relay, NO) 6
AS-B360-002 Dry Contact (Relay, NC) 6
Application
Model Range Words(I/O)
AS-B373-001 0...10VDC 2/0
AS-B374-001 1...5VDC/4...20mA 0/2
AS-B375-001 1...5VDC/4...20mA 2/0
Application
Model Range Words(I/O)
AS-B370-001 0...5VDC; 3 digits 0/2
AS-B371-001 0...5VDC; 3 digits 2/0
Modbus Capabilities
A Modbus Network
A Modbus II Network
All chassis mount, slot mount, and micro controllers provide at least one Modbus
port as a serial communications capability. The communication parameters for
your Modbus port(s) may be set by switches on the controller or via the panel soft-
ware, depending on your controller type. There are three communication parame-
ters:
ASCII Mode
data bits
logic 1 start parity stop stop
bit 1 2 3 4 5 6 7
logic 0
bit 1 2
RTU Mode
data bits
logic 1 start parity stop
bit 1 2 3 4 5 6 7 8
logic 0
bit bit
RTU mode packs data bits more compactly in order to increase speed.
The chassis mount controllers provide one or more 25-pin Modbus ports, and the
other controllers provide nine-pin ports. Here are the pinouts for for the P230
Panel with these ports. (The same pinouts apply to an IBM-AT Personal
Computer and to a FactoryMate Plus Operator Panel.):
P230 to Modbus Pinouts
CD 1 1 SHIELD
RX 2 2 TX
TX 3 3 RX
DTR 4 4 RTS
GROUND 5 5 CTS
DSR 6 6 DSR
RTS 7 7 GROUND
CTS 8 8 CD
20 DTR
NC 1 1 SHIELD
RX 2 2 RX
TX 3 3 TX
DTR 4 4 DTR
GROUND 5 5 GROUND
DSR 6 6 DSR
RTS 7 7 RTS
CTS 8 8 CTS
9 NC
TX: transmitted data DSR: data set ready CTS: clear to send
RX: received data DTR: data terminal ready NC: no connection
RTS: request to send CD: carrier detect
Here are the Modbus port pinouts for the P190 Programming Panel:
SHIELD 1 1 SHIELD
TX 2 2 TX
RX 3 3 RX
RTS 4 4 RTS
CTS 5 5 CTS
DSR 6 6 DSR
GROUND 7 7 GROUND
CD 8 8 CD
DTR 20 20 DTR
SHIELD 1 1 SHIELD
TX 2 2 RX
RX 3 3 TX
RTS 4 4 DTR
CTS 5 5 GROUND
DSR 6 6 DSR
GROUND 7 7 RTS
NC 8 8 CTS
DTR 20 9 NC
Here are the Modbus port pinouts for an IBM-XT Personal Computer:
SHIELD 1 1 SHIELD
TX 2 2 TX
RX 3 3 RX
RTS 4 4 RTS
CTS 5 5 CTS
DSR 6 6 DSR
GROUND 7 7 GROUND
CD 8 8 CD
DTR 20 20 DTR
SHIELD 1 1 SHIELD
TX 2 2 RX
RX 3 3 TX
RTS 4 4 DTR
CTS 5 5 GROUND
DSR 6 6 DSR
GROUND 7 7 RTS
NC 8 8 CTS
DTR 20 9 NC
Here are the Modbus port pinouts for the J478/S978 Modicon Modems:
SHIELD 1 1 SHIELD
TX 2 2 TX
RX 3 3 RX
RTS 4 4 RTS
CTS 5 5 CTS
DSR 6 6 DSR
GROUND 7 7 GROUND
CD 8 8 CD
DTR 20 20 DTR
SHIELD 1 1 SHIELD
TX 2 2 RX
RX 3 3 TX
RTS 4 4 DTR
CTS 5 5 GROUND
DSR 6 6 DSR
GROUND 7 7 RTS
NC 8 8 CTS
DTR 20 9 NC
A Modbus network has one master device that originates all communications to
as many as 247 slave nodes throughout the plant (or in remote locations)—the to-
tal number of nodes supported depends on the communications equipment used.
A Modicon J478 master modem, for example, may support up to 32 slaves over a
twisted-pair cable network. Additional J478s may be used as repeaters to extend
the number of slave nodes on the network beyond 32.
Slave nodes may be linked via four-wire twisted-pair cable in a local installation up
to 15,000 ft (4572 m) long. They may also be linked via common carrier (phone
line, radio, microwave) over remote distances or linked locally via other dedicated
lines. A well-defined set of network guidelines is available for systems that use
Modicon modems and Belden 8777 twisted-pair cable (see Modbus System
Planning User’s Manual, ML-MBUS-PLN). The requirements for other arrange-
ments depend on the type of commercial facilities selected.
The master communicates at a set baud to all slaves on the network. The Mod-
bus ports on all slave devices must be set to a uniform set of communication pa-
rameters—this means that if some controllers have a more limited selection of
bauds, the entire network is constrained to those selections.
Modbus Plus is a local area network that allows host computers, programmable
controllers, and other data sources to communicate as peers throughout an indus-
trial plant via twisted-pair cable. A Modbus Plus network operates at a data trans-
fer rate of one million bits/s.
Programming of controllers
The network comprises one or more communication links; one comm link may
support up to 32 peer devices (nodes); by using an RR85 Repeater, you can join
two links to support up to a maximum of 64 Modbus Plus nodes on a network.
One communication link may be up to 1500 ft (450 m) long. Additional repeaters
(up to three between any two nodes) may be used to extend the network dis-
tance—the maximum cable length between any two nodes is 6000 ft (1800 m) in a
linear configuration. (The minimum cable length between nodes is 10 ft.)
32 Nodes
per Link Max.
The network medium is two-wire twisted-pair shielded cable, laid out in a sequen-
tial multidrop path directly between successive nodes. Use Belden type 9841
cable, available from Modicon in rolls of 100 ft (97-9841-100), 500 ft
(97-9841-500), and 1000 ft (97-9841-01K). Taps and splitters are not allowed.
A connector is attached to the cable at each node site and is plugged into a 9-pin
Modbus Plus port on each node. Use AS-MBKT-185 terminating connectors at
the two ends of a link, and AS-MBKT-085 inline connectors at all other node sites.
These connectors are available from Modicon.
For applications requiring a large number of nodes, you can use the BP85 Bridge
Plus device to join multiple Modbus Plus networks. The BP85 has two port con-
nectors and two sets of address switches and is connected as a node on two
Modbus Plus networks. The Bridge operates as an independent node on each
network, receiving and passing tokens according to each network’s address se-
quence.
BP85
Node 20
= Terminating Connector
= Inline Connector
The illustration on the following page shows an example of a Modbus Plus system
topology.
The Bridge Plus provides the benefit of faster communications on individual net-
works. Each network maintains faster communication between devices for
time-critical control applications, while the bridge facilitates intercommunication
between two networks.
= Terminating Connector
FactoryMate Plus = Inline Connector
MMI w SA85
Modbus
PS/2 w SM85 IBM--AT w SA85
Bridge
MUX
Modbus Plus
Station Station
#3 #3
Station Station
#4 #4
Station Station
#5 #5
2
4.9 A Modbus II Network
Programming of controllers
Modbus II communications are conducted over the same type of cable media
used in MAP networks.
Any node on the network may initiate data transfers across the network using
these two instructions. CRC-32 error checking diagnostics automatically assure
you of reliable data transfer.
Self--terminating Self--terminating
F Adapter F Adapter
1
4.10 Distributed Control Processing
A D908 module plugs into an option slot in a distributed 984-68x or -78x Control-
ler. It communicates over the coaxial link with an S908 (or S929) RIO Processor
in the supervisor. Up to 32 distributed controllers may be linked to the supervisory
controller, depending on that supervisor’s RIO capabilities.
Supervisory 984
(with S908 RIOP)
Distributed 984 Distributed 984
(with D908-120) (with D908-120)
The supervisory controller sees the distributed controller as a J890 I/O drop with
input and output addresses Traffic Copped to it. A special D908 Traffic Cop
screen is used in the panel software.
Distributed processing systems are well suited to transfer line control and material
handling applications. In certain cell applications, a supervisory 984 controller
with a C986 Coprocessor can act as the cell controller, doing data collection, data
logging, and program uploading/downloading and archiving; when process
changes are required, new data can be downloaded via the D908s to quickly
change parameters and resume production:
Mass Storage
Device Distributed 984 Distributed 984 Distributed 984
(with D908-110) (with D908-110) (with D908-110)
RIO Network
The illustration on the following page shows, in simplified form, how multiple net-
works types may be interconnected in a 984 control system. It shows networked
hierarchy for controlling a material handling environment.
Above the distributed network in the control hierarchy is a Modbus Plus network
used for data acquisition and management. It Modbus Plus bridge MUX links the
Modbus Plus network via a Modbus interface to the host computer that resides at
the top of the control hierarchy.
Host Computer
FactoryMate Plus
MMI w SA85
Bridge
MUX
Modbus Plus
3
Chapter 5
984 Memory Allocation
User Memory
State RAM
User Logic
Executive Firmware
User memory is the space provided in the controller for your logic program and for
system overhead. Optional user memory sizes varying from 1.5K ... 64K words
are available, depending on controller type and model. Each word in user
memory is stored on page 0 in the controller’s memory structure; words may be
either 16 or 24 bits long, depending on the controller’s CPU size.
page 0
CKSM Diagnostics
Configuration Table
Loadables
Traffic Cop
Approximately
Segment Scheduler
(129 words)
888 Words
Overhead STAT Block Tables
(up to 277 words)
System Diagnostics
User
Logic
User Application Program
System overhead comprises a set of tables that define the system’s size, struc-
ture, and status. Some tables in system overhead have a predetermined amount
of memory space allocated to them—for example, the configuration table always
contains 128 words and the order-of-solve table (or segment scheduler) always
contains 129 words. Other tables, such as the traffic cop, may consume a large
but nonpredetermined amount of memory. Optional pieces of system overhead,
such as a loadables table, may or may not consume memory depending on the
requirements of your application.
User memory is stored in CMOS RAM. In the event that power is lost, CMOS
RAM is backed up by a long-life (typically 12-month) lithium battery.
Ladder logic requires one word of either 16 bit or 24 bit memory to uniquely
identify each node in an application program. Contacts and coils each occupy
one node, and therefore one word. Function blocks, which usually comprise two
or three nodes, require two or three words, respectively. Other elements that con-
trol program scanning—start of a network (SON), beginning of a column (BOC),
and horizontal shorts—use one word of user logic memory as well. (A vertical
short does not use any user logic memory words.)
SON
BOC BOC BOC
SON = 1
BOC = 3
=3
=1
8 words
As part of the 984 configuration process (using the Configurator editor in the panel
software), you will specify a certain number of discrete outputs (or coils), discrete
inputs, input registers, and holding registers available for application control.
These inputs and outputs are placed in a table of 16-bit words in an area of sys-
tem memory called state RAM.
The system displays the various types of inputs and outputs using a reference
numbering system. Each reference number has a leading digit that identifies its
data type followed by a string of digits that defines it unique location in state RAM:
State RAM data are always 16 bit words and are stored on page F in System
Memory. The state RAM table is followed immediately by a discrete history table
that stores the state of the bits at the end of the previous scan, and by a table of
the current ENABLE/DISABLE status of all the discrete (0x and 1x) values in state
RAM.
page F
0000
State RAM
ENABLE/DISABLE Tables
Discrete History Tables
4x History Table
EOL Pointers
Crash Codes
Executive ID
Executive Rev #
16 bits
Counter input states for the previous scan are represented on page F in an
upcounter/downcounter history table. Each counter register is represented by a
single bit in a word in the table; a value of 1 indicates that the top input was ON in
the last scan, and a value of 0 indicates that the top input was OFF in the last
scan.
Words are entered into the state RAM table from the top down in the following
order:
Word 0001
0x
..
.
0x + n
1x
...
1x + n
The discrete words come first in the top-down entry procedure, first the 0x words
followed immediately by the 1x words. The register values follow; the blocks of 3x
and 4x register values must each begin at a word that is a multiple of 16. For ex-
ample, if you allocate five words for eighty 0x references and five words for eighty
1x references (5 words x 16 bits/word = 80), you have used words 0001 ... 0010.
Words 0011 ... 0016 are then left empty so that the first 3x reference begins at
word 0017.
For each discrete word allocated in state RAM, two words are allocated in the his-
tory/disable tables, which follow the state RAM table on page F in system
memory. The history/disable tables are generated from the bottom up in the fol-
lowing manner:
Word 0001
..
.
Output History Bits
..
.
Input History Bits
..
.
Output DISABLE Bits
..
.
Input DISABLE Bits Word 2048
The configuration table is one of the key pieces of overhead contained in system
memory. It comprises 128 consecutive words and provides a means of accessing
information defining your control system capabilities and your user logic program.
With your programming panel software, you can access the configurator editor,
which allows you to specify the configuration parameters—such as those shown
on the following page—for your control system.
• Discrete inputs
• Discrete outputs
• Input registers
• Holding registers
• I/O drops
• I/O modules
• Logic segments
• Modbus ports
• ASCII messages
• Total ASCII message words
A 0x coil can be set aside in the configuration to reflect the current status of the
controller’s battery backup system. If this coil has been set and is queried, it dis-
plays a discrete value of either 0, indicating that the battery system is healthy, or
1, indicating that the battery system is not healthy.
When a 4x holding register assignment is made in the configurator for the time of
day (TOD) clock, that register and the next seven consecutive registers (4x ...
4x + 7) are set aside in the configuration to store TOD information. The block of
registers is implemented as follows:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
For example, if you configured register 40500 for your TOD clock, set the bits ap-
propriately as shown above, then read the clock values at 9:25:30 on Tuesday,
July 16, 1991, the register values displayed in decimal format would read:
40500 0110000000000000
40501 3 Dec
40502 7 Dec
50503 16 Dec
40504 91 Dec
40505 9 Dec
40506 25 Dec
40507 30 Dec
Configuration Size
Special Functions
Loadables Instructions
Install loadable PROCEED or CANCEL Various 984 controllers support different kinds
Delete loadable(s) DELETE ALL, DELETE ONE, CANCEL of loadable instruction sets. Make sure that
your loadables and controller are compatible.
Write data as specified PROCEED or CANCEL NONE PROCEED will overwrite any previous
Configuration Table data.
5.5 The Traffic Cop Table
The traffic cop directs data flow between the input/output signals and the user log-
ic program; it tells the controller how to implement inputs in user logic and pro-
vides a pathway down which to send signals to the output modules. The traffic
cop table, which is stored on page 0 in system memory, consumes a large but not
predetermined amount of system overhead. Its length is a function of the number
of discrete and register I/O points your system has implemented and is defined by
the type of I/O modules you specify in the configuration table. The minimum al-
lowable size of the traffic cop table is nine words.
With your programming panel software, you can access a traffic cop editor that al-
lows you to define:
The number of discretes/registers that may be used for input and output
The number, type, and slot location of the I/O modules in the drop
The reference numbers that link the discretes/registers to the I/O modules
A 984 automatically translates symbolic ladder elements and function blocks into
database nodes that are stored on page 0 in system memory. A node in ladder
logic is a 16 or 24 bit word—an element such as a contact translates into one da-
tabase node, while an instruction such as an ADD block translates into three data-
base nodes.
The five most significant bits in a 16 bit node and the eight most significant bits in
a 24 bit node—the x bits—are reserved for opcodes. An opcode defines the type
of functional element associated with the node—for example, the code 01000
specifies that the node is a normally open contact, and the code 11010 specifies
that the node is the third of three nodes in a multiplication function block.
When the system is translating standard ladder logic elements and non-DX func-
tion blocks, it uses the remaining (y and z) bits as pointers to register or bit loca-
tions in State RAM associated with the discretes or registers used in your ladder
logic program.
With a 16 bit node, 11 bits are available as state RAM pointers, giving you a total
addressing capability of 2048 words. The maximum number of configurable regis-
ters in most 16 bit machines is 1920, with the balance occupied by up to 128
words (2048 bits) of discrete reference, disable, and history bits. An exception is
the 984-680/-685 Controllers, which have an extended registers option that sup-
ports 4096 registers in state RAM.
Note The opcodes for these standard ladder logic elements and in-
structions are hard-coded in the system firmware, and they cannot be
altered.
When you are using a 16 bit CPU, you are left with only four more x bit combina-
tions—11100, 11101, 11110, and 11111—with which to express opcodes for 18 DX
functions. To gain the necessary bit values, the system uses the three least sig-
nificant (z) bits along with the x bits to express the opcodes:
1 1 1 0 0 z z z
0 0 0 = R→T
0 0 1 = T→ R
0 1 0 = T→ T
0 1 1 = BLKM
1 0 0 = FIN
1 0 1 = FOUT
1 1 0 = SRCH
1 1 1 = STAT
1 1 1 0 1 z z z
0 0 0 = AND
0 0 1 = OR
0 1 0 = CMPR
0 1 1 = SENS
1 0 0 = MBIT
1 0 1 = COMP
1 1 0 = XOR
1 1 1 = BROT
1 1 1 1 0 z z z
0 0 0 = READ
0 0 1 = WRIT
0 1 0
0 1 1
For Loadable Options 1 0 0
1 0 1
1 1 0
1 1 1
In the 24 bit CPUs, the three most significant x bits are used to indicate the type of
DX function:
x x x 1 1 1 0 0 z z z
0 0 0 = R→T 0 0 0
0 0 1 = T→ R 0 0 1
0 1 0 = T→ T 0 1 0
0 1 1 = BLKM 0 1 1
1 0 0 = FIN 1 0 0
1 0 1 = FOUT 1 0 1
1 1 0 = SRCH 1 1 0
1 1 1 = STAT 1 1 1
x x x 1 1 1 0 1 z z z
0 0 0 = AND 0 0 0
0 0 1 = OR 0 0 1
0 1 0 = CMPR 0 1 0
0 1 1 = SENS 0 1 1
1 0 0 = MBIT 1 0 0
1 0 1 = COMP 1 0 1
1 1 0 = XOR 1 1 0
1 1 1 = BROT 1 1 1
x x x 1 1 1 1 0 z z z
0 0 0 = READ 0 0 0
0 0 1 = WRIT 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 For Loadable Options 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1
The z bits, which simply echo the three most significant x bits, may be ignored in
the 24 bit nodes.
00011100 1C R→T
00111100 3C T→R
01011100 5C T→T
01111100 7C BLKM
10011100 9C FIN
10111100 BC FOUT
11011100 DC SRCH
11111100 FC STAT
00011101 1D AND
00111101 3D OR
01011101 5D CMPR
01111101 7D SENS
10011101 9D MBIT
10111101 BD COMP
11011101 DD XOR
11111101 FD BROT
00011110 1E READ
00111110 3E WRIT
01111110 7E XMWT*
10011110 9E XMRD*
* XMWT and XMRD are used for extended memory capabilities available only in the
984B chassis mount Controller. They are not installed in other 24 bit controllers.
Note The opcodes for these standard ladder logic elements and in-
structions are hard-coded in the system firmware, and they cannot be
altered.
The y bits in a database node holding DX function data contain a binary number
that expresses the number of registers being transferred in the function.
A 16 bit database node has eight y bits. A 16 bit CPU is, therefore, machine lim-
ited to no more than 255 transfer registers per DX operation.
A 24 bit database node has 13 y bits. A 24 bit CPU is, therefore, capable of
reaching a theoretical machine limit of 8191 transfer registers per DX operation;
practically, however, the greatest number of transfer registers allowed in a 24 bit
DX operation is 999.
01011110 5E PID2
11011110 DE JSR
10111110 BE LAB
11111110 FE RET
01111111 7F EMTH
10011111 9F BLKT
10111111 BF CKSM or MSTR*
11011111 DF TBLK
*MSTR and CKSM share the same opcode and are mutually exclusive EPROM-based in-
structions. MSTR is included in the Executive of any 984 controller that employs Modbus
Plus, and the CKSM instruction is not included on these Executives. CKSM is provided in
several 984 controllers that do not implement Modbus Plus.
The PID2, BLKT, TBLK, MSTR, and CKSM instructions are also avail-
able as loadable instructions for some 984 controllers (when a control-
ler does not support these functions in any version of its Executive
firmware). The loadable versions of these instructions are assigned
the same opcodes.
Various ladder logic instructions are available only in loadable software packages.
When instructions are loaded to a controller, they are stored in RAM on page 0 in
system memory. They are not resident on the EPROM. The loadable functions
have the following opcodes:
11111111 FF HSBY
01011111 5F CALL, FNxx, or EARS (non--chassis mount)
00011111 1F MBUS
00111111 3F PEER
11011110 DE DMTH
10111110 BE MATH or EARS (for chassis mount only)
11111110 FE DRUM
01111111 7F ICMP
The easiest way to stay out of trouble is to never employ two loadables with con-
flicting opcodes in your user logic. If you are using MODSOFT panel software, it
allows you to change the opcodes for loadable instructions. The lodutil utility in
the Modicon Custom Loadable Software package (SW-AP98-GDA) also allows
you to change loadable opcodes—this software package is not available for all
984 controllers (see Section 21.1).
Because the 24 bit CPUs provide eight x bits per node, 28 (256) combinations are
available for opcode assignments. The 984B chassis mount Controller is the ex-
ception—it is design--limited to the x--bit assignments described in Section 6.2.2 in
order to enforce conformance with the 16 bit CPUs. The other 24 bit CPUs—e.g.,
the 984-780/-785, the Q984—can use all opcodes in the hexadecimal range
00 ... FF for loadables and user-defined function blocks.
The matrix on the following page shows how the opcode assignments, indicating
which codes are reserved, which codes may be flexibly assigned in either 16 bit or
24 bit CPUs, and which are available for 24 bit CPUs only:
You can modify the order in which logic is solved with the segment scheduler, an
editor available with your panel software that allows you to adjust the or-
der-of-solve table in system memory. With some 984 controllers, you may also
create an unscheduled segment that contains one or more ladder logic subrou-
tines, which can be called from the scheduled segments via the JSR function.
The networks that comprise the ladder logic segment(s) have a clearly defined
structure. Each network is a small ladder diagram bounded on the left by a power
rail and on the right by a rail which, by convention, is not displayed. Within the
rails, the network holds seven rungs (or rows) and eleven columns.
The 77 intersections of the rungs and columns are called nodes. Logic elements
—contacts, coils, horizontal and vertical shorts—and function block instructions
are inserted in the nodes of a network. Logic elements and instructions, which
are the fundamental building blocks of ladder logic, can occupy the whole 77-node
network area or just a portion of it.
In some panel software programming packages, the seven nodes in the 11th col-
umn are reserved for displaying coils. If your software treats coil usage this way,
then no other logic elements may be displayed in the 11th column, and the re-
maining 70 nodes may not be used for coils.
Although coils may be automatically displayed in the 11th column, they are not al-
ways solved there. The column in which coil 00101 is solved is determined by the
position of its controlling logic:
30101 00200
10033 00101
UCTR
40101 40005
00102
SUB
40102
00103
Coil 00103 is solved immediately after the UCTR function block, and coil 00102 is
solved immediately after the normally open contact (10033). Coil 00101 is the last
coil to be solved in this network.
There are six standard one-node ladder logic elements (contacts and coils) in all
984 Controller firmware packages:
Symbol Meaning
A normal coil
L
A latched coil
Instruction Meaning
Some special instructions are standard in some 984 controllers but are unavail-
able in others:
Instruction Meaning
* The MSTR block is available in the 984A/B/X chassis mount controllers only as a load-
able function, not in firmware.
All standard elements and instructions are stored in the system Executive
firmware.
Instruction Meaning
* The PID2, TBLK, and BLKT blocks are available in the 984A/B/X chassis mount con-
trollers only as loadable functions, not in firmware.
DX MOVE functions copy 16 bit words of data from one memory area to another.
The copied data can then be operated on, and the original data remain intact.
Groups of 16 discretes can also be placed in tables. The reference number used
is the first discrete in the group, and the other 15 are implied. The number of the
first discrete must be of the first of 16 type—00001, 10001, 00017, 10017, 00033,
10033, ... , etc.
Some DX move functions use a register to indicate which table position the rele-
vant data has been copied from or moved to. This register is called a pointer.
The pointer value must never exceed the table length. Zero is a valid pointer val-
ue, typically indicating that the next operation of the function block will be to copy
data from or read data to the first table position. (See examples in Chapter 11.)
The minimum table length is 1—i.e., one word or one register. The maximum
table length depends on the DX function and on the type of controller (16 or 24 bit
CPU).
Groups of 16 discretes can also be placed in tables. The reference number used
is the first discrete in the group, and the other 15 are implied. The number of the
first discrete must be of the first of 16 type—00001, 10001, 0017, 10017, 00033,
10033, ... , etc. (See examples in Chapter 12.)
The controller’s CPU scans the ladder logic program sequentially in this manner:
Nodes within each network are scanned top to bottom, left to right:, in the
following manner:
NETWORK 1 START
NETWORK 2
NEXT NETWORK
The controller begins solving logic within a network at the top of the leftmost col-
umn and proceeds down, then moves to the top of the next column and proceeds
down. Each node is solved in the order it is encountered in the logic scan. Power
flow within the network is always down each column from left to right, never from
bottom to top and never from right to left.
The time it takes a controller to solve a complete ladder logic program and update
all I/O modules is called scan time. Scan time comprises the time it takes the 984
controller to solve all scheduled logic—i.e., logic solve time, service I/O drops, and
perform system overhead—servicing communication ports and option processors,
executing intersegment transfer (IST) and system diagnostics.
Logic solve time is the time it takes to solve a complete logic program, indepen-
dent of the time it takes to service I/O or carry out any system overhead tasks.
Logic solve times are different in different types of 984 controllers—the various
times, measured in ms/Kwords of logic, are given in the chart in Section 1.2.
One Scan
= Logic Solve Time
This method of I/O servicing assures that the most recent input status is available
for logic solve and that outputs are written as soon as possible after logic solve.
One Scan
7.6.3 Overhead
An intersegment transfer occurs between each segment, at which time data are
exchanged between the I/O processor and the state RAM—previous inputs are
transferred to state RAM and the next outputs are transferred to the I/O processor.
The logic scan and I/O servicing for each segment are coordinated in this fashion.
Using direct memory access (DMA), ISTs typically take less than 1 ms/segment.
At the end of each scan, input messages to the communication ports (Modbus,
Modbus Plus, Modbus II) are serviced. The maximum time allotted for comm port
servicing is 2.5 ms/scan; typical servicing times are less than 1 ms/scan. If the
controller is using any option processors (C986 Coprocessors or D908 Distributed
Communications Processors), they are also serviced at the end of each scan and
typically require less than 1 ms/scan.
System diagnostics take from 1 ... 2 ms/scan to run, depending on controller type.
One Scan
The following ladder logic circuit may be entered into your program to evalute sys-
tem scan time:
01000
00500
01000
UCTR 00999
40001
10001
T.01
40003
10001
40002
100
DIV
40005
The upcounter counts 1000 scans as it transitions 500 times. When the counter
has transitioned 500 times, the T.01 timer turns OFF and stores the number of
hundredths of seconds it has taken for the counter to transition 500 times (1000
scans) in register 40003.
The value stored in 40002/40003 in the DIV block is then divided by 100 and the
result—which represents logic solve time in ms—is stored in register 40005.
The way that the 984 architecture simultaneously solves logic and services I/O
drops optimizes system throughput. Throughput is the time it takes for a signal
received at a field sensing device to be sent as an input to the controller, pro-
cessed in ladder logic, and returned as an output signal to a field working device.
Throughput time may be longer or shorter than a single scan; it gives you a realis-
tic measure of the system’s actual performance.
If the default order-of-solve table is in place, the system automatically solves the
logic starting at segment 01 and moving sequentially through segment nn.
Throughput is optimized when logic referring to real-world I/O is contained in the
segment that corresponds to that I/O drop.
For instance, if you are using I/O in drop 1 of a three-drop system to control a
pushbutton that starts a motor, the ideal condition is for logic segment 1 to contain
all the appropriate logic:
984 Controller
10001 Segment 1
00001
Drop 2
Drop 3
Scan 1 Scan 2
A B C D E
Throughput
The illustration above shows the throughput for drop 3—the time beginning with
field input data being read by the input modules in drop 3 and ending with the out-
put modules at drop 3 being updated with data from the CPU. Throughput in this
best case example is about 75% of total scan time. Five events are shown as
drop 3 throughput benchmarks:
Event A, where the inputs from drop 3 are available to the I/O processor
Event C, where the segment 3 logic networks (which correspond to drop 3 I/O)
are solved
Event D, where data are transferred from state RAM to the I/O processor
Event E, where the output data are written to the output modules at drop 3
You specify the number of segments and I/O drops with the configurator editor in
your panel software package. The default order-of-solve condition is segment 01
through segment nn consecutively and continuously, once per scan, with the cor-
responding I/O drops serviced in like order. You are able to change the order of
solve using the segment scheduler editor in your panel software package.
There may be times when you can modify the order of solve to improve overall
system performance. The segment scheduler can be used effectively to:
F1 F2 F3 F4 F5 F6 F7 F8 F9 L
SEGMENT - SCHEDULER
Number of Drops : 3
Min Register
Constant Sweep : OFF Scan Time --- ms :
4----
Ref. Seg- Drop Drop
Number Type Number Sense ment Input Output
Nr
1 CONTINUOUS 01 01 01
2 CONTINUOUS 02 02 02
3 CONTINUOUS 03 03 03
4 EOL
Suppose that your logic program is three segments long and that segment 3 con-
tains logic that is critical to your application—for example, monitoring a proximity
switch to verify part presence. Segments 1 and 2 are running noncritical logic
such as part count analysis and statistic gathering, The program is running in the
standard order-of-solve mode, and you are finding that the controller is not able to
read critical inputs with the frequency desired, thereby causing unexceptable sys-
tem delay.
Using the segment scheduler editor, you can improve the throughput for the criti-
cal I/O at drop 3 by scheduling segment 3 to be solved two (or more) times in the
same scan:
One Scan
By rescheduling the order-of-solve table, you actually increase the scan time, but
more importantly you improve throughput for the critical I/O supported by logic in
segment 3. Throughput is the better measure of system performance.
F1 F2 F3 F4 F5 F6 F7 F8 F9 L
SEGMENT - SCHEDULER
Number of Drops : 3
Min Register
Constant Sweep : OFF Scan Time --- ms :
4----
Ref. Seg- Drop Drop
Number Type Number Sense ment Input Output
Nr
1 CONTINUOUS 01 01 01
2 CONTINUOUS 03 03 03
3 CONTINUOUS 02 02 02
4 CONTINUOUS 03 03 03
5 EOL
When certain areas of a ladder logic program do not need to be solved continually
on every scan—for example, an alarm handling routine, a data analysis routine,
some diagnostic message routines—they can be designated as controlled seg-
ments by the segment scheduler editor. Based on the status of an I/O or internal
reference, a controlled segment may be scheduled to be skipped, thereby reduc-
ing scan time and improving overall system throughput.
For example, suppose that you have some alarm handling logic in segment 2 of a
three-segment logic program. You can use the segment scheduler editor to con-
trol segment 2 based on the status of a coil 00056—if the coil is ON, segment 2
logic will be activated in the scan, and if the coil is OFF the segment will not be
solved in the scan. I/O servicing is still performed, regardless of the conditional
status.
Here is how the MODSOFT segment scheduler would show the resulting or-
der-of-solve table:
F1 F2 F3 F4 F5 F6 F7 F8 F9 L
SEGMENT - SCHEDULER
Number of Drops : 3
Min Register
Constant Sweep : OFF Scan Time --- ms :
4----
Ref. Seg- Drop Drop
Number Type Number Sense ment Input Output
Nr
1 CONTINUOUS 01 01 01
2 CONTINUOUS 03 03 03
3 CONTROLLED 00056 ON 02 02 02
4 CONTINUOUS 03 03 03
5 EOL
When you find that the frequency of standard end-of-scan servicing of communi-
cation ports, option processors, or system diagnostics is inadequate for your
application requirements, you can increase service frequency by inserting one or
more reset watchdog timer routines in the order-of-solve table. Each time this
routine is encountered by the CPU, it causes all communication ports to be serv-
iced and causes the system diagnostics to be run.
F1 F2 F3 F4 F5 F6 F7 F8 F9 L
SEGMENT - SCHEDULER
Number of Drops : 3
Min Register
Constant Sweep : OFF Scan Time --- ms :
4----
Ref. Seg- Drop Drop
Number Type Number Sense ment Input Output
Nr
1 CONTINUOUS 01 01 01
2 WDT RESET
3 CONTINUOUS 02 02 02
4 WDT RESET
5 CONTINUOUS 03 03 03
6 EOL
An Order-of-Solve Table Rescheduled for Three Comm Port Servicings per Scan
Sweep functions allow you to scan a logic program at fixed intervals. They do not
make the controller solve logic faster or terminate scans prematurely.
Constant Sweep allows you to set target scan times from 10 ... 200 ms (in multi-
ples of 10). A target scan time is the time between the start of one scan and the
start of the next; it is not the time between the end of one scan and the beginning
of the next.
If a Constant Sweep is invoked with a time lapse smaller than the actual scan
time, the time lapse is ignored and the system uses its own normal scan rate.
The Constant Sweep target scan time encompasses logic solving, I/O and
Modbus port servicing, and system diagnostics. If you set a target scan of 40 ms
and the logic solving, I/O servicing, and diagnostics require only 30 ms, the con-
troller will wait 10 ms on each scan.
The Single Sweep function allows your controller to execute a fixed number of
scans (from 1 ... 15) and then to stop solving logic but continue servicing I/O.
This function is useful for diagnostic work—it allows solved logic, moved data, and
performed calculations to be examined for errors.
Relay Contacts
Normally Open
A normally open contact passes power when its referenced coil or input is ON.
Normally Closed
A normally closed contact passes power when its referenced coil or input is OFF.
Here is an example of how you might use two sets of normally open and normally
closed contacts to create logic for a momentary pushbutton switch:
Physical Ladder
Inputs Logic
Input
Module 10001
10001 No Power Flow
Pushbutton Open
10001
Passes Power
Input 10002
Module Passes Power
10002
Pushbutton Closed
10002
No Power Flow
A positive transitional contact passes power for only one scan as the contact or
coil transitions from OFF to ON.
ON
OFF
Controller State
CLOSE
OFF
Power Flow
One
Scan
Negative Transitional
A negative transitional contact passes power for only one scan as the contact or
coil transitions from ON to OFF.
ON
OFF
Controller State
CLOSE
OFF
Power Flow
One
Scan
A vertical short connects contacts or function blocks one above the other in a net-
work column. Vertical shorts can also be used to connect inputs or outputs in a
function block to create either/or conditions. When two contacts are connected by
vertical shorts, power is passed when one or both contacts receive power. A ver-
tical short does not consume any user memory.
Horizontal shorts are used in combination with vertical shorts to expand logic with-
in a network without breaking the power flow. A horizontal short consumes one
word of memory in a 16 bit CPU and 1.5 words in a 24 bit CPU.
Horizontal and vertical shorts can be combined with relay contacts to create an
either/or condition in ladder logic.
Horizontal short
Power will pass through to energize coil 00001 if either contacts 10001 and 10002
are energized or if contact 10003 is energized.
Normal Coil
Latched Coil
If a latched coil has been energized at the time of a controller power loss, the coil
will come back up in the same state for one scan once power has been restored.
Input Output
10001 Module Module 00001
10001 00001
Each network can contain a maximum of seven coils. Each 0x reference number
can be used as a coil only once, but it can be referenced to any number of relay
contacts.
Via panel software, you may disable a logic coil or a discrete input in your logic
program. A disable condition will cause the input field device to have no control
over its assigned 1x logic and the logic to have no control over the disabled 0x
value.
The MEMORY PROTECT switch on your 984 controller must be OFF before you
disable (or enable) a coil or a discrete input.
The panel software also provides FORCE ON and FORCE OFF capabilities.
When a coil or discrete input has been disabled, the only way you can change its
state from OFF to ON is with FORCE ON, and the only way to change from ON to
OFF with FORCE OFF.
Two counter instructions are available, UCTR and DCTR, for up counting and
down counting. Both are designed to count control input transitions from OFF to
ON either up to or down from a counter preset value. Each is a two-node function
block structured as follows:
A decimal ranging from 1 ... 999 in 16 bit CPUs and 1 ... 9999 in 24 bit CPUs
The bottom node signifies the DCTR or UCTR function and contains a holding
register (4x) that stores the accumulated count.
00100
10027 00077
UCTR
40007
00077 00055
When contact 10027 is energized, CONTROL IN receives power, and, since con-
tact 00077 is also receiving power, UCTR is enabled.
Each time contact 10027 transitions from OFF to ON, the accumulated count val-
ue increments 1. When the value reaches 100 (when contact 10027 has transi-
tioned 100 times), the top output passes power. Coil 00077 is energized, and coil
00055 is de-energized.
Contact 00077 loses power when coil 00077 is energized, and the accumulated
count value is reset to 0 on the next scan.
On the next scan, coil 00077 is de-energized. Contact 00077 is then re-energized
and the UCTR function is enabled.
Three timer instructions are available for timing an event or creating a delay.
They measure time in seconds (T1.0), in tenths of a second (T0.1), and in hun-
dredths of a second (T.01). Each timer is a two-node function block:
A decimal ranging from 1 ... 999 in 16 bit CPUs and 1 ... 9999 in 24 bit CPUs
The bottom node indicates that the timer is incrementing as a T1.0, T0.1, or T.01
counter and contains a holding register (4x) that stores accumulated time.
The example above assumes that 10002 is closed (timer enabled) and that the
value contained in register 40040 is 0. Because 40040 does not equal the timer
preset (5), coil 00107 is OFF and coil 00108 is ON.
When 10002 is opened, 40040 resets to 0, coil 00107 goes OFF, and 00108 goes
ON.
Note If the accumulated time value is less than the timer preset val-
ue, the bottom output will pass power even though no inputs to the
block are present.
00060
00001
T1.0
40053
00001
00060
00001 00002
UCTR
40052
00002
00024
00002 00003
UCTR
40051
00003
The first function block above is a T1.0 instruction programmed as a one minute
timer. When logic solving begins, coil 00001 is OFF—both the top and bottom in-
puts of the timer receive power.
Register 40053 starts incrementing time in seconds. After 60 increments, the top
output passes power and energizes coil 00001. Register 40053 is reset. Register
40052 in the first up counter block increments by 1, indicating that one minute has
passed.
Because the T1.0 block is no longer equal to the preset, coil 00001 is de-ener-
gized and the timer resumes incrementing seconds. When the value in 40052
reaches 60, the top output in the first up counter passes power and energizes coil
00002.
Register 40052 is reset, and the accumulated count in the second up counter
(register 40051) increases by 1, indicating that one hour has passed.
The correct time of day can be read in registers 40051 (indicating hours), 40052
(indicating minutes), and 40053 (indicating seconds).
ADD
SUB
MUL
DIV
A DIV Example
The ADD instruction adds value 1 to value 2 and stores the sum in a holding reg-
ister. ADD is a three-node function block:
value 2
ADD
sum
The top node and middle node contain value 1 and value 2, respectively—they
can be:
Decimals ranging from 1 ... 999 in a 16 bit CPU and from 1 ... 9999 in a 24 bit
CPU
The bottom node indicates that this is an ADD function and contains a holding
register (4x) where the sum of the addition is stored.
SUB
value 1 < value 2
result
The top node and middle node are value 1 and value 2, respectively—they can
be:
Decimals ranging from 1 ... 999 in a 16 bit CPU and from 1 ... 9999 in a 24 bit
CPU
The bottom node indicates that this is a SUB function and contains a holding reg-
ister (4x) where the result of the subtraction is stored.
The MUL instruction multiplies value 1 by value 2 and stores the result in two
holding registers. MUL is a three-node function block:
value 2
MUL
result:
high order low order
The top node and middle node are value 1 and value 2, respectively—they can
be:
A decimal ranging from 1 ... 999 in a 16 bit CPU and from 1 ... 9999 in a 24 bit
CPU
The bottom node indicates that this is a MUL function and contains two consecu-
tive a holding registers (4x and 4x + 1) where the result of the multiplication is
stored.
The higher order digits are stored in the register specified in the bottom node, and
the lower order digits are stored in the next sequential register. For example, if
the top node value is 8000 and the middle node value is 2, the result (16,000) is
stored in two sequential registers: 4x contains the higher order digits (0001), and
4x + 1 contains the lower order digits (6000).
The DIV instruction divides value 1 by value 2 and stores the result and the re-
mainder in two consecutive holding registers. DIV is a three-node function block:
DIV
value 2 = 0
result: remainder
A decimal ranging from 1 ... 999 in a 16 bit CPU and from 1 ... 9999 in a 24 bit
CPU
Two consecutive input registers, 3x for the higher order digits and 3x + 1 for the
lower order digits
Two consecutive holding registers, 4x for the higher order digits and 4x + 1 for
the lower order digits
A decimal ranging from 1 ... 999 in a 16 bit CPU and from 1 ... 9999 in a 24 bit
CPU
The bottom node indicates that this is a DIV function and contains two holding
registers (4x and 4x + 1). The result of the division is stored in the first register,
and the remainder is stored in the second register. The remainder may be ex-
pressed as a fraction or a decimal, depending on whether the middle input is a 1
or a 0.
00105
10001
00025
10002
DIV
40270
The result (4) is stored in register 40270, and the remainder (5) is stored in regis-
ter 40271.
00011
Note The vertical short to coil 00011 must be to the left of the vertical
shorts linking the three SUB block outputs.
When the top input of the SUB function block receives power, the number 32 is
subtracted from the value in register 30001, which represents some number of de-
grees Fahrenheit. The result is placed in register 41201.
The top input to the MUL function block then receives power, whether the SUB re-
sult is positive, negative, or 0. If the SUB result is negative, coil 00011 is ener-
gized to indicate a negative value.
The value in register 41201 is then multiplied by 5, and the result is placed in reg-
ister 41202. The top input of the DIV function block is then energized, and the val-
ue in register 41202 is divided by 9. The result, which is the temperature conver-
sion in degrees Centigrade, is placed in register 40001.
SRCH
BLKM
The 984 standard instruction set provides three function blocks for moving register
and table data—one for moving register values to a table (R→T), one for moving
table values to a single register (T→R), and one for moving values from one table
to another (T→T). Each of these register transfer instructions is a three-node
function block, and the system can accommodate the transfer of one register per
scan.
The value in the middle node is a pointer to the register in the destination table
where data will be moved in this scan. The pointer is a 4x register, and the first
register in the destination table is 4x + 1. The number of registers in the destina-
The bottom node indicates that the function is a register-to-table transfer instruc-
tion and specifies the table length—it may range from 1 ... 255 in 16 bit CPUs and
from 1 ... 999 in 24 bit CPUs.
An R→T Example
30001
10001
40340
10002 00135
R→T pointer
00005
40340
10003
source destination
30001 40341
40342
40343 max length = 255/999
40344
40345
The first transition of 10001 copies 30001 to 40341 and increments the pointer
value stored in 40340 to 1; its second transition copies 30001 to 40342 and incre-
ments the pointer value to 2; and so on through five transitions. At the fifth transi-
tion, which copies 30001 to 40345 and increments the pointer value to the table
length, the middle output passes power, energizing coil 00135. No R→T opera-
tions are possible while these two values are equal.
If, after the second transition, 10002 were to be energized, the pointer value could
not be changed. All subsequent transitions of 10001 would cause the value in
30001 to be copied to 40343. When 10003 is energized, the pointer will be reset
to 0.
The T→R instruction copies the bit pattern of a register or 16 discretes located
within a table to a specific holding register:
pointer to
ON freezes the pointer source table pointer = table length
The value in the middle node is a pointer to the register in the source table that
will be moved in this scan. The pointer is a 4x register, and the destination regis-
ter is 4x + 1. A value of 0 in the pointer equals the first register in the table.
The bottom node indicates that the function is one of the three register transfer in-
structions and specifies the length of the source table—in the range 1 ... 255 in 16
bit CPUs and 1 ... 999 in 24 bit CPUs. The number specifies the total number of
registers to be transferred.
40371
10001
40376
10002 00136
T→ R
00005 pointer
10003 40376
destination source
40377 40371
40372
40373
40374
40385
The first transition of 10001 copies the contents of 40371 to register 40377 and in-
crements the pointer value stored in 40376 to 1. The second transition of 10001
copies 40372 to 40377 and increments the pointer value to 2; the third transition
copies 40373 to 40377 and increments the pointer value to 3; the fourth transition
copies 40374 to 40377 and increments the pointer value to 4.
The fifth transition of 10001 copies 40375 to 40377 and increments the pointer
value to 5. Because the pointer value now equals the table length, the middle
output passes power, energizing coil 00136. No T→R operations are possible
while these two values are equal.
If, after the second transition of 10001, 10002 were to be energized, the pointer
value could not be changed. All subsequent transitions of 10001 would cause the
value in 40343 to be copied to 40377.
The T→T instruction copies the bit pattern of a register or 16 discretes from a po-
sition within one table to the same position in a second table of holding registers:
ON = move data and increment pointer; source table Copies top input
maximum pointer value = table length
The value in the middle node is a pointer to the register in the source table to be
moved in the scan and to the register in the destination table where the source
register will go. The pointer is a 4x register, and the first register in the destination
table is 4x + 1. The length of the two tables must be equal, and this length is spe-
cified in the bottom node. A value of 0 in the pointer equals the first register in the
table.
The bottom node indicates that the function is a table-to-table register transfer in-
struction and specifies the table length for both the source and destination tables.
The length may range from 1 ... 255 in 16 bit CPUs and 1 ... 999 in 24 bit CPUs.
30001
10001
40380
10002 00137
T→ T
00003 pointer
10003 40380
source destination
30001 40381
30002 40382
30003 40383
The first transition of 10001 moves the contents of 30001 to register 40381 and in-
crements the pointer value stored in 40380 to 1, and the second transition moves
the contents of 30002 to register 40382 and increments the pointer value to 2.
The third transition of 10001 moves the contents of 30003 to register 40383 and
increments the pointer value to 3. Because the pointer value now equals the table
length, the middle input passes power and energizes coil 00137. No T→T opera-
tions are possible while these two values are equal.
If, after the second transition of 10001, 10002 were to be energized, the pointer
value would be locked to 2, and all subsequent transitions of 10001 would cause
the value in 30003 to be moved to register 40383.
The standard 984 instruction set provides two function blocks that are used to pro-
duce a first in-first out queue. The FIN instruction copies the bit pattern of any
register or 16 discretes to the first register in a table of holding registers; this reg-
ister is at the top of the queue:
FIN FIN FIN
1111 1111 2222 2222 3333 3333
Source Source 1111 Source 2222
1111
Stack Stack Stack
The FOUT instruction moves the bit pattern of a holding register within a table to a
destination register or to 16 discrete outputs; the oldest data in the queue is
moved first. FOUT should be placed before FIN to ensure that the oldest data are
removed from a full queue before the newest data are entered. If the FIN block
were to appear first, the attempt to enter the new data would be ignored if the
queue were full.
FIN
3333 4444 4444
2222 FOUT Source 3333
1111 1111 2222
Stack Destination Stack
The source, which is specified in the top node of the FIN block, may be:
The pointer, which is specified in the middle node of the FIN block and the top
node of the FOUT block, is a holding register (4x). A pointer indicates where in
the table the data will be taken from or written to.
The bottom node indicates that the block is either an FIN or FOUT instruction and
specifies the queue length, which may range from 1 ... 100 and which represents
the number of registers in the queue.
The SRCH instruction searches a table of registers for a specific bit pattern.
SRCH is a three-node function block:
SRCH
table length
The middle node must be a holding register (4x). It is a pointer to the table being
searched (as specified in the top node). The next consecutive register, 4x + 1,
contains the value or bit pattern being searched for.
The bottom node indicates that this is a SRCH function and specifies a table
length, which may range from 1 ... 100.
Here we search a five-register table for the register that contains the value 3333.
40421
10001
40430
10002 00142
SRCH
00005
table to be searched
40421 = 1111 40430 = pointer
40422 = 2222 40431 = 3333 = value searched for
40423 = 3333
40424 = 4444
40425 = 5555
The source table is searched for a 3333 on every scan where 10001 transitions
from OFF to ON. If 10002 is OFF, the SRCH function finds a match at register
40423 and stops searching for the remainder of the scan. It sets the pointer value
to 3 for one scan, indicating that a match exists in table position 3. Coil 00142 is
energized for one scan.
When 10001 is transitioned a second time, it starts again at 40421 and searches
for a match. It will find it again at 40423.
When 10002 is energized and 10001 transitions from OFF to ON, the source table
is searched for a 3333. The SRCH function finds a match at register 40423 and
stops the SRCH. It sets the pointer value to 3, indicating that a match exists in
table position 3. Coil 00142 is energized for one scan.
BLKM is the block move instruction—in one scan, it copies the entire contents of
one table to another table of outputs or holding registers. BLKM is a three-node
function block:
destination
BLKM
table length
The first 0x in a table of coils or output registers (the one and only time that the
referenced coils may be used)
The bottom node indicates that this is a BLKM function and specifies a table size
that can range from 1 ... 100.
You can use ladder logic to write specific process programs (or recipes), store
each in a unique table, then write a general process program and store it in anoth-
er working table. The recipe tables must be structured with similar information in
corresponding registers—if a heating temperature is in the third register in one
recipe table, it should be in the third register in all recipe tables. Recipes can be
pulled into the generic process program with BLKM functions:
40101
10101 10102 10103
40201
BLKM
00008
40109
10102 10101 10103
40201
BLKM
00008
40117
10103 10101 10102
40201
BLKM
00008
The process is controlled with three input switches—10101, 10102, and 10103.
To run process A, turn on 10101, and leave 10102 and 10103 off. When input
10101 is energized, it passes power through normally closed contacts 10102 and
10103. A BLKM function moves the recipe for process A from registers 40101 ...
40108 to registers 40201 ... 40208. This table of registers is a working table, with
each register controlling a part of the general process. By using one working
table, you can control the output for three separate processes with only one pro-
gram.
COMP
CMPR
The standard 984 instruction set provides three function blocks that perform AND,
OR, and Exclusive OR Boolean operations. The AND instruction logically ANDs
each bit in a source matrix with corresponding bits in a destination matrix. The re-
sult is placed in the destination matrix, overwriting the previous contents:
source 0 1 1 0
ANDing
Operation
destination 0 0 0 0 1 1 1 0
The OR instruction logically ORs each bit in a source matrix with corresponding
bits in a destination matrix:
source 0 1 1 0
ORing
Operation
destination 0 0 0 1 1 1 1 1
source 0 1 1 0
XORing
Operation
destination 0 0 0 1 1 0 1 1
destination
AND, OR,
or XOR
matrix length
If you specify a 0x in the middle node, it counts as the one and only time that the
referenced coils may be used.
The bottom node indicates which type of Boolean function to implement and spec-
ifies a matrix length that may range from 1 ... 100 words—i.e., a length of 2 indi-
cates 32 bits.
ANDing Example
source matrix
40600 40600 = 1111111100000000 40601 = 1111111100000000
10001
destination matrix
40604 40604 = 1111111111111111 40605 = 0000000000000000
When 10001 passes power, the bit matrix formed by registers 40600 and 40601
are ANDed with the bit matrix formed by registers 40604 and 40605. The result is
copied into registers 40604 and 40605, overwriting the previous bit pattern. (If
you want to keep the original bit pattern of registers 40604 and 40605, copy the
information into another table before performing an AND operation using a
BLKM.)
ORing Example
source matrix
40600 40600 = 1111111100000000 40601 = 1111111100000000
10001
destination matrix
40606 40606 = 1111111111111111 40607 = 0000000000000000
OR ORed destination
00002 40606 =11111111111111111 40607 = 1111111100000000
Whenever 10001 passes power, the bit matrix formed by registers 40600 and
40601 is ORed with the bit matrix formed by 40606 and 40607. The result is co-
pied into registers 40606 and 40607.
source matrix
40600 40600 = 1111111100000000 40601 =
10001 1111111100000000
destination matrix
40608 40608 = 1111111111111111 40609 = 0000000000000000
When 10001 passes power, the bit matrix formed by registers 40600 and 40601 is
XORed with the bit matrix formed by 40608 and 40609. The result is copied into
registers 40608 and 40609.
The COMP instruction complements the bit pattern of one matrix (changes all 0’s
to 1’s and all 1’s to 0’s), then copies the result into a second matrix, all in the same
scan. COMP is a three-node function block:
destination
COMP
matrix length
The matrix specified in the top node is the data source; it may be:
The matrix specified in the middle node is the destination for the complemented
data; it may be:
If the middle node entry is a 0x, it counts as the one and only time that the refer-
enced coils may be used.
The bottom node indicates that this is a COMP function and specifies a matrix
length that can range from 1 ... 100.
40600
10001
matrix a
40602 40600 = 1111111100000000 40601 = 1111111100000000
When 10001 passes power, the bit value complements in the source matrix (regis-
ters 40600 and 40601) are copied into the destination matrix (registers 40602 and
40603).
Warning COMP will override any disabled coils within the desti-
nation matrix without enabling them. This can cause injury if a
coil has been disabled for repair or maintenance because the
coil’s state can change as a result of the COMP instruction.
The CMPR instruction compares the bit pattern of one matrix against the bit pat-
tern of a second matrix for discrepancies. CMPR is a three-node function block:
CMPR
State of miscompared bit
matrix length
in matrix a
The matrix in the top node specifies the source data to be compared; it may be:
The middle node must be a holding register (4x); it is the pointer to a particular bit
in the matrix starting with 4x + 1.
The bottom node indicates that this is a CMPR function and specifies a matrix
length that can range from 1 ... 100.
40620
10001
40622
10002 00143
CMPR
00002
00144
matrix a
40620 = 0000000000000000 40621 = 1000000000000001
pointer
40622
matrix b
40623 = 0000000000000000 40624 = 0000000000000000
In this example, the comparison continues until bit 17, where matrix a = 1 and ma-
trix b = 0. At this point, when 40622 = 17, the function stops; 00143 and 00144
energize for one scan. On the second transition of 10001, the function starts
again at bit 1 and stops again when 40622 = 17.
If 10002 is de-energized, the first transition of 10001 will stop the function at
40622 = 17; 00143 and 00144 will energize for one scan. On the second transi-
tion of 10001, the function will stop at 40622 = 32; 00143 and 00144 will energize
for one scan.
Coil 00144 indicates the sense of the bit in the source matrix when a miscompare
occurs.
The standard 984 instruction set provides two function blocks that allow you to ex-
amine and modify current bit values inside data tables in a matrix. The SENS in-
struction examines and reports the sense—1 or 0—of specific bits within a matrix.
The MBIT instruction modifies a specific bit within a matrix—a 0 bit is set to 1 or a
1 bit is cleared to 0. One bit may be sensed or modified per scan. Both instruc-
tions are three-node function blocks:
SENS
Reset pointer to 1 pointer > matrix length
matrix length
MBIT
Increment pointer pointer > matrix length
after modification matrix length
Note The differences in each of the function blocks are in the way
the middle and bottom inputs are treated; the block nodes themselves
are essentially the same.
The top node is a pointer to a value to be sensed or modified in the data table; it
may be:
164 DX Matrix Functions GM--0984--SYS
A constant when the value falls in the range 1 ... 999 in 16 bit CPUs or
1 ... 9600 in 24 bit CPUs
An input register (3x) that may hold a value in the range 1 ... 4080 in 16 bit
CPUs or 1 ... 9600 in 24 bit CPUs
A holding register (4x) that may hold a value in the range 1 ... 4080 in 16 bit
CPUs or 1 ... 9600 in 24 bit CPUs
The middle node is the first word or register in the data table; it may be:
The bottom node indicates that the function is either a SENS or MBIT operation
and specifies a matrix length that may range from 1 ... 255 in 16 bit CPUs and
from 1 ... 600 in 24 bit CPUs. The number represents registers or groups of 16
discretes—for example, 200 = 3200 bits.
The BROT instruction rotates or shifts the bit pattern of a matrix. The bits shift
one position per scan. BROT is a three-node function block:
The bottom node indicates that the function is a BROT operation and specifies a
matrix length that may range from 1 ... 100.
A simple ladder logic construction of a STAT block and a SENS block allows you
to report system status information as part of your User Logic program. In this ex-
ample, bit 12 of register 40201 is being checked. All other bits may be checked
using the same method:
40201 00012
STAT 40201
00043
00003
SENS
00001
The top input to the STAT block receives power on every scan because it is at-
tached to the power rail. Status information is recorded in registers
40201 ... 40243. Register 40201 holds the controller status, which needs to be in-
terpreted.
Since each bit’s state represents different information, you can use a SENS block
to report incoming bit status. Connect the top output of the STAT block to the top
input of the SENS block. This construction lets you check and report the com-
plete bit status on every scan.
T→ R ADD ADD
00084 40202 40201
40201 40201
00003
40203 40201
DIV XOR
AVERAGE = 40301 . 40302 40301 00003
When input 10006 receives power, the top input to the T→R block receives power
and the value in the first register in the table of registers 40101 ... 40184 is copied
into the middle node (40204) of the first ADD block. The middle node (40203) in
the DIV block holds the pointer value. Because the top output of the T→R block
is passing power, the first ADD block receives power, causing the value copied to
40204 to be added to 40202. Register 40202 equals 0 to start.
This routine continues until the pointer value in the T→R block (40203) equals the
table length—84. The middle output in the T→R block then passes power, and
the DIV block receives power. The values in registers 40201 and 40202 are di-
vided by 84 (the value in the middle node of the DIV block). The result is placed
in register 40301, and the remainder is placed in register 40302. Because the
middle input of the DIV block is receiving power, the remainder is expressed as a
decimal.
The top output of the DIV block passes power, and the XOR block receives power.
By using the XOR function to exclusively OR the values in matrix 40201 ... 40203
with themselves, you clear the matrix to 0. The top output of the XOR block
passes power to coil 00003, indicating that the current table averaging operation
is complete and that a new one should start.
READ
WRIT
The READ instruction provides the ability to read data entered at an ASCII device
through the RIO interface and into 984 Memory. READ is a three-node function
block:
The first register in the ASCII control block is specified in the top node. It is the
first of seven consecutive (4x) holding registers:
Register Definition
4x bits 0 ... 5 = port number (1 ... 32); bits 6 ... 15 = error code
4x + 1 message number
4x + 2 number of registers required to satisfy format
4x + 3 number of registers transmitted thus far
4x + 4 status of solve
4x + 5 unassigned
4x + 6 checksum of registers 0 ... 5
The 10-character ASCII field AAAAAAAAAA is the variable data field; variable
data must be entered via an ASCII input device.
The bottom node indicates that this is an ASCII READ function, and it contains a
number specifying length of the destination table. Table length may range from
1 ... 255 in a 16 bit CPU and from 1 ... 999 in a 24 bit CPU.
The WRIT instruction provides the ability to send a message from the 984 control-
ler over the RIO communications link to an ASCII device. WRIT is a three-node
function block:
ASCII
Power pauses WRIT control block Error condition detected
function
(for one scan)
Power aborts WRIT WRIT
function WRIT complete (for one scan)
table length
The source register in the top node may be either the first (3x) input register or the
first (4x) holding register in a table whose length is specified in the bottom node.
This table will contain the data required to fill the variable field in a message.
Consider the following WRIT message
The 3-character ASCII field III is the variable data field; variable data are
loaded, typically via DX moves, into a table of variable field data.
4x bits 0 ... 5 = port number (1 ... 32); bits 6 ... 15 = error codes
4x + 1 message number
4x + 2 number of registers required to satisfy format
4x + 3 number of registers transmitted thus far
4x + 4 status of solve
4x + 5 unassigned
4x + 6 checksum of registers 0 ... 5
The bottom node indicates that this is an ASCII READ function, and it contains a
number specifying length of the source table. Table length may range from
1 ... 255 in a 16 bit CPU and from 1 ... 999 in a 24 bit CPU.
The ASCII READ and WRIT function blocks provide the routines necessary for
communication between the ASCII message table in 984 system memory and an
RIO interface module that supports ASCII at your RIO drops (such as a J812,
J892, P892, or P453). These routines verify correct ASCII parameters—for exam-
ple, port # and message #—lengths of variable data fields, error detection and re-
cording, and RIO interface status.
Each function requires two tables of registers: one to retrieve and store variable
data and the other to identify which port and message numbers are to be used.
The port and message table contains seven registers, and the size of the variable
data table needs to be specified. The balance of the registers is used for
housekeeping.
The 984 provides support logic to monitor the status of a READ or WRIT function,
detect errors, and enable you to take corrective action. Two basic errors that re-
quire action are declared (detected) errors and timeout errors.
Once a READ or WRIT block has been activated (power transitioned from low to
high at the top input), you may remove power from the node; the block remains
active for as many scans as are necessary to complete the message transaction.
Power at the middle or bottom input will stop the function.
When the middle input receives power, the READ/WRIT function pauses—i.e., the
middle input deactivates the function. When power is removed from the middle in-
put, the READ/WRIT function continues from where it was interrupted unless
there has been some communication at the port during the pause. If there has
been communication, the message transaction starts at the beginning.
When the bottom input receives power, the READ/WRIT function is aborted. The
middle output (error condition detected) passes power for one scan, then loads
the four most significant bits of the register specified in the top node with error
code 6:
To restart an ASCII READ/WRIT function after an abort, the top input must be
cycled from low to high.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 An error has been detected in the input to the RIO interface from
the ASCII device.
2 An exception response from the RIO interface indicates bad data.
3 A sequenced number from the addressed RIO interface differs from
the expected value.
4 There is a user register checksum error—often caused by altering
READ/WRIT registers while the block is active.
5 An invalid port or message number has been detected.
6 A user-initiated abort is indicated; the bottom input of the READ/
WRIT block is energized.
7 No response from the drop indicates a communication error.
8 A node has aborted because of the use of the SKP function.
9 The ASCII message area has been scrambled. Reload memory.
A A port has not been configured in the traffic cop (J892 only).
B This error indicates an illegal ASCII request (J892 only).
C An unknown response has been received from the ASCII port (J892
only).
D An illegal ASCII element has been detected in user logic—
e.g., Duplicate Block.
F The (S901 or S908) RIO processor in the 984 is down.
11 The input from the ASCII device is not compatible with the specified
format.
10 There is an input buffer overrun—data are being received too quickly at
the (J812/J892) RIO interface.
9 A USART error has been detected—a bad byte has been received at the
(J812/J892) RIO interface.
8 An illegal format has been processed—the format has not been received
properly by the (J812/J892) RIO interface.
7 The ASCII device is off-line—it has been turned off, disconnected, put
into off-line operation, or has activated normal handshaking. Check the
cabling to the device.
6 An ASCII message has terminated early (keyboard mode only).
Controller Status
The STAT instruction lets you access the 984 status table in system memory; here
vital system diagnostic information is written into a table of registers or discretes,
as specified in the destination node. This information includes
Controller status
STAT
table length
The top destination node, where the first word of system status is written, may be
The bottom node indicates that this is a STAT function and specifies the number
of registers in the table where status information will be written. The table length
ranges from 1 ... 75 for controllers using the S901 RIO protocol and 1 ... 277 for
controllers using the S908 protocol. The table length that can actually be read by
the STAT block depends on the addressing capabilities of the controller—a 16 bit
CPU can access only up to the first 255 words in the STAT table, whereas a 24 bit
CPU can access all 277 words.
The 75 words in the S901 status table are divided into three sections—the first 11
words for controller status information, the next 32 words for I/O module health in-
formation, and the last 32 words for I/O communications information:
DECIMAL HEX
WORD WORD
1 Controller Status 01
2 Unused 02
3 Controller Status 03
4 S901 Status 04
5 Controller Stop State 05
6 Number of Segments in User Logic 06
7 Address of End-0f-Logic Pointer 07
8 RIO Redundancy and Timeout 08
9 ASCII Message Status 09
10 Run Load Debug Status 0A
11 Address of Status Word Pointer Table 0B
xxxxx 3xxxxxx
where the last five digits (xxxxx) of the pointer become the last five digits of the address. For
example, pointer 00984 becomes address 300984.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Bad Config
Coil Disabled
in RUN Mode
Logic chksm
Invalid Node
Invalid Traffic Cop
CPU Failed
Real Time Clock Error
Watchdog Timer Expired
No End-Of-Logic
State RAM Test Failed
Start of Node Did Not Start Segment
Segment Scheduler Invalid
Illegal Peripheral Intervention
Controller in DIM AWARENESS
Extended Memory Parity Error
Peripheral Port Stop
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
EOL Pointer
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Debug = 0 0
Run = 0 1
Load = 1 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Words 12 ... 43 display the health of the I/O modules in the odd and even
channels:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Slot 8
Slot 7
Slot 6
Slot 5
Slot 4
Slot 3
Slot 2
Slot 1
Slot 8
Slot 7
Slot 6
Slot 5
Slot 4
Slot 3
Slot 2
Slot 1
Note These indicators are valid only when scan time > 30 ms.
RIO system communication status is given in words 44 ... 75. Two words are
used to describe each of up to 16 drops:
If the bit is set to 1, then the condition is TRUE.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Busy 1
Send Sequence
Cable B
Receive Sequence
Busy 0
Not Used
Current Message Not Supported
Byte Count Underrun
Sequence Number Invalid
Function Scheduled:
000 = Normal I/O
001 = Restart (Comm Reset)
010 = Restart (Application Reset)
011 is unassigned
100 = Inhibit
101 unassigned
110 unassigned
111 unassigned
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Retry Counter
Command Not Supported by Drop
Invalid Sequence Number
Drop Just Powered Up
Not Used
Addressed Drop Did Not Respond
CRC Error From Addressed Drop
Character Overrun From the Addressed Drop
Not Used
The 277 words in the S908 status table are organized in three sections—the first
11 words for controller status, the next 160 words for I/O module health, and the
last 106 words for I/O communication health:
DECIMAL HEX
WORD WORD
1 Controller Status 01
12 Drop 1, Rack 1
0C
13 Drop 1, Rack 2
14 Drop 1, Rack 3 0D
15 Drop 1, Rack 4 0E
16 Drop 1, Rack 5 0F
17 Drop 2, Rack 1 10
18 Drop 2, Rack 2 11
12
” ” ” ” ” ” ” ” ”
170 Drop 32, Rack 4 AA
171 Drop 32, Rack 5
AB
AC
172 S908 Startup Error Code AD...AF
173...175 Cable A Errors B0...B2
176...178 Cable B Errors B3...B5
179...181 Global Communication Errors B6...B8
182...184 Drop 1 Errors /
Health Status and Retry Counters
(in the Compact 984 Controllers)
185...187 Drop 2 Errors B9...BB
188...190 Drop 3 Errors BC...BE
When accessing the status table from your programming panel, words 1 ... 11 are
found in sequential memory locations 65 ... 6F (hex). The I/O health status table
is kept in 160 sequential memory locations; the communication status table is kept
in 106 sequential memory locations. The actual memory locations that hold these
two tables will vary with different 984 mainframe models.
Use pointers to locate the first word in the I/O module health status table and the
communication status table. The pointers are always found at the same locations
in absolute memory:
If the most significant hex digit of the pointer is > 8, add E8000 to the pointer as
follows:
Pointer Address
8xxx f0xxx
9xxx f1xxx
axxx f2xxx xxx = last three digits of the
bxxx f3xxx pointer become the last three
cxxx f4xxx digits of the address
dxxx f5xxx
exxx f6xxx For example, pointer B984 becomes
fxxx f7xxx address F3984
To find the address of an I/O health status word, subtract 0C (hex) from the status
word number, then add the result to the I/O health pointer.
To find the address of a communication status word, subtract 0AC (hex) from the
status word number, then add the result to the I/O communication pointer.
If you are accessing the status table with a P965 DAP, words 1 ... 11 can be found
in absolute memory locations 300101 ... 300111 (decimal). The I/O health status
table is kept in 160 sequential memory locations; the communication status table
is kept in 106 sequential memory locations. The actual memory locations that
hold these two tables will vary with different 984 controllers.
Use pointers to locate the first word in the I/O module health status table and the
communication status table. The pointers are always found at the same locations
in absolute memory:
Pointer Address
xxxxx 3xxxxxx
where the last five digits (xxxxx) of the pointer become the last five digits of the address. For
example, pointer 00984 becomes address 300984.
To find the address of an I/O health status word, subtract 12 from the status word
number, then add the result to the I/O health status pointer.
To find the address of a communication status word, subtract 172 from the status
word number, then add the result to the I/O communication pointer.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Word 2 Displays the Hot Standby status for 984 controllers that
use S911/R911 Modules:
If the bit is set to 1, then the condition is TRUE.
1 2 3 4 5 6 7 8 9 10 11
11 12 13 14 15 16
Not Used
S911/R911 Present and Healthy
0 = Controller Toggle Set to A
1 = Controller Toggle Set to B
0 = Controllers have Matching Logic
1 = Controllers do not have Matching Logic
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Extended Memory Parity Error (for chassis mount controllers) or Traffic Cop/S908
Error (for other controllers)
If the bit = 1 in a 984B Controller, an error has been detected in extended
memory; the controller will run, but the error output will be ON for XMRD/XMWT
functions. If the bit = 1 for any controller other than a chassis mount, then either a
traffic cop error has been detected or the S908 is missing from a multi-drop
configuration.
Peripheral Port Stop
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Word 9 Uses its four least significant bits to display ASCII message
status:
If the bit is set to 1, then the condition is TRUE.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Mismatch Between Number of Messages and Pointers
Invalid Message Pointer
Invalid Message
Message cksm Error
Debug = 0 0
Run = 0 1
Load = 1 0
12 Drop 1 Rack 1
13 Drop 1 Rack 2
14 Drop 1 Rack 3
15 Drop 1 Rack 4
16 Drop 1 Rack 5
17 Drop 2 Rack 1
18 Drop 2 Rack 2
” ” ” ” ” ” ”
170 Drop 32 Rack 4
171 Drop 32 Rack 5
Five words are reserved for each of up to 32 drops, one word for each of up to
five possible racks (I/O housings) in each drop. Each rack may contain up to 11 I/
O modules; bits 1 ... 11 in each word represent the health of the associated I/O
module in each rack.
If the bit is set to 1, then the condition is TRUE.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Valid communications must exist between the module and the RIO interface at
remote drops
Valid communications must exist between the RIO interface at each remote
drop and the I/O processor in the controller
Word # --12
= Quotient + Remainder
5
where
Drop # = Quotient + 1
Rack # = Remainder + 1
The status of the 32 Element Pushbutton Panels and PanelMate units on an RIO
network can also be monitored with an I/O health status word. The Pushbutton
Panels occupy slot 4 in an I/O rack and can be monitored at bit 4 of the appropri-
ate status word. A PanelMate on RIO occupies slot 1 in rack 1 of the drop and
can be monitored at bit 1 of the first status word for the drop.
Status words 172 ... 277 contain the I/O system communication status. Words
172 ... 181 are global status words. Among the remaining 96 words, three words
are dedicated to each of up to 32 drops, depending on the type of 984 controller
you are using.
Word 172 S908 Startup Error Code. This word is always 0 when the
system is running. If an error occurs, the controller does
not start—it generates a stop state code of 10 (word 5):
Traffic Cop Validation Soft Error Codes
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Cable B Status
Cable A Status
Comm Health
For controllers that support remote I/O, words 182 ... 277 are used to describe re-
mote I/O drop status; three status words are used for each drop:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
For any 984 controller where drop 1 is reserved for local I/O, status words
182 ... 184 are used as follows:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
word # -- 182
= quotient and remainder
3
quotient + 1 = drop #
remainder + 1 = word
With the SKP instruction, you can bypass networks in your ladder logic program
and not solve the skipped logic. SKP functions allow you to reduce scan time
and, in effect, establish subroutines in the logic. The SKP instruction is a
one-node function block:
ON = acti- SKP
vate number of blocks
skip function to be skipped
The node indicates that this is a SKP function and specifies the number of net-
works to be skipped—this number must include the network that contains the SKP
instruction. The number can be
When the node is powered, SKP is performed on every scan. This causes the
rest of the network containing the SKP block to be skipped (this counts as one
network skipped); the CPU continues to skip networks until the total number of
networks skipped equals the value specified in the function block.
A SKP operation cannot pass the boundary of a segment. No matter how many
extra networks you schedule to be skipped, the instruction will stop if it reaches
the end of a segment.
Network 42
Rung 1
10003 00193
SKP
Rung 7
00002
10001
Network 43
10002 00116
When 10001 is closed, the remainder of network 42 and all of network 43 are
skipped. The power flow display for these two networks becomes invalid, and
your system displays an information message to that effect.
Coil 00193 is still controlled by contact 10003 because the solution of coil 00193
occurs before the SKP instruction.Coil 00116 will remain in whatever state it was
in when network 43 was skipped.
The 984B chassis mount Controller provides an optional capability for supporting
extended memory. Extended memory is used for massive data storage in a group
of files made up of storage registers. These extended memory storage registers
use 6x reference numbers on pages 1 ... 3 in system memory.
Extended memory provides up to ten files, and each file can contain as many as
10,000 registers ranging from 60000 ... 69999:
Three optional sizes of extended memory are available: 32K words, 64K words,
and 96K words. Each 6x register uses one word of extended memory. The total
memory available may be up to 128K words, with either 32K words or 64K words
allocated for user logic memory so that:
A 984B with 64K words of memory may use all 64K for user logic or 32K of
user logic and 32K words of extended memory
A 984B with 96K words of memory may use 32K for user logic and 64K for ex-
tended memory or 64K for user logic and 32K for extended memory
A 984 with 128K words of memory may use 32K for user logic and 96K for ex-
tended memory or 64K for user logic and 64K for extended memory
16 bits page F
page 3
Executive PROM
Extended Memory
page 2 IOP Address Space
Extended Memory
page 1
Optional User Logic or
Extended Memory State RAM
page 0
User Logic
Executive Scratchpad
ASCII Message Table
Loadable Instructions 16 bits
Traffic Cop Table
Segment Scheduler
Status Tables
Other Diagnostics
Configuration Table
24 bits
The 984B can be configured for either 32K or 64K words of user logic using the
configurator editor in your panel software. If you use 64K, pages 0 and 1 (which
contain 24 bit words) are used; if you choose 32K, only page 0 is used. If page 1
is not used for optional user logic in a 984B, it may be used for Extended Memory,
along with pages 2 and 3.
Two additional three-node instructions are included in the 984B executive firm-
ware to be used for manipulating extended memory files—XMWT for writing data
into extended memory files and XMRD for reading data from extended memory to
state RAM. Both these instructions use a table of six 4x holding registers called
the extended memory control table.
The 16 bit values in the first word in the control table provide you with diagnostic
information regarding extended memory:
0 = offset parameter OK
1 = offset parameter too large
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Not used
0 = State RAM OK
1 = Nonexistent state RAM
The XMWT instruction is used to write data from a block of input registers or hold-
ing registers in state RAM to a block of 6x registers in an extended memory file. It
is a three-node function block:
The top node may be a 3x input register or 4x holding register that specifies the
first register in the block of registers to be written to extended memory.
The middle node is the first of six consecutive 4x registers to be used as the ex-
tended memory control block (as described in Section 16.3). If you are in
multi-scan mode, these six registers should be unique to this function block.
The bottom node identifies the function as an extended memory write and always
contains the constant value 1, which cannot be changed.
The top node is the first of six consecutive 4x registers to be used as the ex-
tended memory control block (as described in Section 16.3). If you are in
multi-scan mode, these six registers should be unique to this function block.
The middle node is the first 4x holding register in a table of registers that receive
the transferred data from the 6x extended memory storage registers.
The bottom node identifies the function as an extended memory read and always
contains the constant value 1, which cannot be changed.
Network Statistics
All 984 controllers that support a Modbus Plus communications capability have a
special master (MSTR) instruction with which nodes on the network can initiate
message transactions. The MSTR function allows you to initiate one of eight pos-
sible operations over the Modbus Plus network:
Write data 1
Read data 2
Get local statistics 3
Clear local statistics 4
Write global database 5
Read global database 6
Get remote statistics 7
Clear remote statistics 8
4x + 2 Displays length
4x + 4 The Routing 1 register, uses the bit value of the low byte to
designate the address of the destination device; if you are using
a controller with just one Mobbus Plus port, the value of the
high byte should be set to 0:
0 0 0 0 0 0 0 0 0 x x x x x x x
If you are using a controller with two Modbus Plus ports—e.g., using
two S985 cards in a chassis mount controller—the value of the high
byte for one port must be set to 0 and the high byte for the other port
must be set to 1, leaving an offset of 256 between the destination
node address and the register value:
0 0 0 0 0 0 0 1 0 x x x x x x x
The middle node, which must also be a 4x register, designates the first register in
the data area. For operations that provide the communication processor with da-
ta—such as a Write operation—the data area is the source of the data. For oper-
ations that acquire data from the communication processor—such as a Read op-
eration—the data area is the destination of the data.
The bottom node indicates that this is an MSTR function and specifies the maxi-
mum number of registers in the data area; area size must be a constant value
ranging from 1 ... 100.
If an error occurs during any one of the eight MSTR operations, a hexadecimal
error code will be displayed in register 4x + 1 in the control block. The form of the
code is Mmss, where
ss represents a subcode
** The m subfield in error code 6mss is an index into the routing information indicating
where an error has been detected—a value of 0 indicates the local node, a 2 the second
device on the route, etc.
01 No response received
02 Program access denied
03 Node offline and unable to communicate
04 Exception response received
05 Router node data paths busy
06 Slave device down
07 Bad destination address
08 Invalid node type in routing path
10 Slave has rejected the command
20 Initiated transaction forgotten by slave device
40 Unexpected master output path received
80 Unexpected response received
An MSTR Write function transfers data from a master source device to a specified
slave destination device on the network. An MSTR Read function transfers data
from a specified slave source device to a master destination device on the net-
work. Read and Write use one data master transaction path and may be com-
pleted over multiple scans.
The contents of the nine registers in the top node of the MSTR block contain the
following information when you implement a Read or Write function:
If you attempt to program the MSTR function to Read or Write its own station ad-
dress, an error will be generated in the second register of the MSTR control block.
It is possible to attempt a Read/Write operation to a nonexistent register in the
slave device. The slave will detect this condition and report it—this may take sev-
eral scans.
The Get local statistics function obtains operational information related to the local
node—where the MSTR function has been programmed. This operation takes
one scan to complete and does not require a data master transaction path.
The contents of the first four registers in the top node of the MSTR block are used
when you implement a Get local statistics function:
4x Operation type 3
4x + 4 Routing 1 If this is the second of two local nodes, set the high
byte to a value of 1
The Clear local statistics function clears operational statistics relative to the local
node—where the MSTR function has been programmed. This operation takes
one scan to complete and does not require a data master transaction path.
The contents of the first two registers in the top node of the MSTR block are used
when you implement a Clear local statistics function:
4x Operation type 4
4x + 4 Routing 1 If this is the second of two local nodes, set the high
byte to a value of 1
The Write global data function transfers data to the comm processor in the current
node so that it can be sent over the network when the node gets the token. All
nodes on the local network link can receive this data. This operation takes one
scan to complete and does not require a data master transaction path.
The contents of the first three registers in the top node of the MSTR block are
used when you implement a Write global data function:
4x Operation type 5
4x + 4 Routing 1 If this is the second of two local nodes, set the high
byte to a value of 1
The Read global data function gets data from the comm processor in any node on
the local network link that is providing global data. This operation may require
multiple scans to complete if no global data are currently available from the re-
quested node; if global data are currently available, the operation completes in a
single scan. No master transaction path is required.
The contents of the first five registers in the top node of the MSTR block are used
when you implement a Read global data function:
4x Operation type 6
4x + 3 Available words Contains the number of words available from the re-
quested node; the value is automatically updated by
internal software
The Get remote statistics function obtains operational information relative to re-
mote nodes on the network. This operation may require multiple scans to com-
plete and does not require a master data transaction path.
The contents of the nine registers in the top node of the MSTR block contain the
following information when you implement a Get remote statistics function:
4x Operation type 7
The remote comm processor always returns its complete statistics table when a
request is made, even if the request is for less than the full table. The MSTR
function then copies only the amount of words you have requested to the desig-
nated 4x registers.
The Clear remote statistics function clears operational statistics related to a re-
mote network node from the data area in the local node. This operation may re-
quire multiple scans to complete and uses a single data master transaction path.
The contents of seven registers in the top node of the MSTR block contain the fol-
lowing information when you implement a Clear remote statistics function:
4x Operation type 8
4x + 2 and
4x + 3 Not used
The following table presents statistics available on the Modbus Plus network. You
may acquire this information by using the appropriate MSTR logic function or by
using Modbus function code 8.
Note When you issue the Clear local or Clear remote statistics func-
tions, only words 13 ... 22 are cleared.
05 Token pass counter; increments each time this station gets the token
984 slot mount and micro controllers that do not support Modbus
Plus come with a standard checksum (CKSM) instruction. The
CKSM instruction has the same opcode as the MSTR function and
is not provided in executive firmware with the 984 controllers that
support Modbus Plus.
CKSM allows you to program four types checksum calculations in ladder logic:
Straight check
All checksum algorithms handle both 8 bit and 16 bit data; if 8 bits are used, the
high order byte in the register must be 0. In a straight checksum calculation, all
bytes (high and low) are summed and the least significant eight bits are returned.
A binary checksum calculation is a 16 bit sum of all registers. An LRC is a
straight checksum that is then two‘s complemented. A CRC-16 calculation is a 16
bit cyclical checksum performed on the least significant bytes of the source regis-
ters.
result and
cksm select 1 implied register Error
implied register count > length or
count
implied register count =0
CKSM
cksm select 2 length of
source table
The top node contains the first 4x register in the source table. The checksum cal-
culation is performed on the registers in this table.
The middle node contains two 4x registers—4x stores the result of the checksum
calculation, and 4x + 1 specifies the number of registers selected from the source
table used as input to the calculation.
The three inputs to the block are used to indicate the type of checksum calculation
to be performed:
CKSM Input
Calculation Top Mid Bottom
JSR
LAB
RET
A Subroutine Example
Several 984 instruction sets provide three standard function blocks in the EPROM
firmware that allow you to set up ladder logic-based subroutines. The JSR func-
tion jumps from the regular (scheduled) logic to a subroutine; the LAB function la-
bels the starting point of the subroutine; and the RET function returns you from the
subroutine network to the regular (scheduled) user logic program.
Ladder logic subroutines allow you to save memory space in the user logic table
in cases where you need to implement the same logic functions multiple times in a
single scan. You need only create the logic once, store it in the logic segment re-
served for subroutines, and call it from user logic with the JSR block as often as
you need it within a scan.
Subroutines can also be helpful in reducing total scan time. Portions of logic that
require only infrequent solution in logic scans can be placed in the subroutine seg-
ment and called from user logic only on those scans where it is needed.
All ladder logic subroutines must be built in the last segment of user logic. This
segment must be removed from the segment scheduler—it is not part of the regu-
lar order-of-solve table.
Note This means that you must specify at least one more segment
than is required for regular user logic in the configuration table.
Controllers that support subroutines provide as many as 255 address locations for
subroutine ladder logic. Each subroutine must start at the beginning of a network
in the last logic segment. There is no set limit on the number of networks in the
segment.
The JSR instruction causes the logic scan to jump to a specified subroutine in the
last (unscheduled) segment of user logic. JSR is a two-node function block:
JSR ON = error
????
The top node contains a source that indicates the subroutine to which the logic
scan is to jump. It may be specified as:
The bottom node indicates that this is a JSR function and contains a string of four
question marks—you must insert the constant value 1 in this node.
Note You can use a JSR block anywhere in user logic, even within a
subroutine. The process of calling one subroutine from another sub-
routine is called nesting. The system allows you to nest up to 100
subroutines—however, we recommend that you use no more than
three nesting levels.
The LAB instruction is used to label the starting point of a subroutine in the last
(unscheduled) segment of user logic. This instruction must be programmed in
row 1, column 1 of a network in the last (unscheduled) segment of user logic.
LAB is a one-node function block:
ON = specified LAB
ON = error
constant
subroutine value
activated
The node indicates that this is a LAB function and contains a unique constant val-
ue identifying the subroutine you are about to run; it may range from 1 ... 255. If
more than one subroutine network has the same LAB value, the network with the
lowest number is used as the starting point for the subroutine.
Note The LAB block also functions as a default return from the sub-
routine in the preceding networks. If you have been executing a series
of subroutine networks and you encounter a network that begins with a
LAB block, the system assumes that the desired subroutine is finished,
and it returns the logic scan to the node immediately following the
most recently executed JSR block.
The RET instruction may be used to conditionally return the logic scan to the node
immediately following the most recently executed JSR block. This node can be
implemented only from within a subroutine network—in the last (unscheduled)
segment of user logic. RET is a one-node function block:
RET
ON = return to ON = error
calling logic 00001
The bottom node indicates that this is a RET function and contains the constant
value 00001.
When the ENABLE input is energized, the RET block returns the logic scan to the
node immediately following the most recently executed JSR block.
If a subroutine does not contain a RET block, either a LAB block or the end-of-log-
ic (whichever comes first) serves as the default return from the subroutine.
The example below shows a series of three user logic networks, the last of which
is used for an up-counting subroutine. Segment 3 has been removed from the or-
der-of-solve table in the segment scheduler:
Segment 001
Network 00001
Subroutine Segment
Segment 003
Network 00001
00010
SUB 00001
40999 JSR
00001
Segment 002
Network 00001
The subroutine will internally loop on itself ten times, counted by the ADD block.
The first nine loops end with the JSR block in the subroutine (network 1 of seg-
ment 3) sending the scan back to the LAB block. Upon completion of the tenth
loop, the RET block sends the logic scan back to the scheduled logic at the JSR
node in network 2 of segment 1.
You should always keep your subroutine logic as straightforward as possible for
debugging purposes. The power flow displayed on your programming panel is in-
valid in the subroutine networks and is therefore more difficult to troubleshoot.
Note We recommend that you debug your ladder logic programs be-
fore making them subroutines.
For transitionals to work properly within a subroutine, the subroutine must be ex-
ecuted at the appropriate time to see the state change. To use a negative transi-
tional within the subroutine, the subroutine must be called once when the contact
is ON, then called again on the scan when the contact is turned OFF. To use a
positive transitional within a subroutine, the subroutine must be called while the
contact is OFF, then called again on the scan when the contact is turned ON.
Counters also work on a state change basis—when the top input transitions from
OFF to ON. Timers do not function properly from within a subroutine unless that
subroutine is executed on every scan.
initiated
destination Error/Move
Hold pointer pointer not
possible
BLKT/TBLK
Reset pointer block length
The middle node is the destination pointer; it is a movable 4x pointer that indicates
the first register in the destination block (or table). The destination block itself be-
gins with register 4x + 1 and runs to the end of the block length specified in the
bottom node.
The bottom node indicates that this is a BLKT or TBLK function and specifies a
number of 4x registers in a destination block within the table. The range is from 1
... 100; the overall size of the destination table is a function of the number of 4x
registers currently available.
EMTH
Bottom In function code Bottom Out
(1 ... 38)
The top node requires two consecutive registers, usually 4x holding registers but,
in the integer math cases, either 4x or 3x registers.
The middle node requires either two, four, or six consecutive registers, depending
on the function you are implementing. Use 4x holding registers.
The bottom node identifies the block as the EMTH function and provides a func-
tional selection mechanism for the block. Enter a constant value in the range
1 ... 38 to indicate the extended math function you want to employ.
Inputs to and outputs from the EMTH block may be ACTIVE or INACTIVE, de-
pending on the function called in the bottom node.
Integer Math
Square Root 05 Top only Top, Middle
Process Square Root 06 Top only Top, Middle
Logarithm 07 Top only Top, Middle
Antilogarithm 08 Top only Top, Middle
EMTH
1
The top node comprises two consecutive 4x registers; each register holds a value
in the range 0000 ... 9999 for a combined value range of up to 99,999,999.
4x and 4x + 1 hold the second operand value, in the range 0 ... 99,999,999
The top node comprises two consecutive 4x registers; each register holds a value
in the range 0000 ... 9999 for a combined value range of up to 99,999,999.
4x and 4x + 1 hold the second operand value, in the range 0 ... 99,999,999
EMTH
3
The top node comprises two consecutive 4x registers; each register holds a value
in the range 0000 ... 9999 for a combined value range of up to 99,999,999.
4x and 4x + 1 hold the second operand value, in the range 0 ... 99,999,999
The top node comprises two consecutive 4x registers; each register holds a value
in the range 0000 ... 9999 for a combined value range of up to 99,999,999.
4x and 4x + 1 hold the second operand value, in the range 0 ... 99,999,999
(Since division by 0 is illegal, a 0 value causes an error—an error trapping rou-
tine sets the remaining middle-node registers to 0000 and turns the bottom out-
put ON.)
Square Root
EMTH
5
The top node comprises either two consecutive 4x holding registers or one 3x in-
put register. If the source value is five to eight digits long in the range 10,000 ...
99,999,99, it is stored in the two consecutive 4x registers. If the source is less
than five digits long, in the range 0 ... 9,999, it is stored in register 4x + 1. If you
specify a 3x register in the top node, the square root calculation is done on only
register 3x; a second register is implied but not used.
The middle node comprises two consecutive 4x registers, where the result of the
standard square root operation is stored. Data are stored in a fixed-decimal for-
mat: 1234.5600. where register 4x stores the most significant data, to the left of
the first decimal point, and register 4x + 1 stores the four-digit value to the right of
the first decimal point. Numbers after the second decimal point are truncated; no
roundoff calculations are performed.
EMTH
6
The process square root function implements the standard square root function
and tailors it for closed loop analog control applications. It takes the result of the
standard square root operation, multiplies it by 63.9922—the square root of
4095—and stores that linearized result in the middle-node registers. In order to
generate values that have meaning, the value entered in the top-node 4x or 3x
register must not exceed 4095. Process square root linearizes signals from differ-
ential pressure flow transmitters so that they may be used as inputs in PID2 oper-
ations (see Section 20.8).
√2000 = 0044.72
EMTH
7
The middle node contains a single 4x holding register where the result is stored.
The result is expressed in a fixed decimal format 1.234, and is truncated after the
third decimal position. The largest number that can be calculated is 7.999, which
is stored in the register as value 7999.
EMTH
8
The top node is a single 4x holding register or 3x input register. The source value
stored here is in the fixed decimal format 1.234 and must be in the range
0 ... 7.999; the largest antilog value that can be calculated is 99770006.
The result is stored in two consecutive 4x holding registers in the middle node, in
the fixed decimal format 12345678, where the most significant bits are in 4x and
the least significant bits are in 4x + 1.
To make use of the FP capability, the standard four-digit integer values used in
standard 984 instructions must be converted to the IEEE floating point format. All
calculations are then performed in FP format, and the results must be converted
back to integer format.
EMTH floating point functions require values in 32-bit IEEE floating point format.
Each value has two registers assigned to it—the eight most significant bits repre-
senting the exponent and the other 23 bits (plus one assumed bit) representing
the mantissa and the sign of the value. It is virtually impossible to recognize an
FP representation on the programming panel. Therefore, all numbers should be
converted back to integer format before you attempt to read them.
Standard 984 integer math does not handle negative numbers explicitly. The only
way to identify negative values is by noting that the SUB function block has turned
the bottom output ON.
If such a negative number is being converted to floating point, perform the Inte-
ger-to-FP conversion (EMTH function #9), then use the Change Sign function
(EMTH function #24) to make it negative prior to any other FP calculations.
result
EMTH
9
The top node comprises two consecutive 4x registers that contain a double preci-
sion integer value to be converted to 32-bit FP format.
The middle node contains four consecutive 4x registers—4x and 4x + 1 are not
used; 4x + 2 and 4x + 3 are used to store the result of the FP conversion.
FP value
and result
EMTH
10
The top node comprises two consecutive 4x registers that contain a double preci-
sion integer value to be added to a FP number.
Integer - FP
FP value
and difference
EMTH
11
The top node comprises two consecutive 4x registers that contain a double preci-
sion integer value from which an FP number is to be subtracted.
FP value
and product
EMTH
12
The top node comprises two consecutive 4x registers that contain a double preci-
sion integer value to be multiplied by an FP number.
Integer : FP
FP value
and quotient
EMTH
13
The top node comprises two consecutive 4x registers that contain a double preci-
sion integer value to be divided by an FP number.
EMTH
14
The top node comprises two consecutive 4x registers that contain an FP number.
FP Integer
integer value
and FP quotient
EMTH
15
The top node comprises two consecutive 4x registers that contain an FP number.
The top node comprises two consecutive 4x registers that contain a double preci-
sion integer value to be compared with an FP number.
The result of the comparison is displayed by the state of the middle and bottom
outputs.
integer value
The top node comprises two consecutive 4x registers that contain an FP value in
32-bit FP format.
The middle node contains four consecutive 4x registers—4x and 4x + 1 are not
used; 4x + 2 and 4x + 3 contain the integer result of the conversion. This value
should be the largest integer value possible that is < the FP value—for example,
the FP value 3.5 is converted to the integer value 3, while the FP value --3.5 is
converted to the integer value --4.
Note If the resultant integer is too large for 984 double precision inte-
ger format (> 99,999,999), the conversion still occurs but an error is
logged in EMTH function #38.
FP value 2
and sum
EMTH
18
The top node comprises two consecutive 4x registers that contain one FP value.
FP Subtraction
FP value 2
and difference
EMTH
19
The top node comprises two consecutive 4x registers that contain one FP value.
FP value 2
and product
EMTH
20
The top node comprises two consecutive 4x registers that contain one FP value,
which will be multiplied by the middle-node value.
FP Division
FP value 2
and quotient
EMTH
21
The top node comprises two consecutive 4x registers that contain one FP value,
which will be divided by the middle-node value.
The top node comprises two consecutive 4x registers that contain one FP value.
FP Square Root
FP result
EMTH
23
The top node comprises two consecutive 4x registers that contain an FP value.
FP Change Sign
-- (FP value)
EMTH
24
The top node comprises two consecutive 4x registers that contain an FP value.
Load FP Value of π
FP value of π
EMTH
25
The top node contains two consecutive 4x registers that are not used.
sine of
FP value
EMTH
26
The top node comprises two consecutive 4x registers that contain an FP value in-
dicating the value of an angle in radians. The magnitude of this value must be
< 65536.0; if not:
cosine of
FP value
EMTH
27
The top node comprises two consecutive 4x registers that contain an FP value in-
dicating the value of an angle in radians. The magnitude of this value must be
< 65536.0; if not:
tangent of
FP value
EMTH
28
arcsine of
FP value
EMTH
29
The top node comprises two consecutive 4x registers that contain an FP value in-
dicating the sine of an angle between -- π/2 ... π/2 radians. This value—the sine of
an angle—must be in the range of --1.0 ... +1.0; if not:
arc cosine of
FP value
EMTH
30
The top node comprises two consecutive 4x registers that contain an FP value in-
dicating the cosine of an angle between 0 ... π radians. This value must be in the
range of --1.0 ... +1.0; if not:
arc tangent of
FP value
EMTH
31
The top node comprises two consecutive 4x registers that contain an FP value in-
dicating the tangent of an angle between -- π/2 ... π/2 radians. Any valid FP value
is allowed.
FP value 2
EMTH
32
The top node comprises two consecutive 4x registers that contain an FP repre-
sentation of the value of an angle in radians.
FP value 2
EMTH
33
The top node comprises two consecutive 4x registers that contain an FP repre-
sentation of the value of an angle in degrees.
integer value
and FP result
EMTH
34
The top node comprises two consecutive 4x registers that contain a floating point
value.
FP Exponential Function
FP result
EMTH
35
The top node comprises two consecutive 4x registers that contain an FP value in
the range --87.34 ... +88.72. If the value is out of range, the result will either be 0
or the maximum value, but no error will be flagged.
FP Natural Logarithm
natural log of
FP value
EMTH
36
The top node comprises two consecutive 4x registers that contain an FP value >
0. If the value < 0, an invalid result will be returned in the middle node and an er-
ror will be logged in EMTH function #38.
common log
of FP value
EMTH
37
The top node comprises two consecutive 4x registers that contain an FP val-
ue > 0. If the value < 0, an invalid result will be returned in the middle node and
an error will be logged in EMTH function #38.
The top node requires the assignment of two consecutive 4x registers, but they
are not used in the operation.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FP Overflow
FP Underflow
An analog closed loop control system is one in which the deviation from an ideal
process condition is measured, analyzed, and adjusted in an attempt to obtain
(and maintain) zero error in the process condition. Provided with the Enhanced
Instruction Set is a proportional-integral-derivative function block called PID2,
which allows you to establish closed loop (or negative feedback) control in ladder
logic.
The desired (zero error) control point, which you will define in the PID2 block, is
called the set point (SP). The conditional measurement taken against SP is called
the process variable (PV). The difference between the SP and the PV is the devi-
ation or error (E). E is fed into a control calculation that produces a manipulated
variable (Mv) used to adjust the process so that PV = SP (and, therefore, E = 0).
CONTROL
END DEVICE
PV
PROCESS
PROCESS
TRANSMITTER
Mv --
PV (INPUT)
(OUTPUT) CONTROL E +
CALCULATION SP
With proportional-only control (P), you can calculate the manipulated variable by
multiplying error by a proportional constant, K1, then adding a bias:
Mv = K1E + bias
To eliminate this offset error without forcing you to manually change the bias, an
integral function can be added to the control equation:
t
Mv = K1(E + K2 ∫ E∆t)
0
You may want to add derivative functionality to the control equation to minimize
the effects of frequent load changes or to override the integral function in order to
get to the SP condition more quickly:
t
Mv = K1(E + K2 ∫ E∆t + K3
∆PV
∆t
)
0
Modicon’s algorithm for PID2 tunes the closed loop operation in a manner similar
to traditional pneumatic and analog electronic loop controllers. It uses a rate gain
limiting (RGL) filter on the PV as it is used for the derivative term only, thereby fil-
tering out higher-frequency PV noise sources (random and process generated).
DERIVATIVE
xn CONTRIBUTION
xn--1 + xn
+
4x + 6 8 4x + 6 8
-- ∆Pv ∆x 60(RGL -- 1)K3
PV + RGL
RGL Ts
4x13 Zn
-- E E --
SP + +
PROPORTIONAL
(4x1 -- 4x2) CONTRIBUTION
x 4095 100
(4x11 -- 4x12) PB
GE
+
Output
Bias + Clamp Mn
4x8 +
Integral 4x17 4x2
Feedback INTEGRAL 4x18
In
Mn--1 F -- CONTRIBUTION
loc
4x16 +
M Qn
Preload Integral
Tloc
Mode ClampWn
4x20 ∆I
+ K2 Ts
--
600000
In--1 + In
In--1 + In
4x + 3, + 4, + 5
K1 = 100
PB
The top source node indicates the first of 21 consecutive holding registers ranging
from 4x0 ... 4x20. The contents of registers 4x5, 4x6, 4x7, and 4x8 in the top
node determine whether the operation will be P, PI, or PID:
P
PI
PID
The middle node contains nine additional holding registers, 4x ... 4x + 8, which are
used by the PID2 block for calculations. You do not need to load anything into
these registers.
The bottom node indicates that this is a PID2 function and contains a number
ranging from 1 ... 255, indicating how often the function should be performed. The
number represents a time value in tenths of a second—for example, the number
17 indicates that the PID function should be performed every 1.7 s.
4x0 Scaled PV: Loaded by the block each time it is scanned; a linear scaling
is done on register 4x13 using the high and low ranges in 4x11 and
4x12:
4x13
Scaled PV = x (4x11 -- 4x12) + 4x12
4095
Truncate the resulting number at the decimal point—discard all digits to
the right of the decimal point, and do not round off
4x1 SP: You must specify the set point in engineering units; the value must
be > 4x11 and > 4x12
4x2 Mv: Loaded by the block every time the loop is solved; it is clamped to
a range of 0 ... 4095, making the output compatible with an analog out-
put module; the manipulated variable register may be used for further
CPU calculations such as cascaded loops
4x3 High Alarm Limit: Load a value in this register to specify a high alarm
for PV (at or above SP); enter the value in engineering units within the
range specified by 4x11 and 4x12
4x4 Low Alarm Limit: Load a value in this register to specify a low alarm
for PV (at or below SP); enter the value in engineering units within the
range specified by 4x11 and 4x12
4x5 Proportional Band: Load this register with the desired proportional
constant in the range 5 ... 500; the smaller the number, the larger the
proportional contribution; a valid number is required in this register for
PID2 to operate
4x6 Reset Time Constant: Load this register to add integral action to the
calculation; enter a value between 0000 ... 9999 to represent a range of
00.00 ... 99.99 repeats/min; the larger the number, the larger the integral
contribution; a value < 9999 or > 0000 stops the PID2 calculation
4x7 Rate Time Constant: Load this register to add derivative action to the
calculation; enter a value between 0000 ... 9999 to represent a range of
00.00 ... 99.99 repeats/min; the larger the number, the larger the deriva-
tive contribution; a value < 9999 or > 0000 stops the PID2 calculation
4x8 Bias: Load this register to add a bias to the output; the value must be
between 000 .... 4095, and added directly to Mv
Top Node
4x9 High Integral Windup Limit: Load this register with the upper limit of
the output value (between 0 ... 4095) where the anti-reset windup takes
effect; the updating of the integral sum is stopped if it goes above this
value—this is normally 4095
4x10 Low Integral Windup Limit: Load this register with the lower limit of
the output value (between 0 ... 4095) where the anti-reset windup takes
effect—this is normally 0
4x11 High Engineering Range: Load this register with the highest value for
which the measurement device is spanned—e.g., if a resistance tem-
perature device ranges from 0 ... 500 degrees C, the high engineering
range value is 500; the range must be given as a positive integer
between 0001 ... 9999, corresponding to a raw analog input value of
4095
4x12 Low Engineering Range: Load this register with the lowest value for
which the measurement device is spanned; the range must be given as
a positive integer between 0 ... 9998, and it must be less than the value
in register 4x11; it corresponds to a raw analog input value of 0
4x13 Raw Analog Measurement: The logic program loads this register with
PV; the measurement must be scaled and linear in the range 0 ... 4095
4x14 Pointer to Loop Counter Register: The value you load in this register
points to the register that counts the number of loops solved in each
scan; the entry is determined by discarding the most significant digit in
the register where the controller will count the loops solved/scan—e.g.,
if the controller does the count in register 41236, load 1236 into 4x14;
the same value must be loaded into the 4x14 register in every PID2
block in the logic program
4x16 Pointer To Reset Feedback Input: The value you load in this register
points to the holding register that contains the value of feedback (F);
drop the 4 from the feedback register and enter the remaining four digits
in register 4x16; integration calculations depend on the F value being
connected to Mv—i.e., as the PID2 output varies from 0 ... 4095, so
should F vary from 0 ... 4095
4x17 Output Clamp—High: The value entered in this register determines the
upper limit of Mv—this is normally 4095
Top Node
4x18 Output Clamp—Low: The value entered in this register determines the
lower limit of Mv—this is normally 0
4x19 Rate Gain Limit (RGL) Constant: The value entered in this register
determines the effective degree of derivative filtering; the range is from
2 ... 30; the smaller the value, the more filtering takes place
4x20 Pointer to Track Input: The value entered in this register points to the
holding register containing the track input (T) value; drop the 4 from the
tracking register and enter the remaining four digits in register 4x20;
the value in the T register is connected to the input of the integral lag
whenever the auto bit and track bit are both true
4x Loop Status Register: Twelve of the 16 bits in this register are used to
define loop status:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Integral see
Windup NOTE
Integral Wind-
up
Limit
Negative Values
in the equation
NOTE: Bit 16 is set after initial startup or installation of the loop. If you clear the bit,
the following actions take place in one scan:
• The loop status register is reset
• The current value in the real-time clock is stored in register 4x + 1
• Registers 4x + 3, 4x + 4, and 4x + 5 are set to zero
• The value (4x13 x 8) is stored in register 4x + 6
• Registers 4x + 7 and 4x + 8 are cleared
4x + 1 Error (E) Status Bits: This register displays PID2 error codes as de-
scribed in previous table
4x + 2 Loop Timer Register: This register stores the real-time clock reading
on the system clock each time the loop is solved: the difference be-
tween the current clock value and the value stored in the register is the
elapsed time; if elapsed time > solution interval (10 times the value given
in the bottom node of the PID2 block), then the loop should be solved in
this scan
4x + 6 Pv x 8 (Filtered): This register stores the result of the filtered analog in-
put (from register 4x14) multiplied by 8; this value is useful in derivative
control operations
NOTE: If lockout occurs often and the parameters are all valid, increase the maxi-
mum number of loops/scan. Lockout may also occur if the counting registers in use
are not cleared as required.
** Activated only if the track feature is ON—i.e., the middle input of the PID2 block is
receiving power while in AUTO mode.
Here is a simplified P&I diagram for an inlet separator in a gas processing plant.
There is a two-phase inlet stream—liquid and gas.
Vent
Blowdown
Inlet Vent
Plant
Inlet
FCV
Inlet Block
LT
1
LSH Gas
1
LC PV--1
1
LSL
1
LV
I/P FC
1
Condensate
The liquid is dumped from the tank to maintain a constant level. The control ob-
jective is to maintain a constant level in the separator. The phases must be sepa-
rated before processing; separation is the role of the inlet separator, PV--1. If the
level controller, LSH--1, fails to perform its job, the inlet separator could fill, caus-
ing liquids to get into the gas stream; this could severely damage devices such as
gas compressors.
The level is controlled by device LC--1, a 984 controller connected to an analog in-
put module; I/P--1 is connected to an analog output module. We can implement
the control loop with the following 984 ladder logic:
30001 40102
0 0
SUB SUB
40113 40500
40100
00101
40200
00102
PID2
00030
00103
The first SUB block is used to move the analog input from LT--1 to the PID2 ana-
log input register, 40113. The second SUB block is used to move the PID2 output
Mv to the traffic copped output I/P--1. Coil 00101 is used to change the loop from
AUTO to MANUAL mode, if desired. For AUTO mode, it should be ON.
Specify the set point in mm for input scaling (EU). The full input range will be
0 ... 4000 mm (for 0 ... 4095 raw analog). Specify the register content of the top
node in the PID2 block as follows:
40101 = 2000 Scaled SP (mm). Set this to 2000 mm (half full) initially.
40102 = 0000 Loop output (0 ... 4095). PID2 writes this; keep it set to 0 just to be safe
40103 = 3500 Alarm High Set Point (mm). If the level rises above 3500 mm, coil 00102
goes ON.
40104 = 1000 Alarm Low Set Point (mm). If the level drops below 1000 mm, coil 00103
goes ON.
40105 = 0100 PB (%). The actual value used here depends on the process dynamics.
40106 = 0500 Integral constant (5.00 repeats/min). This actual value used here depends
on the process dynamics.
40107 = 0000 Rate time constant (per minute). Setting this to 0 turns off the derivative
mode.
40108 = 0000 Bias (0 ... 4095). This is set to 0, since we have a integral term.
40109 = 4095 High windup limit (0 ... 4095). Normally set to the maximum.
40110 = 0000 Low windup limit (0 ... 4095). Normally set to the minimum.
40111 = 4000 High engineering range (mm). The scaled value of the process variable
when the raw input is at 4095.
40112 = 0000 Low engineering range (mm). The scaled value of the process variable
when the raw input is at 0.
40113 = Raw analog measure (0 ... 4095). A copy of the input from the analog input
module register (30001) copied by the first SUB block in the ladder logic.
40114 = 0000 Offset to loop counter register. Zero disables this feature. Normally, this is
not used.
40116 = 0102 Pointer to reset feed back. If you leave this as zero, the PID2 function auto-
matically supplies a pointer to the loop output register. If the actual output
(40500) could be changed from the value supplied by PID2, then this regis-
ter should be set to 500 (40500) to calculate the integral properly.
40117 = 4095 Output clamp high (0 ... 4095). Normally set to maximum.
40118 = 0000 Output clamp low (0 ... 4095). Normally set to minimum.
40120 = 0000 Pointer to track input. Used only if the PRELOAD feature is used. If the
PRELOAD is not used, this is normally 0.
The values in the registers in the 40200 destination block are all set by the PID2
block.
Two types of software loadable functions are available for 984 programmable con-
trollers—function blocks that support optional controller modules, such as the co-
processing and Hot Standby capabilities, and function blocks that support special
application or programming requirements, such as drum sequencing and the
event/alarm recording system (EARS).
* When the X in the above software part numbers is a T, the medium is a P190 tape;
when the X is a D, the software media are 5.25 in and 3.5 in diskettes.
** The MSTR function that is a loadable for the chassis mount controllers is functionally
identical to the MSTR block provided in firmware for the 984-385/485/685/785
Controllers.
* When the x in the above software part numbers is a T, the medium is a P190 tape;
when the x is a D, the software media are 5.25 in and 3.5 in diskettes.
** TBLK, BLKT, CKSM, and PID2 are functionally identical to those instructions of the same
name provided in firmware for the 984-385/485/685/785 Controllers.
This chapter describes all the loadable functions that support option modules ex-
cept MSTR, which is described in Chapter 17.
It also describes the sequence control loadables (DRUM and ICMP), the EARS
function block, and the custom loadable function block model (FNxx).
The MATH and DMTH functions—which do double precision math, square root,
log, and antilog functions similar to those in EMTH (see Chapter 20)—are also de-
scribed here. For descriptions of TBLK, BLKT, and PID2, refer to Chapter 20; for
a description of the CKSM function, refer to Chapter 18.
Through the HSBY instruction you can access two registers—a command register
and a status register—that allow you to monitor and control Hot Standby opera-
tions. The status register is the third register in the nontransfer area you specify.
The top node contains a 4x holding register used as the HSBY command register;
eight bits in this register may be configured and controlled via your panel soft-
ware:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
The middle node is a 4x register that is the first register in the nontransfer area in
state RAM. The first three registers in the nontransfer area are special registers:
4x and 4x + 1 are the reverse transfer registers for passing information from the
standby to the primary controller, and 4x + 2 is the HSBY status register. The total
size of the nontransfer area is specified in the bottom node.
The bottom node indicates that this is an HSBY function and defines the size of
the nontransfer area in state RAM. The nontransfer area must contain at least
four registers. In a 16 bit CPU, the size may range from 4 ... 255 registers; in
24 bit CPUs, the size may range from 4 ... 8000 registers.
The combined states of bits 15 and 16 tells you whether the controller you are
attached to is in primary, standby, or OFFLINE mode
The combined states of bits 13 and 14 tell you whether the other controller in
the Hot Standby system is in primary, standby, or OFFLINE mode
Bit 12 tells you whether both controllers are using identical application logic
programs
Bit 11 tells you whether the R911/S911 module in the controller you are at-
tached to has its toggle switch set to position A or position B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Not Used
The two networks below are for a primary controller that monitors two fault lamps
and a reverse transfer that sends status data from the standby controller to the
primary controller. The first network must be network 2 of segment 1; the second
network must not be in segment 1.
40102
00801
BLKM
00001
40100
00815 00816 STAT
00001
40100
00813 00814
00705
BLKM
00001
The first BLKM function transfers the HSBY status register (40102) to internal
coils (00801). The STAT block, which is enabled if the other controller is in stand-
by mode, sends one status register word from the standby controller to a reverse
transfer register (40100) in the primary controller.
Enable an
function Immediate DX function complete
immediate code
DX CALL
source table
Enable a
deferred function Deferred DX function complete
DX CALL code
Deferred DX
mode selected source table Deferred DX function active
CALL
length of Error in deferred DX function
source table
A CALL block runs a deferred DX when the middle input is enabled and an imme-
diate DX when no middle input is programmed.
The 4x register in the middle node is the first in a block of registers to be passed
to the Copro for processing; the number of registers in the block is defined in the
bottom node.
The S975 Modbus II Interface option modules use two loadable function blocks—
MBUS and PEER. MBUS is always used to initiate a single transaction with
another device on the Modbus II network; PEER may initiate identical message
transactions with as many as 16 devices on Modbus II at one time. In an MBUS
transaction, you are able to read or write discrete or register data; in a PEER
transaction, you may only write register data.
A transaction cannot be initiated unless the S975 has enough resources for the
entire transaction to be performed. Once a transaction has been initiated, it runs
until a reply is received, an error is detected, or a timeout occurs. A second trans-
action cannot be started in the same scan that the previous transaction completes
unless the middle input is ON; a second transaction cannot be initiated by the
same MBUS/PEER block until the first transaction has completed.
21.6.1 MBUS
Enable an
MBUS control block Transaction complete
transaction
Repeat transaction
data block Transaction in progress or
new
in same scan
transaction starting
MBUS
Reset number of
(clears system words reserved Error detected in transaction
statistics) for data block
The top node is the first of seven 4x registers in the MBUS control block:
The middle node is the first 4x register in a data block to be transmitted or re-
ceived in the MBUS transaction.
The number of words reserved for the data block is entered as a constant value in
the bottom node. This number does not imply a data transaction length, but it can
restrict the maximum allowable number of register or discrete references to be
read or written in the transaction. The maximum number of words that may be
used in the specified transaction is:
490 for reading discretes using 24 bit CPUs: 255 for reading discretes using
16 bit CPUs (up to 16 discretes/word)
487 for writing discretes using 24 bit CPUs; 255 for reading discretes using
16 bit CPUs (up to 16 discretes/word)
Enable a
PEER transaction control block Transaction complete
Repeat transaction
data block Transaction in progress or
new
in same scan
transaction starting
PEER
number of
words to be
read/written Error detected in transaction
The top node is the first of 19 4x registers in the PEER control block:
The bottom node contains a constant value defining the number of holding regis-
ters to be written, starting with the 4x register defined in the middle node; the
range is 1 ... 249.
Function code 255 in register 4x + 2 in the MBUS control block allows you to ob-
tain a copy of the Modbus II local statistics, which stores errors and system condi-
tions in a series of 46 consecutive locations. When using MBUS for a get statis-
tics operation, set the constant value in the bottom node to 46; any value less
than 46 will return an error (the bottom output will go ON), and any value greater
than 46 will reserve extra registers that cannot be used. For example:
4100
0
Clear system
MBUS Error—length specified in bottom
statistics 46 node
is less than 46
Register 40101 is the first register in the MBUS control block, making register
40103 the control register that defines the MBUS function code. By entering a
value of 255 in register 40103, you implement a get statistics function. Registers
41000 ... 41045 are then filled with the following system statistics:
first register
Middle input in subfunction Middle output
(optional) table (optional)
The top node may be either a 4x holding register or a constant value; it is used to
identify a subfunction ID number. Valid ID numbers range from 0 ... 9999, and as
many as 8192 different subfunctions may be designed within a block. When multi-
ple subfunctions are designed within an FNxx block, each subfunction within the
block must have a unique ID number, but those numbers do not have to be con-
secutive.
The middle node is the first 4x register in a table of registers to be used by the
subfunction. The table may be used to pass data to the subfunction and store re-
sults. The table format may be customized for your requirements, and each sub-
function developed within the function block may have its own format.
The bottom node defines the function number, which may range from
FN01 ... FN99, and uses a constant value to define the number of 4x registers in
the subfunction table—the table length range may be from 1 ... 255 in a 16 bit
CPU and from 1 ... 999 in a 24 bit CPU.
Modicon provides a drum sequencer software package, for use with 984 chassis
mount controllers, which can be used in sequential control applications where si-
multaneous control of multiple devices—e.g., motors, valves, solenoids—at differ-
ent steps in a process is required. The package consists of two loadable instruc-
tions—DRUM and ICMP—along with a DOS-based user interface. The DRUM
instruction uses software to emulate a Tenor drum in ladder logic. The ICMP in-
struction is an input compare function used with DRUM to verify the correct opera-
tion of each step in the drum sequence.
21.9.1 DRUM
You may pre-allocate registers used to store data for each step in the sequence,
thereby allowing you to add future sequencer steps without having to modify appli-
cation logic.
DRUM blocks incorporate an output mask that allows you to selectively mask bits
in the register data before writing it to coils. This is particularly useful when all
physical sequencer outputs are not contiguous on the output module. Masked
bits are not altered by the DRUM instruction, and may be used by logic unrelated
to the sequencer. DRUM is a three-node function block:
DRUM
Reset the step max # of Error (a validation
pointer to 0 steps check has failed)
The middle node contains the first 4x register in an implied register table of step
data information; the first six registers in the table hold constant and variable data
required to solve the block:
The remaining registers contain data for each step in the sequence.
The bottom node contains a constant value used to calculate the maximum num-
ber of registers allocated to the step data table; the number may range from
1 ... 255 in 16 bit CPUs and 1 .. 999 in 24 bit CPUs. The maximum number of
registers is the specified constant + 6. The specified constant must be > the value
placed in the steps used register in the middle node.
ICMP (input compare) provides logic for verifying the correct operation of each
step processed by a DRUM block. Errors detected by ICMP may be used to trig-
ger additional error-correction logic or to shut down the system. ICMP and DRUM
are synchronized through the use of a common step pointer register. As the
pointer increments, ICMP moves through its data table in lock step with DRUM.
As ICMP moves through each new step, it compares—bit for bit—the live input
data to the expected status of each point in its data table. ICMP is a three-node
function block:
Enables the input compare step pointer Copies top input state
operation
The top node contains one 4x register used to hold the current step number value.
The value is referenced by ICMP each time the instruction is solved; the value in
this register must be controlled externally by a DRUM function or by other user
logic. The same register must be used in the top node of all ICMP and DRUM
blocks that are to be solved as a single sequencer.
The middle node contains the first 4x register in an implied register table of step
data information; the first eight registers in the table hold constant and variable
data required to solve the block:
The remaining registers contain data for each step in the sequence.
The bottom node contains a constant value used to calculate the maximum num-
ber of registers allocated to the step data table; the number may range from
1 ... 255 in 16 bit CPUs and 1 .. 999 in 24 bit CPUs. The maximum number of
registers is the specified constant + 8. The specified constant must be > the value
placed in the steps used register in the middle node.
Included in the loadables library provided for chassis mount controllers are two
extended math instructions—MATH and DMTH—which provide you with double
precision math, square root, process square root, log, and antilog functions com-
parable to those in the EMTH instruction (Section 20.2).
Note The BLKM, TBLK, PID2 functions included in the loadables li-
brary are functionally identical to the functions of the same names de-
scribed in Chapter 20. The CKSM function in the loadables library is
functionally identical to the function described in Chapter 18.
21.10.1 MATH
The MATH function performs any one of four integer math operations. MATH is a
three-node function block:
result Error
(invalid operand)
MATH
function code
(1 ... 4)
The top node requires either two consecutive 4x registers or one 3x register. The
selected operation is performed on the value held in the register(s). The four dif-
ferent operation types (as specified by code number in the bottom node) each has
specific limits on the operand value allowed in the register(s):
For integer square root functions, the value stored in each register cannot ex-
ceed 9999, permitting a maximum stored value of 99,999,999 in the 4x regis-
ters and a maximum stored value of 9,999 in the 3x register
For logarithm functions, the value stored in each register cannot exceed 9999,
permitting a maximum stored value of 99,999,999 in the 4x registers and a
maximum stored value of 9,999 in the 3x register; the register value must not
be less than 1
The middle node is the first of two consecutive 4x holding registers. The result of
the operation is stored in these two registers.
The bottom node provides the functional selection mechanism for the block. En-
ter a constant value in the range 1 ... 4 to indicate the integer math function you
want to employ:
21.10.2 DMTH
The DMTH function performs any one of four double precision math operations.
DMTH is a three-node function block with input and output lines that vary depend-
ing on the selected operation:
DMTH
1
4x and 4x + 1 hold the second operand value, in the range 0 ... 99,999,999
The top node comprises two consecutive 4x registers; each register holds a value
in the range 0000 ... 9999 for a combined value range of up to 99,999,999.
4x and 4x + 1 hold the second operand value, in the range 0 ... 99,999,999
DMTH
3
The top node comprises two consecutive 4x registers; each register holds a value
in the range 0000 ... 9999 for a combined value range of up to 99,999,999.
4x and 4x + 1 hold the second operand value, in the range 0 ... 99,999,999
ON = operand #1 is divided
by operand #2 and the re- operand #1 ON = operation performed
sult is placed in designated successfully
registers
The top node comprises two consecutive 4x registers; each register holds a value
in the range 0000 ... 9999 for a combined value range of up to 99,999,999.
4x and 4x + 1 hold the second operand value, in the range 0 ... 99,999,999
(Since division by 0 is illegal, a 0 value causes an error—an error trapping rou-
tine sets the remaining middle-node registers to 0000 and turns the bottom out-
put ON.)
The EARS block is loaded to a 984 controller being used in an alarm/event re-
cording system. An EARS system requires that the 984 work in conjunction with a
man-machine interface (MMI) host device that runs a special off-line software
package. The controller monitors a specified group of events for any changes in
state and logs change data into a buffer; the data are then removed by the host
over a high speed network such as Modbus II or Modbus Plus. The two devices
comply with a defined handshake protocol that ensures that all data detected by
the 984 controller are accurately represented in the host.
When the controller detects a change between the current state bit and the history
bit for an event, the EARS function block prepares a two-word message and
places it in a circular buffer where they can be off-loaded to a host MMI. This
message contains:
A time stamp representing the time span from midnight to 24:00 hours in tenths
of a second
A transition flag indicating that the event is either a positive or negative transi-
tion with respect to the event state
The host MMI device must be able to read and write 984 data registers via the
Modbus protocol. A handshake protocol maintains integrity between the host and
the circular buffer running in the 984; this enables the the host to receive events
GM--0984--SYS 984 Loadable Instructions 317
asynchronously from the buffer at a speed suitable to the host while the controller
detects event changes and load the buffer at its faster scan rate.
EARS
Buffer Reset—event table and top # of registers Buffer full—no events can
node pointers are cleared to 0 used in buffer be added until host off-loads
some or until Buffer Reset
The top node contains the first of 64 consecutive 4x registers. The first two of
these registers contain values that specify the location and size of the current
state table. The the remaining 62 registers are available to contain the history
table:
4x is the indirect pointer to the current state table—e.g., if the register contains
a value of 5, then the state table begins at register 40005
4x + 1 contains a value in the range 1 ... 62 that specifies the number of regis-
ters in the current state table
4x + 2 is the first register of the history table, and the remaining registers allo-
cated to the top node may be used in the table as required; the history table
can provide monitoring for as many as 992 contiguous events (if 16 bits in all
the 62 available registers are used)
If all 62 registers are not required for the history table, the extra registers may be
used elsewhere in the program for other purposes, but they will still be found (by a
Modbus search) in the top node of the EARS block.
4x contains a value that defines the maximum number of registers the circular
buffer may occupy
4x + 1 contains the Q_take pointer—the pointer to the next register where the
host will go to remove data
The low byte of register 4x + 2 contains the Q_put pointer—the pointer to the
register in the circular buffer where the EARS block will begin to place the next
state-change data; the high byte of register 4x + 2 contains the last transaction
number received
4x + 5 is the first register in the circular buffer where event-change data are
stored; each detected change in event status produces two consecutive regis-
ters of information:
Event Data Register 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 =Bits
Four Most Significant Positive Transition
of Event Event Type
Time Stamp
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
The following table shows binary weighted values for the time stamp, where n is
the relative bit position in the 20-bit time scheme:
Event Data Register 1 Event Data Register 2
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2n n 2n n 2n n
1 0 256 8 65536 16
2 1 512 9 131072 17
4 2 1024 10 262144 18
8 3 2048 11 524288 19
16 4 4096 12
32 5 8192 13
64 6 16384 14
128 7 32768 15
Note The real time clock in the chassis mount controllers has a
tenth-of-a-second resolution, but the other 984s have real time clock
chips resolve only to a second. An algorithm is used in EARS to pro-
vide a best estimate of tenth-of-a-second resolution—it is accurate in
the relative time intervals between events, but it may vary slightly from
the real time clock.
The bottom node displays an even constant value in the range 2 .... 100, which
represents the actual number of registers allocated for the circular buffer. Each
event requires two registers for data storage—therefore, if you wish to trap up to
25 events at any given time in the buffer, assign a value of 50 in the bottom node.
C
A C986 Coprocessor, 22
A120 Series I/O CALL function, for 984 coprocessors, 24
combo module, 46 CALL loadable function, 298
discrete input modules, 46, 47 part numbers, 292
discrete output modules, 46, 47 capacities of 984 controllers, 4
ADD function, 134 CKSM function, in ladder logic, 233
addition clearing bits, in a DX matrix, 164
floating point, 262 closed loop control, 276
floating point and integer values, 257
CMPR function, 162
integer, 134
coils
alarm/event warning system, 317
0x, 74
AND function, 156
as displayed in ladder logic, 97
antilogarithm (base 10) calculation latched, 124
using EMTH, 254 normal, 124
using MATH, 313
arccosine calculation, in floating point, 269