Chinesisch With Dac7718

Texas Instruments Incorporated
ߛ Ⴀ ీ ఇAnalog
High-Performance ెׂ೗ Products
ఇెᆌᆩ೺਽
Analog Applications
Journal
2011
Third ౎‫ڼ‬ෙल‫܈‬
Quarter, 2011
© Copyright 2011 Texas Instruments

ዘᄲำ௽
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Following are URLs where you
ຕጴᅼೕ can obtain information on other Texas Instruments
www.ti.com.cn/audio থ੨ products and application solutions:
http://www.ti.com.cn/interface
ཚ႑ᇑ‫ۉ‬႑
Products www.ti.com.cn/telecom Ҿ‫ݞ‬ᆌᆩ
Applications www.ti.com.cn/security
‫ٷݣ‬ഗࢅ၍Ⴀഗॲ
Audio http://www.ti.com.cn/amplifiers
www.ti.com/audio இड and Telecom www.ti.com/communications
Communications http://www.ti.com.cn/logic
ऺ໙ऐतዜՉ
Amplifiers www.ti.com.cn/computer
amplifier.ti.com Computersഛ‫ۉכ‬ጱand Peripherals www.ti.com.cn/automotive
www.ti.com/computers
ຕ਍ገ࣑ഗ
Data Converters dataconverter.ti.com Consumer‫ۉ‬ᇸ࠶૙
ers http://www.ti.com.cn/dataconvert Electronics www.ti.com/consumer-apps
http:///www.ti.com.cn/power
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ၩ‫ۉݯ‬ጱ www.dlp.com
www.ti.com/consumer-apps Energy and๫ೕࢅᆖၟ
Lighting www.ti.com/energy
www.ti.com.cn/video
DSP
DLP ®
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www.dlp.com Industrial ྲ੦዆ഗ www.ti.com/industrial
(MCU) ershttp://www.ti.com.cn/
Clocks and Timers
ీᇸ www.ti.com/clocks
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microcontroll
Interface
DSP - ຕጴ႑ࡽ‫ت‬૙ഗ interface.ti.com
http://www.ti.com.cn/dsp Security ࿮၍ཚ႑ www.ti.com/security
www.ti.com.cn/wireless
Logic
߾ᄽᆌᆩ logic.ti.com Space, Avionics
RFID ဣཥand Defense www.ti.com/space-avionics-defense
http://www.ti.com.cn/rfidsys
www.ti.com.cn/industrial
Power Managementt power.ti.com Transportation and Automotive www.ti.com/automotive
้ዓࢅऺ้ഗ ers http://www.ti.com.cn/clockandtim RF/IF ࢅZigBee® ঴ਦ‫ݛ‬ӄ www.ti.com.cn/radiofre
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
ᅅଐ‫ۉ‬ጱ www.ti.com.cn/medical
RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions www.ti.com/lprf
TI E2E ߾‫ײ‬฾ม൶ http://e2e.ti.com/cn/
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CopyrightCopyright © 2011, Texas Instruments Incorporated
2
High-Performance Analog Products www.ti.com/aaj 3Q 2011 Analog Applications Journal

ణ୤
Contents
Introduction
ᆅჾ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Data Acquisition
ຕ਍֑ण
Clock jitter analyzed in the
time domain, Part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
้ዓ۶‫้ۯ‬ᇘ‫ݴ‬ဆǈ‫ڼ‬ և‫ ݴ‬analysis by showing how to increase the SNR of an ADC by improving
This article continues3clock-jitter 5
the ADC’s aperture jitter. One of the methods evaluated to increase
Ԩ࿔ीჄ৊ႜ้ዓ۶‫ݴڦۯ‬ဆǈ‫׃‬௽କසࢆཚࡗ߀฀ SNR was to use a low-noise ampli-
ADC‫ڦ‬੥০۶‫ۯ‬ઠ༵ߛ ADC‫ڦ‬SNR ă໯ೠࠚ
fier for active gain. Another method was to use a step-up transformer for passive gain. The results of the
‫ڦ‬ኼሞ༵ߛ SNR ‫݆ݛڦ‬ኮᅃ๟๑ᆩᅃ߲‫گ‬ሯำ‫ٷݣ‬ഗǈᅜํ၄ᆶᇸሺᅮăଷᅃዖ‫݆ݛ‬ሶ๟֑ᆩᅃ߲
analysis show that improving the slew rate of the clock signal makes the ADC’s SNR match the predicted
ืუՎუഗǈᅜइ‫ڥ‬࿮ᇸሺᅮă‫ݴ‬ဆ‫ڦ‬঳ࡕ՗௽ǖ‫ܔ‬ᇀߴۨ‫้ڦ‬ዓ۶‫ۯ‬ଉǈ߀฀้ዓ႑ࡽ‫ڦ‬ገ࣑໏
SNR for a given amount of clock jitter.
୲੗๑ADC‫ڦ‬SNRᇑᇨ֪‫ڦ‬SNR၎೅ದă
How delta-sigma ADCs work, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
˚˨ADCSignal-processing
߾ፕᇱ૙ǈ‫ڼ‬ 1և‫ݴ‬are
techniques
beginning to shift from analog to digital. The design of delta-sigma
13
ADCs is approximately three-quarters digital and one-quarter analog. Delta-sigma ADCs are now ideal
႑ࡽ‫ت‬૙रຍኟሞٗఇెၠຕጴገᅎă ΔΣADC
for converting analog signals over a wide range ยऺ‫ٷڦ‬ሀ຺‫ݴ‬ኮෙྺຕጴยऺǈ຺‫ݴ‬ኮᅃྺఇె
of frequencies. This article, the first of a two-part series,
explores theΔΣADC
ยऺă၄ሞǈ basic topology and function of the delta-sigma modulator.
๟ሞ੻ೕ୲‫ܔాྷݔ‬ఇె႑ࡽ৊ႜገ࣑‫ڦ‬૙ၙ჋ስăԨ࿔๟ᅃೊԈࡤଇ߲և
‫ڦݴ‬ဣଚ࿔ቤ‫ڼڦ‬1և‫ݴ‬ǈॽ༑৯ΔΣۙ዆ഗ‫ڦ‬एԨྊ೫঳ࠓᇑࠀీă
Power Management
‫ۉ‬ᇸ࠶૙
A boost-topology battery charger powered from a solar panel . . . . . . . . . . . . . . . . . . .17
ᆩ໿ᄞీ‫׾ۉ‬ӱྺืუྊ೫঳ࠓ‫׾ۉ‬؊‫ۉ‬ഗࠃ‫ۉ‬
The growing popularity of charging batteries with solar panels has increased the need to charge multicell
17
batteries with a solar-panel voltage that is lower than the battery voltage. This situation calls for a boost-
ໜጣ‫׾ۉ‬໿ᄞీ؊‫ڦۉ‬න൵ୁႜǈට்‫ܔ‬ᇀ૧ᆩ‫گ‬ᇀ‫ۉ׾ۉ‬უ‫ڦ‬໿ᄞీ‫׾ۉ‬ӱ‫ۉ‬უ‫׾ۉ༹ܠܔ‬ፇ৊
topology charger. This article describes how it is possible to modify a buck battery charger into a boost
or step-up battery charger.
ႜ؊‫ڦۉ‬Ⴔ൱ᆶ໯ሺेăኄዖ൧઄ᄲ൱๑ᆩᅃ߲ืუྊ೫঳ࠓ؊‫ۉ‬ഗăԨ࿔ຫ௽କසࢆཚࡗ‫ܔ‬ইუ
‫׾ۉ‬؊‫ۉ‬ഗ৊ႜ߀৊ܸ๑ኮ‫ྺׯ‬ᅃዖืუ‫׾ۉ‬؊‫ۉ‬ഗă
Interface (Data Transmission)
Isolated RS-485 transceivers support DMX512 stage lighting and
থ੨Ǆຕ਍‫د‬๼ǅ
special-effects applications . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .21
߰૗๕RS-485 ๭݀ഗ੗ኧ‫׼‬
Data-transmission DMX512
networks often ࿸໼ቷ௽ࢅ༬ၳᆌᆩ
reach distances of up to 1200 meters. This article provides an overview 21
ຕ਍of‫د‬the๼DMX512-A
ྪ ஏ ‫ ڦ‬ཚstandard
႑ ਐ ૗that‫׉ ׉‬specifies
੗ ‫ ٳ‬12EIA-485
00௝ă asԨthe
࿔network’s
߁ຎକॽ physical
E I A - 4layer.
8 5 ࡀIncluded
ۨ ྺ ྪisஏa ኮ
design
࿿૙֫‫ڦ‬
example that shows how to connect an isolated responder node to a DMX512-A network.
DMX512-AՔጚă࿔ዐଚਉକᅃ߲ยऺํ૩ǈཚࡗ޿ํ૩੗ᅜକ঴සࢆӝ߰૗๕ገ݀ഗব‫૶ۅ‬থ዁
Industrial data-acquisition
ᅃ߲DMX512-A ྪஏă interfaces with digital isolators . . . . . . . . . . . . . . . . . . . . . .24
Galvanic isolation has become the mantra for industrial applications to protect personnel and equipment.
ਏᆶຕጴ߰૗ഗ‫߾ڦ‬ᄽຕ਍֑णথ੨ 24
While analog systems use single-channel isolation amplifiers, power-saving digital isolators offer multi-
channel equipment interfaces with smaller form factors. This article explains both types of isolators and
‫߰ۉ‬૗ᅙ‫ྺׯ‬କ߾ᄽᆌᆩ‫ڦ‬Ղႜ൵๞ǈ໲੗‫ܔ‬ටᇵᇑยԢഐ‫ڟ‬ԍࢺፕᆩăఇెဣཥ֑ᆩ‫ڇ‬ཚ‫߰ڢ‬૗
their operation principles.
‫ٷݣ‬ഗǈܸবీ‫ڦ‬ຕጴ߰૗ഗሶ༵ࠃକྔႚ؅٫ডၭ‫ܠڦ‬ཚ‫ڢ‬ยԢথ੨ăԨ࿔ຫ௽କኄଇዖૌ႙‫ڦ‬
߰૗ഗतഄ߾ፕᇱ૙ă
Amplifiers: Op Amps
Converting single-ended video to differential video in single-supply systems . . . . . .29
‫ٷݣ‬ഗǖሏ໙‫ٷݣ‬ഗ
Video signals are commonly processed as single-ended, but it is often desirable to use differential
techniques for transmission through cables. This
‫ۉڇ‬ᇸဣཥዐ‫܋ڇ‬๫ೕ዁ֶ‫ݴ‬๫ೕ‫ڦ‬ገ࣑ article shows how to use a fully differential amplifier to 29
convert single-ended video signals to differential to drive a Cat 5 cable with double termination in a
๫ೕ႑ࡽ‫׉׉‬ፕྺ‫܋ڇ‬႑ࡽ৊ႜ‫ت‬૙ǈ‫ڍ‬๟ට்ཚ‫׉‬ထྭ֑ᆩֶ‫ݴ‬रຍॽഄገ࣑ྺֶ‫ݴ‬႑ࡽǈᅜཚ
single-supply system. Included is a TINA-TI™ software file for viewing the example circuit simulation
ࡗ၍મ৊ႜ‫د‬๼ăԨ࿔঻ถසࢆ๑ᆩᅃ߲ඇֶ‫ٷݣݴ‬ഗॽ‫܋ڇ‬๫ೕ႑ࡽገ࣑ྺֶ‫ݴ‬႑ࡽǈᅜሞ‫ۉڇ‬
with TI’s free software tool.
ᇸဣཥዐൻ‫ۯ‬ᅃཉມ‫܋‬থ5ૌ (Cat 5) ၍મă࿔ዐԈઔᅃ߲TINA-TITM෉ॲ࿔ॲǈᆩᇀ૧ᆩTI‫ڦ‬௨‫ݯ‬
Index of Articles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
෉ॲ߾ਏઠֱੂ‫ۉ‬ୟ‫ݠ‬ኈ๖૩ă
࿔ቤ໭ᆅ
TI Worldwide Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4034
TIඇ൰रຍኧ‫ ׼‬40
සႴֱለĖఇెᆌᆩሗኾėࡗ਽ǈ
To view past issues of the
৤൩‫ݡ‬࿚ᅜူྪ኷ǖ
Analog Applications Journal, visit the Web site
www.ti.com/aaj
www.ti.com/aaj
Analog Applications Journal 3Q 2011 www.ti.com/aaj High-Performance Analog Products

ᆅჾ
Introduction
Ėఇెᆌᆩ೺਽ė๟ᅃԨఇెᆌᆩ࿔ቤ‫ࢇڦ‬णǈኼሞඟ࠽‫܁ٷ‬ኁକ঴ TI ׂ೗ǈཞ้঻ถ
ᅃၵ०‫ڍڇ‬ඐ࢔ํᆩ‫ۆڦ‬႙ᆌᆩ૩ጱăԨ೺਽փৈৈ௬ၠยऺ߾‫ײ‬฾ǈܸ൐࣏௬ၠ߾‫ײ‬
ঢ়૙ĂरຍටᇵĂဣཥยऺටᇵࢅ๨‫ׇ‬ᆐၨतၨ๳ටᇵăԨ೺਽ཚࡗ‫ٷ‬ೊ‫ڦޗ‬ຕბ‫ݴ‬ဆ
Analog Applications Journal is a collection of analog application articles
཭‫؜‬ຫ௽କᅃӯᆌᆩ߁౒ă
designed to give readers a basic understanding of TI products and to provide
simple but practical examples for typical applications. Written not only for
঻ถኄၵᆌᆩ‫ڦ‬ణ‫ڦ‬ǈժ‫ݥ‬๟ፕྺగၵਏ༹‫ۉ‬ୟ‫ڦ‬Đ๑ᆩኸళđຫ௽ກǈܸ๟ፕྺසࢆ
design engineers but also for engineering managers, technicians, system
૧ᆩഗॲઠ঴ਦਏ༹ยऺ࿚༶‫ڦ‬૩ጱăཚࡗူଚణ୤ǈ‫܁‬ኁ੗ᅜइ‫ڥ‬ঞბጨଙࢅᅃၵํ
designers and marketing and sales personnel, the book emphasizes general
ᆩ‫ײ߾ڦ‬঴ਦ‫ݛ‬ӄǖ
application concepts over lengthy mathematical analyses.
sຕ਍֑ण
These
s‫ۉ‬ᇸ࠶૙applications are not intended as “how-to” instructions for specific
circuits but as examples of how devices could be used to solve specific design
থ੨Ǆຕ਍‫د‬๼ǅ
s
requirements. Readers will find tutorial information as well as practical
s‫ٷݣ‬ഗǖᅼೕ
engineering solutions on components from the following categories:
s‫ٷݣ‬ഗǖሏ໙‫ٷݣ‬ഗ
Y Data Acquisition
‫ࡼࠀگ‬
s Y PowerRFManagement
s‫׉‬९࿚༶
Y Interface (Data Transmission)
Y Amplifiers: Audio
ሞࢇ๢‫ڦ‬൧઄ူǈ‫܁‬ኁ࣏੗ᅜକ঴‫ॲ෉ڟ‬૩‫ײࢅײ‬Ⴞ঳ࠓăፌࢫǈĖఇెᆌᆩ೺਽ė࣏
Y Amplifiers: Op Amps
ᆶᅃၵᆶᆩ‫༵ڦ‬๖ࢅঢ়ᄓ݆ሶǈᅜኸ‫܁ڞ‬ኁྜ‫ׯ‬ഄยऺጚԢ߾ፕă
Y Low-Power RF
Y General Interest
Where applicable, readers will also find software routines and program
structures. Finally, Analog Applications Journal includes helpful hints and
rules of thumb to guide readers in preparing for their design.

Texas Instruments Incorporated Data Acquisition
้ዓ۶‫้ۯ‬ᇘ‫ݴ‬ဆ ‫ ڼ‬3 և‫ݴ‬

ፕኁǖThomas Neuǈ
‫ڤ‬ዝᅏഗ (TI) ဣཥᇑᆌᆩ߾‫ײ‬฾
ᆅჾ
཮ 20 SNR
Figure Ă้ዓና‫ࢅޗ‬๼෇ೕ୲‫࠲ڦ‬ဣ൸၍཮Ǆቌ
20. SNR versus clock amplitude versus input
Ԩဣଚ࿔ቤࠌ 3 ߲և‫ݴ‬ǈ‫ ڼ‬1 և‫ݴ‬ዘ‫঻ۅ‬ถ ጲ
frequency
ADS54RF63(fromׂ೗ຫ௽ກǅ
ADS54RF63 data sheet)
କසࢆጚඓࠚ໙ᅃ้߲ዓᇸ‫ڦ‬۶‫ۯ‬ǈժॽഄཞ
ADC1 ‫ڦ‬੥০۶‫ۯ‬ፇࢇሞᅃഐăሞ‫ ڼ‬2 և‫ݴ‬ 66.0
ዐǈ࿢்૧ᆩኄዖፇࢇ۶‫ऺۯ‬໙ ADC ‫ڦ‬႑ሯ
fIN = 100 MHz
Բ (SNR)ǈኮࢫॽऺ໙঳ࡕᇑํा֪ଉ൧઄‫ܔ‬ 65.5
Signal-to-Noise Ratio, SNR (dBFS)

Բ2ăԨ࿔๟ဣଚ࿔ቤ‫ ڼڦ‬3 և‫ݴ‬ǈॽྺ౞঻
65.0
ถසࢆཚࡗ߀฀ ADC ‫ڦ‬੥০۶‫ۯ‬ઠ৊ᅃօ༵ fIN = 300 MHz
ߛ ADC ‫ڦ‬႑ሯԲă࿔ቤॽዘ‫঻ۅ‬ถසࢆ‫้ܔ‬
64.5
ዓ႑ࡽ‫ڦ‬ገ࣑໏୲৊ႜᆫࣅă
64.0
ස‫ ڼ‬1 և‫ ڼࢅݴ‬2 և‫ݴ‬໯ຎǈ้ዓ႑ࡽ‫ټ‬ཚ
୳հഗ๟‫ ڟٳ‬ADC ׂ೗ຫ௽ກ SNR ኵ‫ڦ‬ᅃ߲
63.5
࠲॰ፇॲă้ዓ႑ࡽ‫ڦ‬ᇺ‫܋‬၎࿋ሯำඟ้ዓ႑
ࡽጺ۶‫ٷۯ‬ଉሺेǈܸٗ๑ SNR ሞߛ๼෇ೕ 63.0
୲ူ੺໏ই‫گ‬ă fS = 500 MSPS
62.5
փ႞‫ڦ‬๟ǈ‫ټ‬ཚ୳հഗ٪ሞଇ߲ჹዘ‫ڦ‬ඍ‫ۅ‬ă 0 1 2 3 4 5
๯ံǈ໲փৈඁ‫أ‬କ้ዓ႑ࡽ‫ڦ‬ᇺ‫܋‬၎࿋ሯ Clock Amplitude (VPP)
ำǈܸ൐ᄺඁ‫أ‬କएԨ้ዓೕ୲‫ߛڦ‬঩ആْၿ
հǈܸٗॽ‫ݛ‬հՎྺኟ၀հăኄၵആْၿհǄ3 ْၿհĂ5
ْၿհ‫ڪ‬ǅ‫ܔ‬ᇀ‫ڟٳ‬ፌၭࣅ ADC ੥০۶‫ۯ‬໯Ⴔ‫ߛڦ‬ገ࣑໏
ADC ‫ׂڦ‬೗ຫ௽ກཚ‫ࣷ׉‬ᅜ SNR ᇑ้ዓና‫ޗ‬൸၍
୲ܸჾ๟ՂႴ‫ڦ‬ăഄْǈߵ਍փཞ‫ڦ‬ྊ೫঳ࠓࢅ঩ǈ໲ࣷ
཮‫ڦ‬ႚ๕՗௽ገ࣑໏୲‫ ܔ‬ADC ‫ ڦ‬SNR Ⴀీ‫ڦ‬ᆖၚ
ᆶᅃۨ‫ڦ‬໦ࡼǈഄᅃӯྺ 1 ‫ ڟ‬9dB փ‫ڪ‬ăኄዖ໦ࡼ၎‫ړ‬ᇀ
‫܈ײ‬ǈස཮ 20 ໯๖ă޿཮ቌጲ TI ADS54RF63 ׂ೗
ປ३କ้ዓና‫ޗ‬ǈܸٗ৊ᅃօই‫گ‬କ้ዓ႑ࡽ‫ڦ‬ገ࣑ ຫ௽ກǈഄ՗௽้ዓና‫ޗ‬ሁ‫ٷ‬ǈገ࣑໏୲৽ሁߛă
໏୲ă ཮ 20 ࣏՗௽ǈස࿢்ᇨऺ‫ڦ‬ఫᄣǈ SNR ‫้ܔ‬ዓ
ገ࣑໏୲‫܈ײߌ௺ڦ‬ǈໜ๼෇ೕ୲ fIN ‫ڦ‬ሺेܸሺ
཮ 21 1.8-V
Figure ࢅ 3.3-V இडഗॲ‫ټڦ‬ཚ୳հ
21. Bandpass-filter input and output ेă‫ڍ‬๟ǈ൸၍཮ᄺ՗௽ǈ้ዓ๼෇ࡗ‫ٷ‬੗ీ‫ڞ‬ዂ
ഗ๼෇ᇑ๼‫؜‬
with 1.8-V and 3.3-V logic ADC ాև‫؜‬၄ၥհईኁ໦࣋ǈܸٗ‫ ܔ‬SNR ׂิփ
૧ᆖၚă
3.3-V
Signal ྺକই‫ࠦگ‬ᆶሯำࢅࠀࡼǈ߳‫ٷ‬዆ሰ‫׍‬ฆ‫ۼ‬๑ᆩ
߸ၭ‫߾ڦ‬ᅝব‫ۅ‬ઠิׂ้ዓ‫ݴ‬ದ IC ǈፌዕ३ณ‫ۉ‬ᇸ
ࡆă૩සǈ၎Բᅃ੼ 3.3-V ഗॲǈཚࡗᅃ੷ 1.8-V ഗ
3.3-V
Sine
ॲइ‫ߛڥ‬ገ࣑໏୲้ዓ႑ࡽᄲઓవ‫ܠڥ‬Ǘଷྔǈ‫ټ‬
1.8-V Wave ཚ୳հഗ‫ڦ‬໦ࡼኻࣷඟኄዖ൧઄დฉेຠǄ൩֖९
1.8-V
Sine
Signal ཮ 21ǅă
Wave
Ԩ࿔ഄ໱և‫ݴ‬ǈॽዘ‫঻ۅ‬ถଇዖํᆩ‫݆ݛ‬ǈຫ௽ස
ࢆሞํाᆌᆩዐཚࡗĐ࣬ްđԥඁ‫้ڦأ‬ዓၿհǈ
ፌ‫୳ࣅٷ‬հ้ዓ႑ࡽ‫ڦ‬ገ࣑໏୲ăԨዊฉܸჾǈႴ
ᄲඟ้ዓᄂምْ‫װ‬၄ྺ‫ݛ‬ႚǈཞ้ᄲ৑੗ీ‫ں‬ሺे

Data Acquisition Texas Instruments Incorporated
႑ࡽӦ‫ޗ‬ǈᅜց‫ټ׋‬ཚ୳հഗ (BPF)ׂิ‫ڦ‬໦ࡼăཚࡗ
ᅃ߲ᆶᇸईኁ࿮ᇸ‫ۉ‬ୟሺे႑ࡽሺᅮǈ੗ᅜྜ‫ׯ‬ኄଇၜ ཮ 22 ሺे‫ۉ‬ୟઠ༵ߛገ࣑໏୲
Figure 22. Addition of circuitry to boost
߾ፕǄ֖९཮ 22ǅăଇዖ‫ۼ‬ᆶጲम‫ڦ‬ᆫ‫ࢅۅ‬ඍ‫ۅ‬ǈူ slew rate
௬࿢்ॽ‫ܔ‬ഄደᅃ৊ႜ༪ஃǈժຫ௽჋ስ๑ᆩనዖ‫݆ݛ‬
‫ڦ‬ᅃၵዘᄲ੊୯ᅺ໎ă Clock
Distribution Clock In
๑ᆩᅃ߲‫گ‬ሯำ‫ٷݣ‬ഗइ‫ڥ‬ᆶᇸሺᅮ IC
BPF Slew-Rate
ဣཥยऺටᇵཚ‫׉‬փဠ࣌๑ᆩᆶᇸሺᅮǈᇱᅺ๟ഄࣷሺ Compensation
ेဣཥ‫ڦ‬ሯำǈժ൐ࣷၩࡼ߸‫୲ࠀڦٷ‬ă‫ڍ‬๟ǈሞᅃၵ
൧઄ူǈ໲੗ీ๟ྸᅃ‫ڦ‬჋ၜǈ૩සǖยऺ๑ᆩକᅃ߲
‫ื؜ג‬უՎუഗ‫้ߛڦ੻ټ‬ዓೕ୲ă
Figure 23. Low-power
཮ 23 ‫ࡼࠀگ‬ LNA ց‫ ׋‬LNA
BPFcompensates
໦ࡼ
჋ስ‫ٷݣ‬ഗǈဣཥยऺටᇵႴᄲ੊୯සူᅃၵ֖ຕǖ for BPF losses
‫ݔࡀ੻ټ‬ĊĊ๨‫ׇ‬ฉᆶႹ‫ ܠ‬RF ‫ٷݣ‬ഗ੗ࠃ჋ስǈ‫ڍ‬๟

ీࠕ‫ڟٳ‬ዐೕǄ<250 ‫ ڟ‬500MHzǅ‫ڦ‬ඐ଒଒࿮बăՔ
ጚ CMOS ‫ٷݣ‬ഗ‫ڦ‬ሯำဣຕփࠕ‫گ‬Ǆ<2 dBǅǈᅺُ CDCE72010 SPF-5043
LNA
ፌॅ‫݆ݛ‬๟჋ስᅃ߲ RF ‫ٷݣ‬ഗăኄዖ‫ٷݣ‬ഗ‫ڦ‬੗ᆩ‫ټ‬
BPF
੻Ⴔᄲፁࠕ੻ǈᅜԈઔ዁ณෙ঩ፌࡻ๟࿵঩एԨ้ዓೕ
୲ၿհăᅺُǈᆩᇀ 122.88-MHz ้ዓ‫ٷݣڦ‬ഗ዁ณႴ
ᄲ‫ ڟٳ‬368.64 MHzǈܸ 500-MHz ้ዓ‫ٷݣڦ‬ഗሶ዁
ณႴᄲ‫ ڟٳ‬1.5 GHză
୳հഗ (BPF) ኮक़Ǆ൩֖९཮ 23ǅǈᅜ၌዆‫ྔܮ‬ሯำଉ
ሯำဣຕĊĊྺକፌၭࣅ‫گ‬ሯำ‫ٷݣ‬ഗ (LNA) ‫ྔܮڦ‬ Ǆ൩֖९཮ 24ǅăǄ཮ 23 ࢅ 24 ๑ᆩ‫ ڦ‬TI CDCE72010
ሯำᆖၚǈഄሯำဣຕᆌ዁ณྺ 2d ईኁ߸ࡻă‫ܠٷ‬ຕ ᄺ৽๟Ԩဣଚ࿔ቤ‫ ڼ‬2 և‫ݴ‬ዐਉ૩໯๑ᆩ‫้ڦ‬ዓཞօ
LNAǄन๑ਏᆶ‫گ‬ሯำဣຕǅǈ‫ࣷۼ‬ሺे้ዓ႑ࡽ‫੻ڦ‬ ഗǅ߸ࡻ‫ڦ‬ሯำဣຕᅃӯᄲ൱߸‫ࡼࠀڦܠ‬ǈܸኄዖᄲ൱
ೕ‫ټ‬ሯำăᅺُǈLNA ᆌ޿࿋ᇀ้ዓ‫ݴ‬ದഗॲࢅ‫ټ‬ཚ ੗ీࣷ၌዆࿢்჋ስࢇ๢‫ٷݣڦ‬ഗă
཮ 24 LNA
Figure ฎྲই‫گ‬କ
24. LNA slightlyBPF ཚ‫้ڦాټ‬ዓ႑ࡽ၎࿋ሯำ
degrades clock signal’s phase noise inside BPF’s pass band
–120
CDCE72010 + LNA + BPF

–130
CDCE72010 + BPF
Phase Noise (dBc/Hz)
–140
–150
–160
–170
–180
0.001 0.01 0.1 1 10
Frequency Offset (MHz)

P1dB უ໫‫ۅ‬ĊĊP1dB უ໫‫ۅ‬Ԩዊฉۨᅭକፌ‫ٷ‬੗ీ ཮ 25 ืუՎუഗ߀Վ๼෇ፆੇ

Figure 25. Step-up transformer changes
๼‫؜‬Ӧ‫ޗ‬ăᄲ‫ڟٳ‬ሀ 2 VPP ‫้ڦ‬ዓ႑ࡽǈႴᄲ P1dB input impedance
዁ณྺ 10 dBmă
‫ۉ‬უࡆĊĊ‫ٷݣ‬ഗ‫ۉڦ‬უࡆǈ੗ᅜᆩᇀՆ௨‫ ؜ג‬ADC
้ዓᆅগ‫ڦ‬ፌ‫ۉٷ‬უ‫ۨܮ‬ኵă‫ڍ‬๟ǈᄲइ‫ڥ‬ፌ‫ٷ‬Ⴀీǈ 1:4
ᅃ߲ႎ‫ۉڦ‬უࡆईႹ๟ՂႴ‫ڦ‬ǈ‫ڍ‬ኄᆼሺेକဣཥ‫ׯڦ‬ R IN
50 200 RT
Ԩࢅӱप੣क़ă
࿘ۨႠĊĊ‫گ‬໦ࡼ LC ‫ټ‬ཚ୳հഗਏᆶߛ‫ੇۉ‬ă RF
LNA ‫ڦ‬૙ၙ൧઄๟ൻ‫ ۯ‬50-Ω ‫޶ڦ‬ሜǈᅺُൻ‫ੇۉۯ‬੗
ీࣷᆅഐփ࿘ۨईኁ฿ኈǈժ‫؜‬၄༪ᄋ‫ڦ‬ॖ‫ރ‬ǈܸٗᄲ უഗ‫׉‬ᆩᇀ้ዓୟ০ዐǈॽ้ዓ๼෇ٗ‫܋ڇ‬ገ࣑ྺֶ‫ۯ‬ă
൱೅ದྪஏă ‫ڍ‬๟ǈሞᆶၵᆌᆩዐืუՎუഗඐժփํᆩăሞ჋ስ้ǈ
ሺ ᅮ ĊĊ न ๑ L N A ߾ ፕ ሞ ᇑ Բ ড ഗ ૌ ຼ ‫ ߛ ڦ‬ሺ ᅮ ౞Ⴔᄲ੊୯සူᅃၵ֖ຕǖ
Ǆ>10 ‫ ڟ‬12 dBǅူǈ‫ڍ‬ᇑԨ࿔၎঳ࢇ‫ڦ‬ჺ৯՗௽ǈ‫ڇ‬ ‫੻ټ‬ᄲ൱ĊĊՎუഗጲวਏᆶ‫ټ‬ཚ୳հഗೕ୲ၚᆌăໜጣ
‫ڦك‬Բডഗժփ๢ࢇྜ‫ׯ‬ኄၜ߾ፕăኄၵԲডഗߴ๼‫؜‬ ೕ୲থৎ DCǈ๼෇ࢅ๼‫؜‬ኮक़‫ىڦ‬᳘ࢇՎ‫ڥ‬ሁઠሁෑǈ
႑ࡽሺेକ໿‫ڦܠ‬ሯำǈፌྺ‫׉‬९‫ڦ‬൧઄๟ഄገ࣑໏୲ ཞ้ሞᅃၵߛೕཉॲူǈՎუഗसิ၄ၡǄ૩සǖాևජ
փࠕߛă ፇ‫ۉ‬ඹࢅ୑‫ڪߌۉ‬ǅਸ๔቞ዷ‫ڞ‬ă၄ᆶՎუഗ‫ڦ‬ཚ‫੻ټټ‬
ဣଚ࿔ቤ‫ ڼڦ‬2 և‫ݴ‬ǈ঻ถକ๑ᆩ 122.88 MSPS ᅃӯ‫گ‬ᇀ੻‫ ټ‬LNAǄ૩සǖSPF-5043ǅǈܸೕ୲ฉ၌ໜื
֑ᄣೕ୲ൻ‫ ۯ‬TI ADS54RF63 ࢅ ADS5483 ADC ‫ڦ‬ უԲሺेǄ1ǖ8 ‫ ܔ‬1ǖ4ǅܸই‫گ‬ă
CDCE72010 ้ዓཞօഗਉ૩ăঢ়ࡗೠࠚǈRF ྲഗॲ ፆੇገ࣑ࢅՎუഗፆੇԲĊĊ‫ߛืأ‬๼‫ۉ؜‬უᅜྔǈื
ࠅິ (RF Micro Devices) ༵ࠃ‫ ڦ‬SPF-5043 LNAǈ‫ׯ‬ უՎუഗ࣏߀Վ๼෇ፆੇă૩සǈ 1 ǖ 4 ፆੇԲ‫ڦ‬Վუഗ
ྺକԨਉ૩‫ڦ‬๢ᆩ‫ٷݣ‬ഗǄ൩֖९཮ 23 ǅăྺକඟ ॽ 50-Ω ‫ۉ‬ᇸፆੇՎྺᅃ߲ 200-Ω ‫ۉ‬ᇸፆੇǄ൩֖९཮
LNA ‫ڟٳࡼࠀྔܮڦ‬ፌၭǈ‫ٷݣ‬ഗཚࡗᅃ߲ 3.3-V 25ǅăᅺُǈሞ჋ስՎუഗፆੇԲ้ǈႴᄲ੊୯ ADC ้
‫ۉ‬ᇸ߾ፕǈ֪‫ৢڥ‬ༀ‫ୁۉ‬ሀྺ 41 mA ǈनࠀࡼሀྺ ዓ‫ڦ‬๼෇ፆੇǈᇱᅺ๟ഄᇑ้ዓ‫ڦ‬๼෇‫( ܋‬RT) ժ૴ă૩
131 mW ă සǈසࡕ ADC ้ዓ‫ڦ‬๼෇ፆੇৈྺ 200 ‫ ڟ‬300Ωǈሶᅃ
߲ 1ǖ8 ‫ืڦ‬უՎუഗǄन๑࿮ඪࢆዕ‫܋‬ǅǈࣷߴ้ዓᇸ
SPF-5043 ׂ೗ຫ௽ກଚਉ‫ݔࡀڦ‬සူǖ
‫ټ‬ઠ 25 ‫ ڟ‬40Ω ‫޶ڦ‬ሜăኄ๟ᅃ߲ट‫޶ٷ‬ሜǈ੗ీፆኹ้
噝੗ᆩ‫ ڟٳ੻ټ‬100 MHz ዓᇸׂิ‫ٷ‬Ӧ‫ޗ‬ǈᅺྺഄ࿮݆༵ࠃፁࠕ‫ڦ‬๼‫ୁۉ؜‬ă
噝ሯำဣຕ=0.6 dB ፌ‫ۉٷ‬უӦ‫ޗ‬ĊĊืუՎუഗ੗ᅜൟ຿‫ٷิׂں‬ᇀ 5V ‫ڦ‬

噝P1dB = ~19 dBm ๼‫ۉ؜‬უǈഄტ໏‫؜ג‬କ ADC ้ዓ๼෇‫ڦ‬ፌ‫ۉٷ‬უ‫ۨܮ‬
ኵăᅃ߲ 5-V ገ࣑ഗཚ‫׉‬ਏᆶሀ 5.5V ‫ڦ‬ፌ‫ٷ‬๼෇‫ۉ‬უǈ
噝ሺᅮ= ~22 dB
ܸᅃ߲ 3.3-V ገ࣑ഗፌ‫ٷ‬ኻీ‫׶‬๴ሀ 3.6V ‫ڦ‬ፌ‫ۉٷ‬უă‫ג‬
न๑޿ LNA ‫ڦ‬ሯำဣຕඓํ࢔‫گ‬ǈ‫ ڍ‬LNA ࿋ᇀ‫ټ‬ཚ୳ ‫ ؜‬ADC ፌ‫ۉٷ‬უ‫ۨܮ‬ኵࣷ໫‫܌‬ഄ๑ᆩ๱ంǈժᆶ੗ీࣷ
հഗമ௬ܸ‫ࢫݥ‬௬้ SNR Ⴀీࣷ߸ॅă ‫ڞ‬ዂᆯ‫ۉ‬ഘࡗᆌ૰ᆅഐ‫ڦ‬ሚవႠࠤቱă৑࠶้ዓ๼෇ᅃӯ
ਏᆶ ESD ܾट࠶ԍࢺǈ‫ڍ‬๟ǈ࠼ᅈ੍໲ઠԍࢺժ‫ݥ‬ፌॅ
SPF-5043 ‫ڦ‬ፌ‫ٷ‬๼‫ۉ؜‬უ๴‫ ڟ‬3.3-V ‫ۉ‬უࡆ‫ڦ‬၌዆ă Ӹ݆ăํ၄‫ۉ‬ഘࡗᆌ૰ԍࢺ‫ڦ‬ᅃዖ߸ࡻӸ݆๟๑ᆩྔևၥ
‫ڍ‬๟ǈ๑ᆩืუՎუഗઠॽ႑ࡽٗ‫܋ڇ‬႑ࡽገ࣑ྺֶ‫ݴ‬
հܾट࠶ă
႑ࡽ้ǈ੗ీႴᄲ֑ൽഄ໱‫ٯ‬แǈᅜՆ௨‫ ؜ג‬ADC ้
ዓ๼෇‫ڦ‬ፌ‫ۉٷ‬უ‫ۨܮ‬ኵă
๑ᆩᅃ߲ืუՎუഗइ‫ڥ‬࿮ᇸሺᅮ
༵ߛ้ዓ႑ࡽገ࣑໏୲‫ڦ‬ፌ०‫ڇ‬Ӹ݆๟๑ᆩᅃ߲ืუՎ
უഗăᆯᇀ໲๟ᅃዖ࿮ᇸፇॲǈᅺُփࣷሺे‫ڦྔܮ‬ሯ
ำईኁࠀࡼăሞᅃၵࠀࡼ௺ߌ႙ईኁՍၻ๕ᆌᆩዐǈए
ᇀՎუഗ‫ڦ‬঴ਦ‫ݛ‬ӄ੗ీ๟ྸᅃํा‫ڦ‬჋ስǗཞ้ǈՎ
7

཮ 26 ๑ᆩၥհܾट࠶ํ၄
Figure ADC ๼෇ԍࢺ
26. Using clipping diodes to protect
ADC inputs
Single Dual
Diode Pair (SDP) Diode Pair (DDP)
๑ᆩၰ༬एၥհܾट࠶ ઄ူ๑ᆩ 1 ǖ 4 Վუഗ้ǈׂิ‫ ڦ‬CDCE72010

Using Schottky clipping diodes
๑ᆩၥհܾट࠶๟‫ݞ‬ኹຕ਍ገ࣑ഗ๼෇‫؜ג‬ፌ ୳հwith and without๼‫؜‬ă޿཮࣏၂๖କᅃ߲
LVCMOS a single diode pair (SDP). AlsoSDP shownࢅ is
Using clipping diodes is a common way to protect the data the output for when a 1:8 transformer is used with an SDP
‫ۉٷ‬უ‫ۨܮ‬ኵ‫ڦ‬ᅃዖ‫׉‬९‫݆ݛ‬ăᆯᇀ‫ۉگ‬ඹၰ ᅃ߲ԝ੍ԝມܾट࠶‫ܔ‬ or a back-to-back dual diode (DDP) ൧઄ူǈ๑ᆩ 1ǖ
pair (DDP). It can be seen
converter’s inputs from exceeding the maximum voltage
༬एܾट࠶Ǆ૩සǖ Avago Technologies
rating. Because low-capacitance Schottky diodes, such as ࠅ āՎუഗ้໯ׂิ๼‫؜‬ă࿢்੗ᅜੂ‫ڟ‬ǈ๑ᆩā
8 that with the 1:4 transformer, the SDP reduces the sine-
ິ‫ڦ‬ HSMS-2812
the HSMS-2812 ǅǈ੗ᅜԍ‫׼‬ডߛ‫ڦ‬ገ࣑໏
from Avago Technologies, can maintain fast 1ǖwave
4 Վუഗ้ǈ SDP
amplitude from ॽኟ၀հና‫ٗޗ‬ሀ
about 1.6 ই‫گ‬
1.6 to 0.9 VPP. However, the
୲ǈᅺُ໲்‫׉ݥ‬๢ࢇᇀ
slew rates, they are well-suited forRF ࢅߛ໏ᆌᆩă
RF and high-speed appli- ዁ clipped
0.9VPP ă‫ڍ‬๟ǈၥհኮࢫ‫ڦ‬๼‫؜‬հႚփምၟ๟
output waveform no longer resembles a pure sine
cations. The HSMS-2812
ᆛᆶ 410 hasmV
a forward voltage of 410 mV.
‫ڦ‬ኟၠ‫ۉ‬უă๑ᆩ wave but looks instead like a square wave.
ᅃዖ‫ك‬ኟ၀հǈܸ๟ੂഐઠၟ‫ݛ‬հă
HSMS-2812
Using a pair of anti-parallel diodes (see Figure 26) creates It is interesting to note that when the SDP configuration
ᅃ‫ొܔ‬ೝႜܾट࠶Ǆ൩֖९཮ 26ǅǈ੗ᅜႚ‫ׯ‬ is used, there doesn’t seem to be an amplitude difference
a differential clipping voltage of ±410 mV (820 mVPP). For
Ġ 410that
ADCs mVrequire
(820amV ‫ۯֶڦ‬ၥհ‫ۉ‬უă‫ܔ‬ᇀ
PP) clock
higher amplitude, two pairs of ࿢்ጀᅪ‫ڟ‬ᅃዖᆶ඀‫ڦ‬၄ၡǖ๑ᆩ
between using the 1:4 or the 1:8 transformer, SDP ঳ࠓᅜ
although the
ఫၵᄲ൱߸ߛ้ዓና‫ڦޗ‬
anti-parallel diodes can be placedADC ܸჾǈ੗ᅜԝ੍
back-to-back, doubling ࢫǈ๑ᆩ
waveform1for ǖ4theࢅlatter
1ǖappears
8 Վუഗኮक़ࡻၟுᆶና‫ޗ‬
to have a slightly faster
ԝ‫ݣں‬ዃଇ‫ొܔ‬ೝႜܾट࠶ǈܸٗඟၥհ‫ۉ‬უ
the clipping voltage to ±820 mV (1.64 VPP). ֶᅴǈ৑࠶ࢫኁ‫ڦ‬հႚၟ๟ਏᆶฎߛᅃၵ‫ڦ‬ገ࣑
slew rate. For the DDP configuration with the 1:8 trans-
former, the 1.6 VPP with a little
Figure 27 shows the filtered
ሺेᅃԠǈ‫ ڟٳ‬Ġ820 mV (1.64 VPP)ă LVCMOS output of the ໏୲ă৽ 1ǖoutput
8 Վუഗ‫ڦ‬ amplitude is about
DDP ঳ࠓܸჾǈ๼‫؜‬ና
CDCE72010 that results when a 1:4 transformer is used better slew rate around the zero crossing point.
‫ޗ‬ሀྺ 1.6VPPǈժ൐ሞଭ঍֮‫޹ۅ‬ৎገ࣑໏୲߸
཮ 27 ၂๖କᆶࢅ࿮‫ܾڇ‬ट࠶‫( ܔ‬SDP) ଇዖ൧ ߛᅃၵă
Figure
཮ 27 27. Clock signal with different transformer and
փཞՎუഗࢅၥհܾट࠶঳ࠓ‫้ڦ‬ዓ႑ࡽ
clipping-diode configurations
Clipping diode reduces

1:8 Transformer peak-to-peak amplitude
DDP
1.6 VPP
1:8 Transformer
1:4 Transformer SDP
SDP
1:4 Transformer
(No Clipping)

཮ 28 ֪๬փཞᆶᇸत࿮ᇸሺᅮ‫ۉ‬ୟ‫ڦ‬ದዃ
Figure 28. Setup for testing different active- and passive-
gain circuits
491.52 MHz
SPF-5043
LNA
VCXO
10 MHz
CDCE72010
Clock-Source
Generator fS = 122.88 MHz
Transformer
10-MHz Clipping
Reference Diodes
Signal-Source f IN ADS54RF63
Generator ADS5483
SNR measurements with the same value for fS but with an fIN of 100 MHz.
An investigation was conducted to see whether the ADC’s The following different parameters were examined:
SNR ֪ଉ ൩ॠֱူଚ߳ၜ֖ຕǖ
Y Use of an LNA to boost the output voltage and slew rate
aperture degradation due to the external clock’s slew-rate
‫ܔ‬ᇀྔև้ዓገ࣑໏୲၌዆ᆅഐ‫ڦ‬
limitation ADC ੥০Ⴀీူই
could be improved. Different configurations of the
噝๑ᆩᅃ߲ CDCE72010
LNA ሺे CDCE72010 ‫ڦ‬๼‫ۉ؜‬უࢅገ࣑
๟‫ޏ‬੗ᅜ߀฀ǈට்ሼঢ়ፔࡗჺ৯ă࿢்‫ܔ‬๑ᆩืუ
using step-up transformers, an SPF-5043 LNA, and clip- Y Step-up
໏୲ transformers with ratios of 1:1, 4:1, 8:1, and
ping diodes SPF-5043
ՎუഗǄ were testedLNAto maximize the ADC’s SNR when
ǅ‫ڦ‬փཞ঳ࠓࢅၥհܾट࠶‫ۼ‬ 16:1 (Coilcraft WBC series and Mini-Circuits ADT series)
a realistic clocking solution such as the CDCE72010 was 噝 1 ǖ 1HSMS-2812
Y Avago’s Ă 4 ǖ 1 Ăclipping
8 ǖ 1 ࢅdiodes—either
1 6 ǖ 1 Բ ‫ ڦ‬SDPs
ื უ or
Վუഗ
ፔକ֪๬ǈణ‫ڦ‬๟ሞ๑ᆩ၄ํ้ዓ঴ਦ‫ݛ‬ӄǄ૩සǖ ǄCoilcraft WBC
used (see Figure 28) rather than a low-jitter clock-source back-to-back DDPsဣଚࢅ Mini-Circuits
in anti-parallel ADTဣଚǅ
configuration
CDCE72010 ‫ڪ‬ǅܸ‫گݥ‬۶‫้ۯ‬ዓᇸิ‫ׯ‬ഗ้ǈፌ‫ࣅٷ‬
generator.
ADC ‫ ڦ‬SNRǈස཮
As highlighted in Part28 ໯๖ă
2 of this article series, the filtered
噝Avagoࠅິfor
Measurements ADS54RF63ၥհܾट࠶Ċ੗ᅜྺొೝႜದ
HSMS-2812
LVCMOS output of the CDCE72010 has about 90 fs of Theዃ‫ڦ‬ ईኁԝ੍ԝDDP
SDPconfiguration
default ă ADS54RF63 evaluation
for the
ኟ සjitter,
ሞ Ԩwhileဣ ଚthe ࿔clock-source
ቤ ‫ ڼ‬2 ևgenerator‫ݴ‬ዐ໯ഽ hasۙonly
‫ڦ‬ఫᄣǈ module (ADS54RF63EVM) used a Coilcraft WBC4-1 step-
clock ADS54RF63 ֪ଉ
about 35 fs. Although the clock-jitter difference prevents up transformer, and the baseline SNR was about 60.7 dBFS
CDCE72010 ‫୳ڦ‬հ LVCMOS ๼‫؜‬ਏᆶሀ 90 fs ‫้ڦ‬ ADS54RF63
when ೠࠚӱ
the low-jitter (ADS54RF63EVM)
clock-source generator was ‫ڦ‬ఐණದዃ๑
used. If
the CDCE72010 from ever achieving the same ă৑࠶ኄዖ้
ዓ۶‫ۯ‬ǈ้ܸዓᇸิ‫ׯ‬ഗඐৈᆶሀ 35 fs SNR as theᆩᅃ߲
CDCE72010 withWBC4-1
Coilcraft ืუՎუഗǈ൐ሞ๑ᆩ‫گ‬۶
the LVCMOS output was used as the
when the clock-source generator is used, the goal was to
ዓ۶‫ֶۯ‬ᅴඟ CDCE72010 ࿮݆‫ڟٳ‬๑ᆩ้ዓᇸิ‫ׯ‬ clock source instead, the SNR
‫้ۯ‬ዓᇸิ‫ׯ‬ഗ้एጚ dropped
SNR ሀྺto60.757.8 dBFS
dBFS.ăසࡕ
find a configuration to reduce the resulting SNR gap as
ഗ้ᅃᄣ‫ڦ‬
much as possible.SNRTheǈ‫ڍ‬࿢்‫ڦ‬ణ‫ڦ‬๟ቴ‫ڟ‬ᅃዖీࠕፌ‫ٷ‬
ADS54RF63 ADC was used with a However, with only about 90 fs of clock jitter, an SNR
LVCMOS ๼‫ ڦ؜‬CDCE72010 ᆩፕ้ዓᇸǈሶ SNR ই
better than about 60 dBFS should theoretically be attain-
ࣅ‫ں‬໫ၭኄዖ
sampling frequency (fS)ֶ‫ڦ‬ದዃ঳ࠓă
SNR of 122.88 MSPS and an input fre-ADC
ADS54RF63 ዁ so
57.8 dBFS ă‫ڍ‬๟ǈ้ዓ۶‫ۯ‬ৈሀྺ fs ้ǈ૙ஃ
quency able, there was room for at least a 2.2-dB 90
improvement.
߾ፕሞ(fIN ) of 1.0 MSPS
122.88 GHz. The ADS5483 ADC
֑ᄣೕ୲Ǆ Sf ǅ was
ࢅ also
1.0 used,
GHz ๼ ฉᆌ޿੗ᅜइ‫ ڥ‬60 dBFS ᅜฉ‫ ڦ‬SNRăᅺُǈ዁ณᆶ
෇ೕ୲ Ǆ f INǅ ူă ADS5483 ADC ‫ ڦ‬fS ၎ཞǈ‫ ڍ‬f IN 2.2-dB ‫ߛ༵ڦ‬੣क़ă
ྺ 100 MHz ă

཮ 29 29.
Figure fS =Measured SNR ࢅ
122.88 MSPS fIN = 1 GHz
of different ้๑ᆩ ADS54RF63
clock-input ‫ڦ‬փ using ADS54RF63
configurations
ཞ้ዓ๼෇঳ࠓ‫ڥ֪ڦ‬
with fS = 122.88 MSPS and
SNRfIN = 1 GHz
62
Default EVM
61 Configuration
60
59
SNR (dBFS)
58
57
56
Clock-Source Generator + BPF
55 CDCE72010 + BPF
CDCE72010 + SPF-5043 LNA + BPF
54
— DDP — SDP DDP SDP DDP SDP DDP
WBC1-1 WBC1-1 WBC4-1 WBC4-1 WBC4-1 WBC8-1 WBC8-1 WBC16-1 WBC16-1
཮ 29 ၂๖କփཞ‫ڦ‬
Figure 29 shows the EVM ้ዓ๼෇ದ
different EVM
ዃᅜत ‫ڥ֪ڦ‬along ኵă ཮ 30 փཞ้ዓᇸࢅၥհܾट࠶঳ࠓ‫ڦ‬๼෇հႚ
Figure 30. Input waveforms with different clock-source and
ADS54RF63
clock-input configurations SNRwith clipping-diode configurations
the measured SNR values of the
࿢்੗ᅜੂ‫ڟ‬ǈ૧ᆩఐණ‫ڦ‬ WBC4-1
ืADS54RF63.
უ Վ უ ഗ ǈIt‫ڇ‬ can
๟beၥ seen
հ ܾthat
ट ࠶theࡻၟ
clipping diodes alone seemed to
৽ᅙ߀฀କ
improve theSNR ǈܸሺे SPF-5043
SNR with the default Clock-Source CDCE72010 + LNA
LNA ᅜࢫ߸๟ट‫ߛ༵ںٷ‬କ
WBC4-1 step-up transformer,SNR ă‫ڇ‬
while Generator WBC4-1
WBC4-1 CDCE72010 + LNA DDP
ܾट࠶‫ܔ‬ā
the addition of
(SDP)theದዃᇑ
SPF-5043WBC4-1 Վ
LNA WBC4-1
provided a big boost
უഗࢅ LNA ᅃഐǈॽ SNR ༵ߛ‫ڟ‬ሀ in SNR. Using SDP
ADC Clock Input (500 mV/div)
the single-diode-pair (SDP) configu-

60.4 dBFSǈन༵ߛକ 2.6-dBƽ‫كڇ‬
ration along with the WBC4-1 trans-
‫ڦ‬࿮ᇸ঴ਦ‫ݛ‬ӄǈ๑ᆩ
former and the LNA improved WBC8-1 theՎუ
ഗࢅᅃ߲ Ǆுᆶ
SDP 60.4 dBFS,
SNR to about ǅǈ‫ڟڥ‬ሀ
LNAwhich was a
2.6-dB
59.5 improvement!
dBFS ‫ ڦ‬SNRǈ‫׉ݥ‬থৎᇀ Using a purely60-
1
passive
dBFS ణՔăsolution, the WBC8-1 trans-
former with an SDP and no LNA,
཮yielded an SNR of about 59.5 dBFS,
30 ၂๖କփཞದዃׂิ‫้ڦ‬ዓ๼ CDCE72010
very close to the 60-dBFS target. CDCE72010 WBC4-1
෇հႚ‫ܔڦ‬Բ൧઄ă‫گ‬۶‫้ۯ‬ዓᇸิ WBC4-1 SDP
Figure 30 shows a comparison of (No Clipping)
‫ׯ‬ഗᇑ ืუՎუഗᅃഐǈ༵
WBC4-1waveforms
the clock-input that
ࠃ‫ڦߛ׉ݥ‬ገ࣑໏୲ă཮ 30 ՗௽ǈ
occurred with different configurations.
The low-jitter‫୳ڦ‬հ๼‫؜‬ਏᆶ߸ၭ‫ڦ‬
CDCE72010 clock-source generator
combined with the WBC4-1 step-up
‫ރڟރ‬ና‫ޗ‬ǈ‫ټ‬ઠ߸‫ڦگ‬ገ࣑໏୲ǈ
transformer provided a very large
ܸٗ‫ܔ‬ ADC
slew rate.
‫ڦ‬੥০۶‫ิׂۯ‬փ૧ᆖ
Figure 30 shows that the Time (2 ns/div)
ၚăߴ޿ದዃሺे SDP
filtered output of the ຼࢭ੗ᅜฎฎ
CDCE72010 had
10

༵ߛଭ঍֮‫޹ۅ‬ৎ‫ڦ‬ገ࣑໏୲ǈ՗၄‫ڦߛ߸؜‬
a smaller peak-to-peak amplitude and thus a slowerSNR slew Ⴀ ‫ت‬ă‫أ‬ ADT4-1WT
The measured SNRᅜྔምሺे LNA
values of the ǈॽ SNR
ADS5483 ༵ߛ‫ڟ‬ሀ
with the
rate, which negatively impacted
ీăྺ CDCE72010 ๼‫؜‬ሺेߛሺᅮ LNAǈࣷၠၥհܾ the ADC’s aperture jitter. various EVM clock-input configurations
77.8 dBFSă࿢்࣏ᆌ޿ጀᅪǈࢅ࿢்໯ᇨऺ‫ڦ‬ᅃᄣǈ߸ are illustrated in
Adding the SDP to that configuration seemed to slightly Figure 31. Adding the SDP
‫้ڦگ‬ዓና‫ޗ‬ǄWBC1-1ǅट‫ںٷ‬ই‫گ‬କ SNRă to the ADT4-1WT transformer
ट࠶݀ໃ߸ߛገ࣑໏୲‫ٷڦ‬႑ࡽăኄᄣ‫ڞ‬ዂ߸े੺໏‫ں‬
improve the slew rate around the zero crossing point, provided enough boost to the slew rate for the SNR with
ٗଭ঍֮‫ۅ‬ሂദࡗඁǈഄ‫ࡗݒ‬ઠᆼ৊ᅃօ߀฀କ ADC‫ڦ‬
which also manifested itself as improved SNR performance. the CDCE72010 to improve by almost 1 dB to the 77.6-
঳ஃ
੥০۶‫ۯ‬ăሞଭ঍֮‫ۅ‬ᅜമǈມܾट࠶‫ܔ‬
Adding the high-gain LNA to the CDCE72010 outputದዃຼ
(DDP) sent dBFS target. A larger step-up ratio didn’t seem to add any
ࢭ૬ਗ਼৽ඟገ࣑໏୲‫ڟڥ‬କᅃ‫߀ۅ‬฀ă‫ڍ‬๟ǈ཮
a much larger signal with a much larger slew rate to the 30 ཞ ኟස࿢்ሞ‫ڼ‬ 1 և‫ڼࢅݴ‬
further benefit. Adding 2 և‫ݴ‬࿔ቤዐ௮ຎ‫ڦ‬ఫᄣǈ
the LNA in addition to the
clipping diodes. This resulted
้ᄺ՗௽ǈසࡕሞுᆶ LNA in an even fasterCDCE72010
‫ڦ‬൧઄ူ๑ᆩ transition ADC ੥০۶‫ۯ‬ժ‫ݥ‬๟ࠦۨփՎ‫ڦ‬ǈܸ๟ൽਦᇀ้ዓ๼෇
ADT4-1WT boosted the SNR to about 77.8 dBFS. It should
through the zero crossing point, which in turn further be noted as well that a lower clock amplitude (WBC1-1)
ገ࣑໏୲ăᄲၙ৑੗ీ‫ں‬ፌၭࣅ้ዓ۶‫ۯ‬ǈ‫ټ‬ཚ୳հഗ
ࢅ WBC4-1 Վუഗǈ๼‫ۉ؜‬უ੗ీࣷ໿‫گ‬ǈᅜ዁ᇀփ
improved the aperture jitter of the ADC. The dual-diode- significantly degraded the SNR, as expected.
๟ՂႴ‫ڦ‬ǈ‫ڍ‬໲ᆼࣷ୳ۖߛ঩ၿհǈܸٗই‫้گ‬ዓ‫ڦ‬ገ
ీྜඇ‫݀ة‬ၥհ๚ॲă཮ 29 ໯๖֪ଉ঳ࡕ՗௽ǈ๑ᆩ
pair (DDP) configuration seemed to improve the slew rate
WBC8-1 ืუՎუഗࢅ
immediately इ‫ڥ‬କ߸ࡻ‫ڦ‬
DDPcrossing
before the zero Ⴀీă
SNRbit.
point a little Conclusion
࣑໏୲ăԨ࿔ྺ౞঻ถକᅃၵ‫݆ݛ‬ǈঞ౞සࢆ༵ߛ၄ᆶ
However, Figure 30 also shows that if the CDCE72010 ‫ټ‬ཚ୳հഗ้ዓ঴ਦ‫ݛ‬ӄ‫ڦ‬ገ࣑໏୲ǈܸٗॽ
As ADC ‫ڦ‬
explained in Parts 1 and 2 of this article series, the
with the ֪ଉ
ADS5483 WBC4-1 transformer were used without the LNA, ADC’s aperture jitter is not
SNR ༵ืຕ‫ݴ‬ԞăSNR ֪ଉ՗௽ǈ้ዓ႑ࡽገ࣑໏୲༵ fixed but dependent on the
the output voltage might be too low to fully trigger the clock-input slew rate. While the bandpass filter is necessary
ADS5483EVM ሞ้ዓ๼෇‫܋‬๑ᆩକᅃ߲ Mini-Circuits ߛᅜࢫǈADC ‫ ڦ‬SNR ‫ڟٳ‬କߴ้ۨዓ۶‫ۯ‬ଉཉॲူ࿢
clipping event. The measurement results in Figure 29 to minimize the clock jitter as much as possible, it also
ADT4-1WT ืუՎუഗă‫گ‬۶‫้ۯ‬ዓᇸ‫ڦ‬एጚ SNR ྺ ்ᇨऺ‫ڦ‬
reduces SNR
the ă slew rate by filtering out the higher-
clock’s
show better SNR performance with the WBC8-1 step-up
78.2 ǈܸ
dBFS and CDCE72010
transformer DDPs. ๼‫ ڦڟڥ؜‬SNR ሀྺ 76.8 order harmonics. This article has shown practical ways
dBFS ă90 fs ፑᆸ้ዓ۶‫ڦۯ‬ CDCE72010ǈᆌ޿༵ࠃሀ (using either active or passive gain) to improve the slew
Measurements for ADS5483
‫ڦ‬ ǈन༵ߛକৎ rate of an existing clocking solution with a bandpass filter,
77.6 dBFS
The 1 dBă
SNR employed a Mini-Circuits
ADS5483EVM ADT4-1WT
thus improving the ADC’s SNR by several decibels. The
step-up transformer on the clock input. The baseline SNR
཮ 31a ၂๖କ๑ᆩ߳ዖ EVMwas้ዓ๼෇ದዃ้ ADS5483 SNR measurements have shown that improving the slew
with low-jitter clock source measured at 78.2 dBFS,
rate of the clock signal makes the ADC’s SNR match the
while the CDCE72010 output
‫ ڥ֪ڦ‬SNR ኵăྺADT4-1WT Վუഗሺे SDPǈ༵ߛ yielded an SNR of about
predicted SNR for a given amount of clock jitter.
76.8 dBFS. TheCDCE72010
କገ࣑໏୲ǈ CDCE72010‫ڦ‬ with
SNRa clock
༵ߛକৎ jitter1ofdB
about
ǈ‫ڟٳ‬
90 fs should provide an SNR of about 77.6 dBFS, which
77.6-dBFS ణՔኵă߸‫ืڦٷ‬უԲǈຼࢭுᆶ߸‫ڦٷ‬ᆩ
would be an improvement of almost 1 dB.
཮ 31 31.
Figure fS =Measured
122.88 MSPS ࢅ different
SNR of MHz ้๑ᆩ configurations
fIN = 100 clock-input ADS5483 ‫ڦ‬փཞ้ዓ๼෇ದ
using ADS5483
with fS = 122.88
ዃ‫ڥ֪ڦ‬ SNR MSPS and fIN = 100 MHz
78.5
Default EVM
78 Configuration
77.5
77
SNR (dBFS)
76.5
76
75.5
75
Clock-Source Generator + BPF
CDCE72010 + BPF
74.5
CDCE72010 + SPF-5043 LNA + BPF
74
— SDP DDP — SDP DDP — SDP DDP — SDP DDP
WBC1-1 WBC1-1 WBC1-1 ADT4-1 ADT4-1 ADT4-1 WBC8-1 WBC8-1 WBC8-1 WBC16-1 WBC16-1 WBC16-1
11

֖੊࿔၅ ၎࠲ྪበ
References Related Web sites
ස ᇡ କ ঴ Ԩ ࿔ ၎ ࠲ ߸ ‫ ၘ ܠ‬൧ ǈ ৤ ൩ ‫ ݡ‬࿚ w w w. Dataconverter.ti.com
For more information related to this article, you can down- dataconverter.ti.com
ti.com/lit/litnumber Ǆ๑ᆩ TI ࿔ॲՊࡽ༺࣑ྪ኷ዐ‫ڦ‬ Www.ti.com/sc/device/partnumber Ǆᆩ ADS5483 Ă
load an Acrobat® Reader® file at www.ti.com/lit/litnumber www.ti.com/sc/device/partnumber
Đlitnumberđǅǈူሜ Acrobat® Reader® ߭๕࿔ॲǈइ AReplace R F 6 3 ई ኁwith
D S 5 4 partnumber C DADS5483, 10 ༺ ࣑ ྪ ኷
C E 7 2 0 ADS54RF63, ዐ‫ڦ‬
and replace “litnumber” with the TI Lit. # for the or
ൽူଚ֖੊ጨଙă Đpartnumberđǅ
materials listed below. CDCE72010
Document Title
࿔၅Ք༶ TI Lit. # TI࿔၅Պࡽ
1. Thomas Neu, “Clock jitter analyzed in the
1ĂĖ้ዓ۶‫้ۯ‬ᇘ‫ݴ‬ဆǈ‫ڼ‬
time domain, Part 1,” Analog 1և‫ݴ‬ėǈፕኁǖ
Applications Thomas Neu ݀՗ᇀĖఇ
ెᆌᆩሗኾėǄ
Journal (3Q 2010 ౎‫ڼ‬
2010) . . . . . . . .
. . .3. ल‫܈‬਽ǅ . . . . . . . . . . . .slyt379 slyt379
2. Thomas Neu, “Clock jitter analyzed in the
2ĂĖ้ዓ۶‫้ۯ‬ᇘ‫ݴ‬ဆǈ‫ڼ‬
time domain, Part 2,” Analog 2և‫ݴ‬ėǈፕኁǖ
Applications Thomas Neu ݀՗ᇀĖఇ
Journal (4Q
ెᆌᆩሗኾėǄ2010౎‫ڼ‬4ल‫܈‬਽ǅ 2010) . . . . . . . . . . . .
. . . . . . . . . . . .slyt389 slyt389
3. “12-bit, 500-/550-MSPS analog-to-digital
3ĂĖ 12࿋Ă500-/550-MSPS
converters,” ADS5463/54RF63 ఇຕገ࣑ഗėǈ
Data Sheet . .ADS5463/54RF63
. . .slas515
ׂ೗ຫ௽ກ slas515
12 ZHCT137

˚˨ ADC
How ߾ፕᇱ૙ǈ‫ڼ‬
delta-sigma 1 և‫ݴ‬work, Part 1
ADCs
ፕኁǖ Bonnie
By Bonnie Bakerǈ
Baker
‫ڤ‬ዝᅏഗ (TI) ႑ࡽྜኝႠ߾‫ײ‬฾
Signal Integrity Engineer
໚඗ఇెरຍᅙঢ়ዷ‫ڞ‬႑ࡽ‫ت‬૙‫ٳ׊‬ຕ౎ኮ৳ǈ‫ڍ‬ຕ
Analog techniques have dominated signal processing for The '6 1converter’s
հഗă཮ ໯๖‫ాڦ‬և internal cells are the '6
ΔΣ ۙ዆ഗᅜ‫ڦߛ׉ݥ‬໏୲‫ܔ‬๼෇
primary
years, but digital techniques are slowly encroaching
ጴरຍᄺኟሞॷॷาཪ‫ڟ‬ኄᅃଶᇘă ΔΣ ఇຕገ࣑ഗ into modulator and the digital/decimation
႑ࡽ৊ႜٚ୼֑ᄣǈժገ࣑‫ׯ‬ filter. The internal
1 ࿋ຕ਍ୁăኮࢫǈຕጴ
this domain. The design of delta-sigma ('6) analog-to- '6 modulator shown in Figure 1 coarsely samples the
(ADC) ยऺ‫ݴ຺ڦ‬ኮෙྺຕጴยऺǈ຺‫ݴ‬ኮᅃྺఇెย ؏ᄣ୳հഗ๑ᆩ޿֑ᄣຕ਍ǈॽഄገ࣑ྺߛ‫ݴ‬Ր୲Ă‫گ‬
/input
digital converters (ADCs) is approximately three-quarters signal at a very high rate into a 1-bit stream. The
ऺă၄ሞǈ ΔΣ ADC ๟ሞ੻ೕ୲‫ॽྷݔ‬ఇె႑ࡽٗ
digital and one-quarter analog. '6 ADCs are now ideal for DC ໏ຕጴ‫پ‬ஓă‫ܠٷ‬ຕገ࣑ഗ‫ۼ‬ᆶᅃ߲֑ᄣ໏୲ǈܸ
digital/decimation filter then takes this sampled data and ΔΣ ገ
ገ࣑ྺबቹࢍ႑ࡽ‫ڦ‬૙ၙ჋ስăएԨฉઠຫǈኄၵገ࣑
converting analog signals over a wide range of frequencies, ࣑ഗඐᆶଇ߲֑ᄣ໏୲ĊĊ๼෇֑ᄣ໏୲
converts it into a high-resolution, slower digital ࢅ๼‫؜‬ຕ਍
(fS) code.
from DC to several megahertz. Basically,
ഗ‫ۼ‬ᆯᅃ߲ࡗ֑ᄣۙ዆ഗࢅᅃ߲ຕጴ these converters
/؏ᄣ୳հഗፇ‫ׯ‬ǈ While(fmost
໏୲ D ) ă converters have one sample rate, the '6 con-
consist of an oversampling modulator followed by a digital/
໲்ၹۙ߾ፕׂิߛ‫ݴ‬Ր୲‫ڦ‬ຕ਍ୁ๼‫؜‬ăԨဣଚ࿔ቤ verter has two—the input sampling rate (fS) and the out-
decimation filter that together produce a high-resolution put data
˚˨ ۙ዆ഗ rate (fD).
ॽጮဦჺ৯ ΔΣ ADC
data-stream output. ‫ࢃڦ‬႐և‫ݴ‬ǈ޿࿔ቤࠌ‫ྺݴ‬
This 2 ߲
two-part article will look closely
և‫ݴ‬ă‫ڼ‬ 1 և‫঻ॽݴ‬ถ
at the '6 ADC’s core. PartΔΣ ۙ዆ഗ‫ڦ‬एԨྊ೫঳ࠓࢅᇱ
1 will explore the basic topology ΔΣ '6 modulator
Theۙ዆ഗ๟ ΔΣ ADC ‫ڦ‬႐ሤă໲޶ሴຕጴࣅఇె๼෇႑
૙ǈ‫ڼ‬ of the '6 modulator,
և‫঻ॽݴ‬ถຕጴ
and func2tion / ؏ᄣ୳հഗఇ੷‫ڦ‬एԨྊ೫
and Part 2 will explore The '6 modulator is the heart of the '6 ADC. It is respon-
ࡽࢅ३ณ‫گ‬ೕሯำăሞኄᅃपዐǈ޿ॐࠓํแକᅃዖԥ
the basic topology and function of the digital/decimation
঳ࠓࢅᇱ૙ă sible for digitizing the analog input signal and reducing
‫ྺ׬‬ሯำኝႚ‫ీࠀڦ‬ǈॽ‫گ‬ೕሯำླྀื዁၎࠲ೕ‫ټ‬ᅜྔ
filter module. noise at lower frequencies. In this stage,
‫ߛڦ‬ೕăኟ๟ᆯᇀሯำኝႚࠀీǈ the architecture
ΔΣ ገ࣑ഗ֍‫׉ݥ‬๢ࢇ
˚˨ ገ࣑ഗǖ߁બAn overview implements a function called noise shaping that pushes low-
'6 converters: ᇀ‫گ‬ೕĂߛ৛‫֪܈‬ଉă
frequency noise up to higher frequencies where it is outside
एԨ‫ڦ‬ ΔΣ ገ࣑ഗྺᅃዖ
The rudimentary 1 ࿋֑ᄣဣཥǈഄᆌᆩᇀገ࣑
'6 converter is a 1-bit sampling system. the band of interest. Noise shaping is one of the reasons
ΔΣ ۙ዆ഗ‫ڦ‬๼෇႑ࡽ๟้Վఇె‫ۉ‬უă‫ܔ‬ᇀ߸ራ‫ڦ‬ᅃၵ
ഗ๼෇‫ڦ܋‬ఇె႑ࡽႴᄲ၎‫ܔ‬ড஥ǈణ‫ڦ‬๟ඟገ࣑ഗ
An analog signal applied to the input of the converter needs that '6 converters are well-suited for low-frequency, high-
to be relatively slow so the converter can sample it multiple
ీࠕ‫ܔ‬ഄ৊ႜ‫ْ֑ܠ‬ᄣǈनዸఁ‫֑ࡗڦ‬ᄣरຍăሞ๼‫؜‬ ΔΣ ADC ઠຫǈኄዖ๼෇‫ۉ‬უ႑ࡽዷᄲᆩᇀ
accuracy measurements. AC ႑ࡽ࢔ዘ
times, a technique known as oversampling. The sampling
‫܋‬ǈ֑ᄣ໏୲Բຕጴ঳ࡕ੺ຕӥԠă‫֑߲ڇ‬ᄣደॷે The input signal to the '6 modulator is a time-varying
ᄲ‫ڦ‬ᅼೕᆌᆩă၄ሞǈᆌᆩ‫ڦ‬ዘ‫ۅ‬ᅙঢ়ገၠᅃၵ৛௢ᆌ
rate is hundreds of times faster than the digital results at analog voltage. WithDC
ᆩǈገ࣑໏୲Ԉઔ earlier '6 ADCs, this input-voltage
the႑ࡽăԨ࿔ॽ๑ᆩᅃ߲‫ڇ‬ዜ೺‫ڦ‬ኟ
ओǈժཚࡗຕጴ
the output ports./؏ᄣ୳հഗॽഄᇑഄ໱๼෇႑ࡽ֑ᄣᅃ
Each individual sample is accumulated signal was primarily for audio applications where AC signals
ഐĐ൱ೝ਩đă ၀հઠ৊ႜຫ௽ă
over time and “averaged” with the other input-signal sam- were important. Now that attention has turned to precision
ples through the digital/decimation filter. applications, conversion rates include DC signals. This dis-
ΔΣ ገ࣑ഗ‫ڦ‬ዷᄲాև‫ڇ‬ᇮྺ ΔΣ ۙ዆ഗࢅຕጴ/؏ᄣ୳ cussion will use a single cycle of a sine wave for illustration.
཮ 1 ˚˨
Figure 1. Block ঳ࠓ཮ of '6 ADC
ADC diagram
Sample Rate (fS )

Analog
Input Modulator
fS /fD = Decimation Ratio
Data Rate (fD)
Digital Digital
Filter Decimator
Output
Digital/Decimation Filter
13

཮ 2 ˚˨
Figure signal to the '6 modulator
ۙ዆ഗ‫ڦ‬๼෇႑ࡽ
2. Input
Input Input
Amplitude Magnitude
Time Frequency
(a) Time domain (b) Frequency domain
཮ Figure
2a ၂๖କ ΔΣ ۙ዆ഗ๼෇‫ڦ‬ᅃ߲‫ڇ‬ዜ೺ኟ၀հă޿
2a shows a single cycle of a sine wave for the ഗิ‫پׯ‬՗๼෇‫ۉ‬უ‫ڦ‬ຕኵຕ਍ୁǄُ‫ྺت‬ 1 ࿋ຕ਍
In this manner, the quantizing action of the '6 modulator
input of a '6 modulator. This single cycle
‫ڇ‬ዜ೺‫ۉڦ‬უና‫ޗ‬ໜ้क़Վࣅă཮ 2b ၂๖କ཮
has voltage2a ໯ ୁǅăኄᄣǈ
is produced at1a ࢅ ‫ڦ‬ຕଉԲՍ‫پ‬՗๼෇ఇె‫ۉ‬უăཞ
high0 sample rate that is equal to that of
amplitude that changes with time.
๖้ᇘ႑ࡽ‫ڦ‬ೕᇘ՗๖ă཮ 2b Figure
ዐ‫ڦ‬൸၍཮‫پ‬՗཮2b shows a 2a the system clock. Like all quantizers,
‫ܠٷ‬ຕଉࣅഗփᅃᄣ‫ڦ‬๟ǈ the '6 modulator
ΔΣ ۙ዆ഗԈઔᅃ߲ओ‫ݴ‬ഗǈ
frequency-domain representation of the time-domain produces a stream of
ഄਏᆶॽଉࣅሯำኝႚྺ߸ߛೕ୲‫ڦ‬ፕᆩăᅺُǈۙ዆digital values that represent the
‫૶ڦ‬Ⴤኟ၀հǈժ՗၄ྺᅃཉ኱၍ईኁኧ၍ă
signal in Figure 2a. The curve in Figure 2b represents the voltage of the input, in this case a 1-bit stream. As a result,
ഗ๼‫ڦ܋؜‬ሯำ೷ժ‫ྺݥ‬ೝ኱਩ሌă
continuous
ჺ৯ sine wave in Figure 2a and appears as a the ratio of the number of ones to zeros represents the
ΔΣ ۙ዆ഗ‫݆ݛڦ‬ᆶଇዖĊĊ้ᇘჺ৯Ǆ൩֖९཮
straight line or a spur. input analog voltage. Unlike most quantizers, the '6
3ǅईኁೕᇘჺ৯Ǆ൩֖९཮ ǅă཮ 3 ໯๖้ᇘ঳ࠓ ሞ้ᇘዐǈ‫ܔ‬1࿋ຕఇገ࣑ഗ (DAC) ‫ڦ‬ఇె๼෇‫ۉ‬უࢅ๼
There are two ways to look at4the '6 modulator—in modulator includes an integrator, which has the effect of
཮௮ຎକᅃ঩
the time domain ۙ዆ഗ‫ڦ‬঳ࠓă޿ۙ዆ഗॽఇె๼෇
ΔΣ(Figure 3) or in the frequency domain ‫؜‬൱ྲ‫ݴ‬ǈ‫ڟڥ‬ X2 ఇె‫ۉ‬უă޿‫ۉ‬უԥໃ዁ओ‫ݴ‬ഗǈ‫ڥ‬
shaping the quantization noise to higher frequencies.
႑ࡽገ࣑ྺᅃ߲ߛ໏Ă‫ڇ‬࿋Ăۙ዆ஞհă߸ዘᄲ‫ڦ‬๟ǈ
(Figure 4). The time-domain block diagram in Figure 3 ‫޶ڟ‬ईኁኟၠ๼‫؜‬ă
Consequently, the noise X3 ‫ڦ‬႑ࡽ‫ݛ‬ၠࢅၽ୲ൽਦᇀ
spectrum at the output of the X2 ‫ۉ‬უ
཮shows the mechanics of a first-order '6 modulator. The
4 ໯๖ೕ୲‫ݴ‬ဆ՗௽କۙ዆ഗසࢆᆖၚဣཥሯำǈᅜ modulator is not Xflat.
‫ٷࢅࡽޙڦ‬ၭă 3 ‫ۉ‬უ‫ڪ‬ᇀԲডഗएጚ‫ۉ‬უ้ǈԲডഗ
modulator converts the analog input signal to a high-speed, In the time domain, the analog input voltage and the out-
๼‫؜‬ᆯ޶ገྺኟǈईኁᆯኟገྺ޶ǈਏ༹ൽਦᇀഄ‫؛‬๔
तසࢆӻዺׂิ߸ߛ‫ݴ‬Ր୲‫ڦ‬঳ࡕă
single-bit, modulated pulse wave. More importantly, the put of the 1-bit digital-to-analog converter (DAC) are differ-
frequency analysis in Figure 4 shows how the modulator
ጒༀăԲডഗ‫ڦ‬๼‫؜‬ኵ X4 ࣮‫ڟ‬
entiated, providing an analog 1࿋
voltage at DAC
ዐǈཞ้๼‫؜‬
x2. This voltage is
཮ 3 ໯๖ ΔΣ ۙ዆ഗइ‫ٷڥ‬ଉ๼෇႑ࡽ‫֑ڦ‬ᄣǈิ‫ ׯ‬1 ‫ڟ‬ຕጴ୳հഗप
affects the noise in the system and facilitates the produc- yiăԲডഗ๼‫ۉߛٗ؜‬ೝገྺ‫ۉگ‬ೝई
presented to the integrator, whose output progresses in a
࿋‫پ‬ஓຕ਍ୁăဣཥ้ዓᇑۙ዆ഗ‫ڦ‬
tion of a higher-resolution result. 1 ࿋Բডഗᅃഐํ ኁٗ‫ۉگ‬ೝገྺߛ‫ۉ‬ೝ้ǈ ࿋ DAC
negative or positive direction.1 The slope ཚࡗ߀Վֶ‫ٷݣۯ‬
and direction of
แ֑ᄣ໏‫܈‬ fSă
The '6 modulator shown in Figure 3 acquires many the signal at x
ഗ‫ڦ‬ఇె๼‫ۉ؜‬უઠፔ‫؜‬ၚᆌăኄᄣՍሞis dependent on the sign andXmagnitude of
2 ႚ‫ׯ‬କփཞ
3
samples of the input signal to produce a stream of 1-bit the voltage at x2. At the time the voltage at x3 equals the
ኄᄣǈՍሞᅃ߲ᇑဣཥ้ዓ၎‫֑ߛڦڪ‬ᄣ໏୲ူׂิ ‫ڦ‬๼‫ۉ؜‬უǈ‫ڞ‬ዂओ‫ݴ‬ഗ‫ݛݒ‬ၠሏႜă޿้ᇘ๼‫؜‬႑ࡽ
codes. The system clock implements the sampling speed, comparator reference voltage, the output of the comparator
ۙ዆ഗ‫ڦ‬ଉࣅႜྺăཞ໯ᆶଉࣅഗᅃᄣǈ ๟֑ᄣ໏୲ ) ူ๼෇႑ࡽ‫ڦ‬ஞհ՗๖ăැ‫ܔ‬๼‫؜‬ஞ؋
switches from(fSnegative
fS, in
ΔΣ ΔΣ ۙ዆
conjunction with the modulator’s 1-bit comparator. to positive, or positive to negative,
‫ز‬൱ೝ਩ǈഄ‫ڪ‬ᇀ๼෇႑ࡽ‫ڦ‬ኵă
཮ 3 ้ᇘዐ‫ڦ‬ᅃ঩
Figure '6 modulator
3. First-order˚˨ ۙ዆ഗ in the time domain
Difference fS
Analog Amplifier Integrator
Input xi ei
+ x2 x3 Output to
+ x4 yi Digital Filter
–
–
VREF Comparator
(1-Bit ADC)
x4
1- Bit DAC
yixi – 1eiei – 1
14

཮ 4 ೕᇘዐ‫ڦ‬ᅃ঩
Figure ˚˨
4. First-order '6 ۙ዆ഗ
modulator in the frequency domain
Sigma
ei
Delta (Integrator)
+ 1-Sample 1-Bit
xi Delay
yi
ADC
Analog – Output to
Input Digital Filter
Magnitude Signal
1-Bit
DAC
Frequency
fS
Quantization
Noise
཮ 3 ໯๖૗ො้क़঳ࠓ཮ᄺ՗௽କኄዖ้ᇘ‫د‬๼ࡧຕă
depending on its original state. The output value of the ঩ۙ዆ഗǈഄᆛᆶଇ߲ओ‫ݴ‬ഗă޿ܾ঩ۙ዆ഗਉ૩ዐǈ
Figure 4 also shows that the combination of the integra-
comparator,
้ᇘዐǈ 1 ࿋x4,ADCis clocked back into the 1-bit DAC,
ॽ႑ࡽຕጴࣅ‫ׯ‬֢ٚ‫ڦ‬ as well
1 ࿋๼‫پ؜‬ ሯำၜփৈৈൽਦᇀമ௬ᅃ߲ဃֶǈܸ๟ൽਦᇀമ௬ଇ
tor and sampling strategy implements a noise-shaping filter
as clocked out to the
ஓǈׂܸٗิገ࣑ഗଉࣅሯำăۙ዆ഗ‫ڦ‬๼‫ڪ؜‬ᇀ๼෇ digital filter stage, yi. At the time that on the digital output code. In the frequency domain, the
߲ဃֶă
the output of the comparator switches from high to low or time-domain output pulses appear as the input signal
ेଉࣅሯำ
vice versa, theei 1-bit ă޿ࠅ๕՗௽ǈଉࣅሯำ๟‫ړ‬മଉࣅ
– ei – 1DAC responds by changing the analog (or spur) and shaped noise. The noise characteristics in
ܾ঩ईኁ‫ܠ‬঩ۙ዆ഗ٪ሞ‫ڦ‬ᅃၵඍ‫ۅ‬ԈઔࡗᇀްሗĂ‫ܠ‬
ဃֶ
output ) ࢅኮമଉࣅဃֶ
(eivoltage ‫ֶڦ‬ă཮This
(ei – 1)amplifier.
of the difference 4 ၂๖କኄዖଉ
creates a Figure 4 are the key to understanding the modulator’s
ዘთ࣍ᅜतยऺઓవ‫ڪ‬ă‫ڍ‬๟ǈ‫ܠٷ‬ຕΔΣۙ዆ഗ਩ྺߛ
ࣅሯำ‫ڦ‬ೕ୲࿋ዃă
different output voltage at x2, causing the integrator to pro- frequency operation and the ability of the '6 ADC to
gress in the opposite direction. This time-domain output ঩ǈස཮ 5 ໯๖ă૩සǈ
achieve such TI ΔΣ ገ࣑ഗ৽Ԉઔକܾ‫ୃڟ‬঩
high resolution.
཮ 4 ࣏՗௽ፇࢇ๑ᆩओ‫ݴ‬ഗࢅ֑ᄣ֧୼ǈํ၄କ‫ܔ‬ຕጴ
signal is a pulse-wave representation of the input signal at ۙ዆ഗă
The noise in the modulator is moved out to higher fre-
the sampling rate (fS). If the output pulse train is averaged,
๼‫پ؜‬ஓ‫ڦ‬ሯำኝႚ୳հăሞೕᇘዐǈ้ᇘ๼‫؜‬ஞ؋՗ quencies. Figure 4 shows that the quantization noise for a
it equals the value of the input signal. ၎Բ‫گ‬঩ۙ዆ഗǈ‫ܠ‬঩ۙ዆ഗ੗ॽଉࣅሯำኝႚ዁߸ߛ
first-order modulator starts low at zero hertz, rises rapidly,
၄ྺ๼෇႑ࡽǄनॖ‫ރ‬ǅࢅঢ়ࡗኝႚ‫ڦ‬ሯำă཮ 4 ໯๖
The discrete-time block diagram in Figure 3 also shows ‫ڦ‬ೕ୲ă཮ 6 ዐǈೕ୲
and then levels fS ࿋ዃፌߛ‫ڦ‬ఫߵ၍ཉ՗௽ෙ঩
off at a maximum value at the modulator’s
ሯำ༬Ⴀ๟૙঴ۙ዆ഗೕ୲๑ᆩࢅ
the time-domain transfer function. In theΔΣ time ీࠕ‫ڟٳ‬ኄ
ADCdomain, the sampling frequency (fS ).
ۙ዆ഗ‫ڦ‬ሯำၚᆌă൩ጀᅪǈሞഄ f S ֑ᄣೕ୲ူǈ޿ۙ
ዖߛ‫ݴ‬Ր୲ᇱᅺ‫࠲ڦ‬॰ă
1-bit ADC digitizes the signal to a coarse, 1-bit output code Using a circuit that integrates twice instead of just once
዆ഗ‫ڦ‬ኝ߲๼‫ۼײࡗ؜‬ᆶ‫ٷ‬ଉሯำă‫ڍ‬๟ǈሞ߸‫گ‬ೕ୲
that produces the quantization noise of the converter. The is a great way to lower the modulator’s in-band quantization
ۙ዆ഗሯำԥᅎ‫؜‬዁߸ߛ‫ڦ‬ೕ୲ă཮ 4 ՗௽ǈᅃ঩ۙ዆
output of the modulator is equal to the input plus the ူǈन fD ᅜူࢅ๼෇႑ࡽॖ‫޹ރ‬ৎǈෙ঩ۙ዆ഗඐ‫׉ݥ‬
noise. Figure 5 shows a 1-bit, second-order modulator that
ഗ‫ڦ‬ଉࣅሯำਸ๔ᇀଭࢍጦǈ඗ࢫტ໏ืߛǈፌዕሞۙ
quantization noise, ei – ei – 1. As this formula shows, the Ҿৢă ๟ຕጴ/؏ᄣ୳հഗ‫ڦ‬ገ࣑ೕ୲ăԨဣଚ࿔ቤ‫ڦ‬
has twofDintegrators instead of one. With this second-order
quantization noise
዆ഗ֑ᄣೕ୲ is the difference between the current
(fS) ‫ڟٳ‬ፌ‫ٷ‬ኵժԍ‫׼‬ೝ࿘ጒༀă modulator
‫ڼ‬ 2 example,
և‫ॽݴ‬༪ஃසࢆ჋ስ the noise term depends on not just
fD ‫ڦ‬ኵă
quantization error (ei ) and the previous quantization error the previous error but the previous two errors.
(ei – 1 ). Figure 4 illustrates the frequency location of this
๑ᆩᅃ߲ଇْओ‫ݥܸݴ‬ᅃْ‫ڦ‬ओ‫ۉݴ‬ୟǈ๟३ณۙ዆ഗ Some of the disadvantages of the second- or multi-order
quantization
ೕ‫ాټ‬ଉࣅሯำ‫݆ݛࡻ࢔ڦ‬ă཮ noise. modulators include increased complexity, multiple loops,
5 ၂๖କᅃ߲ 1 ࿋Ăܾ
཮ 5 ܾ঩
Figure diagram of a second-order '6 modulator
˚˨ ۙ዆ഗ঳ࠓ཮
5. Block
Integrator Integrator 1- Bit

ADC OUT
IN + +
xi
yi
– –
ei
1- Bit
DAC
yixi – 1eiei – 1ei – 2
15

and increased design difficulty. However, most '6 modula-

ۙ዆ഗǖࠤ๚֍঄କᅃӷ ၎࠲ྪበ
in the final output of the converter. Part 2 of this article
tors are higher-order, like the one in Figure 5. For instance, series will discuss how to get rid of this noise with a low-
ΔΣ ADC ‫ۙڦ‬዆ഗ‫ںࠀׯ‬ሞገ࣑ࡗ‫ײ‬ዐ३ณକ‫گ‬ೕሯ Dataconverter.ti.com
Texas Instruments '6 converters include second- through pass digital/decimation filter.
ำă‫ڍ‬๟ǈߛೕሯำඐᆼ‫ׯ‬କ࿚༶ǈ໲๟ገ࣑ഗፌዕ๼
sixth-order modulators.
‫؜‬໯փႴᄲ‫ڦ‬ăဣଚ࿔ቤ‫ڼڦ‬
Multi-order modulators shape 2theև‫ॽݴ‬༪ஃසࢆ๑ᆩ‫گ‬
quantization noise to References
ཚຕጴ /؏ᄣ୳հഗઠ‫ت‬૙ኄዖሯำă
even higher frequencies than do the lower-order modula- 1. R. Jacob Baker, CMOS: Mixed-Signal Circuit Design,
tors. In Figure 6, the highest line at the frequency fS Vol. II. John Wiley & Sons, 2002.
֖੊࿔၅
shows the third-order modulator’s noise response. Note 2. Texas Instruments, Nuts and Bolts of the Delta-Sigma
that this modulator’s output is very noisy all the way out at Video Tutorial [Online]. Available: http://focus.ti.com/
1 ĂĖ CMOS ǖंೕ႑ࡽ‫ۉ‬ୟยऺėǈፕኁǖ R. Jacob docs/training/catalog/events/event.jhtml?sku=
its sampling frequency of fS. However, down at lower fre-
Baker ǈሀࡪ
quencies, sྰ૧ࡔा‫؜‬Ӳࠅິǈ
below 2002 ౎ă
fD and near the input-signal spur, the WEB408001
third-order modulator is very quiet. fD is the conversion
Ă TI ǈĖ ΔΣ ए‫إ‬๫ೕঞ‫ײ‬ėǄሞ၍ǅǈྪ኷ǖ http://
2frequency Related Web site
of the digital/decimation filter. Selecting a value
focus.ti.com/docs/training/catalog/events/event.
for fD will be discussed in Part 2 of this article series. dataconverter.ti.com
jhtml?sku= WEB408001
Modulators: The first half of the story
The modulator of the '6 ADC successfully reduces low-
frequency noise during the conversion process. However,
the high-frequency noise is a problem and is undesirable
཮ 6 ˚˨
Figure 6. '6ۙ዆ഗሯำኝႚᇑ֑ᄣೕ୲ fS ࿋ዃۙ዆঩
modulator noise shaping versus modulator order
ຕ‫࠲ڦ‬ဣ
with a sampling frequency of fS
Third-Order
Modulator
Output Noise
fD Second-Order
Modulator
First-Order
Modulator
fD fS
Frequency
ZHCT138
16

Texas Instruments Incorporated Power Management
ᆩ໿ᄞీ‫׾ۉ‬ӱྺืუྊ೫঳ࠓ‫׾ۉ‬؊‫ۉ‬ഗࠃ‫ۉ‬
A boost-topology battery charger powered
from a solar panel
ፕኁǖ
By JeffJeff Falin
Falin, Power Applications Engineer,
‫ڤ‬ዝᅏഗ (TI) ‫ۉ‬ᇸᆌᆩ߾‫ײ‬฾ࢅ Wang Li ‫ۉ׾ۉ‬ᇸᆌᆩ߾‫ײ‬฾
and Wang Li, Battery Power Applications Engineer
ᆅჾ
Introduction ཮ 1 ໿ᄞీ‫׾ۉ‬؊‫ۉ‬ഗ঳ࠓ཮
Figure 1. Block diagram of solar-powered battery charger
ৎ౎ઠǈ‫׾ۉ‬໿ᄞీ؊‫ۉ‬Վ‫ୁ׉ݥڥ‬ႜă
Solar charging of batteries has recently
ᅃ੷໿ᄞీ‫ۆڦ׾ۉ‬႙‫ۉ‬უྺ
become 0.7V ăႹ
very popular. A solar cell’s typical
voltage is 0.7 V. Many panels
‫ܠ‬໿ᄞీ‫׾ۉ‬ӱ‫ۼ‬ᆶ 8 have
੷‫׾ۉ૴ز‬ǈᅺُ eight cells Solar
VSP
in series and are therefore
ፌ‫ ิׂࠕీܠ‬5.6V ‫ۉڦ‬უă૧ᆩইუ؊ capable of produc- Panel
ing 5.6 V at most. This voltage is adequate for RSNS VBAT
‫ۉ‬ഗǈኄᅃ‫ۉ‬უፁᅜॽᅃ੷‫༹ڇ‬ᯜ૗ጱ‫ۉ‬
charging a single Li-ion battery, such as that VCC GDRV HI Power
‫׾‬Ǆ૩සǖ๮ऐ‫ڪ׾ۉ‬ǅ؊‫ۉ‬዁
used in cell phones, to 4.2 V with a buck or ă
4.2V GDRVLO Stage
+
‫ڍ‬๟ǈ၎ཞ‫ڦ‬໿ᄞీ‫׾ۉ‬ӱᆩᇀྺ‫༹ܠ‬ᯜ
step-down charger. However, using the same CIN CBAT –
panel to charge a multicell Li-ion battery like Buck Charger
૗ጱ‫׾ۉ‬ፇǄ૩සǖԴऻԨ‫ۉ‬స‫׾ۉڦ‬ǅ Controller
that used in laptop computers requires a
؊‫้ۉ‬ǈሶᄲ൱๑ᆩᅃ߲ืუ؊‫ۉ‬ഗăణ
boost or step-up charger. Most chargers VRSNS+ RTFB
മǈ๨‫ׇ‬ฉၨ๳‫ܠٷڦ‬ຕ؊‫ۉ‬ഗ਩एᇀই
currently on the market are based on a buck CFLTR
უྊ೫঳ࠓǈᅺُᄲ൱ഄ๼෇‫ۉ‬უߛᇀ‫ۉ‬
or step-down topology and therefore require VRSNS–
RBFB
their input voltage to be higher than the
‫ྜ׾‬ඇ؊‫ۉۉ‬უă‫ڍ‬๟ǈ‫ܔ‬ইუ‫׾ۉ‬؊‫ۉ‬ VREF FB
battery’s fully charged voltage. However, it is
ഗ৊ႜᅃၵ߀৊ǈՍ੗ᅜඟഄ‫ྺׯ‬ᅃዖื
possible to modify a buck battery charger into
უ‫׾ۉ‬؊‫ۉ‬ഗăԨ࿔ॽ঻ถํแኄዖ߀৊
a boost or step-up battery charger. This article
‫ײࡗڦ‬ዐႴᄲጀᅪ‫ڦ‬ᅃၵዘᄲ࿚༶ǈժ༵ࠃᅃ߲ยऺํ
identifies the key concerns in implementing such
a૩ă޿ยऺํ૩๑ᆩକ
modification and providesTI ‫ڦ‬a bq24650 ໿ᄞీ‫׾ۉ‬؊‫ۉ‬ഗă
design example that uses
཮ 2 ࠀ୲पྊ೫
Figure 2. Power-stage topologies
the Texas Instruments (TI) bq24650 solar battery charger.
ইუࠀ୲पᇑืუࠀ୲प‫ܔڦ‬Բ
The buck power stage versus the boost L
power
཮ stage
1 ๟ᅃ߲໿ᄞీ‫׾ۉ‬؊‫ۉ‬ഗ‫ڦ‬०ᅟ঳ࠓ཮ă؊‫ۉ‬ഗ੦ Q PWR
VSP VO_Buck
዆ഗ ཚࡗᅃ߲‫ୁۉ‬ॠ֪‫ۉ‬ፆഗ
FigureIC1 shows (RSNS)of॔੦؊‫ୁۉۉ‬ǈ
a simplified block diagram a solar-
powered battery charger.
ժཚࡗ‫ݒ‬ઍ‫ۉ‬ፆഗǄRTFB ࢅ RBFBǅ॔੦‫ۉ׾ۉ‬უ The charger-controller IC moni-
(VBAT)ă CO_Buck
CIN
tors the charging current through a current-sense resistor
ኄዖ IC ࣏‫୲ࠀܔ‬प‫ڦ‬๼‫؜‬৊ႜۙবǈᅜ஢ፁ؊‫֖ۉ‬ຕᄲ GDRVHI
(R SNS ) and the battery voltage (VBAT) through the feed-
൱ăසࡕ๼෇ᇸ‫ۉ‬უ
back resistors (R TFB and (VSP ๔ዕߛᇀፌ‫ۉ׾ۉٷ‬უǈሶ੗
R )BFB ). The IC also adjusts the QSYNC
GDRVLO
ᅜ๑ᆩᅃ߲ইუࠀ୲पăසࡕ
output of the power stage in orderVto ๔ዕ‫گ‬ᇀፌ‫ۉ׾ۉٷ‬
SP meet the charging
უǈሶᄲ൱๑ᆩᅃ߲ืუࠀ୲पă (VSP) will always be
parameters. If the input source voltage
higher than the maximum battery voltage, a buck power
(a) Synchronous buck
཮ 2 ྺᅃ߲ཞօইუࠀ୲पࢅᅃ߲‫ݥ‬ཞօืუࠀ୲पă
stage can be used. If VSP will always be lower than the
maximum battery voltage, a boost power
ଇ߲ࠀ୲‫ۼ‬๑ᆩߛ֨ቆटൻ‫ۯ‬ഗ stage) isઠൻ‫୲ࠀۯ‬
(G DRVHI required.
L DRECT
Figure 2 shows a synchronous buck power stage and a
FET (Q PWR) ă‫ڍ‬๟ǈ࿢்੗ᅜ࢔ൟ຿‫ܔں‬ইუ੦዆ഗ৊
nonsynchronous boost power stage. Both use the high- VSP VO_Boost
ႜದዃǈඟഄൻ‫ืۯ‬უገ࣑ഗ‫ڦ‬ཞօኝୁਸ࠲Ǘኄᄣǈ
side gate drive (GDRVHI ) to drive the power FET (QPWR ).
Q PWR
QSYNC ԥܾट࠶
However, ༺‫پ‬ǈ൐ுᆶᆩ‫֨گڟ‬ቆटൻ
DRECTcannot
a buck controller be easily configured to CIN GDRVHI CO_Boost
drive a synchronous rectifying
‫ۯ‬ഗ (GDRVLO)ăইუገ࣑ഗ࣏੗༵ࠃ૶Ⴤ‫ୁۉߌۉ‬ǈ‫ۉ‬ switch for a boost converter;
so QSYNC is replaced by
ୁཚࡗ‫ۉ‬ඹഗ diode DRECT, and the low-side gate
CIN ࢅ CBAT ୳հǄ൩֖९཮ 1ǅǈᇑన
drive (GDRVLO ) is not used. A buck converter also provides (b) Nonsynchronous boost
߲ਸ࠲‫ڞ‬ཚ࿮࠲ăᇑইუገ࣑ഗփཞ‫ڦ‬๟ǈืუገ࣑ഗ
continuous inductor current that is filtered by capacitors
๑ᆩ
C IN and CBATኻߴ‫ߌۉ‬؊‫ۉ‬ăሞኄ೺क़ǈ๼‫ۉ؜‬ඹഗՂႷ༵
QPWR (see Figure 1) regardless of which switch is
ࠃ‫׾ۉ‬؊‫ୁۉۉ‬ă
on. Unlike the buck D RECT ਸഔ้ǈ‫ړ‬മথ๴؊‫ߌۉڦۉ‬ཞ
converter, the boost converter uses
Q PWR only to charge the inductor. During this time the
้༵ࠃ๼‫ۉ؜‬ඹഗ‫׾ۉࢅୁۉ‬؊‫ୁۉۉ‬ăᅺُǈ၎Բ๑
output capacitor must supply the battery-charge current.
ᆩ၎ཞ‫ߌۉ‬Ă๼‫ۉ؜‬ඹࢅ၎ཞ๼‫ڦ୲ࠀ؜‬ইუገ࣑ഗǈ
When DRECT turns on, the now charged inductor provides
ืუገ࣑ഗ‫ڦ‬๼‫ۉ؜‬უ࿖հ๔ዕ‫ߛ߸ۼ‬ăኄዖ࿖հ੗‫ڞ‬
both the output-capacitor and the battery-charging cur-
ዂ‫ୁۉ‬ॠ֪‫ۉ‬ፆഗ‫؜‬၄փጚඓ‫֪ୁۉڦ‬ଉ঳ࡕă‫ܔ‬Բ཮
rents. Therefore, the boost converter’s output-voltage ripple 1
17

Power Management Texas Instruments Incorporated
໯๖ইუࠀ୲पǈืუࠀ୲पᄲ൱ᅃ߲߸‫ۉڦٷ‬უॠ֪୳
will always be higher than that of a buck converter that
཮ 3 ᇨ؊‫ۉۉ‬ୟ
Figure 3. Precharge circuitry
uses the same
հ‫ۉ‬ඹഗ (CFLTRinductor and output capacitance(Cand)ă
)ǈᅜतᅃ߲߸‫ڦٷ‬๼‫ۉ؜‬ඹ the
BAT
same output power. This ripple can cause inaccurate
Vcurrent measurement across the current-sense resistor.
BAT << VSP ้ǈ၌዆ᇨ؊‫ୁۉۉ‬
RPrecharge
Compared to the buck power stage shown in Figure 1, the VBAT
ሞ੦዆ഗ࿄৊ႜਸ࠲֡ፕ้ǈืუࠀ୲प‫ڦ‬ኝୁܾट࠶
boost power stage will require a larger sense-voltage filter VO_Charger
༵ࠃକᅃཉٗ VSP
capacitor (CFLTR ‫ڦ׾ۉڟ‬
) and a largerDC ‫ୁۉ‬ୟ০ăศ‫ۉڦۉݣ܈‬
output capacitance (CBAT).
‫׾‬ǈ‫ۉ׾ۉ‬უ‫گ‬ᇀ໿ᄞీ‫׾ۉ‬ӱ‫ڦ‬๼‫ۉ؜‬უǈ‫ڞ‬ዂ؊‫ۉ‬ R PwrUp QShort
Limiting precharge current when VBAT << VSP +
ഗ੦዆ഗཕኹਸ࠲֡ፕǈժ൐փም‫׾ۉܔ‬؊‫ୁۉۉ‬৊ႜ –
The boost power stage’s rectifying diode provides a DC R HYS
ۙবăᅺُǈᄲ൱๑ᆩᅃ߲ᇑܾट࠶Ǆ൩֖९཮
current path from VSP to the battery when the controller 3 ǅ‫ز‬
is
૴‫ڦ‬၌ୁ‫ۉ‬ፆഗǄ
not switching. With aRdeeply
Precharge ǅǈᅜॽ؊‫ୁۉۉ‬၌ۨሞగ߲
discharged battery, the battery VCC
߸‫ڦگ‬ᇨ؊‫ୁۉۉ‬ኵăᅃ‫ۉ׾ۉڋ‬უ‫ڟٳ‬
voltage could be below the solar panel’s output ǈ੦዆ഗՍ
VSPvoltage,
+
causing the charger controller to
ਸ๔ਸ࠲֡ፕǈཞ้ཚࡗᅃ߲ FET (QShort) ඟ RPrecharge stop switching and no ‫܌‬
longer regulate the battery-charging current. Therefore, a
ୟǈܸٗሎႹ੦዆ഗ༵ࠃ߸ߛ‫ڦ‬؊‫ୁۉۉ‬ă཮ 3 ௮ຎକ –
current-limiting resistor (RPrecharge) in series with the diode
R(see ĂQShort
Figure
Precharge 3) isࢅԲডഗසࢆᅃഐ߾ፕઠํแኄዖࠀీ‫ڦ‬
required to limit the charge current to a
ࡗ‫ײ‬ă
lower, precharging current value. Once the battery voltage VSP
reaches VSP, the controller begins switching, and RPrecharge
๢‫ړ‬჋ስ
can be shortedR Precharge ‫ٷڦ‬ၭǈඟഄీࠕᅜ໿ᄞీ‫׾ۉ‬ӱፌ
out with a FET (QShort ) to allow the con-
troller to provide higher
‫ۉۅ୲ࠀٷ‬უ (VSP_MPP)ྺ‫ࠃ༵׾ۉ‬ፌ‫ॺٷ‬ᅱᇨ؊‫ୁۉۉ‬ă charge currents. Figure 3 shows
how
࣏ᄲጀᅪ჋ስ R can be used with QShort and a comparator
Short ‫ٷڦ‬ၭǈඟഄీࠕ‫׶‬๴ፌ‫ۉ׾ۉٷ‬უ
Precharge Q
to implement this functionality.
(VBAT(max) ) ࢅፌ‫ٷ‬؊‫ୁۉۉ‬
RPrecharge (ICHRG(max)
is sized to give the maximum )ăԲডഗ‫ݒ‬ઍ‫ۉ‬ፆഗ
recommended
(R )
precharge
HYS ༵ࠃ‫׿‬ውፕᆩăᅺُǈԲডഗ‫ۉڦ‬უॠ֪๼෇‫܋‬Ⴔ
current for the battery at the solar panel’s maxi-
ᄲᅃၵ‫ۉ‬ፆ‫ݴ‬უഗă
mum power-point voltage (VSP_MPP). QShort is sized to Figure 4. Current-sensing circuit with
཮ 4 ๑ᆩ‫ۉ‬ೝᅎ‫ୁۉڦۯ‬ॠ֪‫ۉ‬ୟ
level shifting
accommodate the maximum battery voltage (VBAT(max))
BAT >the
Vand ईኁ VBAT charge
VSPmaximum ้ǈඓԍኟ‫׉‬ሏႜ
< VBATSHTcurrent (ICHRG(max)). The com-
parator feedback resistor (R ) provides hysteresis. RSNS VBAT
ইუ؊‫ۉ‬ഗထྭ‫ۉ׾ۉ‬უ๔ዕ‫گۼ‬ᇀ؊‫ۉ‬ഗ‫ڦ‬๼෇‫ۉ‬უă HYS
Therefore, resistor dividers are needed on the sensed- VO_Boost
ํाฉǈႹ‫ܠ‬؊‫ۉ‬ഗ‫ۼ‬ਏᆶᅃዖࠀీǈनሞ VBAT ‫ٷ‬ᇀ VSP
voltage inputs to the comparator.
้ඟ؊‫ۉ‬ഗ৊෇ລ௥ఇ๕ăईኁǈසࡕ V BAT ই዁గ߲ព VBAT CBAT
ኵEnsuring
(VBATSHT)operation
ᅜူǈIC when VBAT > VSP or when
Ս्ࣷย‫܌׾ۉ‬ୟǈ඗ࢫ৊ႜԍࢺ CFLTR1
VSP
V BAT < VBATSHT
ఇ๕ăසࡕ‫ୁۉ‬ॠ֪ᆅগ‫ۉڦ‬უǄ VRSNS+ ࢅ VRSNS–ǅᆩᇀ
A buck charger expects the battery voltage to always be
ඓۨ‫ڦ׾ۉ‬ጒༀǈሶႴᄲ‫ܔ‬๴ॠ֪‫ۉ‬უ৊ႜ‫ۉ‬ೝᅎ‫ۯ‬ǈ Current Shunt
less than the charger’s input voltage. In fact, many chargers +
ᅜՆ௨ॠ֪‫ڟ‬࿁‫܌‬ୟ๼‫؜‬ă཮
have a feature that puts the charger 4 ௮ຎକසࢆ๑ᆩᅃ߲ದ
into sleep mode if
Monitor
ዃྺ‫॔ୁݴ‬੦ഗ‫ڦ‬ॠ֪‫ٷݣ‬ഗǈ‫ܔ‬
VBAT is greater than VSP. Alternatively,RifSNS ‫ୁۉڦ‬ॠ֪႑တ
VBAT falls below a –
certain threshold (VBATSHT), the IC may assume
৊ႜ‫ۉ‬ೝᅎ‫ۯ‬ă޿‫ۉ‬ୟই‫گ‬କॠ֪‫ۉ‬უ‫ڦ‬ DCthe battery
ยዃ‫ۅ‬ǈඟ VRSNS+
is shorted and enter protection mode. If the voltages at
IC փࣷ৊෇ລ௥ఇ๕ǈժ൐ඟ‫ۉ‬უྼ‫׼‬ፁࠕߛǈᅜ๑ IC CFLTR2
the current-sense pins (VRSNS+ and VRSNS– ) are used to
փ৊෇‫܌‬ୟԍࢺఇ๕ăසࡕ؊‫ۉ‬ഗுᆶጲम‫ۉ੊֖ڦ‬უ VRSNS– VBIAS
determine the battery’s state, the sensed voltages will
(V REF)ǈ੗ᅜ๑ᆩᅃ߲ྔև֖੊
need ă detection of a
to be level shifted to avoid aICfalse
shorted output. Figure 4 shows how to use an instrumen-
tation amplifier, configured as a current-shunt monitor, to
level shift the current information sensed across R SNS.
This circuit lowers the DC set point of the sensed voltages
enough that the IC will not enter sleep mode but keeps
the voltages high enough that the IC does not enter short-
circuit-protection mode. If the charger does not have its
own reference voltage (VREF), an external reference IC
can be used.
18

Texas Instruments Incorporated Power Management
ऺ໙ፌ‫ٷ‬؊‫ୁۉۉ‬
Computing the maximum charge current ব‫ڦ‬
3shows ᯜbq24650
TI’s ૗ጱ‫׾ۉ‬ ፇ؊‫ۉ‬
charger ă ፌ ‫ٷ‬configured
controller ؊ ‫ୁ ۉ ۉ‬to ԥcharge
၌዆ሞ
ืუ؊‫ۉ‬ഗ‫ڦ‬ፌ‫ٷ‬؊‫ୁۉۉ‬ᇑഄ੗ᆩ๼෇ࠀ୲ᆶ࠲ăࠚ
A boost charger’s maximum charge current is a function of a 12.6-V, 3-cell Li-ion battery
1.2A ă૧ᆩืუገ࣑ഗ‫ڦ‬Քጚยऺኸ‫ڞ‬ᇱሶǈ࿢்ඓۨ from a 5-V solar panel. The
maximum charge current is limited to 1.2 A. The power
໙ፌ‫ٷ‬؊‫ڦୁۉۉ‬ᅃዖ०‫݆ݛڇ‬๟ǖ๯ံࠚ໙๼෇‫ڟ‬๼
its available input power. A simple way to estimate the କࠀ୲nཚ‫ڢ‬FET (Q1) ࢅኝୁܾट࠶ (D1) ‫ٷڦ‬ၭă࿢்
maximum charge n-channel FET (Q1) and rectifying diode (D1) are sized
‫؜‬ၳ୲ǈन POUT/Pcurrent is to first estimate the input-to-
IN = ηestǈഄዐ ηest ྺ၎ຼ߾ፕཉॲူ ๢‫ړ‬჋ስକ‫ߌۉ‬ (L1) ࢅ๼‫ۉ؜‬ඹഗǄ
by using standard design ࢅ C4 ǅ‫ٷڦ‬
C3 converters.
guidelines for boost
output efficiency, POUT / PIN = Kest, where Kest is an estimate
ืუ؊‫ۉ‬ഗၳ୲‫ࠚڦ‬໙ኵăူଚ‫ײݛ‬๕੗ᆩᇀऺ໙ਏ༹ ၭǈᅜ३ณ‫ୁۉߌۉ‬࿖հतഄׂิ‫ڦ‬๼‫ۉ؜‬უ࿖հă
The inductor (L1) and output capacitors (C3 and C4) areR18
of the boost charger’s efficiency in similar operating condi-
‫ۉ׾ۉ‬უ‫ڦ‬ፌ‫ٷ‬؊‫ୁۉۉ‬ǖ
tions. The following equation can then be used to estimate sized to reduce
ᆩᇀ३࣐ inductor-current ripple and the resulting
Q1 ‫੺ڦ‬໏ਸഔăଷྔǈॽ੦዆ഗ‫ڦ‬ PH ᆅগথ
the maximum charge current at a specific battery voltage: output-voltage ripple. R18 is used to slow down the fast
‫ں‬ǈᅜӻዺ༵ࠃডߛ‫ڦ‬๼‫ۉ؜‬უăྺକ‫ݞ‬ኹ‫॔ୁݴ‬੦ഗ
turn-on of Q1. Also, the controller’s PH pin is grounded to
VSP _ MPP
ISP _ MPP
est (U2) ‫ڦ‬๼‫ߴ؜‬ ᆅগ‫ټ‬ઠ޶ሜǈᅃ߲ኝ༹ሺᅮ࣐؋ഗ
ICHRG(max) , help provide theSRPboosted output voltage. To prevent the
VBAT (U3) ๟Ղᄲ‫ڦ‬ă
output of the current-shunt monitor (U2) from loading the
ഄዐ SRP pin, a unity-gain buffer (U3) is necessary.
SP_MPP ྺ໿ᄞీ‫׾ۉ‬ӱ‫ڦ‬ፌ‫ۉۅ୲ࠀٷ‬უǈܸ
whereVVSP_MPP is the solar panel’s maximum power-point
voltage,
I SP_MPP and I SP_MPP is the solar panel’s maximum power-
ྺ໿ᄞీ‫׾ۉ‬ӱ‫ڦ‬ፌ‫ୁۉۅ୲ࠀٷ‬ă
point current.
R SNS should
๢‫ړ‬჋ስ be ‫ٷڦ‬ၭǈඟഄీࠕ༵ࠃ
sized to provide ICHRG(max)ICHRG(max)
. QPWR ă hasQaPWR ՗ 1 ੦዆ഗᆅগఁ‫ܔ׬‬ቷ՗
Table 1. Cross-reference for controller pin names
RSNS
voltage rating slightly higher
‫ۉۨܮڦ‬უฎߛᇀ ǈܸ than VSP(max)
ࢅ , and QPWR and
‫ୁۉۨܮڦ‬዁ FIGURE 1 CONTROLLER
VSP(max) QPWR L1 bq24650 PIN NAME
L1 have current ratings equal to at least ISP_MPP . The PIN NAME
ณ‫ڪ‬ᇀ ISP_MPPă࠶૙๼෇‫ۉ‬უࢅ‫ڦୁۉ‬؊‫ۉ‬ഗ੦዆‫ۉ‬ୟ
charger’s control circuitry that manages input voltage and GDRVHI HIDRV
ࣷ‫ܔ‬؊‫ୁۉۉ‬৊ႜۙবǈᅜඟ؊‫ۉ‬ഗ߾ፕሞ໿ᄞీ‫׾ۉ‬
current will adjust the charge current to keep the charger
GDRVLO LODRV
ӱ‫ڦ‬ፌ‫ۅ୲ࠀٷ‬ăස
operating at the solar panel’s
bq24650 ‫ڪ‬؊‫ۉ‬੦዆ഗǈ๑ᆩፌ‫ٷ‬
maximum power point.
Charge controllers such as the bq24650 perform the same VRSNS+ SRP
ࠀ୲‫ۅ‬ጕጷ (MPPT) रຍઠํแ၎ཞ‫ీࠀڦ‬ă
function with maximum-power-point tracking (MPPT). VRSNS– SRN
๑ᆩ bq24650 ‫ڦ‬ยऺํ૩ FB VFB
Design example using the bq24650
՗ 1 ॽ཮
Table 1 ‫ీࠀڦ‬ᆅগఁ‫׬‬ᇑ཮
1 maps the functional pin names ዐ၎ᆌ‫ڦ‬
5 from Figurebq24650
1 to the
ᆅগఁ‫׬‬၎‫ܔ‬ᆌă཮ ၂๖‫ڦ‬๟
corresponding bq246505 pin ‫ ڦ‬bq24650
TI Figure
names in ؊‫ۉ‬ഗ
5. Figure 5
੦዆ഗǈഄ๑ᆩᅃ߲ 5-V ໿ᄞీ‫׾ۉ‬ӱྺᅃ੷ 12.6-VĂ
཮ 5 ದዃྺืუ؊‫ۉ‬ഗ‫ڦ‬
Figure 5. The bq24650 configured
bq24650as a boost charger
D1 R20
C3 R21 C4
L1 PDS1040 10 μF 100 VBAT
VSP 33 m 10 μF
C2 Q1 R10
R1 10 μF CSD17308Q3 Q2 + 3-Cell
2 R2 D2 C5 100 k – Battery
BAT54C 1 μF Pack
10 VCC R11
C1 HIDRV VBAT
2.2 μF C6 VCC 499 k
1 μF U1
VSP
bq24650
R12
VREF PH U2 100 k
R3 C7 INA139 +
301 k PGND
1 μF C8
R5 1 μF – R19
301 k MPPSET REGN 1 M
BTST R17
TS VCC R13
R18 1 k 301 k
TERM_EN 15 VCC +
R6 R4 LODRV R14
+
301 k 100 k U4 – 301 k
SRP TLV7211
STAT1 U3 –
LM358 D3
STAT2 IN4148 VSP
Q3 SRN VREF R15
2N7002 R20 C7 301 k R16
VFB 1 μF 301 k
1 k
19

Power Management Texas Instruments Incorporated
཮Figure
6 ၂๖କ཮ ໯๖؊‫ۉ‬ഗ‫ڦ‬ၳ୲ă৑࠶
6 shows5the efficiency of the charger
཮ 6 ཮6.5Efficiency
໯๖ืუ؊‫ۉ‬ഗ‫ڦ‬ၳ୲
Figure of boost charger in Figure 5
in Figure 5. Although
bq24650 ፕྺᅃ߲ইუ؊‫ۉ‬ഗሞాևइ‫ڥ‬ the bq24650 is inter-
nally compensated as a buck charger, its
ց‫׋‬ǈ‫ ړڍ‬IC ፕྺᅃ߲ืუ؊‫ۉ‬ഗ߾ፕ
small-signal control loop is stable over a wide 100
้ǈഄၭ႑ࡽ੦዆࣍ୟሞᅃ߲ড੻‫߾ڦ‬ፕ‫ݔ‬
operating range when the IC is operating as a 98 VIN = 5 V
ྷሏႜ࿘ۨǈස཮ 7 ໯๖ăॽ
boost charger (see Figure bq24650
7). When ᇑ
using the
96 VOUT = 12.6 V
bq24650 with different power-stage inductors
փཞ‫୲ࠀڦ‬प‫ۉࢅߌۉ‬ඹഗᅃഐ๑ᆩ้ǈย
and capacitors, the designer is responsible for 94
ऺටᇵՂႷඓණ࣍ୟ‫ڦ‬࿘ۨႠă
Efficiency (%)
confirming loop stability. 92
঳ஃ
Conclusion 90
‫ܔ‬ᇀืუ‫׾ۉ‬؊‫ۉ‬ഗ‫ڦ‬Ⴔ൱ኟփ܏ሺ‫׊‬ǈ༬
The demand for step-up battery chargers is 88
growing, especially as the demand for charg-
՚๟ሞ໿ᄞీ‫׾ۉ‬ӱ؊‫ۉ‬Ⴔ൱ሺ‫ڦ׊‬൧઄ 86
ing from solar panels grows. Following the
ူă૧ᆩԨ࿔঻ถ‫ڦ‬ᅃၵኸ‫ڞ‬ᇱሶǈยऺට 84
guidelines presented in this article, a designer
ᇵ੗ᅜॽ the bq24650
can convertbq24650
ইუ؊‫ۉ‬ഗገ࣑ྺᅃ߲
buck charger into a 82
ืუ؊‫ۉ‬ഗăॽփཞ‫ڦ‬ইუ؊‫ۉ‬ഗገ࣑ྺื
boost charger. When converting a different 80
უ؊‫ۉ‬ഗ้ǈยऺටᇵՂႷ૙঴؊‫ۉ‬ഗ‫߾ڦ‬
buck charger into a boost charger, the 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
designer is responsible for understanding how IOUT (A)
ፕᇱ૙ǈኄᄣ֍ీඓۨనᅃዖ޹े‫ۉ‬ୟ๟Ղ
that charger operates in order to determine
Ⴔ‫ڦ‬ǈ֍ీඓۨഄ๟‫ࠕీޏ‬࿘ۨሏႜă
which additional circuitry is necessary as well
as to confirm stable operation.
၎࠲ྪበ
Related Web sites
Power.ti.com
power.ti.com
www.ti.com/sc/device/partnumber Ǆᆩ bq24650 Ă
www.ti.com/sc/device/partnumber
CSD17308Q3 ĂINA139
Replace partnumber Ăbq24650,
with LM358 ईኁ TLV7211༺࣑ྪ኷
CSD17308Q3,
ዐ‫ڦ‬Đpartnumber
INA139, đǅ
LM358, or TLV7211
཮ 7 ਸ‫ݒ‬ઍ࣍ୟ‫ڦ‬ሺᅮࢅ၎࿋հ༬཮
Figure 7. Bode plot of gain and phase with an open feedback loop
60 180
Phase VIN = 4.8 V
ICHRG = 0.8 A VOUT = 12.6 V
40 120
Gain
ICHRG = 0.2 A
20 Phase 60
ICHRG = 0.2 A Phase (degrees)
Gain (dB)
0 0
Gain
ICHRG = 0.8 A
–20 –60
–40 –120
–60 –180
100 1k 10 k 100 k 1M
Frequency (Hz)
ZHCT139
20

Texas Instruments Incorporated Interface (Data Transmission)
߰૗๕
Isolated ๭݀ഗ੗ኧ‫׼‬
RS-485
RS-485 transceivers
DMX512support
࿸໼ቷ௽ࢅ༬ၳᆌᆩ
DMX512 stage lighting and special-
effects applications
ፕኁǖThomas Kugelstadt
By Thomas Kugelstadt
‫ڤ‬ዝᅏഗ (TI) ߛपᆌᆩ߾‫ײ‬฾
Senior Applications Engineer
཮
Figure ྪஏ‫ڦ‬ਅࢾ૾๕ྊ೫঳ࠓ
1. Daisy-chained
1 DMX512 topology of DMX512 network
Controller Receiver 1 Receiver 2 Receiver n Terminator

(Master) (Slave) (Slave) (Slave) (120 )
OUT IN OUT IN OUT IN OUT IN
၄‫پ‬ਗᇾĂਗ‫ׇ‬Ă༹ᇣ࠷ࢅᅼૂཐ‫ڦ‬࿸໼ቷ௽ࢅ༬ၳᆌ
Stage lighting and special-effects applications in modern ੨ăኻᆶᅃ߲ থ੨‫ڦ‬੦዆ഗǈ૶থ዁๯߲ٗব‫ڦۅ‬
OUT all
Within the network, nodes are connected through daisy-
ᆩ‫ۼ‬๑ᆩକްሗ‫ڦ‬ຕ਍‫د‬๼ྪஏăኄၵྪஏ‫ڦ‬ཚ႑ਐ૗
theaters, opera houses, sports arenas, and concert halls IN থ੨ă๯߲ٗব‫ڦۅ‬
chaining; that is, each slave
OUT থ੨૶থ዁ူᅃ߲ٗব‫ڦۅ‬
node has an IN connector as
utilize complex
ཚ‫׉‬੗‫ٳ‬ 1200data-transmission
௝ǈᅜሞຕӥ߲ྪஏব‫ۅ‬Ǆ޶ሴ੦዆ networks. These net- well
IN as an OUT
থ੨ǈසُૌླྀǄ൩֖९཮ connector. The controller, which has only
1ǅă૾‫ڦ‬ፌࢫᅃ߲ٗব
works, often reaching distances of up to 1200 m, provide an OUT connector, connects to the IN connector of the
ۙ࠼ഗĂ‫࠼ڨ‬ᅎ‫ۯ‬Ă಩ჶऐࢅഄ໱༬ၳยԢǅኮक़ํ ‫ ڦۅ‬OUT থ੨૶থᅃ߲ 100-Ω ई 120-Ω ዕ‫܋‬ഗ֭ཀྵă
communication between several hundreds of network first slave. The OUT connector of the first slave connects
၄ཚ႑ă
nodes that control dimmers, moving lights, fog machines, to the IN connector of the next slave, and so on (see
ኄᄣǈՍ੗ᅜ൶‫ݴ‬ DMX512 ‫܋‬੨‫؜دࢅ෇دڦ‬ຕ਍႑
and other special-effects equipment. Figure 1). The OUT connector of the last slave in the
ྺኄၵᆌᆩ༵ࠃ੗੍‫ాڦ‬ևཚ႑ԍቱ‫ڼڦ‬ᅃዖՔጚՍ
The first standard ensuring reliable intercommunication ࡽǈ
chain থ੨ྺኍ႙
INconnects ǈܸ
XLR-5or
to a 100-: থ੨ྺ֭੥႙
OUTterminator
120-: plug. XLR-5
๟ዸఁ‫ڦ‬ DMX512 ă໲ፌ‫؛‬๟ᆯெࡔਗᇾरຍჺ৯໯
for these applications was known as DMX512 and was Ǆ൩֖९཮ ǅă
2 ingoing and outgoing data signals of a
So that the
originally߾‫ײ‬྿ᇵࣷᇀ
(USITT) developed in 1986
1986by౎዆ۨă
the United States
1998 Institute
౎ǈᇏૂ‫ޜ‬ခ DMX512 port can be distinguished, the IN connectors are
for Theatre Technology
ᇑरຍၹࣷ (USITT) Engineering Commission.
থ๮କ޿Քጚ‫߾ࢺྼڦ‬ፕăெࡔࡔॆ male XLR-5, and the OUT connectors are female XLR-5
(ESTA)
In 1998, the Entertainment Services and Technology (see Figure 2).
Քጚბࣷ (ANSI) ᇀ 2004౎ ಼ጚ݀քକՔጚ‫ڦ‬Ⴊ۩Ӳă
Association (ESTA) took over maintenance of this stan-
dard. A౎ǈՔጚምْԥႪ۩ǈ‫ྺׯ‬କ၄ሞ‫ڦ‬
2008 ANSI E1.11-
revised version was approved by the American
2008 ǈഄඇ‫ྺ׬‬ĖᇏૂरຍĊ
National Standards Institute (ANSI) in 2004.
USITT DMX512-A Ċቷ
The standard ཮ 2 DMX512
Figure Քጚথ੨
2. DMX512 standard connectors
was revised again in 2008 and is now officially known as
௽ยԢतದॲ‫ݥ‬ཞօ‫ز‬ႜຕጴࣅຕ਍‫د‬๼Քጚėǈ०‫׬‬
ANSI E1.11-2008, entitled Entertainment Technology—
DMX512-Aă
USITT DMX512-A—Asynchronous Serial Digital Data
5 1 1 5
Transmission Standard for Controlling Lighting
ྊ೫঳ࠓ Male XLR-5
Equipment and Accessories, or DMX512-A in short. 4 2 2 4 Female XLR-5
DMX512 ྪஏ๑ᆩᅃዖᇑ RS-422 ૌຼ‫ۅܠڦ‬ྊ೫঳ 3 3
Topology
ࠓǈഄ‫ڇ‬੦዆ഗǄዷব‫ۅ‬ǅၠ‫߲ܠ‬থ๭ऐǄٗব‫ۅ‬ǅ݀
A DMX512 network utilizes a multidrop topology similar IN OUT
ໃዘް੦዆ຕ਍ăྪஏా໯ᆶব‫ۅ‬਩ཚࡗਅࢾ૾૶থǗ Connector Connector
to RS-422, where a single controller (master node) sends
ᄺ৽๟ຫǈ௅߲ٗব‫ۼۅ‬ᆶᅃ߲ IN থ੨ࢅᅃ߲
repetitive control data to multiple receivers OUT থ
(slave nodes).
21

Interface (Data Transmission) Texas Instruments Incorporated
ၹᅱ
Protocol ଷྔǈFurthermore,
DMX512-A ࣏ࡀۨକႹ‫ܠ‬ሺഽࠀీ
DMX512-A makes provisions for ྊ೫঳
enhanced-
(EF)
A DMX512੦዆ഗᅜ functionality (EF) topologies
ࠓǈඟᆌ‫ٴ‬ഗ‫ڦ‬๑ᆩ‫ྺׯ‬੗ీăᆌ‫ٴ‬ഗথ๭ব‫ۅ‬ຕ਍ǈ that enable the use of
DMX512 controller250
transmits ໏୲݀ໃ‫ݥ‬ཞօ‫ز‬ႜຕ਍
kbps packets of asynchronous
serial data at 250 kbps (see Figure 3). A data packet starts responders. The responders are receiving nodes that can
ԈǄ൩֖९཮ 3ǅăຕ਍Ԉᅜᅃ߲੣߭Ǆஇड‫ۉگ‬ೝǅ ඗ࢫၠ੦዆ഗ‫࣮ݓ‬ጒༀ႑တăፌ‫׉‬ᆩ‫ڦ‬ଇዖ EF ྊ೫๟
with a break (logic low) and is followed by a mark (logic return status information to the controller. The two EF
ਸ๔ǈࢫ௬߶ᅃ߲‫ࡽޙ‬Ǆஇडߛ‫ۉ‬ೝǅǈኄዖႾଚԥ‫׬‬ EF1 ࢅ EF2most
topologies ăEF1 ሞapplied
often DMX512 ྪஏ੦዆ഗࢅᆌ‫ٴ‬ഗኮ
are EF1 and EF2. EF1 pro-
high), a sequence known as mark-after-break (MAB).
ፕ੣߭ -‫ࡽޙ‬ ǈMAB) क़༵ࠃӷມ߾૾থă EF2 ሞྪஏব‫ۅ‬ኮक़༵ࠃඇມ߾૾
Following MAB (mark-after-break
is a time slot consisting ofă start ā‫ࢫڦ‬௬
a MAB bit, eight vides a half-duplex link between the DMX512 network’s
๟ᅃ้߲ဤǈഄᆯᅃ߲ഐ๔࿋Ăӗ߲ຕ਍࿋ࢅଇ߲ዕኹ
data bits, and two stop bits. The entire packet consists of controller and responders. EF2 provides a full-duplex
থăኄଇዖ൧઄ူǈຌᇀথ๭ऐॲ‫ڦ‬ᆌ‫ٴ‬ഗ I/O ‫܋‬੨ǈlink
a maximum of 513 time slots, 513 512 of which are actual data between the network nodes. In both cases, the I/O port of
ՂႷᆶ߰૗‫݀ڦ‬ໃࢅথ๭‫܋‬੨ă
࿋ፇ‫ׯ‬ăኝ߲ຕ਍Ԉፌ‫ܠ‬ᆯ ้߲ဤፇ‫ׯ‬ǈഄዐ 512
slots. The first slot, known as the start code, specifies the responders, falling under the category of receiving devices,
้߲ဤྺํाຕ਍้ဤă‫ڼ‬ᅃ้ဤԥ‫׬‬ፕഐ๔ஓǈࡀۨ must have isolated transmit and receive ports.
type of data in the packet. ඇມ߾ RS-485 ๭݀ഗፌྺ๢ࢇᇀኄၵᆌᆩǈᅺྺ A,B
କຕ਍Ԉዐຕ਍‫ڦ‬ૌ႙ă Full-duplex RS-485 transceivers are the devices best
ࢅ Y,Z ጺ၍ዕ‫܋‬ዘႎք၍०‫ڇ‬ǈփৈৈ੗ᅜඹభՔጚ
Physical layer suited for these applications because simple rewiring of
࿿૙֫ DMX512
the A,B andဣཥ‫ڇڦ‬থ๭ऐದዃ঳ࠓǈܸ൐੗ᅜඹభ
Y,Z bus terminals can accommodate not only EF1
The DMX512-A standard specifies EIA-485 as the network’s
physical layer, thus allowing
Քጚࡀۨ for a maximum
ྺྪஏ‫ڦ‬࿿૙֫ǈܸٗ common- ࢅ EF2
the ဣཥ‫ݴ‬՚๑ᆩ‫ڦ‬ӷມ߾ࢅඇມ߾ದዃ঳ࠓă
receiver-only configuration in standard DMX512 sys-
DMX512-A EIA-485
tems but also the half- and full-duplex configurations used
ሎႹߛ‫ ٳ‬32 ‫ڇ‬࿋޶ሜ‫ڦ‬ፌ‫ࠌٷ‬ఇ޶ሜǈᅜत‫ٳ׊‬bus
mode loading of up to 32 unit loads and a maximum
1200 ‫د‬ཥ‫ڦ‬থ๭ऐยऺཚ‫׉‬๑ᆩᅃ߲‫߰ݥ‬૗๕๭݀ഗǈᇑᅃ
length of 1200 m. Network wiring typically consists of respectively in EF1 and EF2 systems.
௝‫ڦ‬ፌᇺጺ၍ཚ႑ਐ૗ăྪஏք၍ᅃӯ๑ᆩ༬Ⴀፆੇྺ
twisted-pair cable with a characteristic impedance of Legacy receiver designs often used a non-isolated trans-
ၵ࠼߰૗ഗፇࢇ๑ᆩă‫ڍ‬๟ǈኄၵ߰૗ഗዐ‫ڦ‬໒‫֌ހ‬ଙ
either‫ڦ‬
120Ω 120 ມজ၍ǈईኁ
: for RS-485
RS-485 100Ω
cable or 100 :‫ڦ‬ for CAT5 ມজ၍ǈ
CAT5 cable, ceiver in combination with opto-isolators. However, the
एԨฉ‫ׯ‬କ݀࠼ܾट࠶ࢅথ๭࠼௺ৗ༹࠶ኮक़‫ڦ‬ਨᇹ
൐ጺ၍‫܋ڦ܋‬থ‫ۉ‬ፆፆੇ၎‫ڪ‬ă
with a termination resistor of equal impedance at the end mold compound in these isolators, basically representing
༹ǈ้क़ᅃ‫ࣷ׊‬ဌ๭຤‫ݴ‬ǈܸٗই‫߰گ‬૗֫‫׊ڦ‬೺࿘ۨ
of the bus. the dielectric between the light-emitting diode and the
‫ أ‬In additionᅜྔǈ ࣏ླྀ४๑ᆩথ‫݀ں‬พഗ‫܋‬ Ⴀă
receiving photo transistor, absorbed moisture over time,
EIA-485 DMX512-A
to EIA-485, DMX512-A recommends earth-
grounded transmitter ports
੨ࢅ߰૗๕থ๭ऐ‫܋‬੨ǈᅜՆ௨ႚ‫ׯ‬೦࣋Ⴀ‫ڦ‬থ‫࣍ں‬ୟ and isolated receiver ports to reducing the long-term stability of the isolation barrier.
‫د‬ཥยऺ‫ڦ‬ଷᅃ߲ඍ‫ۅ‬๟๑ᆩ߰૗๕‫ۉ‬ᇸǈഄᄲ൱ሞ߰
A further drawback of legacy designs was the use of an
avoid the
Ǆ൩֖९཮ 4ǅă formation of disruptive ground loops (see
Figure 4). ૗༵֫ࠃ‫ۉ‬ᇸ‫ۉ‬უăኄዖยऺཚ‫׉‬๑ᆩ༹ओຬ‫ڦٷ‬
isolated power supply that was required to provide the DC/
DC ገ࣑ഗፇॲǈഄ‫ׯ‬Ԩ‫ࡗג‬କ໯ᆶ‫ڦ‬႑ࡽཚୟፇॲĊ
཮ 3 DMX512
Figure ຕ਍Ԉ้Ⴞ
3. DMX512 packet timing
DMX512 Packet
Idle
Time Slot 0 Time Slot 1 Time Slot n
(nmax = 512)
Start
Start
Start
MBB Break MAB 8-Bit Data Stop D0 D1 D2 D3 D4 D5 D6 D7 Stop D0 D1 D2 D3 D4 D5 D6 D7 Stop MBB

LSB MSB
཮ 4 থ‫݀੊֖ں‬พഗࢅ߰૗থ๭ऐ
Figure 4. Ground-referenced transmitter and isolated receiver
Isolation
VS VS(ISO) Barrier VS
Data 1+ Data 1+ Non-

Isolated
Isolated
Logic
Data 1– Data 1– Logic
RA < 100 RA < 100 0 VISO

0V Data-Link Data-Link 0V
Common Common
RB < 20 RB > 22 M
Protective- Protective-
Chassis Earth Earth Chassis
22

Ԉઔ๭݀ഗĂ߰૗ഗࢅ
supply voltage across theUART ĊĊߛ‫؜‬ኝኝ
isolation barrier. Bulky ă
DC/DC-
300% ๼‫؜‬ຕ਍৊෇
and the longerTIrise and fall times of
MSP430F2132 Ǆᅃዖ‫ྲࡼࠀگ‬੦዆ഗǅ‫ڦ‬
200 ns ensure low
converter modules were often applied whose cost exceed- electromagnetic interference.
UART থ੨ă޿ྲ੦዆ഗॽ UART ຕ਍ገ࣑ྺཞօߛ໏‫ز‬ႜ
ፌৎǈຕጴ‫ۉ‬ඹ๕߰૗रຍ‫؜ڦ‬၄ǈ঴ਦକ‫׊‬೺੗੍Ⴀ
ed that of all the signal-path components—including the Here the incoming control data from the DMX512 bus is
ຕ਍ୁǈࠃߴᅃ߲ӗཚ‫ڢ‬Ăߛუ๼‫؜‬ຕఇገ࣑ഗ (DAC)ăTI
transceiver, isolators, and
࿚༶ăኄዖ߰૗֫ᆯ 120UARTs—by up to 300%.
fF ᅜా‫ڦ‬ၭ႙Ăߛუ‫ۉ‬ඹഗፇ signal-conditioned by the input comparator and sent across
With the recent introduction of digital capacitive-isolation ‫ڦ‬theDAC7718 ሎႹߛ‫ٳ‬
isolation barrier ±16.5
towards ‫ڦ‬ມट๼‫؜‬ǈᅜतߛ‫ٳ‬
theV receiver output. Output 33V
‫ׯ‬ǈ๑ᆩܾᄟࣅࡂ (SiO2) ፕྺ߰૗‫঻ۉ‬ዊăSiO2 ๟ፌॕ
technology, the issue of long-term reliability has been ‫ڇڦ‬ट๼‫؜‬ă
data at the R terminal enters the UART interface of TI’s
ᆘ‫߰ڦ‬૗֌ଙኮᅃǈबࢭփဌ๭຤‫ݴ‬ǈᅺُ੗ᅜ༵ࠃट
solved. The isolation barrier, consisting of small, high- MSP430F2132, a low-power microcontroller. The micro-
ߛ൐‫׊‬೺‫ڦ‬੗੍Ⴀᅜतড‫ڦ׊‬๑ᆩ๱ంă
voltage capacitors in the range of 120 fF, uses silicon ᆯᇀ࿸໼༬ၳยԢ਩๑ᆩ
controller converts the UART 0‫ڟ‬ V ‫ڇڦ‬ट੦዆‫ۉ‬უǈᅺُ
10into
data a synchronous,
dioxide (SiO2) as the isolation dielectric. SiO2 is one of the DAC7718 ๟ኄૌᆌᆩ‫ڦ‬૙ၙఇెথ੨ǈഄీࠕํ၄௅߲ྪ
high-speed serial data stream to feed an eight-channel,
ଷྔǈ ႎ႙ဣཥ߰૗๕
hardestTIisolation materials with little ๭݀ഗǈᆛᆶण‫ׯ‬Վ
RS-485 moisture absorption, high-voltage-output digital-to-analog converter (DAC). TI’s
ஏব‫ ٳܠۅ‬8 ߲ۙ࠼ഗ‫ڦ‬੦዆ă
უഗൻ‫ۯ‬ഗǈट‫ںٷ‬०ࣅକ߰૗๕‫ۉ‬ᇸ‫ڦ‬ยऺăኄዖೌ
thus providing extremely high, long-term reliability and DAC7718 allows for bipolar outputs of up to ±16.5 V and
long life.
ฉՎუഗൻ‫ۯ‬ഗएԨྺᅃ߲ጲᆯና‫ږ‬ഗǈഄ‫ۆ‬႙ೕ୲ unipolar outputs of up DAC
ഄ໱ব‫ۉۅ‬ୟǈԈઔ to 33Ăྲ੦዆ഗࢅ๭݀ഗǈ਩ཚࡗᅃ
V.
Furthermore, the new Texas Instruments (TI) family of Because stage special-effects equipment uses unipolar
fOSC ྺ 400kHză޿ና‫ږ‬ഗൻ‫ۯ‬ଇ߲ࠀీഽ‫ڦٷ‬๼‫؜‬ৗ ߲‫ ڇ‬3.3-V ‫ۉ‬ᇸ߾ፕă߰૗‫ ڦ܋‬3.3-V ‫گ‬უইۙবഗǄTI ‫ڦ‬
isolated RS-485 transceivers possesses integrated trans- control voltages in the range of 0 to 10 V, the DAC7718 is
༹࠶ǈৗ༹࠶‫ࡗݒ‬ઠᆼൻ‫ۯ‬ᅃ߲ླྀྞ๕ದዃ঳ࠓ‫ྔڦ‬և
former drivers that drastically simplify the design of the TPS76333 ǅ੗ᅜ༵ࠃߛ‫ٳ‬
an ideal analog mA of‫ڦ‬๼‫ୁۉ؜‬ǈཞ้ᆛᆶ
150type
interface for this application,
؏ཀྵ๕Վუഗă၎‫ܔ‬ডߛ‫ڦ‬ೕ୲ሎႹ๑ᆩၭ႙Վუഗǈ
isolated power supply. The on-chip transformer driver is ࡗ‫ୁۉ‬၌዆ࢅࡗඤԍࢺࠀీă
enabling the control of up to eight light dimmers per
basically a free-running oscillator with a typical frequency,
ܸٗํ၄ᅃዖኝ༹ၭ႙ࣅยऺă network node.
fOSC, of 400 kHz. This oscillator drives two powerful output ၎࠲ྪበ
The remaining node circuitry, including the DAC, the
཮transistors,
5 ၂๖କ‫ࢇޙ‬ which in turn drive an
DMX512-A external center-tapped
Քጚ‫ڦ‬ᆌ‫ٴ‬ഗ‫ۉ‬ୟྜኝ঴ Interface.ti.com and the transceiver, operates from a single
microcontroller,
transformer in a push-pull
ਦ‫ݛ‬ӄăፕྺᅃዖ߰૗๕Ă3.3-V ‫ࡼࠀگ‬๭݀ഗǈ configuration. The relative high
TI ‫ڦ‬ 3.3-V supply. The 3.3-V low-dropout regulator (TI’s
frequency allows for the use of small transformers that TPS76333) on the isolated side provides up Ǆᆩ
www.ti.com/sc/device/partnumber DAC7718
to 150 mA of Ă
ISO35T ሞඇֶ‫ࠌࢅۯ‬ఇ޶ሜཉॲူǈ੗ྺ RS-485 Ք
enable an overall small-form-factor design. ISO35T Ă ISO1176T
output current Ă ISO3086T
along with overcurrentĂ and ther- ईኁ
MSP430F2132
limiting
ጚጺ၍႑ࡽ༵ࠃ
Figure 5 shows a1.5 V ‫ڦ‬ፌ‫ۉگ‬უࢅ
complete V ‫ۆڦ‬႙ֶ‫ۯ‬
solution for a2 responder cir- mal protection.
TPS76333 ༺࣑ྪ኷ዐ‫ڦ‬Đpartnumberđǅ
๼‫ۉ؜‬უăഗॲ‫ڦ‬ፌ‫ٷ‬ຕ਍໏୲ྺ
cuit that complies with DMX512-A. As 1Mbps ǈ੗ᅜ஢ፁ
an isolated, 3.3-V,
low-power transceiver, TI’sᄲ൱ǈཞ้
ISO35T provides RS-485- Related Web sites
DMX512-A ‫ ڦ‬250-kbps 200 ns ‫ื׊ڦ‬ই้
compliant bus signals with a 1.5-V minimum and a 2-V interface.ti.com
क़ԍኤକ‫߅ىۉگ‬ඡă www.ti.com/sc/device/partnumber
typical differential output voltage at full differential and
common-mode loading. The device’s maximum data rate Replace partnumber with DAC7718, ISO35T, ISO1176T,
ઠጲ DMX512 ጺ၍‫෇دڦ‬੦዆ຕ਍ǈঢ়ࡗ๼෇Բডഗ
of 1 Mbps satisfies the 250-kbps requirement of DMX512-A, ISO3086T, MSP430F2132, or TPS76333
ۙবǈ඗ࢫཚࡗ߰૗֫݀ྫথ๭ऐ๼‫܋؜‬ă R ዕ‫ڦ܋‬
཮ 5 ߰૗๕
Figure DMX512
5. Isolated ᆌ‫ٴ‬ഗব‫ۅ‬
DMX512 responder node
Isolation
TPS76333 Barrier
10 μF 3.3 V
OUT IN
GND EN
0.1 μF 0.1 μF 0.1 μF
10 V 0.1 μF
Input
VCC2 ISO35T
0.1 μF VCC1
DVCC DVDD AVDD
4 OSC
5 Data 1+ A MSP430F2132 IOVDD
R DAC0
3 B RXD
2 1 Data 1– RE SCLK SCLK 0- to 10-V
P3.2 DAC7718 Lighting-
Y MOSI SDI
D Control
2 1 Z TXD Signals
3 ISO- GND DE MISO SDO
5 P3.3 DAC7
4 DGND
GND2 GND1 DVSS AGND AVSS
Output ISO- GND
ZHCT140 23

ຕጴ߰૗ഗ߾ᄽຕ਍֑णথ੨
Industrial data-acquisition interfaces
with digital isolators
ፕኁǖ
By Thomas
Thomas Kugelstadt
Kugelstadt
‫ڤ‬ዝᅏഗ (TI) ߛपᆌᆩ߾‫ײ‬฾
Senior Applications Engineer
Galvanic isolation has become the mantra in the industrial
ᆯᇀႹ‫ۼࡀ݆ܠ‬ᄲ൱ሞ߾ᄽဣཥยऺዐํ၄‫߰ۉ‬૗ǈඟ ‫د‬ཥ߰૗ยऺ
of isolators and their operational principles. Application
engineering community as legal regulations call for its
߰૗ഗ‫ׯ‬କ߾ᄽ߾‫ײ‬ଶᇘ‫ڦ‬ᅃዖՂႜ൵๞ă‫߰ۉ‬૗ሎႹ examples are also provided.
๑ᆩ߰૗‫ٷݣ‬ഗ๟‫ۆ‬႙‫دڦ‬ཥยऺǈ཮ 1 ၂๖କᅃ߲‫ڇ‬
implementation in industrial system designs. Galvanic
ሞଇ߲ཚ႑‫ۅ‬ኮक़৊ႜ႑တ঍࣑ǈ‫ڍ‬ཞ้ፆኹํा‫ୁۉ‬ ཚ‫ڢ‬Ă߰૗࿒‫֪܈‬ଉ‫ۉ‬ୟǈ໲๟‫د‬ཥยऺ‫ڦ‬ঢ়‫ۆ‬૩ጱă
Legacy isolation designs
isolation allows for the exchange of information and power
ঢ়ࡗă
between two communicating points while preventing ኄ૛ǈᅃ߲ඤ‫ۉ‬౾ॽ֪‫ڥ‬࿒‫܈‬ገ࣑ྺ‫گ‬უ
A classic example of a legacy design using anDC ๼‫؜‬ăࢫ
isolation
actual current flow at the same time. amplifier is the single-channel,
௬‫ۉڦ‬ፆഗܾट࠶ྪஏǈཚࡗ༵ࠃ֡ፕ‫ۅ‬ೋዃĂց‫׋‬࿒ isolated temperature-
‫߰ۉ‬૗ᆶଇ߲ዷᄲ‫تࡻڦ‬ă๯ံǈ໲ԍࢺටᇵࢅยԢ௨
Galvanic isolation has two main benefits. First, it protects measurement circuit in Figure 1. Here a thermocouple
‫܈‬೏ᅎǈᅜत؊‫ߛืݴ‬๼෇ઠ೅ದ߰૗‫ٷݣ‬ഗ๼෇‫ۉ‬უ
๴ླ၃ഽ‫ۉߛࢅୁۉ‬უ‫ڦ‬ฅ࡞ăഄْǈ໲࣏ీࠕ‫ݞ‬ኹ‫؜‬
people and equipment from potentially dangerous current converts the measured temperature into a low-voltage DC
‫݆ݛڪྷݔ‬ǈํ၄‫ܔ‬๼෇႑ࡽ‫ۙڦ‬বă
and voltage surges. Second, it prevents the unintentional
၄࿮ᅪ๎থ‫࣍ں‬ୟยऺǈܸኄዖยऺࣷ߅ඡຕ਍૾ࢅഄ output. The following resistor-diode network conditions
design of ground loops, whose noise would otherwise inter- the input signal by providing operating-point biasing,
໱ࢻ૴႑ࡽă ߰૗‫ٷݣ‬ഗ๟ᅃዖ৛௢‫ٷݣ‬ഗǈഄ๑ᆩ቞੣Բۙ዆
fere with signals from data links and other interconnections. compensating for temperature drift, and boosting the
(DCM) ઠ‫ۉࡗح‬ඹ๕߰૗֫݀ໃ๼෇႑ࡽă
input sufficiently to match the input-voltage rangeDCM of the ԍ
Legacy designs of
‫د‬ཥ‫ڦ‬ᅃၵఇె analog
I/O I/O, instrumentation, motion-
Ăᅏ՗Ăሏ‫ۯ‬੦዆ࢅഄ໱‫ߌد‬ഗথ
control, and other sensor interfaces often used single- ኤକ‫ܔ‬Վࣅ‫߰ڦ‬૗֫༬Ⴀ‫ੇڦ‬ඡႠǈཞ้ྼ‫׼‬କ႑ࡽ
isolation amplifier.
੨ยऺǈཚ‫׉‬๑ᆩ‫ڇ‬ཚ‫߰ڢ‬૗‫ٷݣ‬ഗǈඟሏႜሞܱଝ߾ The isolation amplifier is a precision amplifier that uses
‫ྜڦ‬ኝႠăኄᄣǈ৽ํ၄କߛ੗੍Ⴀࢅଆࡻ‫ࠌڦ‬ఇຨ
channel isolation amplifiers to separate the sensor circuitry
‫כ׍‬क़࣍ৣူ‫ߌدڦ‬ഗ‫ۉ‬ୟǈᇑ࿮ሯ੦዆๪࣍ৣူ‫ڦ‬႑
in the harsh environment of the factory floor from the ༀ௨ᅧႠămodulation (DCM) to transmit the input signal
duty-cycle
ࡽ‫ت‬૙प߰૗ăሞरຍࢅยऺ‫ݛ‬௬ൽ‫ڦڥ‬ᅃၵ৊ቛǈׂ
signal-processing stage in the noise-free control-room across a capacitive isolation barrier. DCM ensures immunity
environment. Advancements in technology and design
ิକႹ‫ܠ‬ႎ‫ڦ‬ၭ႙Ă‫ࡼࠀگ‬ຕጴ߰૗ഗǈഄ‫ܠ‬ཚ‫ీࠀڢ‬ to varying barrier characteristics while maintaining signal
have led to new space- and power-saving digital isolators integrity. This results in high reliability and good common-
ඟยԢยऺ߸ेၭ႙ࣅăԨ࿔ॽྺ౞঻ถ߰૗ഗ‫ڦ‬ૌ႙ mode transient immunity.
whose multichannel capability permits equipment designs
तഄ߾ፕᇱ૙ăଷྔǈ࿔ቤ࣏ଚਉକຕ߲ํ૩ă
with smaller form factors. This article explains both types
཮ 1 ߰૗࿒‫֪܈‬ଉ
Figure 1. Isolated temperature measurement
Isothermal 10 V
Block REF 15 V
(VS1)
6.04 k
150 k
77.7 k
10 k
10 V
2.94 k
549 k 15 V –15 V
– (VS2 )
Thermocouple Amp
200 +
Isolation VOUT
6.04 k 60.4 Amp
5.1 V
24

ഗॲాևཚࡗଇ߲೅ದ‫ۉ‬ඹํ၄କ๼෇ࢅ๼‫؜‬և‫ۉݴ‬ ৑࠶߰૗‫ٷݣ‬ഗਏᆶߛጚඓႠࢅߛ੗੍Ⴀ‫ڦ‬ᆫ‫ۅ‬ǈ‫ڍ‬ᄺ٪
Inside the device, the input and output sections are average value of VOUT equal to VIN. The sample-and-hold
߰૗Ǆ൩֖९཮ ǅă๼෇և‫ݴ‬ཚࡗᅃ߲๼෇‫ۉ‬ፆഗ
galvanically isolated2 by two matched capacitors (see
ሞᅃၵरຍඍ‫ۅ‬ăኄၵ‫ٷݣ‬ഗ‫ڦ‬๼෇႑ࡽ‫੻ټ‬ড‫گ‬ǈᅃӯ
(S/H) amplifiers in the feedback loop remove undesired
RIN ǈॽ๼෇‫ۉ‬უ
Figure 2). The inputVIN ገ࣑ྺ๼෇‫ୁۉ‬
section IINă‫ٷݣ‬ഗ
converts the input voltage, A1 ၭᇀ 50 kHz
voltage ăഄ
ripples ±4 V ‫ڦ‬ፌ‫ۉگ‬ᇸᄲ൱ǈ࿮݆ྺ၄‫گڦپ‬უ
inherent in the demodulation process.
ԥದዃྺᅃ߲ओ‫ݴ‬ഗǈ‫ܔ‬ , viaࢅ‫ୁۉ‬ᇸኮֶ൱ओ‫ݴ‬ǈ኱
VIN, into an input current, IINIIN an input resistor, RIN. ยऺ༵ࠃኧ‫׼‬ă໲்๑ᆩߛ‫ׯ‬Ԩ‫ڦ‬዆ሰ߾ᅝǈᄲ൱๼෇ႊ
Isolation amplifiers, while highly accurate and reliable,
Configured as an integrator, amplifier A1 integrates the
዁‫ࢫ؜ג‬௬Բডഗ‫ڦ‬๼෇ពኵăԲডഗࢅ‫ٷݣ؜܁‬ഗ have several technological drawbacks. These amplifiers
ೌࢅ๼‫؜‬ႊೌ‫ݴ‬ਸิׂǈ૧ᆩघ࠼Ⴊኝरຍइ‫ڥ‬৛௢‫ۉڦ‬
difference between IIN and the current source until the possess a low input-signal bandwidth no greater than
AS1 ᅃഐ೨๑‫ୁۉ‬ᇸሞాև 500-kHz ና‫ږ‬ഗೕ୲ူਸ࠲ ୟ೅ದǈፌࢫምॽଇዖႊೌጎದሞᅃഐǈӝᅃၵ߰૗‫ۉ‬ඹ
input threshold of the following comparator is exceeded. 50 kHz. Their requirement for a minimum power supply of
ገ࣑ă໯‫ڦڟڥ‬৊෇‫ۉ‬ඹ๕߰૗֫‫ڦ‬ൻ‫ۯ‬႑ࡽǈྺᅃዖ
Together, the comparator and the sense amplifier, AS1, ण‫ڟׯ‬ᅃ߲‫ހ‬ጎዐă
±4 V does not support modern low-voltage designs. Their
ࢻցႠĂঢ়቞੣Բۙ዆‫ݛڦ‬հă
force the current source to switch at the frequency of the expensive manufacturing process requires the separate
internal 500-kHz oscillator. The resulting drive signal into ၄‫߰پ‬૗ยऺ
fabrication of input and output chips, laser trimming for
๼‫؜‬և‫ݴ‬ཚࡗೝ࿘‫گ‬ཚ୳հǈ‫ܔ‬ઠጲ߰૗֫‫ڦ‬႑ࡽ৊ႜ
the capacitive barrier is a complementary, duty-cycle- ၄‫ڦپ‬ຕ਍֑णยऺ਩๑ᆩఇຕገ࣑ഗ
precise circuit matching, and final assembly(ADC) ǈኄၵገ࣑
of both chips
঴ۙă‫ٷݣ؜܁‬ഗ
modulated square wave.AS2 ॠ֪ཚࡗ߰૗֫‫ڦ‬႑ࡽሂദǈॽ together with the isolation
ഗ‫ڦ‬๼෇ԥ‫ܠ‬ୟ‫د‬๼዁ᅃཉ‫ڇ‬ཚ‫ۙڢ‬বཚୟዐǄ൩֖९཮ capacitors into one package.
The output section
ൻ‫ۯ‬ঢ়ࡗਸ࠲ገ࣑‫ୁۉڦ‬ᇸ৊෇ओ‫ݴ‬ഗ demodulates the signalA2from the iso-
ăኄᅃपߵ 3ǅăᅃ߲੗Պ‫ײ‬ሺᅮ‫ٷݣ‬ഗ
Modern isolation designs(PGA) ሺഽෑ๼෇႑ࡽǈ඗ࢫ
lation barrier through a balanced low-pass filtering. Sense
਍ RF ‫ݒڦ‬ઍ‫ୁۉ‬ǈ‫ܔ‬቞੣Բۙ዆‫ୁۉڦ‬৊ႜೝ࿘ǈٗ ገ࣑ഗ‫ܔ‬႑ࡽ৊ႜ ΔΣ ۙ዆ǈॽഄገ࣑ྺຕጴຕ਍ୁăኮ
Modern data-acquisition designs use analog-to-digital
amplifier AS2 detects signal transitions across the barrier
ܸ‫ڟڥ‬ VOUTa‫ڦ‬ೝ਩ኵ
and drives switched (V OUT=VIN
current )ă‫ݒ‬ઍ࣍ୟዐ‫ڦ‬ൽᄣԍ‫׼‬
source into integrator A2. converters (ADCs) whose inputs are multiplexed into a
ࢫǈॽຕጴገ࣑঳ࡕཚࡗຕጴ߰૗ഗ݀ໃߴဣཥ੦዆ഗǈ
(S/H) ‫ٷݣ‬ഗǈඁ‫أ‬କ঴ۙࡗ‫ײ‬ዐࠦᆶ‫ܠڦ‬ᇆ‫ۉ‬უ࿖հă
This stage balances the duty-cycle-modulated current single-channel conditioning path (see Figure 3). A pro-
ሞຕጴᇘዐ৊ᅃօ‫ت‬૙ă
against the feedback current through RF, thus yielding an grammable gain amplifier (PGA) boosts the weak input
཮ 2 ߰૗‫ٷݣ‬ഗాև঳ࠓ
Figure 2. Inside the isolation amplifier
Isolation Barrier
AS1 AS2
R IN RF
VIN VOUT
– –
A1 A2
+ +
S/H S/H
Gain = 1 Gain = 6
OSC
+VS1 GND1 –VS1 +VS2 GND2 –VS2
཮ 3 ߰૗ຕ਍֑णဣཥ
Figure 3. Isolated data-acquisition system
MUX-Input ADC
Isolators
AIN1+
3
AIN1–
Digital
4:1 PGA
Temperature Input ADC Interface 2 System
Sensors Controller
MUX
AIN4+ 3
AIN4– OSC Control
Multiple Devices
25

߾ᄽᆌᆩ
ຕጴ߰૗ഗ੗ᅜᆶ߳ዖ߳ᄣ‫߰ڦ‬૗֫ǈഄ੗ᅜ๑ᆩ‫ى‬Ă
signal, and the converter applies delta-sigma modulation to Because low-speed signals lack sufficient transitions to
࠼‫ۉ‬ईኁ‫ۉ‬ඹ๕߰૗रຍă཮ 4 ໯๖߰૗ഗՍ๟एᇀ‫ۉ‬
the signal to convert it to a digital data stream. The digital- ଇዖፌ‫׉‬९‫߾ڦ‬ᄽຕ਍֑णဣཥᆌᆩ๟ิׂࡗ‫ײ‬੦዆ࢅ߾
easily cross the tiny isolation capacitors, the carrier fre-
conversion results are
ඹ๕߰૗֫रຍăഗॲᆯଇཉժႜຕ਍ཚ‫ڢ‬ፇ‫ׯ‬ǖᅃཉ then transmitted across the digital ‫׍‬ጲ‫ࣅۯ‬ăิׂࡗ‫ײ‬੦዆ဣཥᅃӯࣷॠ֪ईኁ֪ଉᅃ߲ဣ
quency of an internal oscillator is applied to them via a
isolator to a system controller for further processing in the pulse-width modulator (PWM). Past the barrier, a low-pass
ཥాև‫߲ܠڦ‬࿿૙ଉǈ૩සǖ࿒‫ࢅ܈‬უ૰‫ڪ‬ǈܸ߾‫׍‬ጲ‫ۯ‬
ߛ໏ AC ཚ‫ڢ‬ǈ‫ ྺ੻ټ‬100 kbps ‫ ڟ‬150 MbpsǗᅃཉ‫گ‬
digital domain. filter (LPF) removes the high-frequency content from the
໏ Digital
DC ཚ‫ڢ‬ǈ‫ྺྷݔ‬ ‫ ڟ‬DCisolation
ă ࣅᅃӯ֪॔‫߲ܠ‬ဣཥ‫ڦ‬ᅃ߲࿿૙ଉăᅺُǈ௅ዖᆌᆩ๑ᆩ
isolators can 100 kbpsvarious
possess barriers actual data prior to passing it on to the output multiplexer.
that use magnetic, optoelectric, or capacitive isolation ‫ڦ‬ຕ਍ገ࣑ഗದዃ‫ۼ‬टྺփཞăิׂࡗ‫ײ‬੦዆ဣཥᆶ‫ٷ‬ଉ
߰૗ഗాևǈཚࡗᅃၵ‫ݒ‬၎ࢅ‫ݒݥ‬၎๼෇࣐؋ഗǈ৊෇
technologies. The isolator in Figure 4 is based on a capaci- Industrial applications
փཞૌ႙‫ߌدڦ‬ഗࢅገ࣑ഗǈᄲ൱৊ႜ‫ٷ‬ଉ‫ڦ‬ሺᅮĂ֑ᄣ
tiveཚ‫܋ڇڦڢ‬๼෇႑ࡽԥገ࣑ྺೝ࢚႑ࡽăኮࢫǈ
AC RC
isolation-barrier technique. The device consists of two The two most common applications for industrial data-
໏୲Ăዘް֪ଉࢅፆੇ࣐؋‫֖ڪ‬ຕยዃăᇑኮႚ‫ׯ‬း௽‫ܔ‬
parallel data channels, a high-speed AC channel with a
ྪஏॽ႑ࡽ൶‫ྺݴ‬Ⴙ‫ܠ‬ຨༀǈԲডഗॽኄၵຨༀገ࣑ྺ acquisition systems are in process control and factory
Բ‫ڦ‬๟ǈ߾‫׍‬ጲ‫ࣅۯ‬ཚ‫׉‬๑ᆩᅃၵ၎ཞૌ႙‫ߌدڦ‬ഗǈᅺ
bandwidth ranging from 100 kbps up to 150 Mbps, and a automation. Process-control systems typically detect or
‫܌‬ஞ؋ăፌࢫǈᅃ߲‫݀ة‬ഗምॽኄၵஞ؋ገ࣑ྺ๼‫؜‬ ُኻႴटณ‫֖ڦ‬ຕยዃă
low-speed DC channel covering the range from 100 kbps measure multiple physical quantities, such as temperature
႑ࡽǈኄၵ႑ࡽሞ၎࿋ࢅႚༀ‫ݛ‬௬ᇑᇱ๔๼෇႑ࡽྜ and pressure, within one system, while factory automation
down to DC.
ඇᅃᄣă ᆯᇀ֖ຕยዃᆖၚ߰૗ยऺ‫߾ڦ‬ፕଉǈᄺᆖၚຕጴথ੨ย
usually monitors one physical quantity across multiple sys-
Inside the isolator, a single-ended input signal entering
the AC channel is converted into a balanced signal through ऺ‫ڦ‬၎࠲‫ׯ‬Ԩǈᅺُକ঴ิׂࡗ‫ײ‬੦዆ࢅ߾‫׍‬ጲ‫ࣅۯ‬ଇኁ
tems. Consequently, the configuration of data converters
ᅜ॔๫ऺ้ഗႚ๕٪ሞ‫ڦ‬ಒۨஇड (DCL)
inverting and non-inverting input buffers. RC ǈ‫ܔ‬႑ࡽຨༀ
networks ኮक़‫ڦ‬൶՚৽ᆮྺዘᄲă཮
used in each application differs ࢅ཮ 6 ௮ຎକຕ਍֑णဣ
5 significantly. Process-
ኮक़‫׼ڦ‬Ⴤ้क़৊ႜ֪ۨăසࡕଇ߲૶Ⴤຨༀኮक़‫׼ڦ‬
then differentiate the signal into transients, and compara- control systems addressing
ཥ‫ڦ‬ଇዖ‫ۆ‬႙ยऺǈᅜຫ௽ഄ٪ሞ‫ֶڦ‬՚ă a wide range of sensor and
tors convert the transients into short pulses. A final flip-
Ⴤ้क़‫؜ג‬ፌ‫้ٷ‬क़‫ش‬੨Ǆᇑ‫گ‬ೕ႑ࡽ൧઄ᅃᄣǅǈሶ transducer types require a wide range of parametric set-
flop then converts these pulses into an output signal that tings for gain, sampling rate, measurement repetition, and
๼‫ܠ؜‬ୟۙ዆ഗᆯߛ໏ ACཚ‫ڢ‬ൎ࣑ྺ‫گ‬໏DCཚ‫ڢ‬ă
is identical in phase and shape to the original input signal. impedance buffering. In strong contrast, factory automa-
A decision logic (DCL) in the form of a watchdog timer tion often gets along with monitoring multiple sensors of
ᆯᇀ‫گ‬໏႑ࡽ‫ࡗح‬ၭ႙߰૗‫ۉ‬ඹ‫ీڦ‬૰ᆶ၌ǈᅺُႴᄲ
measures the durations between signal transients. If the the same type, thus requiring only a minimum number of
ཚࡗᅃ߲ஞ੻ۙ዆ഗ(PWM) ߴ໲்ᆌᆩాևና‫ږ‬ഗ‫ڦ‬ parametric settings.
duration between two consecutive transients exceeds the
ሜհೕ୲ăཚࡗ߰૗֫ᅜࢫǈሞीჄ‫د‬ໃߴ๼‫ܠ؜‬ୟۙ
maximum time window (as in the case of a low-frequency Because the number of parametric settings impacts the
዆ഗᅜമǈႴ๑ᆩ‫گ‬ཚ୳հഗ
signal), the output multiplexer is(LPF) ॽߛೕాඹٗํा
switched from the high- isolation efforts and the associated costs of the digital-
speed
ຕ਍ዐඁ‫أ‬ă AC to the low-speed DC channel. interface design, it is important to distinguish between
཮ 4 ຕጴ‫ۉ‬ඹ߰૗ഗ
Figure 4. Digital capacitive isolator
OSC
PWM VREF
LPF
DC Channel (DC to 100 kbps) 0

IN OUT
AC Channel (100 kbps to 150 Mbps) 1 S
DCL
VREF
26

process
཮ control and factory automation. Two typical designs
5 ໯๖ದዃዐǈ߳ዖ߳ᄣ‫ߌدڦ‬ഗ޶ሴ֪ଉ߳ዖ࿿૙ ዆၍ୟă
different types of equipment continuously. While this design
of a data-acquisition system are shown in Figures 5 and 6
ଉǈ૩සǖ࿒‫܈‬Ăუ૰ࢅ‫ڪୁۉ‬ă࿢்Ⴔᄲྺ௅ᅃዖ‫د‬ uses the same ADC as in Figure 5, the uniform sensor
to illustrate the difference. ঳ஃ
characteristics allow the settings for gain and sample rate
ߌഗยዃփཞ‫ڦ‬ሺᅮǈᅜํ၄ variety๼෇‫ۯ‬ༀ‫ྷݔ‬ፌ‫ٷ‬
In the Figure 5 configuration, a ADC of sensors mea- to be fixed and the power-down feature to be disabled.
߰૗‫ٷݣ‬ഗᅙঢ়ࡗ้କǈຕጴ߰૗ഗ֍๟ୁႜ൵๞ăැ
ࣅăྺକ೅ದగၵ๼෇ཚ‫ڦڢ‬Վࣅ໏୲ǈՂႴ‫֑ܔ‬ᄣ໏
sure different quantities such as temperature, pressure, This system configuration drastically reduces isolation
ၙবูยऺ้क़ࢅӱप੣क़ǈᅜतই‫֌گ‬ଙ‫ׯ‬Ԩǈሞਦ
୲৊ႜൎ࣑ăሞுᆶኴႜ֪ଉඪခ้ǈ੗ᅜ๑ᆩู‫ࠀۉ‬
and current. Various gain settings maximize the input requirements because there are only four lines for data
dynamic range ۨ๑ᆩనዖ߰૗ഗᅜമ౞ՂႷ૙঴ဣཥᄲ൱ă
ీઠবู ADC of the ADC for each sensor. Switching
ࠀ୲ăኄዖ‫ీࠀܠ‬ᄲ൱‫ٳܠ‬ 8 ཉ߰૗੦዆ and control.
between sampling rates might be necessary to match the
ཚ‫ڢ‬ă Conclusion
֖੊࿔၅
rate of change at certain input channels. An optional
power-down feature preserves ADC power when measure- සIsolation
ᇡକ঴ amplifiers
Ԩ ࿔ ၎are ࠲ out,
߸ ‫ܠ‬andၘ digital
൧ǈ৤ isolators
൩‫ݡ‬࿚ are in. To
၎Բኮူǈ཮ 6 ໯๖ದዃዐǈ4 ߲၎ཞૌ႙‫ڦ‬ඤ‫ۉ‬౾޶ w w w.
ments are not performed. This high versatility necessitates save design time and board space and to keep the cost of
ሴ‫׼‬Ⴤ֪ଉ߳ዖยԢ‫ڦ‬࿒‫܈‬ă৑࠶ኄዖยऺ๑ᆩକᇑ཮ 5 ti.com/lit/litnumber Ǆᆩ TI ࿔ॲՊࡽ༺࣑ྪ኷ዐ‫ڦ‬
up to eight isolated control channels. materials down, it is imperative to understand the system
® ®
໯๖၎ཞ‫ڦ‬ ADC
By contrast, ǈ‫ڍ‬๟ཥᅃ‫ߌدڦ‬ഗ༬ႠሎႹࠦۨփՎ
in the Figure 6 configuration, four thermo- Đ litnumberđǅǈူሜ
requirements Acrobat
before deciding Reader
what type ߭๕࿔ॲǈ
of isolator to use.
‫ڦ‬ሺᅮࢅ֑ᄣ໏୲ยዃǈᄺሎႹ࠲Կู‫ీࠀۉ‬ăኄዖဣ
couples of the same type measure the temperatures of इൽူଚ֖੊ጨଙăāāā
ཥದዃट‫ںٷ‬ই‫گ‬କ߰૗ᄲ൱ǈᅺྺኻᆶ 4 ཉຕ਍ࢅ੦
཮ 5 ิׂࡗ‫ײ‬੦዆‫߰ڦ‬૗ຕ਍֑णဣཥ
Figure 5. Isolated data-acquisition system for process control
VIN
0.1 μF 10 μF 3.3 V
1,2,16
VIN
0.1 μF TPS55010
13
MBR0520L BOOT 8
10,11,12 RT/CLK
5 VISO PH 7
6 COMP 511 k
47 μF VSNS GND
10 nF
5 VISO 5 VISO 16.5 k 3,4,5
0.1 μF 0.1 μF 10 k
4.7 μF 3.3 V 0.1 μF
22 1 5 VISO 3.3 V 2
AVDD DVDD ISO7241C
16 1 DVCC
ADS1234 VCC2 VCC1
0.1 μF 10 7 0.1 μF
11 EN 2 EN1 MSP430F2132
AIN1+ 8 14 3 11 5
A0 OUTA INA P3.0 XOUT
RTD 12 7 13 4 12
AIN1– A1 OUTB INB P3.1
27 12 IN 5 14 6
SCLK OUTC C CLK XIN
18 28 11 6 13 18
Bridge AIN2+ DOUT IND OUTD SOMI P3.7
5 VISO 9,15 2,8 17
17 GND2 GND1 P3.6
AIN2– 5 VISO 3.3 V 15 16
20 ISO7240C P3.4 P3.5
REF+ 16 1 DVSS
13 19 0.1 μF VCC2 VCC1
AIN3+ REF– 0.1 μF 10 7 0.1 μF 4
14 EN NC
AIN3– 23 14 3
Thermocouple GAIN0 OUTA INA
24 13 4
GAIN1 OUTB INB
16
AIN4+ 25 12 IN 5
Current SPEED OUTC C
Shunt 15 26 11 6
AIN4 – PWDN OUTD IND
AGND DGND 9,15 2,8
GND2 GND1
21 2
27

࿔၅Ք༶
References TI࿔၅Պࡽ ၎࠲ྪበ
Related Web sites
1For
Ă more information related to this article,
Ėຕጴ߰૗ഗยऺėǈፕኁǖ you can down-
Thomas interface.ti.com
interface.ti.com
load an Acrobat® Reader® file at www.ti.com/lit/litnumber www.ti.com/sc/device/partnumber
Kugelstadtǈ݀՗ᇀĖఇెᆌᆩሗኾėǄ2010 ౎‫ڼ‬ Www.ti.com/sc/device/partnumber Ǆᆩ
and replace “litnumber” with the TI Lit. # for the Replace partnumber with ADS1234, ISO7240C,
ल‫܈‬਽ǅlisted
2materials
below. slyt335 12 3 4 Ă I S O 7or2TPS55010
A D SMSP430F2132,
ISO7241C, 40CĂISO7241CĂ
2ĂĖຕጴ‫ۉ‬ඹ๕߰૗ഗ‫ੇׇىڦ‬ඡ‫܈‬ėǈፕኁǖ MSP430F2132ईኁ TPS55010༺࣑ྪ኷ዐ‫ڦ‬
Document Title TI Lit. #
Thomas
1. ThomasKugelstadt ǈ݀՗ᇀĖఇెᆌᆩሗኾė
Kugelstadt, “Designing with digital Đpartnumberđǅ
Ǆ2010 ౎‫ ڼ‬3Analog
isolators,” ल‫܈‬਽ǅ
Applications Journal slyt381
(2Q 2009) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .slyt335
2. Thomas Kugelstadt, “Magnetic-field immunity
of digital capacitive isolators,” Analog
Applications Journal (3Q 2010) . . . . . . . . . . . .slyt381
཮ 6 ߾‫׍‬ጲ‫߰ڦࣅۯ‬૗ຕ਍֑णဣཥ
Figure 6. Isolated data-acquisition system in factory automation
VIN
0.1 μF 10 μF 3.3 V
5 VISO 5 VISO 1,2,16
0.1 μF 0.1 μF VIN
0.1 μF TPS55010
22 1 13
MBR0520L BOOT 8
AVDD DVDD 10,11,12 RT/CLK
5 VISO 5 VISO PH
ADS1234 7
11 6 COMP 511 k
AIN1+ 23 47 μF VSNS GND
GAIN0 10 nF
K-Type 12 24 0.1 μF 16.5 k
AIN1– GAIN1 3,4,5
Thermocouple 25
SPEED 10 k
18 26 4.7 μF
AIN2+ PWDN
5 VISO 3.3 V 0.1 μF
K-Type 17
AIN2– 5 VISO
Thermocouple 3.3 V
REF+
20 ISO7241C 2
0.1 μF 16 1
13 19 VCC2 VCC1 DVCC
AIN3+ REF– 0.1 μF 10 7 0.1 μF
K-Type 14 EN2 EN1 MSP430F2132
AIN3– 8 14 3 11 5
Thermocouple A0 OUTA INA P3.0 XOUT
7 13 4 12
A1 OUTB INB P3.1
16
AIN4+ 27 12 IN 5 14 6
SCLK OUTC C CLK XIN
K-Type 15 28 11 6 13
AIN4 – DOUT IND OUTD SOMI
Thermocouple 9,15 2,8
AGND DGND GND2 GND1 DVSS
21 2 4
28 ZHCT141

Texas Instruments Incorporated Amplifiers: Op Amps
‫ۉڇ‬ᇸဣཥዐ‫܋ڇ‬๫ೕ‫ۯֶڟ‬๫ೕ‫ڦ‬ገ࣑
Converting single-ended video to differential
video in single-supply systems
ፕኁǖ
By JimJim Karki
Karki
‫ڤ‬ዝᅏഗ (TI)
Member, TechnicalߛႠీఇెׂ೗ํᄓ๪ჺ৯ፇ‫ׯ‬ᇵ
Staff, High-Performance Analog
ᆅჾ
Introduction ཮ 1 ၂๖ࣨ‫ڦ܈‬
Figure SD ްࢇ๫ೕए‫ټ‬႑ࡽ
1. SD composite (CVBS)
video baseband signal (CVBS) showing grayscale
๫ೕ႑ࡽ‫׉׉‬ፕྺ‫܋ڇ‬႑ࡽԥ
Video signals are commonly
encoded, decoded, and pro-
ՊஓĂ঴ஓࢅ‫ت‬૙ǈ‫ڍ‬๟ට் IRE Units
cessed as single-ended, but it is NTSC PAL
ཚ‫׉‬ထྭॽഄገ࣑ྺֶ‫ۯ‬႑ 100
often desirable to convert them
ࡽ differential
to ǈᅜཚࡗ၍ forમtransmission
৊ႜ‫د‬๼ă 80
Ҿඇ ဣ ཥ Ս ๟ ᅃ ߲ ‫ ۆ‬႙ ‫ڦ‬is૩a
over cables. A good example
60
security
ጱǈഄฝ system
ၟ ཀྵ where
Ҿጎሞ cameras
փཞ‫ڦ‬ Sync +0.714 V +0.700 V
are placed in various 40 Pulse
࿋ዃ ǈ๫ೕ ႑ ࡽ ཚlocations
ࡗ၍ୟԥ Y
and the video feeds are routed 20
‫࣮د‬ዐᄕ‫ڇ‬ᇮǈํ၄॔੦ࢅ
back to a central location for
ຕ਍٪‫ీࠀئ‬ă
observation and storage. 0
Because of its inherent resist- –20 – 0.286 V – 0.300 V
ᅺഄࠦᆶ‫ੇڦ‬ሯำ༬Ⴀǈֶ‫ۯ‬
ance to noise, differential trans- – 40
‫د‬๼‫׊‬೺ᅜઠᅃ኱ᆩᇀ‫ࣆۉ‬၍
mission has been used for many
years in telephone lines and
ୟࢅጆᄽᅼೕᆌᆩăሯำ᳘ࢇ
professional audio. Assuming
዁ֶ‫دۯ‬๼၍ୟዐ้ǈ໲ࣷᅜᅃዖ๴‫ڟ‬ᅞ዆‫ࠌڦ‬ఇ႑ࡽ
noise is coupled equally into the differential transmission ᄲ൱߸‫ڦܠ‬ፇॲǈ‫ׯ‬Ԩᄺ߸ߛă DC ᳘ࢇ੗ᅜই‫ׯگ‬Ԩǈ
fully modulated composite video signal is about 1.23 VPP.
ႚ๕‫؜‬၄ሞথ๭ഗ‫܋‬ă
line(s), it shows up at the receiver as a common-mode ‫ڍ‬๟߀ᆩኧ‫ۉڇ׼‬ᇸ‫ڦ‬ DC ᳘ࢇ႑ࡽᄲ൱‫ܔ‬႑ࡽ৊ႜ‫ۉ‬
To support the negative pulse, split-supply (±VS) opera-
signal that is rejected. ೝገ࣑ă૩සǈ TIābeTMS320DM368
tional amplifiers can ๫ೕ‫ت‬૙ഗ‫ׂڦ‬೗
used, or AC coupling where the DC
ໜጣ‫ۉڇ‬ᇸยԢՎ‫ڥ‬ሁઠሁ೵Փǈॽ၍ൻ‫ۉۯ‬ୟᄺยऺ
With single-supply devices becoming more and more levels are restored at the
ຫ௽ກǈࡀۨ๫ೕ࣐؋ഗሞ 75Ω ޶ሜ้‫ڦ‬๼‫ۉ؜‬უ‫ྷݔ‬receiver. Using a split supply or
‫ۉڇׯ‬ᇸ࿄‫׈‬փ๟ᅃዖࡻ‫ڦ‬Ӹ݆ăሞ‫ۉڇ‬ᇸဣཥዐǈ႑
common these days, it is nice to design the line-drive AC coupling requires more components and is more costly.
ྺ 0.35 V ‫ ڟ‬1.35 V ăኄᄣǈ੗ᅜཚࡗೋዃ‫ۉ‬ೝገ࣑ኧ
ࡽ‫ۉ‬ೝঢ়ࡗገ࣑ᅜ๢ᆌ‫ۉ‬ᇸ‫ۉ‬უǈཞ้࣏ᄲ੊୯ೋዃ‫ۉ‬
circuit to be single-supply as well. In single-supply systems, DC coupling can lower cost, but moving to DC-coupled
the signal levels are shifted to fit within the supply voltage, ‫׼‬
signals that ๫ೕ႑ࡽǈܸኄ‫ܔ‬ၩ‫ݯ‬ૌ๫ೕܸჾ๟੗ᅜথ
1-VPP support a single supply requires level shifting
ೝǈᅜՍփׂࣷิ༪ᄋ‫ڦ‬๼‫؜‬ೋᅎଉăଷྔǈ࣏Ⴔᄲፔ
and the bias levels need to be accounted for so as not to ๴‫ڦ‬ă
the signal. For example, the data sheet of the Texas
ᅃၵೝ‫߾ڦ׉‬ፕǈ૩සǖሺᅮยዃĂ၍ୟ‫܋‬থૌ႙჋ስ
cause unwanted offsets in the output. These tasks are Instruments (TI) TMS320DM368 video processor specifies
ᅜत‫ڟٳ‬ፁࠕ‫ࢅ੻ټڦ‬ገ࣑໏୲‫ڪ‬ă
aside from the normal ones like setting gains, choosing the ഄ໱ߛൣ๫ೕ߭๕ǈ૩සǖሺഽൣည‫܈‬ (ED)V ࢅߛൣည‫܈‬
video-buffer output voltages ranging from 0.35 to 1.35 V
type of line termination, and allowing for adequate band- with a‫ڪ‬ǈփࣷၟ
(HD) 75-: load. InSD way, a 1-VPP video signal can be
thisఫᄣॽ‫ٷ‬ଉփཞ႑တ‫ۼ‬Պஓ‫ڟ‬ᅃཉ
࿢்੗ᅜ૧ᆩ‫܋ڇ‬๼‫؜‬ሏ໙‫ٷݣ‬ഗईኁඇֶ‫ٷݣۯ‬ഗ
width and slew rate. supported with a shift in bias level and is acceptable in
၍ୟዐă໲்ࣷߵ਍๫ೕాඹࢅࡀ‫ݔ‬ǈ๑ᆩ‫ܠ‬ཉ၍ୟઠ
(FDA) ॽ‫܋ڇ‬๫ೕገ࣑ྺֶ‫ۯ‬๫ೕăԨ࿔‫ڦ‬ణ‫ڦ‬๟ၠ౞
Single-ended-output operational amplifiers or fully consumer video.
‫د‬๼փཞ‫׼‬Ⴤ้क़ࢅ‫د‬๼໏‫ڦ܈‬႑ࡽă
঻ถසࢆ๑ᆩᅃ߲
differential amplifiersFDA ॽ‫܋ڇ‬๫ೕ႑ࡽገ࣑ྺֶ‫ۯ‬႑
(FDAs) can be used to convert Other higher-definition video formats like enhanced-
single-ended
ࡽǈᅜሞ‫ۉڇ‬ᇸဣཥዐൻ‫ۯ‬ᅃཉມ‫܋‬থvideo signals to differential. The purpose
5 ૌǄ Cat of
5ǅ definition (ED) and high-definition (HD) do not encode as
๫ೕ႑ࡽԨวྺஞ؋႙ǈᅺُ‫ٷݣ‬ഗࢅ‫د‬๼঻ዊႴᄲᆶ
this article is to show how to use an FDA to convert single- much different information into one line as SD. They use
၍મă࿢்्ย‫܁‬ኁຄဒ FDA ߁౒ࢅ๑ᆩ‫݆ݛ‬ăFDA ᆫᅴ‫ڦ‬ஞ؋༬Ⴀ֍ీྜඇኟඓ‫ں‬ዘ၄໲்ăኟᅺසُǈ
ended video signals to differential to drive a Cat 5 cable multiple lines with signals of varying duration and transition
ए‫ၘܠ߸ڦإ‬൧ǈ൩֖९֖੊࿔၅
with double termination in a single-supply 1ă system. It is ๑ᆩມ‫܋‬থ‫د‬๼၍ୟ๟ᅃዖՔጚ‫݆ݛ‬ăሞມ‫܋‬থዐǈൻ
speed depending on the video content and specification.
assumed that the reader is familiar with FDA concepts So video signals are pulse-oriented by nature, and ampli-
‫ۯ‬၍ୟ‫ٷݣڦ‬ഗԨวਏᆶᇑ༬Ⴀ၍ୟፆੇ၎ཞ‫ڦ‬๼‫؜‬ፆ
‫ۆ‬႙๫ೕ֖ຕ
and use. For more information on FDA fundamentals, fiers and transmission media need to have excellent pulse
ੇǈܸথ๭ऐԨวᄺᆶᇑ༬Ⴀ၍ୟፆੇ၎ཞ‫ڦ‬๼෇ፆ
཮ 1 ྺᅃ߲ްࢇ๫ೕए‫ټ‬႑ࡽ
please see Reference 1. (CVBS)ǈഄ၂๖କ࿢் characteristics to properly reproduce them. Because of
ੇă૧ᆩኄዖದዃǈஞ؋ᄂ‫ݒڦ‬พԥፌၭࣅǈժ൐ԍ‫׼‬
this, it is standard practice to use double termination of
ঢ় ‫׉‬๑ᆩ‫ڦ‬Քጚൣည‫܈‬
Typical (SD) ๫ೕ‫܈ࣨڦ‬ăSD ๫ೕ༬
video parameters କፌॅ႑ࡽྜኝႠăᆯᇀሞ૙ၙ൧઄ူሏ໙‫ٷݣ‬ഗ๟ᅃ
the transmission line. In double termination, the amplifier
Ⴀᅃӯ‫ࢇޙ‬ఇె႑ࡽՔጚăኄ๟ᅃዖጆྺ
Figure 1 shows a composite video baseband signalNTSC ईኁ
(CVBS) ၵ‫ۉ‬უᇸǈᅺُഄ๼‫؜‬ਏᆶट‫ڦگ‬ፆੇǄথৎ 0Ω ǅǈ
driving the line is designed to have the same output imped-
PAL ‫ۉ‬๫࠽խဣཥ዆ۨ‫ڦ‬ᅃዖՔጚăࡀۨጺ‫ރ‬዁‫ރ‬๼
showing grayscale that is often used with standard- ance as the characteristic line impedance, and the receiver
ኻႴཁेᅃ߲‫૴ز‬๼‫ۉ؜‬ፆഗՍ੗ൟ຿ํ၄๼‫؜‬ፆੇ೅
definition
‫ۉ؜‬უྺ (SD) 140 video.
IRE =SD 1 video characteristics typically
VPPǈ‫ك‬ཞօଋ‫܈‬Ǆ Yďǅ้ǈ is designed to have the same input impedance as the
follow the analog-signal standards established for the NTSC ದă޿๼‫ۉ؜‬ፆഗᇑথ๭ഗ‫ڦ‬๼෇ፆੇᅃഐǈ‫ڟڥ‬6-dB
ཞօஞ؋ྺ޶ăሺे෥‫܈‬႑တᅜࢫǈྜඇۙ዆ްࢇ๫ೕ characteristic line impedance. With this configuration,
or PAL television broadcast systems. The total peak-to- ‫ڦ‬໦ࡼǈഄྺມ‫܋‬থ‫ࠦڦ‬ᆶ໦ࡼăැၙ‫ܔ‬ኄዖ໦ࡼ৊ႜ
reflections from pulse edges are minimized and the best
႑ࡽሀྺ VPPisăྺକኧ‫޶׼‬ஞ؋ǈ੗ᅜ๑ᆩ‫ݴ‬૗
peak output1.23voltage specified to be 140 IRE = 1 VPP, ௜ցǈ‫׉‬ᆩ‫݆ݛ‬๟ǖඟ๫ೕ࣐؋ഗ‫ڦ‬ሺᅮྺ V/V(6 dB)ǈ
signal integrity is maintained. Since operational2 amplifiers
‫ۉ‬ᇸǄ
with only±VS ǅሏ໙‫ٷݣ‬ഗǈᄺ੗ᅜ๑ᆩ AC ᳘ࢇǈഄ
the sync and luminance (Y’) where the sync DC are ideally voltage sources, their outputs
ኄᄣ๫ೕᇸ‫޶ڟ‬ሜ‫ڦ‬ጺሺᅮՍྺ have
1 V/V (0 dB)very
ă low
‫ۉ‬ೝሞথ๭ഗ‫܋‬ԥ࣬ްă๑ᆩ‫ݴ‬૗‫ۉ‬ᇸईኁ
pulse is negative. With chrominance informationAC ᳘ࢇǈ
added, a impedance (near 0 :), and matching the output impedance
29

Amplifiers: Op Amps Texas Instruments Incorporated
5isૌǄ
easily 5ǅ၍‫ڦ‬๑ᆩ‫׉ݥ‬೵Փǈ໲࠽‫ݘ‬ᆩᇀऺ໙ऐਆ
Catdone by adding a series output resistor. This out- = 100Ω ้R
RG and , FRare
O =the
50Ω ăRL
main ྺ೅ದ Zresistors
gain-setting O ‫ۉڦ‬ፆഗă
for theZO =
ᇘྪ (LAN)ǈ‫ڍ‬໲ᄺᆩᇀ‫د‬๼ഄ໱႑ࡽǈ૩සǖ‫ࣆۉ‬႑
put resistor, in conjunction with the input impedance of 100 amplifier. For aă
W, RL = 100Ω gain of 2 V/V, RF = 2RG.
the receiver, gives a 6-dB loss that is inherent
ࡽĂ๫ೕ႑ࡽࢅᅼೕ႑ࡽ‫ڪ‬ă‫ܠٷ‬ຕ in double
5 ૌ၍ॏ߭‫࢔ۼ‬ VOUT+ and VOUT– are the differential output signals from
termination. To make
‫گ‬ǈᄺுᆶೡԸࠀీǈ๑ᆩມজ၍ยऺํ၄ֶ‫ۯ‬႑ࡽ‫د‬up for the loss, it is common practice ቉ᅃੂ཮ the FDA. ዐ‫ۉڦ‬ୟǈࡻၟ๟੗ᅜথ๴‫ڦ‬ǈ‫ڍ‬ጮဦֱ
2 They are 180° out of phase and are level shifted
for video buffers to be designed to have a gain of 2 V/V ੂኮࢫ݀၄࣏Ⴔᄲፔᅃၵ߾ፕ֍ႜă޿‫ۉ‬ୟժுᆶྺ
to the common-mode output voltage, VOCM.
๼‫ڦ‬ሯำᅞ዆ă 5 ૌ၍‫ڦ‬Քጚ༬Ⴀፆੇྺ
(6 dB) so the overall gain from video source100Ω ă is
to load
TMS320DM368 ๫ೕ࣐؋ഗ༵ࠃ
The two RO resistors 75-Ω
are selected to match޶ሜǈᅺُ࣐
the charac-
1 V/V (0 dB).
‫ۉ‬ୟ‫ݴ‬ဆ = 100 :, RO = 50 :.
teristic line impedance, ZO . For ZO TMS320DM368
؋ഗ๼‫ۉ؜‬უॽփኟඓă‫ړ‬๑ᆩස ‫ڪ‬
Category 5 (Cat 5) cabling is very common and used
ॺᅱ‫ۉ‬ୟ
widely for1computer local-area networks (LANs), but it is ๫ೕᇸൻ‫้ۯ‬ǈ๫ೕᇸ‫ڦ‬๫ೕ࣐؋ഗ๼‫ྺྷݔ؜‬
RL is the resistor selected to match ZO . For ZO = 100 0.35:,
also ‫ڟ‬ R = 100 :.
ǈᅺُ޿‫ۉ‬ୟ‫ڦ‬๼‫؜‬႑ࡽᆶᅃ߲‫ڪ‬ᇀ๫ೕ႑
‫ڼ‬ ᅃused
੼ ॺtoᅱcarry
‫ ۉ‬ୟother
ǈ ᆩsignals
ᇀ‫ڇܔ‬ such
‫ۉ‬ᇸ as ๫
telephone,
ೕ ᇸ Ǆ video,
૩සǖ V 1.35 V
L
and audio. Most Cat 5 cables are low-cost and unshielded At first look the circuit in Figure 2 might appear to be
ࡽࠌఇ‫ۉ‬უ‫ױ‬ᅜሺᅮ‫ۯֶڦ‬ೋᅎଉǈഄॽԥ‫ۉ‬ೝገ࣑ྺ
TMS320DM368 ǅ‫܋ڇڦ‬๫ೕ႑ࡽ৊ႜገ࣑ǈణ‫ڦ‬๟ൻ
and use a twisted-pair design with differential signaling for acceptable, but closer inspection shows it needs some
‫ۯֶۯ‬၍ୟǈස཮ ໯๖ă߳և‫ీࠀݴ‬සူǖ
noise rejection. The2nominal characteristic impedance of
VOCMăऺ໙՗௽ǈ཮ 2 ‫ۉ‬ୟ๼‫؜‬ᆶᅃ߲ 1.7-V ‫ۯֶڦ‬ೋ
work. This circuit does not provide a 75-: load for the
Cat 5 cable is 100 :. ᅎଉăᄲৰኟ޿ೋᅎଉǈ
TMS320DM368 video buffer, FDA ࿄๴ൻ‫ڦ֨ۯ‬
so the G ՂႷԥ
buffer outputRvoltages
VS+ ྺ‫ٷݣ‬ഗ‫ۉڦ‬ᇸǗ޶‫ۉ‬ᇸ๼෇ VS- থ‫ں‬ă ‫ݴ‬૗ࢅೋዃǈᅜՍํ၄
will not be correct. WhenFDA ๴ൻ‫֨ۯ‬ ‫ྼٻڦ‬ౢ‫ڪ‬ၳ
RG source like
driven from a video
Circuit analysis the TMS320DM368, whose video-buffer output range is
‫ۉ‬ୟă‫ྼٻ‬ౢ‫ڪ‬ၳ๼෇‫ۉ‬უ‫ڪ‬ᇀ๫ೕᇸ‫ࠌڦ‬ఇ‫ۉ‬უǈन
IN ྺ TMS320DM368
VProposed circuit #1 ๫ೕᇸ‫ڦ‬๼෇ǈഄ‫ ྺྷݔ‬0.35 V 0.35 V to 1.35 V, the output signals from this circuit will
VTH =V IN_CMă
‫ڟ‬A first Vă
1.35proposed circuit for converting a single-ended have a differential offset equal to the common-mode volt-
video signal from a single-supply video source like the age of the video signal times the gain and will be level
G ࢅ RF ྺ‫ٷݣ‬ഗ‫ڦ‬ዷᄲሺᅮยዃ‫ۉ‬ፆഗăሺᅮྺ
RTMS320DM368 to drive a differential line might be as 2 V/V shifted to VOCM . Calculations show that the Figure 2 circuit
้ǈ
shownRF in ă
Figure
= 2R G
2. The function of the various elements is output will have a 1.7-V differential offset. To correct the
as follows: offset, RG on the undriven side of the FDA must be split
VS+ࢅ
VOUT+ is V
the ྺ FDA
power
OUT– ‫ۯֶڦ‬๼‫؜‬႑ࡽă໲்ྺ
supply nega-ᅴ
to the amplifier; and the180° and biased to make a Thevenin equivalent of RG on the
၎ǈժԥ‫ۉ‬ೝገ࣑ྺࠌఇ๼‫ۉ؜‬უ VOCM
tive supply input, VS– , is grounded. ă driven side of the FDA. The Thevenin-equivalent input
voltage equals the common-mode voltage from the video
VIN is the input from the TMS320DM368 video source,
࿢்჋ስକଇ߲ RO V‫ۉ‬ፆഗઠ೅ದ༬Ⴀ၍ୟፆੇ Z Oă Z O source; i.e., VTH = VIN_CM.
ranging from 0.35 to 1.35 V.
཮ 2 ᆩᇀॽ‫܋ڇ‬๫ೕ႑ࡽገ࣑ྺֶ‫ۯ‬႑ࡽ‫ॺڦ‬ᅱ‫ۉ‬ୟ
Figure 1
2. Proposed circuit #1 for converting single-ended video signals to differential
VIN RG RF
CVBS
0V VS+ Cat 5 VOCM
Video Z O = 100
VOUT– RO
+
–
FDA + RL
–
VOUT+ RO
VOCM
VOCM
RG RF
Problem:
With RG to GND, input
offset from GND causes
differential-output offset
30

཮ 3 ၯኟֶ‫ۯ‬๼‫؜‬ೋᅎଉ‫ॺڦ‬ᅱ‫ۉ‬ୟ
Figure 2
3. Proposed circuit #2 with corrected differential-output offset
VIN R G1 RF
VIN_CM
CVBS
VS+ Cat 5
0V Video RT Z O = 100
VOUT– RO VOCM
+
–
FDA + RL
–
VOUT+ RO VOCM
VOCM
R G2b RF
Changing undriven
input to Thevenin
R G2a equivalent solves
offset problem
VS+
ॺᅱ‫ۉ‬ୟ
Proposed2circuit #2 ૧ᆩ཮ 4ǈ੗ᅜ࢔ඹᅟ‫ܔں‬໯Ⴔ VTH ৊ႜ‫ݴ‬ဆǈഄऺ໙‫ݛ‬
A second proposed circuit forTMS320DM368
converting a single-ended The required VTH is easy to analyze by using Figure 4 and
‫ॺ੼ܾڼ‬ᅱ‫ۉ‬ୟǈᆩᇀ‫ܔ‬ස ‫ۉڇڪ‬ᇸ๫ ݆සူǖ
video signal from a single-supply video source like the is calculated by
ೕᇸ‫܋ڇڦ‬๫ೕ႑ࡽ৊ႜገ࣑ǈᅜൻ‫ۯֶۯ‬၍ୟǈස཮
3TMS320DM368 to drive a differential line is shown in
໯๖ăሞኄዖ‫ۉ‬ୟዐǈ࿢்‫ۉ‬ୟ৊ႜକᅃၵ߀৊ǖߴ RG2b
Figure 3. In this version, the circuitFDA
is improved to correctRG VTH VS
. (3)
75-Ω ๼෇‫܋‬থཁे RTǈ඗ࢫॽ ࿄๴ൻ‫ڦ֨ۯ‬ RG2a RG2b
the offset in
߀ྺ๴ൻ‫ྼٻڦ֨ۯ‬ౢ‫ڪ‬ၳ‫ۉ‬ୟǈ circuit #1 by adding R for a 75-: input termi-
TH = V IN_CM ăኄᄣፔ
T V
ྺକႼຎ‫ྜڦ‬ኝႠǈ࿢்्ยᅙঢ়Ӏቷฉຎᄲ൱ॺ૬କ
For completeness before going on, assuming the device
nation and changing
‫ڦ‬ణ‫ڦ‬๟ၯኟ‫ۉ‬ୟ 1 ዐ‫؜‬၄‫ڦ‬ೋᅎଉă߳ፇ‫ׯ‬և‫ࠀڦݴ‬RG on the undriven side of the FDA
to be the Thevenin equivalent of the driven side, with ഗॲǈሶ‫܋ڇ‬๼෇‫ۯֶڟ‬๼‫ڦ؜‬ሺᅮྺǖ
has been set up per the foregoing, the gain from single-
ీᇑኮമ၎ཞǈኻ๟ᆩ R ࢅ RG2b ‫༺پ‬କ࿄๴ൻ‫ڦ֨ۯ‬ ended input to differential output is set by
V = VIN_CM . The functionG2aof the components is the same
RGTH
ăူ௬๟‫ۉܔ‬ୟ 2 ‫ݴڦ‬ဆࢅఇె൧઄ă
VOUT R RT
as before, with RG on the undriven side replaced by RG2a
G 2
F
. (4)
‫ۉ‬ୟ G2b. An analysis and a simulation of circuit #2 follow.
and 2R‫ݴ‬ဆ VIN RTH RS RT
Analysis of circuit
ྺକ‫ݴ‬ဆ཮ #2 ௅ ߲‫܋ڇ‬๼‫؜‬਩ྺᅃӷֶ‫ۯ‬๼‫؜‬ǈഄԥ‫ۉ‬ೝገ࣑ྺ
3 ໯๖‫ۉ‬ୟ 2ǈ࿢்्ย FDA ྺᅃ߲૙ၙ‫ݣ‬ Each single-ended output is half the differential output
For analysis of circuit #2 in Figure 3, it is assumed that the Vand ǖlevel shifted to V :
‫ٷ‬ഗǈഄᆶ࿮၌‫ڦ‬ሺᅮǈ൐փ٪ሞೋᅎଉăኄᄣፔ‫ڦ‬ణ OCMis
OCM
FDA is an ideal amplifier with infinite gain and no offset.
‫ڦ‬๟ඟFDA‫ڦ‬࿄๴ൻ‫ྺׯ֨ۯ‬๴ൻ‫ڦ֨ۯ‬ᅃ߲‫ྼٻ‬ౢ‫ڪ‬ၳ
One goal of the design is to make the undriven side of the RF RT
‫ۉ‬ୟăኄዖፔ݆ǈᇑኄᅃۨ૙Ǆ‫ྼٻ‬ౢ‫ڪ‬ၳ‫ۉ‬ୟۨ૙ǅ VOUT VIN

VOCM
FDA a Thevenin equivalent of the driven side. This is RTH RS RT
‫ڦ‬ᅃӯ๑ᆩ‫݆ݛ‬၎‫ݒ‬ǈഄॽ߸०‫ڦڇ‬๴ൻ‫֨ۯ‬ገ࣑ྺ࿄
working backwards from the normal way to use the theo-
๴ൻ‫ްྺ߸֨ۯ‬ሗ‫ۉڦ‬ୟă
rem, converting the simpler form of the driven side to a RF RT
more complex circuit on the undriven side. ǈഄዐ VOUT VIN

VOCM
‫ڼ‬ᅃօ๟ยዃೝႜࢅǈन RG2a || RG2b =RTH R = RTH RS RT
The first step is to set the parallel sum, RG2a || RG2b = TH
RG1 + RS || RTă࿢்੗ᅜॽ໲ႀ‫ׯ‬සူ‫ײݛ‬๕ǖ
RTH, where RTH = RG1 + RS || RT. This can be written in
equation form as
཮ 4 ‫ྼٻ‬ౢ‫ڪ‬ၳ‫ۉ‬ୟǄ
Figure VTHǅ‫ݴ‬ဆ཮
4. Thevenin equivalent (VTH)
RS
R T analysis diagram
RTH RG1 . (1)
RS R T
RS ‫ڪ‬ᇀ 75Ω
RS equals 75 :ǈഄྺ
and is TMS320DM368 ๫ೕ࣐؋ഗ‫ڦ‬๼‫؜‬
the output impedance of the VS+
ፆੇă RT ‫ڪ‬ᇀvideo
TMS320DM368 82.5Ω RT equals 82.5 : and is the
ǈഄྺ๑‫ٷݣ‬ഗ‫ۉ‬ୟ๼෇ፆੇ‫ڪ‬
buffer.
ᇀ 75Ω໯Ⴔᄲ‫ۉڦ‬ፆăසࢆ჋ስኟඓ‫܋‬থࢅሺᅮ‫ڦ‬
resistance required to make the input impedance of theRTࢅ
circuit equal 75 :. 2For R G2a
G1ǈၘ൧൩֖९֖੊࿔၅
Ramplifier ă detailed information on
how to select RT and RG1 for proper termination and gain, VTH
‫ܾڼ‬օ๟ยዃ 2.TH = VIN_CMǈഄዐ
see Reference V
The second step is to set VTH = VIN_CM , where R G2b
VIN(min) VIN(max)
VIN _ CM . (2)
2
31

Amplifiers: Op Amps Texas Instruments Incorporated
TM
཮ 5 TINA-TI
Figure ਉ૩‫ۉ‬ୟ
5. TINA-TI™ example circuit
75% NTSC/PAL SD CVBS signal

typically 1Vpp and 6MHz max
DM368 video out buffer 0.35V to 1.35V
Twisted pair Cat 5 typically 100 ohm

Rs 75 Vin_SE RG1 487 RF 1k differential characteristic impedance Differential CVBS signal to load
Vs+
Rt 82.5 RO 49.9 Vout_SE-
+
Vin 1.7
Vin+ VS+
Vocm Vout- +
Vocm
FDA
RL 100 Vout_DIFF
U1 THS4521 -

Vin-
Vout+
C1 220n RO 49.9
VS- PD
Vs+ Vout_SE+
Vs+
RF 1k
V2 5 2X RO provides 100 ohm RL provides 100 ohm
RG2b 634 differential output impedance differential termination impedance
RG2a 3.09k
Vs+
RG2a & RG2b provide pull-up of input pins to balance offset due to Vin_CM = 0.85V.
ྺକቴ‫ڟ‬஢ፁยऺᄲ൱‫ڦ‬
To find the unique values of RRG2a ࢅ RG2b
G2a and ‫ڦ‬ኵǈႴᄲ‫ܔ‬
G2b that will satisfy ૧ᆩ‫ײݛ‬๕ 5ǖ 5:
Using Equation
‫ײݛ‬ 1 ࢅ 3Equations
the design, ዘႎಇଚǈժཞ้൱঴‫؜‬঳ࡕăᅃዖ‫݆ݛ‬
1 and 3 need to be rearranged and VS 5V
‫ڟڥ‬ǖ
solved simultaneously. One approach yields RG2a RTH
526
3096
VTH 0.85 V
VS
RG2a RTH
. (5) ૧ᆩ‫ײݛ‬๕ 6ǖ 6:
Using Equation
VTH
RG2a
RTH 3096
526
޿ኵ੗ᆩᇀ൱঴ǖ
This value can then be used to find RG2b 634
RG2a RTH 3096 526
RG2a
RTH
RG2b . (6) ፌথৎՔጚ
The nearest 1% ኵ 3.09kΩ
standard ࢅ 634Ω
1% values, k: and 634 :, are
3.09ǈᆩᇀူଚ‫ݠ‬ኈă
RG2a RTH
used in the following simulation.
TM
‫ۉ‬ୟ 2 ऺ໙ਉ૩
Calculation example for circuit #2 TINA-TI ෉ॲ‫ݠ‬ኈ
Simulation with TINA-TI™ software
For this
ኄ๟ᅃ߲සࢆ๑ᆩ‫ۉ‬ୟexample of how to2 use circuit #2, it is assumed
‫ڦ‬૩ጱǈ࿢்्ย๼෇႑ࡽ ཚࡗ‫ॺܔ‬ᅱ‫ۉ‬ୟ৊ႜ‫ݠ‬ኈǈቴ‫ٱ؜‬ဃժᄓኤ्ย๟‫ޏ‬ᆶ
It is always a good idea to simulate a proposed circuit to
that the input signal is
ઠጲ TMS320DM368 ǈഄ႑ࡽ๼‫ྺྷݔ؜‬ from the TMS320DM368,0.35 with V
a ‫ڟ‬ ၳǈ๔ዕ‫ۼ‬๟ᅃዖࡻ‫݆ݛ‬ă཮ 5 ࢅ 6 ၂๖କሏႜ
catch errors and verify that any assumptions TINA-
are valid.
signal output range of 0.35 V to 1.35 V. Cat 5 cable is used, Figures෉ॲ‫ڦڟڥ‬ຨༀ঳ࡕࢅೕ୲‫ݴ‬ဆ঳ࡕă޿‫ݠ‬ኈ՗
5 and 6 show the result of a transient and fre-
1.35 Vă࿢்๑ᆩକ 5 ૌ၍ǈᅺُມ‫܋‬থ RO = 50Ωࢅ TITM
so R = 50 : and RL = 100 : for double termination. The ௽ǈ๼‫ۉ؜‬ೝገ࣑ྺ
quency analysis performed ้ுᆶ‫؜‬၄༪ᄋ‫ڦ‬ຨༀ
with TINA-TI™ software. The
R L= O100Ω ă޿ਉ૩๑ᆩକ TI THS4521 ǈ໲๟ᅃዖ‫ڇ‬ VOCM=2.5V
TI THS4521, an FDA with a single +5-V supply, was chosen simulation shows no unwanted
ၚᆌೋᅎଉǈཞ้ AC ೕ୲ၚᆌ၂๖޶ሜሺᅮྺ૙ၙ‫ڦ‬ offsets in the transient
+5-V ‫ۉ‬ᇸ‫ ڦ‬FDAă
for this example. response with
1 V/V (0 dB)ă the output level shifted to V OCM = 2.5 V, and
The THS4521
THS4521 data sheet recommends
ׂ೗ຫ௽ກॺᅱ RF ‫ڪ‬ᇀ that F be equal to
1kΩRăැၙ༵ࠃ the AC frequency response shows that gain to the load is
1 k:. To provide 75-: input termination
75-Ω ๼෇‫܋‬থࢅ 2 V/V (6 dB) ‫ ڦ‬G ኵǈ੗ॽ and a value
RG1for
ยዃ G සᇡֱੂ‫ۉ‬ୟ‫ڦ‬ TINA-TI ‫ݠ‬ኈ൧઄ǈ൩‫ݡ‬࿚ http://www.
1 V/V (0 dB) as desired.
of 2 V/V (6
ྺ 487ΩǈRT ยዃྺdB), R can be set at 487
G1 82.5Ωǈස֖੊࿔၅ 2໯ຎăॽኄ: and R T at 82.5 : ti.com/lit/zip/slyt427 ǈ඗ࢫ‫ۅ‬ऍĐ‫ٶ‬ਸđሞ၍៓બ
To see the TINA-TI simulation of this circuit, go to
per Reference 2. These values can be used in the following
ၵኵᆩᇀူଚ‫ײݛ‬๕ዐǈऺ໙‫؜‬ഄᇆ‫ۉ‬ፆኵă Winzip ణ୤Ǆᄺ੗ᅜ‫ۅ‬ऍĐԍ٪đူሜ
http://www.ti.com/lit/zip/slyt427 Open to࿔ॲ૗၍
and click Winzip view
equations to calculate the remaining resistor values. ๑ᆩǅăසࡕ౞ᅙঢ়Ҿጎକ
the WinZip directory online (or ෉ॲǈ౞Ս੗ᅜ‫ٶ‬
click Save
TINA-TI to download the
૧ᆩ‫ײݛ‬๕ 1ǖ1:
Using Equation WinZipTHS4521_SE_to_DIFF_for_Cat5_video_drive
ਸ࿔ॲ file for offline use). If you have the TINA-TI soft- ă
RS
R T 75
82.5 ware installed, you can open the file THS4521_SE_to_
TSC ֱੂํ૩ăැၙူሜࢅҾጎ௨‫ڦݯ‬ TINA-TI ෉ॲǈ
RTH RG1 487 526 DIFF_for_Cat5_video_drive.TSC
൩‫ݡ‬࿚ www.ti.com/tina-tiǈ඗ࢫ‫ۅ‬ऍĐူሜđӀ౧ă to view the example. To
RS R T 75 82.5
download and install the free TINA-TI software, visit
Using Equation 2: www.ti.com/tina-ti and click the Download button.
VIN(min) VIN(max) 0.35 V 1.35 V
VIN _ CM 0.85 V
2 2
32

TM
཮ 6 ํ૩‫ۉ‬ୟ‫ڦ‬
Figure TINA-TI
6. TINA-TI™ ‫ݠ‬ኈ঳ࡕ
simulation results of example circuit
2
VIN_SE 3
(V) Overall Gain = 0 dB (1 V/V)
0 Peaking = No Peaking
5
VOCM
(V)
0 0
Gain (dB)
0.5
VOUT_DIFF
(V)
–0.5
2.8
VOUT_SE+ –3
f(–3dB) = 73 MHz
(V)
2.2
2.8
VOUT_SE–
(V) –6
2.2
10 k 100 k 1M 10 M 100 M
0 250 500 750 1000 Frequency (Hz)
Time (ns)
(a) Transient simulation with a 1-MHz square wave and (b) Simulation of AC frequency response from VIN_SE to
VIN_SE = 0.35 to 1.35 V VOUT_DIFF
঳ஃ ֖੊࿔၅
Conclusion References
THS4521
The THS4521 ๟‫ۉڇ‬ᇸᆌᆩዐॽՔጚൣည‫܈‬ (SD) ईኁሺ
is an excellent choice for converting සForᇡ କ঴
more Ԩ࿔၎࠲
information ߸ ‫ܠ‬toၘthis
related ൧ article,
ǈ৤൩ ‫ݡ‬can
you ࿚w w w.
down-
ഽൣည‫܈‬ (ED) ๫ೕ႑ࡽǈٗ‫܋ڇ‬ገ࣑ྺֶ‫ڦۯ‬टࡻ჋
standard-definition (SD) or enhanced-definition (ED) video tload
i . c oan
mAcrobat m b e r®Ǆfile
/ l i t / l i t n®uReader ᆩat ࿔ॲՊࡽ༺࣑ྪ኷ዐ‫ڦ‬
T Iwww.ti.com/lit/litnumber
ስă՗ 1 ଚਉକ
signals from SD ࢅ to
single-ended ፌྺჹ߭‫ڦ‬
EDdifferential NTSC ࢅ PAL
in single-supply Đand litnumber đǅǈူሜwith
replace “litnumber”
®
the TIReader
Acrobat ®
Lit. # for߭๕࿔ॲǈइ
the
๫ೕ࣐؋ᄲ൱ǈժॽഄᇑ THS4521
applications. Table 1 shows the ࡀ‫ݔ‬৊ႜԲডă
most stringent NTSC and ൽူଚ֖੊ጨଙă
materials listed below.
THS4521 ੗ᅜ஢ፁ໯ᆶኄၵᄲ൱ă
PAL video-buffer requirements of SD and ED versus
THS4521 specifications. The THS4521 meets them all.
࿔၅Ք༶
Document Title ࿔၅Պࡽ
TITILit. #
THS4521 ీࠕ‫׉ݥ‬๢ᆩᇀኄዖᆌᆩǈഄᆛᆶᅃ߲‫گ‬዁ 1. James Karki, “Fully-differential amplifiers,”
The THS4521 is capable of working for this application 1ĂĖඇֶ‫ٷݣۯ‬ഗėǈፕኁǖ
+2.5 V ‫ۉڦ‬ᇸăଷྔǈ໲࣏ᆛᆶ‫ৢگ‬ༀ‫ࠀۉูࢅୁۉ‬ Application Report. . . . . . . . . . .James . . . . .ǈ
. . . . . . . Karki . sloa054d
with a supply as low as +2.5 V. This, along with its low
ీǈඟ໲‫ྺׯ‬ᇺ‫ײ‬ĂՍၻ๕ࢅ‫ۉࠃ׾ۉ‬႙ยԢ‫ڦ‬૙ၙ ݀՗ᇀĖᆌᆩԒߢė
2. Jim Karki, “Input impedance matching with sloa054d
quiescent current and power-down capability, makes it
჋ስă fully differential
2ĂĖඇֶ‫ٷݣۯ‬ഗ‫ڦ‬๼෇ፆੇ೅ದėǈፕኁǖ amplifiers,” Analog
ideal for remote, portable, and battery-powered devices.
Applications Journal (4Q 2008) . . . . . . . . . . . . slyt310
ǈ݀՗ᇀĖఇెᆌᆩሗኾėǄ
James Karki 2008
՗ 1 NTSC/PAL
Table SD/ED
1. NTSC/PAL ๫ೕ࣐؋ᄲ൱ᇑ
SD/ED THS4521 ࡀ‫ܔڦݔ‬Բ
video-buffer requirements versus Related
౎‫ڼ‬ 4 ल‫܈‬਽ǅ
Web sites slyt310
THS4521 specifications amplifier.ti.com
0.1-dB
0.1-dB ‫੻ټ‬
BANDWIDTH SLEW RATE ၎࠲ྪበ
www.ti.com/sc/device/THS4521
ࡀ‫ݔ‬
SPECIFICATION ገ࣑໏୲ (V/μs) www.ti.com/sc/device/TMS320DM368
Ǆ(MHz)
MHzǅ (V/μs) amplifier.ti.com
NTSC/PAL
NTSC/PAL CVBS Video๫ೕ
CVBS 66 3838 TINA-TI example:
www.ti.com/sc/device/THS4521
NTSC/PAL
NTSC/PAL ED๫ೕ
ED Video 12
12 5353 www.ti.com/lit/zip/slyt427
www.ti.com/sc/device/TMS320DM368
THS4521
THS4521 (VS (VS
= 3.3 =
V) 3 .3 V) 20
20 420
420 TINA-TI ਉ૩ǖ
To download TINA-TI software:
www.ti.com/lit/zip/slyt427
www.ti.com/tina-ti
TINA-TI ෉ॲူሜǖ
www.ti.com/tina-ti
ZHCT142 33

Texas Instruments Incorporated Index of Articles
Title Issue Page Lit. No.
Data Acquisition (Continued)

Understanding the pen-interrupt (PENIRQ) operation of touch-screen controllers . . . . . . . . . . .2Q, 2008 ......... 5 SLYT292
A DAC for all precision occasions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 ......... 5 SLYT300
Stop-band limitations of the Sallen-Key low-pass filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 ......... 5 SLYT306
How the voltage reference affects ADC performance, Part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 ......... 5 SLYT331
Impact of sampling-clock spurs on ADC performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 ......... 5 SLYT338
How the voltage reference affects ADC performance, Part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 13 SLYT339
How digital filters affect analog audio-signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 ......... 5 SLYT375
Clock jitter analyzed in the time domain, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 ......... 5 SLYT379
The IBIS model: A conduit into signal-integrity analysis, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . 11 SLYT390
The IBIS model, Part 2: Determining the total quality of an IBIS model. . . . . . . . . . . . . . . . . . . . .1Q, 2011 ......... 5 SLYT400
The IBIS model, Part 3: Using IBIS models to investigate signal-integrity issues. . . . . . . . . . . . . .2Q, 2011 ......... 5 SLYT413
How delta-sigma ADCs work, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2011 . . . . . . . . 13 SLYT423
Power Management
Stability analysis of low-dropout linear regulators with a PMOS pass element. . . . . . . . . . . . . . . .August 1999 . . . . . 10 SLYT194
Extended output voltage adjustment (0 V to 3.5 V) using the TI TPS5210 . . . . . . . . . . . . . . . . . .August 1999 . . . . . 13 SLYT195
Migrating from the TI TL770x to the TI TLC770x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . 14 SLYT196
TI TPS5602 for powering TI’s DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . . 8 SLYT185
Synchronous buck regulator design using the TI TPS5211 high-frequency
hysteretic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 10 SLYT186
Understanding the stable range of equivalent series resistance of an LDO regulator . . . . . . . . . .November 1999. . . 14 SLYT187
Power supply solutions for TI DSPs using synchronous buck converters . . . . . . . . . . . . . . . . . . . .February 2000. . . . 12 SLYT177
Powering Celeron-type microprocessors using TI’s TPS5210 and TPS5211 controllers . . . . . . . .February 2000. . . . 20 SLYT178
Simple design of an ultra-low-ripple DC/DC boost converter with TPS60100 charge pump . . . . .May 2000 . . . . . . . . 11 SLYT170
Low-cost, minimum-size solution for powering future-generation Celeron™-type
processors with peak currents up to 26 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 14 SLYT171
Advantages of using PMOS-type low-dropout linear regulators in battery applications . . . . . . . .August 2000 . . . . . 16 SLYT161
Optimal output filter design for microprocessor or DSP power supply . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 22 SLYT162
Understanding the load-transient response of LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 19 SLYT151
Comparison of different power supplies for portable DSP solutions
working from a single-cell battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 24 SLYT152
Optimal design for an interleaved synchronous buck converter under high-slew-rate,
load-current transient conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 15 SLYT139
–48-V/+48-V hot-swap applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 20 SLYT140
Power supply solution for DDR bus termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . . 9 SLYT130
Runtime power control for DSPs using the TPS62000 buck converter . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 15 SLYT131
Power control design key to realizing InfiniBandSM benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 10 SLYT124
Comparing magnetic and piezoelectric transformer approaches in CCFL applications . . . . . . . . .1Q, 2002 . . . . . . . . 12 SLYT125
Why use a wall adapter for ac input power? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 18 SLYT126
SWIFT™ Designer power supply design program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 15 SLYT116
Optimizing the switching frequency of ADSL power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 23 SLYT117
Powering electronics from the USB port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 28 SLYT118
Using the UCC3580-1 controller for highly efficient 3.3-V/100-W isolated supply design . . . . . . .4Q, 2002 . . . . . . . . . 8 SLYT105
Power conservation options with dynamic voltage scaling in portable DSP designs . . . . . . . . . . .4Q, 2002 . . . . . . . . 12 SLYT106
Understanding piezoelectric transformers in CCFL backlight applications. . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . 18 SLYT107
Load-sharing techniques: Paralleling power modules with overcurrent protection . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 5 SLYT100
Using the TPS61042 white-light LED driver as a boost converter . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 7 SLYT101
Auto-Track™ voltage sequencing simplifies simultaneous power-up and power-down . . . . . . . . .3Q, 2003 . . . . . . . . . 5 SLYT095
Soft-start circuits for LDO linear regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 10 SLYT096
UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 1. . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 13 SLYT097
LED-driver considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 14 SLYT084
Tips for successful power-up of today’s high-performance FPGAs . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 11 SLYT079
A better bootstrap/bias supply circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 33 SLYT077
35

Data Acquisition (Continued)

Understanding the pen-interrupt (PENIRQ) operation of touch-screen controllers . . . . . . . . . . .2Q, 2008 ......... 5 SLYT292
A DAC for all precision occasions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 ......... 5 SLYT300
Stop-band limitations of the Sallen-Key low-pass filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 ......... 5 SLYT306
Impact of sampling-clock spurs on ADC performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 ......... 5 SLYT338
How the voltage reference affects ADC performance, Part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 13 SLYT339
How digital filters affect analog audio-signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 ......... 5 SLYT375
The IBIS model: A conduit into signal-integrity analysis, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . 11 SLYT390
The IBIS model, Part 2: Determining the total quality of an IBIS model. . . . . . . . . . . . . . . . . . . . .1Q, 2011 ......... 5 SLYT400
The IBIS model, Part 3: Using IBIS models to investigate signal-integrity issues. . . . . . . . . . . . . .2Q, 2011 ......... 5 SLYT413
How delta-sigma ADCs work, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2011 . . . . . . . . 13 SLYT423
Power Management
Stability analysis of low-dropout linear regulators with a PMOS pass element. . . . . . . . . . . . . . . .August 1999 . . . . . 10 SLYT194
Extended output voltage adjustment (0 V to 3.5 V) using the TI TPS5210 . . . . . . . . . . . . . . . . . .August 1999 . . . . . 13 SLYT195
Migrating from the TI TL770x to the TI TLC770x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . 14 SLYT196
TI TPS5602 for powering TI’s DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . . 8 SLYT185
Synchronous buck regulator design using the TI TPS5211 high-frequency
hysteretic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 10 SLYT186
Understanding the stable range of equivalent series resistance of an LDO regulator . . . . . . . . . .November 1999. . . 14 SLYT187
Power supply solutions for TI DSPs using synchronous buck converters . . . . . . . . . . . . . . . . . . . .February 2000. . . . 12 SLYT177
Powering Celeron-type microprocessors using TI’s TPS5210 and TPS5211 controllers . . . . . . . .February 2000. . . . 20 SLYT178
Simple design of an ultra-low-ripple DC/DC boost converter with TPS60100 charge pump . . . . .May 2000 . . . . . . . . 11 SLYT170
Low-cost, minimum-size solution for powering future-generation Celeron™-type
processors with peak currents up to 26 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 14 SLYT171
Advantages of using PMOS-type low-dropout linear regulators in battery applications . . . . . . . .August 2000 . . . . . 16 SLYT161
Optimal output filter design for microprocessor or DSP power supply . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 22 SLYT162
Understanding the load-transient response of LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 19 SLYT151
Comparison of different power supplies for portable DSP solutions
working from a single-cell battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 24 SLYT152
Optimal design for an interleaved synchronous buck converter under high-slew-rate,
load-current transient conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 15 SLYT139
–48-V/+48-V hot-swap applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 20 SLYT140
Power supply solution for DDR bus termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . . 9 SLYT130
Runtime power control for DSPs using the TPS62000 buck converter . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 15 SLYT131
Power control design key to realizing InfiniBandSM benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 10 SLYT124
Comparing magnetic and piezoelectric transformer approaches in CCFL applications . . . . . . . . .1Q, 2002 . . . . . . . . 12 SLYT125
Why use a wall adapter for ac input power? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 18 SLYT126
SWIFT™ Designer power supply design program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 15 SLYT116
Optimizing the switching frequency of ADSL power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 23 SLYT117
Powering electronics from the USB port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 28 SLYT118
Using the UCC3580-1 controller for highly efficient 3.3-V/100-W isolated supply design . . . . . . .4Q, 2002 . . . . . . . . . 8 SLYT105
Power conservation options with dynamic voltage scaling in portable DSP designs . . . . . . . . . . .4Q, 2002 . . . . . . . . 12 SLYT106
Understanding piezoelectric transformers in CCFL backlight applications. . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . 18 SLYT107
Load-sharing techniques: Paralleling power modules with overcurrent protection . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 5 SLYT100
Using the TPS61042 white-light LED driver as a boost converter . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 7 SLYT101
Auto-Track™ voltage sequencing simplifies simultaneous power-up and power-down . . . . . . . . .3Q, 2003 . . . . . . . . . 5 SLYT095
Soft-start circuits for LDO linear regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 10 SLYT096
LED-driver considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 14 SLYT084
Tips for successful power-up of today’s high-performance FPGAs . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 11 SLYT079
A better bootstrap/bias supply circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 33 SLYT077
35

Index of Articles Texas Instruments Incorporated
Power Management (Continued)

Understanding noise in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 ......... 5 SLYT201
Understanding power supply ripple rejection in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 ......... 8 SLYT202
Miniature solutions for voltage isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 13 SLYT211
New power modules improve surface-mount manufacturability . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 18 SLYT212
Li-ion switching charger integrates power FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 19 SLYT224
TLC5940 dot correction compensates for variations in LED brightness . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 21 SLYT225
Powering today’s multi-rail FPGAs and DSPs, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 ......... 9 SLYT232
TPS79918 RF LDO supports migration to StrataFlash® Embedded Memory (P30) . . . . . . . . . . .1Q, 2006 . . . . . . . . 14 SLYT233
Practical considerations when designing a power supply with the TPS6211x . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . 17 SLYT234
TLC5940 PWM dimming provides superior color quality in LED video displays . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 10 SLYT238
Wide-input dc/dc modules offer maximum design flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 13 SLYT239
Powering today’s multi-rail FPGAs and DSPs, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 18 SLYT240
TPS61059 powers white-light LED as photoflash or movie light . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 ......... 8 SLYT245
TPS65552A powers portable photoflash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . 10 SLYT246
Single-chip bq2403x power-path manager charges battery while powering system . . . . . . . . . . . .3Q, 2006 . . . . . . . . 12 SLYT247
Complete battery-pack design for one- or two-cell portable applications . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . 14 SLYT248
A 3-A, 1.2-VOUT linear regulator with 80% efficiency and PLOST < 1 W . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . 10 SLYT254
bq25012 single-chip, Li-ion charger and dc/dc converter for Bluetooth® headsets . . . . . . . . . . . .4Q, 2006 . . . . . . . . 13 SLYT255
Fully integrated TPS6300x buck-boost converter extends Li-ion battery life. . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . 15 SLYT256
Selecting the correct IC for power-supply applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 ......... 5 SLYT259
LDO white-LED driver TPS7510x provides incredibly small solution size . . . . . . . . . . . . . . . . . . .1Q, 2007 ......... 9 SLYT260
Power management for processor core voltage requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . 11 SLYT261
Enhanced-safety, linear Li-ion battery charger with thermal regulation and
input overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 ......... 8 SLYT269
Current balancing in four-pair, high-power PoE applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 11 SLYT270
Power-management solutions for telecom systems improve performance, cost, and size. . . . . . .3Q, 2007 . . . . . . . . 10 SLYT278
TPS6108x: A boost converter with extreme versatility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007 . . . . . . . . 14 SLYT279
Get low-noise, low-ripple, high-PSRR power with the TPS717xx . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007 . . . . . . . . 17 SLYT280
Simultaneous power-down sequencing with the TPS74x01 family of linear regulators . . . . . . . . .3Q, 2007 . . . . . . . . 20 SLYT281
Driving a WLED does not always require 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2007 ......... 9 SLYT284
Host-side gas-gauge-system design considerations for single-cell handheld applications . . . . . . .4Q, 2007 . . . . . . . . 12 SLYT285
Using a buck converter in an inverting buck-boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2007 . . . . . . . . 16 SLYT286
Understanding output voltage limitations of DC/DC buck converters . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 11 SLYT293
Battery-charger front-end IC improves charging-system safety. . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 14 SLYT294
New current-mode PWM controllers support boost, flyback, SEPIC, and
LED-driver applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 ......... 9 SLYT302
Getting the most battery life from portable systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 ......... 8 SLYT307
Compensating and measuring the control loop of a high-power LED driver . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 14 SLYT308
Designing DC/DC converters based on SEPIC topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 18 SLYT309
Paralleling power modules for high-current applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 ......... 5 SLYT320
Improving battery safety, charging, and fuel gauging in portable media applications . . . . . . . . . .1Q, 2009 ......... 9 SLYT321
Cell balancing buys extra run time and battery life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 14 SLYT322
Using a portable-power boost converter in an isolated flyback application . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 19 SLYT323
Taming linear-regulator inrush currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 ......... 9 SLYT332
Designing a linear Li-Ion battery charger with power-path control . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . 12 SLYT333
Selecting the right charge-management solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . 18 SLYT334
Reducing radiated EMI in WLED drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 17 SLYT340
Using power solutions to extend battery life in MSP430 applications . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 10 SLYT356
Designing a multichemistry battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 13 SLYT357
Efficiency of synchronous versus nonsynchronous buck converters. . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 15 SLYT358
Fuel-gauging considerations in battery backup storage systems . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 ......... 5 SLYT364
Li-ion battery-charger solutions for JEITA compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 ......... 8 SLYT365
Power-supply design for high-speed ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . 12 SLYT366
Discrete design of a low-cost isolated 3.3- to 5-V DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 12 SLYT371
Designing DC/DC converters based on ZETA topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 16 SLYT372
Coupled inductors broaden DC/DC converter usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . 10 SLYT380
Computing power going “Platinum” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . 13 SLYT382
36

Power Management (Continued)

A low-cost, non-isolated AC/DC buck converter with no transformer. . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . 16 SLYT391
Save power with a soft Zener clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . 19 SLYT392
An introduction to the Wireless Power Consortium standard and TI’s compliant solutions . . . . .1Q, 2011 . . . . . . . . 10 SLYT401
Fine-tuning TI’s Impedance Track™ battery fuel gauge with LiFePO4 cells in
shallow-discharge applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2011 . . . . . . . . 13 SLYT402
Implementation of microprocessor-controlled, wide-input-voltage, SMBus smart
battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2011 ........ 11 SLYT410
Benefits of a coupled-inductor SEPIC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2011 ........ 14 SLYT411
IQ: What it is, what it isn’t, and how to use it . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2011 ........ 18 SLYT412
Backlighting the tablet PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2011 ........ 23 SLYT414
Challenges of designing high-frequency, high-input-voltage DC/DC converters. . . . . . . . . . . . . . .2Q, 2011 ........ 28 SLYT415
A boost-topology battery charger powered from a solar panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2011 ........ 17 SLYT424
Interface (Data Transmission)

TIA/EIA-568A Category 5 cables in low-voltage differential signaling (LVDS) . . . . . . . . . . . . . . . .August 1999 . . . . . 16 SLYT197
Keep an eye on the LVDS input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 17 SLYT188
Skew definition and jitter analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 29 SLYT179
LVDS receivers solve problems in non-LVDS applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 33 SLYT180
LVDS: The ribbon cable connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 19 SLYT172
Performance of LVDS with different cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 30 SLYT163
A statistical survey of common-mode noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 30 SLYT153
The Active Fail-Safe feature of the SN65LVDS32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 35 SLYT154
The SN65LVDS33/34 as an ECL-to-LVTTL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 19 SLYT132
Power consumption of LVPECL and LVDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 23 SLYT127
Estimating available application power for Power-over-Ethernet applications . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 18 SLYT085
The RS-485 unit load and maximum number of bus connections . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 21 SLYT086
Failsafe in RS-485 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 16 SLYT080
Maximizing signal integrity with M-LVDS backplanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . 11 SLYT203
Device spacing on RS-485 buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 25 SLYT241
Improved CAN network security with TI’s SN65HVD1050 transceiver . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . 17 SLYT249
Detection of RS-485 signal loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . 18 SLYT257
Enabling high-speed USB OTG functionality on TI DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 18 SLYT271
When good grounds turn bad—isolate!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . 11 SLYT298
Cascading of input serializers boosts channel density for digital inputs . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . 16 SLYT301
RS-485: Passive failsafe for an idle bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 22 SLYT324
Message priority inversion on a CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 25 SLYT325
Designing with digital isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . 21 SLYT335
Magnetic-field immunity of digital capacitive isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . 19 SLYT381
Interfacing high-voltage applications to low-power controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . 20 SLYT393
Designing an isolated I2C Bus® interface by using digital isolators . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2011 . . . . . . . . 17 SLYT403
Isolated RS-485 transceivers support DMX512 stage lighting and special-effects applications . .3Q, 2011 . . . . . . . . 21 SLYT425
Industrial data-acquisition interfaces with digital isolators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2011 . . . . . . . . 24 SLYT426
Amplifiers: Audio
Reducing the output filter of a Class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . 19 SLYT198
Power supply decoupling and audio signal filtering for the Class-D audio power amplifier . . . . .August 1999 . . . . . 24 SLYT199
PCB layout for the TPA005D1x and TPA032D0x Class-D APAs. . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 39 SLYT182
An audio circuit collection, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 39 SLYT155
1.6- to 3.6-volt BTL speaker driver reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 23 SLYT141
Notebook computer upgrade path for audio power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 27 SLYT142
An audio circuit collection, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 41 SLYT145
An audio circuit collection, Part 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 34 SLYT134
Audio power amplifier measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 40 SLYT135
Audio power amplifier measurements, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 26 SLYT128
Precautions for connecting APA outputs to other devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 22 SLYT373
37

Index of Articles Texas Instruments Incorporated
Amplifiers: Op Amps
Single-supply op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 20 SLYT189
Reducing crosstalk of an op amp on a PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 23 SLYT190
Matching operational amplifier bandwidth with applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 36 SLYT181
Sensor to ADC — analog interface design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 22 SLYT173
Using a decompensated op amp for improved performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 26 SLYT174
Design of op amp sine wave oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 33 SLYT164
Fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 38 SLYT165
The PCB is a component of op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 42 SLYT166
Reducing PCB design costs: From schematic capture to PCB layout . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 48 SLYT167
Thermistor temperature transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 44 SLYT156
Analysis of fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 48 SLYT157
Fully differential amplifiers applications: Line termination, driving high-speed ADCs,
and differential transmission lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 32 SLYT143
Pressure transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 38 SLYT144
Frequency response errors in voltage feedback op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 48 SLYT146
Designing for low distortion with high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 25 SLYT133
Fully differential amplifier design in high-speed data acquisition systems . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 35 SLYT119
Worst-case design of op amp circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 42 SLYT120
Using high-speed op amps for high-performance RF design, Part 1 . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 46 SLYT121
Using high-speed op amps for high-performance RF design, Part 2 . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . 21 SLYT112
FilterPro™ low-pass design tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . 24 SLYT113
Active output impedance for ADSL line drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . 24 SLYT108
RF and IF amplifiers with op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 9 SLYT102
Analyzing feedback loops containing secondary amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . 14 SLYT103
Video switcher using high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 20 SLYT098
Expanding the usability of current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 23 SLYT099
Calculating noise figure in op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . 31 SLYT094
Op amp stability and input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 24 SLYT087
Integrated logarithmic amplifiers for industrial applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 28 SLYT088
Active filters using current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 21 SLYT081
Auto-zero amplifiers ease the design of high-precision circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . 19 SLYT204
So many amplifiers to choose from: Matching amplifiers to applications . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 24 SLYT213
Getting the most out of your instrumentation amplifier design . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 25 SLYT226
High-speed notch filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . 19 SLYT235
Low-cost current-shunt monitor IC revives moving-coil meter design . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 27 SLYT242
Accurately measuring ADC driving-circuit settling time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . 14 SLYT262
New zero-drift amplifier has an IQ of 17 μA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 22 SLYT272
A new filter topology for analog high-pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . 18 SLYT299
Input impedance matching with fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 24 SLYT310
A dual-polarity, bidirectional current-shunt monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 29 SLYT311
Output impedance matching with fully differential operational amplifiers . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 29 SLYT326
Using fully differential op amps as attenuators, Part 1: Differential bipolar input signals . . . . . . .2Q, 2009 . . . . . . . . 33 SLYT336
Using fully differential op amps as attenuators, Part 2: Single-ended bipolar input signals . . . . .3Q, 2009 . . . . . . . . 21 SLYT341
Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 24 SLYT342
Using the infinite-gain, MFB filter topology in fully differential active filters . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 33 SLYT343
Using fully differential op amps as attenuators, Part 3: Single-ended unipolar input signals . . . .4Q, 2009 . . . . . . . . 19 SLYT359
Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACs . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 23 SLYT360
Operational amplifier gain stability, Part 1: General system analysis. . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . 20 SLYT367
Signal conditioning for piezoelectric sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . 24 SLYT369
Interfacing op amps to high-speed DACs, Part 3: Current-sourcing DACs simplified . . . . . . . . . .1Q, 2010 . . . . . . . . 32 SLYT368
Operational amplifier gain stability, Part 2: DC gain-error analysis . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 24 SLYT374
Operational amplifier gain stability, Part 3: AC gain-error analysis . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . 23 SLYT383
Using single-supply fully differential amplifiers with negative input voltages to drive ADCs . . . .4Q, 2010 . . . . . . . . 26 SLYT394
Converting single-ended video to differential video in single-supply systems . . . . . . . . . . . . . . . .3Q, 2011 . . . . . . . . 29 SLYT427
38

Low-Power RF
Using the CC2430 and TIMAC for low-power wireless sensor applications: A power-
consumption study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 17 SLYT295
Selecting antennas for low-power wireless applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 20 SLYT296
General Interest
Synthesis and characterization of nickel manganite from different carboxylate
precursors for thermistor sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 52 SLYT147
Analog design tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 50 SLYT122
Spreadsheet modeling tool helps analyze power- and ground-plane voltage drops
to keep core voltages within tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 29 SLYT273
39

TI Worldwide Technical Support
Internet
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Fax +1(972) 927-6377 mobile and IP phones.
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๯ံǈ໲փৈඁ‫أ‬କ้ዓ႑ࡽ‫ڦ‬ᇺ‫܋‬၎࿋ሯ Clock Amplitude (VPP)

Analog Applications Journal 3Q 2011 www.ti.com/aaj High-Performance Analog Products

‫ݔࡀ੻ټ‬ĊĊ๨‫ׇ‬ฉᆶႹ‫ ܠ‬RF ‫ٷݣ‬ഗ੗ࠃ჋ስǈ‫ڍ‬๟

CDCE72010 + LNA + BPF

High-Performance Analog Products www.ti.com/aaj 3Q 2011 Analog Applications Journal

P1dB უ໫‫ۅ‬ĊĊP1dB უ໫‫ۅ‬Ԩዊฉۨᅭକፌ‫ٷ‬੗ీ ཮ 25 ืუՎუഗ߀Վ๼෇ፆੇ

噝ሯำဣຕ=0.6 dB ፌ‫ۉٷ‬უӦ‫ޗ‬ĊĊืუՎუഗ੗ᅜൟ຿‫ٷิׂں‬ᇀ 5V ‫ڦ‬

Analog Applications Journal 3Q 2011 www.ti.com/aaj High-Performance Analog Products

๑ᆩၰ༬एၥհܾट࠶ ઄ူ๑ᆩ 1 ǖ 4 Վუഗ้ǈׂิ‫ ڦ‬CDCE72010

Clipping diode reduces

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WBC1-1 WBC1-1 WBC4-1 WBC4-1 WBC4-1 WBC8-1 WBC8-1 WBC16-1 WBC16-1

the single-diode-pair (SDP) configu-

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Sample Rate (fS )

Data Rate (fD)

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(a) Time domain (b) Frequency domain

High-Performance Analog Products www.ti.com/aaj 3Q 2011 Analog Applications Journal

Integrator Integrator 1- Bit

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and increased design difficulty. However, most '6 modula-

High-Performance Analog Products www.ti.com/aaj 3Q 2011 Analog Applications Journal

Analog Applications Journal 3Q 2011 www.ti.com/aaj High-Performance Analog Products

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High-Performance Analog Products www.ti.com/aaj 3Q 2011 Analog Applications Journal

Controller Receiver 1 Receiver 2 Receiver n Terminator

OUT IN OUT IN OUT IN OUT IN

Analog Applications Journal 3Q 2011 www.ti.com/aaj High-Performance Analog Products

MBB Break MAB 8-Bit Data Stop D0 D1 D2 D3 D4 D5 D6 D7 Stop D0 D1 D2 D3 D4 D5 D6 D7 Stop MBB

Data 1+ Data 1+ Non-

RA < 100 RA < 100 0 VISO

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Output ISO- GND

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+VS1 GND1 –VS1 +VS2 GND2 –VS2

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DC Channel (DC to 100 kbps) 0

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High-Performance Analog Products www.ti.com/aaj 3Q 2011 Analog Applications Journal

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75% NTSC/PAL SD CVBS signal

Twisted pair Cat 5 typically 100 ohm

High-Performance Analog Products www.ti.com/aaj 3Q 2011 Analog Applications Journal

Analog Applications Journal 3Q 2011 www.ti.com/aaj High-Performance Analog Products