Task 1
Task 1
Task 1
1
INDEX
Sl.no. Components Page no., Student RA
Check Check
mark mark
1 Aim ✔ ✔
4 Truth Table
2
15 Verilog code: Data Flow language
16 Test Bench
19 Result
20 Inference
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Question:
Using Reg.no. formulate expressions in SOP and POS for F and F '. Use K-
Map and Boolean laws to simplify the expressions. Write a Verilog code to
implement F and F’ with a neat circuit diagram for all circuits designed using
the following forms:
Use only two input logic elements for AND, OR, NAND, NOR logic gates.
Calculate the number of two I/P NAND gates required to design. Providing the
proof for Justifying your designed circuit requires less number of logical
elements to obtain F and F’.
Calculate the number of two I/P NOR gates required to design Justifying
your circuit requires only fewer logical elements.
2. Derive the truth table for each of the outputs based on their relationships to
the input.
6. Implement the Verilog code for the circuit in Model sim and obtain the
waveform for the expected truth table.
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8. Write the aim, procedure, theory, pin diagram, block diagram, truth table
Simulation output, inference and result.
9. Write the test bench for testing the functionality of the code. BECE 102P
Digital system design TASK I QP *QP for BECE102P DSD TASK I to V and
BECE102L Digital Assignment 2 of 3
10. Write the need for real time application of the circuit designed.
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AIM: Realization of Boolean expression and Verilog
modelling of combinational logic circuits
COMPONENTS REQUIRED:
1. AND, OR, NOR, NAND, NOT gates
2. Voltage source 5v
3. LED lights
TOOLS REQUIRED:
Multisim online simulator, Charlie-Coleman KMAP solver
(https://www.charlie-coleman.com/experiments/kmap/ ), Boolean algebra
simplify (https://www.boolean-algebra.com/)
THEORY
K-maps:
Karnaugh maps (K-maps) are graphical representations of Boolean
functions.
Don’t care conditions:
There may be a combination of input values which (i)will never occur,
(ii)if theydo occur, the output is of no concern.
Canonical Forms:
1. Any Boolean function F( ) can be expressed as a unique sum of
minterms and a unique product of maxterms (under a fixed variable
ordering).
2. In other words, every function F() has two canonical
forms:Canonical Sum-Of-Products (sum of minterms)
Canonical Product-Of-Sums (product of maxterms)
PROCEDURE:
1. Write down the SoP and PoS expression using registration numbers.
2. Implement the expression in K-map using Logic minimizer or
LogicFriday.
3. Then design circuits using these expressions in Multisim using
AND OR INV and 2 input NAND logic for Σm expressions.
4. Similarly design ΠM expressions in OR AND INV Logic and 2- input
NOR Logic.
5. Compare and contrast the circuits with the number of gates used.
6. Draw suitable conclusions and inference.
7. Implement one of these 8 circuits in hardware and cross check the
results with the truth table.
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FUNCTIONAL EXPRESSION:
F(A,B,C,D) = Σm(2,1,B,C,1,0,2,9,7) = Σm(0,1,2,7,9,11,12)
F = A’B’C’D’ + A’B’C’D + A’B’CD’ + A’BCD + AB’C’D + AB’CD + ABC’D’
F'(A,B,C,D) = πM(3,4,5,6,8,10,13,14,15)
F' = (A+B+C’+D’)(A+B’+C+D)(A+B’+C+D’)(A+B’+C’+D)
(A’+B+C+D)(A’+B+C’+D)(A’+B’+C+D’)(A’+B’+C’+D)(A’+B’+C’+D’)
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TRUTH TABLE (F’) :
F'(A,B,C,D)
= πM(3,4,5,6,8,10,13,14,15)
= (A+B+C’+D’)(A+B’+C+D)(A+B’+C+D’)(A+B’+C’+D)(A’+B+C+D)
(A’+B+C’+D)(A’+B’+C+D’)(A’+B’+C’+D)(A’+B’+C’+D’)
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SOP Boolean Expression simplification using Boolean Laws
F(A,B,C,D) = Σm(2,1,B,C,1,0,2,9,7)
= Σm(0,1,2,7,9,11,12)
F= A’B’C’D’ + A’B’C’D + A’B’CD’ + A’BCD + AB’C’D + AB’CD + ABC’D’
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Simplified SOP form:
F(A,B,C,D) = A’B’D’+A’B’C’+A’BCD+AB’D+ABC’D’
POS Boolean Expression simplification using Boolean Laws
F= F'(A,B,C,D)
= πM(3,4,5,6,8,10,13,14,15)
=(A+B+C’+D’)(A+B’+C+D)(A+B’+C+D’)(A+B’+C’+D)
(A’+B+C+D)(A’+B+C’+D)(A’+B’+C+D’)(A’+B’+C’+D)(A’+B’+C’+D’)
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SOP form Simplification using K-MAP technique
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Circuit diagram using AOI logic:
12
Circuit diagram using NAND logic:
13
Circuit diagram using NOR logic:
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SOP AND-OR-INV (Dataflow Language)
module aoi_df(a,b,c,d,F);
input a,b,c,d;
output F;
assign F= {a&b&(~c)&(~d)} | {a&(~b)&d} | {(~a)&(~b)&(~d)} |
{(~a)&b&c&d} | {(~a)&(~b)&(~c)};
endmodule
Testbench:
module aoi_testbench;
reg a,b,c,d;
wire F;
aoi_df aoi1(a,b,c,d,F);
initial
begin
a=0;
b=0;
c=0;
d=0;
#10 a=0; b=0; c=0; d=0;
#10 a=0; b=0; c=0; d=1;
#10 a=0; b=0; c=1; d=0;
#10 a=0; b=0; c=1; d=1;
#10 a=0; b=1; c=0; d=0;
#10 a=0; b=1; c=0; d=1;
#10 a=0; b=1; c=1; d=0;
#10 a=0; b=1; c=1; d=1;
#10 a=1; b=0; c=0; d=0;
#10 a=1; b=0; c=1; d=1;
#10 a=1; b=0; c=1; d=1;
#10 a=1; b=1; c=0; d=0;
#10 a=1; b=1; c=0; d=1;
#10 a=1; b=1; c=1; d=0;
#10 a=1; b=1; c=1; d=1;
#50 $stop;
end
endmodule
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Waveform:
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POS OR-AND-INV (Dataflow Language)
module oai_df(a,b,c,d,Fbar);
input a,b,c,d;
output Fbar;
assign Fbar=((~a)|b|d) & ((~a)|(~b)|(~d)) & (a|(~b)|c) &
((a)|(b)|(~c)|(~d)) & ((~b)|(~c)|d);
endmodule
Testbench:
module oai_testbench;
reg a,b,c,d;
wire F;
oai_df oai1(a,b,c,d,F);
initial
begin
a=0;
b=0;
c=0;
d=0;
#10 a=0; b=0; c=0; d=0;
#10 a=0; b=0; c=0; d=1;
#10 a=0; b=0; c=1; d=0;
#10 a=0; b=0; c=1; d=1;
#10 a=0; b=1; c=0; d=0;
#10 a=0; b=1; c=0; d=1;
#10 a=0; b=1; c=1; d=0;
#10 a=0; b=1; c=1; d=1;
#10 a=1; b=0; c=0; d=0;
#10 a=1; b=0; c=1; d=1;
#10 a=1; b=0; c=1; d=1;
#10 a=1; b=1; c=0; d=0;
#10 a=1; b=1; c=0; d=1;
#10 a=1; b=1; c=1; d=0;
#10 a=1; b=1; c=1; d=1;
#50 $stop;
end
endmodule
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Waveform:
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SOP NAND-NAND (Dataflow language)
module nand_nand_df(a,b,c,d,F);
input a,b,c,d;
output F;
assign F= {a&b&(~c)&(~d)} | {a&(~b)&d} | {(~a)&(~b)&(~d)} |
{(~a)&b&c&d} | {(~a)&(~b)&(~c)};
endmodule
Testbench:
module nand_nand_testbench;
reg a,b,c,d;
wire F;
nand_nand_df nand1(a,b,c,d,F);
initial
begin
a=0;
b=0;
c=0;
d=0;
#10 a=0; b=0; c=0; d=0;
#10 a=0; b=0; c=0; d=1;
#10 a=0; b=0; c=1; d=0;
#10 a=0; b=0; c=1; d=1;
#10 a=0; b=1; c=0; d=0;
#10 a=0; b=1; c=0; d=1;
#10 a=0; b=1; c=1; d=0;
#10 a=0; b=1; c=1; d=1;
#10 a=1; b=0; c=0; d=0;
#10 a=1; b=0; c=1; d=1;
#10 a=1; b=0; c=1; d=1;
#10 a=1; b=1; c=0; d=0;
#10 a=1; b=1; c=0; d=1;
#10 a=1; b=1; c=1; d=0;
#10 a=1; b=1; c=1; d=1;
#50 $stop;
end
endmodule
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Waveform:
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POS NOR-NOR (Dataflow Language)
module nor_nor(a,b,c,d,Fbar);
input a,b,c,d;
output Fbar;
assign Fbar=((~a)|b|d) & ((~a)|(~b)|(~d)) & (a|(~b)|c) &
((a)|(b)|(~c)|(~d)) & ((~b)|(~c)|d);
endmodule
Testbench:
module nor_nor_testbench;
reg a,b,c,d;
wire F;
nor_nor_df nor1(a,b,c,d,F);
initial
begin
a=0;
b=0;
c=0;
d=0;
#10 a=0; b=0; c=0; d=0;
#10 a=0; b=0; c=0; d=1;
#10 a=0; b=0; c=1; d=0;
#10 a=0; b=0; c=1; d=1;
#10 a=0; b=1; c=0; d=0;
#10 a=0; b=1; c=0; d=1;
#10 a=0; b=1; c=1; d=0;
#10 a=0; b=1; c=1; d=1;
#10 a=1; b=0; c=0; d=0;
#10 a=1; b=0; c=1; d=1;
#10 a=1; b=0; c=1; d=1;
#10 a=1; b=1; c=0; d=0;
#10 a=1; b=1; c=0; d=1;
#10 a=1; b=1; c=1; d=0;
#10 a=1; b=1; c=1; d=1;
#50 $stop;
end
endmodule
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Waveform:
Some of the combinational circuits used for these operations are Half- adder, Full-
adder, Half-subtractors, Full subtractors, Adder-subtractors, Comparators, PLDs
(ProgrammableLogic Devices), etc.
RESULT:
I have successfully completed and simulated the combinational circuit. The
result of the circuit was as expected from the truth table. I have derived
functional expressions from the truth table using Boolean laws and K-map and
got the same results in both techniques.
There were 4 inputs (A,B,C,D) for each of the logic circuits mentioned below:
AOI
OAI
NAND-NAND
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NOR-NOR
40 NAND gates were used in SOP NAND-NAND logic circuit
38 NOR gates were used in POS NOR-NOR logic circuit
INFERFENCE:
I have derived the functional expressions using my registration
number(21BCI0297) both in SOP and POS form. I have learnt to derive a truth
table from functional expressions.I learnt Boolean expressions simplification using
Boolean laws and K-map technique.
DIGITAL SIGNATURE:
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