Compal La-8691p r0.2
Compal La-8691p r0.2
Compal La-8691p r0.2
1 1
QIQY5
2
Whisky3.0 (Y490) 2
2012-02-05 Rev0.2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 1 of 65
A B C D E
A B C D E
FDI *8 DMI *4
2.7GT/s 5GT/s
HDMI Conn. CRT Conn. LVDS Conn. USB Left USB Right
Page 36 Page 35 Page 34 USB 2.0 4x
USB 2.0 Port 2 USB 2.0 Port 9
HDMI1.4b 5V 480MHz USB 3.0 Port 2 USB 2.0 Port 5, Cha
Page 48 Sub/B Page 49
2
Intel PCH USB 3.0 2x Int. Camera BT
2
HD Audio
LPC BUS
3.3V 33MHz
3.3V 24MHz
4 DC/DC Interface CKT. RTC CKT. Thermal Sensor Int. MIC Conn. 4
Battery only O X X X 7
61@ X76 P/N for AR8161
EHCI2 8 51@ X76 P/N for AR8151
9 USB Port (Right Side) X76@ X76 Level part for VRAM
S5 S4 10 Mini Card(WLAN)
GC6@ NV CG6 support part
AC & Battery X X X X 11
NOGC6@ NV no CG6 support part
12 AOAC@ AOAC support part
don't exist Blue Tooth
13 KBL@ K/B Light part
ME@ ME part
SMBUS Control Table OPT@ For optimus function part
Main 2nd WLAN Thermal PCH TP PCIE PORT LIST SLI@ For SLI function part
SOURCE VGA VGA BATT IT8580E SODIMM WiMAX Sensor Module DS3@ Deep S3 support part
Port Device
3 S3@ For S3 function part 3
Address
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address ZZZ1
4 4
GPIO18 IN - dGPU_HDMI_HPD
GPIO19 IN - HPD_IRQ
GPU N13P-GT
Samsung K4G10325FG-HC04
B
+3VS_VGA 2500MHz B
32Mx32 PD 45K
+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K
tFBVDDQ >0
Samsung K4G20325FD-FC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K
+3VS_VGA
A A
Tpower-off <10ms
D D
DMI
DMI_CRX_PTX_P3 B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_CRX_GTX_N5
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N6 1: Normal Operation; Lane # definition matches
DMI_CTX_PRX_N0 G21 PEG_RX#[6] G33 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] CFG2 socket pin map definition
DMI_CTX_PRX_N1 E22 G30 PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 F21 DMI_TX#[1] PEG_RX#[8] F35 PCIE_CRX_GTX_N9
<16> DMI_CTX_PRX_N2 D21 DMI_TX#[2] PEG_RX#[9] E34
DMI_CTX_PRX_N3 PCIE_CRX_GTX_N10 0:Lane Reversed
<16>
<16>
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P0 G22
D22
DMI_TX#[3]
DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
D31
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N12 *
DMI_CTX_PRX_P1 PCIE_CRX_GTX_N13
<16> DMI_CTX_PRX_P1 F20 DMI_TX[1] PEG_RX#[13] B33
DMI_CTX_PRX_P2 PCIE_CRX_GTX_N14
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
Intel(R) FDI
FDI_CTX_PRX_N4 B21 F33 PCIE_CRX_GTX_P7
<16> FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 C20 FDI1_TX#[0] PEG_RX[7] F30 PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 D18 FDI1_TX#[1] PEG_RX[8] E35 PCIE_CRX_GTX_P9
<16> FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 E17 FDI1_TX#[2] PEG_RX[9] E33 PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32 PCIE_CRX_GTX_P11
PEG_RX[11] D34 PCIE_CRX_GTX_P12
FDI_CTX_PRX_P0 A22 PEG_RX[12] E31 PCIE_CRX_GTX_P13
<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 G19 FDI0_TX[0] PEG_RX[13] C33 PCIE_CRX_GTX_P14
<16> FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 E20 FDI0_TX[1] PEG_RX[14] B32 PCIE_CRX_GTX_P15
<16> FDI_CTX_PRX_P2 G18 FDI0_TX[2] PEG_RX[15]
FDI_CTX_PRX_P3
<16> FDI_CTX_PRX_P3 B20 FDI0_TX[3] M29 1 2 PCIE_CTX_GRX_N[0..15] <23,32>
FDI_CTX_PRX_P4 PCIE_CTX_GRX_C_N0 C1 0.22U_0402_10V6K PCIE_CTX_GRX_N0
<16> FDI_CTX_PRX_P4 C19 FDI1_TX[0] PEG_TX#[0] M32 1 2
FDI_CTX_PRX_P5 PCIE_CTX_GRX_C_N1 C2 0.22U_0402_10V6K PCIE_CTX_GRX_N1
<16> FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 D19 FDI1_TX[1] PEG_TX#[1] M31 PCIE_CTX_GRX_C_N2 1 2 PCIE_CTX_GRX_N2
C3 0.22U_0402_10V6K
<16> FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 F17 FDI1_TX[2] PEG_TX#[2] L32 PCIE_CTX_GRX_C_N3 1 2 PCIE_CTX_GRX_N3
C4 0.22U_0402_10V6K
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29 1 2
PCIE_CTX_GRX_C_N4 C5 0.22U_0402_10V6K PCIE_CTX_GRX_N4
FDI_FSYNC0 J18 PEG_TX#[4] K31 PCIE_CTX_GRX_C_N5 C6 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N5
<16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_C_N6 C7 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N6
<16> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] J30 PCIE_CTX_GRX_C_N7 C8 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N7
FDI_INT H20 PEG_TX#[7] J28 PCIE_CTX_GRX_C_N8 SLI@ C9 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N8
<16> FDI_INT FDI_INT PEG_TX#[8] H29 PCIE_CTX_GRX_C_N9 SLI@ C10 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N9
FDI_LSYNC0 J19 PEG_TX#[9] G27 PCIE_CTX_GRX_C_N10 SLI@ C11 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N10
<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_C_N11 SLI@ C12 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N11
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] F27 PCIE_CTX_GRX_C_N12 SLI@ C13 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N12
PEG_TX#[12] D28 PCIE_CTX_GRX_C_N13 SLI@ C14 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N13
+1.05VS PEG_TX#[13] F26 PCIE_CTX_GRX_C_N14 SLI@ C15 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N14
B R7 PEG_TX#[14] E25 PCIE_CTX_GRX_C_N15 SLI@ C16 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N15 B
1 2 EDP_COMP A18 PEG_TX#[15]
A17 eDP_COMPIO M28 PCIE_CTX_GRX_C_P0 1 2 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_P[0..15] <23,32>
C20 0.22U_0402_10V6K
24.9_0402_1% B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_C_P1 C23 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P1
eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_C_P2 C25 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P2
PEG_TX[2] L31 PCIE_CTX_GRX_C_P3 1 2 PCIE_CTX_GRX_P3
eDP_COMPIO and ICOMPO signals PEG_TX[3]
C30 0.22U_0402_10V6K
should be shorted near balls C15 L28 PCIE_CTX_GRX_C_P4 C18 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P4
D15 eDP_AUX PEG_TX[4] K30 PCIE_CTX_GRX_C_P5 C22 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P5
and routed with typical eDP_AUX# PEG_TX[5] K27 PCIE_CTX_GRX_C_P6 C28 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P6
eDP
TYCO_2013620-2_IVY BRIDGE
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 5 of 65
5 4 3 2 1
5 4 3 2 1
JCPU1B ME@
D D
A28 CLK_CPU_DMI
H_SNB_IVB# C26 BCLK A27 CLK_CPU_DMI# CLK_CPU_DMI <15>
MISC
CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
H : Sandy Bridge
PROC_SEL AN34
SKTOCC# A16 R12 2 1 1K_0402_5% +1.05VS
DPLL_REF_CLK A15 2 1
L : IVY Bridge R13 1K_0402_5%
DPLL_REF_CLK#
THERMAL
H_PECI AN33 R8 H_DRAMRST#
+1.05VS <45> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
DDR3
MISC
1 R9 2 1 R15 2 AL32 AK1 2 1 140_0402_1%
H_PROCHOT# H_PROCHOT# H_PROCHOT#_R SM_RCOMP0 R16
<45,53> H_PROCHOT# PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 R17 2 1 25.5_0402_1%
62_0402_5% 56_0402_5% SM_RCOMP[1] A4 SM_RCOMP2 2 1 200_0402_1%
R18
SM_RCOMP[2]
H_THRMTRIP# AN32
<19> H_THRMTRIP# THERMTRIP#
DDR3 Compensation Signals
AP29 +1.05VS
PRDY# AP27
PREQ#
C AR26 XDP_TCK XDP_TMS R20 2 1 51_0402_5% C
TCK AR27 XDP_TMS XDP_TDI R21 2 1 51_0402_5%
R22
PWR MANAGEMENT
TMS
BPM#[1] AR30
9/23 ESD Request BPM#[2]
BUF_CPU_RST# AR33 AT30
RESET# BPM#[3] AP32
BPM#[4] AR31
BPM#[5] AT31
BPM#[6] AR32
BPM#[7]
TYCO_2013620-2_IVY BRIDGE
B B
1
1 1
R338 C33 R30 R32 C34
10K_0402_5% 0.1U_0402_16V4Z 200_0402_5% 75_0402_5% 0.1U_0402_16V4Z
2 2
1
2
5
5
1 2 0_0402_5% 1
1.05V 1
R65 @ This is NC pin
P
P
<16> SYS_PWROK B R34 NC
4 PM_SYS_PWRGD_BUF BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 3V
2 O Y 2 PLT_RST#
<16> PM_DRAM_PWRGD A 43_0402_1% A PLT_RST# <18,23,32,37,38,44,45>
G
G
1
U1
74AHC1G09GW_TSSOP5 U2
3
3
R35 @ SN74LVC1G07DCKR_SC70-5
0_0402_5%
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 6 of 65
5 4 3 2 1
5 4 3 2 1
AB6 AE2
<12> DDR_A_D[0..63] SA_CK[0] AA6 M_CLK_DDR0 <12> <13> DDR_B_D[0..63] SB_CK[0] AD2 M_CLK_DDR2 <13>
DDR_A_D0 C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> DDR_B_D0 C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
DDR_A_D1 D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D1 A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
D DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1 D
DDR_A_D5 C6 SA_DQ[4] SA_CK[1] AB5 M_CLK_DDR1 <12> DDR_B_D5 A8 SB_DQ[4] SB_CK[1] AD1 M_CLK_DDR3 <13>
DDR_A_D6 C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> DDR_B_D6 D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D7 DDR_B_D7
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] SA_CK[2] AA4 DDR_B_D11 G1 SB_DQ[10] SB_CK[2] AA2
DDR_A_D12 F9 SA_DQ[11] SA_CLK#[2] W9 DDR_B_D12 G5 SB_DQ[11] SB_CLK#[2] T9
DDR_A_D13 F7 SA_DQ[12] SA_CKE[2] DDR_B_D13 F5 SB_DQ[12] SB_CKE[2]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] SA_CK[3] AA3 DDR_B_D17 J8 SB_DQ[16] SB_CK[3] AB1
DDR_A_D18 K1 SA_DQ[17] SA_CLK#[3] W10 DDR_B_D18 K10 SB_DQ[17] SB_CLK#[3] T10
DDR_A_D19 J1 SA_DQ[18] SA_CKE[3] DDR_B_D19 K9 SB_DQ[18] SB_CKE[3]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
DDR_A_D23 K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> DDR_B_D23 K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR_A_D24 DDR_B_D24
DDR_A_D25 N10 SA_DQ[24] SA_CS#[2] AH1 DDR_B_D25 N4 SB_DQ[24] SB_CS#[2] AE6
DDR_A_D26 N8 SA_DQ[25] SA_CS#[3] DDR_B_D26 N2 SB_DQ[25] SB_CS#[3]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
DDR_A_D30 N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> DDR_B_D30 M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
SA_DQ[30] SA_ODT[1] M_ODT1 <12> SB_DQ[30] SB_ODT[1] M_ODT3 <13>
+1.5V
1
R37
1K_0402_5%
2
3 1 1 R38 2
S
H_DRAMRST# DDR3_DRAMRST#_R
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
1K_0402_5%
2
Q2
R39 BSS138_NL_SOT23-3
G
2
4.99K_0402_1%
A A
1
1 @ 2 DRAMRST_CNTRL
<15> DRAMRST_CNTRL_PCH
R40 0_0402_5% 1
<10> DRAMRST_CNTRL
1 DS3@2
C35
0.047U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
<45> DRAMRST_CNTRL_EC 2 Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
R64 0_0402_5%
Reserve for Deep S3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
Module design used 0.047u AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 7 of 65
5 4 3 2 1
5 4 3 2 1
D D
JCPU1E ME@
CFG Straps for Processor
AH27
AK28 VCC_DIE_SENSE AH26
AK29 CFG[0] VSS
CFG2 AL26 CFG[1] CFG2
AL27 CFG[2]
CFG[3] PEG Static Lane Reversal - CFG2 is for the 16x
AK26 L7
CFG[4] RSVD28
1
CFG5 AL29 AG7
CFG[5] RSVD29
CFG6
CFG7
AL30
AM31
AM32
CFG[6]
CFG[7]
RSVD30
RSVD31
AE7
AK2 @
R41
1K_0402_1% CFG2 * 1: Normal Operation; Lane #
socket pin map definition
definition matches
AM30 CFG[8] W8
CFG
2
AM28 CFG[9] RSVD32
CFG[10] 0:Lane Reversed
AM26
AN28 CFG[11] AT26
AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
AM27 CFG[14] RSVD35
AK31 CFG[15]
AN29 CFG[16]
CFG[17]
Display Port Presence Strap
T8
RSVD37 J16 1 : Disabled; No Physical Display Port
C T56
T57
PAD
PAD
AJ31
AH31
AJ33
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
RSVD38
RSVD39
RSVD40
H16
G16
CFG4 * attached to Embedded Display Port C
AT33
RSVD_NCTF3 AP35
RSVD_NCTF4 AR34
RSVD_NCTF5
CFG6
F25 PCIE Port Bifurcation Straps
F24 RSVD8 CFG5
F23 RSVD9
RSVD10
1
D24 B34 11: (Default) x16 - Device 1 functions 1 and 2 disabled
G25 RSVD11 RSVD_NCTF6 A33
RSVD12 RSVD_NCTF7 R43 R44
G24
E23
D23
RSVD13
RSVD14
RSVD_NCTF8
RSVD_NCTF9
A34
B35
C35
1K_0402_1%
@
1K_0402_1% CFG[6:5]
*10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
2
C30 RSVD15 RSVD_NCTF10
RSVD16 01: Reserved - (Device 1 function 1 disabled ; function
A31
B30 RSVD17 2 enabled)
B29 RSVD18
RSVD19 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
D30 AJ32
B31 RSVD20 RSVD51 AK32
A30 RSVD21 RSVD52
C29 RSVD22
RSVD23
AN35
J20 BCLK_ITP AM35 CFG7
B18 RSVD24 BCLK_ITP#
RSVD25 PEG DEFER TRAINING
1
B B
R45
@
1K_0402_1% 1: (Default) PEG Train immediately following xxRESETB
J15 AT2 CFG7
RSVD27 RSVD_NCTF11 AT1 de assertion
2
RSVD_NCTF12 AR1
RSVD_NCTF13
0: PEG Wait for BIOS for training
B1
KEY
TYCO_2013620-2_IVY BRIDGE
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 8 of 65
5 4 3 2 1
5 4 3 2 1
VCC51
1
Y34 1
Y33 VCC52
Y32 VCC53 C36 @ R46
Y31 VCC54 0.1U_0402_10V7K 75_0402_5%
Y30 VCC55 2
2
Y29 VCC56
Y28 VCC57
VCC58
Reserve 0.1u to avoid noise Place the PU resistor close to CPU
Y27
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# R47 1 2 43_0402_5%
SVID
1
R32
R31 VCC84 R51
R30 VCC85
VCC86 100_0402_1%
R29 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
R28 VCC87
SENSE LINES
2
R27 VCC88 AJ35 VCCSENSE_R R52 1 2 0_0402_5% VCCSENSE
R26 VCC89 VCC_SENSE AJ34 1 2 VCCSENSE <59>
VSSSENSE_R R53 0_0402_5% VSSSENSE
P35 VCC90 VSS_SENSE VSSSENSE <59>
P34 VCC91 +1.05VS
VCC92
1
P33 R1294 2 1 10_0402_1%
P32 VCC93 B10 VCCIO_SENSE R54
P31 VCC94 VCCIO_SENSE A10 2 1 VCCIO_SENSE <57>
VSSIO_SENSE 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO
VCC96
R1297 10_0402_1% VSS_SENCE 100ohm +-1% pull-down to GND near processor
A P29 A
2
P28 VCC97
P27 VCC98
P26 VCC99
VCC100
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
TYCO_2013620-2_IVY BRIDGE Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 9 of 65
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V_CPU_VDDQ
+1.5V_CPU_VDDQ C287 1 2 0.1U_0402_10V6K
2
1 2 0.1U_0402_10V6K Q8 BSS138_SOT23
G
C96
For Deep S3
C95 1 2 0.1U_0402_10V6K 1 3
S
+3VALW +VSB U3
8 1
D 7 2 R74 1 @ 2 0_0402_5% +V_DDR_REFA_R D
+VREF_DQ_DIMMA
1
R56 need to check on SDV 6 3 R75 1 2 0_0402_5% +V_DDR_REFB_R
+VREF_DQ_DIMMB
5 @
1
R1537 @ R56
1
100K_0402_5% 100K_0402_5% AO4304L_SO8
4
AO4304L @ R1487 1 3
S
2
2
Vgs=10V,Id=18A, 470_0603_5% R139 @ @ R132
RUN_ON_CPU1.5VS3 1 R1349 2
Q7 BSS138_SOT23 1K_0402_1% 1K_0402_1%
Rds<6.7m ohm
G
470K_0402_5%
2
P/N: SB00000RV00 DRAMRST_CNTRL
3
D D
R1538
1
1 2 2 1 5 SUSP
<37,51,55,57> SUSP G G
0_0402_5%
1
D R57 C97
2 S Q4A 470K_0402_5% 0.01U 50V K X7R 0603 S
<45> CPU1.5V_S3_GATE
4
@ 2 Q4B
G
2N7002KDWH_SOT363-6 6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
2
Q156 2N7002KDWH_SOT363-6
S
3
2N7002_SOT23
+VCC_GFXCORE_AXG
VCC_AXG_SENSE <59>
Place the PU/PD
2
+VCC_GFXCORE_AXG JCPU1G
POWER R66
100_0402_1%
VSS_AXG_SENSE <59> resistor close
to CPU within 2
OPT@ +1.5V_CPU_VDDQ inch
R1488 OPT@
(Reserve power
1
C 46A AT24 AK35 VCC_AXG_SENSE_R10_0402_5%2 C
side)
SENSE
LINES
VAXG1 VAXG_SENSE
1
AT23 AK34 VSS_AXG_SENSE_R 1 2
VAXG2 VSSAXG_SENSE
2
2
AR24 +V_SM_VREF_CNT
1
AR23 VAXG7
VAXG8
1
AR21 0.1U_0402_16V4Z 1
AR20 VAXG9
VAXG10 C114 R88
AR18 AL1 1K_0402_1%
AR17 VAXG11 SM_VREF
AP24 VAXG12 2
VREF
VAXG13
2
AP23
AP21 VAXG14
AP20 VAXG15 B4 +V_DDR_REFA_R
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R
AP17 VAXG17 SB_DIMM_VREFDQ
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
AN20 VAXG21
AN18 VAXG22
VAXG23 5A
DDR3 -1.5V RAILS
AN17 +1.5V_CPU_VDDQ
AM24 VAXG24 AF7
GRAPHICS
330U_D2_2.5VY_R9M
AM21 AF1 1
VAXG27 VDDQ3
C123
AM20 AC7 1 1 1 1 1 1
VAXG28 VDDQ4
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
C118
10U_0603_6.3V6M
C119
10U_0603_6.3V6M
C120
10U_0603_6.3V6M
C121
10U_0603_6.3V6M
C122
AM18 AC4 +
AM17 VAXG29 VDDQ5 AC1
AL24 VAXG30 VDDQ6 Y7 @
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 2
B AL21 VAXG32 VDDQ8 Y1 B
AL20 VAXG33 VDDQ9 U7
AL18 VAXG34 VDDQ10 U4
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4
AK21 VAXG38 VDDQ14 P1
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
AJ20 VAXG45 +VCCSA
AJ18 VAXG46 6A
AJ17 VAXG47 M27 +VCCSA
AH24 VAXG48 VCCSA1 M26
SA RAIL
330U_D2_2.5VY_R9M
AH21 J26 1 1 1 1 1
VAXG51 VCCSA4
10U_0805_6.3V6M
C124
10U_0805_6.3V6M
C125
10U_0805_6.3V6M
C126
10U_0805_6.3V6M
C127
C128
AH20 J25
AH18 VAXG52 VCCSA5 J24 @ + @
AH17 VAXG53 VCCSA6 H26
VAXG54 VCCSA7 H25 2 2 2 2
VCCSA8 2
1.8V RAIL
H23
+1.8VS VCCSA_SENSE +VCCSA_SENSE <56>
@
1 R67 2 +1.8VS_VCCPLL B6 1 2 0_0402_5%
10U_0805_6.3V6M 1U_0402_6.3V6K R68
A A6 VCCPLL1 C22 A
1
MISC
2 2 2 2 A19
VCCIO_SEL
330U_B2_2.5VM_R15M 1U_0402_6.3V6K
TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data Compal Electronics, Inc.
11/24 change 22U X2 to 330U B2 size Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
ME@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 10 of 65
5 4 3 2 1
5 4 3 2 1
JCPU1H JCPU1I
D AT35 AJ22 D
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR7 VSS19 VSS100 AH16 N34 VSS177 VSS250 E2
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP31 VSS23 VSS104 AG8 N30 VSS181 VSS254 D29
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25
C AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23 C
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AN7 VSS42 VSS123 AC8 K29 VSS200 VSS273 B8
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
AL28 VSS58 VSS139 Y8 H6 VSS216
AL25 VSS59 VSS140 Y6 H5 VSS217
AL22 VSS60 VSS141 Y5 H4 VSS218
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220
AL13 VSS63 VSS144 W35 H1 VSS221
B AL10 VSS64 VSS145 W34 G35 VSS222 B
AL7 VSS65 VSS146 W33 G32 VSS223
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225
AK33 VSS68 VSS149 W30 G23 VSS226
AK30 VSS69 VSS150 W29 G20 VSS227
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80
ME@ ME@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 11 of 65
5 4 3 2 1
5 4 3 2 1
DDR3 SO-DIMM A
+1.5V +1.5V +1.5V
1
R78
1K_0402_1% +VREF_DQ_DIMMA
3A@1.5V
For RF request
JDIMM1 ME@
2
+VREF_DQ_DIMMA 1 2
VREF_DQ VSS1 DDR_A_D[0..63] <7>
3 4 DDR_A_D4
VSS2 DQ4
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DDR_A_DQS[0..7] <7>
0.1U_0402_10V6K
2.2U_0603_6.3V6K
D DDR_A_D1 7 DQ0 DQ5 8 D
1 1 DQ1 VSS3 1 1 1
R79 C141 C140 9 10 DDR_A_DQS#0 C51 C52 C53
VSS4 DQS#0 DDR_A_DQS#[0..7] <7>
1K_0402_1% 11 12 DDR_A_DQS0 @ @ @
13 DM0 DQS0 14
DDR_A_MA[0..15] <7>
2
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4 Layout Note:
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2 Place near DIMM (10uF_0603_6.3V)*8
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100 (0.1uF_402_10V)*4
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<7> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <7>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<7> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <7>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# +1.5V +1.5V
BA0 RAS# DDR_A_RAS# <7>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
1
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118
10U_0603_6.3V6M
10U_0603_6.3V6M
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
VDD15 VDD16 R80
DDR_A_MA13 119 120 M_ODT1
A13 ODT1 M_ODT1 <7> 1K_0402_1% C151 1 C142 1 C143 1 C152 1 C144 1 C145 1 C153 1 C146 1 C154 1 C155 1 C147 1 C156 1 + C148
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
123 S1# NC2 124 220U_6.3V_M
@ @
2
125 VDD17 VDD18 126 +VREF_CA
127 NCTEST VREF_CA 128 2 2 2 2 2 2 2 2 2 2 2 2 2
VSS27 VSS28
0.1U_0402_10V6K
2.2U_0603_6.3V6K
B DDR_A_D32 129 130 DDR_A_D36 B
DQ32 DQ36
1
DDR_A_D33 131 132 DDR_A_D37 1 1
133 DQ33 DQ37 134 C149 C150
DDR_A_DQS#4 135 VSS29 VSS30 136 R81
DDR_A_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_A_D38 2 2
2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
Layout Note: Layout Note:
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46 Place near DIMM Place near DIMM
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170 +0.75VS
DQS#6 DM6 DDR_A_DM[0:7] connect to GND
DDR_A_DQS6 171 172
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
DQ51 VSS45
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
179 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DQ56 DQ61 1 1 1 1
DDR_A_D57 183 184 C288 C158 C159 C160
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190 2 2 2 2
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62
A DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 A
195 DQ59 DQ63 196
R82 VSS51 VSS52
1 2 197 198
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,37,46>
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 <13,15,37,46>
1
1 1 203 204
VTT1 VTT2 +0.75VS
C290 C162 R83 205 206 0.65A@0.75V
2.2U_0603_6.3V6K
2 2
0.1U_0402_10V6K 10K_0402_5% G1 G2
LCN_DAN06-K4806-0103
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 12 of 65
5 4 3 2 1
5 4 3 2 1
DDR3 SO-DIMM B
+1.5V
+1.5V +1.5V
1
R84
1K_0402_1% +VREF_DQ_DIMMB
3A@1.5V
For RF request
JDIMM2 ME@
DDR_B_D[0..63] <7>
2
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4 DDR_B_DQS[0..7] <7>
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
DDR_B_D0 5 6 DDR_B_D5
0.1U_0402_10V6K
DQ0 DQ5
2.2U_0603_6.3V6K
1 1 DDR_B_D1 7 8 1 1 1
DQ1 VSS3 DDR_B_DQS#[0..7] <7>
R85 C289 C157 9 10 DDR_B_DQS#0 C54 C55 C56
D 1K_0402_1% 11 VSS4 DQS#0 12 DDR_B_DQS0 @ @ @ D
DM0 DQS0 DDR_B_MA[0..15] <7>
13 14
2
2 2 DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6 2 2 2
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,7>
31 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
37 DQ11 DQ15 38
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26
C C
1
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 <7>
117 118
VDD15 VDD16 R86
DDR_B_MA13 119 120 M_ODT3
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
A13 ODT1 M_ODT3 <7> 1K_0402_1%
DDR_CS3_DIMMB# 121 122
<7> DDR_CS3_DIMMB# S1# NC2 C161 1 C282 1 C163 1 C164 1 C165 1 C166 1 C167 1 C168 1 C169 1 C170 1 C171 1 C172 1
123 124
2
125 VDD17 VDD18 126 +VREF_CB
NCTEST VREF_CA @ @
127 128
VSS27 VSS28 2 2 2 2 2 2 2 2 2 2 2 2
0.1U_0402_10V6K
2.2U_0603_6.3V6K
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
1
DDR_B_D33 131 132 DDR_B_D37 1 1
B 133 DQ33 DQ37 134 C280 C281 B
DDR_B_DQS#4 135 VSS29 VSS30 136 R87
DDR_B_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_B_D38 2 2
2
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
157 VSS37 VSS38 158
Layout Note: Layout Note:
DDR_B_D42 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47 Place near DIMM Place near DIMM
161 DQ43 DQ47 162
DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172 +0.75VS
DQS6 VSS43 DDR_B_DM[0:7] connect to GND
173 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
VSS46 DQ60
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
DQ57 VSS47 1 1 1 1
185 186 DDR_B_DQS#7 C173 C174 C175 C176
187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 2 2 2 2
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196
A R95 VSS51 VSS52 A
1 2 197 198
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
VDDSPD SDA SMB_DATA_S3 <12,15,37,46>
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <12,15,37,46>
R97 10K_0402_5% 203 204 +0.75VS
VTT1 VTT2
1 1
205
G1 G2
206 0.65A@0.75V
C177 C178
2.2U_0603_6.3V6K 0.1U_0402_10V6K TYCO_2-2013287-1
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 13 of 65
5 4 3 2 1
5 4 3 2 1
W=20mils W=20mils
+RTCBATT +RTCVCC CMOS U4A
EC and Mini card debug port
2 R99 1 +RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <37,45>
1
1 C183 JCMOS A38 LPC_AD1
1K_0402_5% FWH1 / LAD1 LPC_AD1 <37,45>
LPC
1U_0603_10V4Z @ SHORT PADS PCH_RTCX2 C20 B37 LPC_AD2
C179 RTCX2 FWH2 / LAD2 C37 LPC_AD2 <37,45>
LPC_AD3
1U_0603_10V4Z LPC_AD3 <37,45>
2
R103 1 2 20K_0402_5% 2 PCH_RTCRST# D20 FWH3 / LAD3
2 RTCRST# D36 LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# <37,45>
R100 1 2 20K_0402_5% PCH_SRTCRST# G22
SRTCRST# E36
1 LDRQ0#
1
D SM_INTRUDER# K22 K36 D
RTC
C182 SERIRQ <45>
1U_0603_10V4Z @ JME INTRUDER# LDRQ1# / GPIO23
SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ 2 1
+3VS
2
2 INTVRMEN SERIRQ R104 10K_0402_5%
+RTCVCC
AM3 SATA_DTX_C_IRX_N0 SSD
SATA0RXN SATA_DTX_C_IRX_N0 <37>
R101 1 2 1M_0402_5% SM_INTRUDER# HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_P0 <37>
HDA_BCLK SATA0RXP AP7 SATA_ITX_C_DRX_N0 C184 2 1 0.01U_0402_16V7K SATA_ITX_DRX_N0
SATA 6G
SATA0TXN SATA_ITX_DRX_N0 <37>
R102 1 2 330K_0402_5% PCH_INTVRMEN HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 C185 2 1 0.01U_0402_16V7K SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 <37>
HDA_SYNC SATA0TXP
HDA_SPKR T10 AM10 SATA_DTX_C_IRX_N1 HDD
<42> HDA_SPKR SPKR SATA1RXN SATA_DTX_C_IRX_N1 <41>
AM8 SATA_DTX_C_IRX_P1
INTVRMEN
::Integrated
SATA1RXP SATA_DTX_C_IRX_P1 <41>
HDA_RST# K34 AP11 SATA_ITX_C_DRX_N1 C273 2 1 0.01U_0402_16V7K SATA_ITX_DRX_N1
HDA_RST# SATA1TXN AP10 SATA_ITX_DRX_N1 <41>
H VRM enable (Default) SATA_ITX_C_DRX_P1 C272 2 1 0.01U_0402_16V7K SATA_ITX_DRX_P1
* L Integrated VRM disable SATA1TXP SATA_ITX_DRX_P1 <41>
HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 ODD
<42> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <41>
(INTVRMEN should always be pull high.) AD5 SATA_DTX_C_IRX_P2
SATA2RXP SATA_DTX_C_IRX_P2 <41>
G34 AH5 SATA_ITX_C_DRX_N2 C186 2 1 0.01U_0402_16V7K SATA_ITX_DRX_N2_CONN
HDA_SDIN1 SATA2TXN AH4 SATA_ITX_DRX_N2_CONN <41>
SATA_ITX_C_DRX_P2 C187 2 1 0.01U_0402_16V7K SATA_ITX_DRX_P2_CONN
C34 SATA2TXP SATA_ITX_DRX_P2_CONN <41>
HDA_SDIN2 AB8
IHDA
A34 SATA3RXN AB10
HDA_SDIN3 SATA3RXP AF3
+3VS SATA3TXN AF1
ME_FLASH R109 1 2 0_0402_5% HDA_SDOUT A36 SATA3TXP
<45> ME_FLASH HDA_SDO
R105 1 @ 2 1K_0402_5% HDA_SPKR Y7
SATA
SATA4RXN Y5
R107 1 2 1K_0402_1% PCH_GPIO33 C36 SATA4RXP AD3
HIGH= Enable ( No Reboot ) @
HDA_DOCK_EN# / GPIO33 SATA4TXN
LOW= Disable (Default) AD1
* +3V_PCH R317 2 @ 1 10K_0402_5% PCH_GPIO13 N32
HDA_DOCK_RST# / GPIO13
SATA4TXP
Y3
SATA5RXN Y1
C SATA5RXP AB3 C
R110 2 1 51_0402_5% PCH_JTAG_TCK J3 SATA5TXN AB1
JTAG_TCK SATA5TXP
+3V_PCH PCH_JTAG_TMS H7 Y11 +1.05VS_VCC_SATA
JTAG_TMS SATAICOMPO
JTAG
R106 2 @ 1 1K_0402_5% HDA_SDOUT PCH_JTAG_TDI K5 Y10 SATA_COMP R111 1 2 37.4_0402_1%
JTAG_TDI SATAICOMPI
Low = Disabled (Default) PCH_JTAG_TDO H1
* High = Enabled
JTAG_TDO
SATA3RCOMPO
AB12 +1.05VS_SATA3
[Flash Descriptor Security Overide] AB13 SATA3_COMP R113 1 2 49.9_0402_1%
SATA3COMPI
SPI_CLK_PCH_0 R298 1 2 33_0402_5%
SPI_CLK_PCH_1 R299 1 2 33_0402_5% SPI_CLK_PCH T3 AH1 RBIAS_SATA3 R115 1 2 750_0402_1%
SPI_CLK SATA3RBIAS
+3V_PCH SPI_SB_CS0#_R R130 2 1 0_0402_5% SPI_SB_CS0# Y14
SPI_CS0#
HDD_LED# <47>
R108 2 1 1K_0402_5% HDA_SYNC SPI_CS1#_R R303 2 1 0_0402_5% SPI_CS1# T1
SPI_CS1#
SPI
P3 HDD_LED# R120 2 1 10K_0402_5%
SATALED# +3VS
This signal has a weak internal pull-down SPI_SI_R R133 1 2 33_0402_5%
SPI_SI_R1 R204 1 2 33_0402_5% SPI_SI V4 V14 PCH_GPIO21 R119 2 1 10K_0402_5%
+3VS
SPI_MOSI SATA0GP / GPIO21
On Die PLL VR Select is supplied by SPI_SO_L R131 2 1 33_0402_5% SPI_SO_R U3 P1 SATA_DET# R316 2 1 10K_0402_5%
1.5V when smapled high (Default) SPI_MISO SATA1GP / GPIO19 +3VS
SPI_SO_L1 R294 2 1 33_0402_5%
* 1.8V when sampled low SATA_DET# <37>
Needs to be pulled High for Chief River platfrom PANTHER-POINT_FCBGA989
B PCH_RTCX1 B
For EMI
HDA AUDIO 1 R98 2 PCH_RTCX2
+5VS SPI_CLK_PCH
10M_0402_5%
1
<42> HDA_BITCLK_AUDIO R112 1 2 HDA_BIT_CLK Y1
2
G
33_0402_5% 1 2
R124 @
<42> HDA_SYNC_AUDIO R114 1 2 HDA_SYNC_R 3 1 HDA_SYNC 32.768KHZ_12.5PF_CM31532768DZFT 33_0402_5%
33_0402_5%
S
1 1
2
1
Q10
C180 C181
<42> HDA_RST_AUDIO# R116 1 2 HDA_RST# BSS138_NL_SOT23-3 C190 @
18P_0402_50V8J 18P_0402_50V8J
33_0402_5% R1353 22P_0402_50V8J
1M_0402_5% 2 2
<42> HDA_SDOUT_AUDIO R118 1 2 HDA_SDOUT
2
33_0402_5%
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI SPI_SO_L 2 CS# VCC 7 SPI_HOLD# SPI_SO_L1 2 CS# VCC 7 SPI_HOLD#_1
SPI_WP# 3 DO HOLD# 6 SPI_CLK_PCH_0 C191 SPI_WP#_1 3 DO(IO1) HOLD#(IO3) 6 SPI_CLK_PCH_1 C275
WP# CLK WP#(IO2) CLK
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC, XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 14 of 65
5 4 3 2 1
5 4 3 2 1
+3V_PCH
U4B
1 R136 2 2.2K_0402_5% 2N7002KDWH 2 R137 1
+3V_PCH 2.2K_0402_5%
PCIE_PRX_DTX_N1 BG34 Vth= min 1V, max 2.5V
2
<38> PCIE_PRX_DTX_N1 PERN1 R135 ESD 2KV R138 1
PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPIO11 1 2 2.2K_0402_5% 2 2.2K_0402_5%
G
<38> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11
LAN C192 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32
<38> PCIE_PTX_C_DRX_N1 1 2 0.1U_0402_10V7K PETN1
C193 PCIE_PTX_DRX_P1 AU32 H14 PCH_SMBCLK
<38> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK 6 1
PCH_SMBCLK SMB_CLK_S3
PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA SMB_CLK_S3 <12,13,37,46>
S
5
<37> PCIE_PRX_DTX_N2 PERN2 SMBDATA
PCIE_PRX_DTX_P2 BF34 Q60A
G
<37> PCIE_PRX_DTX_P2 PERP2
WLAN C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32 2N7002KDWH_SOT363-6
<37> PCIE_PTX_C_DRX_N2 1 2 0.1U_0402_10V7K PETN2
C195 PCIE_PTX_DRX_P2 AY32
D <37> PCIE_PTX_C_DRX_P2 PETP2 A12 3 4 D
SMBUS
PCH_SMBDATA SMB_DATA_S3
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7> SMB_DATA_S3 <12,13,37,46>
Q60B
S
BJ36 PERN3 C8 SML0CLK 2N7002KDWH_SOT363-6
AV34 PERP3 SML0CLK
AU34 PETN3 G12 SML0DATA
PETP3 SML0DATA
PCIE_PRX_DTX_N4 BF36
<44> PCIE_PRX_DTX_N4 PERN4
PCIE_PRX_DTX_P4 BE36
<44> PCIE_PRX_DTX_P4 PERP4
Card Reader C277 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT# DIMM1, DIMM2, Mini CARD, TP
<44> PCIE_PTX_C_DRX_N4 1 2 0.1U_0402_10V7K PETN4 SML1ALERT# / PCHHOT# / GPIO74
C276 PCIE_PTX_DRX_P4 BB34
<44> PCIE_PTX_C_DRX_P4 PETP4 E14 SML1CLK
BG37 SML1CLK / GPIO58 1 R141 2 2.2K_0402_5%
PCI-E*
PERN5 +3V_PCH +3V_PCH
BH37 M16 SML1DATA
2
AY36 PERP5 SML1DATA / GPIO75 1 R142 2 2.2K_0402_5%
G
BB36 PETN5
PETP5
BJ38 SML1CLK 6 1 EC_SMB_CK2
BG38 PERN6 EC_SMB_CK2 <23,32,40,45>
S
5
AU36 PERP6 M7 Q61A
Controller
G
AV36 PETN6 CL_CLK1 2N7002KDWH_SOT363-6
PETP6
BG40 T11 3 4
Link
SML1DATA EC_SMB_DA2
BJ40 PERN7 CL_DATA1 EC_SMB_DA2 <23,32,40,45>
Q61B
S
AY40 PERP7 2N7002KDWH_SOT363-6
BB40 PETN7 P10
PETP7 CL_RST1#
BE38
BC38 PERN8
AW38 PERP8
AY38 PETN8
PETP8 CLK_REQ_GPU#_R <23>
M10 CLK_REQ_GPU#_R R202 1 2 10K_0402_5% +3V_PCH
C PEG_A_CLKRQ# / GPIO47 +3V_PCH C
CLK_PCIE_LAN# Y40
<38> CLK_PCIE_LAN# CLK_PCIE_LAN Y39 CLKOUT_PCIE0N
<38> CLK_PCIE_LAN CLKOUT_PCIE0P AB37 CLK_PCIE_VGA# PCH_GPIO11 2 R134 1
LAN 10K_0402_5%
J2 CLKOUT_PEG_A_N AB38 CLK_PCIE_VGA# <23>
CLKREQ_LAN# CLK_PCIE_VGA
CLOCKS
<38> CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <23> R329
DRAMRST_CNTRL_PCH 2 1 1K_0402_5%
+3VS
@ R176 @ C199
A R158 2 1 10K_0402_5% WLAN_CLKREQ1# 33_0402_5% 22P_0402_50V8J A
CLK_PCI_LPBACK 2 1 1 2
R308 2 1 10K_0402_5% CLKREQ_TV#_R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 15 of 65
5 4 3 2 1
5 4 3 2 1
D D
U4C
1
DMI
FDI
BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
1 DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 R179
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
C1060 DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 330K_0402_5%
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
0.1U_0402_16V4Z DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AU18 DMI2TXP
<5> DMI_CRX_PTX_P3
2
2 DMI3TXP AW16 FDI_INT
FDI_INT FDI_INT <5>
DSWODVREN
R177
5
1
4 BG25 BC10 FDI_FSYNC1
:
1 Y SYS_PWROK <6> DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
PCH_PWROK DSWODVREN - On Die DSW VR Enable R183
A R178 *
G
:
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 H Enable @ 330K_0402_5%
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5>
750_0402_1% L Disable
3
2
FDI_LSYNC1
MC74VHC1G08DFT2G SC70 5P 100K_0402_1% 4mil width and place
within 500mil of the PCH
2
A18 DSWODVREN
DSWVRMEN
For Deep S3 R198 1 2 0_0402_5% PBTN_OUT#_R E20 G10 Can be left NC when IAMT is not support on the platfrom
B <45> PBTN_OUT# PWRBTN# SLP_A# B
+3V_PCH
+3VS
+3VALW
A A
D D
+3VS
U4D
OPT@ EDID_CLK PCH_ENBKL J47 AP43
R836 2.2K_0402_5%
<34> PCH_ENBKL PCH_ENVDD M45 L_BKLTEN SDVO_TVCLKINN AP45
OPT@ EDID_DATA <34> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
R835 2.2K_0402_5%
P45 AM42
<34> PCH_PWM L_BKLTCTL SDVO_STALLN AM40
EDID_CLK T40 SDVO_STALLP
OPT@ <34> EDID_CLK L_DDC_CLK +3VS
R205 1 2 2.2K_0402_5% CTRL_CLK EDID_DATA K47 AP39
<34> EDID_DATA L_DDC_DATA SDVO_INTN AP40
OPT@ SDVO_INTP
R261 1 2 2.2K_0402_5% CTRL_DATA CTRL_CLK T45
CTRL_DATA P39 L_CTRL_CLK HDMICLK R203 2 OPT@ 1 2.2K_0402_5%
L_CTRL_DATA
LVDS_IBG AF37 P38 HDMICLK
HDMICLK <36>
AF36 LVD_IBG SDVO_CTRLCLK M39 HDMIDAT HDMIDAT R267 2 OPT@ 1 2.2K_0402_5%
OPT@ LVD_VBG SDVO_CTRLDATA HDMIDAT <36>
R257 2 1 2.37K_0402_1% LVDS_IBG
AE48
AE47 LVD_VREFH AT49
Remove netname LVD_REF LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40 TMDS_B_HPD
AK39 DDPB_HPD TMDS_B_HPD <36>
LVDS_ACLK#
<34> LVDS_ACLK# LVDSA_CLK#
LVDS
LVDS_ACLK AK40 AV42 TMDS_B_DATA2#_PCH
<34> LVDS_ACLK LVDSA_CLK DDPB_0N AV40 TMDS_B_DATA2_PCH TMDS_B_DATA2#_PCH <36>
LVDS_A0# AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCH TMDS_B_DATA2_PCH <36>
C <34> LVDS_A0# LVDS_A1# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS_B_DATA1_PCH TMDS_B_DATA1#_PCH <36> C
<34> LVDS_A1# LVDSA_DATA#1 DDPB_1P TMDS_B_DATA1_PCH <36>
CRT
CRT_DDC_CLK T39 AT43
<35> CRT_DDC_CLK CRT_DDC_DATA M40 CRT_DDC_CLK DDPD_AUXP BH41
B <35> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD B
+3VS BB43
CRT_HSYNC M47 DDPD_0N BB45
<35> CRT_HSYNC CRT_VSYNC M49 CRT_HSYNC DDPD_0P BF44
OPT@ <35> CRT_VSYNC CRT_VSYNC DDPD_1N
R848 1 2 2.2K_0402_5% CRT_DDC_CLK BE44
DDPD_1P BF42
CRT_IREF T43 DDPD_2N BE42
OPT@ DAC_IREF DDPD_2P
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 17 of 65
5 4 3 2 1
5 4 3 2 1
+3VS
RP2
8 1 PCI_PIRQA#
7 2 PCI_PIRQD#
6 3 PCI_PIRQC#
5 4 PCI_PIRQB# U4E
AY7
8.2K_0804_8P4R_5% RSVD1 AV7
BG26 RSVD2 AU3
RP1 BJ26 TP1 RSVD3 BG4
8 1 PCH_GPIO2 BH25 TP2 RSVD4
7 2 DGPU_PWR_EN BJ16 TP3 AT10
D 6 3 PCH_GPIO4 BG16 TP4 RSVD5 BC8 D
5 4 ODD_DA#_R AH38 TP5 RSVD6
AH37 TP6 AU2
8.2K_0804_8P4R_5% AK43 TP7 RSVD7 AT4
AK45 TP8 RSVD8 AT3
C18 TP9 RSVD9 AT1
+3VS N30 TP10 RSVD10 AY3
PPT EDS DOC#474146 TP11 RSVD11
H3 AT5
R305 1 @ 2 8.2K_0402_5% PCH_GPIO51 AH12 TP12 RSVD12 AV3
AM4 TP13 RSVD13 AV1
TP14 RSVD14
R297 1 @ 2 8.2K_0402_5% DGPU_GC6_EN USB3.0 AM5
Y13 TP15 RSVD15
BB1
BA3
R213 1 2 8.2K_0402_5% PCH_GPIO5 K24 TP16 RSVD16 BB5
L24 TP17 RSVD17 BB3
Port1 Camera USB TP18 RSVD18
R225 1 2 8.2K_0402_5% PCH_WL_OFF# AB46 BB7
AB45 TP19 RSVD19 BE8
1 2 TP20 RSVD20 BD4
RSVD
R212 8.2K_0402_5% NVDD_PWR_EN Port2 RSVD21 BF6
R252 1 2 8.2K_0402_5% DGPU_HOLD_RST# RSVD22
Port3 LEFT USB B21 AV5
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
R306 1 2 8.2K_0402_5% DGPU_GC6_EN BG46 TP23 AT8
@ Port4 TP24 RSVD25
R214 1 @ 2 8.2K_0402_5% DGPU_HOLD_RST# AY5
RSVD26 BA2
USB30_RX_N1 BE28 RSVD27
<34> USB30_RX_N1 BC30 USB3Rn1 AT12
USB30_RX_N3 BE32 USB3Rn2 RSVD28 BF3
<48> USB30_RX_N3 BJ32 USB3Rn3 RSVD29
USB30_RX_P1 BC28 USB3Rn4
<34> USB30_RX_P1 USB3Rp1 USB DEBUG= PORT1 AND PORT9
R215 2 @ 1 1K_0402_5% PCH_WL_OFF# BE30
C USB30_RX_P3 BF32 USB3Rp2 C
<48> USB30_RX_P3 BG32 USB3Rp3 C24 USB20_N0
USB20_N0 <34>
<34> USB30_TX_N1
USB30_TX_N1 AV26 USB3Rp4
USB3Tn1
USBP0N
USBP0P
A24 USB20_P0
USB20_P0 <34>
Camera
BB26 C25
USB30_TX_N3 AU28 USB3Tn2 USBP1N B25
A16 swap overide Strap/Top-Block <48> USB30_TX_N3 USB3Tn3 USBP1P
AY30 C26 USB20_N2
Swap Override jumper USB20_N2 <48>
<34> USB30_TX_P1
USB30_TX_P1 AU26 USB3Tn4
USB3Tp1
USBP2N
USBP2P
A26 USB20_P2
USB20_P2 <48>
LEFT USB
AY26 K28
USB30_TX_P3 AV28 USB3Tp2 USBP3N H28
<48> USB30_TX_P3 AW30 USB3Tp3 USBP3P E28
Low = A16 swap USB3Tp4 USBP4N D28
PCI_GNT3# override/Top-Block USBP4P C28 USB20_N5
USB20_N5 <49>
Swap Override enabled USBP5N
USBP5P
A28 USB20_P5
USB20_P5 <49>
RIGHT USB 1 (CHARGER PORT, SUB/B)
C29
USBP6N B29
PCI_PIRQA# K40 USBP6P N28
***High=Default PCI_PIRQB# K38 PIRQA#
PIRQB#
USBP7N
USBP7P
M28 Some PCH config not support USB port 6 & 7.
PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# G38 PIRQC# USBP8N K30
<23> DGPU_HOLD_RST# PIRQD# USBP8P G30 USB20_N9
USB20_N9 <49>
<15,32> S_DGPU_RST
R1505 1 2 0_0402_5% DGPU_HOLD_RST# C46
REQ1# / GPIO50
USBP9N
USBP9P
E30 USB20_P9
USB20_P9 <49>
RIGHT USB 2 (SUB/B)
USB
NVDD_PWR_EN C44 C30 USB20_N10
<58> NVDD_PWR_EN USB20_N10 <37>
<23,51> DGPU_PWR_EN
DGPU_PWR_EN E40 REQ2# / GPIO52
REQ3# / GPIO54
USBP10N
USBP10P
A30 USB20_P10
USB20_P10 <37>
WLAN
L32
PCH_GPIO51 D47 USBP11N K32
DGPU_GC6_EN E42 GNT1# / GPIO51 USBP11P G32
GPIO53 => This Signal has a weak internal pull-up. <27> DGPU_GC6_EN GNT2# / GPIO53 USBP12N
PCH_WL_OFF# F46 E32
NOTE: The internal pull-up is disabled after <37> PCH_WL_OFF# GNT3# / GPIO55 USBP12P C32 USB20_N13
USB20_N13 <47>
PLTRST# deasserts. USBP13N
USBP13P
A32 USB20_P13
USB20_P13 <47>
BT
PCH_GPIO2 G42 +3V_PCH
ODD_DA#_R G40 PIRQE# / GPIO2
<41> ODD_DA#_R PCH_GPIO4 C42 PIRQF# / GPIO3 C33 USBRBIAS 1 R218 2 RP3
B PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# USB_OC5# 4 5 B
PIRQH# / GPIO5 Within 500 mils 22.6_0402_1%
USB_OC2# 3 6
B33 USB_OC7# 2 7
K10 USBRBIAS USB_OC0# 1 8
20111024 Del PCI_PME# PME#
PLT_RST# C6 A14 USB_OC0# 10K_1206_8P4R_5%
<23,32,37,38,44,45,6> PLT_RST# PLTRST# OC0# / GPIO59 K20 USB_OC1#
OC1# / GPIO40 B17 USB_OC2# USB_OC1# <48>
1 2 CLK_PCI_LPBACK_R H49 OC2# / GPIO41 C16 USB_OC3# USB_OC2# <49>
R219 22_0402_5%
<15> CLK_PCI_LPBACK 1 2 H43 CLKOUT_PCI0 OC3# / GPIO42 L16
R220 22_0402_5% CLK_PCI_EC_R USB_OC4# RP4
<45> CLK_PCI_EC 2 1 CLK_PCI_DB_R J48 CLKOUT_PCI1 OC4# / GPIO43 A16 USB_OC5# USB_OC4# <49> USB_OC6# 4 5
R173 22_0402_5%
<37> CLK_PCI_DB K42 CLKOUT_PCI2 OC5# / GPIO9 D14 3 6
@ USB_OC6# USB_OC1#
H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7# USB_OC4# 2 7
CLKOUT_PCI4 OC7# / GPIO14 USB_OC3# 1 8
PANTHER-POINT_FCBGA989 10K_1206_8P4R_5%
PLT_RST#
1
A
0 1 Reserved A
GNT1#/
GPIO51 1 0 Reserved
1 1 * SPI (Default)
0 0 LPC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 18 of 65
5 4 3 2 1
5 4 3 2 1
SKU ID +3VS
Optimus 0 0 X
SLI@ 2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
Reserve 0 1 X @ @
1
DIS PCH_GPIO38
(SLI) 1 0 X
PCH_GPIO67
<15> PCH_GPIO67
D
+3VS Reserve 1 1 X PCH_GPIO70 D
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
R235 2 1 10K_0402_5% EC_SMI# GC6_EVENT#
<23,32> GC6_EVENT#
OPT@
R233 1 2 10K_0402_5%
+3VS
1
U4F
T7 C40 PCH_GPIO68
BMBUSY# / GPIO0 TACH4 / GPIO68
R227 1 2 10K_0402_5% PCH_GPIO1 A42 B41 S_DGPU_PWR_EN
TACH1 / GPIO1 TACH5 / GPIO69 S_DGPU_PWR_EN <32,51>
R228 1 2 10K_0402_5% PCH_GPIO6 H36 C41 PCH_GPIO70 9/18 Reseve for SKU ID
+3VS TACH2 / GPIO6 TACH6 / GPIO70 S_DGPU_PWR_EN R268 1 2 10K_0402_5% +3VS
EC_SCI# E38 A40 S_NVDD_PWR_EN
<45> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71 S_NVDD_PWR_EN <32>
GPIO28 S_NVDD_PWR_EN R237 1 2 10K_0402_5% +3VS
On-Die PLL Voltage Regulator EC_SMI# C10
<45> EC_SMI# GPIO8
This signal has a weak internal pull up
* H
L
:
:On-Die voltage regulator enable
On-Die PLL Voltage Regulator disable
+3V_PCH R229
R230
1
1
@ 2 10K_0402_5%
2 10K_0402_5%
PCH_GPIO12
EC_LID_OUT#
C4
G2
LAN_PHY_PWR_CTRL / GPIO12
P4
R236 1 2 10K_0402_5% +3VS
GPIO15 A20GATE GATEA20 <45>
1 2 1K_0402_5% PCH_GPIO28 <45> EC_LID_OUT# AU16
R240 @
R231 1 2 10K_0402_5% PCH_GPIO16 U2 PECI
+3VS SATA4GP / GPIO16
R232 1 2 10K_0402_1% P5 KBRST#
RCIN# KBRST# <45>
@
C D40 AY11 C
GPIO
DGPU_PWROK
<27,32,55,58> DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <6>
CPU/MISC
R238 1 2 10K_0402_5% PCH_BT_DISABLE# T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
+3VS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# <6>
R239 390_0402_5%
<37> PCH_BT_DISABLE# ODD_EN E8 T14
* PCH_GPIO27 (Have internal Pull-High) <41> ODD_EN GPIO24 INIT3_3V#
High: VCCVRM VR Enable @ PCH_THRMTRIP#_R <23,32>
0_0402_5% 2 1 R224 DS3_WAKE#_R E16 AY1 NV_CLE
<16,37,38> PCIE_WAKE# GPIO27 DF_TVS
Low: VCCVRM VR Disable
+3V_PCH R241 1 2 10K_0402_5% PCH_GPIO28 P8
GPIO28 AH8
<37,47> PCH_BT_ON# TS_VSS1
INIT3_3V
1 2 10K_0402_5% PCH_BT_ON# K1 +3VS
+3VS STP_PCI# / GPIO34
R242 AK11 This signal has weak internal
+3VALW R243 1 2 10K_0402_5% PCH_GPIO35 K4 TS_VSS2 PCH_GPIO68 R255 1 2 10K_0402_5%
GPIO35 PU, can't pull low
AH10
ODD_DETECT# V8 TS_VSS3 KBRST# R226 1 2 10K_0402_5%
<41> ODD_DETECT# SATA2GP / GPIO36 AK10
DS3@
R207 2 1 10K_0402_5% PCH_GPIO37 M5 TS_VSS4 PCH_THRMTRIP#_R R244 1 2 10K_0402_5%
SATA3GP / GPIO37
PCH_GPIO38 N2 P37
1 2 10K_0402_5% DS3_WAKE#_R SLOAD / GPIO38 NC_1
R245 @ Intel schematic reviwe recommand.
R247 1 2 10K_0402_5% PCH_GPIO39 M3
+3VS SDATAOUT0 / GPIO39
R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
R249 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
+3VS SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
SLAVE_PRESENT# D6 BH3
<32> SLAVE_PRESENT# GPIO57 VSS_NCTF_17
1 2 R250 ODD_DETECT# BH47
+3VS200K_0402_5% VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
B 10K_0402_5% A44 BJ44 H : Sandy Bridge B
R251 1 2 SLAVE_PRESENT# VSS_NCTF_2 VSS_NCTF_20
+3V_PCH PROC_SEL
A45 BJ45 L : IVY Bridge
VSS_NCTF_3 VSS_NCTF_21
NCTF
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22 +1.8VS
R259 1 2 10K_0402_5% PCH_GPIO37 A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 BJ6
VSS_NCTF_6 VSS_NCTF_24 R216
B3 C2 2.2K_0402_5%
VSS_NCTF_7 VSS_NCTF_25
B47 C48
VSS_NCTF_8 VSS_NCTF_26 NV_CLE 1 2
H_SNB_IVB# <6>
BD1 D1 R217 1K_0402_5%
VSS_NCTF_9 VSS_NCTF_27
BD49 D49 CLOSE TO THE BRANCHING POINT
VSS_NCTF_10 VSS_NCTF_28
BE1 E1
VSS_NCTF_11 VSS_NCTF_29
BE49 E49
VSS_NCTF_12 VSS_NCTF_30
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32
PANTHER-POINT_FCBGA989
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 19 of 65
5 4 3 2 1
5 4 3 2 1
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
C212
1 1 1 1 AD21 Voltage Rail Voltage Current (A)
CRT
VCCCORE[3]
10U_0603_6.3V6M
C209
AD23 U47 C213 C214 C215
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K 0.1U_0402_10V7K
2 10U_0603_6.3V6M
VCC CORE
AF23 VCCCORE[5] 2 2
VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36 +VCCA_LVDS 2 R295 1
VCCCORE[9] 1mA VCCALVDS
V5REF 5 0.001
AG26 0_0603_5%
AG27 VCCCORE[10] AK37
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
AJ26 VCCCORE[13] AM37
LVDS
L2
AJ27 VCCCORE[14] VCCTX_LVDS[1]
VCCCORE[15]
0.1UH_MLF1608DR10KT_10%_1608 Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2] 0.1uH inductor, 200mA
VCCCORE[17] 1 1 1
+1.05VS AP36 VccADAC 3.3 0.063
40mA VCCTX_LVDS[3] C216 C217 C218
AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
2 1 +1.05VS_VCCDPLLEXP AN19 VCCTX_LVDS[4] 2 2 2
R254 0_0603_5%
VCCIO[28]
VccADPLLA 1.05 0.08
HVCMOS
0_0603_5% VccCore 1.05 1.7
On-Die VR enabled mode (default). VCCIO[15]
1
AN17
VCCIO[16] V34
VCC3_3[7]
C219 VccDMI 1.05 0.047
0.1U_0402_10V7K
AN21 2
VCCIO[17]
VccIO 1.05 3.711
AN26
VCCIO[18]
AN27 3711mA AT16 +VCCAFDI_VRM VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+1.05VS AP21 +VCCP_VCCDMI +1.05VS
C VCCIO[20] C
VccSPI 3.3 0.01
+1.05VS AP23 AT20 +VCCP_VCCDMI 2 R258 1
VCCIO[21] VCCDMI[1] 0_0603_5%
1
+1.05VS
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
C225
DMI
1 1 1 1 1 AP24 VccDSW 3.3 0.001
VCCIO[22]
10U_0603_6.3V6M
C221
VCCIO
del R296 for 14' layout C220
AP26 AB36 +1.05VS_VCC_DMI_CCI 2 R300 1 1U_0402_6.3V6K
VCCIO[23] 70mA VCCCLKDMI 2
1 0_0603_5% VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.095
+3VS VCCIO[26] VCCDFTERM[1]
1 R260 2 +3VS_VCCA3GBG BH29 AG17 +VCCPNAND +1.8VS VccSusHDA 3.3 / 1.5 0.01
0_0603_5% VCC3_3[3] 190mA VCCDFTERM[2]
DFT / SPI
1
C227
0.1U_0402_10V7K AJ16 2 R293 1 VccVRM 1.8 / 1.5 0.167
VCCDFTERM[3] 0_0603_5%
2 +VCCAFDI_VRM AP16
VCCVRM[2] 1
AJ17 C228 VccCLKDMI 1.05 0.07
VCCDFTERM[4] 0.1U_0402_10V7K
PAD T48 @ +1.05VS_VCCAPLL_FDI BG6
VccAFDIPLL 2 +3VS VccSSC 1.05 0.095
1 R263 2 +1.05VS_VCCDPLL_FDI AP17 R399
+1.05VS VCCIO[27]
0_0603_5% V1 +3V_VCCPSPI 2 1 VccDIFFCLKN 1.05 0.055
FDI
+VCCAFDI_VRM
+1.5VS
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 20 of 65
5 4 3 2 1
5 4 3 2 1
10U_0805_10V4Z
C231
1U_0402_6.3V6K
C232
2 1 +VCCPDSW
1 AD49 N26 +1.05VS_VCCUSBCORE 2 R270 1
VCCACLK VCCIO[29] 0_0603_5%
2 2 1
C234 P26
0.1U_0402_10V7K T16 VCCIO[30] C233
D 2 VCCDSW3_3 1mA P28 1U_0402_6.3V6K D
VCCIO[31] 2
V12 T27
DCPSUSBYP VCCIO[32]
T29
+3VS_VCC_CLKF33 T38 VCCIO[33] +3V_PCH
VCC3_3[5]
0.1U_0402_10V7K
C236
T24 1
2 R271 1 +VCCDPLL_CPY AL29 VCCSUS3_3[8] +5V_PCH +3V_PCH
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 +1.05VS VCCIO[14]
0_0603_5% V23 +3V_VCCAUBG 2 R273 1
,VCCAPLLSATA VCCSUS3_3[9]
USB
1 0_0603_5%
2
+VCCSUS1 AL24 V24 2
DCPSUS[3] VCCSUS3_3[10]
1
1 C238 D1
P24 0.1U_0402_10V7K R275 CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 +1.05VS 10_0402_5%
1U_0402_6.3V6K AA19
1
2 VCCASW[1] T26 +1.05VS_VCCAUPLL 2 R276 1 +PCH_V5REF_SUS
2
+1.05VS AA21 VCCIO[34]
VCCASW[2]
903mA 0_0603_5% 1
1 R277 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
0_0805_5% VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
C242
AA26
2
C C
1 1 1
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
C246
L5 AC27 2 R278 1 R279 D2
1 2 +1.05VS_VCCA_A_DPL VCCASW[9] N20 +3V_VCCPSUS 0_0603_5% CH751H-40PT_SOD323-2
VCCSUS3_3[2] 1 10_0402_5%
AC29
PCI/GPIO/LPC
BLM18PG181SN1D_0603
2 2 2 VCCASW[10] N22 C247
1
AC31 VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
VCCASW[11] P20 2 +3VS
VCCSUS3_3[4] 1
L6 AD29
1 2 +1.05VS_VCCA_B_DPL VCCASW[12] P22 2 R281 1 C248
BLM18PG181SN1D_0603 AD31 VCCSUS3_3[5] 0_0603_5% 1U_0603_10V6K
VCCASW[13] 1 2
C249
W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]
1
22U_0805_6.3V6M
C250
2 +3VS
1U_0402_6.3V6K
C251
1U_0402_6.3V6K
C253
1 W23 W16
22U_0805_6.3V6M
C252
VCCASW[15] VCC3_3[8]
1 1
W24 T34 +3VS_VCCPPCI 2 R282 1
2 VCCASW[16] VCC3_3[4]
2 1 0_0603_5%
W26
2 2 VCCASW[17] C254
W29 +3VS 0.1U_0402_10V7K
VCCASW[18] 2
W31 AJ2 +VCC3_3_2 2 R283 1
VCCASW[19] VCC3_3[2] 0_0603_5% +1.05VS_SATA3 +1.05VS
Before gerber out change to 22u_0805 1
W33
VCCASW[20] AF13 2 R285 1
VCCIO[5] C255 0_0603_5%
2 0.1U_0402_10V7K 1
+VCCRTCEXT N16
DCPRTC AH13 C257
1 VCCIO[12]
C258 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
VCCVRM[4] VCCIO[13]
2
B AF14 B
2 R274 1 +1.05VS_VCCA_A_DPL BD47 VCCIO[6]
SATA
0_0603_5%
VCCAPLLSATA On-Die PLL Voltage Regulator
1 +1.05VS_VCCA_B_DPL BF47 H
C256 VCCADPLLB 80mA +VCCAFDI_VRM
1U_0402_6.3V6K AF11 +VCCAFDI_VRM VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
+1.05VS_VCCDIFFCLKN +VCCDIFFCLK AF17 VCCVRM[1] +1.05VS_VCC_SATA +1.05VS
2 AF33 VCCIO[7] ,VCCAPLLSATA
AF34 VCCDIFFCLKN[1] AC16 +1.05VS_VCC_SATA 2 R288 1
55mA
VCCDIFFCLKN[2] VCCIO[2]
2 R304 1 +1.05VS_VCCDIFFCLKN AG34 0_0603_5%
+1.05VS VCCDIFFCLKN[3]
0_0603_5% 1 AC17 1
VCCIO[3] C261
C259 +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +1.05VS
DCPSST
1
2 R284 1 C263
+1.05VS
0_0603_5% 1 0.1U_0402_10V7K T17 T21
V19 DCPSUS[1] VCCASW[22]
C262 2 DCPSUS[2]
MISC
0.1U_0402_10V7K
C266
0.1U_0402_10V7K
C267
@ 0_0603_5%
1U_0402_6.3V6K
C268
0.1U_0402_10V7K
C269
0.1U_0402_10V7K
C270
1 1 1 1
PANTHER-POINT_FCBGA989 C271
A 0.1U_0402_16V4Z A
@
2 2 2 2
U4I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
D U4H B15 VSS[163] VSS[263] K7 D
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AA3 VSS[2] VSS[81] AK42 B35 VSS[168] VSS[268] L28
AA33 VSS[3] VSS[82] AK46 B39 VSS[169] VSS[269] L36
AA34 VSS[4] VSS[83] AK8 B7 VSS[170] VSS[270] L48
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AB4 VSS[8] VSS[87] AL2 BB20 VSS[174] VSS[274] M22
AB43 VSS[9] VSS[88] AL21 BB22 VSS[175] VSS[275] M24
AB5 VSS[10] VSS[89] AL23 BB24 VSS[176] VSS[276] M30
AB7 VSS[11] VSS[90] AL26 BB28 VSS[177] VSS[277] M32
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC2 VSS[13] VSS[92] AL31 BB38 VSS[179] VSS[279] M38
AC21 VSS[14] VSS[93] AL33 BB4 VSS[180] VSS[280] M4
AC24 VSS[15] VSS[94] AL34 BB46 VSS[181] VSS[281] M42
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD12 VSS[21] VSS[100] AM43 BC32 VSS[187] VSS[287] P11
AD13 VSS[22] VSS[101] AM45 BC34 VSS[188] VSS[288] P18
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD24 VSS[24] VSS[103] AM7 BC40 VSS[190] VSS[290] P40
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
C AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 C
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD4 VSS[33] VSS[112] AP32 BF12 VSS[199] VSS[299] T4
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD42 VSS[35] VSS[114] AP4 BF20 VSS[201] VSS[301] T46
AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47
AD45 VSS[37] VSS[116] AP46 BF24 VSS[203] VSS[303] T8
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF29 VSS[51] VSS[130] AT42 BH15 VSS[217] VSS[317] W27
AF31 VSS[52] VSS[131] AT46 BH17 VSS[218] VSS[318] W48
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF5 VSS[57] VSS[136] AV20 BH33 VSS[223] VSS[323] Y46
AF7 VSS[58] VSS[137] AV24 BH35 VSS[224] VSS[324] Y8
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
B AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 B
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH42 VSS[69] VSS[148] AW28 D30 VSS[235] VSS[340] BG22
AH46 VSS[70] VSS[149] AW32 D32 VSS[236] VSS[342] BG24
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A
PANTHER-POINT_FCBGA989
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 22 of 65
5 4 3 2 1
5 4 3 2 1
UV1A
PCIE_CTX_GRX_N[0..15] +VDD33MISC
<32,5> PCIE_CTX_GRX_N[0..15] PCIE_CTX_GRX_P7 AN12 +VDD33MISC
Part 1 of 7
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N7 AM12 PEX_RX0 P6 GPU_VID4
<32,5> PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_P6 AN14 PEX_RX0_N GPIO0 M3 GPU_VID3 GPU_VID4 <58>
PEX_RX1 GPIO1 GPU_VID3 <58>
10K_0402_5%
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N6 AM14 L6 VGA_BL_PWM PCH_THRMTRIP#_R
<32,5> PCIE_CRX_GTX_N[0..15] PEX_RX1_N GPIO2 VGA_BL_PWM <34> PCH_THRMTRIP#_R <19,32>
1
PCIE_CTX_GRX_P5 AP14 P5 VGA_ENVDD
PEX_RX2 GPIO3 VGA_ENVDD <34>
RV65
PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_N5 AP15 P7 VGA_ENBKL RV208
<32,5> PCIE_CRX_GTX_P[0..15] PEX_RX2_N GPIO4 VGA_ENBKL <34>
3
PCIE_CTX_GRX_P4 AN15 L7 GPU_VID1 @ 10K_0402_5%
PCIE_CTX_GRX_N4 AM15 PEX_RX3 GPIO5 M7 GPU_VID2 GPU_VID1 <58>
@ QV7B
PCIE_CTX_GRX_P3 AN17 PEX_RX3_N GPIO6 N8 GPU_VID2 <58>
DMN66D0LDW-7 2N_SOT363-6
2
PCIE_CTX_GRX_N3 AM17 PEX_RX4 GPIO7 M1 OVERT# 5
PCIE_CTX_GRX_P2 AP17 PEX_RX4_N GPIO8 M2 GPIO9 @
Under GPU(below 150mils) PEX_RX5 GPIO9
6
D
150mA PCIE_CTX_GRX_N2 AP18 L1 D
4
PCIE_CTX_GRX_P1 AN18 PEX_RX5_N GPIO10 M5 GPU_VID0 MEM_VREF <28,29,30,31> @
LV1 BLM18PG181SN1D_2P QV7A
GPIO
1 2 +SP_PLLVDD PCIE_CTX_GRX_N1 AM18 PEX_RX6 GPIO11 N3 GPU_VID0 <58> VGA_AC_DET
+1.05VS_VGA PEX_RX6_N GPIO12 VGA_AC_DET <32,45,58> DMN66D0LDW-7 2N_SOT363-6
10K_0402_5%
22U_0805_6.3V6M
4.7U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
PCIE_CTX_GRX_P0 AN20 M4 GPU_VID5 OVERT# 2
PEX_RX7 GPIO13 GPU_VID5 <58>
1
CV112
CV113
CV4
CV5
180ohms (ESR=0.2) Bead 1 1 1 1 PCIE_CTX_GRX_N0 AM20 N4 FB_CLAMP_TOGGLE_REQ#
PEX_RX7_N GPIO14
RV223
AP20 P2
1
AP21 PEX_RX8 GPIO15 R8
AN21 PEX_RX8_N GPIO16 M6 DPRSLPVR_VGA <58>
2 2 2 2 AM21 PEX_RX9 GPIO17 R1 DGPU_HDMI_HPD
DGPU_HDMI_HPD <36>
2
AN23 PEX_RX9_N GPIO18 P3
AM23 PEX_RX10 GPIO19 P4
AP23 PEX_RX10_N GPIO20 P1
AP24 PEX_RX11 GPIO21
AN24 PEX_RX11_N
AM24 PEX_RX12
+VDD33MISC AN26 PEX_RX12_N
AM26 PEX_RX13 Vendor recommand reserve PU/PD resistor +VDD33MISC
+VDD33MISC AP26 PEX_RX13_N
AP27 PEX_RX14
PEX_RX14_N
2
2
RV24 RV25 AM27 AL10 VGA_CRT_G
PEX_RX15_N DACA_GREEN AL9 VGA_CRT_B VGA_CRT_G <35>
2.2K_0402_5% 2.2K_0402_5% RV52
DACA_BLUE VGA_CRT_B <35>
DACs
10K_0402_5%
5
1
VGA_SMB_CK2 4 3 PCIE_CRX_GTX_P6 CV21 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P6 AH14 AN9 VGA_CRT_VSYNC
EC_SMB_CK2 <15,32,40,45> PCIE_CRX_GTX_N6 1 2 PCIE_CRX_C_GTX_N6 AG14 PEX_TX1 DACA_VSYNC VGA_CRT_VSYNC <35>
CV23 0.22U_0402_10V6K
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_P5 CV25 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P5 AK15 PEX_TX1_N
PEX_TX2 FB_CLAMP_TOGGLE_REQ# 1 2
1 2 PCIE_CRX_GTX_N5 CV27 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N5 AJ15 AG10 +DACA_VDD GC6_EVENT# <19,32>
PEX_TX2_N DACA_VDD RV170 GC6@ 0_0402_5%
PCI EXPRESS
RV126 @ 0_0402_5% PCIE_CRX_GTX_P4 CV29 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P4 AL16 AP9 +DACA_VREF
PCIE_CRX_GTX_N4 CV31 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N4 AK16 PEX_TX3 DACA_VREF AP8 DACA_RSET
PEX_TX3_N DACA_RSET
0.1U_0402_10V7K
PCIE_CRX_GTX_P3 CV33 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AK17
PEX_TX4
2
CV130
C PCIE_CRX_GTX_N3 CV28 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 AJ17 1
C
QV1A PCIE_CRX_GTX_P2 CV30 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P2 AH17 PEX_TX4_N RV107 +VDD33MISC
VGA_SMB_DA2 1 6 PCIE_CRX_GTX_N2 CV32 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N2 AG17 PEX_TX5 124_0402_1%
GPIO 14 of GPU connect to PCH GPIO 0
EC_SMB_DA2 <15,32,40,45> PCIE_CRX_GTX_P1 1 2 PCIE_CRX_C_GTX_P1 AK18 PEX_TX5_N
CV36 0.22U_0402_10V6K SLI@
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_N1 CV41 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N1 AJ18 PEX_TX6 2 SLI@ GPIO9 1 2
2
1 2 PCIE_CRX_GTX_P0 CV34 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AL19 PEX_TX6_N
PEX_TX7 RV15 2.2K_0402_5%
RV137 @ 0_0402_5% PCIE_CRX_GTX_N0 CV35 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 AK19 R4 VGA_CRT_CLK VGA_EDID_CLK 1 2
PEX_TX7_N I2CA_SCL VGA_CRT_CLK <35>
AK20 R5 VGA_CRT_DATA RV4 2.2K_0402_5%
VGA_CRT_DATA <35>
PU AT EC SIDE, +3VS AND 4.7K AJ20 PEX_TX8
PEX_TX8_N
I2CA_SDA CRT SLI@
VGA_EDID_DATA 1 2
AH20 R7 I2CB_SCL VGA_BL_PWM 2 1 RV7 2.2K_0402_5%
AG20 PEX_TX9 I2CB_SCL R6 I2CB_SDA RV16 10K_0402_5% VGA_CRT_DATA 1 2
AK21 PEX_TX9_N I2CB_SDA RV10 2.2K_0402_5%
I2C
AJ21 PEX_TX10 R2 VGA_EDID_CLK VGA_CRT_CLK 1 2
VGA_EDID_CLK <34>
AL22 PEX_TX10_N
PEX_TX11
I2CC_SCL
I2CC_SDA
R3 VGA_EDID_DATA
VGA_EDID_DATA <34>
LVDS RV11 2.2K_0402_5%
AK22 I2CB_SCL 1 2
+3VS PEX_TX11_N
AK23 T4 VGA_SMB_CK2 RV12 2.2K_0402_5%
AJ23 PEX_TX12 I2CS_SCL T3 VGA_SMB_DA2 I2CB_SDA 1 2
AH23 PEX_TX12_N I2CS_SDA RV13 2.2K_0402_5%
1
AG23 PEX_TX13 Close to GPU OVERT# 1 2
C1061
0.1U_0402_16V4Z AK24 PEX_TX13_N RV1 10K_0402_5%
AJ24 PEX_TX14 VGA_CRT_R 1 SLI@ 2 VGA_AC_DET 1 2
2 AL25 PEX_TX14_N RV106 150_0402_1% RV2 10K_0402_5%
AK25 PEX_TX15 60mA +PLLVDD VGA_CRT_G 1 SLI@ 2
PEX_TX15_N RV108 150_0402_1%
5
CLK
RV111 PEX_CLKREQ_N
NC7SZ08P5X_NL_SC70-5 10K_0402_5%
1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTAL_IN
B Differential signal RV20 200_0402_1% PEX_TSTCLK_OUT# AK26 PEX_TSTCLK_OUT XTAL_IN H2 XTAL_OUT B
PEX_TSTCLK_OUT_N XTAL_OUT
1
1
1 2 PEX_TERMP 10K_0402_5% RV26 LV5
RV22 2.49K_0402_1% RV27 +DACA_VDD
Under GPU Near GPU 2 1
R1495 @ 0_0402_5% +3VS_VGA
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
10K_0402_5% BLM18PG181SN1D_0603
@ CV125
@ CV126
SLI@ CV139
SLI@ CV122
SLI@ CV127
SLI@ CV128
1U_0402_6.3V6K
1 2 1 1 1 1 1 1
2
N13P-GT1-A2_FCBGA908 Internal Thermal Sensor
2 2 2 2 2 2
GT@ CV126
+3VS_VGA
2
RV230 1 2
10K_0402_5% 10K_0402_5%
RV23 10M_0402_5% OPT@
@
RV231
1
2 1 +3VS_VGA
<18,51> DGPU_PWR_EN YV1
4 3 XTAL_OUT +PLLVDD 1 2
NC OSC +1.05VS_VGA
22U_0805_6.3V6M
0.1U_0402_10V7K
10K_0402_5% LV7 0_0402_5%
XTAL_IN 1 2
CV131
2
OSC NC 1 1
CV40
RV32 27MHZ 16PF +-30PPM X3G027000FG1H-HX 1
10K_0402_5% 1
2
G
CV37 CV38 2 2
QV16 15P_0402_50V8J 15P_0402_50V8J
1
1 3 CLK_REQ_GPU# 2 2
<15> CLK_REQ_GPU#_R
D
A A
2
RV233 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-PCIE/DAC/GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 23 of 65
5 4 3 2 1
5 4 3 2 1
UV1D
Part 4 of 7
<34> VGA_TXCLK+ VGA_TXCLK+ AM6
VGA_TXCLK- AN6 IFPA_TXC P8
<34> VGA_TXCLK- IFPA_TXC_N NC
<34> VGA_TXOUT0+ VGA_TXOUT0+ AP3 AC6
VGA_TXOUT0- AN3 IFPA_TXD0 NC AJ28
<34> VGA_TXOUT0- IFPA_TXD0_N NC
<34> VGA_TXOUT1+ VGA_TXOUT1+ AN5 AJ4
VGA_TXOUT1- AM5 IFPA_TXD1 NC AJ5
<34> VGA_TXOUT1- IFPA_TXD1_N NC
<34> VGA_TXOUT2+ VGA_TXOUT2+ AL6 AL11
VGA_TXOUT2- AK6 IFPA_TXD2 NC C15
<34> VGA_TXOUT2- IFPA_TXD2_N NC
NC
AJ6 D19
AH6 IFPA_TXD3 NC D20
D IFPA_TXD3_N NC D23 D
NC D26
AJ9 NC H31
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
for 15" dual channel AM7 IFPB_TXD4_N
AL7 IFPB_TXD5
AN8 IFPB_TXD5_N
AM8 IFPB_TXD6
AK8 IFPB_TXD6_N
AL8 IFPB_TXD7
IFPB_TXD7_N L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <58>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5 VSSSENSE_VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA <58>
AJ2
AH3 IFPC_L1_N
IFPC_L2 trace width: 16mils
AH4
AG5 IFPC_L2_N differential voltage sensing.
IFPC_L3
AG4
IFPC_L3_N differential signal routing.
TEST
AM1 AK11 TESTMODE
AM2 IFPD_L0 TESTMODE
AM3 IFPD_L0_N AM10
IFPD_L1 JTAG_TCK TV2
1
AM4 AM11
IFPD_L1_N JTAG_TDI TV3
AL3 AP12
IFPD_L2 JTAG_TDO TV4 10K_0402_5%
C AL4 AP11 C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
AK5 IFPD_L3 JTAG_TRST_N RV34 10K_0402_5%
2
IFPD_L3_N
LVDS/TMDS
<36> VGA_HDMI_TX2+ VGA_HDMI_TX2+ AD2
VGA_HDMI_TX2- AD3 IFPE_L0
<36> VGA_HDMI_TX2- IFPE_L0_N
VGA_HDMI_TX1+ AD1
<36>
<36>
VGA_HDMI_TX1+
VGA_HDMI_TX1- VGA_HDMI_TX1- AC1 IFPE_L1 SERIAL
VGA_HDMI_TX0+ AC2 IFPE_L1_N H6 ROM_CS#
<36> VGA_HDMI_TX0+ IFPE_L2 ROM_CS_N
<36> VGA_HDMI_TX0- VGA_HDMI_TX0- AC3 H4 ROM_SCLK ROM_SCLK <33>
VGA_HDMI_CLK+ AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI
<36> VGA_HDMI_CLK+ IFPE_L3 ROM_SI ROM_SI <33>
<36> VGA_HDMI_CLK- VGA_HDMI_CLK- AC5 H7 ROM_SO ROM_SO <33>
IFPE_L3_N ROM_SO
AE3
AE4 IFPF_L0
AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N GENERAL RV35 10K_0402_5%
AD5 IFPF_L2 L2 2 1
AG1 IFPF_L2_N BUFRST_N
AF1 IFPF_L3 L3
IFPF_L3_N CEC
J1 1 2
MULTI_STRAP_REF0_GND RV38 40.2K_0402_1%
AG3
AG2 IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_N J2 STRAP0
STRAP0 STRAP0 <33>
J7 STRAP1 STRAP1 <33>
B
AK3 STRAP1 J6 STRAP2 B
+VDD33MISC IFPD_AUX_I2CX_SCL STRAP2 STRAP2 <33>
AK2 J5 STRAP3 STRAP3 <33>
IFPD_AUX_I2CX_SDA_N STRAP3 J3 STRAP4
STRAP4 STRAP4 <33>
SLI@
1 2 VGA_HDMI_CLK VGA_HDMI_CLK AB3
RV113 4.7K_0402_5% HDMI <36> VGA_HDMI_CLK
VGA_HDMI_DATA AB4 IFPE_AUX_I2CY_SCL
<36> VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N K3
SLI@ THERMDP
1 2 VGA_HDMI_DATA K4
RV114 4.7K_0402_5% AF3 THERMDN
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
1
@
0.1U_0402_16V4Z @ @
RV229 RV225
10K_0402_5% 10K_0402_5%
@
UV15 @
2
RV224 0_0402_5%
ROM_CS#1 2 ROM_CS#_R 1 8
ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 ROM_HOLD#
RV226 0_0402_5% 3 DO HOLD# 6 @
A W P# CLK A
@ 4 5 RV228 0_0402_5%
GND DIO ROM_SCLK_R1 2 ROM_SCLK
MX25L1005AMC-12G SOP ROM_SI_R 1 2 ROM_SI
RV227 0_0402_5%
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-LVDS/HDMI/DP/THM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 24 of 65
5 4 3 2 1
5 4 3 2 1
UV1E
Near GPU
+1.5VS_VGA
For GDDR5 setting. Near GPU Part 5 of 7 2000mA +1.05VS_VGA
3.5A
AA27 AG19
FBVDDQ_0 PEX_IOVDD_0
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CV273
CV274
CV275
CV276
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
AA30 AG21
FBVDDQ_1 PEX_IOVDD_1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CV263
CV264
CV265
CV266
CV267
CV268
CV269
CV270
CV271
CV272
CV43
CV44
CV45
CV46
CV47
CV48
CV49
CV50
CV51
CV52
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 1 1 2 2 2 2 1 1 1 1 AB27 AG22 1 1 1 1 1 1 2 2 2 2
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
2 2 2 2 2 2 1 1 1 1 2 2 2 2 AE27 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
B13 FBVDDQ_8 PEX_IOVDDQ_0 AG15
FBVDDQ_9 PEX_IOVDDQ_1 Under GPU(below 150mils) +1.05VS_VGA For N13P-GT
D B16 AG16 D
FBVDDQ_10 PEX_IOVDDQ_2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
Under GPU(below 150mils) B19 AG18
+1.5VS_VGA FBVDDQ_11 PEX_IOVDDQ_3
CV54
CV53
CV56
CV55
E13 AG25 1 1 1 1
E16 FBVDDQ_12 PEX_IOVDDQ_4 AH15
FBVDDQ_13 PEX_IOVDDQ_5 <51> DGPU_PWR_EN#
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
E19 AH18
FBVDDQ_14 PEX_IOVDDQ_6 +3VS_VGA
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+VDD33MISC
CV277
CV281
CV282
CV278
CV279
CV280
CV292
CV287
CV294
CV284
CV285
CV286
1 1 1 1 1 1 1 1 1 1 1 1 H10 AH26
FBVDDQ_15 PEX_IOVDDQ_7
2
H11 AH27 2 2 2 2 QV8 AO3413_SOT23
G
H12 FBVDDQ_16 PEX_IOVDDQ_8 AJ27
H13 FBVDDQ_17 PEX_IOVDDQ_9 AK27 +VDD33MISC 1 3
2 2 2 2 2 2 2 2 2 2 2 2 FBVDDQ_18 PEX_IOVDDQ_10
0.1U_0402_10V7K
0.1U_0402_10V7K
H14 AL27
S
POWER
FBVDDQ_19 PEX_IOVDDQ_11
CV72
CV105
H15 AM28 1 1
H16 FBVDDQ_20 PEX_IOVDDQ_12 AN28 +3VS_VGA
H18 FBVDDQ_21 PEX_IOVDDQ_13
H19 FBVDDQ_22
H20 FBVDDQ_23 2 2
H21 FBVDDQ_24 AH12
FBVDDQ_25 PEX_PLL_HVDD
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
H22
FBVDDQ_26
CV70
CV74
CV73
H23 1 1 1
H24 FBVDDQ_27
H8 FBVDDQ_28 AG12
H9 FBVDDQ_29 PEX_SVDD_3V3
L27 FBVDDQ_30 2 2 2
M27 FBVDDQ_31
N27 FBVDDQ_32 AG26 +PEX_PLLVDD
P27 FBVDDQ_33 PEX_PLLVDD
R27 FBVDDQ_34 +VDD33MISC
FBVDDQ_35 Under GPU(below 150mils)
T27
T30 FBVDDQ_36 J8
T33 FBVDDQ_37 VDD33_0 K8 +3VS_VGA
FBVDDQ_38 VDD33_1 Place near balls Place near GPU
V27 L8 0_0603_5%
W27 FBVDDQ_39 VDD33_2 M8 +VDD33 2 1
FBVDDQ_40 VDD33_3
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
W30
FBVDDQ_41
1U_0402_6.3V6K
CV109
CV111
CV293
CV75
W33 1 1 1 1 RV5
Y27 FBVDDQ_42
FBVDDQ_43 AH8 +IFPAB_PLLVDD
C IFPAB_PLLVDD AJ8 2 1 C
1 2 FB_VDDQ_SENSE IFPAB_RSET 1K_0402_1% RV40 2 2 2 2
<55> VDDQ_SENSE
RV141 0_0402_5% AG8 +IFPAB_IOVDD @
IFPA_IOVDD AG9
1 2 FB_VSS_SENSE F1 IFPB_IOVDD
RV142 0_0402_5% FB_VDDQ_SENSE
AF7 +IFPC_PLLVDD 1 2
+1.5VS_VGA F2 IFPC_PLLVDD AF8 10K_0402_5% RV42 2 1
FB_GND_SENSE IFPC_RSET 1K_0402_1% RV43
AF6 +IFPC_IOVDD 1 2 @
1 2 J27 IFPC_IOVDD 10K_0402_5% RV44
RV6 40.2_0402_1% FB_CAL_PD_VDDQ IFPAB & IFPEF have to use
CALIBRATION PIN GDDR5 AG7 +IFPD_PLLVDD 1 2
1 2 H27 IFPD_PLLVDD AN2 10K_0402_5% RV45 2 1
RV8 40.2_0402_1% FB_CAL_PU_GND IFPD_RSET 1K_0402_1% RV46
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD 1 2 @
1 2 H25 IFPD_IOVDD 10K_0402_5% RV47
RV9 60.4_0402_1% FB_CAL_TERM_GND
FB_CAL_x_PU_GND 40.2Ohm AB8 +IFPEF_PLLVDD
IFPEF_PLVDD AD6 2 1
IFPEF_RSET 1K_0402_1% RV50
FB_CAL_xTERM_GND 60.4Ohm AC7 +IFPE_IOVDD SLI@
IFPE_IOVDD AC8
Place near balls IFPF_IOVDD
LV2 +1.05VS_VGA
120mA 0_0603_5%
+PEX_PLLVDD 2 1
1U_0603_10V6K
4.7U_0805_25V6-K
0.1U_0402_10V7K
N13P-GT1-A2_FCBGA908
CV65
CV3
CV66
1 1 1
2 2 2
B 300ohms @100MHz (ESR=0.25) B
0.1U_0402_10V7K
0.1U_0402_10V7K
BLM18PG181SN1D_0603 2 1 +IFPAB_PLLVDD
1U_0402_6.3V6K
CV149
CV147
CV171
CV173
CV150
4.7U_0603_6.3V6K
SLI@ 1 1 1 1 1 BLM18PG181SN1D_0603
0.1U_0402_10V7K
SLI@
1U_0402_6.3V6K
CV146
CV140
CV141
1 1 1
CV140
CV147 2 2 2 2 2
4.7U_0603_6.3V6K
2 2 2
SLI@ SLI@ SLI@ SLI@
SLI@
SLI@ SLI@
Place near balls 10K_0402_5% SLI@
10K_0402_5% OPT@
OPT@
Place near balls
180ohms @100MHz (ESR=0.2)
220ohms @100MHz (ESR=0.05) P/N: SM010030710
+1.05VS_VGA +3VS_VGA
LV10 570mA LV4
0.1U_0402_10V7K
0.1U_0402_10V7K
2 1 +IFPE_IOVDD 2 1 +IFPAB_IOVDD
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
CV152
CV172
CV153
CV158
CV176
CV216
CV197
SLI@ SLI@ 1 1 1 1
IFPB_IOVDD combined
4.7U_0603_6.3V6K
2 2 2 2
4.7U_0603_6.3V6K
CV172 CV176 2 2 2 2
Security Classification
2011/11/01
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-POWER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 25 of 65
5 4 3 2 1
5 4 3 2 1
UV1F
Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
AA22 GND_3 GND_103 E22
UV1G +VGA_CORE AB12 GND_4 GND_104 E25
+VGA_CORE AB14 GND_5 GND_105 E5
AB16 GND_6 GND_106 E7
Part 7 of 7 V17 AB19 GND_7 GND_107 F28
AA12 VDD_56 V18 AB2 GND_8 GND_108 F7
AA14 VDD_0 VDD_57 V20 AB21 GND_9 GND_109 G10
D
AA16 VDD_1 VDD_58 V22 A33 GND_10 GND_110 G13 D
GND
P23 VDD_34 XVDD_16 AH33 GND_43 GND_143 N28
R13 VDD_35 AH5 GND_44 GND_144 N30
R15 VDD_36 W2 AH7 GND_45 GND_145 N32
R17 VDD_37 XVDD_17 W3 AJ7 GND_46 GND_146 N33
R18 VDD_38 XVDD_18 W4 AK10 GND_47 GND_147 N5
R20 VDD_39 XVDD_19 W5 AK7 GND_48 GND_148 N7
R22 VDD_40 XVDD_20 W7 AL12 GND_49 GND_149 P13
T12 VDD_41 XVDD_21 W8 AL14 GND_50 GND_150 P15
T14 VDD_42 XVDD_22 AL15 GND_51 GND_151 P17
T16 VDD_43 AL17 GND_52 GND_152 P18
T19 VDD_44 Y1 AL18 GND_53 GND_153 P20
T21 VDD_45 XVDD_23 Y2 AL2 GND_54 GND_154 P22
T23 VDD_46 XVDD_24 Y3 AL20 GND_55 GND_155 R12
U13 VDD_47 XVDD_25 Y4 AL21 GND_56 GND_156 R14
U15 VDD_48 XVDD_26 Y5 AL23 GND_57 GND_157 R16
U17 VDD_49 XVDD_27 Y6 AL24 GND_58 GND_158 R19
U18 VDD_50 XVDD_28 Y7 AL26 GND_59 GND_159 R21
U20 VDD_51 XVDD_29 Y8 AL28 GND_60 GND_160 R23
U22 VDD_52 XVDD_30 AL30 GND_61 GND_161 T13
V13 VDD_53 AL32 GND_62 GND_162 T15
V15 VDD_54 AA1 AL33 GND_63 GND_163 T17
VDD_55 XVDD_31 AA2 AL5 GND_64 GND_164 T18
XVDD_32 AA3 AM13 GND_65 GND_165 T2
XVDD_33 AA4 AM16 GND_66 GND_166 T20
XVDD_34 AA5 AM19 GND_67 GND_167 T22
XVDD_35 AA6 AM22 GND_68 GND_168 AG11
B XVDD_36 AA7 AM25 GND_69 GND_169 T28 B
XVDD_37 AA8 AN1 GND_70 GND_170 T32
XVDD_38 AN10 GND_71 GND_171 T5
AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
N13P-GT1-A2_FCBGA908 AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
B25 GND_86 GND_186 W15
B28 GND_87 GND_187 W17
B31 GND_88 GND_188 W18
B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
A C7 GND_98 GND_198 AH11 A
GND_99 GND_199 C16
GND_OPT W32
GND_OPT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-VGA CORE, GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 26 of 65
5 4 3 2 1
5 4 3 2 1
FBC_D[0..63]
FBA_D[0..63] <30,31> FBC_D[0..63]
<28,29> FBA_D[0..63]
1
FBA_D8 J28 V28 FBA_ABI#_L FBC_D7 G12 G15 FBC_MA6_MA11_L DATA Bus
FBA_D8 FBA_CMD8 FBA_ABI#_L <28> FBB_D7 FBB_CMD7 FBC_MA6_MA11_L <30>
1
FBA_D9 H29 V29 FBA_MA12_RFU_L RV209 FBC_D8 G6 F15 FBC_ABI#_L
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_MA0_MA10_L FBA_MA12_RFU_L <28> FBC_D9 F5 FBB_D8 FBB_CMD8 E15 FBC_MA12_RFU_L FBC_ABI#_L <30>
FBA_D10 FBA_CMD10 FBA_MA0_MA10_L <28> 10K_0402_5% FBB_D9 FBB_CMD9 FBC_MA12_RFU_L <30>
RV210 Address 0..31 32..63
FBA_D11 H28 U34 FBA_MA1_MA9_L FBC_D10 E6 D15 FBC_MA0_MA10_L 10K_0402_5%
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_RAS#_L FBA_MA1_MA9_L <28> FBC_D11 F6 FBB_D10 FBB_CMD10 A14 FBC_MA1_MA9_L FBC_MA0_MA10_L <30>
FBx_CMD0 CS#
2
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_RST#_L FBA_RAS#_L <28> FBC_D12 F4 FBB_D11 FBB_CMD11 D14 FBC_RAS#_L FBC_MA1_MA9_L <30>
2
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CKE_L FBA_RST#_L <28> FBC_D13 G4 FBB_D12 FBB_CMD12 A15 FBC_RST#_L FBC_RAS#_L <30>
FBA_D14 FBA_CMD14 FBA_CKE_L <28> FBB_D13 FBB_CMD13 FBC_RST#_L <30> FBx_CMD1 A3_BA3
FBA_D15 F30 Y32 FBA_CAS#_L FBC_D14 E2 B15 FBC_CKE_L
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CS#_H FBA_CAS#_L <28> FBC_D15 F3 FBB_D14 FBB_CMD14 C17 FBC_CAS#_L FBC_CKE_L <30>
FBA_D16 FBA_CMD16 FBA_CS#_H <29> FBB_D15 FBB_CMD15 FBC_CAS#_L <30> FBx_CMD2 A2_BA0
FBA_D17 D32 AA29 FBA_MA3_BA3_H FBC_D16 C2 D18 FBC_CS#_H
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_MA2_BA0_H FBA_MA3_BA3_H <29> FBC_D17 D4 FBB_D16 FBB_CMD16 E18 FBC_MA3_BA3_H FBC_CS#_H <31>
FBA_D18 FBA_CMD18 FBA_MA2_BA0_H <29> FBB_D17 FBB_CMD17 FBC_MA3_BA3_H <31> FBx_CMD3 A4_BA2
FBA_D19 C33 AC34 FBA_MA4_BA2_H FBC_D18 D3 F18 FBC_MA2_BA0_H
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_MA5_BA1_H FBA_MA4_BA2_H <29> FBC_D19 C1 FBB_D18 FBB_CMD18 A20 FBC_MA4_BA2_H FBC_MA2_BA0_H <31>
FBA_D20 FBA_CMD20 FBA_MA5_BA1_H <29>
+1.5VS_VGA FBB_D19 FBB_CMD19 FBC_MA4_BA2_H <31> FBx_CMD4 A5_BA1
FBA_D21 F32 AA32 FBA_WE#_H FBC_D20 B3 B20 FBC_MA5_BA1_H
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_MA7_MA8_H FBA_WE#_H <29> FBC_D21 C4 FBB_D20 FBB_CMD20 C18 FBC_WE#_H FBC_MA5_BA1_H <31>
+1.5VS_VGA
FBA_D22 FBA_CMD22 FBA_MA7_MA8_H <29> FBB_D21 FBB_CMD21 FBC_WE#_H <31> FBx_CMD5 WE#
FBA_D23 H32 Y28 FBA_MA6_MA11_H FBC_D22 B5 B18 FBC_MA7_MA8_H
FBA_D23 FBA_CMD23 FBA_MA6_MA11_H <29> FBB_D22 FBB_CMD22 FBC_MA7_MA8_H <31>
MEMORY INTERFACE
1
FBA_D24 P34 Y29 FBA_ABI#_H FBC_D23 C5 G18 FBC_MA6_MA11_H FBx_CMD6 A7_A8
FBA_D24 FBA_CMD24 FBA_ABI#_H <29> FBB_D23 FBB_CMD23 FBC_MA6_MA11_H <31>
1
FBA_D25 P32 W31 FBA_MA12_RFU_H RV221 FBC_D24 A11 G17 FBC_ABI#_H
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_MA0_MA10_H FBA_MA12_RFU_H <29> FBC_D25 C11 FBB_D24 FBB_CMD24 F17 FBC_MA12_RFU_H FBC_ABI#_H <31>
10K_0402_5% RV222 FBx_CMD7 A6_A11
MEMORY INTERFACE B
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_MA1_MA9_H FBA_MA0_MA10_H <29> FBC_D26 D11 FBB_D25 FBB_CMD25 D16 FBC_MA0_MA10_H FBC_MA12_RFU_H <31>
FBA_D27 FBA_CMD27 FBA_MA1_MA9_H <29> FBB_D26 FBB_CMD26 FBC_MA0_MA10_H <31> 10K_0402_5%
FBA_D28 L31 Y31 FBA_RAS#_H FBC_D27 B11 A18 FBC_MA1_MA9_H FBx_CMD8 ABI#
2
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_RST#_H FBA_RAS#_H <29> FBC_D28 D8 FBB_D27 FBB_CMD27 D17 FBC_RAS#_H FBC_MA1_MA9_H <31>
2
FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CKE_H FBA_RST#_H <29> FBC_D29 A8 FBB_D28 FBB_CMD28 A17 FBC_RST#_H FBC_RAS#_H <31>
FBA_D30 FBA_CMD30 FBA_CKE_H <29> FBB_D29 FBB_CMD29 FBC_RST#_H <31> FBx_CMD9 A12_RFU
FBA_D31 L33 V31 FBA_CAS#_H FBC_D30 C8 B17 FBC_CKE_H
FBA_D32 AG28 FBA_D31 FBA_CMD31 FBA_CAS#_H <29> FBC_D31 B8 FBB_D30 FBB_CMD30 E17 FBC_CAS#_H FBC_CKE_H <31>
FBA_D32 FBB_D31 FBB_CMD31 FBC_CAS#_H <31> FBx_CMD10 A0_A10
FBA_D33 AF29 FBC_D32 F24
FBA_D34 AG29 FBA_D33 FBC_D33 G23 FBB_D32
FBA_D34 FBB_D33 FBx_CMD11 A1_A9
FBA_D35 AF28 R32 FBC_D34 E24
C FBA_D36 AD30 FBA_D35 FBA_CMD_RFU0 AC32 FBC_D35 G24 FBB_D34 C12 C
FBA_D36 FBA_CMD_RFU1 FBB_D35 FBB_CMD_RFU0 FBx_CMD12 RAS#
FBA_D37 AD29 FBC_D36 D21 C20
FBA_D38 AC29 FBA_D37 FBC_D37 E21 FBB_D36 FBB_CMD_RFU1
FBA_D38 FBB_D37 FBx_CMD13 RST#
FBA_D39 AD28 @ FBC_D38 G21
FBA_D39 FBB_D38
A
FBA_D40 AJ29 R28 60.4_0402_1%
1 2RV58 FBC_D39 F21 @ FBx_CMD14 CKE#
FBA_D40 FBA_DEBUG0 +1.5VS_VGA FBB_D39
FBA_D41 AK29 AC28 60.4_0402_1%
1 2RV59 FBC_D40 G27 G14 60.4_0402_1%
1 2RV60
FBA_D41 FBA_DEBUG1 FBB_D40 FBB_DEBUG0 +1.5VS_VGA
FBA_D42 AJ30 FBC_D41 D27 G20 60.4_0402_1%
1 2RV61 FBx_CMD15 CAS#
FBA_D43 AK28 FBA_D42 FBC_D42 G26 FBB_D41 FBB_DEBUG1
FBA_D43 @ FBB_D42
FBA_D44 AM29 FBC_D43 E27 @ FBx_CMD16 CS#
FBA_D45 AM31 FBA_D44 R30 FBA_CLK0 FBC_D44 E29 FBB_D43
FBA_D46 AN29 FBA_D45 FBA_CLK0 R31 FBA_CLK0# FBA_CLK0 <28> FBC_D45 F29 FBB_D44 D12 FBC_CLK0
FBA_D46 FBA_CLK0_N FBA_CLK0# <28> FBB_D45 FBB_CLK0 FBC_CLK0 <30> FBx_CMD17 A3_BA3
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D46 E30 E12 FBC_CLK0#
FBA_D48 AN31 FBA_D47 FBA_CLK1 AC31 FBA_CLK1# FBA_CLK1 <29> FBC_D47 D30 FBB_D46 FBB_CLK0_N E20 FBC_CLK1 FBC_CLK0# <30>
FBA_D48 FBA_CLK1_N FBA_CLK1# <29> FBB_D47 FBB_CLK1 FBC_CLK1 <31> FBx_CMD18 A2_BA0
FBA_D49 AN32 FBC_D48 A32 F20 FBC_CLK1#
FBA_D50 AP30 FBA_D49 FBC_D49 C31 FBB_D48 FBB_CLK1_N FBC_CLK1# <31>
FBA_D50 FBB_D49 FBx_CMD19 A4_BA2
FBA_D51 AP32 FBC_D50 C32
FBA_D52 AM33 FBA_D51 K31 FBA_WCK0 FBC_D51 B32 FBB_D50
FBA_D52 FBA_WCK01 FBA_WCK0 <28> FBB_D51 FBx_CMD20 A5_BA1
FBA_D53 AL31 L30 FBA_WCK0_N FBC_D52 D29 F8 FBC_WCK0
FBA_D54 AK33 FBA_D53 FBA_WCK01_N H34 FBA_WCK1 FBA_WCK0_N <28> FBC_D53 A29 FBB_D52 FBB_WCK01 E8 FBC_WCK0_N FBC_WCK0 <30>
FBA_D54 FBA_WCK23 FBA_WCK1 <28> FBB_D53 FBB_WCK01_N FBC_WCK0_N <30> FBx_CMD21 WE#
FBA_D55 AK32 J34 FBA_WCK1_N FBC_D54 C29 A5 FBC_WCK1
FBA_D56 AD34 FBA_D55 FBA_WCK23_N AG30 FBA_WCK2 FBA_WCK1_N <28> FBC_D55 B29 FBB_D54 FBB_WCK23 A6 FBC_WCK1_N FBC_WCK1 <30>
FBA_D56 FBA_WCK45 FBA_WCK2 <29> FBB_D55 FBB_WCK23_N FBC_WCK1_N <30> FBx_CMD22 A7_A8
FBA_D57 AD32 AG31 FBA_WCK2_N FBC_D56 B21 D24 FBC_WCK2
FBA_D58 AC30 FBA_D57 FBA_WCK45_N AJ34 FBA_WCK3 FBA_WCK2_N <29> FBC_D57 C23 FBB_D56 FBB_WCK45 D25 FBC_WCK2_N FBC_WCK2 <31>
FBA_D58 FBA_WCK67 FBA_WCK3 <29> FBB_D57 FBB_WCK45_N FBC_WCK2_N <31> FBx_CMD23 A6_A11
FBA_D59 AD33 AK34 FBA_WCK3_N FBC_D58 A21 B27 FBC_WCK3
FBA_D60 AF31 FBA_D59 FBA_WCK67_N FBA_WCK3_N <29> FBC_D59 C21 FBB_D58 FBB_WCK67 C27 FBC_WCK3_N FBC_WCK3 <31>
FBA_D60 FBB_D59 FBB_WCK67_N FBC_WCK3_N <31> FBx_CMD24 ABI#
FBA_D61 AG34 FBC_D60 B24
FBA_D62 AG32 FBA_D61 FBC_D61 C24 FBB_D60
FBA_D62 FBB_D61 FBx_CMD25 A12_RFU
FBA_D63 AG33 J30 FBC_D62 B26
FBA_D63 FBA_WCKB01 J31 FBC_D63 C26 FBB_D62 D6
FBA_WCKB01_N FBB_D63 FBB_WCKB01 FBx_CMD26 A0_A10
FBA_DBI0# P30 J32 D7
<28> FBA_DBI0# FBA_DBI1# F31 FBA_DQM0 FBA_WCKB23 J33 FBC_DBI0# E11 FBB_WCKB01_N C6
<28> FBA_DBI1# FBA_DQM1 FBA_WCKB23_N GC6 support on 15" <30> FBC_DBI0# FBB_DQM0 FBB_WCKB23 FBx_CMD27 A1_A9
FBA_DBI2# F34 AH31 FBC_DBI1# E3 B6
B <28> FBA_DBI2# FBA_DBI3# M32 FBA_DQM2 FBA_WCKB45 AJ31 <30> FBC_DBI1# FBC_DBI2# A3 FBB_DQM1 FBB_WCKB23_N F26 B
<28> FBA_DBI3# FBA_DQM3 FBA_WCKB45_N FB_CLAMP <30> FBC_DBI2# FBB_DQM2 FBB_WCKB45 FBx_CMD28 RAS#
FBA_DBI4# AD31 AJ32 FBC_DBI3# C9 E26
<29> FBA_DBI4# FBA_DBI5# AL29 FBA_DQM4 FBA_WCKB67 AJ33 <30> FBC_DBI3# FBC_DBI4# F23 FBB_DQM3 FBB_WCKB45_N A26
<29> FBA_DBI5# FBA_DQM5 FBA_WCKB67_N <31> FBC_DBI4# FBB_DQM4 FBB_WCKB67 FBx_CMD29 RST#
FBA_DBI6# AM32 FBC_DBI5# F27 A27
<29> FBA_DBI6# FBA_DBI7# AF34 FBA_DQM6 <31> FBC_DBI5# FBC_DBI6# C30 FBB_DQM5 FBB_WCKB67_N
<29> FBA_DBI7# FBA_DQM7 <31> FBC_DBI6# FBB_DQM6 FBx_CMD30 CKE#
RV66 NOGC6@ 10K_0402_5% FBC_DBI7# A24
FBA_EDC0 M31 E1 2 1 <31> FBC_DBI7# FBB_DQM7
FBA_DQS_WP0 FB_CLAMP FBx_CMD31 CAS#
FBA_EDC1 G31 FBC_EDC0 D10
<28> FBA_EDC[3..0] FBA_DQS_WP1 +FB_PLLAVDD FBB_DQS_WP0
FBA_EDC2 E33 FBC_EDC1 D5
FBA_EDC3 M33 FBA_DQS_WP2 CV106 0.1U_0402_10V7K FBC_EDC2 C3 FBB_DQS_WP1
<29> FBA_EDC[7..4] FBA_EDC4 AE31 FBA_DQS_WP3 K27 1 2 FBC_EDC3 B9 FBB_DQS_WP2
FBA_EDC5 AK30 FBA_DQS_WP4 FB_DLL_AVDD FBC_EDC4 E23 FBB_DQS_WP3 H17
FBA_DQS_WP5 FBB_DQS_WP4 FBB_PLL_AVDD +FB_PLLAVDD
0.1U_0402_10V7K
FBA_EDC6 AN33 Place close to ball FBC_EDC5 E28
FBA_DQS_WP6 FBB_DQS_WP5
CV108
FBA_EDC7 AF33 FBC_EDC6 B30 1
FBA_DQS_WP7 U27 FBC_EDC7 A23 FBB_DQS_WP6
FBA_PLL_AVDD +FB_PLLAVDD FBB_DQS_WP7
22U_0805_6.3V6M
0.1U_0402_10V7K
M30
FBA_DQS_RN0
CV107
CV110
1U_0402_6.3V6K
H30 1 1 1 D9
FBA_DQS_RN1 <30> FBC_EDC[3..0] FBB_DQS_RN0 2
CV39
E34 E4
M34 FBA_DQS_RN2 H26 B2 FBB_DQS_RN1
AF30 FBA_DQS_RN3 FB_VREF <31> FBC_EDC[7..4] A9 FBB_DQS_RN2
AK31 FBA_DQS_RN4 2 2 2 D22 FBB_DQS_RN3
AM34 FBA_DQS_RN5 D28 FBB_DQS_RN4
FBA_DQS_RN6 FBB_DQS_RN5
Place close to ball
AF32 A30
FBA_DQS_RN7 B23 FBB_DQS_RN6 FBC_RST#_L
FBB_DQS_RN7
Place close to ball Place close to BGA FBC_RST#_H
+3VS
1
1
D @ N13P-GT1-A2_FCBGA908
2 QV4 N13P-GT1-A2_FCBGA908 RV74 RV73
<18> DGPU_GC6_EN FBA_RST#_L 10K_0402_5% 10K_0402_5%
RV169 G 2N7002_SOT23
FBA_RST#_H
GC6@ 1 2 S
3
GC6_EN <32>
DV3
2
A A
GC6@ 0_0402_5% DAN202UT106_SC70-3
1
FB_CLAMP 1 2 GC6_EN 2
1K_0402_1% RV18 1 RV71 RV72
2 1 3 FBVDDQ_PWR_EN <55> 10K_0402_5% 10K_0402_5%
10K_0402_5% RV68
1
GC6@ GC6@
2
RV29
<19,32,55,58> DGPU_PWROK
1 2
200K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
RV156 0_0402_5% GC6@ Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
2
NOGC6@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-MEM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 27 of 65
5 4 3 2 1
5 4 3 2 1
A4 FBA_D0 A4 FBA_D24
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1 FBA_EDC3 C2 DQ24 DQ0 A2 FBA_D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D26
R13 EDC1 EDC2 DQ26 DQ2 B2 R13 EDC1 EDC2 DQ26 DQ2 B2
<27> FBA_D[0..31]
FBA_EDC2
EDC2 EDC1 DQ27 DQ3
FBA_D3 BYTE0 FBA_EDC1
EDC2 EDC1 DQ27 DQ3
FBA_D27
R2 E4 FBA_D4 R2 E4 FBA_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5 EDC3 EDC0 DQ28 DQ4 E2 FBA_D29
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D30
<27> FBA_EDC[3..0] DQ30 DQ6 DQ30 DQ6
FBA_DBI0# D2 F2 FBA_D7 FBA_DBI3# D2 F2 FBA_D31
<27> FBA_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBA_DBI3# DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
FBA_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBA_DBI2# DBI2# DBI1# DQ17 DQ9 <27> FBA_DBI1# DBI2# DBI1# DQ17 DQ9
D
P2 B11 P2 B11 D
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_CLK0 J12 DQ19 DQ11 E11
<27> FBA_CLK0 CK DQ20 DQ12 CK DQ20 DQ12
FBA_CLK0# J11 E13 FBA_CLK0# J11 E13
<27> FBA_CLK0# CK# DQ21 DQ13 CK# DQ21 DQ13
FBA_CKE_L J3 F11 FBA_CKE_L J3 F11
<27> FBA_CKE_L CKE# DQ22
DQ23
DQ14
DQ15
F13 CKE# DQ22
DQ23
DQ14
DQ15
F13 GDDR5
U11 FBA_D16 U11 FBA_D8
<27> FBA_MA2_BA0_L
FBA_MA2_BA0_L H11
K10 BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13
T11
FBA_D17 FBA_MA4_BA2_L H11
K10 BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13
T11
FBA_D9 Mode H - Mirror Mode Mapping
FBA_MA5_BA1_L FBA_D18 FBA_MA3_BA3_L FBA_D10
<27> FBA_MA5_BA1_L BA1/A5 BA3/A3 DQ10 DQ18 BA1/A5 BA3/A3 DQ10 DQ18
FBA_MA4_BA2_L K11 T13 FBA_D19 FBA_MA2_BA0_L K11 T13 FBA_D11 BYTE1
<27> FBA_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 BA2/A4 BA0/A2 DQ11 DQ19
FBA_MA3_BA3_L H10 N11 FBA_D20 BYTE2 FBA_MA5_BA1_L H10 N11 FBA_D12 DATA Bus
<27> FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 BA3/A3 BA1/A5 DQ12 DQ20
N13 FBA_D21 N13 FBA_D13
DQ13 DQ21 M11 DQ13 DQ21 M11 Address
DQ14 DQ22
FBA_D22
DQ14 DQ22
FBA_D14 0..31 32..63
FBA_MA7_MA8_L K4 M13 FBA_D23 FBA_MA0_MA10_L K4 M13 FBA_D15
<27> FBA_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23
FBA_MA1_MA9_L H5 U4 FBA_MA6_MA11_L H5 U4 FBx_CMD0 CS#
<27> FBA_MA1_MA9_L A9/A1 A11/A6 DQ0 DQ24 A9/A1 A11/A6 DQ0 DQ24
FBA_MA0_MA10_L H4 U2 FBA_MA7_MA8_L H4 U2
<27> FBA_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25
FBA_MA6_MA11_L K5 T4 FBA_MA1_MA9_L K5 T4 FBx_CMD1 A3_BA3
<27> FBA_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 A11/A6 A9/A1 DQ2 DQ26
FBA_MA12_RFU_L J5 T2 FBA_MA12_RFU_L J5 T2
<27> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
N4 N4 FBx_CMD2 A2_BA0
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
U5 VPP/NC DQ5 DQ29 M4 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30
FBx_CMD3 A4_BA2
2 RV115 1 M2 2 RV116 1 M2
DQ7 DQ31 DQ7 DQ31
1K_0402_1%
+1.5VS_VGA
1K_0402_1%
+1.5VS_VGA
FBx_CMD4 A5_BA1
J1 J1
2 RV117 1 J10 MF 2 RV118 1 J10 MF
SEN SEN FBx_CMD5 WE#
2 RV119 1 1K_0402_1% J13 B1 2 RV120 1 1K_0402_1% J13 B1
ZQ VDDQ D1 ZQ VDDQ D1
121_0402_1%
VDDQ
121_0402_1%
VDDQ
FBx_CMD6 A7_A8
F1 F1
J4 VDDQ M1 J4 VDDQ M1
Follow DG <27> FBA_ABI#_L
FBA_ABI#_L
ABI# VDDQ
FBA_ABI#_L
ABI# VDDQ
FBx_CMD7 A6_A11
FBA_RAS#_L G3 P1 FBA_CAS#_L G3 P1
<27> FBA_RAS#_L RAS# CAS# VDDQ RAS# CAS# VDDQ
FBA_CS#_L G12 T1 FBA_WE#_L G12 T1 FBx_CMD8 ABI#
<27> FBA_CS#_L CS# WE# VDDQ CS# WE# VDDQ
FBA_CLK0 1 2 FBA_CAS#_L L3 G2 FBA_RAS#_L L3 G2
<27> FBA_CAS#_L CAS# RAS# VDDQ CAS# RAS# VDDQ
RV21 40.2_0402_1% FBA_WE#_L L12 L2 FBA_CS#_L L12 L2 FBx_CMD9 A12_RFU
<27> FBA_WE#_L WE# CS# VDDQ WE# CS# VDDQ
B3 B3
2
VDDQ D3 VDDQ D3
VDDQ VDDQ FBx_CMD10 A0_A10
RV123 F3 F3
D5 VDDQ H3 D5 VDDQ H3
160_0402_1% <27> FBA_WCK0_N
FBA_WCK0_N
WCK01# WCK23# VDDQ
FBA_WCK1_N
WCK01# WCK23# VDDQ
FBx_CMD11 A1_A9
C @ FBA_WCK0 D4 K3 FBA_WCK1 D4 K3 C
<27> FBA_WCK0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ
M3 M3 FBx_CMD12 RAS#
1
+FBA_VREFD_L +FBA_VREFD_L
0.01U_0402_25V7K
VSS VSS
1
L10 A1 L10 A1
CV42
D11 R4 D11 R4
RV129 G11 VDD VSSQ F5 G11 VDD VSSQ F5
549_0402_1% L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
RV213 VDD VSSQ VDD VSSQ
G14 M10 G14 M10
2
VSSQ VSSQ
1
A12 A12
CV58
1 VSSQ VSSQ
RV130 C12 C12
VSSQ VSSQ
1
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV68
CV69
CV77
CV78
CV71
CV76
CV79
CV80
CV166
CV129
CV132
CV133
CV174
CV134
CV135
CV136
2 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-VRAM A Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 28 of 65
5 4 3 2 1
5 4 3 2 1
K4
DQ13
DQ14
DQ21
DQ22
M11
M13
FBA_D54 FBA_MA0_MA10_H K4
H5 A8/A7 A10/A0
DQ14
DQ15
DQ22
DQ23
M13
U4
FBA_D47 Mode H - Mirror Mode Mapping
FBA_MA7_MA8_H FBA_D55 FBA_MA6_MA11_H
<27> FBA_MA7_MA8_H A8/A7 A10/A0 DQ15 DQ23 A9/A1 A11/A6 DQ0 DQ24
FBA_MA1_MA9_H H5 U4 FBA_MA7_MA8_H H4 U2
<27> FBA_MA1_MA9_H A9/A1 A11/A6 DQ0 DQ24 A10/A0 A8/A7 DQ1 DQ25
FBA_MA0_MA10_H H4 U2 FBA_MA1_MA9_H K5 T4 DATA Bus
<27> FBA_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25 A11/A6 A9/A1 DQ2 DQ26
FBA_MA6_MA11_H K5 T4 FBA_MA12_RFU_H J5 T2
<27> FBA_MA6_MA11_H A11/A6 A9/A1 DQ2 DQ26 A12/RFU/NC DQ3 DQ27
FBA_MA12_RFU_H J5 T2 N4 Address 0..31 32..63
<27> FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27 DQ4 DQ28
N4 A5 N2
A5 DQ4 DQ28 N2 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ5 DQ29 VPP/NC DQ6 DQ30
FBx_CMD0 CS#
U5 M4 2 RV132 1 M2
2 RV131 1 VPP/NC DQ6 DQ30 M2 DQ7 DQ31
DQ7 DQ31
1K_0402_1%
+1.5VS_VGA
FBx_CMD1 A3_BA3
1K_0402_1% J1
J1 +1.5VS_VGA 2 RV134 1 J10 MF
MF SEN FBx_CMD2 A2_BA0
2 RV133 1 J10 2 RV136 1 1K_0402_1% J13 B1
2 RV135 1 J13 SEN B1 ZQ VDDQ D1
1K_0402_1%
ZQ VDDQ
121_0402_1%
VDDQ
FBx_CMD3 A4_BA2
121_0402_1% D1 F1
VDDQ F1 J4 VDDQ M1
Follow DG VDDQ
FBA_ABI#_H
ABI# VDDQ
FBx_CMD4 A5_BA1
FBA_ABI#_H J4 M1 FBA_CAS#_H G3 P1
<27> FBA_ABI#_H ABI# VDDQ RAS# CAS# VDDQ
FBA_RAS#_H G3 P1 FBA_WE#_H G12 T1 FBx_CMD5 WE#
<27> FBA_RAS#_H RAS# CAS# VDDQ CS# WE# VDDQ
FBA_CS#_H G12 T1 FBA_RAS#_H L3 G2
<27> FBA_CS#_H CS# WE# VDDQ CAS# RAS# VDDQ
FBA_CLK1 1 2 FBA_CAS#_H L3 G2 FBA_CS#_H L12 L2 FBx_CMD6 A7_A8
<27> FBA_CAS#_H CAS# RAS# VDDQ WE# CS# VDDQ
RV31 40.2_0402_1% FBA_WE#_H L12 L2 B3
<27> FBA_WE#_H WE# CS# VDDQ VDDQ
B3 D3 FBx_CMD7 A6_A11
VDDQ VDDQ
2
D3 F3
VDDQ F3 D5 VDDQ H3
RV139
VDDQ
FBA_WCK3_N
WCK01# WCK23# VDDQ
FBx_CMD8 ABI#
C 160_0402_1% FBA_WCK2_N D5 H3 FBA_WCK3 D4 K3 C
<27> FBA_WCK2_N WCK01# WCK23# VDDQ WCK01 WCK23 VDDQ
@ FBA_WCK2 D4 K3 M3 FBx_CMD9 A12_RFU
<27> FBA_WCK2 WCK01 WCK23 VDDQ VDDQ
M3 FBA_WCK2_N P5 P3
1
T10 E1 H14 N1
CV59
1 VSSQ VSSQ
RV146 R12 170-BALL U12
VSSQ VSSQ
1
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV84
CV81
CV82
CV83
CV179
CV138
CV142
CV137
2 1 1 1 1 1 1 1
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV187
CV87
CV88
CV85
CV86
CV145
CV143
CV144
2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2
A A
1 2 2 2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-VRAM A Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 29 of 65
5 4 3 2 1
5 4 3 2 1
A4 FBC_D0 A4 FBC_D24
FBC_EDC0 C2 DQ24 DQ0 A2 FBC_D1 FBC_EDC3 C2 DQ24 DQ0 A2 FBC_D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D26
FBC_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D3 FBC_EDC1 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D27
<27> FBC_D[0..31] R2 EDC2 EDC1 DQ27 DQ3 E4
BYTE0 R2 EDC2 EDC1 DQ27 DQ3 E4
FBC_D4 FBC_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 E2 FBC_D5 EDC3 EDC0 DQ28 DQ4 E2 FBC_D29
DQ29 DQ5 F4 FBC_D6 DQ29 DQ5 F4 FBC_D30
<27> FBC_EDC[3..0] FBC_DBI0# D2 DQ30 DQ6 F2 FBC_D7 FBC_DBI3# D2 DQ30 DQ6 F2 FBC_D31
D <27> FBC_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBC_DBI3# DBI0# DBI3# DQ31 DQ7 D
D13 A11 D13 A11
FBC_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBC_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBC_DBI2# P2 DBI2# DBI1# DQ17 DQ9 B11 <27> FBC_DBI1# P2 DBI2# DBI1# DQ17 DQ9 B11
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBC_CLK0 J12 DQ19 DQ11 E11 FBC_CLK0 J12 DQ19 DQ11 E11
<27> FBC_CLK0 FBC_CLK0# J11 CK DQ20 DQ12 E13 FBC_CLK0# J11 CK DQ20 DQ12 E13
<27>
<27>
FBC_CLK0#
FBC_CKE_L
FBC_CKE_L J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 FBC_CKE_L J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 GDDR5
F13 F13
FBC_MA2_BA0_L H11
DQ23
DQ8
DQ15
DQ16
U11
U13
FBC_D16
FBC_D17 FBC_MA4_BA2_L H11
DQ23
DQ8
DQ15
DQ16
U11
U13
FBC_D8
FBC_D9
Mode H - Mirror Mode Mapping
<27> FBC_MA2_BA0_L FBC_MA5_BA1_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D18 FBC_MA3_BA3_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D10
<27> FBC_MA5_BA1_L FBC_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D19 FBC_MA2_BA0_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D11
<27> FBC_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 BA2/A4 BA0/A2 DQ11 DQ19 BYTE1 DATA Bus
FBC_MA3_BA3_L H10 N11 FBC_D20 BYTE2 FBC_MA5_BA1_L H10 N11 FBC_D12
<27> FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D21 BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D13
DQ13 DQ21 DQ13 DQ21
Address 0..31 32..63
M11 FBC_D22 M11 FBC_D14
FBC_MA7_MA8_L K4 DQ14 DQ22 M13 FBC_D23 FBC_MA0_MA10_L K4 DQ14 DQ22 M13 FBC_D15
<27> FBC_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23 FBx_CMD0 CS#
FBC_MA1_MA9_L H5 U4 FBC_MA6_MA11_L H5 U4
<27> FBC_MA1_MA9_L FBC_MA0_MA10_L H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_MA7_MA8_L H4 A9/A1 A11/A6 DQ0 DQ24 U2
<27> FBC_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25 FBx_CMD1 A3_BA3
FBC_MA6_MA11_L K5 T4 FBC_MA1_MA9_L K5 T4
<27> FBC_MA6_MA11_L FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2
<27> FBC_MA12_RFU_L A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27 FBx_CMD2 A2_BA0
N4 N4
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
VPP/NC DQ5 DQ29 +1.5VS_VGA VPP/NC DQ5 DQ29 FBx_CMD3 A4_BA2
U5 M4 U5 M4
2 RV147 1 VPP/NC DQ6 DQ30 M2 2 RV148 1 VPP/NC DQ6 DQ30 M2
DQ7 DQ31 DQ7 DQ31 FBx_CMD4 A5_BA1
1K_0402_1% 1K_0402_1%
J1 +1.5VS_VGA J1 +1.5VS_VGA FBx_CMD5 WE#
2 RV149 1 J10 MF 2 RV150 1 J10 MF
2 RV151 1 J13 SEN B1 2 RV152 1 J13 SEN B1
1K_0402_1%
ZQ VDDQ
1K_0402_1%
ZQ VDDQ FBx_CMD6 A7_A8
121_0402_1% D1 121_0402_1% D1
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD7 A6_A11
Follow DG FBC_ABI#_L J4 M1 FBC_ABI#_L J4 M1
<27> FBC_ABI#_L FBC_RAS#_L G3 ABI# VDDQ P1 FBC_CAS#_L G3 ABI# VDDQ P1
<27> FBC_RAS#_L RAS# CAS# VDDQ RAS# CAS# VDDQ FBx_CMD8 ABI#
FBC_CS#_L G12 T1 FBC_WE#_L G12 T1
FBC_CLK0 1 2 <27> FBC_CS#_L FBC_CAS#_L L3 CS# WE# VDDQ G2 FBC_RAS#_L L3 CS# WE# VDDQ G2
<27> FBC_CAS#_L CAS# RAS# VDDQ CAS# RAS# VDDQ FBx_CMD9 A12_RFU
RV37 40.2_0402_1% FBC_WE#_L L12 L2 FBC_CS#_L L12 L2
<27> FBC_WE#_L WE# CS# VDDQ B3 WE# CS# VDDQ B3
VDDQ VDDQ FBx_CMD10 A0_A10
2
C
D3 D3 C
VDDQ F3 VDDQ F3
RV155
VDDQ VDDQ FBx_CMD11 A1_A9
160_0402_1% FBC_WCK0_N D5 H3 FBC_WCK1_N D5 H3
<27> FBC_WCK0_N FBC_WCK0 D4 WCK01# WCK23# VDDQ K3 FBC_WCK1 D4 WCK01# WCK23# VDDQ K3
@
<27> FBC_WCK0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ FBx_CMD12 RAS#
M3 M3
1
B5 D14 B5 D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
RV159
VSS VDDQ VSS VDDQ FBx_CMD22 A7_A8
549_0402_1% L5 M14 L5 M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
RV216 VSS VDDQ VSS VDDQ FBx_CMD23 A6_A11
B10 T14 B10 T14
2
CV61
G11 F5 G11 F5
RV161 L11 VDD VSSQ M5 L11 VDD VSSQ M5
549_0402_1% P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
RV217 L14 VDD VSSQ C11 L14 VDD VSSQ C11
2
CV62
1 C12 C12
RV162 VSSQ E12 VSSQ E12
1.33K_0402_1% VSSQ N12 VSSQ N12
VSSQ R12 VSSQ R12
VSSQ VSSQ
1
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.5VS_VGA UV7 SIDE
CV207
CV95
CV96
CV93
CV94
CV163
CV161
CV162
H5GQ1H24AFR-T2L_BGA170 2 1 1 1 1 1 1 1 H5GQ1H24AFR-T2L_BGA170
10U_0603_6.3V6M
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV199
CV91
CV92
CV89
CV90
CV160
CV157
CV159
2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2
A A
1 2 2 2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-VRAM C Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 30 of 65
5 4 3 2 1
5 4 3 2 1
D3 FBC_CS#_H L12 L2
VDDQ F3 WE# CS# VDDQ B3
C RV171
VDDQ VDDQ FBx_CMD13 RST# C
160_0402_1% FBC_WCK2_N D5 H3 D3
<27> FBC_WCK2_N FBC_WCK2 D4 WCK01# WCK23# VDDQ K3 VDDQ F3
@
<27> FBC_WCK2 WCK01 WCK23 VDDQ VDDQ FBx_CMD14 CKE#
M3 FBC_WCK3_N D5 H3
1
B5 D14 H1 L13
G5 VSS VDDQ F14 K1 VSS VDDQ B14
RV175
VSS VDDQ VSS VDDQ FBx_CMD24 ABI#
549_0402_1% L5 M14 B5 D14
T5 VSS VDDQ P14 G5 VSS VDDQ F14
RV218 VSS VDDQ VSS VDDQ FBx_CMD25 A12_RFU
B10 T14 L5 M14
2
CV63
D11 R4 C10 U3
RV177 G11 VDD VSSQ F5 R10 VDD VSSQ C4
549_0402_1% L11 VDD VSSQ M5 D11 VDD VSSQ R4
P11 VDD VSSQ F10 G11 VDD VSSQ F5
RV219 G14 VDD VSSQ M10 L11 VDD VSSQ M5
2
CV64
D 2 R12 E12
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
H5GQ1H24AFR-T2L_BGA170 X76@
CV227
CV103
CV104
CV101
CV102
CV170
CV168
CV169
2 1 1 1 1 1 1 1
10U_0603_6.3V6M
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
H5GQ1H24AFR-T2L_BGA170
CV245
CV99
CV100
CV97
CV98
CV167
CV164
CV165
2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2
1 2 2 2 2 2 2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-VRAM C Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 31 of 65
5 4 3 2 1
5 4 3 2 1
B+
follow MXM 3.0 spec
D JSLI1 D
1 2
3 GND GND 4
5 NC GND 6
7 NC GND 8
9 NC GND 10
11 NC +19V 12
13 NC +19V 14
15 NC +19V 16
17 NC +19V 18
PCIE_CTX_GRX_N15 19 GND +19V 20
PCIE_CTX_GRX_P15 21 PEG_RX_N7 +19V 22
23 PEG_RX_P7 +19V 24
PCIE_CTX_GRX_N14 25 GND +19V 26
PCIE_CTX_GRX_P14 27 PEG_RX_N6 GND 28
29 PEG_RX_P6 GND 30
GND GND +5VS
31 32
PCIE_CTX_GRX_N13 33 GND GND 34
PCIE_CTX_GRX_P13 35 PEG_RX_N5 GND 36
37 PEG_RX_P5 GND 38
PCIE_CTX_GRX_N12 39 GND +5V 40
PCIE_CTX_GRX_P12 41 PEG_RX_N4 +5V 42
43 PEG_RX_P4 +5V 44
PCIE_CTX_GRX_N11 45 GND +5V 46
PCIE_CTX_GRX_P11 47 PEG_RX_N3 +5V 48
49 PEG_RX_P3 GND 50
GND GND +3VS_SLI
PCIE_CTX_GRX_N10 51 52
PCIE_CTX_GRX_P10 53 PEG_RX_N2 GND 54
55 PEG_RX_P2 NC 56
C C
PCIE_CTX_GRX_N9 57 GND +3V 58
PCIE_CTX_GRX_P9 59 PEG_RX_N1 +3V 60
61 PEG_RX_P1 GND 62
PCIE_CTX_GRX_N8 63 GND NC 64
PCIE_CTX_GRX_P8 65 PEG_RX_N0 NC 66
67 PEG_RX_P0 NC 68
69 GND NC 70
GND NC SUSP# <45,51,55,57,58>
PCIE_CRX_GTX_N15 0.22U_0402_10V6K 2 1 SLI@ CV20 PCIE_CRX_C_GTX_N15 71 72
PCIE_CRX_GTX_P15 0.22U_0402_10V6K 2 1 SLI@ CV22 PCIE_CRX_C_GTX_P15 73 PEG_TX_N7 NC 74 SLI_FAN_SPEED
PEG_TX_P7 TH_TACH SLI_FAN_SPEED <41,45>
75 76 SLI_FAN_PWM SLI_FAN_PWM <41,45>
PCIE_CRX_GTX_N14 0.22U_0402_10V6K 2 1 SLI@ CV16 PCIE_CRX_C_GTX_N14 77 GND TH_PWN 78
PCIE_CRX_GTX_P14 0.22U_0402_10V6K 2 1 SLI@ CV18 PCIE_CRX_C_GTX_P14 79 PEG_TX_N6 NC 80
81 PEG_TX_P6 PEX_STD_SW# 82
GND AC_DC VGA_AC_DET <23,45,58>
PCIE_CRX_GTX_N13 0.22U_0402_10V6K 2 1 SLI@ CV19 PCIE_CRX_C_GTX_N13 83 84
PEG_TX_N5 PWR_GOOD DGPU_PWROK <19,27,55,58>
PCIE_CRX_GTX_P13 0.22U_0402_10V6K 2 1 SLI@ CV14 PCIE_CRX_C_GTX_P13 85 86 S_DGPU_PWR_EN# S_DGPU_PWR_EN# <51>
87 PEG_TX_P5 PWR_EN 88 CLK2_REQ_GPU#_R
GND CLK_REQ# CLK2_REQ_GPU#_R <15>
PCIE_CRX_GTX_N12 0.22U_0402_10V6K 2 1 SLI@ CV15 PCIE_CRX_C_GTX_N12 89 90
PEG_TX_N4 RSVD S_NVDD_PWR_EN <19>
PCIE_CRX_GTX_P12 0.22U_0402_10V6K 2 1 SLI@ CV17 PCIE_CRX_C_GTX_P12 91 92 S_DGPU_RST S_DGPU_RST <15,18>
93 PEG_TX_P4 RSVD 94 SLAVE_PRESENT#
GND NC SLAVE_PRESENT# <19>
PCIE_CRX_GTX_N11 0.22U_0402_10V6K 2 1 SLI@ CV12 PCIE_CRX_C_GTX_N11 95 96 PCH_THRMTRIP#_R <19,23>
PCIE_CRX_GTX_P11 0.22U_0402_10V6K 2 1 SLI@ CV13 PCIE_CRX_C_GTX_P11 97 PEG_TX_N3 TH_OVERT# 98 PLT_RST#
PEG_TX_P3 NC PLT_RST# <18,23,37,38,44,45,6>
99 100 GC6_EVENT_SLI# 1 2
GND RSVD GC6_EVENT# <19,23>
PCIE_CRX_GTX_N10 0.22U_0402_10V6K 2 1 SLI@ CV10 PCIE_CRX_C_GTX_N10 101 102 RV158 0_0402_5%
CV177
PEG_TX_N2 SMB_DAT EC_SMB_DA2 <15,23,40,45> @ 1
2 1 SLI@ 103 104
0.01U_0402_25V7K
PCIE_CRX_GTX_P10 0.22U_0402_10V6K CV11 PCIE_CRX_C_GTX_P10
PEG_TX_P2 SMB_CLK EC_SMB_CK2 <15,23,40,45>
105 106
PCIE_CRX_GTX_N9 0.22U_0402_10V6K 2 1 SLI@ CV8 PCIE_CRX_C_GTX_N9 107 GND WAKE# 108 GC6_SLI_EN
PEG_TX_N1 RSVD Close to SLI connector
PCIE_CRX_GTX_P9 0.22U_0402_10V6K 2 1 SLI@ CV9 PCIE_CRX_C_GTX_P9 109 110 S_DGPU_PWR_EN S_DGPU_PWR_EN <19,51> 2
111 PEG_TX_P1 RSVD 112
PCIE_CRX_GTX_N8 0.22U_0402_10V6K 2 1 SLI@ CV6 PCIE_CRX_C_GTX_N8 113 GND GND 114 CLK_PCIE_2VGA#
PEG_TX_N0 CLK_PCIE_N CLK_PCIE_2VGA# <15>
PCIE_CRX_GTX_P8 0.22U_0402_10V6K 2 1 SLI@ CV7 PCIE_CRX_C_GTX_P8 115 116 CLK_PCIE_2VGA
PEG_TX_P0 CLK_PCIE_P CLK_PCIE_2VGA <15>
117 118
GND GND
B B
119 120
121 GND GND 122 1 2 1 2
GND GND GC6_EN <27>
RV234 0_0402_5% RV173 0_0402_5%
GC6@
NOGC6@
TE_PT11-FBB0-PC-021
ME@
PCIE_CTX_GRX_N[0..15]
<23,5> PCIE_CTX_GRX_N[0..15]
11/11 for 2nd VGA fan PCIE_CTX_GRX_P[0..15]
need to notic EC <23,5> PCIE_CTX_GRX_P[0..15]
PCIE_CRX_GTX_N[0..15]
<23,5> PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_P[0..15]
<23,5> PCIE_CRX_GTX_P[0..15]
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 32 of 65
5 4 3 2 1
5 4 3 2 1
+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
2
@ @ SLI@
RV92 RV93 RV94 RV121 RV122 STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
45.3K_0402_1% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 20K_0402_1%
@ STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
D D
1
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
<24> STRAP0 STRAP0
<24> STRAP1 STRAP1 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3 STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
STRAP4
<24> STRAP4 CHANGE_GEN3
2
2
OPT@ Pull-up to
@ RV95 RV96 RV97 RV124 RV125 Resistor Values Pull-down to Gnd
SLOT_CLK_CFG
45.3K_0402_1% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
+3VS_VGA
5K 1000 0000 0 GPU and MCH don't share a common reference clock
1
1
10K 1001 0001
1 GPU and MCH share a common reference clock (Default)
15K 1010 0010
Change STRAP1 to
"0000" for N13P-GT 20K 1011 0011
25K 1100 0100 SUB_VENDOR
30K 1101 0101
0 No VBIOS ROM (Default)
35K 1110 0110
+3VS_VGA 45K 1
C 1111 0111 BIOS ROM is present C
OPT@
RV101
X76 30K_0402_1% RV102 RV103
X76@ 2 256MB (Default)
30K_0402_1%
@
15K_0402_1%
@ SMBUS_ALT_ADDR VGA_DEVICE
1
X76
GPU FB Memory (GDDR5) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 VRAM X76 VRAM P/N
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P_MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 33 of 65
5 4 3 2 1
5 4 3 2 1
+LEDVDD B+
2A 80 mil 2A 80 mil
+CMOS_PW
+LEDVDD +LCDVDD_CONN
1 R813 2 0_0805_5% CMOS Camera
1 1 Q94 AO3413_SOT23-3 R432
JLVDS1ME@ C523
0_0603_5%
W=40mils
LVDS_A0#_CONN 1 2 470P_0603_50V8J C524 (40 MIL)
3 1 1 2
D
LVDS_A0_CONN 3 1 2 4 4.7U_0805_25V6-K +CMOS_PW_R
+3VS
LVDS_A1#_CONN 5 3 4 6 2 2 1 CMOS@ 1
9/23 EMI Request
10U_0603_6.3V6M
C519
LVDS_A1_CONN 7 5 6 8 W=60mils CMOS@ CMOS@
7 8 C518
G
LVDS_A2#_CONN 9 10
2
9 10 1 1 0.1U_0402_16V4Z
LVDS_A2_CONN 11 12 C1051 CMOS@ C1052 CMOS@ 2 2 @
11 12 +3VS
LVDS_ACLK#_CONN 13 14 0.1U_0402_16V4Z
15 13 14 16 @
LVDS_ACLK_CONN R822 2 1 4.7K_0402_5%
+3VS 1 0.01U_0402_16V7K
17 15 16 18 @ 2 2
19 17 18 20 DISPOFF# R891 2 1 0_0402_5% BKOFF# 680P_0402_50V7K
D 21 19 20 22 INVPWM BKOFF# <45> CMOS@ D
<45> ECR_EN C528 R435
23 21 22 24 EDID_DATA_CONN 2 1 2
<45> CMOS_ON#
25 23 24 26 EDID_CLK_CONN 1
100K_0402_5%
27 25 26 28 C520
29 27 28 30 @
0.1U_0402_16V4Z
29 30
2
31 32
GNDGND
0.01U_0402_16V7K
8
0.1U_0402_16V7K
1 1 U75 REP@ B_INp 9
25 10 9
REP@ REP@ 1 EPAD 24 A_OUTn C304 CMOS@ 1 2 0.1U_0402_10V6K A_OUTn_C 11 10
2 1 R1515 B_EQ0 2 VDD 12C_EN 23 B_OUTn 0.1U_0402_16V7K REP@ 2 1 C1104 USB30_RX_N1 A_OUTp C303 CMOS@ 1 2 0.1U_0402_10V6K A_OUTp_C 12 11
EC_INVT_PWM <45> 2 2 B_DE0 3 B_EQ0 B_OUTn 22 B_OUTp 2 1 C1103 USB30_RX_P1 13 12 15
0_0402_5% 0.1U_0402_16V7K REP@
@ I2C_R0 B_OUTp 13 GND1
C1101
C1102
INVPWM 2 1 R824 B_EQ1 4 21 14 16
C VGA_BL_PWM <23> 5 I2C_R1 GND 20 A_INn 2 1 C1105 USB30_TX_N1 14 GND2 C
0_0402_5% 0.1U_0402_16V7K REP@
2 @ 1 R847 B_DE1 6 PD# A_INn 19 A_INp 0.1U_0402_16V7K REP@ 2 1 C1106 USB30_TX_P1
PCH_PWM <17> 7 B_DE1 A_INp 18 A_DE1
0_0402_5%
B_INn 8 REXT A_DE1 17 A_EQ0
B_INn A_EQ0
1
B_INp 9 16 A_DE0 close to U75
10 B_INp SCL_CTL 15 A_EQ1
OPT@ 1 R1212 2 11 GND SDA_CTL 14
<17> PCH_ENBKL R1569 REP@ A_OUTn TEST
0_0402_5% 2.49K_0402_1% A_OUTp 12 A_OUTn TEST 13
A_OUTp VDD
SLI@ 1 R1201 2
2
<23> VGA_ENBKL ENBKL <45>
PS8710BTQFN24GTR-A0_TQFN24_4X4
0_0402_5%
2
R827
預預預預
100K_0402_1%
+3VS
Equalizer control and program for channel B Programmable output pre-emphasis level setting for channel B
1
B_EQ0 R1571 1 REP@ 2 4.7K_0402_5% 3.3V tolerant. Internally pulled down at ~150KΩ 3.3V tolerant. Internally pulled down at ~150KΩ
[B_EQ1, B_EQ0] == [B_DE1, B_DE0] ==
B_EQ1 R1573 1 REP@ 2 4.7K_0402_5% LL: adaptive EQ enable
LH: program EQ for channel loss up to 7dB
* **LL: 3.5dB de-emphasis
LH: No de-emphasis
HL: program EQ for channel loss up to 14.5dB HL: 7dB de-emphasis
B_DE0 R1575 1 @ 2 4.7K_0402_5%
* **HH: program EQ for channel loss up to 11.5dB HH: 5dB with boost output swing
預預預預
LVDS_ACLK# R1255 1 OPT@ 2 0_0402_5% LVDS_ACLK#_CONN +3VS
<17> LVDS_ACLK# 1 2
LVDS_ACLK R1257 OPT@ 0_0402_5% LVDS_ACLK_CONN
<17> LVDS_ACLK LVDS_A0# 1 2 LVDS_A0#_CONN
R1259 OPT@ 0_0402_5% Equalizer control and program for channel A Programmable output pre-emphasis level setting for channel A
<17> LVDS_A0# LVDS_A0 1 2 LVDS_A0_CONN A_EQ0 1 REP@ 2 4.7K_0402_5%
R1261 OPT@ 0_0402_5% R1570 3.3V tolerant. Internally pulled down at ~150KΩ 3.3V tolerant. Internally pulled down at ~150KΩ
<17> LVDS_A0 LVDS_A1# 1 2 LVDS_A1#_CONN
PCH R1262 OPT@ 0_0402_5% [A_EQ1, A_EQ0] == [A_DE1, A_DE0] ==
<17> LVDS_A1# LVDS_A1 1 2 LVDS_A1_CONN A_EQ1 1 REP@ 2 4.7K_0402_5%
R1265 OPT@ 0_0402_5% R1572
B <17> LVDS_A1
LVDS_A2# R1267 1 OPT@ 2 0_0402_5% LVDS_A2#_CONN
LL: adaptive EQ enable
LH: program EQ for channel loss up to 7dB
* **LL: 3.5dB de-emphasis
LH: No de-emphasis B
<17> LVDS_A2# 1 2
LVDS_A2 R1269 OPT@ 0_0402_5% LVDS_A2_CONN HL: program EQ for channel loss up to 14.5dB HL: 7dB de-emphasis
<17> LVDS_A2
A_DE0 R1574 1 @ 2 4.7K_0402_5%
* **HH: program EQ for channel loss up to 11.5dB HH: 5dB with boost output swing
W=60mils
R1467 D28 @ D59 @
R816 R817 INVPWM B_INn 9 10 1 B_INn USB20_P0 4 1 DMIC_DATA
150_0603_1% 100K_0402_5% @ 100K_0402_5% DMIC_CLK 1 @ 2 1
I/O3 I/O1
470P_0402_50V7K
470P_0402_50V7K
1
100P_0402_50V8J
2
6
1@ 1@ A_OUTn_C 7 7 4 4 A_OUTn_C 5 2
+3VS VDD GND
3
2
S
@ C527
Q67A 2 1 R820 2 2
G
LCD_ENVDD# Q68 A_OUTp_C 6 6 5 5 A_OUTp_C
2N7002DW-T/R7_SOT363-6 2
AO3413_SOT23-3
100K_0402_5% 2 2 3 6 3
1 1
D 3 USB20_N0 DMIC_CLK
1
A I/O4 I/O2 A
0.01U_0402_16V7K
C1046
C1050
3
8 AZC099-04S.R7G_SOT23-6
0.1U_0402_16V4Z +LCDVDD_CONN
2 2
SLI@
R1197 1 2 0_0402_5% 5 W=60mils YSCLAMP0524P_SLP2510P8-10-9
<23> VGA_ENVDD Q67B
@
OPT@ 2 2N7002DW-T/R7_SOT363-6
R1195 1 0_0402_5%
<17> PCH_ENVDD
4
C531 C532
R821 4.7U_0603_6.3V6K 0.1U_0402_16V4Z Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
100K_0402_5% 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/ CMOS/ USB-ReDriver
Size Document Number Rev
2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 34 of 65
5 4 3 2 1
A B C D E
3 3 3
2
1 GREEN
2
1 RED
BAT54S-7-F_SOT23-3
+5VS
D36
+CRT_VCC
F1
CRT Connector
<23> VGA_CRT_R
@ @ @ 2 1 1 2 +CRT_VCC_CONN
SLI@ D31 D32 D33 1
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 RB491D_SC59-3 0.5A_8V_KMC3S050RY
VGA_CRT_G R1273 1 2 0_0402_5% C536
<23> VGA_CRT_G
1 SLI@
W=40mils 2
0.1U_0402_16V4Z
1
JCRT1
6
T75 PAD CRT_TEST 11
DAC_RED_1 L16 1 2 NBQ100505T-800Y_0402 RED 1
7
CRT_DDC_DAT_CONN 12
DAC_GRN_1 L17 1 2 NBQ100505T-800Y_0402 GREEN 2
8
JVGA_HS 13
DAC_BLU_1 L18 1 2 NBQ100505T-800Y_0402 BLUE 3
9
1
1 1 1 1 1 1 JVGA_VS 14
4
R830 R831 R832 C537 C538 C539 C540 C542 C541 10 G 16
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J CRT_DDC_CLK_CONN 15 G 17
2 2 2 2 2 2 5
2
1
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J C543 SUYIN_070546HR015M22BZR
CLOSE TO CONN
100P_0402_50V8J ME@
2
DAC_RED R1274 1 2 0_0402_5%
<17> DAC_RED
2 OPT@ 2
DAC_GRN R1181 1 2 0_0402_5% +CRT_VCC
<17> DAC_GRN R833
OPT@ 1 2
DAC_BLU R1182 1 2 0_0402_5% 1
<17> DAC_BLU
OPT@ C544 OE# 1K_0402_5%
0.1U_0402_16V4Z
2
1
R840 NBQ100505T-800Y_0402
OPT@
OE#
P
CRT_HSYNC R1183 1 2 0_0402_5% HSYNC_G 2 4 CRT_HSYNC_1 1 2 CRT_HSYNC_2 1 2 JVGA_HS
<17> CRT_HSYNC A Y
33_0603_5% L19
G
U24
VGA_CRT_HSYNC R1184 1 2 0_0402_5% SN74AHCT1G125DCKR_SC70-5 1
<23> VGA_CRT_HSYNC
3
@
D8
SLI@ C545 @
10P_0402_50V8J JVGA_VS 3 6 JVGA_HS
+CRT_VCC 2 I/O2 I/O4
1 2 5 +5VS
GND VDD
C546 OE#
0.1U_0402_16V4Z
CRT_VSYNC R1185 1 2 0_0402_5% 2 CRT_DDC_CLK_CONN 1 4 CRT_DDC_DAT_CONN
<17> CRT_VSYNC I/O1 I/O3
5
1
R839 NBQ100505T-800Y_0402
OPT@
OE#
P
VGA_CRT_VSYNC R1186 1 2 0_0402_5% VSYNC_G 2 4 CRT_VSYNC_1 1 2 CRT_VSYNC_2 1 2 JVGA_VS AZC099-04S.R7G_SOT23-6
3 <23> VGA_CRT_VSYNC A Y 3
33_0603_5% L20
G
SLI@ U25 1
SN74AHCT1G125DCKR_SC70-5
+3VS
3
@ C547
10P_0402_50V8J
+CRT_VCC 2
1
1
2.2K_0402_5%
5
G
R837 R838
2.2K_0402_5%
2
Q73B
2N7002KDW H_SOT363-6
<17> CRT_DDC_CLK CRT_DDC_CLK R1190 1 2 0_0402_5% CRT_DDC_CLK_R 1 6 CRT_DDC_CLK_CONN
D
OPT@
S
1 1
@ @
Q73A C548 C549
<23> VGA_CRT_DATA VGA_CRT_DATA R1191 1 2 0_0402_5% 2N7002KDW H_SOT363-6 100P_0402_50V8J 68P_0402_50V8K
SLI@ 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 35 of 65
A B C D E
5 4 3 2 1
+3VS +3VS_VGA
W CM-2012-900T_4P
HDMI_CLK+_CK 4 3 HDMI_CLK+_CONN 1 2
4 3
2
C1016 3.3P_0402_50V8C
2
@ R1468 R1469
HDMI_CLK-_CK 1 2 HDMI_CLK-_CONN 1 2
1 2 HDMIDAT_R 0_0402_5% 0_0402_5%
C1015 3.3P_0402_50V8C
L23 HDMICLK_R OPT@ SLI@
2
@
1
1
L24 D57
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN 1 2 PJSOT24C 3P C/A SOT-23 Q152
1 2 C1018 3.3P_0402_50V8C @ BSH111_SOT23-3
D D
2
HDMI@
@ R1470 1 SLI@ 2
G
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN 1 2 VGA_HDMI_CLK 0_0402_5%
<24> VGA_HDMI_CLK
1
4 3 C1017 3.3P_0402_50V8C
W CM-2012-900T_4P <17> HDMICLK HDMICLK R1471 1 OPT@ 2 0_0402_5% 3 1 HDMICLK_R
@
D
W CM-2012-900T_4P
G
HDMI_TX1+_CK 4 3 HDMI_TX1+_CONN 1 2 VGA_HDMI_DATA R1472 1 SLI@ 2 0_0402_5%
4 3 <24> VGA_HDMI_DATA
C1020 3.3P_0402_50V8C
@ <17> HDMIDAT HDMIDAT R1473 1 OPT@ 2 0_0402_5% 3 1 HDMIDAT_R
HDMI_TX1-_CK 1 2 HDMI_TX1-_CONN 1 2
1 2
D
C1019 3.3P_0402_50V8C
L26 Q80
@
+3VS BSH111_SOT23-3
L27 HDMI@
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN 1 2 +5VS
1 2 C1022 3.3P_0402_50V8C
2
@
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN 1 2
4 3 C1021 3.3P_0402_50V8C R862 +5VS PMEG2010AEH
1M_0402_5%
2
W CM-2012-900T_4P IF=0.1A, 0.29V HDMI@
@
D37
2
IF=1A, 0.43V
G
Q85
2
1
PMEG2010AEH_SOD123
R1486 1 OPT@ 2 3 1
<17> TMDS_B_HPD
1
0_0402_5%
D
2N7002_SOT23
2
R885 @
1
20K_0402_5% D38 F2 HDMI@
C BAT54S-7-F_SOT23-3 0.5A_8V_KMC3S050RY C
R320
1
499_0402_1%
1
SLI@
2
HDMI_CLK+_CONN 1 2
R1499 +5VS_HDMI
HDMI_CLK-_CONN SLI@ 1 2 0_0402_5%
R321 499_0402_1%
SLI@ SLI@ 1 C561
HDMI_TX0+_CONN 1 2 for NV recommend 0.1U_0402_16V4Z
2
R322 499_0402_1% HDMI@
HDMI_TX0-_CONN SLI@ 1 2 L67
R323 499_0402_1% R860 R861 2
SLI@ BLM18PG181SN1D_0603
HDMI_TX1+_CONN 1 2 R859 2 @ 1 HDMI_DET_R 2 1 2.2K_0402_5% 2.2K_0402_5%
R324 499_0402_1% <23> DGPU_HDMI_HPD @ HDMI@ HDMI@
1
HDMI_TX1-_CONN SLI@ 1 2 1K_0402_5%
1
R325 499_0402_1%
R864
100K_0402_5%
HDMI_TX2+_CONN SLI@ 1 2 1
R326 499_0402_1% @ C59
HDMI_TX2-_CONN SLI@ 1 2
@
220P_0402_25V8J JHDMI1
R327 499_0402_1% D 2 HDMI_DET 19
1
HP_DET
2
18
2 Q114 17 +5V
+3VS DDC/CEC_GND
G 2N7002H 1N_SOT23-3 HDMIDAT_R 16
S HDMI@ HDMICLK_R 15 SDA
3
1 @ 2 14 SCL
R328 100K_0402_5% 13 Reserved
VGA_HDMI_CLK- SLI@ CV254 1 2 0.1U_0402_10V6K HDMI_CLK-_CK R866 1 @ 2 0_0402_5% HDMI_CLK-_CONN 12 CEC 20
<24> VGA_HDMI_CLK- CK- GND
11 21
VGA_HDMI_CLK+ SLI@ CV253 1 2 0.1U_0402_10V6K HDMI_CLK+_CK R865 1 @ 2 0_0402_5% HDMI_CLK+_CONN 10 CK_shield GND 22
<24> VGA_HDMI_CLK+ CK+ GND
<24> VGA_HDMI_TX0- VGA_HDMI_TX0- SLI@ CV256 1 2 0.1U_0402_10V6K HDMI_TX0-_CK R868 1 @ 2 0_0402_5% HDMI_TX0-_CONN 9 23
B 8 D0- GND B
R327 R326
VGA_HDMI_TX0+ SLI@ CV255 1 2 0.1U_0402_10V6K HDMI_TX0+_CK R867 1 @ 2 0_0402_5% HDMI_TX0+_CONN 7 D0_shield
<24> VGA_HDMI_TX0+ D0+
<24> VGA_HDMI_TX1- VGA_HDMI_TX1- SLI@ CV258 1 2 0.1U_0402_10V6K HDMI_TX1-_CK R870 1 @ 2 0_0402_5% HDMI_TX1-_CONN 6
5 D1-
VGA_HDMI_TX1+ SLI@ CV257 1 2 0.1U_0402_10V6K HDMI_TX1+_CK R869 1 @ 2 0_0402_5% HDMI_TX1+_CONN 4 D1_shield
<24> VGA_HDMI_TX1+ D1+
<24> VGA_HDMI_TX2- VGA_HDMI_TX2- SLI@ CV260 1 2 0.1U_0402_10V6K HDMI_TX2-_CK R872 1 @ 2 0_0402_5% HDMI_TX2-_CONN 3
2 D2-
680_0402_1% 680_0402_1% D2_shield
OPT@ OPT@ <24> VGA_HDMI_TX2+ VGA_HDMI_TX2+ SLI@ CV259 1 2 0.1U_0402_10V6K HDMI_TX2+_CK R871 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1
D2+
R324 R323 TAITW _PDVBR0-19FLBS4NN4N0
ME@
680_0402_1% 680_0402_1%
OPT@ OPT@
R321 R320
680_0402_1% 680_0402_1%
OPT@ OPT@
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 36 of 65
5 4 3 2 1
A B C D E
For RF request
+1.5VS LPC_AD1 <14,45>
LPC_AD0_R R878 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <14,45>
9/18 JP1 Pin2,24,52 contact to +3VS_WLAN for AOAC function PCI_RST#_R R879 1 @ 2 0_0402_5% PLT_RST#
0.047U_0402_16V4Z
+1.5VS CLK_PCI_DB
1 CLK_PCI_DB <18>
C57
Mini-Express Card(WLAN/WiMAX)
1
@ 1 1
1 2 1
R400
0_0603_5% C564 C565
0.1U_0402_16V4Z 0.1U_0402_16V4Z
JWLN1 2 2
2
COMBT@ <16,19,38> PCIE_WAKE# PCIE_WAKE# 1 2
3 WAKE# 3.3V 4
BT_CTRL R897 1 2 0_0402_5% BT_CTRL_R 5 NC GND 6 +1.5VS_WLAN
WLAN_CLKREQ1# 7 NC 1.5V 8 LPC_FRAME#_R
<15> WLAN_CLKREQ1# CLKREQ# NC
9 10 LPC_AD3_R
1 2 BT_DISABLE# 11 GND NC 12 LPC_AD2_R
<15> CLK_PCIE_WLAN1# REFCLK- NC
13 14 LPC_AD1_R
R1556 <15> CLK_PCIE_WLAN1 15 REFCLK+ NC 16 LPC_AD0_R
1K_0402_5% PCI_RST#_R 17 GND NC 18 R1541 2 @ 1 0_0402_5%
19 NC GND 20 1 2 EC_WL_OFF# <45>
COMBT@ CLK_PCI_DB WL_OFF# R880 0_0402_5%
NC NC PCH_WL_OFF# <18>
21 22 PLT_RST#
GND PERST# PLT_RST# <18,23,32,38,44,45,6>
For isolate Intel Rainbow Peak and <15> PCIE_PRX_DTX_N2
23
PERn0 +3.3Vaux
24 R881 1 2 @ 0_0402_5%
+3VALW
25 26 R882 1 2 0_0402_5%
Compal debug card. <15> PCIE_PRX_DTX_P2 PERp0 GND +3VS_WLAN
27 28
29 GND +1.5V 30 SMB_CLK_S3_R R883 1 2 @ 0_0402_5%
GND SMB_CLK SMB_CLK_S3 <12,13,15,46>
31 32 SMB_DATA_S3_R R884 1 2 @ 0_0402_5% SMB_DATA_S3 <12,13,15,46>
<15> PCIE_PTX_C_DRX_N2 PETn0 SMB_DATA
33 34
<15> PCIE_PTX_C_DRX_P2 35 PETp0 GND 36
+3VS_WLAN GND USB_D- USB20_N10 <18>
37 38
39 NC USB_D+ 40 USB20_P10 <18>
41 NC GND 42
43 NC LED_WWAN# 44
100_0402_1% 45 NC LED_WLAN# 46
NC LED_WPAN# +3VS +3VS_WLAN
R887 47 48
EC_TX 1 2 49 NC +1.5V 50 J8
@
<45> EC_TX NC GND
EC_RX 1 2 BT_DISABLE# 51 52
<45> EC_RX NC +3.3V 1 2
R888 1 2
100_0402_1% 53 54
GND GND
JUMP_43X79
+3VALW
TAITW_PFPET0-AFGLBG1ZZ4N0 Q104
2
For EC to detect AO3413_SOT23-3
R889
debug card insert. ME@
D
3 1 1
2 100K_0402_5% 2
AOAC@
1 C533
WLAN&BT Combo module circuits AOAC@ AOAC@ 1 0.1U_0402_16V4Z
G
2
C526 2
C1048
BT on module BT on module 0.1U_0402_16V4Z
2 0.01U_0402_25V7K
AOAC@
Enable Disable AOAC@ 2
R436
1 2 1
<51> AOAC_ON#
@
BT_CRTL 100K_0402_5%
H L C1055
0.1U_0402_16V4Z
2
PCH_BT_ON# L H
softstart (RC) will check on EVT PCB
R1557
0_0402_5%
<19> PCH_BT_DISABLE# 1 2 BT_CTRL
@
6
D D
<19,47> PCH_BT_ON# 2 5 SUSP <10,51,55,57> 9/18 Increase for Intel AOAC function
Q157A
Q157B
G G
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S S
1
COMBT@ COMBT@
3 3
TAITW_PFPET0-AFGLBG1ZZ4N0
SATA_DET# 1 2
<14> SATA_DET# R896 0_0402_5% ME@
For SSD use: @
Security Classification
2011/11/01
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 37 of 65
A B C D E
5 4 3 2 1
@
1 2 +LX_R 1 2 +LX +1.1V
JUMP_43X79
1000P_0402_50V7K
AR8161 R1357,R1372,L76
10U_0805_10V4Z
4.7UH_SIA4012-4R7M_20%
0.1U_0402_16V4Z
<DVDDL,AVDDL>
@ C935
C936
C937
R1357 8161@ 0_0402_5% 1 1
Q70
+1.1_DVDDL 1 2
3
D
1 Note: Place Close to LAN chip L75 L76
2 2 L39 DCR< 0.15 ohm FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
D 1 1
LP2301ALT1G_SOT-23 Rate current > 1A D
+1.1_AVDDL_L 1 2 +1.1_AVDDL 1 2 +1.1_DVDDL
G
2
0.1U_0402_16V4Z
1U_0402_6.3V4Z
4.7U_0603_6.3V6K
C552 C1047
0.1U_0402_16V4Z 0.01U_0402_25V7K 8161@
2
C967
C980
C278
2 1 1 1
LAN_PWR_ON# 2 R59 1
<45> LAN_PWR_ON#
100K_0402_5%
1 Close to 2 2 2
@ C1056 Pin40
0.1U_0402_16V4Z
2
Vendor recommand reseve the
PU resistor close LAN chip Place close to Pin34
@
PLT_RST#
<18,23,32,37,44,45,6> PLT_RST#
C
<15> PCIE_PRX_DTX_N1 C946 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 ACTIVITY# C
TX_N LED_0 39 ACTIVITY# <39>
LAN_LINK#
C947 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 23 LAN_CLK_SEL R58 2 1 LAN_LINK# <39>
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161
36
@ 10K_0402_5% 2011103 for vendor comment
<15> PCIE_PTX_C_DRX_N1 RX_N 12 MDI0-
35 TRXN0 11 MDI0- <39>
MDI0+
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 15 MDI1-
MDI0+ <39> Place Close to LAN chip
32 TRXN1 14 MDI1- <39>
MDI1+
<15> CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ <39>
33 18 MDI2- 8151@ 49.9_0402_1%
<15> CLK_PCIE_LAN REFCLK_P TRXN2 17 MDI2- <39>
MDI2+ MDI0+ R1358 1 2 1@ 2 C938 1000P_0402_50V7K
2 TRXP2 21 MDI2+ <39>
PLT_RST# MDI3- 8151@ 49.9_0402_1% 8151@
PERST# TRXN3 MDI3- <39>
20 MDI3+ MDI0- R1359 1 2 1 2 C939 0.1U_0402_16V4Z
R1369 1 @ 2 0_0402_5% PCIE_WAKE#_R 3 TRXP3 MDI3+ <39> Place Close to PIN1 8151@ 49.9_0402_1%
<16,19,37> PCIE_WAKE# W AKE#
<45> LAN_WAKE# R1370 1 2 0_0402_5% MDI1+ R1360 1 2 1@ 2 C940 1000P_0402_50V7K
25 10 LAN_RBIAS 1 2 +3V_LAN 8151@ 49.9_0402_1% 8151@
26 SMCLK RBIAS R1371 2.37K_0402_1% MDI1- R1361 1 2 1 2 C941 0.1U_0402_16V4Z
SMDATA 8151@ 49.9_0402_1%
Place Close to PIN10
28 1 +3V_LAN MDI2+ R1362 1 2 1@ 2 C942 1000P_0402_50V7K
NC VDD33
1000P_0402_50V7K
27
10U_0805_10V4Z
10U_0805_10V4Z
8151@ 49.9_0402_1% 8151@
0.1U_0402_16V4Z
1U_0402_6.3V4Z
TESTMODE 1 1 1 1
@
@ MDI2- R1363 1 2 1 2 C943 0.1U_0402_16V4Z
40 +LX R1372 8161@ 30K_0402_5% 8151@ 49.9_0402_1%
LX +LX
C950
C951
C952
C953
C954
LAN_XTALO 7 1 2 MDI3+ R1364 1 2 1@ 2 C944 1000P_0402_50V7K
+3VS
1
LAN_XTALI 8 XTLO 8151@ 2 2 2 2 8151@ 49.9_0402_1% 8151@
XTLI 5 +1.7_VDDCT 1 2 MDI3- R1365 1 2 1 2 C945 0.1U_0402_16V4Z
VDDCT/ISOLAN C955 0.1U_0402_16V4Z
4 Note : C938, C940, C942, 944, reserved for EMI.
<15> CLKREQ_LAN# CLKREQ# 24 +1.1_DVDDL_R R1366 1 2 0_0402_5% +1.1_DVDDL
DVDDL/PPS 37
+1.1_AVDDL 13 DVDDL_REG/DVDDL +1.1_DVDDL 8151@
B
+1.1_AVDDL 19 AVDDL B
AVDDL For AR8151: Stuff 49.9K and 0.1u
+1.1_AVDDL 31 16 +AVDDH_AVDD3.3
+1.1_AVDDL_L 34 AVDDL AVDDH/AVDD33 22 +2.7_AVDDH For AR8161: NC
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C956
C957
C958
C959
C960
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
1 1 1 1 1
C961
C962
C963
C966
41 1 1 1 2
GND +3V_LAN
C964
C965
1 1
AR8161-AL3A-R_QFN40_5X5 8151@
2 2 2 2 2 8161@ +2.7_AVDDH
U63 2 2 2 1 R1367 1 2 0_0402_5%
8161@ 2 2
8151@
For AR8151: Stuff C966,R1366 +AVDDH_AVDD3.3 R1368 1 2 0_0402_5% +2.7_AVDDH
For AR8161: NC
Near
Near Near Near Near SA00003LE20 Near Near Near
1U_0402_6.3V4Z
0.1U_0402_16V4Z
Pin9
Pin13 Pin19 Pin31 Pin6 Pin22 Pin37 Pin24
C948
C949
8151@ 1 1
8161@
LAN_XTALI 2 2
Y6
4 3 LAN_XTALO
NC OSC
Place close to Pin16
1 2
OSC NC
A 1 1 For AR8151: Stuff R1368 for +AVDD3.3 A
25MHZ_12PF_X3G025000DC1H~D
C968 C969
For AR8161: Stuff R1367,C949 for +AVDDH
15P_0402_50V8J 15P_0402_50V8J
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-AR8151/8161
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 38 of 65
5 4 3 2 1
5 4 3 2 1
LAN Transformer
+1.7_VDDCT
T49
2 8151@ 1 +1.7_VDDCT_R 1 24 MCT3 2 R1374 1
TCT1 MCT1
R1373 1 2 0_0402_5% If vendor test result is "ok", need to change as below
MDI3+ 2 1:1 23 MDO3+
0_0603_5% C976 C970 <38> MDI3+ TD1+ MX1+ 1. Change R1374,R1375,R1376,R1377 to 0 ohm
@ 8151@
1U_0402_6.3V4Z 0.1U_0402_16V4Z
D
2 1
2. Change R1194 to 75 ohm D
3. Mount F6
MDI3- 3 22 MDO3- 4. Un mount F3,F4,F5
<38> MDI3- TD1- MX1-
6/23 update --> 2012/02/20 : already implement to Sch
4 21 MCT2 2 R1375 1
TCT2 MCT2
2 0_0402_5%
MDI2+ 5 1:1 20 MDO2+
8151@ C972 <38> MDI2+ TD2+ MX2+ BOM option:
0.1U_0402_16V4Z 1. For GDTx4
1 R1374/R1375/R1376/R1377=75 ohm
R1194=0 ohm
MDI2- 6 19 MDO2-
<38> MDI2- TD2- MX2- MCT0~3=Mount
7 18 MCT1 2 R1377 1
TCT3 MCT3
2 0_0402_5%
2. For GDTx1
C970 C972 MDI1+ 8 1:1 17 MDO1+ R1374/R1375/R1376/R1377=0 ohm
C974 <38> MDI1+ TD3+ MX3+
8151@
0.1U_0402_16V4Z R1194=75 ohm
8161S@ 8161S@ 1 MCT0=Mount
MCT1~3=Mount
MDI1- 9 16 MDO1-
<38> MDI1- TD3- MX3-
0.1U_0402_16V4Z 0.1U_0402_16V4Z
10 15 MCT0 2 R1376 1
TCT4 MCT4
2 0_0402_5%
MDI0+ 11 1:1 14 MDO0+
C975 <38> MDI0+ TD4+ MX4+
1
C974 C975 8151@
0.1U_0402_16V4Z
1 R1194
8161S@ 8161S@ 75_0402_5%
MDI0- 12 13 MDO0-
<38> MDI0-
2
TD4- MX4-
1
C 0.1U_0402_16V4Z 0.1U_0402_16V4Z Place close to T49(TCT) pin NS892402 1G C
C973
10P_1206_2KV7K
2
5 4 7 6 2 R1378 1 10
MCT1 1
5 6 +3V_LAN Green LED+
MCT0 220_0402_5% MDO0+ 1
C978 @
11
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
R02 2 MDO0- 2
PR1-
2
2
MDO1+ 3
PR2+
MDO2+ 4
F6
F3
F4
F5
PR3+
SURGE@ SURGE@ SURGE@ SURGE@ MDO2- 5
PR3-
1
1
MDO1- 6
PR2-
MDO3+ 7 14
D67 8151S@ PR4+ G2
MDI0- 1 10 MDO3- 8 13
2 1 10 9 MDI1+ PR4- G1
MDI0+ 3 2 9 8 ACTIVITY# 11
4 3 8 7 <38> ACTIVITY# Yellow LED-
MDI1-
GND
5 4 7 6 2 R1442 1 12
5 6 1 +3V_LAN Yellow LED+
Reserve for EMI go rural solution 220_0402_5%
C979 @ SANTA_130456-111
11
TCLAMP3302N.TCT_SLP2626P10-10 470P_0402_50V7K
R02 2
A A
REMOTE1+
1
+3VS placed near by VRAM REMOTE1+
Under VRAM
C449 1
1
2200P_0402_50V7K U29 @ C
2 REMOTE1- C982 2 Q137
Remove +VDD netname B
100P_0402_50V8J MMST3904-7-F_SOT323-3
1 10 EC_SMB_CK2 2 E
EC_SMB_CK2 <15,23,32,45>
3
VDD SMCLK REMOTE1-
REMOTE1+ 2 9 EC_SMB_DA2
DP1 SMDATA EC_SMB_DA2 <15,23,32,45>
REMOTE2+ 2
1 REMOTE1- 3 8
DN1 ALERT# R624
C443
C658 0.1U_0402_16V4Z REMOTE2+ 4 7 2 1
2200P_0402_50V7K 1 DP2 THERM# +3VS Close to SSD side
2 REMOTE2- REMOTE2- 5 6 REMOTE2+
DN2 GND 10K_0402_5%
1
1
@ @ C
C984 2 Q138
EMC1403-2-AIZL-TR_MSOP10 100P_0402_50V8J B MMST3904-7-F_SOT323-3
FAN_PWM & TACH 2 E
3
for PWM FAN Address 1001_101xb REMOTE2-
REMOTE2+/-:
internal pull up 1.2K to 1.5V
C
Trace width/space:10/10 mil C
R for initial thermal
Trace length:<8"
shutdown temp
B B
FAN1 Conn
+5VS
JFAN1
1
2 1
2 1 <45> EC_FAN_SPEED 2
<45> EC_FAN_PW M 3
C986 C49 @ 4 3
10U_0805_10V6K 0.1U_0402_10V7K 5 4
1 2 6 G5
G6
ACES_85205-04001
ME@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EMC1403/2103_Thermal sensor/FAN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 40 of 65
5 4 3 2 1
A B C D E F G H
1
SATA HDD Conn. SATA ODD Conn. 1
1 1
SATA_ITX_DRX_P1 2 GND SATA_ITX_DRX_P2_CONN 2 GND
<14> SATA_ITX_DRX_P1 A+ <14> SATA_ITX_DRX_P2_CONN A+
SATA_ITX_DRX_N1 3 SATA_ITX_DRX_N2_CONN 3
<14> SATA_ITX_DRX_N1 A- <14> SATA_ITX_DRX_N2_CONN A-
4 4
SATA_DTX_C_IRX_N1 C627 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5 GND SATA_DTX_C_IRX_N2 C629 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2 5 GND
<14> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 C628 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P1 6 B- <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C630 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P2 6 B-
<14> SATA_DTX_C_IRX_P1 7 B+ <14> SATA_DTX_C_IRX_P2 7 B+
GND R1479 1 2 0_0402_5% GND
<32,45> SLI_FAN_SPEED 1
<19> ODD_DETECT# R1476 @2 0_0402_5%
R710 1 @2 0_0402_5% 8
8 9 DP
9 VCC3.3 10 +5V
10 VCC3.3 +5VS_ODD 11 +5V
11 VCC3.3 12 MD 15
12 GND R921 1 2 10K_0402_5% ODD_DA# 13 GND GND 14
GND +3VS GND GND
@J12
@ J12 13
1 2 +5VS_HDD 14 GND R1497 1 @ 2 0_0402_5%
+5VS 1 2 15 VCC5 <18> ODD_DA#_R 1 2
R1494 0_0402_5% SANTA_202404-1
JUMP_43X79 16 VCC5 <32,45> SLI_FAN_PWM
17 VCC5
18 GND
19 RESERVED
+5VS 20 GND
21 VCC12
22 VCC12
2 VCC12 2
1 1 1 1 1
23
C631 C632 C633 C634 C635 24 GND
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0603_6.3V6M 10U_0603_6.3V6M GND
2 2 2 2 2 SANTA_190302-1
1
1
1 2 1 1
2
2
2
2 1 2 2
2 R1110 1 ODD_EN#
100K_0402_5%
3
D
2
C1057 ODD_EN# 5 Q89B
6
D @ 0.01U_0402_16V7K G 2N7002KDWH_SOT363-6
2
<19> ODD_EN G 1
Q89A S
4
1
2N7002KDWH_SOT363-6
S
1
R1478
100K_0402_5%
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 41 of 65
A B C D E F G H
A B C D E F G H
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0_0603_5%
0.1U_0402_16V4Z
600ohms @100MHz 1A 1 1
CA13
CA14
1U_0603_10V4Z
P/N: SM01000BU00 1 1
CA15
CA16
1 2 2 1
2 2
+3VS_DVDD +3VS_DVDDIO
+5VS_AVDD
1 RA6 2 +3VS_DVDDIO
10U_0603_6.3V6M
0.1U_0402_16V4Z
1 RA5 2 +5VS_PVDD +5VS_AVDD 0_0402_5%
+5VS 1 1
CA17
CA18
0_0805_5% P/N: SM01000DI00
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+3VS_DVDDIO
+3VS_DVDD
2 1 1 1 2 2 2
CA21
CA22
600ohms @100MHz 2A @ @
CA6
CA7
CA8
P/N: SM01000EE00
1 2 2 2 1 Place near UA8.Pin1
11/07 -->
39
46
25
38
9
UA8 Place near UA8.Pin38 Change CA17 type to 0603
Place near UA8.Pin39, Pin46
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD1
30 mils
EAPD 47 24 SPKOUT_R1
<43> EAPD DAPD/COMB_JACK LINE1-R(PORT-C-R) SPKOUT_R1 <43>
2 4 23 SPKOUT_L1
External SPK (One Channel) 2
PD# LINE1-L(PORT-C-L) SPKOUT_L1 <43>
HDA_SDOUT_AUDIO 5 22 C_MIC2 CA1277 2 1 2.2U_0603_6.3V6K MIC2_R
<14> HDA_SDOUT_AUDIO SDATA-OUT MIC1-R(PORT-B-R) MIC2_R <49>
6 21
Ext. MIC
HDA_BITCLK_AUDIO C_MIC1 CA1276 2 1 2.2U_0603_6.3V6K MIC1_R
+3VS <14> HDA_BITCLK_AUDIO BIT-CLK MIC1-L(PORT-B-L) MIC1_R <49>
HDA_SDIN0 2 1 HDA_SDIN0_R 8 17 10 mils
<14> HDA_SDIN0 SDATA-IN MIC2-R(PORT-F-R)
RA1637
2
16
22_0402_5% MIC2-L(PORT-F-L)
RA475
@ 4.7K_0402_5% HDA_SYNC_AUDIO 10 15
<14> HDA_SYNC_AUDIO SYNC LINE2-R(PORT-E-R)
HDA_RST_AUDIO# HDA_RST_AUDIO# 11 14
<14> HDA_RST_AUDIO#
1
RESET# LINE2-L(PORT-E-L)
PC_BEEP 12
PCBEEP
@ CA1368 40
100P_0402_50V8J~N 2 RA1640 1 JDREF 19 SPK-OUT-L+
MIC Sense --> RA1639 place near pin13 JDREF 41
Capless HP Sense --> RA1638 place near pin34 20K_0402_1% 20 SPK-OUT-L-
MONO-OUT(PORT-H) 44
MIC_JD RA1639 2 1 20K_0402_1% SENSEA 13 SPK-OUT-R-
<49> MIC_JD Sense A 45
PLUG_IN RA1638 2 1 39.2K_0402_1% 18 SPK-OUT-R+
<49> PLUG_IN Sense-B 10 mils
1 2 CBN 35 33 HPOUTR_R R3 2 1 75_0402_5% HP_OUTR
CBN HPOUT-R(PORT-A-R) HP_OUTR <49>
CA1288 2.2U_0603_6.3V6K HeadPhone
CBP 36 32 HPOUTL_R R4 2 1 75_0402_5% HP_OUTL
CBP HPOUT-L(PORT-A-L) HP_OUTL <49>
2 1 CPVEE 34 48 SPDIF R945 1 2 SPDIF_OUT SPDIF
CPVEE SPDIF-OUT SPDIF_OUT <49>
CA19 2.2U_0603_6.3V6K FBMA-10-100505-301T_2P
2 1 LDO_CAP 28 EMI Request
3 CA20 4.7U_0603_6.3V6K LDO-CAP 3 DMIC_CLK_R R955 1 2 DMIC_CLK 3
GPIO1/DMIC-CLK DMIC_CLK <34>
FBMA-10-100505-301T_2P Int. MIC
Del RA3, RA4 29 2 DMIC_DATA_R R954 2 1 0_0402_5% DMIC_DATA
MIC2-VREFO GPIO0/DMIC-DATA DMIC_DATA <34>
30 10 mils
MIC1-VREFO-R
10 mils 31
+MIC1_VREFO_L MIC1-VREFO-L
1U_0603_10V4Z
0.1U_0402_16V4Z
43 26 2 1
PVSS2 AVSS1
CA1290
CA1291
HDA_SYNC_AUDIO HDA_SDOUT_AUDIO
2 2 7 37
DVSS AVSS2
CA1278 @ CA1285 49 1 2
10P_0402_50V8J 10P_0402_50V8J Thermal PAD
1 1
Close to UA8.Pin27
ALC269Q-VC2-GR_QFN48_6X6 AGND
@ 2 RA1635 1 HDA_BITCLK_AUDIO
1 0_0402_5%
@ CA1282
22P_0402_50V8J~N
2
@ RA2
10K_0402_5%
0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/03/09 Title
HD Audio ALC269Q-VC3
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DGND AGND AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 42 of 65
A B C D E F G H
A B C D E F G H
B+ B+_PVDD
2 LA57
22U_1210_25V6K~D
22U_1210_25V6K~D
22U_1210_25V6K~D
1 B+_PVDD B+ = 19V
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0_0603_5%
1A, W=40 mils 2 2 2 1 1
1
CA1369
CA1370
CA1371
CA1372
CA1373
CA1374
CA1375
CA1376
@ @ @ @ @
CA1
CA2
CA3
1 C40 C41 1
1U_0603_25V6 1U_0603_25V6
2
1 1 1 2 2
+5VS
C42
1 2
1U_0402_6.3V4Z U73
B+_PVDD
4 5 GAIN1 GAIN SETTING
21 VS G1 6 GAIN2
22 PVDD G2 W=30 mils
PVDD GAIN1
One channel analog input
3 SPKOUT_L1+ LA56 2 1 0_0603_5% SPK_L1 GAIN2
OUTL+
SPKOUT_L1 C43 1 2 1U_0402_6.3V4Z 8 1 SPKOUT_L2- LA58 2 1 0_0603_5% SPK_L2
<42> SPKOUT_L1 INL+ OUTL-
1
2
SPKOUT_R1 C44 1 2 1U_0402_6.3V4Z 12 OUTL-
+5VS <42> SPKOUT_R1 INR+ 17 SPKOUT_R2- LA61 2 1 0_0603_5% SPK_R2 R895 R890@
9 OUTR- 18 0_0402_5% 0_0402_5%
1 INL- OUTR-
1
C46
2
R899 C45 1 2 11 16 SPKOUT_R1+ LA60 2 1 0_0603_5% SPK_R1
1U_0402_6.3V4Z INR- OUTR+
0_0402_5%
2 2 1U_0402_6.3V4Z Add JUMP for layout route 2
@
2
7
LIM_TH 10
GND
1
13
TEMPLOCK PGND
19 GAIN1 GAIN2 GAIN
R898 20
PGND 23
0_0402_5% @ 9
+3VALW
2 1 AMP OFF# 15 PGND 24 GND GND
SHUTDOWN PGND
R1407 10K_0402_5%
2
2 14 RELEASE EP
25 * NC GND 13
Change BOM structure to @ C47
for leakage 1U_0402_6.3V4Z GND NC 20.1
1 MAX98400BETGLFT_TQFN-EP24_4X4
NC NC 23.3
3 R959 1 2 0_0402_5% 3
SPK_R1 @CA9
@ CA9 1 2 1000P_0402_50V7K~N
+3VS Speaker Conn.
SPK_R2 CA10 1
@CA10
@ 2 1000P_0402_50V7K~N
JSPK1 ME@
2 SPK_L1 CA11 1
@CA11
@ 2 1000P_0402_50V7K~N SPK_L1 1
@ C1064 SPK_L2 2 1
0.1U_0402_10V7K SPK_L2 CA12 1
@CA12
@ 2 1000P_0402_50V7K~N SPK_R1 3 2
SPK_R2 4 3
4
5
1 5
2009/11/02 Modify G5
EC_MUTE# 1 6
P
U74 @
3
2
SN74AHC1G08DCKR_SC70-5
3
D62 @ D61 @
AZ5125-02S.R7G_SOT23-3 AZ5125-02S.R7G_SOT23-3
@
1 2
R958 0_0402_5%
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP-MAX98400BETG+T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 43 of 65
A B C D E F G H
5 4 3 2 1
R1458
2 1
+3VS +3VS_CARD
0_0603_5%
close to JREAD1 pin 9 @
MDIO5_R R1459 2 @ 1 C1023 1 2
Power
44 9 PCIE_PTX_C_DRX_N4
PCIE
18 DV33 APRXN 8 PCIE_PTX_C_DRX_N4 <15>
+1.8VS_CARD PCIE_PTX_C_DRX_P4
DV18 APRXP PCIE_PTX_C_DRX_P4 <15>
37 11 PCIE_PRX_C_DTX_N4 C1026 1 2 .1U_0402_16V7K PCIE_PRX_DTX_N4 Close to connector for EMI request.
1 2 43 DV18 APTXN 12 PCIE_PRX_DTX_N4 <15>
PCIE_PRX_C_DTX_P4 C1028 1 2 .1U_0402_16V7K PCIE_PRX_DTX_P4
SDDV33_18 APTXP PCIE_PRX_DTX_P4 <15>
C1027 W=20mils
2.2U_0603_6.3V6K
Please close to pin43 +CRD_POWER
48 MDIO0
MDIO0 47 MDIO1
MDIO1
System
1 46 MDIO2 (40mil)
Card Reader
6> PLT_RST# 2 XRSTN MDIO2 45 MDIO3 +CRD_POWER
13 XTEST MDIO3 41 MDIO4
CPPE_N MDIO4 800mA
21 42 MDIO5 1 2 R1463 MDIO5_R 1 2 R1464 MDIO5_RR
17 CR1_LEDN MDIO5 24 MDIO6 0_0402_5% 0_0402_5% JREAD1 ME@
+CRD_POWER CR1_PCTLN MIDO6 1 (40mil)
SD_CD# 16 40 MDIO7 C1029 22 11
MS_CD# 15 CR1_CD0N/WAKEN MDIO7 29 MDIO8 XD-VCC SD4-VDD 18
CR1_CD1N MDIO8 1 MS9-VCC
XD_CD# 14 28 MDIO9 10U_0805_10V6K MDIO0 30 (40mil)
33 CR2_CD2N MDIO9 27 MDIO10 C1031 2 MDIO1 29 XD10-D0 9 MDIO5_R
C
34 SPI_CSN MDIO10 26 MDIO11
Close to CONN. MDIO2 28 XD11-D1 SD5-CLK 4 MDIO0
C
@ 22P_0402_50V8J
35 SPI_SO MDIO11 25 2 27 XD12-D2 SD7-DAT0 3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
MDIO12 1 MDIO3 MDIO1 1 1
30 SPI_SI MDIO12 23 MDIO13 MDIO8 26 XD13-D3 SD8-DAT1 21 MDIO2
SPI_SCK MDIO13 XD14-D4 SD9-DAT2
C1030
C1032
C1033
39 22 MDIO14 MDIO9 25 19 MDIO3
TXIN MDIO14 MDIO10 24 XD15-D5 SD1-DAT3 16 MDIO4
2 MDIO11 23 XD16-D6 SD2-CMD 1 SD_CD# 2 2
XD17-D7 SD-CD 2 MDIO6
MDIO4 33 SD-WP
MDIO6 32 XD07-WE 6
6 MDIO14 34 XD08-WP SD6-VSS 13
31 APGND XD_CD# 39 XD06-ALE SD3-VSS
GND XD01-CD
GND
32 MDIO13 38
38 GND MDIO12 37 XD02-R/B
GND MDIO5_RR 36 XD03-RE 17 MDIO5_R
MDIO7 35 XD04-CE MS8-SCLK 10 MDIO0
JMB389-LGAZ0C_LQFP48_7X7 XD05-CLE MS4-DATA0 8 MDIO1
31 MS3-DATA1 12 MDIO2
40 XD GND MS5-DATA2 15 MDIO3
XD GND MS7-DATA3 14 MS_CD#
MS6-INS 7 MDIO4
MS2-BS 5
41 MS1-VSS 20
+1.8VS_CARD 42 SD CD/WP GND MS10-VSS
SD CD/WP GND
B B
T-SOL_144-1313002600_40P_NR-T
+3VS_CARD
10U_0805_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1
C1034
C1036
C1037
+1.8VS_CARD
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 2 2
1 1 1 1
C1038
C1039
C1040
C1041
2 2 2 2
@ @ 1
Close to pin10 C1042 1
C1043
Close to pin5->1000P->0.1u->10u 0.1U_0402_16V4Z
2 10U_0805_10V6K
2
XD_CD#
Close to pin 19,20 Close to pin 36 Close to pin 37 Close to pin 18
Close to pin 44
SD_CD# +CRD_POWER
A A
1 1
C1044 C1045
MDIO6 1 R1465 2
0.1U_0402_16V4Z
@ 2
0.1U_0402_16V4Z
@ 2
1K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2010/11/11 Title
MDIO13 1 R1466 2
1K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card reader JMB389
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 44 of 65
5 4 3 2 1
1 2 +3VALW
R1524 0_0603_5%
1 @ 2 +3VL +3VS
R1525 0_0603_5%
close EC For S3.5
EC_SCI#/ EC_SMI# pull up to PCH C1082
1
0.1U_0402_16V4Z
C1075
1 2 VCOREVCC All capacitors close to EC +3VALW_EC
+3VALW_R +3VALW_R
L80 2
D70 2 1 EC_SMI#_R .1U_0402_16V7K 1 2
<19> EC_SMI# +3VALW_R
RB751V-40_SOD323-2 BLM18PG181SN1D_0603 1
D71 2 1
1 EC_SCI#_R C1072 C1073
0.1U_0402_16V4Z
C1076
0.1U_0402_16V4Z
C1077
0.1U_0402_16V4Z
C1078
0.1U_0402_16V4Z
C1079
0.1U_0402_16V4Z
C1080
0.1U_0402_16V4Z
C1081
<19> EC_SCI# RB751V-40_SOD323-2 1 1 1 1 1 1 0.1U_0402_16V4Z 1000P_0402_50V7K
@ +3VS +3VALW_EC L81 2
1 2 ECAGND 2
+RTCBATT R1519 2 1
2 2 2 2 2 2 BLM18PG181SN1D_0603
0_0402_5%
R1520 2 1
0_0402_5%
114
121
127
12
11
18
26
50
92
74
3
U70
VBAT/VCC
VCORE/VCC
VCC/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
AVCC
+3VALW +3VL
KBRST# 4 24
<19> KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED# <47>
pull up to PCH
1
SERIRQ 5 25 BATT_CHG_LED#
<14> SERIRQ SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# <47>
LPC_FRAME# 6 28 BATT_LOW_LED# R1529 R1530
<14,37> LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# <47>
LPC_AD3 LED_KB_PWM 0_0603_5% @ 0_0603_5%
<14,37> LPC_AD3 LAD3/GPM3 PWM3/GPA3 LED_KB_PWM <46>
LPC_AD2 8 PWM PWM4/GPA4 30 SLI_FAN_PWM For 2nd fan
<14,37> LPC_AD2 9 LAD2/GPM2 31 SLI_FAN_PWM <32,41>
LPC_AD1 EC_FAN_PWM For fan
<14,37> LPC_AD1 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM <40>
2
LPC_AD0 10 32 BEEP# For EC beep
+3VALW <14,37> LPC_AD0 LAD0/GPM0 PWM6/SSCK/GPA6 BEEP# <42>
13 LPC 34 EC_INVT_PWM EC_SMB_CK1 2 1
1 2 <18> CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 EC_INVT_PWM <34>
WRST# ACIN R1417 2.2K_0402_5%
WRST# TMRI0/WUI2/GPC4 ACIN <62>
R1404 100K_0402_5% EC_SMI#_R 15 124 VGA_AC_DET
+3VL 16 ECSMI#/GPD4 TMRI1/WUI3/GPC6 VGA_AC_DET <23,32,58>
BATT_LEN# EC_SMB_DA1 2 1
1 <53> BATT_LEN# PWUREQ#/BBO/SMCLK2ALT/GPC7
1 @ 2 17 66 VGA_IMON VGA_IMON <58> R1424 2.2K_0402_5%
22 NC ADC0/GPI0 67
R1405 100K_0402_5% <18,23,32,37,38,44,6> PLT_RST# LPCRST#/WUI4/GPD2 ADC1/GPI1 SA_PGOOD <56>
For S3.5 C999 EC_SCI#_R 23 68 BATT_TEMP +3VS
2 ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP <53>
1U_0402_6.3V6K GATEA20 126 ADC 69 +3VALW
<19> GATEA20 GA20/GPB5 ADC3/GPI3 70 IMVP_IMON <59> OPT@
LAN_WAKE# R1532 1 2 100K_0402_5% EC_FAN_SPEED 2 1
ADC4/WUI28/GPI4 71
ADC5/DCD1#/WUI29/GPI5 ADP_I <53,62> R1431 10K_0402_5%
72 AD_ID R1533 1 SLI@ 2 100K_0402_5%
ADC6/DSR1#/WUI30/GPI6 73 LID_SW#
ADC7/CTS1#/WUI31/GPI7 LID_SW# <46> SLI_FAN_SPEED 2 1
KSI0 58 for power adapter ID R1485 10K_0402_5%
KSI1 59 KSI0/STB# 78
SUSWARN# <16> 3V--- 90W OPT,35W --> R1532
KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 +3VS
KSO[0..15] AC_PRESENT <16> 1.5V--- 120W OPT,45W --> R1532, R1533
KSI3 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80
<46> KSO[0..15] KSI3/SLIN# DAC DAC4/DCD0#/GPJ4 DRAMRST_CNTRL_EC <7> 0V--- 170W SLI --> R1533
KSI[0..7] KSI4 62 81 EC_WL_OFF# TP_CLK 1 2
KSI4 DAC5/RIG0#/GPJ5 EC_WL_OFF# <37>
<46> KSI[0..7] KSI5 63 R1410 4.7K_0402_5%
KSI6 64 KSI5 85 USB_CH#
KSI6 PS2CLK0/TMB0/GPF0 USB_CH# <49>
KSI7 65 PS2 86 TP_DATA 1 2
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# <16>
KSO0 36 87 PM_SLP_SUS# <16,51> R1412 4.7K_0402_5%
KSO1 37 KSO0/PD0 PS2CLK1/DTR0#/GPF2 88 SUSACK#
KSO1/PD1 Int. K/B PS2DAT1/RTS0#/GPF3 SUSACK# <16> +3VS
KSO2 38 89 TP_CLK
Matrix TP_CLK <46>
1
KSO13 53 105 R1482 10K_0402_5%
Reserved SMBus channel 0 for debugging KSO14 54 KSO13 GPG7 CMOS_ON# <34>
KSO14 R1433
KSO15 55 10K_0402_5% @ USB_ON# 1 2
EC_SMB_CK1 56 KSO15 108 EC_RX
<49,53,62> EC_SMB_CK1 EC_RX <37> R1409 10K_0402_5%
EC_SMB_DA1 57 KSO16/SMOSI/GPC3 RXD/SIN0/GPB0 109 EC_TX
<49,53,62> EC_SMB_DA1 KSO17/SMISO/GPC5 UART TXD/SOUT0/GPB1 EC_TX <37>
2
EC_SMB_CK2 110 82 SYSON
<15,23,32,40> EC_SMB_CK2 111 SMCLK0/GPB3 EGAD/WUI25/GPE1 83 SYSON <55>
EC_SMB_DA2 SM Bus SUSP# +3VS
<15,23,32,40> EC_SMB_DA2 SMDAT0/GPB4 EGCS#/WUI26/GPE2 SUSP# <32,51,55,57,58>
Please place R1435 close to EC within 790mil EC_SMB_CK1 115 84 @ R1402
116 SMCLK1/GPC1 EGCLK/WUI27/GPE3 VR_ON <59>
EC_SMB_DA1 EC_FAN_PWM 2 1
H_PECI 43_0402_1% 2 1 R1435 PECI_EC 117 SMDAT1/GPC2 77
<6> H_PECI SMCLK2/PECI/WUI22/GPF6 GPJ1 EC_MUTE# <43> 10K_0402_5%
LAN_PWR_ON# 118 100 ENBKL ENBKL <34>
<38> LAN_PWR_ON# 94 SMDAT2/PECIRQT#/WUI23/GPF7 SSCE0#/GPG2 106
GPIO SSCE1#/GPG0 H_PROCHOT#_EC R1429 2 @ 1 0_0402_5%
<16> PM_SLP_S3# WUI17/CRX1/SIN1/SMCLK3/GPH1/ID1 PROCHOT <53> +3VS
<16> PM_SLP_S4# 95 104
WUI18/CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 ME_FLASH <14>
EC_ON
DTR1#/SBUSY/GPG1/ID7 EC_ON <50,54>
119 BKOFF# R1521
CRX0/GPC0 BKOFF# <34>
112 123 AOAC_ON LPC_FRAME# 1 2
<16> EC_RSMRST# 125 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 CTX0/TMA0/GPB2 AOAC_ON <51>
<50> ON/OFF PWRSW/GPE4
WAKE UP 10K_0402_5%
76 A_DET#
TACH2/GPJ0 A_DET# <49>
48 SLI_FAN_SPEED
TACH1A/TMA1/GPD7 SLI_FAN_SPEED <32,41>
NOVO# 19 47 EC_FAN_SPEED
<50> NOVO# 33 BAO/WUI24/GPE0 TACH0A/GPD6 EC_FAN_SPEED <40>
USB_ON#
<48,49> USB_ON# GINT/CTS0#/GPD5
35 GPIO
<16> DPWROK_EC 93 RTS1#/WUI5/GPE5
NUM_LED# only for Y590 CLKRUN#/WUI16/GPH0/ID0
VR_HOT# 1 R1427 2 H_PROCHOT# <53,6>
<59> VR_HOT#
0_0402_5%
EC_LID_OUT# 2
<19> EC_LID_OUT# CK32KE/GPJ7
1
128 Clock D
CK32K/GPJ6
H_PROCHOT#_EC 2 1
R1539 1 2 ECR_EN_R G
<34> ECR_EN
AVSS/AGND
3
2N7002H_SOT23-3 47P_0402_50V8J
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
1
R1540 1 @ 2 2
<10> CPU1.5V_S3_GATE
0_0402_5% R1102
100K_0402_5%
For Deep S3
2
1
20
21
27
49
91
113
122
75
IT8580E-HX_LQFP128
ECAGND
1
1
SYSON ACIN 1 2
2
C1001 100P_0402_50V8J
100K_0402_5% 100K_0402_5%
R1434
C1007
0.1U_0402_10V6K
R1101 R1522
10K_0402_5%
2
1
2
@
1
2 LAN_WAKE#
LAN_WAKE# <38>
For factory EC flash
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC IT8580E
WRST# PAD IT8 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 45 of 65
5 4 3 2 1
0.1U_0402_10V6K
KSO15 C736 1 2 @ 100P_0402_50V8J KSO7 C737 1 2 @ 100P_0402_50V8J KSI6 3 4
3 4
C905
KSO9 4 2 5
KSO6 C738 1 2 @ 100P_0402_50V8J KSI2 C739 1 2 @ 100P_0402_50V8J KSI4 5 4 6 G1
KSI5 6 5 G2
KSO8 C740 1 2 @ 100P_0402_50V8J KSO5 C741 1 2 @ 100P_0402_50V8J KSO0 7 6 @ E&T_6906-Q04N-00R
KSI2 8 7 1 ME@
KSO13 C742 1 2 @ 100P_0402_50V8J KSI3 C743 1 2 @ 100P_0402_50V8J KSI3 9 8
KSO5 10 9
KSO12 C744 1 2 @ 100P_0402_50V8J KSO14 C745 1 2 @ 100P_0402_50V8J KSO1 11 10
KSI0 12 11
KSO11 C746 1 2 @ 100P_0402_50V8J KSI7 C747 1 2 @ 100P_0402_50V8J KSO2 13 12
KSO4 14 13
KSO10 C748 1 2 @ 100P_0402_50V8J KSI6 C749 1 2 @ 100P_0402_50V8J KSO7 15 14
KSO8 16 15 +5VS
KSO3 C750 1 2 @ 100P_0402_50V8J KSI5 C751 1 2 @ 100P_0402_50V8J KSO6 17 16 AO3413
KSO3 18 17 VGS= -4.5V, Id=-3A, Rds<97m ohm
KSO4 C752 1 2 @ 100P_0402_50V8J KSI4 C753 1 2 @ 100P_0402_50V8J KSO12 19 18 +VCC_KB_LED
KSO13 20 19 Q121 AO3413_SOT23-3
20
1
KSI0 C754 1 2 @ 100P_0402_50V8J KSO9 C755 1 2 @ 100P_0402_50V8J KSO14 21 KBL@
22 21 3 1
D
KSO11
KSO0 C756 1 2 @ 100P_0402_50V8J KSI1 C757 1 2 @ 100P_0402_50V8J KSO10 23 22 R1229
KSO15 24 23 10K_0402_5%
25 24 KBL@ 1 1 KBL@
G
KBL@ 2
0.01U_0402_25V7K
2
2
26 G1
CONN PIN define need double check G2 C1053 C1054 C908
0.1U_0402_16V4Z KBL@
ACES_85202-24051 2 2 0.1U_0402_16V4Z
ME@ 1 R1232 2 1
100K_0402_5%
C 1 C
KBL@
C907
@
1
D 0.01U_0402_16V7K
2
2 Q122
<45> LED_KB_PWM
G 2N7002_SOT23
1
S KBL@
3
R1480
100K_0402_5%
KBL@
2
To TP/B Conn.
JTP1 ME@
SMB_DATA_S3 1
<12,13,15,37> SMB_DATA_S3 SMB_CLK_S3 2 1
<12,13,15,37> SMB_CLK_S3 3 2
TP_DATA 4 3
<45> TP_DATA TP_CLK 5 4
B <45> TP_CLK
1
@
1
@
+3VS
6 5
6 Lid Switch B
2
5711ACDL-M3T1S SOT-23
D58
VDD
4 1
I/O3 I/O1 1
+3VALW 3
OUTPUT LID_SW# <45>
C758
0.1U_0402_16V4Z 2
GND
5 2 2
VDD GND
C759
U37 10P_0402_50V8J
1
1
6 3
I/O4 I/O2
AZC099-04S.R7G_SOT23-6
@
For ESD request
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 46 of 65
5 4 3 2 1
+3VALW +3VALW
BATT_LOW_LED#_R BATT_CHG_LED#_R
BATT CHARGE/LOW LED
1
R1562 R1558 White
@ @
10K_0402_1% 10K_0402_1%
6
D Q160A D Q158A LED2
Amber
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2 2
2 R1012 1 3
G G BATT_LOW_LED#_R
1 1 470_0402_5%
S S White 1
C1100 @ C1098 @ +5VALW
1
@ @
0.1U_0402_16V4Z 0.1U_0402_16V4Z R1014 1
3
@ D @ D BATT_CHG_LED#_R 2 2
5 2 5 2
<45> BATT_LOW_LED# <45> BATT_CHG_LED# 470_0402_5%
G G
Q160B Q158B 12-22-S2ST3D-C30-2C_WHI-ORG
S 2N7002KDWH_SOT363-6 S 2N7002KDWH_SOT363-6
4
1 R1564 2 1 R1561 2
0_0402_5% 0_0402_5%
+3VALW +5VS
PWR LED HDD LED CapsLK LED
@
PWR_LED#_R 1 R1491 2 HDD_LED#_R
+5VS
10K_0402_1% White
1
1
LED3
1 2 2 R1013 1
R1559 R1490 <50> PWR_LED#_R +5VALW
@ @
10K_0402_1% 10K_0402_1%
300_0402_5%
6
6
@ D Q159A @ D Q151A 12-21SYGCS530-E1S155TR8_W
2
2
2 2
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
G G
1 LED1
HDD_LED#_R 1 2 2 R1322 1
C1099 S S +5VS
1
1
@
0.1U_0402_16V4Z 300_0402_5%
3
D
3
@ D @ 12-21SYGCS530-E1S155TR8_W
5 2 5
<45> PWR_LED# <14> HDD_LED#
G G
Q159B Q151B LED4
2N7002KDWH_SOT363-6 1 2 2 R1323 1
S 2N7002KDWH_SOT363-6 S <45> CAPS_LED# +5VS
4
4
300_0402_5%
12-21SYGCS530-E1S155TR8_W
1 R1560 2 1 R1492 2 LED3 LED2 LED1 LED4
0_0402_5% 0_0402_5%
POWER BATTERY HDD CapsLK
Screw Hole
BlueTooth DC
+3VS +3VS_BT
CPU and GPU: H_3P8X 6 MIN PCIE: H_3P3 X 1
BT@ Q154 30mils
AO3413_SOT23-3
C: H_3P8X 3 B: H_3P8X 3 E: H_3P3X 1
3 1
S
1
1
BT@ 2 2 2
1 R1526 2
<19,37> PCH_BT_ON#
100K_0402_5%
CPU GPU
1
C1084
@ 0.1U_0402_16V4Z
2
BT Conn.
+3VS_BT
JBT1 ME@ ME: H_8P0 X 8; H_3P3X 1; H_4P0X3P0N X 2; H_2P0X 1
1
2 1
USB20_P13 3 2 A: H_2P8X 8
<18> USB20_P13 3
<18> USB20_N13 USB20_N13 4
4 H16 H22 H24 H25 H31 H33
H30 H32
5 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
6 GND
GND
ACES_50209-0040N-001
1
1
1
1
1
E: H_3P3X 1 H_4P0X3P0NX 3 H_2P0X 2
H29 H20 H21 H23
HOLEA HOLEA HOLEA HOLEA
1
1
1
PCB Fedical Mark PAD
FD1 FD2 FD3 FD4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/EC SPI ROM/BT
Size Document Number Rev
1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 47 of 65
A B C D E
+
2 1 2
C816 470P_0402_50V7K
JUSB1
For EMI request 1
USB20_N2 R1162 1 2 0_0402_5% USB20_N2_R 2 VBUS
USB2.0 choke --> SM070000I00 <18> USB20_N2 D-
USB20_P2 R1163 1 2 0_0402_5% USB20_P2_R 3
<18> USB20_P2 D+
@ 4
USB3.0 Choke --> SM070001U00 USB30_RX_N3 R1154 1 @ 2 0_0402_5% USB30_RX_R_N3 5 GND_1
<18> USB30_RX_N3 SSRX-
USB30_RX_P3 R1155 1 2 0_0402_5% USB30_RX_R_P3 6 13
<18> USB30_RX_P3 SSRX+ GND_6
@ 7 12
USB30_TX_N3 C300 1 2 0.1U_0402_10V6K USB30_TX_C_N3 R1156 1 @ 2 0_0402_5% USB30_TX_R_N3 8 GND_2 GND_5 11
<18> USB30_TX_N3 SSTX- GND_4
USB30_TX_P3 C299 1 2 0.1U_0402_10V6K USB30_TX_C_P3 R1157 1 2 0_0402_5% USB30_TX_R_P3 9 10
L68 <18> USB30_TX_P3 SSTX+ GND_3
@
USB30_RX_N3 2 1 USB30_RX_R_N3 @ SANTA_370300-1
2 1
ME@
USB30_RX_P3 3 4 USB30_RX_R_P3
3 4
2 2
WCM-2012-900T_4P
L70
USB30_TX_C_N3 2 1 USB30_TX_R_N3
2 1
For ESD request
USB30_TX_C_P3 3 4 USB30_TX_R_P3
3 4 D27 D24
@ @
WCM-2012-900T_4P USB30_RX_R_N3 9 10 1 1USB30_RX_R_N3 USB20_N2_R 3 6
I/O2 I/O4
L72 USB30_RX_R_P3 8 9 2 2 USB30_RX_R_P3
USB20_N2 2 1 USB20_N2_R
2 1 USB30_TX_R_N3 7 4 USB30_TX_R_N3 2 5
7 4 +5VALW
GND VDD
USB20_P2 3 4 USB20_P2_R USB30_TX_R_P3 6 6 5 5 USB30_TX_R_P3
3 4
WCM-2012-900T_4P 3 3 1 4 USB20_P2_R
I/O1 I/O3
8
AZC099-04S.R7G_SOT23-6
YSCLAMP0524P_SLP2510P8-10-9
3 3
4 4
Security Classification Compal Secret Data For EMI request Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
USB3.0 ports
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 48 of 65
A B C D E
5 4 3 2 1
+5VALW +5V_CHGUSB
Active Mode Selection:
1U_0402_6.3V6K
0.1U_0402_16V4Z
1 2
C1093
M1 M2 EM_EN ACTIVE MODE
C1094
2 1
*0 0 1 Dedicated Charger Emulation Cycle
0 1 0 Date Pass-through
Del C1095 0 1 1 BC1.2 DCP
1 0 0 BC1.2 SDP
9
U8 1 0 1 Dedicated Charger Emulation Cycle
1 1 0 Date Pass-through
VDD
7 1 1 1 BC1.2 CDP
+5VALW VS1
1 1 3 R1587
VBUS1
10U_0603_6.3V6M
0.01U_0402_16V7K
8 4 10K_0402_5% +3VALW
VS2 VBUS2
C1096
C1097
1 @ 2
2 2 USB20_P5 14 17 USB20_P5_C R1583
<18> USB20_P5 DPIN DPOUT ILIM SETTING SEL Pin Decode
USB20_N5 15 16 USB20_N5_C 10K_0402_5%
<18> USB20_N5 DMIN DMOUT 1 2
USB_CH# 10 18 A_DET# Pull Low Pull Low
<45> USB_CH# PWR_EN A_DET# 13 A_DET# <45>
USB_OC2# OR-500mA 0R -1010_000
EM_EN 19 ALERT# 11 EC_SMB_DA1 USB_OC2# <18> 10K-900mA
EM_EN SMDATA/LATCH EC_SMB_DA1 <45,53,62> * 10K-1010_000
12 EC_SMB_CK1 12K-1000mA 12K-1010_000
1 SMCLK/S0 6 1 2 EC_SMB_CK1 <45,53,62>
CH_M1 CH_SEL 15K-1200mA 15K-1010_000
M1 SEL
GND FLAG
CH_M2 2 5 CH_ILIM 1 2 R1553 18K-1500mA 18K-0110_000
M2 COMM_SEL/ILIM R1555 10K_0402_5% 22K-1800mA 22K-0110_000
33K_0402_5% 27K-2000mA 27K-0110_000
GND
C C
@ * 33K-2500mA 33K-0110_000
R1551 1 2 EM_EN R1584 2 1
+5VALW
10K_0402_5% 10K_0402_5%
21
20
UCS1002-1-BP-TR_QFN20_4X4
1 @ 2 CH_M1 2 1
R1585 R1552
10K_0402_5% 10K_0402_5%
1 @ 2 2 1
R1586 CH_M2 R1554
10K_0402_5% 10K_0402_5%
need change to 霧霧
material
COMPAL : SP010015W1J
Footprint : 88514-0240N-071
A A
RA1622 RA1623
2.2K_0402_5% 2.2K_0402_5%
2
TOP Side 2 4
R1116 R1117
SMT1-05_4P 100K_0402_5% @ 100K_0402_5%
6
5
J7
1
Bottom Side 1 2 1 @ 2 For S3.5
R1531 0_0603_5% +5VALW
SHORT PADS JPW R1 ME@
@ D72 1
2 1
3 ON/OFF 2
ON/OFF <45> NOVO_BTN# 3
ON/OFFBTN# 1 3
2 51_ON# <47> PW R_LED#_R 4
51_ON# <52> ON/OFFBTN# 5 4
6 5
DAN202UT106_SC70-3 6
1
D
@ 1 7
EC_ON 2 C551 8 GND
<45,54> EC_ON GND
G
2
3
R1523 2N7002_SOT23-3 2
10K_0402_5%
9/23 ESD Request
1
+3VALW +3VL
2
2
R1119
R1118 @ 100K_0402_5%
100K_0402_5%
1
1
For S3.5
D56
NOVO# 2
<45> NOVO#
1 NOVO_BTN#
51_ON# 1 2 3
R19 0_0402_5%
ON/OFF 1 @ 2 DAN202UT106_SC70-3
EMI REQUEST 1ST = SCA00000E00
R28 0_0402_5%
For S3.5 2ST = SCA00000R00
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
other IO connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 50 of 65
A B C D E
D
1
1 7 2 1 1 1 7 2 1 1 1 1
1 6 3 6 3 C856 Q120 1
5 5 C857 C835
C837 C838 C840 C841 10U_0805_10V6K
G
10U_0603_6.3V6M 1U_0603_10V4Z
2
C836 10U_0603_6.3V6M 1U_0603_10V4Z C839 10U_0603_6.3V6M 1U_0603_10V4Z 2 SI2301BDS-T1-E3_SOT23-3
1
2 10U_0805_10V6K AP4800BGM-HF 2 2 2 10U_0805_10V6K AP4800BGM-HF 2 2 2 2
4
4
R1474 +3VALW
R1475 @
@ 470_0603_5%
1
470_0603_5%
1
2
2
R1481
@
R1087 470_0603_5%
100K_0402_5%
R1088 2 R1085 1 R1089 2 R1086
2
5VS_GATE_R 1 5VS_GATE 3VS_GATE_R 2 3VS_GATE 1
+VSB +VSB R1090 1
2
2 1.5VS_GATE
82K_0402_5% 150K_0402_5% 0_0402_5% 470K_0402_5%
1 1 0_0402_5% 1
1
3
C842 D D C843 D D D D
0.01U_0402_25V7K 2 5
SUSP 0.01U_0402_25V7K 2 SUSP 5 SUSP# 2 C845 1.5VS_GATE 5
R1484 G G R1483 G G G G
@ @ .1U_0402_16V7K
2 820K_0402_5% 2 820K_0402_5% 2
Q99A Q99B Q100A Q100B Q101A
S 2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6 Q101B S
2
4
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6
1
R1120 1 2 1 2
DS3@
100K_0402_5% 1 2 1 2
1 1 R1097 R1094
2 C38 @ C39 @ 100K_0402_5% 22_0603_5% 2
JUMP_43X79 JUMP_43X79
2
2
100K_0402_5% SUSP
D DS3@ <10,37,55,57> SUSP
1
2 2
PCH_PWR_EN R117 1 DS3@ 2 2 Q118 Q148 Q149
<45> PCH_PWR_EN
3
0_0402_5% G 2N7002_SOT23 AO3413_SOT23 AO3413_SOT23 D D
S 2 5 SUSP
<32,45,55,57,58> SUSP#
3
1
PM_SLP_SUS# R1448 2 1 3 1 3 1
D
@ 1. C38, C39 resistance change to 0.1u_0402 G G
<16,45> PM_SLP_SUS# 2. and the BOM structure as "@" for discharge
0_0402_5% Q107B
R1121 DS3@ 1 DS3@ 1 1 DS3@ 1 Q107A S S 2N7002KDWH_SOT363-6
4
100K_0402_5% 2N7002KDWH_SOT363-6
G
C1065 C1067
2
DS3@ DS3@ C1066 DS3@ DS3@ C1068
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2
PCH_PWR_EN#_R PCH_PWR_EN#_R
+5VALW
R1122 Q145
1
AOAC@
100K_0402_5%
AO3413_SOT23
R6 +5VALW
@
100K_0402_5%
2
3 1
D
AOAC_ON#
<37> AOAC_ON#
D AOAC@ 1 1
2
1
1
AOAC@ 2 <57> 0.75VR_EN# C1058 C1059
1
AOAC_ON R1453 1 2 Q119
G
<45> AOAC_ON R1449 0.1U_0402_16V4Z 0.01U_0402_25V7K 2
2
3
0_0402_5% G 2N7002_SOT23 D@
2 R8 @ 1 0.75VR_EN 5 47K_0402_5% 2 2
S <56,57> +V1.05S_VCCP_PWRGOOD R1450 @ C37
3
1
G 470_0603_5% 10U_0603_6.3V6M
100K_0402_5%
2
3 Q144B 1 3
R1451 2
2
6
R1123 AOAC@ D@ 1
S <25> DGPU_PWR_EN#
4
100K_0402_5% 2 SUSP 2N7002KDWH_SOT363-6
G 100K_0402_5%
Q144A 1
2
3
D C1011 D
2N7002KDWH_SOT363-6 2 R1452 1 2 DGPU_PWR_EN# 5
S 0.1U_0402_10V7K @
<18,23> DGPU_PWR_EN
1
G G
0_0402_5% 2
Q146A Q146B
1
S 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 S
4
R1454
100K_0402_5%
For S3 CPU Power Saving
2
+3VS +3VS_SLI
+3VS to +3VS_SLI
Q147
AO3413_SOT23
+5VALW
3 1
S
1 1
1
C1062 C1063
1
G
4 1 4
R1513 2
2
1
<32> S_DGPU_PWR_EN#
100K_0402_5%
1
6
D C1012 D
2 R1503 1 2 S_DGPU_PWR_EN# 5
0.1U_0402_10V7K @
<19,32> S_DGPU_PWR_EN G G
0_0402_5% 2
Security Classification Compal Secret Data Compal Electronics, Inc.
1
S Q150A Q150B S
1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 51 of 65
A B C D E
5 4 3 2 1
DC030006J00 VIN
PF1 PL1
12A_65V_451012MRL SMB3025500YA_2P
4 APDIN 1 2 APDIN1 1 2
4
3
3
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
2
2
1
D 1 D
1
2
@ 4602-Q04C-09R 4P P2.5
PC1
PC2
PC3
PC4
JDCIN1
VIN
LL4148_LL34-2
2
PD1
PD2
1
C LL4148_LL34-2 PJ1 51ON-1 C
BATT+ 2 1 @ JUMP_43X39
1
68_1206_5%
68_1206_5%
1 2
1 2
PR1
PR2
PQ1
PR3 @ TP0610K-T1-E3_SOT23-3
2
200_0402_1%
1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
1
100K_0402_1%
0.1U_0603_25V7K
2
1
PR4
PC5
PC6
1
PR5 2
2
22K_0402_1%
1 2 51ON-3
+3VLP
<50> 51_ON#
- JRTC1 + PR6
560_0603_5%
PR7
560_0603_5%
PD3
2 1 1 2 1 2 2 1
+RTCBATT
RB751V-40_SOD323-2
2
0_0402_5%
@ MAXEL_ML1220T10 1 2 +CHGRTC
+CHGRTC
PR8
PD4
@ PU1 PR9 RB751V-40_SOD323-2
@ 200_0603_5%
RTC Battery
1
APL5156-33DI-TRL_SOT89-3
3.3V
2
3 2 CHGRTCIN
B VOUT VIN B
1
GND PC8
PC7 1U_0805_25V6K
10U_0603_6.3V6M 1
@
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 52 of 65
5 4 3 2 1
5 4 3 2 1
VMB2 VMB
PF2 PL2
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5
1
D 6 D
6
1
7 PC9 PC10
7
100_0402_1%
100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K
2
GND 9
GND PR10
PR11
TYCO_1775789-1
2
2
@
0.1U_0603_25V7K
6.49K_0402_1%
<BOM Structure> <45,62> ADP_I PR205
2
4.42K_0402_1%
13.7K_0402_1%
21.5K_0402_1%
PC11
4.42K:90W
1
1 2
BATT_TEMP A/D
<45>
9.1K:120W
PR15
PR16
PR17
PR14 @
2
10K_0402_5%
<BOM Structure> +3VS 16.5K:170W
1
PU2
2
1 8
VCC TMSNS1
100K_0402_1%
C 2 7 OTP_N_002 2 1 C
GND RHYST1 PR19
100K_0402_1%_NCP15WF104F03RC
1
PR18
PH1
3 6 Turbo_V 10K_0402_1%
<45,6> H_PROCHOT# OT1 TMSNS2
4 5 ADP_OCP_2 1 2
1
OT2 RHYST2
2
D
10K_0402_1%
G718TM1U_SOT23-8 PR20
2
PR21
PQ3 2 ADP_OCP_1 57.6K_0402_1%
OTP_N_003
2N7002KW_SOT323-3 G
S
PR210
1
PR22 @
0_0402_5% PR23
57.6K:90W
<45> PROCHOT 1 2 2 1
MAINPWON 82.5K:120W
<54>
0_0402_5% 76.8K:170W
B B
P2
PQ4
+3VALW +3VALW
0.01U_0402_25V7K
TP0610K-T1-E3_SOT23-3
1
100K_0402_1%
100K_0402_1%
PC12
3 1
B+ +VSBP
2
VMB2
100K_0402_1%
PR24
PR25
0.22U_0603_25V7K
2
1
PR26
PC13
PR27 PR28
2
1 2 0.1U_0603_25V7K
BATT_OUT <62>
2
PR29 PQ5
2
10K_0402_1% 2N7002KW_SOT323-3 PR30
8
1 2 VL 22K_0402_1%
1
3 D 1 2
P
+ 1 2
O
2
PR31 2 G
-
G
2
AS393MTR-E1 SO 8P OP 100K_0402_1%
4
1K_0402_1% D PJ2
1
1 2 2 2N7002KW_SOT323-3 @ JUMP_43X39
<54> SPOK
100K_0402_1%
2 1 G 1 2
+CHGRTC +VSBP 1 2 +VSB
2
1U_0402_6.3V6K
S
3
1
PR35
PC15
PR34 @
10K_0402_1%
2
2 1
2VREF_8205
1
A PQ7 A
PR37
1
PR36 D 2N7002KW_SOT323-3
10K_0402_1% 2 1 2
<45> BATT_LEN#
G
10K_0402_1% S
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN/OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 53 of 65
5 4 3 2 1
5 4 3 2 1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205 PJ3
+3VALW P 2 1 +3VALW
2 1
@ JUMP_43X118
1U_0603_10V6K
D D
1
PJ4
PC16
+5VALW P 2 1 +5VALW
2
2 1
@ JUMP_43X118
PR38 PR39
13K_0402_1% 30K_0402_1%
1 2 1 2
PR40 PR41
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
PJ5 Typ: 175mA
B+ 2 1 +3VLP
0.1U_0603_25V7K
2 1
ENTRIP2
ENTRIP1
@ JUMP_43X118 @ PR55 PR43 PR42
PC22
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
PC26
+3VL
1
1
PC18
PC19
PC20
PC21
PC23
PC25
2
8
7
6
5
5
6
7
8
PU4
4.7U_0805_10V6K
2
2
PQ9
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
C PQ8 AO4406AL_SO8 C
25
AO4466L_SO8 P PAD
PC24
2
4 4
7 24
VO2 VO1 SPOK <53>
8 23 PR45 PC28
PR44 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3
3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
2.2_0603_5% BOOT2 BOOT1
PL3 PC27 UG_3V 10
VFB=2.0V 21 UG_5V PL4
3.3UH +-20% PCMC063T-3R3MN 6A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_VMPI1004AR-4R7M-Z01_10A_20% +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
1
8
7
6
5
1
LG_3V 12 19 LG_5V
4.7_1206_5%
4.7_1206_5%
LGATE2 LGATE1
5
6
7
8
PQ10
PR46
PR47
SKIPSEL
AO4712_SO8 PQ11
VREG5
2012/02/29
GND
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
VIN
RT8205LZQW _W QFN24_4X4
NC
EN
1 1
150U_B2_6.3VM_R35M
2
change PC29, PC32, 4
@ 1U_0603_10V6K
1
1
4 + +
PC31
PC32
PC34
PC34 from
13
14
15
16
17
18
1
1
+ PR48
PC29
PC30
680P_0603_50V7K
SGA00001E0J to 499K_0402_1%
680P_0603_50V7K
2
1 2 2 2
PC33
2
1
2
3
2
SGA00002N8J 2 AO4456_SO8
B+
3
2
1
1
100K_0402_1%
1U_0603_10V6K
VL
1
PC35
1
PR49
PC36
Typ: 175mA
4.7U_0805_10V6K
B B
2
ENTRIP1 ENTRIP2
2
2
PQ12B RT8205_B+
6
2N7002KDW -2N_SOT363-6
PR50
PQ12A 0_0402_5% RT8205
0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2 1
2VREF_8205 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
PC37
PR52 @ (2)SMPS2=375KHZ(+3VALWP)
1
2
0_0402_5% 2 1 TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
<53> MAINPW ON 2 1 VL
PR54 @ (2)SMPS2=305KHZ(+3VALWP)
PR53 0_0402_5%
100K_0402_1% 2 1
2 1
VL
@ PR185
<45,50> EC_ON 0_0402_5% +3.3VALWP Imax=7.5A ; Ipeak=9A +5VALWP Imax=11.1A ; Ipeak=13.32A
2 1
1/2 Delta I=1.113A (F=375K Hz) 1/2 Delta I=1.33A (F=300K Hz)
1
Vtrip=0.169V Vtrip=0.098V
PQ14
PR56 2N7002KW _SOT323-3
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Rds(on)=7.0m ohm(max) ; Rds(on)=5.1m ohm(typical)
D
1
2.2U_0603_10V6K
3
A A
1
100K_0402_1%
1
1
PR58
PC38
3
2
2
EC_ON 2
PQ15
DTC115EUA_SC70-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/12/31 Title
3VALWP/5VALWP
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 54 of 65
5 4 3 2 1
A B C D
PJ6
1.5V_B+ 2
2 1
1 B+
Freq= 266~314KHz , 290KHz(typ)
470P_0603_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5
6
7
8
@ JUMP_43X118
1
PC39
PC40
PC41
PC42
PC43
PQ16 <BOM Structure>
Iocp=13.58A~23.10A AO4406AL_SO8
2
4
PR59
0_0402_5%
1 2
<45> SYSON
3
2
1
2
47K_0402_5%
PR61 PC45 PL5
.1U_0402_16V7K
1 1
PC44 @
PR60
PU5 2.2_0603_5% 0.22U_0603_16V7K S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A
+1.5VP
1
1 10 BST_1.5V 1 2BST_1.5V-1 1 2 1 2
PGOOD VBST
2 9 DH_1.5V
2
TRIP DRVH
3 8 LX_1.5V
4.7_1206_5%
220U_B2_6.3VM_R15M
EN SW
PR62 @
1
5
6
7
8
4 7
VFB V5IN +5VALW +
PC46
PQ17
1
5 6 DL_1.5V
RF DRVL PC47
84.5K_0402_1%
2
1
11 1U_0603_10V6K 2
470K_0402_1%
2
TP
2
PR63
4
1000P_0603_50V7K
PC48 @
TPS51212DSCR_SON10_3X3 PJ7 +1.5V
1
PR64
VFB=0.7V +1.5VP 2 1
2 1
2
AO4456_SO8 @ JUMP_43X118
3
2
1
2
PR65
1 2
PJ8
11.5K_0402_1%
1.5VSP_VGA_B+ 2
2 1
1 B+
1
470P_0603_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5
@ JUMP_43X118
1
PC49
PC50
PC51
PC52
PC53
PR66 <BOM Structure>
PR67 10K_0402_1% PQ18
2
0_0402_5% 2
2
2
FBVDDQ_PWR_EN 1 2
4
PR68
@ 0_0402_5%
1 2
2,45,51,57,58> SUSP# MDV1525URH_PDFN33-8-5
3
2
1
2
PR69 @
47K_0402_5%
1 10 1
BST_1.5VSP_VGA 2BST_1.5VSP_VGA-1
1 2 1 2
PGOOD VBST
2 9 DH_1.5VSP_VGA
1
TRIP DRVH
3 8 LX_1.5VSP_VGA
4.7_1206_5%
220U_B2_6.3VM_R15M
EN SW
PR71 @
1
4 7
0.1U_0402_10V7K
VFB V5IN +5VALW
2
+
PC56
1
5 6 DL_1.5VSP_VGA PQ19
RF DRVL
PC58
75K_0402_1%
PC57
1
1
11 1U_0603_10V6K 2
470K_0402_1%
2
TP
2
PR72
1000P_0603_50V7K
PC59 @
TPS51212DSCR_SON10_3X3 4 PJ9 +1.5VS_VGA
1
PR73
VFB=0.7V +1.5VSP_VGA 2 1
2 1
2
@ JUMP_43X118
1
2
AON6504_POW ERDFN56-8-5
3
2
1
PR75
PR74
0_0402_5%
1 2 2 1
VDDQ_SENSE <25>
1
3 3
11.5K_0402_1%
Freq= 266~314KHz , 290KHz(typ) PR76
10K_0402_1% PJ10
2 1
+1.05VS +1.05VS_VGA
2
Iocp=12.25A~20.77A 2 1
@ JUMP_43X118
+1.05VS +1.05VS_VGA
8 PQ20 1
10U_0805_25V6K
+5VALW 7 2
@ 470K_0603_5%
1U_0603_10V6K
10U_0805_25V6K
2
+5VALW 6 3
1
PC60
PC61
PC62
PR77
1
2
1
PR78
1
10K_0402_1% PR79
100K_0402_1% AO4456_SO8 PR80 PQ21 @
2
1
@ 0_0402_5% D
PR81
2
1 2 2 2N7002KW _SOT323-3
PR82 1 2 <10,37,51,57> SUSP G
PQ22B
0_0402_5% S
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
3
1
<19,27,32,58> DGPU_PWROK 1 2
100K_0402_1%
PR84
3
6
PQ22A
PC63 @ 0_0402_5%
PR83 0.01u_0603_10V6K 1 2
2
@ 0_0402_5%
SUSP# 1 2 5 2
4
1
@ 1U_0603_10V6K
1
PC64
4 4
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP/1.5VSP_VGA/1.05VSP_VGA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 55 of 65
A B C D
5 4 3 2 1
+3VS PR85
1K_0402_1%
2 1
VID [0] VID[1] VCCSA Vout PJ11
+VCC_SAP
100K_0402_5%
0 0 0.9V H_VCCSA_VID1 <10> +VCCSAP 1 2 +VCCSA
1
TDC 4.2A
0 1 0.8V PAD-OPEN 4x4m
PR86
Peak Current 6A
1 0 0.725V OCP current 7.2A
2
H_VCCSA_VID0 <10>
1 1 0.675V
PR87
<45> SA_PGOOD
1K_0402_1%
output voltage adjustable network 2 1
D D
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
H_VCCSA_VID0
H_VCCSA_VID1
+5VALW
SA_PGOOD
VCCSA VID is 00 prior to VCCIO stability.
1U_0603_10V6K
2
PC65
PR88 PR89
10_0402_1% 0_0402_5%
1
2 1 +VCCSA_EN 1 2
+V1.05S_VCCP_PWRGOOD <51,57>
PC66
2.2U_0603_10V7K
1 2
18
17
16
15
14
13
PU7
PR90 PC67
VID1
VID0
PGOOD
EN
V5FILT
V5DRV
2.2_0603_5% 0.22U_0603_16V7K
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
19 BST PL7
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_10V7K
10
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2200P_0402_50V7K
SW
1
21
2200P_0402_50V7K
PC68 @ @ @ @
0.1U_0603_25V7K
PGND
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1000P_0603_50V7K
PC69
PC70
PC72
PC73
PC75
PC76
TPS51461RGER_QFN24_4X4 9
PC71
PC74
1 2
22 SW
PC78
1 2 2
1
VIN
2
PC77
PC79
PC80
8 PR91
23 SW 4.7_1206_5%
1
2 1 1 VIN
PJ12 7
+3VALW
2
2 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24 SW
2 1 VIN
C @ JUMP_43X118 25 C
COMP
MODE
TP
SLEW
VOUT
VREF
GND
1
6
@ PR92
2 1
33K_0402_5%
PC81 PR93
2 1 100_0402_5%
2 1
0.22U_0402_10V6K
0.01U_0402_25V7K
2
2 1 2 1
PR95
PC83
PC82 PR94 0_0402_5%
1
3300P_0402_50V7K 4.99K_0402_1% 2 1
+VCCSA_SENSE <10>
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VCCSAP/1.05S_VCCPP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 56 of 65
5 4 3 2 1
5 4 3 2 1
4
HCB1608KF-121T30_0603 1UH_PH041H-1R0MS_3.8A_20%
1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+5VALW
PG
PVIN LX +1.8VSP
9 3
68P_0402_50V8J
PVIN LX
1
680P_0603_50V7K 4.7_1206_5%
1
1
PC84 8
PC85
22U_0805_6.3VAM SVIN PR97
PR96
D D
6 20K_0402_1%
2
5 FB
22U_0805_6.3VAM
22U_0805_6.3VAM
1 2
2
EN
1
PJ13
NC
NC
TP
FB=0.6Volt +1.8VSP 2 1 +1.8VS
PC87
PC88
2 1
<32,45,51,55,58> SUSP# PR98
PC86
11
2
1 2 EN_1.8VSP @ JUMP_43X118
2
0_0402_5%
+1.5V
0.1U_0402_10V7K
2
PC89 @
1.8VSP_FB PJ14
1
PR99 +0.75VSP 2 1 +0.75VS
2 1
1
1M_0402_5%
1
@ JUMP_43X118
2
PJ15 PR100
1
1
JUMP_43X118 10K_0402_1%
@ PJ16
2
2
2 1
2 1
2
PU9 @ JUMP_43X118
1
VIN NC
8 +3VALW +1.05VS_VCCPP PJ17 +1.05VS
2 1
PC90 2 7 2 1
GND NC
1
4.7U_0805_6.3V6K @ JUMP_43X118
1
3 6 PC91
PR101 VREF VCNTL
2
PR102 1K_0402_1% 4 5 1U_0603_10V6K
@ 0_0402_5% VOUT NC
<51> 0.75VR_EN# 1 2 9
2
TP
C APL5336KAI-TRL_SOP8P8 C
PR103
0.1U_0402_16V4Z
D
+0.75VSP
1
47K_0402_1% PQ23
10U_0603_6.3V6M
<10,37,51,55> SUSP 1 2 2 2N7002KW _SOT323-3
PC95
1K_0402_1%
10U_0603_6.3V6M
1
1
PC93
PC94
PR104
G
2
S
0.1U_0402_10V7K
3
2012/02/29
2
1
PR105
0_0402_5%
SUSP# 1 2
@ 10K_0402_1%
+3VS
2
+1.05VS_VCCPP OCP(min)=22.38A
@.1U_0402_16V7K
1
PR106
PC97
100K_0402_1%
2
PJ18
100K_0402_1%
1
1.05VS_B+ 2 1
PR107
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2 1
B+
0.1U_0402_25V6
2
@ JUMP_43X118
PR109
1
PR108
PC99
PC102
<BOM Structure>
1
5
0_0402_5% PR110 PC103
PC98
PC101
1 2 0_0603_5% 0.1U_0603_25V7K PQ24
<51,56> +V1.05S_VCCP_PWRGOOD
2
1
BST_1.05VS_VCCP 2 1 2
1
B B
17
16
15
14
13
PU10 4
10.7K_0402_1%
PAD
PGOOD
EN
MODE
BST
2
AON6428L_DFN8-5
PR111
1 12 LX_1.05VS_VCCP PL10
0.1U_0402_25V6
3
2
1
VREF SW 1UH_PCMB062D-1R0MS_9A_20%
+1.05VS_VCCPP
1
1 2
1
PC100
2 11 DH_1.05VS_VCCP
2
REFIN DH
2
1
PQ25
PR112
1000P_0603_50V7K 4.7_1206_5%
5
PC104
12K_0402_1%
AON6504 1N DFN
TPS51219RTER_QFN16_3X3
PR113
0.01U_0402_25V7K 1
1
330U_D2_2VM_R6M
3 10 DL_1.05VS_VCCP
GSNS DL
PC105
+
1
2
4
4 9 2 3
VSNS V5 +5VALW
COMP
1
PGND
PC106
TRIP
GND
3
2
1
2
5
PC107
1
54.9K_0402_1%
PR114
2 PR115 1
1 2 PC108
<9> VCCIO_SENSE 1 2 1U_0603_10V6K
2
2
PR116 @
0.01U_0402_25V7K
0_0402_5%
A A
10_0402_1%
1000P_0402_50V7K
2
PC109
PR117
1
10_0402_1%
PC110
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VSP/0.75VSP/1.05VS_VCCPP
1000P_0402_50V7K Size Document Number Rev
1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 57 of 65
5 4 3 2 1
8 7 6 5 4 3 2 1
+VGA_B+ FBMA-L11-453215800LMA90T_2P
+VDD33MISC
@ @ @ 1 2
B+
PR118
PR119
PR120
PR121
PR122
PR123
PL11
1
2.2U_0402_6.3V6M
I_TDC=33.6A
0.1U_0603_25V7K
0.1U_0603_25V7K
2200P_0402_50V7K
2
PC112
PR124
2_0603_5%
10U_1206_25VAK
10U_1206_25VAK
1
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
Iccmax= 45A
2
PR125
PC111
PC113
1
1
OCP min=54A 1 2
PC114
PC115
PC116
H +5VS H
2
0_0402_5%
1
Load line : -1.9 mV/A
2
<23> GPU_VID5
DCM#
FSW=600KHz
<23> GPU_VID4
42
10
<23> GPU_VID3
1
41
<23> GPU_VID2
ZCD_EN#
VIN
VIN
VIN
NC
GH
CGND
NC
VCIN
BOOT
PHASE
CGND
PR126
<23> GPU_VID1 @ @ @ 11 40 A3210_PWM1 47K_0402_1%
VIN PWM
1
1 2
<23> GPU_VID0 +3VS
PR127
PR131
PR132
PR133
PR128
PR134
12 39 3210_EN
VIN DISB#
1
1 2
<18> NVDD_PWR_EN PR129 0_0402_5% 13 38 2 1 Themal_P
VIN THWN PR135
2
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
1 2 14 37 0_0402_5%
G <32,45,51,55,57> SUSP# 0_0402_5% VIN CGND G
2
PR130 @ 15 PU11 36 PL12
3210_EN VSWH NCP5369MNR2G_QFN40_6X6 GL .42UH 20% PCME064T-R42MS1R557 20A
PR136 16 35 3210_PH1 1 2 +VGA_CORE
1K_0402_1% PGND VSWH
2 1 +3VS 17 34
2.2_1206_1% 1000P_0603_50V7K
PGND VSWH
1
PC119
18 33
PR137 PGND VSWH
1 1 1
470U_D2_2VM_R9M
2
470U_D2_2VY_R9M
470U_D2_2VY_R9M
+5VS
PR138
PR139
PR140
PR141
PR142
PR143
PR144
PSI# 1 2 DPRSLPVR_VGA 19 32
PGND VSWH
2
2
2
2
2
2
2
2
+ + +
PC120
PC121
PC122
0_0402_5%
10_0402_1%
20 31
PR146
0_0402_5% PGND VSWH
1
VSWH
VSWH
VSWH
2 2 2
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PR147
PR148
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
10_0402_1%
1
1
1
1
1
1
1
3210_CS_PH1 1
3210_CSREF 1
PR149
PR145
2
21
22
23
24
25
26
27
28
29
30
43
2
7.32K_0402_1%
1 2
F F
0.01U_0402_25V7K
1
+3VS
2
PSI#
PH2
PC123 100K_0402_5%_TSM0B104J4702RE
PC124
1U_0603_10V6K
3.3K_0402_1%
1
1
2
2 1
+3VS
@
PR150
40
39
38
37
36
35
34
33
32
31
10U_1206_25VAK
10U_1206_25VAK
0.1U_0603_25V7K
0.1U_0603_25V7K
2200P_0402_50V7K
PR153 VGA_AC_DET <23,32,45>
PU12
2_0603_5%
1
1
2 1VGA_AC_DET
PR154
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PSI#
NC
VCC
2
1
@ PC126
PC125
PC127
PC129
PC130
PR152
PC128
2.2U_0402_6.3V6M
2
0_0402_5%
1
0_0402_5% 1 30 D 2 PR155 1
<19,27,32,55> DGPU_PWROK +5VS
2
1 2 2 EN TTSNS 29 H_PROCHOT#_VGA 2 0_0402_5%
2
<45> VGA_IMON 3 PWRGD VRTT 28 DCM# G PQ26 @
0.068U_0402_10V6K
3
1 2 5 CLKEN# OD# 26 A3210_PWM1 2N7002KW_SOT323-3
42
10
FBRTN PWM1
1
@ PR156 97.6K_0402_1% 6 25 A3210_PWM2
E FB PWM2 E
1
VCC_SEN_C 7 24 41
ZCD_EN#
VIN
VIN
VIN
NC
GH
CGND
NC
VCIN
BOOT
PHASE
COMP PWM3 +5VS CGND
PR157 8 23 PR158
PC131
TRDET# SW2
2
1 2 1 2
CSSUM
PC133
PC134
CSREF
+3VS
2
RAMP
LLINE
PR159 12 39 3210_OD#
IREF
RPM
GND
1
ILIM
ADP3210JCPZ-RL_QFN40_6X6 PR161
11
12
13
14
15
16
17
18
19
20
PR162 14 37 0_0402_5%
1.65K_0402_1% VIN CGND
15 36 PL13
VSWH PU13
GL .42UH 20% PCME064T-R42MS1R557 20A
7.87K_0402_1%
150P_0402_50V8J
2
16 NCP5369MNR2G_QFN40_6X6 35 3210_PH2 1 2
PGND VSWH +VGA_CORE
1
1
VCC_SEN
VSS_SEN
2 PR165 1
PR164
39.2K_0402_1%
1000P_0603_50V7K
0_0402_5% 17 34
PR163
0_0402_5%
10_0402_1%
PGND VSWH
2
1
PC135
PC136
2
3210_CSCOMP 73.2K_0402_1% 18 33
1200P_0402_50V7K
PGND VSWH
PR166
PR167
1 1
20K_0402_1%
D D
100P_0402_50V8J
470U_D2_2VM_R9M
470U_D2_2VM_R9M
1
2
1
2
19 32
PGND VSWH
2
PH3 + +
PC137
PC140
PR168
PC138
PC139
@ 220K_0402_5%_ERTJ0EV224J 20 31
3210_CSREF 1
PGND VSWH
1
1
PR172
1
VSWH
VSWH
VSWH
2
2 2
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PR169 PR170 165K_0402_1%
PR173
3210_CS_PH2
2.2_1206_1%
2
1
1K_0402_1%
2
21
22
23
24
25
26
27
28
29
30
43
2
@ PR178 on the same layer
PR174
PR171 1
2
178K_0603_1%
PR176 PR177 PR175 1 2 3210_CS_PH1
27.4_0402_1% 27.4_0402_1% 0_0402_5%
1
3210_CSREF PR179
@ @ 178K_0603_1%
1
2012/02/29
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
<24> VSSSENSE_VGA
1
change PR164
PC142
PC143
PC144
PC145
PC146
PC147
PC148
PC149
from 5.49k to +VGA_CORE Near VGA Core
2
<24> VCCSENSE_VGA 7.87k
+VGA_B+
22U_0805_6.3V6M
47U_0805_6.3V6M
4.7U_0805_6.3V6K
1 1
80.6K_0402_1%
22U_0805_6.3V6M
1
1
PC150
PC151
PC152
PC160
59K_0402_1%
68.1K_0402_1%
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1
2
357K_0402_1%
1
PR184
PR180
PR181
PR182
PR183
PC153
PC154
PC155
PC156
PC157
PC158
PC159
2
2
2 2
1K_0402_1%
2
B B
2
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
1
1
PC161
PC162
PC163
PC164
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2
2
2
1
PC165
PC166
PC167
PC168
PC169
PC170
PC171
PC172
PC173
1000P_0402_50V7K
1
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/30 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 58 of 65
8 7 6 5 4 3 2 1
5 4 3 2 1
PR190
PR192
PR186 PC174
10_0402_1% 0.033u_0402_16V7K PC175 GFX@ GFX@
1200P_0402_50V7K
1 2 FBA3 1 2 GFX@ 0_0402_1% 1 2
330P_0402_50V8J
D GFX@ SLI@ GFX@ PUT COLSE 0_0402_1% D
75K_0402_1%
.1U_0402_16V7K SLI@
TO GT
1
PR188 PR189 1 PR190 2
PC176
PC177
PR191
TRBSTA# 1 2 FBA1 1 2 GFX@ PH4 Inductor GFX@ GFX@
0.033U_0402_16V7K
2P: 24K 24K_0402_1% PR192 PC179
1
1
8.06K_0402_1% 806_0402_1% GFX@ GFX@ GFX@ 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
1P: 24.9K
PC178
GFX@ GFX@
2
GFX@ PR193 PC180 PC181 GFX@ 2 PR194 1 NTC_PH203 1.65K_0402_1% 1000P_0402_50V7K
2
1 2 FBA2 1 2 1 2 165K_0402_1%
2 PR197 1
SLI@ 0_0402_5%
10_0402_1% GFX@ 2P: 1.65K
GFX@ 560P_0402_50V7K PR196 10P_0402_50V8J PC182 PR198 2P: install
1 PR195 2 1 2 COMPA1 1 2 1 2 SWN2A 1P: 1K
GFX@ GFX@ 1P: @
1K_0402_1% 5.11K_0402_1% 2200P_0402_50V7K 91K_0603_1% CSREFA
GFX@ GFX@ 1 2 PC183 TSENSEA
2
0_0402_5% 1 PR200 2 SWN1A 0.047U_0402_16V7K
2 GFX@
SLI@ PR199 GFX@
2P: 21.5K 91K_0603_1% GFX@ GFX@ PR201 5.49K_0402_1%
1
CSP1A 1 2
1P: 15.8K SWN1A <60>
2
21.5K_0402_1%
PC185 GFX@
CSCOMPA
1000P_0402_50V7K
<10> VCC_AXG_SENSE
2
8.25K_0402_1%
1PR203
1PR202 2 2 PR204 1 CSREFA
1
PC184 0_0402_5% 0_0402_5% SLI@ 2P: install PH5
PR206
1000P_0402_50V7K SLI@ CSREFA <60> 1P: @
1
2 PR205 1 PC186 100K_0402_1%_TSM0B104F4251RZ
<10> VSS_AXG_SENSE 0.047U_0402_16V7K
PR207 0_0402_5% SLI@
1
+3VS
CSP2A
CSP1A
GFX@ 1 SLI@ 2 2 PR208 1 SLI@ CSP2A 1 2
+5VS SWN2A <60>
TRBSTA#
DROOPA
CSSUMA
0_0402_5% 0_0402_5% PR209
COMPA
TSENSEA
IMONA
FBA
1 2 GFX@ GFX@ 5.49K_0402_1% GFX@
DIFFA
ILIMA
1
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
TO V_GT
2
VSNA
VSPA
DIFFA
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD
TRBSTA#
+1.05VS GFX@ 6132_PWMA <60>
PC188
1 2 6132_VCC
.1U_0402_16V7K
.1U_0402_16V7K
1 45 PR214 PC189
2.2U_0603_10V7K 2 VCC PWMA 44 BSTA1 1 2 BSTA1_12 1
VDDBP BSTA +5VS
130_0402_1%
54.9_0402_1%
PR215 2
0_0402_5%
PR224 @
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 0.22U_0603_10V7K Option for
SW2 <60>
1
2
VRDY LG1
1
13 33 2.2U_0603_10V7K CSP2A
+1.05VS VSN SW1 SW1 <60>
PC194 14 32
+3VS VSP HG1 HG1 <60>
DIFF_CPU 15 31 BST1 1 PR225 2 BST1_1 2 1
CSCOMP
2
DIFF BST1
TRBST#
4.7_0603_5%
DROOP
CSSUM
DRVEN
CSREF
1
COMP
75_0402_1%
TSNS
PC195 0.22U_0603_10V7K
CSP3
CSP2
CSP1
PWM
IOUT
ILIM
1
PR226
FB
PR227 PC200 +5VS
PC196 @ 10K_0402_5% PR228
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
43P_0402_50V7K 3P: 73.2K
2
1 2 10P_0402_50V8J 1 PR228 2
<45> VR_HOT# 2P: 41.2K
2
COMP_CPU
0_0402_5%
CPU2@ FB_CPU 73.2K_0402_1% 41.2K_0402_1% Option for 3Phase: @
TRBST#
<16> VGATE
PR230
CPU2@
PR229 CPU2@ 2 phase CPU
DROOP
CPU3@
TSENSE
ILIM_CPU
1 2 VSN 3P: 22p 2Phase: install
<9> VSSSENSE 6132_PWM <60>
1
0_0402_5% CPU3@
PC197 2P: 10p
DRVEN <60>
2
21K_0402_1% 21K_0402_1%
PR232 1000P_0402_50V7K CSP3 1 PR2312 CSP3
SWN3 <60>
2
1
1 2 VSP PC198 6.98K_0402_1%
<9> VCCSENSE
2
21K_0402_1%
@ PR300
0_0402_5% 1 2 PC199 3P: install
0.047U_0402_16V7K
CPU3@
.1U_0402_16V7K
2P: @
2
B B
CPU3@ PC200 CSP1 PR233 CSREF TSENSE
1
1 PR234 2 2 1 CSP2 PC208
1
1
PR301 @
22P_0402_50V8J 6.98K_0402_1%
PR233
PC201
PR236 PC202 PR237 PC203 3P: 21K 0.047U_0402_16V7K
2
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1 12.4K_0402_1%
PR238 PC204 49.9_0402_1% 6.04K_0402_1% 2P: 12.4K CPU2@ 1200P_0402_50V7K CSREF
8.25K_0402_1%
1 2FB_CPU3 1 2 470P_0402_50V7K 2200P_0402_50V7K CPU2@
PR240 1
2
10_0402_1%
CSREF <60>
CSCOMP
21K_0402_1%
0.033u_0402_16V7K CSP1 1 PR2392 PH6
SWN1 <60>
1
PR302 @
PR241 PR242 PC205 6.98K_0402_1%
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p PC206 100K_0402_1%_TSM0B104F4251RZ
1
0.033u_0402_16V7K
0.047U_0402_16V7K
2P: 1200p
1
1
8.06K_0402_1% 806_0402_1%
PC207 CSREF
1
CSSUM
2
.1U_0402_16V7K
PC969@QC TO VCORE
PC209
330P_0402_50V7K
24.9K_0402_1% 1 PR246 2 SWN3
1
CPU2@ 130K_0603_1%
CPU3@ PR247 PC212 1 2 PC211 CPU3@
CSCOMP 1 2 DROOP 1 2 CSREF 330P_0402_50V7K 3P: install
PUT COLSE 2P: @
PR247 806_0402_1% 1000P_0402_50V7K PR248 PR249
3P: 806 <45> IMVP_IMON TO VCORE 1 2
NTC_PH201 1 2
2P: 1K Phase 1 75K_0402_1%
165K_0402_1%
A Inductor PH7 A
1K_0402_1% 2 1
CPU2@
220K_0402_5%_ERTJ0EV224J
Security Classification
2011/06/30
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y490-LA8691P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 59 of 65
5 4 3 2 1
5 4 3 2 1
CPU_B+ CPU_B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
B+
0.1U_0402_25V6
0.1U_0402_25V6
1000P_0402_50V7K
2200P_0402_25V7K
1000P_0402_50V7K
2200P_0402_25V7K
5
5
PL14
PQ27 HCB4532KF-800T90_1812 PQ28
1
1 2
PC330
PC213
PC214
PC215
PC216
PC440
PC217
PC218
PC219
PC220
CPU_B+
1 1
470P_0603_50V7K
470P_0603_50V7K
68U_25V_M_R0.36
1000P_0603_50V7K
68U_25V_M_R0.36
2
2
4 4
<59> HG1 <59> HG2
1
+ +
PC221
PC223
PC224
PC225
+VCC_CORE +VCC_CORE
AON6428L_DFN8-5 AON6428L_DFN8-5
2
PL15 2 2
PC222
3
2
1
3
2
1
D D
0.36UH_VMPI1004AR-R36M-Z03_30A_20% PL16
<BOM Structure> 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1 4 1 4
<59> SW1 <59> SW2
1
2 3 2 3
5
PR250 PR251
4.7_1206_5% 4.7_1206_5%
PQ29 PQ30
2
AON6504 1N DFN PR252 AON6504 1N DFN
4 V1N_CPU2 1 4 V2N_CPU 2 PR253 1 CSREF
<59> LG1 CSREF <59> <59> LG2
1SNUB_CPU1
SNUB_CPU2
10_0402_1%
10_0402_1%
3
2
1
3
2
1
PC226
680P_0402_50V7K
1
PC227
2
680P_0402_50V7K
2
CPU_B+
PR254
BST3 1 2 BST3_1
10U_0805_25V6K
10U_0805_25V6K
4.7_0603_5%
0.1U_0402_25V6
2200P_0402_25V7K
5
CPU3@
2
1
PQ31
PC229
PC230
PC231
PC232
PC228
0.22U_0603_10V7K
1
2
CPU3@
4
PU15 CPU3@ CPU3@ CPU3@ CPU3@ +VCC_CORE
1 9
BST FLAG AON6428L_DFN8-5
C C
CPU3@ 2 8 HG3 PL17
<59> 6132_PWM
3
2
1
1
+5VS 2 1VCC_CPU3 4 6 2 3
VCC GND IccMax=94A IccMax=53A
5
PR256 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
0_0402_5% CPU3@
DRVL
5 LG3 PR257 Icc_Dyn=66A Icc_Dyn=43A
PQ32 4.7_1206_5%
PC233 NCP5911MNTBG_DFN8_2X2 CPU3@
Icc_TDC=52A Icc_TDC=36A
2
10_0402_1%
CPU3@
SWN3 <59>
3
2
1
CPU3@
1
PC234
680P_0402_50V7K
3Phase: install
2
CPU3@
2Phase:: @
CPU_B+ CPU_B+
2Phase: install
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
2200P_0402_25V7K
B 1Phase:: @ B
1
1
PC235
PC236
PC237
PC238
PC241
PC239
PC242
PC243
2
2
5
5
BSTA2 1 PR259 2 BSTA2_1
PQ33 GFX@ GFX@ GFX@ GFX@ PQ34 GFX@ GFX@ GFX@ GFX@
2
2.2_0603_5%
GFX@ PC240
0.22U_0603_10V7K
1
4 4
<59> HG1A GFX@
GFX@
PU16
AON6428L_DFN8-5 1 9 AON6428L_DFN8-5
+VCC_GFXCORE_AXG BST FLAG
3
2
1
3
2
1
PL18 2 8 HG2A GFX@ PL19
<59> 6132_PWMA PWM DRVH
0.36UH 20% PDME064T-R36MS1R405 24A GFX@ 0.36UH 20% PDME064T-R36MS1R405 24A
1 2 DRVEN 2 PR260 1EN_GFX2 3 7 SW2A 1 2 +VCC_GFXCORE_AXG
<59> SW1A EN SW
2K_0402_1% GFX@
1
GFX@
+5VS 2 1VCC_GFX2 4 6
@ 4.7_1206_5%
VCC GND
5
5
PR262 GFX@
PR261
1
0_0402_5% 5 PQ36
0_0402_5%
PQ35 DRVL
PR264
GFX@
1
NCP5911MNTBG_DFN8_2X2 AON6504 1N DFN PR263 @
2
GFX@
4 2.2U_0603_10V7K LG2A 4 2 1 CSREFA
PR265
<59> LG1A
2
2
10_0402_1%
SNUB_GFX1
SNUB_GFX2
GFX@ GFX@ GFX@
2
2 PR267 1
CSREFA <59>
3
2
1
3
2
1
@ 680P_0402_50V7K
SWN2A <59>
GFX@
10_0402_1%
GFX@
GFX@
1
1
PC246 @
PC245
SWN1A <59>
2
680P_0402_50V7K
2
A A
R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
Size Document Number Rev
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Y490-LA8691P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 60 of 65
5 4 3 2 1
5 4 3 2 1
D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1
sites
PC258
PC259
PC260
PC261
PC262
PC263
PC264
PC265
1 1 1 1 1 1
PC252 PC253 PC254 PC255 PC256 PC257
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 2 2 2 2 2 2 2 2
2 2 2 2 2 2
GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@
+1.05VS
+VCC_CORE +1.05VS
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1
PC271
PC272
PC273
PC274
PC275
PC276
PC277
PC278
PC279
PC280
PC281
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC266 PC267 PC268 PC269 PC270 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2
PC282
PC283
PC284
PC285
PC286
PC287
PC288
PC289
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2
2 2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1
PC295
PC296
PC297
PC298
PC299
PC300
PC301
PC302
PC290 PC291 PC292 PC293 PC294
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2 1 1 1
330U_D2_2VM_R9M
330U_D2_2VM_R9M
330U_D2_2VM_R9M
PC303
PC304
PC305
+ + +
C C
2 3 2 3 2 3
PC59@DC 1 1
330U_D2_2VM_R6M
330U_D2_2VM_R6M
1 1 1 1 1 GFX@ GFX@ GFX@
PC311
PC312
+ +
PC306 PC307 PC308 PC309 PC310
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 3 2 3
PC38,PC39,PC40,PC41
1 1 1 1
PC313 PC314 PC315 PC316
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2
PC32,PC49,PC54,PC55,PC56
+VCC_CORE
PC8,PC21,PC22,PC63
PC38,PC39,PC40,PC41
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1 1 1 1 1 1
470U_D2_2VM_R4.5M
+ + + + + +
PC317
PC318
PC319
PC320
PC321
PC322
B 2 3 2 3 2 3 2 3 2 3 2 B
DC:PC73,PC74,PC75,PC76,PC77,PC78(330uF/9m)
QC:PC76,PC78(470uF/4.5m),PC73,PC74,PC75(330uF/9m)
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Y490-LA8691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 61 of 65
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ37 PQ38
AO4423L 1P SO8 AO4423L 1P SO8
8 1 1 8 PR268
VIN 7 2 2 7 0.01_1206_1% PL20 CHG_B+
6 3 3 6 1UH_PCMB061H-1R0MS_7A_20%
5 5 1 4 1 2 PQ39
AO4423L 1P SO8
2 3 1 8
@ 10U_0805_25V6K
@ 10U_0805_25V6K
4
4
D D
SH00000AA00 2 7
2
PC323 3 6
2200P_0402_50V7K
PQ40 5600P_0402_25V7K 5
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1 2
PC324
PC325
47K_0402_5%
1
1
2
200K_0402_1%
0.1U_0603_25V7K
PC327
4
1
PR269
PC331
PC326
PC332
DTA144EUA_SC70-3 DISCHG_G
3
PC328
PR270
1 2
1
PR271
PC329 @ 47K_0402_1%
2
2
2 0.1U_0603_25V7K 1 2
2
ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR272
1DISCHG_G-1
10K_0402_1%
1
2
PD5
P2-1 PR273
0.1U_0603_25V7K
1
2 200K_0402_1%
PQ41 PQ42
1
PC333 PC334 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3 +3VALW P
PR274 <54> ACPRN 1 2 2 1 PD6
3
20K_0402_1% 1SS355_SOD323-2
0.1U_0603_25V7K 2 1 2
100K_0402_1%
6 2
6
@ 10K_0603_1%
1
1
PR276 @
PQ44A PC335
2
PR275
PR277
PQ43A 2N7002KDW -2N_SOT363-6
2 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K
6
2 PQ45A
0.1U_0603_25V7K
BATT_OUT <53> 2 1
150K_0402_1% 2N7002KDW -2N_SOT363-6
1
1
PC336
VIN PR278 @ PR279 @
1
1
C 2 1 1 2 2 PACIN C
4.7M_0603_1% P2 PQ46
390K_0603_1%
2
1
5
P2-2
39.2K_0402_1% AON7408L_DFN8-5
1
PR280
2N7002KDW-2N_SOT363-6
1
PR282
3
PQ43B
10_1206_5%
ACOK
CMPIN
CMPOUT
ACP
ACN
PR281 PR283 <45,53> ADP_I 1 2
2
47K_0402_1% 64.9K_0603_1% 21 4
PACIN 1 2 5 1 2 6 TP
ACDET PC339
20 1 2
SH000005Y80
PC337 .1U_0603_25V7K PC338
4
2 1 1 2 7 VCC PL21
3
2
1
PR284 IOUT PR285
1U_0603_25V6
1
5
1 2ACOFF-12 <45,49,53> EC_SMB_CK1 1 2 9 2 3
<45> ACOFF SCL
1
10K_0402_5% PR288 PC340 PQ48
4.7_1206_5%
PR290
PR289 2.2_0603_5% 0.047U_0603_16V7K AON7702L_DFN8-5
1
1 2 10 17 BST_CHG 1 2 2 1
10U_0805_25V6K
10U_0805_25V6K
+3VALW P ILIM BTST
1
16251_SN
PR291 147K_0402_1% PD7
3
2012/02/29 RB751V-40_SOD323-2 4
LODRV
0_0402_5%
1
16 2 1
PC341
PC342
PR292
GND
SRN
SRP
Add PC337 0.1uF REGN
BM
100K_0402_1%
2
2N7002KDW-2N_SOT363-6
2
680P_0603_50V7K
BQ24737_VDD
11
1 12
13
14
15
3
2
1
3
1
PQ44B
PC343
10_0603_5%
6.8_0603_5%
2
1
PR294
BM#
PR293
PC344
BATT_OUT 5 1U_0603_25V6
2
B B
2
10K_0402_5%
4
2
2
PR295 @
PC345 DL_CHG
0.1U_0603_25V7K
2 1
1
PC346
0.1U_0603_25V7K
2
+3VS
BQ24737_VDD
PR298
10K_0402_1%
1
1
1 2
ACIN <45>
PR297
PR296 10K_0402_1%
47K_0402_1%
2
2
PACIN
2N7002KDW-2N_SOT363-6
1
3
PQ45B
PR299
ACPRN 5 12K_0402_1%
2
4
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 62 of 65
5 4 3 2 1
5 4 3 2 1
D D
PCH_PWR_EN# 2
U14,+3VALW_PCH
V
AC A1
MODE VIN QH4,+5VALW_PCH
V V
A2 A3 B5
VV
PU2 A5 2
V
PU3
V
B+ +3VALW_PCH
+3VALW B7 2 3
BATT V +5VALW_PCH
BATT
MODE
B1
B2
B+ B4 V
V
V
EC 4 SYS_PWROK
13
PQ2 PCH_RSMRST# PM_DRAM_PWRGD
V
V V PCH
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
CPU
V V
V
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 15
C C
PM_SLP_S5#
A4 B6 PM_SLP_A# 6
PM_SLP_SUS#
V
V
ON/OFF V
SYSON 7 SYSON# +1.5V
V
PU5
DGPU_PWR_EN 8a (DIS) VGA_ON
+3VSDGPU
V
8
Q6 11
SUSP#,SUSP U49
V
VGATE
+5VS
V
+1.5VSDGPU
U40
V
U20
V
+3VS +1.8VSDGPU VGA
U37
B B
V
U13
V
+1.5VS +1.0VSDGPU
PU28
V
PU8
V
+0.75V +VGA_CORE
VCCPPWRGOOD
PU998
V
V
PU9 PU7
+1.05VS_VCCP +VCCSA 8b (DIS)
VGA_PWROK
U47
CK505
VR_ON 9 PU1000
V
10
V
+CPU_CORE
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 63 of 65
5 4 3 2 1
5 4 3 2 1
2 EMI Request
add PC526,PC527,PC970,PC971(470uF) 201109/27 B test
Remove one power rail +V1.05S_VCCPP
3 Combine 1.05V 51 B test
Pop PR722,PR712,PR718 201109/27
10
11
12
13
14
B B
15
16
17
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 64 of 65
5 4 3 2 1
5 4 3 2 1
D
NO DATE PAGE MODIFICATION LIST PURPOSE D
---------------------------------------------------------------------------------------------------------------------
01) 03/14 10 R64 Change R64 BOM structure from "@" to "DS3@" For Deep S3 Function
C C
B B
A A