Audio, Power Management and Control: Key Features

Audio, Power Management P95020
and Control
Preliminary Datasheet
OVERVIEW KEY FEATURES

Quick Turn Customization
The P95020 is designed to provide maximum flexibility to Embedded Microcontroller
system designers by providing full customization and  Master Controller during Power Up & Power-Down
programmability. It is the first of a new generation of • Initialization and power sequencing
standardized application-specific controllers that  Dynamic Power Management via I²C bus interface
incorporates a general purpose microcontroller, a high  Up to 10 General Purpose I/Os available
fidelity audio CODEC including headphone outputs and a  General house keeping for P95020 and other devices
2.5W Class D audio amplifier, full power management Audio Features
functionality, a touch screen controller and a real time  4 Channel CODEC with 24-bit resolution and internal
registers for status and control
clock all of which are required by portable consumer
 Integrated 2.5 Watt Mono Class D Amplifier
devices such as cellular phone handsets, portable gaming with Filterless Operation.
devices, digital media players, portable navigational  Stereo cap-less headphone driver
devices, etc.  Differential Analog Audio Line Inputs
 Dual Mode Microphone Inputs (Analog or DMIC)
The general purpose microcontroller controls the device
Battery Charging Circuit
power-on/power-off sequencing and can also be used for  Autonomous Li-Ion/Li-Poly charger up to 1.5A
general system housekeeping. • Automatic Load Prioritization
The P95020 includes two I²C Interfaces, a master for • Advanced Battery Safety features
 High efficiency switch-mode *EnergyPath™ controller
communicating with an external EEPROM and a slave for
 USB or Wall-mounted Charging
communicating with the host. • Programmable Current Limit
The high fidelity audio CODEC along with headphone • Automatic end-of-charge control
outputs and the 2.5 watt Class D audio speaker amplifier  Internal 180 m ideal diode with external
comprise a total audio solution for portable applications. ideal diode controller
Power Management Features
The switch-mode EnergyPath™ Battery Charger operates  All Converters:
with its own high efficiency buck regulator to transmit the • Power up/down sequence field reprogrammable with
2.5 watts available from a USB port to the system with external EEPROM
minimal wasted power. It can also handle up to 2A from a • Dynamic voltage scaling
wall charger. • Host or I2C output enable / disable
 Buck DC-DC PWM converters with PFM mode
Its power management features along with switch-mode • Two at 500mA, 0.75V to 3.7V
converters and LDOs should be sufficient to provide power • One at 1000mA, 0.75V to 3.7V
for even the most complex hand-held devices.  Boost DC-DC converters
• One at 1.5 A peak on inductor, 4.05V to 5.0V
The integrated touch screen controller allows adding touch • One LED supply with 2 W total output power
screen capability to devices at significantly reduced cost.  Two programmable current sinks, @ 25mA each
 Voltage limited to rating of external FET & diode
It also includes IDT‟s high quality, low power real time  Linear Regulators
clock. • Three LDOs at 150mA, 0.75V to 3.7V
• Four LDOs at 50mA, 0.7V to 3.7V
• One always-on LDO at 10mA, 3.3 or 3.0V
APPLICATIONS ADC and Touch Screen Controller
Smart Phones  4-wire touch screen interface
Portable Gaming Device  One direct battery measurement channel
Digital Media Players  One direct VSYS measurement channel
Portable Navigational Devices  One direct charge current measurement channel
 On-Chip temperature measurement
 Four auxiliary analog input channels (shared with GPIO
pins)
 Touch pressure measurement
 Sample rate: 62.5k SPS
 12 bit resolution, DNL: -1~+2 LSB, INL: +-2
 On-chip 2.5V reference
Revision 0.7.10 1 ©2010 Integrated Device Technology, Inc.

P95020 / Preliminary Datasheet
BLOCK DIAGRAM
Thermal Sensor
I2C Slave I/F
To
Power-On-Reset External Processor Audio Codec
SW_DET
Bus Arbitrator
Real Time Clock

Headphone Amp
1.5K Byte &
Program
Pin MUX
RAM CLASS_D Amp

10 GPIOs
Micro
Controller
ADC 4K Byte I2C Master
Code Space
Touch Screen ROM Interface
Controller To external
Interrupt EEPROM
Controller
LED_BOOST
WatchDog LDO_150_2 (150mA)
LED Backlight P/S LDO_150_1 (150mA)
with 2 Current Sinks LDO_150_0 (150mA)
LDO_050_3 (50mA)
LDO_050_2 (50mA)
LDO_050_1 (50mA)
Hot Swap Interrupt Manager LDO_050_0 (50mA)
Switches LDO_LP (10mA)
BUCK1000 (1000 mA DC-DC)

PLL BUCK500_1 (500mA DC-DC)
BUCK500_0 (500mA DC-DC)
& Battery
Clock Synthesizer Charger
BOOST5 (5V DC-DC)
Figure 1 – P95020 Block Diagram.

TABLE OF CONTENTS
OVERVIEW ............................................................................................................................................................................. 1
APPLICATIONS ...................................................................................................................................................................... 1
KEY FEATURES ..................................................................................................................................................................... 1
BLOCK DIAGRAM .................................................................................................................................................................. 2
PIN ASSIGNMENTS ............................................................................................................................................................... 7
PIN FUNCTIONS BY PIN NUMBER ....................................................................................................................................... 9
I/O LEVELS BY TYPE ........................................................................................................................................................... 14
ABSOLUTE MAXIMUM RATINGS........................................................................................................................................ 15
RECOMMENDED OPERATING CONDITIONS ................................................................................................................... 16
DIGITAL INTERFACES - DC ELECTRICAL CHARACTERISTICS ..................................................................................... 16
I2C MASTER - ELECTRICAL CHARACTERISTICS ............................................................................................................ 16
I2C SLAVE - ELECTRICAL CHARACTERISTICS ............................................................................................................... 16
I2S - ELECTRICAL CHARACTERISTICS ............................................................................................................................ 16
GPIO - ELECTRICAL CHARACTERISTICS ......................................................................................................................... 16
AUDIO POWER CONSUMPTION ........................................................................................................................................ 17
1.0 OVERVIEW .............................................................................................................................................................. 18
1.1 FUNCTIONAL MODES ............................................................................................................................................ 19
1.2 REGISTER MAP ...................................................................................................................................................... 20
1.3 BYTE ORDERING AND OFFSET ........................................................................................................................... 21
1.4 REGISTER ACCESS TYPES .................................................................................................................................. 21
1.5 RESERVED BIT FIELDS ......................................................................................................................................... 21
2.0 AUDIO MODULE ..................................................................................................................................................... 22
2.1 AUDIO - PIN DEFINITIONS ..................................................................................................................................... 22
2.2 AUDIO - SECTION OVERVIEW .............................................................................................................................. 23
2.3 AUDIO - ANALOG PERFORMANCE CHARACTERISTICS ................................................................................... 23
2.4 AUDIO - MICROPHONE INPUT PORT ................................................................................................................... 24
2.5 AUDIO - ANALOG LINE INPUT ............................................................................................................................... 27
2.6 AUDIO - DAC, ADC ................................................................................................................................................. 27
2.7 AUDIO - AUTOMATIC GAIN CONTROL ................................................................................................................. 28
2.8 AUDIO - ANALOG MIXER BLOCK .......................................................................................................................... 28
2.9 AUDIO - DIGITAL AUDIO INPUT/OUTPUT INTERFACE ....................................................................................... 29
2.10 AUDIO - REFERENCE VOLTAGE GENERATOR, BUFFER, & FILTERING CAPS .......................................... 31
2.11 AUDIO - ANALOG AND CLASS D OUTPUT BLOCK ......................................................................................... 31
2.12 AUDIO - CLASS-D BTL AMPLIFIER ................................................................................................................... 32
2.13 AUDIO CLASS_D - REGISTERS ........................................................................................................................ 32
2.14 AUDIO CLASS_D - EQUALIZER COEFFICIENT & PRESCALER RAM (EQRAM) ........................................... 39
2.15 AUDIO – AUDIO CONTROL REGISTERS ......................................................................................................... 40
3.0 CHARGER MODULE ............................................................................................................................................... 52
3.1 CHARGER - OVERVIEW ......................................................................................................................................... 52
3.2 CHARGER – SUB-BLOCKS .................................................................................................................................... 52
3.3 CHARGER – DC ELECTRICAL CHARACTERISTICS ........................................................................................... 53
3.4 CHARGER – TYPICAL PERFORMANCE CHARACTERISTICS ............................................................................ 54
3.5 CHARGER - REGISTER ADDRESSES .................................................................................................................. 55
3.6 CHARGER - PRE-REGULATOR ............................................................................................................................. 58
3.7 IDEAL DIODE FROM VBAT TO VSYS ......................................................................................................................... 59
3.8 CHARGER - CHARGER/DISCHARGER ................................................................................................................. 60
3.9 CHARGER - THERMAL MONITORING .................................................................................................................. 60
3.10 CHARGER - POWER ON RESET....................................................................................................................... 60
4.0 CLOCK GENERATOR MODULE ............................................................................................................................ 61
4.1 CKGEN - PIN DEFINITIONS ................................................................................................................................... 61
4.2 CKGEN - OSCILLATOR CIRCUIT ELECTRICAL CHARACTERISTICS ................................................................ 62
4.3 CKGEN - PLL CONTROL ........................................................................................................................................ 63
4.4 CKGEN – OSCILLATOR CIRCUIT .......................................................................................................................... 63
4.5 CKGEN - CKGEN POWER SOURCE ..................................................................................................................... 63
4.6 CKGEN – CLOCK ACCURACY ............................................................................................................................... 63
4.7 CKGEN – CLOCK GENERATOR REGISTERS ...................................................................................................... 64

5.0 RTC MODULE ......................................................................................................................................................... 66

5.1 RTC - GENERAL DESCRIPTION ............................................................................................................................ 66
5.2 RTC - TIMEKEEPER REGISTERS ......................................................................................................................... 67
5.3 RTC - DATE REGISTERS ....................................................................................................................................... 67
5.4 RTC - ALARM REGISTERS .................................................................................................................................... 68
5.5 RTC - INTERRUPT REGISTERS ............................................................................................................................ 69
5.6 RTC RESERVED REGISTERS ............................................................................................................................... 70
6.0 GENERAL PURPOSE TIMERS ............................................................................................................................... 71
6.1 GENERAL PURPOSE TIMERS – GENERAL DESCRIPTION................................................................................ 71
6.2 GENERAL PURPOSE TIMERS – REGISTERS ...................................................................................................... 71
7.0 DC_DC MODULE .................................................................................................................................................... 74
8.0 2MHz, 500mA & 1000mA SYNCHRONOUS BUCK REGULATORS ...................................................................... 75
8.1 BUCK1000 & BUCK500 - PIN DEFINITIONS.......................................................................................................... 76
8.2 BUCK1000 & BUCK500 - ELECTRICAL CHARACTERISTICS .............................................................................. 76
8.3 BUCK CONVERTERS – TYPICAL PERFORMANCE CHARACTERISTICS .......................................................... 77
8.4 BUCK1000 & BUCK500 - REGISTER ADDRESSES .............................................................................................. 79
8.5 BUCK1000 & BUCK500 - ENABLING & DISABLING ............................................................................................. 80
8.6 BUCK1000 & BUCK500 - APPLICATIONS INFORMATION ................................................................................... 81
9.0 HIGH EFFICIENCY 10 LED BOOST CONVERTER AND SINKS ........................................................................... 83
9.1 LED_BOOST - ELECTRICAL CHARACTERISTICS ............................................................................................... 84
9.2 LED_BOOST – TYPICAL PERFORMANCE CHARACTERISTICS ........................................................................ 84
9.3 LED_BOOST - REGISTER SETTINGS ................................................................................................................... 85
9.4 LED_BOOST - ENABLING & DISABLING .............................................................................................................. 86
9.5 LED_BOOST – Over-Voltage Protection ................................................................................................................. 87
9.6 LED_BOOST – Over-Current Limiter ....................................................................................................................... 87
9.7 LED_BOOST - APPLICATIONS INFORMATION .................................................................................................... 87
10.0 BOOST5 – 1.5A, SYNCHRONOUS PWM BOOST CONVERTER ......................................................................... 89
10.1 BOOST5 - ELECTRICAL CHARACTERISTICS.................................................................................................. 90
10.2 BOOST5 - REGISTER SETTINGS...................................................................................................................... 90
10.3 BOOST5 - ENABLING & DISABLING ................................................................................................................. 91
10.4 OUTPUT DIODE .................................................................................................................................................. 92
10.5 BOOST5 - APPLICATIONS INFORMATION ...................................................................................................... 92
11.0 CLASS_D BTL POWER OUTPUT STAGE ............................................................................................................. 93
11.1 CLASS_D - ELECTRICAL CHARACTERISTICS ................................................................................................ 93
11.2 CLASS_D – TYPICAL PERFORMANCE CHARACTERISTICS ......................................................................... 94
11.3 CLASS_D – REGISTER SETTINGS ................................................................................................................... 94
11.4 CLASS_D - AUDIO INTERFACE AND DECODE ............................................................................................... 95
11.5 CLASS_D - SHORT CIRCUIT PROTECTION CIRCUITRY ............................................................................... 95
11.6 CLASS_D - APPLICATIONS INFORMATION ..................................................................................................... 95
12.0 TSC MODULE - ADC AND TOUCH SCREEN CONTROLLER .............................................................................. 96
12.1 ADC AND TOUCH SCREEN CONTROLLER ELECTRICAL CHARACTERISTICS .......................................... 97
12.2 ADC AND TOUCH SCREEN CONTROLLER PIN DEFINITIONS ...................................................................... 97
12.3 ADC AND TOUCH SCREEN CONTROLLER OPERATION ............................................................................... 97
12.4 ADC AND TOUCH SCREEN CONTROLLER REGISTERS ............................................................................. 100
13.0 PCON MODULE – POWER CONTROLLER AND GENERAL PURPOSE I/O ..................................................... 107
13.1 GPIO PIN DEFINITIONS ................................................................................................................................... 107
13.2 POWER STATES .............................................................................................................................................. 107
13.3 POWER SEQUENCING BY EMBEDDED MICROCONTROLLER ................................................................... 107
13.4 POWER ON RESET OUTPUT (POR_OUT) ..................................................................................................... 108
13.5 POWER SWITCH DETECTOR (SW_DET) ....................................................................................................... 108
13.6 GPIO GENERAL DESCRIPTION ...................................................................................................................... 108
13.7 PCON REGISTERS ........................................................................................................................................... 108
14.0 HOTSWAP MODULE ............................................................................................................................................. 113
14.1 HOT SWAP (LOAD SWITCHES) – ELECTRICAL CHARACTERISTICS ......................................................... 113
14.2 HOTSWAP – TYPICAL PERFORMANCE CHARACTERISTICS ..................................................................... 114
14.3 HOTSWAP – PIN DEFINITIONS ....................................................................................................................... 115
14.4 PCON REGISTER - HOTSWAP CONFIGURATION ........................................................................................ 115
15.0 I2C_I2S MODULE .................................................................................................................................................. 116
15.1 I2C_I2S - PIN DEFINITIONS ............................................................................................................................. 116
15.2 I²C SLAVE.......................................................................................................................................................... 116
15.3 INTERRUPT DISPATCHER .............................................................................................................................. 117

15.4 ACCESS ARBITER ........................................................................................................................................... 117

15.5 DIGITAL AUDIO DATA SERIAL INTERFACE .................................................................................................. 117
15.6 I2C_I2S – INTERFACE TIMING ........................................................................................................................ 118
15.7 GLOBAL REGISTER SETTINGS (I²C-page 0) ................................................................................................. 120
15.8 ACCM REGISTERS .......................................................................................................................................... 123
16.0 LDO MODULE ....................................................................................................................................................... 124
16.1 LDO - PIN DEFINITIONS .................................................................................................................................. 125
16.2 LDO - LDO_150 & LDO_050 ELECTRICAL CHARACTERISTICS .................................................................. 125
16.3 LDO – TYPICAL PERFORMANCE CHARACTERISTICS ................................................................................ 126
16.4 LDO - LDO_LP - ELECTRICAL CHARACTERISTICS ...................................................................................... 127
16.5 LDO - LIST OF ALL LDOS ................................................................................................................................ 127
16.6 LDO – REGISTER SETTINGS .......................................................................................................................... 127
17.0 EMBUP – EMBEDDED MICROCONTROLLER SUBSYSTEM & I/O.................................................................... 131
17.1 OVERVIEW ........................................................................................................................................................ 131
17.2 FUNCTIONAL DESCRIPTION .......................................................................................................................... 131
17.3 ON-CHIP RAM & ROM ...................................................................................................................................... 131
17.4 I²C SLAVE INTERFACE .................................................................................................................................... 131
17.5 PERIPHERALS .................................................................................................................................................. 132
17.6 INTERRUPT CONTROLLER ............................................................................................................................. 132
18.0 APPLICATIONS INFORMATION ........................................................................................................................... 133
18.1 EXTERNAL COMPONENTS ............................................................................................................................. 133
18.2 DIGITAL LOGIC DECOUPLING CAPACITORS ............................................................................................... 133
18.3 CLASS_D CONSIDERATIONS ......................................................................................................................... 133
18.4 SERIES TERMINATION RESISTORS .............................................................................................................. 133
18.5 I²C EXTERNAL RESISTOR CONNECTION ..................................................................................................... 133
18.6 CRYSTAL LOAD CAPACITORS ....................................................................................................................... 133
18.7 PCB LAYOUT CONSIDERATIONS................................................................................................................... 133
18.8 POWER DISSIPATION AND THERMAL REQUIREMENTS ............................................................................ 133
18.9 TYPICAL BLOCK PERFORMANCE CHARACTERISTICS GRAPHS .............................................................. 133
18.10 APPLICATIONS REFERENCE DESIGN(S) ...................................................................................................... 134
19.0 SOLDERING PROFILE.......................................................................................................................................... 134
20.0 PACKAGE OUTLINE DRAWING ........................................................................................................................... 134
20.1 LLG124 PACKAGE OUTLINE ........................................................................................................................... 134
20.2 NQG132 PACKAGE OUTLINE (Exposed Die Paddle Size D2 = E2 = 5.5 mm) ............................................... 135
21.0 ORDERING INFORMATION.................................................................................................................................. 135
TABLE OF FIGURES
Figure 1 – P95020 Block Diagram. ......................................................................................................................................... 2

Figure 2 – P95020 Pinout Diagram (LLG124) ........................................................................................................................ 7
Figure 3 – P95020 Pinout (NGQ132) ..................................................................................................................................... 8
Figure 4 – Overall System Functional Diagram. ................................................................................................................... 18
Figure 5 – Audio Block Diagram ........................................................................................................................................... 22
Figure 6 –Stereo Digital Microphone (Mode 3) ..................................................................................................................... 26
Figure 7 –Stereo Digital Microphone (Mode 1 & 2)............................................................................................................... 27
Figure 8 – Automatic Gain Control ........................................................................................................................................ 28
Figure 9 – Charger Block Diagram ....................................................................................................................................... 52
Figure 10 – Pre-Regulator Efficiency vs Load Current VBUS = 5.0V, VSYS = 3.7V............................................................ 54
Figure 11– Pre-Regulator Load Regulation VBUS = 5.0V, VSYS = 3.7V ............................................................................ 55
Figure 12 – Battery Charge Current vs Temperature ........................................................................................................... 55
Figure 13 – VSYS Regulation Curve (Tracking VBAT ) ............................................................................................................. 59
Figure 14 – Clock Generator Block Diagram ........................................................................................................................ 61
Figure 15 DC_DC Block Diagram ......................................................................................................................................... 74
Figure 16 – BUCK500 / BUCK1000 Block Diagram ............................................................................................................. 76
Figure 17 – BUCK500 DC-DC Regulator Efficiency vs Load Current PWM Mode .............................................................. 78
Figure 18 – BUCK1000 DC-DC Regulator Efficiency vs Load Current PWM Mode ............................................................ 78
Figure 19 – BUCK500 DC-DC Regulator Efficiency vs Load Current PFM Mode ................................................................ 79
Figure 20 – BUCK500 or BUCK 1000 Applications Diagram ............................................................................................... 81
Figure 21 – White LED Boost & Sink Driver Block Diagram ................................................................................................. 83

Figure 22 – LED Boost Efficiency vs Load Current (two srings of 10 LEDs) ........................................................................ 84
Figure 23 – LED Boost Efficiency vs VIN (two srings of 10 LEDs) ....................................................................................... 85
Figure 24 – LED_BOOST Application Schematic ................................................................................................................. 87
Figure 25 – BOOST5 Block Diagram .................................................................................................................................... 89
Figure 26 – BOOST5 Applications Diagram ......................................................................................................................... 92
Figure 27 – Clss D BTL Efficiency vs Outpout Power (4 ohm speaker) ............................................................................... 94
Figure 28 – ADC & Touchscreen Controller Block Diagram ................................................................................................. 96
Figure 29 – Hotswap Block Diagram .................................................................................................................................. 113
Figure 30 – Hotswap #1 ON Resistance vs Temperature .................................................................................................. 114
Figure 31 – Hotswap #2 ON Resistance vs Temperature .................................................................................................. 114
2
Figure 32 – I C Read / Write Operation .............................................................................................................................. 117
Figure 33 – LDO_050 / LDO_150 Block Diagram ............................................................................................................... 124
Figure 34 – LDO_050_n 50mA LDO Load Regulation ....................................................................................................... 126
Figure 35 – LDO_150_n 150mA LDO Load Regulation ..................................................................................................... 126
Figure 36 - Top level Interrupt routing ................................................................................................................................. 132
Figure 37 – Power Derating Curve (Typical) ....................................................................................................................... 133
LIST OF TABLES
Table 1 – LLG124 Pin Functions by Pin Number (See Figure 2) ........................................................................................... 9

Table 2 - NQG132 Pin Functions by Pin Number (see Figure 3) ......................................................................................... 11
Table 3 – Register Address Global Mapping ........................................................................................................................ 20
Table 4 - Valid Digital Mic Configurations ............................................................................................................................. 25
Table 5 - MCLK Rate selection: MCLK_DIV2: MCLK_RATE .............................................................................................. 29
Table 6 – MCLK/Sample Rate .............................................................................................................................................. 30
Table 7 - EQRAM Addresses ................................................................................................................................................ 39
Table 8 – Register 0xA090 (0x90) Current Limit (I_LIM) Settings Bits [2:0] ........................................................................ 56
Table 9 – Register 0xA091, (0x91) Charging Maximum Voltage (CHG_VOL) Settings, Bits [5:4] ..................................... 56
Table 10 – Register 0xA091, (0x91) Charging Current Limit via Sense Resistor (CHG_CUR) Settings, Bits [3:0] ........... 56
Table 11 – Register 0xA092 (0x92) Charging Termination Time (CHG_TERM) Settings Bits [1:0] .................................... 56
Table 12 – Register 0xA093 (0x93) Battery Recovery Charge Current Control Settings Bits [7:5] ...................................... 57
Table 13 – Register 0xA093, (0x93) Battery Good Voltage Threshold Settings, Bits [4:3] .................................................. 57
Table 14 – Register 0xA095, (0x95) Current Charger Mode Settings, Bits [4:3] .................................................................. 57
Table 15 - Crystal Specifications........................................................................................................................................... 63
Table 16 - Alarm mask bits ................................................................................................................................................... 66
Table 17 – DC-DC Block Registers (Including the CLASS_D BTL Power Bridge) ............................................................... 74
Table 18 – BUCK500_0, BUCK500_1 and BUCK1000 Register Addresses ....................................................................... 79
Table 19 – Output Voltage Register Settings, Bits [6:0] ....................................................................................................... 79
Table 20 – Control Register Cycle by Cycle Current Limit (I_LIM) Settings for Bits [3:2] [Note ] ......................................... 80
Table 21 – Interoperability of enabling/disabling methods vs. loading default values. ......................................................... 80
Table 22 – Register 0xA086 (0x86) IOUT Current Settings for Bits [4:0], Half Scale and Full Scale ................................... 85
Table 24 – Register 0xA088 Output Voltage Bit Setting [4:0] ............................................................................................... 90
Table 25 – Register 0xA089 (0x89) Peak Current Limit (I_LIM) Settings Bits [3:2] .............................................................. 91
Table 27 – Peak Short Circuit Detect Level Settings for Bits [3:2]........................................................................................ 94
Table 28 – I2C Interface Timing .......................................................................................................................................... 118
Table 29 – I2S Interface Timing .......................................................................................................................................... 119
Table 30 - Interrupt Source Mapping .................................................................................................................................. 122
Table 31 – Control Register Current Limit (I_LIM) Settings for Bits [1:0]............................................................................ 128

PIN ASSIGNMENTS
HOT
GPIO_TSC CHARGER DC_DC
LED_BOOST_SINK2
LED_BOOST_SINK1
GND_BAT/ADCGND
SWAP
GPIO4/CHRG_ILIM
CHRG_SYSVCC2
CHRG_SYSVCC1
GPIO1/SW_OUT
CHRG_INPUT2
CHRG_INPUT1
CHRG_CLSEN
CHRG_ICHRG
CHRG_GND2
CHRG_GND1
CHRG_VNTC
CHRG_GATE
CHRG_BAT2
CHRG_BAT1
GPIO3/LED2
GPIO2/LED1
CHRG_SW2
CHRG_SW1
CHRG_NTC
POR_OUT
HSCTRL2
HSCTRL1
SW_DET
PSCREF
HSPWR
DGND
HSO2
HSO1
124
123
121
119
117
115
113
111
109
107
105
103
101
099
097
095
094
122
120
118
116
114
112
110
108
106
104
102
100
098
096
GPIO5/INT_OUT 001 093 LED_BOOST_GND
GPIO6/ADC1 002 092 LED_BOOST_GATE

GPIO7/ADC3 003 091 LED_BOOST_ISENSE
GPIO8/ADC2 004 090 LED_BOOST_VIN
GPIO9/ADC0/MCLK_IN 005 089 LED_BOOST_VSENSE
GPIO10 006 088 BUCK500_0_IN
MIC_R- 007 087 BUCK500_0_OUT
MIC_R+/DMICDAT2 008 086 BUCK500_0_GND
MICBIAS_R/DMICSEL 009 085 BUCK500_0_FDBK
MICBIAS_L/DMICCLK 010 084 BUCK500_1_IN
MIC_L+/DMICDAT1 011 083 BUCK500_1_OUT
MIC_L- 012 082 BUCK500_1_GND
AFILT2 013 081 BUCK500_1_FDBK
AFILT1 014 080 BUCK1000_GND
AGND_MIC
LISLP 016
015
P95020 079
078
BUCK1000_OUT
BUCK1000_IN
AUDIO LISLM 017
(TOP VIEW) 077 BUCK1000_FDBK
LISRP 018 076 BOOST5_GND
LISRM 019 075 BOOST5_SW1
LLO_L 020 074 BOOST5_OUT
LLO_R 021 073 BOOST5_SW2
AVREF 022 072 CLASS_D+
VDD_AUDIO33 023 071 PVDD
ADC_REF 024 070 PGND CLASS_D
HP_R 025 069 CLASS_D-
HP_L 026 068 GND
AGND 027 067 I2CM_SDA
VIRT_GND 028 066 I2CM_SCL
LDO_GND 029 065 I2CS_SDA
LDO_IN3 030 064 I2CS_SCL
LDO_LP 031 063 I2S_SDIN1

034
036
038
040
042
044
046
048
050
052
054
056
058
060
032
033
035
037
039
041
043
045
047
049
051
053
055
057
059
061
062
LDO_050_3
LDO_IN2
LDO_050_2
LDO_050_1
LDO_050_0
LDO_150_2
LDO_IN1
LDO_150_1
LDO_150_0
32KHZ_OUT2
CKGEN_GND
32KHZ_CLKIN/XTALIN
XTALOUT/32KHZ_OUT1
VDD_CKGEN18
HXTALOUT/TCXO_IN
VDD_CKGEN33
HXTALIN/TCXO_OUT1
TCXO_OUT2
SYS_CLK
CKGEN_GND
USB_CLK
VDDIO_CK
EX-ROM
DGND
I2S_BCLK2
I2S_WS2
I2S_SDOUT2
I2S_SDIN2
I2S_BCLK1
I2S_WS1
I2S_SDOUT1
LDO CKGEN I2C_I2S
Figure 2 – P95020 Pinout Diagram (LLG124)
NOTES:
1. All the Buck Converter inputs (BUCK500_0_IN, BUCK500_1_IN, BUCK1000_IN) must be connected to
CHRG_SYSVCC1 and CHRG_SYSVCC2.
2. LLG124 package is available upon request.

LED_BOOST_SINK2
LED_BOOST_SINK1
GND_BAT/ADCGND
GPIO4/CHRG_ILIM
CHRG_SYSVCC2
CHRG_SYSVCC1
GPIO1/SW_OUT
CHRG_INPUT2
CHRG_INPUT1
CHRG_CLSEN
CHRG_ICHRG
CHRG_GND2
CHRG_GND1
CHRG_VNTC
CHRG_GATE
GPIO2/LED1
CHRG_BAT2
CHRG_BAT1
GPIO3/LED2
CHRG_SW2
CHRG_SW1
CHRG_NTC
POR_OUT
HSCTRL2
HSCTRL1
SW_DET
PSCREF
HSPWR
DGND
HSO2
HSO1
NC
NC
A72
A71
A70
A69
A68
A67
A66
A65
A64
A63
A62
A61
A60
A59
A58
A57
A56
A55
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B49
B48
B47
B46
GPIO5/INT_OUT A1 A54 LED_BOOST_GND
NC A2 A53 NC
GPIO7/ADC3 B1 B45 LED_BOOST_GATE
GPIO6/ADC1 A3 A52 LED_BOOST_ISENSE
GPIO8/ADC2 B2 B44 LED_BOOST_VIN
GPIO9/ADC0 A4 A51 LED_BOOST_VSENSE
GPIO10 B3 B43 BUCK500_0_IN
MIC_R- A5 A50 BUCK500_0_OUT
MIC_R+/DMICDAT2 B4 B42 BUCK500_0_GND
MICBIAS_R/DMICSEL A6 A49 BUCK500_0_FDBK
MICBIAS_L/DMICCLK B5 B41 BUCK500_1_IN
MIC_L+/DMICDAT1 A7 A48 BUCK500_1_OUT
MIC_L- B6 B40 BUCK500_1_GND
AFILT2 A8 A47 BUCK500_1_FDBK
AFILT1 B7 B39 BUCK1000_GND
AGND_MIC
LISLP
A9
B8 P95020 B38
A46 BUCK1000_OUT
BUCK1000_IN
LISLM A10 A45 BUCK1000_FDBK
(TOP VIEW)
LISRP B9 B37 BOOST5_GND
LISRM A11 A44 BOOST5_SW1
LLO_L B10 B36 BOOST5_OUT
AVREF A12 A43 BOOST5_SW2
LLO_R B11 B35 CLASS_D+
ADC_REF A13 A42 PVDD
VDD_AUDIO33 B12 B34 PGND
HP_L A14 A41 CLASS_D-
HP_R B13 B33 GND
VIRT_GND A15 A40 I2CM_SDA
AGND B14 B32 I2CM_SCL
LDO_IN3 A16 A39 I2CS_SDA
LDO_GND B15 B31 I2CS_SCL
NC A17 A38 I2S_SDIN1
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
LDO_LP A18 A37 I2S_SDOUT1

B30
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
LDO_050_3
NC
LDO_050_2
LDO_IN2
LDO_050_1
LDO_050_0
LDO_150_2
LDO_IN1
LDO_150_1
LDO_150_0
32KHZ_OUT2
CKGEN_GND
32KHZ_CLKIN/XTALIN
XTALOUT/32KHZ_OUT1
VDD_CKGEN18
HXTALOUT/TCXO_IN
VDD_CKGEN33
HXTALIN/TCXOOUT1
TCXO_OUT2
SYS_CLK
CKGEN_GND
USB_CLK
VDDIO_CK
EX_ROM
DGND
I2S_WS2
I2S_SDIN2
I2S_SDOUT2
I2S_WS1
I2S_BCLK1
NC
NC
I2S_BCLK2
Figure 3 – P95020 Pinout (NGQ132)
NOTES:
All the Buck Converter inputs (BUCK500_0_IN, BUCK500_1_IN, BUCK1000_IN) must be connected to
CHRG_SYSVCC1 and CHRG_SYSVCC2.

PIN FUNCTIONS BY PIN NUMBER

Table 1 – LLG124 Pin Functions by Pin Number (See Figure 2)
MODULE PIN # PIN NAME DESCRIPTION I/O TYPE
GPIO_TSC GPIO 5: General Purpose I/O # 5
(See Pins 1 GPIO5/INT_OUT INT_OUT : Interrupt Output GPIO
117-124 GPIO 6: General Purpose I/O # 6
also) 2 GPIO6/ADC1 ADC1 : Auxiliary Input Channel 2 / X- pin to 4-wire resistive touch-screen GPIO
GPIO 7: General Purpose I/O # 7
3 GPIO7/ADC3 ADC3 : Auxiliary Input Channel 4 / Y- pin to 4-wire resistive touch-screen GPIO
4 GPIO8/ADC2 ADC2 : Auxiliary Input Channel 3 / Y+ pin to 4-wire resistive touch-screen GPIO
ADC0 : Auxiliary Input Channel 1 / X+ pin to 4-wire resistive touch-screen
5 GPIO9/ADC0/MCLK_IN MCLK_IN : Master Clock Input GPIO
6 GPIO10 GPIO 10: General Purpose I/O # 10 GPIO
7 MIC_R- MIC_R-: Analog Microphone Differential Stereo Right Inverting Input A-I
MIC_R+: Analog Microphone Differential Stereo Right Non-Inverting Input A-I
8 MIC_R+/DMICDAT2 DMICDAT2: Digital Microphone 2 Data Input D-I
MICBIAS : Microphone Right Bias A-O
9 MICBIAS_R/DMICSEL DMICSEL : Digital Microphone Select (Common to both inputs) D-O
MICBIAS : Microphone Left Bias A-O
10 MICBIAS_L/DMICCLK DMICCLK : Digital Microphone Clock (Common to both inputs) D-O
MIC_L+ : Analog Microphone Differential Stereo Left Non-Inverting Input A-I
11 MIC_L+/DMICDAT1 DMICDAT1 : Digital Microphone 1 Data Input D-I
12 MIC_L- MIC_L- : Analog Microphone Differential Stereo Left Inverting Input A-I
13 AFILT2 Microphone ADC Anti-Aliasing Filter Capacitor #2 A-I
14 AFILT1 Microphone ADC Anti-Aliasing Filter Capacitor #1 A-I
15 AGND_MIC Microphone Ground (Analog Ground) GND
16 LISLP Line Input Stereo Left Non-Inverting A-I
17 LISLM Line Input Stereo Left Inverting A-I
18 LISRP Line Input Stereo Right Non-Inverting A-I
19 LISRM Line Input Stereo Right Inverting A-I
20 LLO_L Line Level Output, Left A-O
21 LLO_R Line Level Output, Right A-O
22 AVREF Analog Reference A-O
23 VDD_AUDIO33 Filter Capacitor for Internal 3.3V AUDIO LDO A-O
24 ADC_REF ADC Reference Bypass Capacitor A-I
25 HP_R Right Headphone Output A-O
26 HP_L Left Headphone Output A-O
27 AGND Line Out Ground (Analog Ground) GND
AUDIO 28 VIRT_GND Virtual Ground for Cap-Less Output A-O
29 LDO_GND LDO Ground GND
Input Voltage to LDOs for AUDIO Power (VDD_AUDIO33 &
30 LDO_IN3 VDD_AUDIO18) AP-I
Always on Low Power LDO Output
31 LDO_LP (Voltage Programmable to 3.0 V or 3.3 V) AP-O
32 LDO_050_3 50mA LDO Output #3 (Voltage Range: 0.75-3.7 V) AP-O
33 LDO_IN2 Input Voltage to LDO_050_0, LDO_050_1, LDO_050_2 & LDO_050_3 AP-I
50mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
Note: This LDO also serves as the internal power source for I2S1, I2S2 and
I2CS. The external function of this pin is not affected but the voltage
register setting for this LDO will also govern the I/O level for I2S1, I2S2 and
36 LDO_050_0 I2CS. AP-O
38 LDO_IN1 Input Voltage to LDO_150_0, LDO_150_1, & LDO_050_2 AP-I
LDO 40 LDO_150_0 150mA LDO Output #0 (Voltage Range: 0.75-3.7 V) AP-O
41 32KHZ_OUT2 Buffered 32.768kHz Output #2 D-O
42 CKGEN_GND PLL Analog Ground GND
32KHZ_CLKIN: External 32.768kHz Clock Input;
CKGEN 43 32KHZ_CLKIN/XTALIN XTALIN : Input Pin when used with an external crystal A-I


XTALOUT: Output Pin when used with an external crystal
32KHZ_OUT1: when XTALIN is connected to a 32kHz input this pin can be
a 32kHz Output when CKGEN_PLL_STATUS register, 32KOUT1_EN (bit
44 XTALOUT/32KHZ_OUT1 4) is set to 1. A-O
45 VDD_CKGEN18 Filter Capacitor for Internal 1.8V CKGEN LDO A-IO
HXTALOUT: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz crystal oscillator output
46 HXTALOUT/TCXO_IN TCXO_IN: External 12 MHz, 13 MHz, 19.2 MHz or 26 MHz Clock Input TCXO-D-I
47 VDD_CKGEN33 Filter Capacitor for Internal 3.3V CKGEN LDO A-IO
HXTALIN: 12 MHz, 13 MHz, 19.2 MHz, or 26 MHz crystal oscillator input
TCXO_OUT1: Buffered HXTALOUT/TCXO_IN Clock Output #1, 32.7638
48 HXTALIN/TCXO_OUT1 KHz Output, 24 MHz PLL Output TCXO-D-O
Buffered HXTALOUT/TXCO_IN Clock Output #2, 12 MHz PLL Output,
49 TCXO_OUT2 24MHz PLL Output TCXO-D-O
50 SYS_CLK 12MHz Output or Buffered Output of TCXO_IN D-O
51 CKGEN_GND PLL Analog Ground GND
52 USB_CLK 24 MHz or 48 MHz Output D-O
53 VDDIO_CK Power Supply Input for TCXO_OUT1 and TCXO_OUT2 (1.1V – 1.9V) AP-I
ROM Select. EX_ROM = 1, read contents of external ROM. EX_ROM = 0,
54 EX_ROM read contents of internal ROM into internal shadow memory. D-I
55 DGND Digital Ground GND
56 I2S_BCLK2 I²S Bit Clock Channel 2 D-I
57 I2S_WS2 I²S Word Select (Left/Right) Channel 2 D-I
58 I2S_SDOUT2 I²S Serial Data OUT Channel 2 D-O
59 I2S_SDIN2 I²S Serial Data IN Channel 2 D-I
60 I2S_BCLK1 I²S Bit Clock Channel 1 D-I
61 I2S_WS1 I²S Word Select (Left/Right) Channel 1 D-I
62 I2S_SDOUT1 I²S Serial Data OUT Channel 1 D-O
63 I2S_SDIN1 I²S Serial Data IN Channel 1 D-I
64 I2CS_SCL I²C Slave clock I2C-I/O
65 I2CS_SDA I²C Slave data I2C-O
66 I2CM_SCL I²C Master clock I2C-O
67 I2CM_SDA I²C Master data I2C-I/O
I2C_I2S 68 GND GND : Ground GND
69 CLASS_D- Class-D Inverting Output A-O
70 PGND Ground for Class D BTL Power Stage GND
71 PVDD Input Power for CLASS_D BTL Power Stage A-I
CLASS_D 72 CLASS_D+ Class-D Non-Inverting Output A-O
BOOST5 Converter Power Switch
73 BOOST5_SW2 Internally connected to pin 075 (BOOST_SW1) AP-O
74 BOOST5_OUT BOOST5 Converter Output AP-O
75 BOOST5_SW1 Internally connected to pin 073 (BOOST_SW2) AP-O
76 BOOST5_GND Ground for BOOST5 Power Supply AP-I
77 BUCK1000_FDBK BUCK2 Converter #2 -Feedback AP-I
78 BUCK1000_IN BUCK2 Converter #2 - Input AP-I
79 BUCK1000_OUT BUCK2 Converter Output #2 – 1000mA AP-O
80 BUCK1000_GND Ground for BUCK2 Converter #2 GND
81 BUCK500_1_FDBK BUCK1 Converter #1 – Feedback AP-I
82 BUCK500_1_GND Ground for BUCK1 Converter #1 GND
83 BUCK500_1_OUT BUCK1 Converter Output #1 - 500mA AP-O
84 BUCK500_1_IN BUCK1 Converter #1 Input AP-I
85 BUCK500_0_FDBK BUCK0 Converter #0 feedback AP-I
86 BUCK500_0_GND Ground for BUCK0 Converter #0 GND
87 BUCK500_0_OUT BUCK0 Converter Output #0 - 500mA AP-O
88 BUCK500_0_IN BUCK0 Converter #0 Input AP-I
89 LED_BOOST_VSENSE LED_BOOST Converter Output Voltage Sense Input to PWM Controller AP-I
90 LED_BOOST_VIN LED_BOOST Converter GATE BIAS Supply AP-I
91 LED_BOOST_ISENSE LED_BOOST Converter Output Current Sense Input to PWM Controller AP-I
92 LED_BOOST_GATE LED_BOOST Converter GATE Drive to Power FET AP-I
93 LED_BOOST_GND Ground for LED_BOOST AP-I
94 LED_BOOST_SINK1 LED_BOOST Converter Current Sink for LED String #1 AP-I
95 LED_BOOST_SINK2 LED_BOOST Converter Current Sink for LED String #2 AP-I
DC_DC 96 PSCREF Power Supply Current Reference AP-O
97 HSCTRL1 Hot Swap Control Input 1 D-I
98 HSO1 Hot Swap Output 1 A-O
99 HSPWR Hot Swap Switches Power Input AP-I
100 HSO2 Hot Swap Output 2 A-O
HOTSWAP 101 HSCTRL2 Hot Swap Control Input 2 D-I


102 CHRG_GND1 Pins 102 & 103 are the Power GND Pins for the Switching Regulator in the A-I
Charger. Due to their higher current requirement they are internally tied
103 CHRG_GND2 together & must be connected externally at the PC board also. A-I
104 CHRG_SW1 Pins 104 and 105 connect to the inductor of the switch-mode step-down A-O
regulator for the Battery Charger. Due to their higher current requirement
they are internally tied together & must be connected externally at the PC
105 CHRG_SW2 board also. A-O
106 CHRG_INPUT1 Pins 106 and 107 provide 5V VBUS Input Power from the USB or from an AP-I
external wall mounted external supply. Due to their higher current
requirement they are internally tied together & must be connected externally
107 CHRG_INPUT2 at the PC board also. AP-I
108 CHRG_SYSVCC1 Pins 108 and 109 are System VCC Output (VSYS). Due to their higher A-O
current requirement they are internally tied together & must be connected
109 CHRG_SYSVCC2 externally at the PC board also. A-O
110 CHRG_BAT1 Pins 110 and 111 form the positive battery lead connection to a single cell Li- AP-I/O
Ion/Li-Poly battery. Due to their higher current requirement they are internally
111 CHRG_BAT2 tied together & must be connected externally at the PC board also. AP-I/O
112 CHRG_CLSEN Input Current Limit Sense/filtering pin for current limit detection A-I
113 CHRG_ICHRG Current setting. Connect to a current sense resistor AP-I/O
114 CHRG_GATE Gate Drive for (Optional) External Ideal Diode A-O
115 CHRG_NTC Thermal Sense, Connect to a battery‟s thermistor A-I
NTC Power output. This pin provides power to the NTC resistor string.
This output is automatically CHRG_SYSVCC level but only enabled when
CHARGER 116 CHRG_VNTC NTC measurement is necessary to save power. AP-O
GND_BAT & ADCGND: Shared analog ground pin for battery charger and
GPIO_TSC 117 GND_BAT/ADCGND ADC. GND
(See Pins 118 DGND Digital Ground GND
001-006 119 POR_OUT Power-On-Reset Output, Active Low GPIO-OUT
also) 120 SW_DET Switch Detect Input GPIO
SW_OUT: Switch Detect Output
121 GPIO1/SW_OUT/PENDOWN PENDOWN: PENDOWN Detect Output GPIO
122 GPIO2/LED1 LED1: Charger LED # 1 Indicates charging in progress GPIO
123 GPIO3/LED2 LED2: Charger LED # 2 Indicates charging complete GPIO
CHRG_ILIM: Control the current limit of the Charger Pre-Regulator.
CHRG_ILIM = 0, limit current to 500mA; CHRG_ILIM = 1, limit current to
124 GPIO4/CHRG_ILIM 1.5A GPIO
Table 2 - NQG132 Pin Functions by Pin Number (see Figure 3)

A1 GPIO5/INT_OUT INT_OUT : Interrupt Output GPIO
A2 NC No Connect NC
B1 GPIO7/ADC3 ADC3 : Auxiliary Input Channel 4 / Y- pin to 4 wire resistive touch screen GPIO
GPIO_TSC GPIO 6: General Purpose I/O # 6
(See Pins
A3 GPIO6/ADC1 ADC1 : Auxiliary Input Channel 2 / X- pin to 4-wire resistive touch screen GPIO
B57 – A71
also) GPIO 8: General Purpose I/O # 8
B2 GPIO8/ADC2 ADC2 : Auxiliary Input Channel 3 / Y+ pin to 4-wire resistive touch screen GPIO
ADC0 : Auxiliary Input Channel 1 / X+ pin to 4-wire resistive touch screen
A4 GPIO9/ADC0/MCLK_IN MCLK_IN : Master Clock Input GPIO
B3 GPIO10 GPIO 10: General Purpose I/O # 10 GPIO
A5 MIC_R- MIC_R-: Analog Microphone Differential Stereo Right Inverting Input A-I
MIC_R+: Analog Microphone Differential Stereo Right Non-Inverting Input A-I
B4 MIC_R+/DMICDAT2 DMICDAT2: Digital Microphone 2 Data Input D-I
MICBIAS : Microphone Right Bias A-O
AUDIO A6 MICBIAS_R/DMICSEL DMICSEL : Digital Microphone Select (Common to both inputs) D-O
MICBIAS : Microphone Left Bias A-O
B5 MICBIAS_L/DMICCLK DMICCLK : Digital Microphone Clock (Common to both inputs) D-O
MIC_L+ : Analog Microphone Differential Stereo Left Non-Inverting Input A-I
A7 MIC_L+/DMICDAT1 DMICDAT1 : Digital Microphone 1 Data Input D-I


B6 MIC_L- MIC_L- : Analog Microphone Differential Stereo Left Inverting Input A-I
A8 AFILT2 Microphone ADC Anti-Aliasing Filter Capacitor #2 A-I
B7 AFILT1 Microphone ADC Anti-Aliasing Filter Capacitor #1 A-I
A9 AGND_MIC Microphone Ground (Analog Ground) GND
B8 LISLP Line Input Stereo Left Non-Inverting A-I
A10 LISLM Line Input Stereo Left Inverting A-I
B9 LISRP Line Input Stereo Right Non-Inverting A-I
A11 LISRM Line Input Stereo Right Inverting A-I
B10 LLO_L Line Level Output, Left A-O
A12 AVREF Analog Reference A-O
B11 LLO_R Line Level Output, Right A-O
A13 ADC_REF ADC Reference Bypass Capacitor A-I
B12 VDD_AUDIO33 Filter Capacitor for Internal 3.3V AUDIO LDO A-O
A14 HP_L Left Headphone Output A-O
B13 HP_R Right Headphone Output A-O
A15 VIRT_GND Virtual Ground for Cap-Less Output A-O
B14 AGND Analog Ground GND
Input Voltage to LDOs for AUDIO Power
A16 LDO_IN3 (VDD_AUDIO33 & VDD_AUDIO18) AP-I
B15 LDO_GND LDO Ground GND
A17 NC No Connect NC
Always on Low Power LDO Output
A18 LDO_LP (Voltage Programmable to 3.0 V or 3.3 V) AP-O
A19 LDO_050_3 50mA LDO Output #3 (Voltage Range: 0.75-3.7 V) AP-O
B16 LDO_050_2 50mA LDO Output #2 (Voltage Range: 0.75-3.7 V) AP-O
LDO A21 LDO_IN2 Input Voltage to LDO_050_0, LDO_050_1, LDO_050_2 & LDO_050_3 AP-I
50mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
Note: This LDO also serves as the internal power source for I2S1, I2S2 and
I2CS. The external function of this pin is not affected but the voltage
register setting for this LDO will also govern the I/O level for I2S1, I2S2 and
A22 LDO_050_0 I2CS. AP-O
A23 LDO_IN1 Input Voltage to LDO_150_0, LDO_150_1 & LDO_150_2 AP-I
A24 LDO_150_0 150mA LDO Output #0 (Voltage Range: 0.75-3.7 V) AP-O
B20 32KHZ_OUT2 Buffered 32.768kHz Output #2 D-O
A25 CKGEN_GND PLL Analog Ground GND
32KHZ_CLKIN: External 32.768kHz Clock Input;
B21 32KHZ_CLKIN/XTALIN XTALIN : Input Pin when used with an external crystal A-I
XTALOUT: Output Pin when used with an external crystal
32KHZ_OUT1: when XTALIN is connected to a 32kHz input this pin can be
a 32kHz Output when CKGEN_PLL_STATUS register, 32KOUT1_EN (bit
A26 XTALOUT/32KHZ_OUT1 4) is set to 1. A-O
B22 VDD_CKGEN18 Filter Capacitor for Internal 1.8V CKGEN LDO A-IO
HXTALOUT: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz output
CK_GEN A27 HXTALOUT/TCXO_IN TCXO_IN: External 12 MHz, 13 MHz, 19.2 MHz or 26 MHz clock input TCXO-D-I
B23 VDD_CKGEN33 Filter Capacitor for Internal 3.3V CKGEN LDO A-IO
HXTALIN: 12 MHz, 13 MHz, 19.2 MHz, or 26 MHz crystal oscillator input
TCXO_OUT1: Buffered HXTALOUT/TCXO_IN Clock Output #1, 32.7638
A28 HXTALIN/TCXO_OUT1 KHz Output or 24 MHz PLL Output TCXO-D-O
Buffered HXTALOUT/TXCO_IN Clock Output #2, 12 MHz PLL Output or 48
B24 TCXO_OUT2 MHz PLL Output TCXO-D-O
A29 SYS_CLK 12MHz Output or Buffered Output of TCXO_IN D-O
B25 CKGEN_GND PLL Analog Ground GND
A30 USB_CLK 24 MHz or 48 MHz Output D-O
B26 VDDIO_CK Power Supply Input for TCXO_OUT1 and TCXO_OUT2 (1.1V – 1.9V) AP-I
ROM Select. EX_ROM = 1, read contents of external ROM. EX_ROM = 0,
A31 EX_ROM read contents of internal ROM into internal shadow memory. D-I
B27 DGND Digital Ground (1) GND
A32 I2S_BCLK2 I²S Bit Clock Channel 2 D-I
B28 I2S_WS2 I²S Word Select (Left/Right) Channel 2 D-I
I2C_I2S A33 I2S_SDIN2 I²S Serial Data IN Channel 2 D-I
B29 I2S_SDOUT2 I²S Serial Data OUT Channel 2 D-O
A34 I2S_WS1 I²S Word Select (Left/Right) Channel 1 D-I
B30 I2S_BCLK1 I²S Bit Clock Channel 1 D-I


A37 I2S_SDOUT1 I²S Serial Data OUT Channel 1 D-O
A38 I2S_SDIN1 I²S Serial Data IN Channel 1 D-I
B31 I2CS_SCL I²C Slave clock I2C-I/O
A39 I2CS_SDA I²C Slave data I2C-O
B32 I2CM_SCL I²C Master clock I2C-O
A40 I2CM_SDA I²C Master data I2C-I/O
B33 GND GND : Ground GND
A41 CLASS_D- Class-D Inverting Output A-O
B34 PGND Ground for Class D BTL Power Stage GND
CLASS_D
A42 PVDD Input Power for CLASS_D BTL Power Stage A-I
B35 CLASS_D+ Class-D Non-Inverting Output A-O
A43 BOOST5_SW2 Internally connected to pin A44 (BOOST_SW1) AP-O
B36 BOOST5_OUT BOOST5 Converter Output AP-O
A44 BOOST5_SW1 Internally connected to pin A43 (BOOST_SW2) AP-O
B37 BOOST5_GND Ground for BOOST5 Power Supply AP-I
A45 BUCK1000_FDBK BUCK2 Converter #2 - Feedback AP-I
B38 BUCK1000_IN BUCK2 Converter #2 - Input AP-I
A46 BUCK1000_OUT BUCK2 Converter Output #2 – 1000mA AP-O
B39 BUCK1000_GND Ground for BUCK2 Converter #2 GND
A47 BUCK500_1_FDBK BUCK1 Converter #1 – Feedback AP-I
B40 BUCK500_1_GND Ground for BUCK1 Converter #1 GND
A48 BUCK500_1_OUT BUCK1 Converter Output #1 - 500mA AP-O
B41 BUCK500_1_IN BUCK1 Converter #1 Input AP-I
DC_DC
A49 BUCK500_0_FDBK BUCK0 Converter #0 feedback AP-I
B42 BUCK500_0_GND Ground for BUCK0 Converter #0 GND
A50 BUCK500_0_OUT BUCK0 Converter Output #0 - 500mA AP-O
B43 BUCK500_0_IN BUCK0 Converter #0 Input AP-I
A51 LED_BOOST_VSENSE LED_BOOST Converter Output Voltage Sense Input to PWM Controller AP-I
B44 LED_BOOST_VIN LED_BOOST Converter GATE BIAS Supply AP-I
A52 LED_BOOST_ISENSE LED_BOOST Converter Output Current Sense Input to PWM Controller AP-I
B45 LED_BOOST_GATE LED_BOOST Converter GATE Drive to Power FET AP-I
A54 LED_BOOST_GND Ground for LED_BOOST AP-I
A55 LED_BOOST_SINK1 LED_BOOST Converter Current Sink for LED String #1 AP-I
B46 PSCREF Power Supply Current Reference AP-O
A57 LED_BOOST_SINK2 LED_BOOST Converter Current Sink for LED String #2 AP-I
B47 HSCTRL1 Hot Swap Control Input 1 D-I
A58 HSO1 Hot Swap Output 1 A-O
HOTSWAP B48 HSPWR Hot Swap Switches Power Input AP-I
A59 HSO2 Hot Swap Output 2 A-O
B49 HSCTRL2 Hot Swap Control Input 2 D-I
A60 CHRG_GND1 Pins A60 & B50 are the Power GND Pins for the Switching Regulator in the A-I
Charger. Due to their higher current requirement they are internally tied
B50 CHRG_GND2 together & must be connected externally at the PC board also. A-I
A61 CHRG_SW1 Pins A61 & B51connect to the inductor of the switch-mode step-down A-O
regulator for the Battery Charger. Due to their higher current requirement
they are internally tied together & must be connected externally at the PC
B51 CHRG_SW2 board also. A-O
A62 CHRG_INPUT1 Pins A62 & B52 provide 5V VBUS Input Power from the USB or from an AP-I
external wall mounted external supply. Due to their higher current
requirement they are internally tied together & must be connected
B52 CHRG_INPUT2 externally at the PC board also. AP-I
A63 CHRG_SYSVCC1 Pins A63 & B53 are System VCC Output (VSYS). Due to their higher current A-O
CHARGER requirement they are internally tied together & must be connected
B53 CHRG_SYSVCC2 externally at the PC board also. A-O
A64 CHRG_BAT1 Pins A64 & B64 form the positive battery lead connection to a single cell Li- AP-I/O
Ion/Li-Poly battery. Due to their higher current requirement they are internally
B54 CHRG_BAT2 tied together & must be connected externally at the PC board also. AP-I/O
A65 CHRG_CLSEN Input Current Limit Sense/filtering pin for current limit detection A-I
B55 CHRG_ICHRG Current setting. Connect to a current sense resistor AP-I/O
A66 CHRG_GATE Gate Drive for (Optional) External Ideal Diode A-O
B56 CHRG_NTC Thermal Sense, Connect to a battery‟s thermistor A-I
NTC Power output. This pin provides power to the NTC resistor string.
This output is automatically CHRG_SYSVCC level but only enabled when
A67 CHRG_VNTC NTC measurement is necessary to save power. AP-O


GND_BAT & ADCGND: Shared analog ground pin for battery charger and
B57 GND_BAT/ADCGND ADC. GND
A68 DGND Digital Ground GND
B58 POR_OUT Power-On-Reset Output, Active Low GPIO-OUT
A69 SW_DET Switch Detect Input GPIO
SW_OUT: Switch Detect Output
B59 GPIO1/SW_OUT/PENDOWN PENDOWN: PENDOWN Detect Output GPIO
GPIO_TSC
A70 GPIO3/LED2 LED2: Charger LED # 2 Indicates charging complete GPIO
B60 GPIO2/LED1 LED1: Charger LED # 1 Indicates charging in progress GPIO
CHRG_ILIM: Control the limit of the Charger Pre-Regulator. CHRG_ILIM =
A72 GPIO4/CHRG_ILIM 0, limit current to 500mA; CHRG_ILIM = 1, limit current to 1.5A. GPIO
I/O LEVELS BY TYPE

I/O TYPE DESCRIPTION
A-I, A-O & A-IO Analog Levels: Input, Output & Input/Output
AP-I, AP-O & AP-I/O Power Supply: Input, Output & Input/Output
D-I, D-O Digital Levels: Input, Output
Voltage levels are all digital levels (nominally 3.3V)
GND Ground: Any connection to Ground
GPIO-IN, GPIO-OUT, GPIO General Purpose: Input, Output, Input/Output.
Inputs are 3.3V
Outputs are VSYS with open-drain capable
I2C-I, I2C-O & I2CIO I²C: Input, Output & Input/Output
Inputs are CMOS
Outputs are open-drain.
TCXO-D-I, TCXO-D-O, TCXO-IO Clock: Input, Output, Input/Output
Inputs are 1.8V, Outputs are 1.1V to 1.9V

ABSOLUTE MAXIMUM RATINGS

Stresses above the ratings listed below can cause permanent damage to the P95020. These ratings are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect
product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
Transient t < 1ms,
CHRG_INPUT to CHRG_GND USB or Wall Charger Input Duty Cycle < 1% -0.3 7 V
CHRG_BAT to DGND Battery Input Source -0.3 5.5 V
CHRG_SYSVCC to DGND System VCC Output (Vsys) -0.3 5.5 V
PVDD to PGND CLASS_D BTL Input Power -0.3 6 V
LDO_IN1, IN2, IN3 to DGND Input voltage for LDO -0.3 6 V
BUCK500_0_IN to BUCK500_0_GND BUCK0 Input voltage -0.3 6 V
BUCK500_1_IN to BUCK500_1_GND BUCK1 Input voltage -0.3 6 V
BUCK1000_IN to BUCK1000_GND BUCK2 Input voltage -0.3 6 V
BUCK0, 1, 2 feedback
FDBK to DGND voltage -0.3 6 V
LED_BOOST Converter
LED_BOOST_VIN to LED_BOOST_GND gate bias supply -0.3 6 V
LED_BOOST_GATE to LED_BOOST Converter
LED_BOOST_GND Gate Drive to Power FET -0.3 LED_BOOST_VIN + 0.3 V
LED_BOOST_VSENSE to
LED_BOOST_GND Voltage Sense Input -0.3 LED_BOOST_VIN + 0.3 V
LED_BOOST_ISENSE to
LED_BOOST_GND Current Sense Input -0.3 LED_BOOST_VIN + 0.3 V
LED_BOOST_SINK to Current Sink for LED String
LED_BOOST_GND #1 or String #2 -0.3 6 V
BOOST5_OUT to BOOST5_GND BOOST5 Converter Output -0.3 6 V
BOOST5 Converter Power
BOOST5_SW to BOOST5_GND Switch1 and Switch2 -0.3 6 V
HSPWR to DGND Hot Swap Switches Power -0.3 6 V
Input voltage for Hot Swap
HSCTRL1, HSCTRL2 to DGND Control -0.3 HSPWR + 0.3 V
Power Supply for
VDDIO_CK to CKGEN_GND TCXO_OUT1, TCXO_OUT2 -0.3 2.5 V
TCXO_IN to CKGEN_GND Input voltage for TCXO_IN -0.3 VDD_CKGEN18 + 0.3 V
Input voltage for
32KHZ_CLKIN to CKGEN_GND 32KHZ_CLK -0.3 LDO_LP + 0.3 V
GPIO to DGND Input voltage for GPIO -0.3 CHRG_SYSVCC + 0.3 V
Input voltage for I2C Master
SDA, SCL to DGND or Slave -0.3 CHRG_SYSVCC + 0.3 V
Input volatge for I2S
BCLK, WS, SDOUT, SDIN to DGND channel 1 or 2 -0.3 LDO_050_0 + 0.3 V
EX_ROM to DGND External ROM enable -0.3 CHRG_SYSVCC + 0.3 V
AGND, LDO_GND, CKGEN_GND, GND,
PGND, BOOST5_GND,
BCUCK500_0_GND,
BCUCK500_1_GND, BUCK1000_GND,
LED_BOOST_GND, CHRG_GND,
GND_BAT/ADCGND to DGND -0.3 0.3 V
Operating Ambient
TA Temperature -40 to +85 °C
Operating Junction
TJ Temperature -40 to +125 °C
TS Storage Temperature -40 to +150 °C
TSOLDER Soldering Temperature 260°C for 10 seconds -
ESD: The P95020 is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can
accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the P95020
implements internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the
functionality or performance.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
CHRG_INPUT USB or Wall Charger Input 4.35V 5.5V V
CHRG_BAT Battery Input Source When Vbat providing power 3.0V 4.5V V
PVDD CASS_D BTL Input Power Supply 3.0V 5.0V V
LDO_IN1, IN2, IN3 Input voltage for LDO 3.0V 5.5V V
BUCK500_0_IN, BUCK0, 1, 2 Input voltage 3.0V 4.5V V
BUCK500_1_IN,
BUCK1000_IN
LED_BOOST_VIN LED Boost Converter gate bias supply 3.0V 5.5V V
VDDIO_CK voltage Power Supply for TCXO_OUT1, 1.1V 1.9V V
TCXO_OUT2
HSPWR Hot Swap Switches Power Supply Do not tie to ground or floating 3.0V 5.5V V
LDO_050_0 Power Supply for I2C Slave Channel, 1.7V 3.6V V
I2S Channel 1 and 2
TA Ambient Operating Temperature -40 85 °C
TJ Operating Junction Temperature -40 125 °C
DIGITAL INTERFACES - DC ELECTRICAL CHARACTERISTICS

I2C MASTER - ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, VLD0_LP=3.3V, TA = -40°C to +85°C
VIH Input High Voltage 0.7x VLD0_LP VSYS + 0.3 V
VIL Input Low Voltage -0.3 0.3x VLD0_LP V
Output Low Voltage
VOL IOL = 3 mA 0.4 V
(Open Drain)
I2C SLAVE - ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, TA = -40°C to +85°C
VLDO_050_0 Input Power Supply 1.7 3.6 V
VIH Input High Voltage 0.7x VLDO_050_0 VSYS + 0.3 V
VIL Input Low Voltage -0.3 0.3x VLDO_050_0 V
VOL Output Low Voltage IOL = +3 mA 0.4 V
I2S - ELECTRICAL CHARACTERISTICS

VLDO_050_0 Input Power Supply 1.7 3.6 V
VIH Input High Voltage 0.7x VLDO_050_0 VSYS + 0.3 V
VIL Input Low Voltage -0.3 0.3x VLDO_050_0 V
IOH = -1mA, VLDO_050_0 = 3.3V 0.9x VLDO_050_0 V
VOH Output High Voltage IOH = -1mA, VLDO_050_0 = 2.5V 0.9x VLDO_050_0 V
IOH = -100uA, VLDO_050_0 = 1.8V VLDO_050_0 - 0.2 V
VOL Output Low Voltage IOL = 1mA 0.1x VLDO_050_0 V
GPIO - ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, VLD0_LP=3.3V, TA = -40°C to +85°C
VIH Input High Voltage 0.7x VLD0_LP VSYS + 0.3 V
VIL Input Low Voltage -0.3 0.3x VLD0_LP V
VOH Output High Voltage IOH = -2mA 0.9x VSYS V
VOL Output Low Voltage IOL = 2mA 0.1x VSYS V

OVERALL POWER CONSUMPTION

MODE DESCRIPTION CHARGE_BAT TYPICAL
CONSUMPTION
Sleep USB or Wall Adaptor is not present, a main battery is present and well-chaged. Always Vbat = 3.8V TBD
on LDO_LP is on, RTC is on and RTC registers are maintained. Wake-up capabilities
(Switch Detect Input) are available.
Standby USB or Wall Adaptor is not present, a main battery is present and well-chaged. Always Vbat = 3.8V TBD
on LDO_LP is on, all DC-DC Bucks in PFM mode. All LDO's are on, no load.
Touch USB or Wall Adaptor is not present, a main battery is present and well-charged. Vbat = 3.8V TBD
Controller Always on LDO_LP is on, touch screen controller is on, LDO_050_0 is on.
Standby
AUDIO POWER CONSUMPTION

MODE CHRG_BAT LDO_050_0 VDD_AUDIO18 VDD_AUDIO33 PVDD CHRG_BAT PVDD Total
Power
(V) (V) (V) (V) (V) (mA) (mA) (mW)
Playback to 4Ω 3.3 2.3 1.5 3.0 3.0 52 7 192
speaker, sampling at 3.8 3.3 1.8 3.3 3.3 60 7 252
96 kHz, no signal 4.2 3.6 1.8 3.6 5.0 60 10 302
Playback to 4Ω 3.3 2.3 1.5 3.0 3.0 53 155 640
96 kHz, 0dB FS 1 kHz 4.2 3.6 1.8 3.6 5.0 61 258 1546
signal
Playback to 8Ω 3.3 2.3 1.5 3.0 3.0 52 6 190
48 kHz, no signal 4.2 3.6 1.8 3.6 5.0 59 10 298
Playback to 8Ω 3.3 2.3 1.5 3.0 3.0 52 96 460
48 kHz, 0dB FS 1 kHz 4.2 3.6 1.8 3.6 5.0 60 163 1067
signal
Playback to 16Ω 3.3 2.3 1.5 3.0 3.0 54 0 178
headphone, sampling 3.8 3.3 1.8 3.3 3.3 58 0 220
at 96 kHz, no signal 4.2 3.6 1.8 3.6 5.0 60 0 252
Playback to 16Ω 3.3 1.7 1.5 3.0 3.0 120 0 396
headphone, sampling 3.8 3.3 1.8 3.3 3.3 133 0 506
at 96 kHz, 0dB FS 1 4.2 3.6 1.8 3.6 5.0 135 0 567
kHz signal
Playback to 16Ω cap- 3.3 2.3 1.5 3.0 3.0 55 0 182
less headphone, 3.8 3.3 1.8 3.3 3.3 60 0 228
sampling at 96 kHz, 4.2 3.6 1.8 3.6 5.0 62 0 260
no signal
Playback to 16Ω cap- 3.3 2.3 1.5 3.0 3.0 122 0 403
less headphone, 3.8 3.3 1.8 3.3 3.3 135 0 513
sampling at 96 kHz, 4.2 3.6 1.8 3.6 5.0 137 0 576
0dB FS 1 kHz signal
Stereo playback 3.3 2.3 1.5 3.0 3.0 41 7 156
bypassing ADC and 3.8 3.3 1.8 3.3 3.3 48 7 206
DAC to Class-D 4Ω 4.2 3.6 1.8 3.6 5.0 48 10 252
speaker, no signal
Record mode – 3.3 2.3 1.5 3.0 3.0 45 0 149
Stereo Line-In to 3.8 3.3 1.8 3.3 3.3 49 0 186
ADC0 sampling at 96 4.2 3.6 1.8 3.6 5.0 50 0 210
kHz, no signal
Record mode – 3.3 2.3 1.5 3.0 3.0 43 0 142
Analog microphone 3.8 3.3 1.8 3.3 3.3 47 0 179
I/P to ADC1 sampling 4.2 3.6 1.8 3.6 5.0 47 0 198
at 16 kHz, no signal
Record mode – 3.3 2.3 1.5 3.0 3.0 45 0 149
Analog microphone 3.8 3.3 1.8 3.3 3.3 49 0 186
I/P to ADC1 sampling 4.2 3.6 1.8 3.6 5.0 50 0 210
at 96 kHz, no signal

1.0 OVERVIEW
The P95020 is an integrated device that combines a microcontroller, power management, battery charging, touch screen
controller, system monitoring, clock synthesis, real time clock and audio functionality. All of these subsystems are
configured, monitored and controlled by either the on-chip Microcontroller or by an external controller (Application
Processor) over an I²C interface. The external Application Processor can monitor and control functions within P95020
even when the internal Microcontroller is enabled. The registers for the various sub functions allow access from more
than one controller through an arbitration mechanism implemented in hardware.
VBUS SW L
VSYS to System
(From USB VBUS External
or wall adpapter) PWM VSYS PMOS
Charger Ideal Diode
CLSEN Ideal
or GATE (Optional)
Diode
Discharger 0V VBAT Single Cell
NTC +
Battery Li-Ion Battery
VNTC VIN
ICHRG Charger
BOOST_LED
Micro- Voltage to LEDs
Backlight Driver &
controller VSENSE
Current Sinks for SINK 1
LEDs SINK 2
ISENSE
SDA I2C Master LDO_IN1
SCL
LDO 150 mA V_Output
(0.75v-3.7V)
SDA I2C Slave
SCL LDO 150 mA V_Output
(0.75v-3.7V)
SW_DET SW_DET
LDO 150 mA V_Output
Real Time (0.75v-3.7V)
LDO_IN2
Clock LDO 50 mA
V_Output
10 pin (0.75v-3.7V)
interface M ADC/Touch LDO 50 mA
U (0.75v-3.7V) V_Output
X
10 GPIO LDO 50 mA
(0.75v-3.7V) V_Output
POR_OUT POR_OUT
HSPWR LDO 50 mA
HSCTRL1 (0.75v-3.7V) V_Output
Hot Swap
HSO1
HSCTRL2 Switches
LDO 1mA (3.0V
HSO2 or 3.3V) V_Output
5V Boost DC-DC Buck

V_Output V_Output
1000 mA
Mic In
Line In DC-DC Buck_1
2
I S Channel 1 In Audio Codec V_Output
I2S Channel 2 In Headphone 500 mA
2
I S Channel 1 Out Amp
I2S Channel 2 Out Class-D DC-DC Buck_0
Line Out V_Output
Amp 500 mA
Headphone Out
Class-D Out
Power
TCXO_OUT Clock On
SYS_CLK Oscillator
USB_CLK Generator Reset
Figure 4 – Overall System Functional Diagram.

1.1 FUNCTIONAL MODES

There are two primary functional modes for operation: external processor only or simultaneous internal and external
processor operation.
External Processor Control

In this mode of operation the external processor can access all internal registers via the I²C interface and receive
interrupts via an interrupt pin, and the internal Microcontroller can be powered down or clock gated off.
Combined Internal and External Processor Operation

In this mode of operation the Microcontroller in the P95020 will function autonomously or semi-autonomously based on
the content of the on-board or external ROM. The external Application Processor may or may not perform additional
control functions through the I²C bus interface. Individual time-based or event-based interrupts generated inside the
P95020 device may be routed internally or externally to be handled separately. All I²C registers can be simultaneously
2
accessed by either the external Application Processor or the internal Microcontroller. Access to the I C registers is
arbitrated via on-chip hardware arbitration.

1.2 REGISTER MAP

All the P95020 control and status registers accessible to the Microprocessor are mapped to a 1024 location address
space. This address space maps to:
4 x 256 Bytes of I²C pages for the I²C slave interface
1024 consecutive addresses in the embedded Microprocessor address space
For easy access from the I²C slave interface (by default 256 Bytes oriented) the first 16 registers of each page are global
for all the pages.
Each Module is allocated a consecutive address space.
Register address computation: Address = Base Address + Offset Address
The Base addresses (for both I²C and embedded uP) are listed in the following table. The Offset addresses are defined in
different functional Modules. The offset address is labeled as “Offset Address” in the Module Register definition sections.
Table 3 – Register Address Global Mapping
Size Base Address Base Address Register Definition
Module Module Description
(Bytes) (I²C) (6811 P) Location
Global registers are used by the Access
Page-x:
Global Registers 16 0xA000 Page 120 Section 15.7 Manager, the first 16 registers of each page
000(0x00)
are global for all the pages.
Page-0: Access manager, including an I²C slave and
ACCM 16 0xA010 Page 123 Section 15.8
016(0x10) bus arbiter
Power controller, including registers that
Page-0: Page 108 Section 13.7.1 control the on/off of the regulators, and
PCON 32 0xA020
032(0x20) control/sense of the GPIO, power states
Page 64 Section 4.7 Clock Generator Registers
Page-0:
RTC 32 0xA040 Page 67 Section 5.2 Real Time Clock
064(0x40)
Page-0: Linear regulators, including regulators for
LDO 32 0xA060 Page 127 Section 16.6
096(0x60) external and internal usage
Switching regulators and Class-D BTL driver
Page-0:
DC_DC 16 0xA080 Page 74 Section 7.0 consisting of three bucks, one 5V boost , one
128(0x80)
white LED driver and one Class-D BTL driver
Battery Charger, including a dedicated
Page-0:
CHARGER 16 0xA090 Page 55 Section 3.5 switching buck regulator, an ideal diode, a
144(0x90)
precision reference and thermal sensor
Page-0:
GPT 16 0xA0A0 Page 71 Section 6.2 General purpose timers
160(0xA0)
Page-0:
RESERVED 16 0xA0B0 RESERVED
176(0xB0)
Touch-screen (ADC, pendown detect and
Page-0:
ADC_TSC 64 0xA0C0 Page 100 Section 12.4 switches, temperature and battery voltage
192(0xC0)
monitoring), and GPIOs
Page-1:
AUDIO 240 0xA100 Page 40 Section 2.15 Audio subsystem, excluding class-D amplifier
000(0x00)
Page-2:
CLASS_D_DIG 240 0xA200 Page 32 Section 2.13 Class-D amplifier digital processing part
000(0x00)
Page-3:
RESERVED 240 0xA300 RESERVED
000(0x00)

1.3 BYTE ORDERING AND OFFSET

Most registers are defined within one byte width and occupy one byte in the address space. Some registers occupy more
than one byte. Please refer to the individual register descriptions for information on how that register is stored in address
space.
1.4 REGISTER ACCESS TYPES
TYPE MEANING
RW Readable and Writeable
R Read only
RW1C Readable and Write 1 to this bit to clear it (for interrupt status)
RW1A Readable and Write 1 to this bit to take actions
1.5 RESERVED BIT FIELDS

Bit fields and Bytes labeled RESERVED are reserved for future use. When writing to a register containing some
RESERVED bits, the user should do a “read-modify-write” such that only the bits which are intended to be written are
modified.
DO NOT WRITE to registers containing all RESERVED bits.

2.0 AUDIO MODULE

FEATURES DESCRIPTION
 4 Channels (2 stereo DACs and 2 stereo ADCs) with 24-bit The audio system is a low power optimized, high fidelity,
4-channel audio codec with integrated Class D speaker
resolution
 Supports full-duplex stereo audio amplifier, cap-less headphone amplifier. It provides high
 Provides a mono output quality HD Audio capability for handheld applications.
 2.5W mono speaker amplifier @ 4 ohms and 5V
 Stereo cap-less headphone amplifier
 Two digital microphone inputs
 Mono or stereo operation
 Up to 4 microphones in a system
 High performance analog mixer

 2 adjustable analog microphone bias outputs
Figure 5 – Audio Block Diagram
2.1 AUDIO - PIN DEFINITIONS

Pin # PIN_ID DESCRIPTION
007 MIC_R- Differential Analog microphone negative input (right channel)
008 MIC_R+/DMICDAT2 Differential Analog microphone positive input (right channel) or second digital microphone data input
009 MICBIAS_R/DMICSEL Analog microphone supply (right channel) or digital microphone select output (GPO)
010 MICBIAS_L/DMICCLK Analog microphone supply (left channel) or digital microphone clock output
011 MIC_L+/DMICDAT1 Differential Analog microphone positive input (left channel) or first digital microphone data input

012 MIC_L- Differential Analog microphone negative input (left channel)

013 AFILT2 ADC filter cap
014 AFILT1 ADC filter cap
015 AGND_MIC Return path for microphone supply (MICBIAS_L/R )
016 LISLP Differential Analog Line Level positive input (left channel)
017 LISLM Differential Analog Line Level negative input (left channel)
018 LISRP Differential Analog Line Level positive input (right channel)
019 LISRM Differential Analog Line Level negative input (right channel)
020 LLO_L Single Ended Line Level Output (Left channel)
021 LLO_R Single Ended Line Level Output (Right channel)
022 AVREF Analog reference (virtual ground) bypass cap
023 VDD_AUDIO33 Filter Capacitor for Internal 3.3V Audio LDO
024 ADC_REF ADC reference bypass cap
025 HP_R Cap-less headphone output (right channel)
026 HP_L Cap-less headphone output (left channel)
027 AGND Analog (audio) return
028 VIRT_GND Cap-less headphone signal return (virtual ground)
2.2 AUDIO - SECTION OVERVIEW

The Audio section can be divided into seven subsections.
Analog Input Buffer & Converter Block
DAC, ADC
Audio Mixer Block
Analog and Class D Output Blocks
Sub System Control and Interface Blocks
Note: All register settings are lost when power is removed.
2.3 AUDIO - ANALOG PERFORMANCE CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VSYS = 5V, TA = -40°C to +85°C,
(VCC_AUDIO33 = 3.3V, VDD_AUDIO18 = 1.8V, AGND = DGND = 0V, TA = 25 ° C; 1 kHz input sine wave, Sample Frequency = 48 kHz, 0 dB = 1 VRMS
into 10 KΩ)
MIN TYP MAX UNIT

PARAMETER CONDITIONS
Full Scale Input Voltage:
All Analog Inputs except Mic (0 dB gain) 1.0 V rms
Differential Mic Inputs (+30dB gain) 30.0 mV rms
Differentail Mic Inputs (0 dB gain) 1.0 V rms
Full Scale Output Voltage:
Line Input to Line Output 1.0 V rms
HP Output Per channel / 16 ohm load 0.707 V rms
PCM (DAC) to LINE_OUT 1.0 V rms
Headphone output power Per channel / 16 ohm load 45 50 55 mWpk
± 1 dB limits. The max frequency response is 40 kHz if the
Analog Frequency Response 10 30,000 Hz
sample rate is 96 kHz or more.
The ratio of the rms output level with 1 kHz full scale input to
the rms output level with all zeros into the digital input.
Digital S/N Measured “A weighted” over a 20 Hz to a 20 kHz bandwidth.
(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-
noise ratio) – At Line_Out pins.
D/A PCM (DAC) to LINE_OUT 95 dB
A/D LINE_IN to PCM 90 dB
Ratio of Full Scale signal to noise output with -60 dB signal,
Dynamic Range: -60dB signal level
measured “A weighted” over a 20 Hz to a 20 kHz bandwidth.
LINE_IN to LINE_OUT (direct) 98 dB
LINE_IN to LINE_OUT (mixer) 95 dB
LINE_IN to HP (direct) 90 dB

LINE_IN to HP (mixer) 90 dB
DAC to LINE_OUT 93 dB
LINE_IN to A/D 90 dB
THD+N ratio as defined in AES17 and outlined in AES6id,
non-weighted, at 1 kHz. Tested at -3 dB FS or equivalent for
Total Harmonic Distortion:
analog only paths. 0 dB gain (PCM data -3 dB FS, analog
input set to achieve -3 dB full scale port output level)
LINE_IN to LINE_OUT (direct) 90 dB
LINE_IN to LINE_OUT (mixer) 80 dB
DAC to LINE_OUT 85 dB
DAC to HP (10 KΩ) 80 dB
DAC to HP (16 Ω) 55 dB
LINE_IN to ADC 80 dB
AMIC to ADC 80 dB
± 0.25 dB limits. The D/A freq. response becomes 40 kHz
D/A Frequency Response 18 22,000 Hz
with sampling rates > 96 kHz. At ±3 dB the response range
is from 20-22,500 Hz at 48 kHz, or 20-20,000 Hz @
A/D Frequency Response 44.1 kHz or 20-45,000 Hz @ 96 kHz. 20 20,000 Hz
Transition Band Transition band is 40-60% of sample rate. 19,200 28,800 Hz

Stop Band Stop band begins at 60% of sample rate 28,800 Hz
Stop Band Rejection 85 dB
The integrated Out-of-Band noise generated by the DAC
process, during normal PCM audio playback, over a
Out-of-Band Rejection 45 dB
bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC
output.
Power Supply Rejection Ratio (1 kHz) 70 dB
Crosstalk between Input channels 85 dB
DAC Volume/Gain Step Size 0.75 dB
ADC/Mixer Volume/Gain Step Size 1.5 dB
Analog Mic Boost Step Size 10 dB
Input Impedance 50 K
Differential Input Impedance 20 K
Input Capacitance 15 pF
Mic Bias 2.97 V
External Load Impedance 6 k
2.4 AUDIO - MICROPHONE INPUT PORT

The microphone input port supports either analog or digital microphones. The analog and digital modes share pins so
only one mode is supported in a typical application.
2.4.1 AUDIO - Analog Microphone Input mode

The Analog Microphone input path consists of:
Stereo Differential Input Analog Microphone Buffer
 L/R swap
 Mono or stereo
 Microphone Bias Generator with 2 independent bias outputs.
 Microphone Boost Amplifier with selectable gain of 10, 20, or 30dB
The analog microphone interface provides a stereo differential input for supporting common electret cartridge
microphones in a balanced configuration (a single-ended configuration is also supported). A boost amplifier provides up
to 30dB of gain to align typical microphone full scale outputs to the ADC input range. The microphone input is then routed

to both ADC1 and the analog mixer for further processing. By using the analog mixer the analog microphone input may
be routed to ADC0, the line output port or the headphone output port.
2.4.2 AUDIO - Digital Microphone Input mode

The Digital Microphone Input path consists of:
Digital Microphone input buffer and MUX with the following features:
 One or two microphones per DMICDATx input.
 Mono data sampled during high or low clock level.
 L/R swap
 Versatile DMICSEL output pin for control of digital microphone modules or other external circuitry. (Used primarily to
enable/disable microphones that do not support power management using the clock pin.)
The digital microphone interface permits connection of a digital microphone(s) via the DMICDAT1, DMICDAT2, and
DMICCLK 3-pin interface. The DMICDAT1 and DMICDAT2 signals are inputs that carry individual channels of digital
microphone data to the ADC. In the event that a single microphone is used, the data is ported to both ADC channels.
This mode is selected using a register setting and the left time slot is copied to the ADC left and right inputs. The digital
microphone input is only available at ADC1.
The DMICCLK output is controllable from 4.704 MHz, 3.528 MHz, 2.352 MHz, 1.176 MHz and is synchronous to the
internal master clock (MCLK). The default frequency is 2.352 MHz.
To conserve power, the analog portion of the ADC and the analog boost amplifier will be turned off if the D-mic input is
selected. When switching from the digital microphone to an analog input to the ADC, the analog portion of the ADC will
be brought back to a full power state and allowed to stabilize before switching from the digital microphone to the analog
input. This should take less than 10mS.
The P95020 codec supports the following digital microphone configurations:
Table 4 - Valid Digital Mic Configurations
DIGITAL DATA
MODE INPUT NOTES
MICS SAMPLE
0 0 N/A N/A No Digital Microphones (1010 bit pattern sent to ADC to avoid pops)
Two microphones connected to DMICDAT1. PhAdj settings apply to Left microphone.

1 2 Double Edge DMICDAT1
Right Microphone sampled on opposite phase. DMICDAT2 ignored.
Two microphones connected to DMICDAT2. PhAdj settings apply to Left microphone.

2 2 Double Edge DMICDAT2
Right Microphone sampled on opposite phase. DMICDAT1 ignored.
DMICDAT1
3 2 Single Edge and DMICDAT1 used for left data and DMICDAT2 used for right data.
DMICDAT2
DMICDAT1 Two microphones, one on each data input. “Left” microphone used for each channel. Two
3 2 Double Edge and “Right” microphones may be used by inverting the microphone clock or adjusting the
DMICDAT2 sample phase.

Off-Chip On-Chip
Digital
Microphones On-Chip
Multiplexer
DMICDAT1 Stereo Channels
Left Output
Left/Right
MUX
Pin STEREO
ADC1
DMICDAT2 Right
DMICCLK
Pin
Microphone not supporting multiplexed output.

Left
DMICDAT1 Valid Data Valid Data Valid Data
Channel
Right
DMICDAT2 Valid Data Valid Data Valid Data
Channel
Left & Right
Channel
DMICCLK
Dual “Left” Microphone. Mics support multiplexed output.

Left Valid Valid Valid Valid
Channel DMICDAT1 Data Data Data Data
AND
Right DMICDAT2 Valid Valid Valid Valid
Channel Data Data Data Data
Left & Right
Channel
DMICCLK
Figure 6 –Stereo Digital Microphone (Mode 3)

Off-Chip On-Chip
Digital
Microphones DMICDAT1 On-Chip
OR Multiplexer
DMICDAT2 Stereo Channels
Output
MUX
Pin STEREO
Shared
ADC1
Data Input
DMICCLK
Pin
DMICDAT1
Valid Valid Valid Valid Valid
OR
Data R Data L Data R Data L Data R
DMICDAT2
Right Left
Channel Channel
DMICCLK
Figure 7 –Stereo Digital Microphone (Mode 1 & 2)
2.5 AUDIO - ANALOG LINE INPUT

The Analog Line Input path consists of a stereo differential input analog buffer that is routed to the analog mixer and
ADC0. By using the analog mixer, the analog line input may be routed to ADC0, the line output port or the headphone
output port.
2.6 AUDIO - DAC, ADC

There are 2 stereo DACs and 2 stereo ADCs. All converters support sample rates of 8kHz, 11.025khz, 12kHz,
22.050kHz, 16kHz, 24kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz. Word lengths of 16, 20 and 24-bits are selectable.
2.6.1 AUDIO - DAC 0/1

The DAC sample rate and word length are programmed at the I²S input port and the DAC may select either I²S port as the
data source.
Digital volume control provides -95.25 dB to 0dB gain in 0.75 dB steps and mute. The output of DAC0 and DAC1 is sent
to the analog mixer, the headphone output and the line output.
2.6.2 AUDIO - ADC 0/1

Each ADC includes a high pass filter to remove DC offsets present in the input path. Sample rate, word length, and
source ADC are programmed at the I²S output port. If an ADC is selected as the data source for more than one sink (I²S
output or DAC) then the rates must be programmed the same at all sinks. If the rates are not identical, then the highest
priority sink will dominate (I2Sout1, I2Sout2, and DAC). The other sink will be muted under these circumstances. ADC0

includes an analog amplifier (0-22.5dB gain in 1.5dB steps) and a multiplexer to select between the line input path or the
analog mixer output.
Note: there is only 1 L/R clock per I²S I/O port. Therefore the input and output rates for that port match.
2.7 AUDIO - AUTOMATIC GAIN CONTROL

The P95020 incorporates digital automatic gain control in the ADC1 record path to help maintain a constant record level
for voice recordings. The AGC maintains the recording level by monitoring the output of the ADC and adjusting the Boost
(analog for analog microphone path or digital for digital microphone path) and digital record gain to compensate for
varying input levels. While the AGC is enabled, the digital record gain and boost register values are ignored.
The AGC target level may be set from -1.5 dB to -22.5
dB relative to the ADC full scale output code in 1.5 dB
steps. The maximum gain allowed may be
programmed to prevent the AGC from using the entire
gain range. The AGC may be applied to either both
channels or only the right or left channel. The AGC
uses both channels to determine proper record level
unless only one channel is selected. When only one
channel is enabled, the other channel is ignored and
that channel‟s gain is controlled by its record gain and
boost register values.
Delay time is the amount of delay between when the AGC Target
Level
peak record level falls below the target level and when
the AGC starts to adjust gain. The delay time may be
set from 0 ms to 5.9 seconds in 16 steps. Each step is
twice as long as the previous step where 0 is the first
step.
Each additional step may be calculated by:
n
((8*2 )/44100) seconds
where n is the register value from 1 to 15
Decay time is the time that the AGC takes to ramp up
across its gain range. The time needed to adjust the Delay Decay Attack
recording level depends on the decay time and the
amount of gain adjustment needed. If the input level is Figure 8 – Automatic Gain Control
close to the target level then a relatively small gain adjustment will be needed and will take much less than the
n+10
programmed decay time. Decay time is adjustable from 23.2 ms to 23.8 seconds and may be calculated as (2 /44100)
where n is the register value from 0 to 10. Register values above 10 set the decay to 23.8 seconds.
Attack time is the time that it takes the AGC to ramp down across its gain range. As with the decay time, the actual time
needed to reach the target recording level depends on the attack time and the gain adjustment needed. The attack time
n+8
is adjustable from 5.8 ms to 5.9 seconds and may be calculated as (2 /44100) where n is the register value from 0 to 10.
Register values above 10 set the decay to 5.9 seconds.
The P95020 also provides a peak limiter function. When the AGC is on, quiet passages will cause the gain to be set to
the maximum level allowed. When a large input signal follows a quiet passage, many samples will become clipped as the
AGC adjusts the gain to reach the target record level. Long attack times aggravate this situation. To reduce the number
of clipped samples the peak limiter will force the attack rate to be as fast as possible (equivalent to zero (0) value in the
attack register) until the record level is 87.5% of full scale or less.
To prevent excessive hiss during quiet periods, a signal threshold level may be programmed to prevent the AGC circuit
from increasing the gain in the absence of audio. This is often referred to as a „noise gate‟ or „squelch‟ function. The
signal threshold may be programmed from -72 dB FS to -24 dB FS in 1.5 dB increments.
Under some circumstances, it is desirable to force a minimum amount of gain in the record path. When the AGC is in
use, the minimum gain may be set from 0 to 30 dB to compensate for microphone sensitivity or other needs.
2.8 AUDIO - ANALOG MIXER BLOCK

The Audio subsection implements an analog mixing block for use as an input or output mixer.
The Audio Mixer Block consists of:
Input Volume Controls

DAC0
DAC1
Line Input
Analog Mic (in analog mic mode only.)
Master Volume Control
The analog mixer has 4 input sources. Each input has an independent volume control that provides gain from -34.5 dB to
+12 dB (1.5 dB steps) and mute. After mixing, the output may be attenuated up to 46.5 dB (1.5 dB steps) before being
sent to ADC0, the headphone output port and the line output port.
2.9 AUDIO - DIGITAL AUDIO INPUT/OUTPUT INTERFACE

The Digital Audio Input/ Output Interface consists of:
Dual I²S input/output interface with independent bit rate/depth
Each I²S input/output pair will operate at same bit rate/depth
MCLK is shared and may be programmed for 64, 128, 256, or 384 times the base rate (44.1 kHz or 48 kHz)
The MCLK is used to align the I²S port signals to the host.
PCON Register – MCLK_CFG: I²C Address = Page-0: 55(0x37), µC Address = 0xA037

Default User
Bit Bit Name Value Description / Comments
Settings Type
Only meaningful when MCLK_SEL bit is set. See
[2:0] MCLK_RATE 000b RW
table below.
Only meaningful when MCLK_SEL bit is set. See
3 MCLK_DIV2 0b RW
table below.
0 = MCLK to audio selected from
GPIO9 pin
4 MCLK_FROM_I2S 0b RW
1 = MCLK to audio selected from
I2S_BCLK2 pin
0 = MCLK is selected from MCLK I/O
MCLK I/O does not bond out due to pin-count
5 MCLK_REMAP_EN 0b RW 1 = MCLK is selected from I2S or
constraint
GPIO9 pin
6 RESERVED 0b RW RESERVED
0 = Audio clock source from 48 MHz
7 MCLK_SEL 0b RW clock from CLKGEN MCLK source selection
1 = Audio Clock source from MCLK
Table 5 - MCLK Rate selection: MCLK_DIV2: MCLK_RATE

MCLK_DIV2:MCLK_RATE[2:0] MCLK Input frequency Comments
00xx 12.288M
0100 11.2896M
0101 18.432M
0110 16.9344
0111 12M
10xx 24.576M
1100 22.5792M
1101 36.864M
1110 33.8688M
1111 24M

Table 6 – MCLK/Sample Rate

Mclk (div = 0) Mclk (div = 1) Sample Rate USB Mode Mclk/Sample Rate
12.288MHz 24.576MHz 96KHz 0 128
48KHz 256
24KHz 512
16KHz 768
12KHz 1024
8KHz 1536
11.2896MHz 22.5792MHz 88.2KHz 128
44.1KHz 256
22.050KHz 512
11.025KHz 1024
18.432MHz 36.864MHz 96KHz 192
48KHz 384
24KHz 768
16KHz 1152
12KHz 1536
8KHz 2304
16.9344MHz 33.8688MHz 88.2KHz 192
44.1KHz 384
22.050KHz 768
11.025KHz 1536
12.000MHz 24.000MHz 96KHz 1 125
48KHz 250
24KHz 500
16KHz 750
12KHz 1000
8KHz 1500
88.2KHz 20000/147
44.1KHz 40000/147
22.050KHz 80000/147
11.025KHz 160000/147
Two independent serial digital I/O ports provide access to the internal converters. Each port provides a stereo input and
output with shared clocks. The ports support slave mode operation only (clocks supplied by host). Each port may be
programmed for 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.050 kHz, 24 kHz, 44.1 kHz, 48 kHz, 88.2 kHz or 96 kHz
operation. I²S, Left justified and Right justified formats support 16, 20 and 24-bit word lengths.

2.10 AUDIO - REFERENCE VOLTAGE GENERATOR, BUFFER, & FILTERING CAPS

AVREF
The AVREF pin is part of the internal virtual ground reference generator. A capacitor placed between AVREF and
AGND is necessary for acceptable power supply rejection and anti-pop performance. A capacitor of 10 F is
recommended to provide about a 10 second ramp-up time.
ADCREF
The ADC reference also requires a capacitor of at least 1 µF for proper operation.
AFILT
ADC1 augments its internal filter capacitors with external filter capacitors to reduce noise outside of the audio
band before sampling. 1000 pF capacitors connected from the AFILT1 and AFILT2 pins to AGND are
recommended but larger capacitors may be used if reduced signal bandwidth is acceptable. Process variation
will cause bandwidth to vary from part to part. A 1000 pF capacitor will place the filter pole far outside of the 20
kHz bandwidth supported so that the ±1 dB 20 kHz bandwidth limit is guaranteed.
2.11 AUDIO - ANALOG AND CLASS D OUTPUT BLOCK

The Audio subsection provides support for line level, headphone and speaker outputs.
The analog line output port features a source MUX and single ended output buffer designed to drive high impedance
loads. This port has selectable 0/3/6 db gain for -6 dBV, -3 dBV or 0 dBV DAC output levels respectively. The Cap-less
Stereo Headphone Output port is similar to the line level output port but can drive 32 ohm headphones and may operate
without DC blocking capacitors by connecting the physical headphone‟s ground return to the VIRT_GND pin.
A CLASS_D Mono BTL Output and Class D Stereo Processor w/ digital volume control (See CLASS_D section for more
information) provides up to 2.5 W of output power into a 4 ohm speaker.
The line output port, headphone port and CLASS_D BTL Power Output can select from the mixer, DAC0, DAC1 or the
line input (LINE_IN). The line input selection is intended for very low power LINE_IN to LINE_OUT pass-thru when
VDD_AUDIO33 and VDD_AUDIO18 power on, and config LINE_OUT_SCTRL (Setting 2h, see Section 2.15.24) to select
LINE_OUT from LINE_IN.

2.12 AUDIO - CLASS-D BTL AMPLIFIER

P95020 implements a digital Class-D 2.5W (4 ) BTL amplifier which supports both 8 and 4 loads. Gain for the BTL
amplifier is programmable from -91 dB to +36 dB in 0.5 dB steps using the Volume 0/1 registers. Gain changes and mute
may be applied immediately, on zero crossing or ramped from the current to target value slowly. These settings are
controlled using the Gain Control HI/LO registers.
2.12.1 AUDIO - EQ
There are 5 bands of parametric EQ (bi-quad) per channel. Due to the flexibility of the bi-quad implementation, each filter
band may be configured as a high-pass, low-pass, band-pass, high shelving, low shelving or other function.
Each band has an independent set of coefficients. A bi-quad filter has 6 coefficients. One coefficient is normalized to 1
and 5 are programmed into the core. Each band supports up to +15 dB boost or up to -36 dB cut.
2.12.2 AUDIO - Coefficients

The following equations describe each filter band. The fundamental equation is a bi-quadratic of the form:
b0  b1z 1  b2 z 2
H ( z) 
a 0  a1z 1  a 2 z 2
Rearranging slightly we can see that normalizing a0 or b0 can reduce the number of stored coefficients.
1
b1 z 1  b2 z 2
 b0  b0 b0
H ( z )    
 a 0  1  a1 z 1 
a2 2
z
a0 a0
Implementation generally takes the form:
 b0   b1   b2   a1   a2 
yn    xn    xn  1    xn  2    yn  1    yn  2
 a0   a0   a0   a0   a0 
It can be seen that 5 coefficients are needed, and if a0 is set to 1 then only b0, b1, b2, a1, and a2 are needed. To
compensate for the total gain realized from all 5 bands the EQ amplitude is adjusted to prevent saturation. Each channel
has an inverse gain coefficient that is used to compensate for the gain in the EQ bands. So, for 5 bands/channel with 5
coefficients/band + inverse gain/channel, there are a total of 52 values needed.
These values are pre-calculated and programmed into RAM before use. The default values should be benign such as an
all-pass implementation, but it is permissible to implement other transfer functions.
2.12.3 AUDIO - Software Requirements

The EQ must be programmed before enabling (bypass turned off). {Coefficients are random at power-on.}
When changing coefficients, the EQ must be bypassed before programming. Muting the path is not sufficient and may not
prevent issues. Changing coefficients while the filter is in use may cause stability issues, clicks and pops, or other
problems.
All coefficients are calculated by software. Software must verify amplifier stability. Programming incorrect coefficients can
cause oscillation, clipping, or other undesirable effects. After calculating coefficients, software must calculate the inverse
gain (normalize the response) for each channel (Left and Right) to prevent saturation or inadequate output levels. All
values are then either programmed directly into the device or stored in a table for use in a configuration file or firmware.
2.13 AUDIO CLASS_D - REGISTERS

The Audio Class-D Module can be controlled and monitored by writing 8-bit control words to the various Registers.
The Base addresses are defined in Table 3 – Register Address Global Mapping on page 20.
2.13.1 AUDIO CLASS_D – RESERVED Registers

These registers are reserved. Do not write to them.

I²C Address = Page-2: 26(0x1A), µC Address = 0xA21A

I²C Address = Page-2: 27(0x1B), µC Address = 0xA21B
I²C Address = Page-2: 37(0x25), µC Address = 0xA225
I²C Address = Page-2: 47(0x2F), µC Address = 0xA22F
thru Page-2: 53(0x35), µC Address = 0xA235
thru Page-2: 255(0xFF), µC Address = 0xA2FF
2.13.2 AUDIO CLASS_D – ID HI & LO Registers

This 24 bit read-only register contains a unique ID for each block.
ID_HI: I²C Address = Page-2: 16(0x10), µC Address = 0xA210
ID_LO: I²C Address = Page-2: 17(0x11), µC Address = 0xA211
Default User
Setting Type
[15:0] ID 4D52h R Unique identifier
2.13.3 AUDIO CLASS_D – VERSION HI & LO Registers

This 24 bit read-only register contains a unique version identifier for each block.
VERSION_HI: I²C Address = Page-2: 18(0x12), µC Address = 0xA212
VERSION_LO: I²C Address = Page-2: 19(0x13), µC Address = 0xA213
Default User
Setting Type
Bits[15:8] updated on major RTL code change.
[15:0] VERSION 0100h R Bits[7:4] updated on minor RTL code change.
Bits[3:0] updated on metal layer bug fix.
2.13.4 AUDIO CLASS_D – STATUS Registers

These are read-only status registers which provide feedback on the operation of the DSP Filtering functions
STATUS0: I²C Address = Page-2: 20(0x14), µC Address = 0xA214
Default User
Settings Type
fs_clk_synced_loss_cnt Count of the number of times synchronization to i_den is lost since
[3:0] 0h R
0 last initialize.
latched max value of i_den jitter detected after fs_clk_synced.
[6:4] den_jitter 000b R Cleared on initialize. How many fclks is i_den for ch0 jittering
between samples.
1 = Input sample rate (i_den for ch0) is properly locked to fclk (within
7 fs_clk_synced 0b R
tolerance).
Default User
Settings Type
Multiply this value by 32 to get the number of fclks between each ch0
input data sample. Knowing the fclk frequency you can then
fclks_per_ch0_in_
[7:0] 00h R determine sample rate. Also useful in making sure there are enough
sample
fclks to allow the DSP filtering processes to complete before the next
input sample.
Default User
Settings Type
0 zerodet_flag 0b R set when input zero detect of long string of zeros.
1 = set if regz saturation after gain multiply for ch0. May change on a
1 limit1 0b R
sample by sample basis.
1 = set if regz saturation after gain multiply for ch0. May change on a
2 limit1 0b R
sample by sample basis.
[5:3] RESERVED 000b R RESERVED
6 limit0latch 0b R Latched version of limit0, clear via GAINCTRL[7].
7 limit1latch 0b R Latched version of limit1, clear via GAINCTRL[7].


Default User
Settings Type
Set if DSP filtering processes didn‟t finish before the next input data
0 timing_error 0b R
sample. Cleared on initialize.
2.13.5 AUDIO CLASS_D – CONFIG Registers

This 16 bit control register primarily controls operation of the DSP Filter block.
CONFIG0: I²C Address = Page-2: 24(0x18), µC Address = 0xA218
Default User
Settings Type
0 eapd 1b RW 1 = force External Amp Power Down (EAPD) output to ON.
1 mute 0b RW 1 = Mute all channels
2 Initialize 0b RW 1 = initialize/soft reset datapath, CSRs not reset
3 offset180 0b RW 1 = PWM ch1 offset from ch 0 by 180deg, 0 = 90deg
4 debug_sel_ns 0b RW 1 = debug output is from NS/PWM, 0 = NS input
5 eapd_polarity 1b RW 1 = invert eapd
7 swap_pwm_ch 0b RW 1 = swap ch0/1 on filter output to Noise Shaper
CONFIG1: I²C Address = Page-2: 25(0x19), µC Address = 0xA219
Default User
Settings Type
0 dc_bypass 0b RW 1 = bypass DC Filter
00 = interpolate by 2
01 = bypass
[2:1] fira_ratio 01b R Fira ratio
10 = decimate by 2
11 = reserved
3 firb_bypass 0b RW 1 = bypass firb interpolation
4 firc_bypass 0b RW 1 = bypass firc interpolation
5 eq_bypass 1b RW 1 = bypass equalization filter (must init EQRAM)
6 prescale_bypass 1b RW 1 = bypass EQ prescaler (must init EQRAM)

2.13.6 AUDIO CLASS_D – PWM Registers

This is a 32-bit register = {PWM3, PWM2, PWM1, PWM0}.
PWM3: I²C Address = Page-2: 28(0x1C), µC Address = 0xA21C
PWM2: I²C Address = Page-2: 29(0x1D), µC Address = 0xA21D
PWM1: I²C Address = Page-2: 30(0x1E), µC Address = 0xA21E
PWM0: I²C Address = Page-2: 31(0x1F), µC Address = 0xA21F
Default User
Settings Type
1 = 4th order binomial filter, 0 = 3rd order, noise improve of 6dB by
2 fourthorder 1b RW
setting this bit to 0
4 roundup 1b RW 1 = roundup, 0 = truncate for quantizer
5 clk320mode 1b RW 1 = PCA clock mode, pclk = 2560*Fs, 0 = 2048*Fs
[7:6] RESERVED 00b RW RESERVED
[14:10] Dithpos 00000b RW Dither position
17 pwm_outflip 0b RW 1 = swap pwm a/b output pair for all channels
[23:18] dvalue 011000b RW dvalue constant field
[29:24] cvalue 001010b RW tristate constant field, must be even and not 0
pwm output muxing, 0 = normal, 1 = swap 0/1, 2 = ch0 on both, 3 =
[31:30] outctrl 00b RW
ch1 on both
2.13.7 AUDIO CLASS_D – LMTCTRL Register

Controls operation of the Volume Limiter (Compressor).
LMTCTRL: I²C Address = Page-2: 32(0x20), µC Address = 0xA220
Default User
Settings Type
0 limiter_en 0b RW 1 = enable limiter (compressor)
0 = 0.5 dB
1 = 1.0 dB
[2:1] stepsize 00b RW Gain stepsize when incrementing or decrementing:
2 = 2.0 dB
3 = 4.0 dB
3 zerocross 0b RW 1 = only change limiter gain value on zero cross.
[7:4 ] RESERVED 0000b RW RESERVED
2.13.8 AUDIO CLASS_D – LMTATKTIME Register

Controls operation of the Volume Limiter (Compressor) Attack Time.
LMTATKTIME: I²C Address = Page-2: 33(0x21), µC Address = 0xA221
Default User
Settings Type
[6:0] time 0000000b RW Timer value in units of 1 ms or 10 ms.
0 = value in bits [6:0]
is in 1 ms units
7 time10ms 0b RW 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units.
is in 10 ms units
2.13.9 AUDIO CLASS_D – LMTRELTIME Register

Controls operation of the Volume Limiter (Compressor) Release Time.
LMTRELTIME: I²C Address = Page-2: 34(0x22), µC Address = 0xA222
Default User
Settings Type
is in 1 ms units
is in 10 ms units

2.13.10 AUDIO CLASS_D - GAINCTRL Registers

This is a 16-bit register = {GAINCTRL_HI, GAINCTRL_LO}.
GAINCTRL_HI: I²C Address = Page-2: 35(0x23), µC Address = 0xA223
GAINCTRL_LO: I²C Address = Page-2: 36(0x24), µC Address = 0xA224
Default User
Settings Type
0 = soft mute Mute After Reset
0 mute_mode 1b RW
1 = hard mute
0 = change on zero
cross Gain Change Mode
1 change_mode 0b RW
1 = change gain
immediately
0 = Don‟t Auto Mute
2 auto_mute 1b RW Auto Mute if long string of zeros detected on input
1 = Auto Mute
0 = Don‟t Disable
3 disable_gain 0b RW Disable All Gain Functions (Bypass Gain Multiply)
1 = Disable
0 = Don‟t Step
4 stepped_change 0b RW Step Volume Progressively to New Setting
1 = Step
0 = 1 ms
5 step_10ms 0b RW Units for step_time Value
1 = 10 ms
0 = Don‟t Clear
7 clr_latch 0b RW 1 = clear limit 0/1 latches, see STATUS2 reg
1 = Clear Limit
0 = 1 units
1 = 2 units
2 = 4 units
3 = 8 units Step time units = 1 << step_time
[10:8] step_time 101b RW
4 = 16 units Unit range is defined in GAINCTRL_LO, bit 5
5 = 32 units
6 = 64 units
7 = 128 units
0 = 512 Samples
1 = 1k Samples
[12:11] zerodetlen 10b RW Enable mute if input consecutive zeros exceeds this length.
2 = 2k Samples
3 = 4k Samples
2.13.11 AUDIO CLASS_D - MUTE Register

Enable mute individually per channel via this register. Global mute is available via CONFIG0[1].
MUTE: I²C Address = Page-2: 38(0x26), µC Address = 0xA226
Default User
Settings Type
0 = Don‟t Mute
0 mute0 0b RW Mute Channel 0
1 = Mute
0 = Don‟t Mute
1 mute1 0b RW Mute Channel 1
1 = Mute
2.13.12 AUDIO CLASS_D – ATTEN Register

This is the master attenuation which is applied to all channels.
ATTEN: I²C Address = Page-2: 39(0x27), µC Address = 0xA227
Default User
Settings Type
00h = 0 dB
01h = -0.5 dB
02h = -1.0 db
...
47h = -35.5 dB
Attenuation. Each bit represents 0.5 dB of attenuation to be applied
[7:0] ATTEN 00h RW 48h = -36.0 dB
to the channel. The range will be from 127 dB to 0 dB.
49h = -36.5 dB
...
FEh = -127 dB
FFh = Hard Master
Mute

2.13.13 AUDIO CLASS_D - VOLUME0/1 Register

There is one 8-bit Channel Volume Control Register for each channel. Each bit represents 0.5 dB of gain or attenuation
to be applied to the channel. The range is from -91 dB to + 36 dB.
Left Channel (0) = I²C Address = Page-2: 40(0x28), µC Address = 0xA228
Default User
Settings Type
00h = +36.0 dB
01h = +35.5 dB
...
47h = +0.5 dB
48h = +0 dB
[7:0] Volume0 48h RW Channel 0 Volume
49h = -0.5 dB
...
FEh = -91 dB
FFh = Hard Channel
Mute
Right Channel (1) = I²C Address = Page-2: 41(0x29), µC Address = 0xA229
Default User
Settings Type
00h = +36.0 dB
01h = +35.5 dB
...
47h = +0.5 dB
48h = +0 dB
[7:0] Volume1 48h RW Channel 1 Volume
49h = -0.5 dB
...
FEh = -91 dB
FFh = Hard Channel
Mute
2.13.14 AUDIO CLASS_D –LMTHOLDTIME Register

Controls operation of the Volume Limiter (Compressor) Hold Time.
LMTHOLDTIME: I²C Address = Page-2: 42 (0x2A), µC Address = 0xA22A
Default User
Settings Type
is in 1 ms units
is in 10 ms units
2.13.15 AUDIO CLASS_D – LMTATKTH & LMTRELTH Registers

These 16-bit registers set the threshold values. When in attack phase and the Attack Threshold is exceeded the
Compressor attenuation is incremented by „stepsize‟ (see LMTCTRL). When in release phase and the Release Threshold
is not exceeded, the Compressor attenuation is incremented by „stepsize‟ (but not above 0).
LMTATKTH_HI: I²C Address = Page-2: 43(0x2B), µC Address = 0xA22B
LMTATKTH_LO: I²C Address = Page-2: 44(0x2C), µC Address = 0xA22C
LMTRELTH_HI: I²C Address = Page-2: 45(0x2D), µC Address = 0xA22D
LMTRELTH_LO: I²C Address = Page-2: 46(0x2E), µC Address = 0xA22E
Default User
Settings Type
Always 0. It usually isn‟t necessary to provide threshold resolution to
[7:0 ] threshold[7:0] 00h RW
the point where these lower 8 bits would be used.
FFh would equal threshold level of +2.0dB. Each step below this
[15:8 ] threshold[15:8] 00h RW
8 bit full scale value reduces threshold level by 0.0078 dB.

2.13.16 AUDIO CLASS_D - DC_COEF_SEL Register

Select bit coefficient for DC Filter.
DC_COEF_SEL: I²C Address = Page-2: 48(0x30), µC Address = 0xA230
Default User
Settings Type
0 = 24'h100000; // 2^^-3 = 0.125
1 = 24'h040000
2 = 24'h010000
3 = 24'h004000
[2:0] DC_COEF_SEL 101b RW DC Filter Coefficient Selection
4 = 24'h001000
5 = 24'h000400
6 = 24'h000100; // 2^^-15 = 0.00030517
7 = 24'h000040; // 2^^-17
2.13.17 AUDIO CLASS_D - EQREAD_DATA Registers

This 24-bit register serves as the 24-bit data holding register used when doing indirect reads to the EQRAM.
Default User
Settings Type
[23:0] EQREAD_DATA 000000h R 24 bit coefficient 24-bit data register used for read data on EQRAM read
2.13.18 AUDIO CLASS_D - EQWRITE_DATA Registers

This 24-bit register serves as the 24-bit data holding registers when doing indirect writes to the EQRAM.
Default User
Settings Type
[23:0] EQWRITE_DATA 000000h RW 24 bit coefficient 24-bit data register used for write data on EQRAM write.
2.13.19 AUDIO CLASS_D - EQ_ADDR Registers

This 16-bit register provides the 10-bit address to the internal RAM when performing indirect writes/reads to the EQRAM.
EQ_ADDR_HI: I²C Addresses = Page-2: 60(0x3C), µC Address = 0xA23C
EQ_ADDR_LO: I²C Addresses = Page-2: 61(0x3D), µC Address = 0xA23D
Default User
Settings Type
[9:0] EQ_ADDR 0000000000b RW 10-bit Address EQRAM is mapped on address space 0 to 51.
2.13.20 AUDIO CLASS_D – EQCONTROL HI & LO Register

This 16-bit register provides the write/read enable when doing indirect writes/reads to the EQRAM.
I²C Address = Page-2: 62(0x3E), µC Address = 0xA23E
Default User
Settings Type
00000000000
[13:0] RESERVED RW RESERVED
00b
0 = Don‟t Read
14 eqram_rd 0b RW1C Read from EQRAM, cleared by HW when done
1 = Read
0 = Don‟t Write
15 eqram_wr 0b RW1C Write to EQRAM, cleared by HW when done
1 = Write

2.14 AUDIO CLASS_D - EQUALIZER COEFFICIENT & PRESCALER RAM (EQRAM)

2.14.1 AUDIO CLASS_D - Writing to EQRAM
The EQRAM is a single port 52x24 synchronous RAM. It is programmed indirectly through the Control Bus in the
following manner:
 Write 24-bit signed/magnitude data to the EQWRITE_DATA register.
 Write target address to the EQ_ADDR register (See Section 2.13.19).
 Set bit 15 of the EQCONTROL register (just write 0x80 to EQCONTROL_HI register.) When the hardware completes
the write it will automatically clear this bit. The write will occur when the EQRAM is not being accessed by the DSP
audio processing routines. NOTE: Bit 10 of the EQCONTROL register must be 0 for proper write cycle.
2.14.2 AUDIO CLASS_D - Reading from EQRAM

Reading back a value from the EQRAM is done in this manner:
 Write target address to EQ_ADDR register.
 Set bit 14 of EQCONTROL register (just write 0x40 to EQCONTROL_HI.) When the hardware completes the read it will
automatically clear this bit. The read data can then be read from the EQREAD_DATA register.
Table 7 - EQRAM Addresses
Channel 0 Coefficients Channel 1 Coefficients
Filter
Address Data Hi Data Mid Data Lo Address Data Hi Data Mid Data Lo
Band
Offset [23:16] [15:08] [07:00] Offset [23:16] [15:08] [07:00]
0x00 EQ_F0_A1C EQ_F0_A1B EQ_F0_A1A 0x19 EQ_F0_A1C EQ_F0_A1B EQ_F0_A1A
0x01 EQ_F0_A2C EQ_F0_A2B EQ_F0_A2A 0x1A EQ_F0_A2C EQ_F0_A2B EQ_F0_A2A
0x02 EQ_F0_B0C EQ_F0_B0B EQ_F0_B0A 0 0x1B EQ_F0_B0C EQ_F0_B0B EQ_F0_B0A
0x03 EQ_F0_B1C EQ_F0_B1B EQ_F0_B1A 0x1C EQ_F0_B1C EQ_F0_B1B EQ_F0_B1A
0x04 EQ_F0_B2C EQ_F0_B2B EQ_F0_B2A 0x1D EQ_F0_B2C EQ_F0_B2B EQ_F0_B2A
0x05 EQ_F1_A1C EQ_F1_A1B EQ_F1_A1A 0x1E EQ_F1_A1C EQ_F1_A1B EQ_F1_A1A
0x06 EQ_F1_A2C EQ_F1_A2B EQ_F1_A2A 0x1F EQ_F1_A2C EQ_F1_A2B EQ_F1_A2A
0x07 EQ_F1_B0C EQ_F1_B0B EQ_F1_B0A 1 0x20 EQ_F1_B0C EQ_F1_B0B EQ_F1_B0A
0x08 EQ_F1_B1C EQ_F1_B1B EQ_F1_B1A 0x21 EQ_F1_B1C EQ_F1_B1B EQ_F1_B1A
0x0A EQ_F2_A1C EQ_F2_A1B EQ_F2_A1A 0x23 EQ_F2_A1C EQ_F2_A1B EQ_F2_A1A
0x0B EQ_F2_A2C EQ_F2_A2B EQ_F2_A2A 0x24 EQ_F2_A2C EQ_F2_A2B EQ_F2_A2A
0x0C EQ_F2_B0C EQ_F2_B0B EQ_F2_B0A 2 0x25 EQ_F2_B0C EQ_F2_B0B EQ_F2_B0A
0x0D EQ_F2_B1C EQ_F2_B1B EQ_F2_B1A 0x26 EQ_F2_B1C EQ_F2_B1B EQ_F2_B1A
0x0E EQ_F2_B2C EQ_F2_B2B EQ_F2_B2A 0x27 EQ_F2_B2C EQ_F2_B2B EQ_F2_B2A
0x0F EQ_F3_A1C EQ_F3_A1B EQ_F3_A1A 0x28 EQ_F3_A1C EQ_F3_A1B EQ_F3_A1A
0x10 EQ_F3_A2C EQ_F3_A2B EQ_F3_A2A 0x29 EQ_F3_A2C EQ_F3_A2B EQ_F3_A2A
0x11 EQ_F3_B0C EQ_F3_B0B EQ_F3_B0A 3 0x2A EQ_F3_B0C EQ_F3_B0B EQ_F3_B0A
0x12 EQ_F3_B1C EQ_F3_B1B EQ_F3_B1A 0x2B EQ_F3_B1C EQ_F3_B1B EQ_F3_B1A
0x13 EQ_F3_B2C EQ_F3_B2B EQ_F3_B2A 0x2C EQ_F3_B2C EQ_F3_B2B EQ_F3_B2A
0x14 EQ_F4_A1C EQ_F4_A1B EQ_F4_A1A 0x2D EQ_F4_A1C EQ_F4_A1B EQ_F4_A1A
0x15 EQ_F4_A2C EQ_F4_A2B EQ_F4_A2A 0x2E EQ_F4_A2C EQ_F4_A2B EQ_F4_A2A
0x16 EQ_F4_B0C EQ_F4_B0B EQ_F4_B0A 4 0x2F EQ_F4_B0C EQ_F4_B0B EQ_F4_B0A
0x32 EQ_PREC EQ_PREB EQ_PREA 0x33 EQ_PREC EQ_PREB EQ_PREA

2.15 AUDIO – AUDIO CONTROL REGISTERS

The Audio Class-D Module can be controlled and monitored by writing 8-bit control words to the various Registers as
described below. The Base addresses are defined in Table 3 – Register Address Global Mapping on page 20.
2.15.1 AUDIO - RESERVED Registers

thru Page-1: 159(0x9F), µC Address = 0xA19F
I²C Address = Page-1: 164(0xA4), µC Address = 0xA1A4
thru Page-1: 165(0xA5), µC Address = 0xA1A5
I²C Address = Page-1: 205(0xCD), µC Address = 0xA1CD
thru Page-1: 208(0xD0), µC Address = 0xA1D0
I²C Address = Page-1: 212(0xD4), µC Address = 0xA1D4
thru Page-1: 255(0xEF), µC Address = 0xA1EF
2.15.2 AUDIO – Audio Control Register

AUDIO_CTRL = I²C Address = Page-0: 56(0x38), µC Address = 0xA038
Def. User
Set. Type
Write “1” to reset audio subsystem. Internal logic will reset this bit to
0 AUDIO_RST 0b RW1A
“0” after 250 ns.
0b = Disable Disabled state will put audio subsystem in low power state (analog in
1 AUDIO_EN 0b RW
1b = Enable standby and PLL shut-off).
0b = Disable
2 AUDIO_DIG_DIS 0b RW Enable/disable digital audio to conserve power
1b = Enable
0b = Disable
3 CLASSD_DIG_DIS 0b RW Enable/disable digital Class-D to conserve power
1b = Enable
[7:4] RESERVED 0h RW RESERVED
2.15.3 AUDIO - DAC0 Volume Control Registers (DAC0x_VOL)

These registers manage the output signal volume for DAC0, Left and Right respectively.
 The MSB, bit 7, of each register is the mute bit. When this bit is set, the output is silent.
 There are 128 gain selections from 0 dB to -95.25 dB. The step size is 0.75 dB.
DAC0L_VOL = I²C Address = Page-1: 160(0xA0), µC Address = 0xA1A0
Def. User
Set. Type
00h = 0 dB attenuation
[6:0] LEVEL_L 0000000b RW Left Volume Control
3Fh = 95.25 dB attenuation
0 = Not Muted
7 MUTE_L 1b RW Left Mute
1 = Muted
DAC0R_VOL = I²C Address = Page-1: 161(0xA1), µC Address = 0xA1A1
Def. User
Set. Type
[6:0] LEVEL_R 0000000b RW Right Volume Control
0 = Not Muted
7 MUTE_R 1b RW Right Mute
1 = Muted
2.15.4 AUDIO - DAC1 Volume Control Registers (DAC1x_VOL)

These registers manage the output signal volume for DAC1, Left and Right respectively.
 The MSB, bit D7, of each register is the mute bit. When this bit is set, the output is silent.
DAC1L_VOL = I²C Address = Page-1: 162(0xA2), µC Address = 0xA1A2
Def. User
Set. Type
0 = Not Muted
1 = Muted

DAC1R_VOL = I²C Address = Page-1: 163(0xA3), µC Address = 0xA1A3

Def. User
Set. Type
0 = Not Muted
1 = Muted
2.15.5 AUDIO - Mixer Output Volume Control Registers (MIX_OUTx_VOL)

These registers manage the output signal volume for the mixer, Left and Right respectively.
MIX_OUTL_VOL = I²C Address = Page-1: 166(0xA6), µC Address = 0xA1A6
Def. User
Set. Type
00h = 0 dB attenuatation
0 = Not Muted
1 = Muted
MIX_OUTR_VOL = I²C Address = Page-1: 167(0xA7), µC Address = 0xA1A7
Def. User
Set. Type
00h = 0 dB attenuatation
0 = Not Muted
1 = Muted
2.15.6 AUDIO - Mixer Input Volume Control - DAC0 Registers (DAC0x_MIX_VOL)

These registers manage the mixer input signal volume for DAC0, Left and Right respectively.
DAC0L_MIX_VOL = I²C Address = Page-1: 168(0xA8), µC Address = 0xA1A8
Def. User
Set. Type
00h = 12 dB gain
[4:0] D0MVL 0Ch RW 0Ch = 0 dB gain Left Volume Control
0 = Not Muted
1 = Muted
DAC0R_MIX_VOL = I²C Address = Page-1: 169(0xA9), µC Address = 0xA1A9
Def. User
Set. Type
00h = 12 dB gain
[4:0] D0MVR 0Ch RW 0Ch = 0 dB gain Right Volume Control
0 = Not Muted
1 = Muted

2.15.7 AUDIO - Mixer Input Volume Control - DAC1 Registers (DAC1x_MIX_VOL)

These registers manage the mixer input signal volume for DAC1, Left and Right respectively.
DAC1L_MIX_VOL = I²C Address = Page-1: 170(0xAA), µC Address = 0xA1AA
Def. User
Set. Type
00h = 12 dB gain
[4:0] D1MVL 0Ch RW 0Ch = 0 dB gain Left Volume Control
0 = Not Muted
1 = Muted
DAC1R_MIX_VOL = I²C Address = Page-1: 171(0xAB), µC Address = 0xA1AB
Def. User
Set. Type
00h = 12 dB gain
[4:0] D1MVR 0Ch RW 0Ch = 0 dB gain Right Volume Control
0 = Not Muted
1 = Muted
2.15.8 AUDIO - Mixer Input Volume Control - Line Input Registers (LINEINx_MIX_VOL)
These registers manage the mixer input signal volume for the Line input, Left and Right respectively.
LINEINL_MIX_VOL = I²C Address = Page-1: 172(0xAC), µC Address = 0xA1AC
Def. User
Set. Type
00h = 12 dB gain
[4:0] LMVL 0Ch RW 0Ch = 0 dB gain Left Volume Control
0 = Not Muted
1 = Muted
LINEINR_MIX_VOL = I²C Address = Page-1: 173(0xAD), µC Address = 0xA1AD
Def. User
Set. Type
00h = 12 dB gain
[4:0] LMVR 0Ch RW 0Ch = 0 dB gain Right Volume Control
0 = Not Muted
1 = Muted
2.15.9 AUDIO - Input Mixer Input Volume Control - Analog Microphone Registers (AMICx_MIX_VOL)
These registers manage the mixer input signal volume for the Analog Microphone input, Left and Right respectively.
AMICL_MIX_VOL = I²C Address = Page-1: 174(0xAE), µC Address = 0xA1AE
Def. User
Set. Type
00h = 12 dB gain
[4:0] MMVL 0Ch RW 0Ch = 0 dB gain Left Volume Control
0 = Not Muted
1 = Muted

AMICR_MIX_VOL = I²C Address = Page-1: 175(0xAF), µC Address = 0xA1AF

Def. User
Set. Type
00h = 12 dB gain
[4:0] MMVR 0Ch RW 0Ch = 0 dB gain Right Volume Control
0 = Not Muted
1 = Muted
2.15.10 AUDIO - ADC0 Analog Input Gain (Volume Control) Registers (ADC0x_IN_AGAIN)
These registers manage the input signal volume for ADC0, Left and Right respectively.
 The MSB, bit D7, of each register is the mute bit. When this bit is set, the output of the gain stage is silent. Muting the
amplifier does not stop the ADC capture stream.
 There are 16 gain selections from 22.5 dB to 0 dB. The step size is 1.5 dB.
ADC0L_IN_AGAIN = I²C Address = Page-1: 176(0xB0), µC Address = 0xA1B0
Def. User
Set. Type
0h = 0 dB gain
[3:0] A0VL 0h RW Left Analog Input Gain Control
Fh = 22.5 dB gain
0 = Not Muted
1 = Muted
ADC0R_IN_AGAIN = I²C Address = Page-1: 177(0xB1), µC Address = 0xA1B1
Def. User
Set. Type
0h = 0dB gain
[3:0] A0VR 0h RW Right Analog Input Gain Control
Fh = 22.5 dB gain
0 = Not Muted
1 = Muted
2.15.11 AUDIO - ADC0 Analog Input Selection Register (ADC0_MUX)

This register selects the input source for ADC0. ADC0 my record the line input or the mixer output.
ADC0_MUX = I²C Address = Page-1: 178(0xB2), µC Address = 0xA1B2
Def. User
Set. Type
0=Line Input
0 A0LSEL0 0b RW Left Analog Input Select
1=Mixer Iutput
0=Line Input
4 A0RSEL0 0b RW Right Analog Input Select
1=Mixer Iutput
2.15.12 AUDIO - ADC0 Control Register (ADC0_CTRL)

This register controls the functionality of the high pass filter for ADC0.
ADC0_CTRL = I²C Address = Page-1: 179(0xB3), µC Address = 0xA1B3
Def. User
Set. Type
0 = Disabled
4 HPF_FREZ 0b RW High-pass filter freeze
1 = Enabled
0 = Not Disabled
6 HPF_DIS 0b RW High Pass Filter Disable
1 = Disabled
2.15.13 AUDIO - ADC1 Digital Input Gain Register (ADC1x_IN_DGAIN)

These registers manage the signal output volume for ADC1, Left and Right respectively.
 The MSB, bit D7, of each register is the mute bit. When this bit is set, the output of the gain stage is silent. Muting the
amplifier does not stop the ADC capture stream.
 There are 16 gain steps from 22.5 dB to 0 dB. The step size is 1.5 dB.

ADC1L_IN_DGAIN = I²C Address = Page-1: 180(0xB4), µC Address = 0xA1B4

Def. User
Set. Type
0h = 22.5 dB gain
[3:0] A1VL Fh RW Left Digital Input Gain
Fh = 0 dB gain
0 = Not Muted
1 = Muted
ADC1R_IN_DGAIN = I²C Address = Page-1: 181(0xB5), µC Address = 0xA1B5
Def. User
Set. Type
0h = 22.5 dB gain
[3:0] A1VR Fh RW Right Digital Input Gain
Fh = 0 dB gain
0 = Not Muted
1 = Muted
2.15.14 AUDIO - ADC1 Digital Boost Gain Control Register

This register selects the amount of boost applied after ADC1 but before the ADC1 output gain/AGC.
ADC1_IN_DBOOST = I²C Address = Page-1: 182(0xB6), µC Address = 0xA1B6, Offset =
0xB6
Def. User
Set. Type
0h = 30 dB Gain
1h = 20 dB Gain
[1:0] DBR 11b RW Right Boost
2h = 10 dB Gain
3h = 0 dB Gain
0h = 30 dB Gain
1h = 20 dB Gain
[5:4] DBL 11b RW Left Boost
2h = 10 dB Gain
3h = 0 dB Gain
2.15.15 AUDIO - ADC1 Control Register

This register controls the function of the High pass filter for ADC1
ADC1_CTRL = I²C Address = Page-1: 183(0xB7), µC Address = 0xA1B7, Offset = 0xB7
Def. User
Set. Type
0 = Disabled
4 HPF_FREZ 0b RW High-pass filter freeze
1 = Enabled
0 = Not Disabled
6 HPF_DIS 0b RW High Pass Filter Disable
1 = Disabled

2.15.16 AUDIO - Microphone Port Mode Control

Microphone mode selection and other microphone port related control.
The digital and analog port pins are shared. Analog or digital microphone mode is selected using this register. When in
digital mode, the DMICCLK, DMICDAT1, DMICDAT2 and DMICCSEL functions are available. When in analog mode, the
MIC_R+, MIC_R-, MIC_L+, MIC_L-, MICBIAS_R, MICBIAS_L are available.
The left and right outputs of ADC1 may be swapped using the L/R swap flag and mono output may be forced using the
mono flag. By using the L/R swap and mono flags together it is possible to support stereo capture, mono capture from the
left channel and mono capture from the right channel. When used in conjunction with the power management controls, it
is possible to shut down half of the ADC and still provide valid data on both the left and right digital output streams from
ADC1.
MIC_MODE = I²C Address = Page-1: 184(0xB8), µC Address = 0xA1B8, Offset = 0xB8
Def. User
Set. Type
0 = Analog MIC Mode
0 AORD 0b RW Microphone Mode
1 = Digital MIC Mode
0 = Don‟t Swap
1 LR_SWAP 0b RW L/R Swap - swap left and right ADC1 channels
1 = Swap
0 = Normal
2 MONO 0b RW Mono - Left channel is copied to right (implemented after L/R swap)
1 = Left Copied to Right
0 = Don‟t Invert
3 BIT_INVERT 0b RW Bit invert - Input 1 as 0 and 0 as 1
1 = Invert
0 = Don‟t Power Down
7 AMIC_PWD 1b RW Dedicated Analog Microphone Power Down
1 = Power Down
2.15.17 AUDIO - Analog Microphone Boost Gain Control Register

This register selects the amount of gain applied to the analog microphone before the ADC.
AMIC_BOOST = I²C Address = Page-1: 185(0xB9), µC Address = 0xA1B9, Offset = 0xB9
Def. User
Set. Type
00b = 0 dB Gain
01b = 10 dB Gain
[1:0] AMBR 00b RW Right Boost
10b = 20 dB Gain
11b = 30 dB Gain
00b = 0 dB Gain
01b = 10 dB Gain
[5:4] AMBL 00b RW Left Boost
10b = 20 dB Gain
11b = 30 dB Gain

2.15.18 AUDIO - Digital Microphone (DMIC) Control Register

This register controls the Digital Microphone interface
DMIC_CTRL = I²C Address = Page-1: 186(0xBA), µC Address = 0xA1BA, Offset = 0xBA
Def. User
Set. Type
00b = 4.704 MHz
01b = 3.528 MHz
[1:0] RATE 10b RW Selects the DMIC clock rate
10b = 2.352 MHz
11b = 1.176 MHz
0h = left data rising
edge/right data falling edge
1h = left data center of
high/right data center of low DMIC sample phase adjust. Selects what phase of the DMIC clock
[3:2] PHADJ 00b RW
2h = left data falling the Left / Mono data should be latched.
edge/right data rising edge
3h = left data center of
low/right data center of high
0h = Disabled - DMICCLK
held low.
A mute pattern (1010) is
sent to CIC
[5:4] MODE 11b RW 1h = Stereo on DMICDAT1 Selects DMIC input mode.
2h = Stereo on DMICDAT2
3h = Stereo using
DMICDAT1 as Left /
DMICDAT2 as Right
0 = DMICCSEL pin is low
7 DMICCSEL 0b RW Logical value of DMICCSEL pin when port is in digital mode.
1 = DMICCSEL pin is high
2.15.19 AUDIO - Analog Microphone Port Mode Control & Bias Register
The analog microphone port supports two independent microphone bias pins.
Each Microphone Bias pin can supply up to 3mA of current.
AMIC_CTRL = I²C Address = Page-1: 187(0xBB), µC Address = 0xA1BB, Offset = 0xBB
Def. User
Set. Type
00b = Hi-Z (off)
01b = 50% VDD_AUDIO33
[1:0] MBIASL 00b RW Left Microphone bias
11b = GND
00b = Hi-Z (off)
[3:2] MBIASR 00b RW Right Microphone bias
11b = GND
2.15.20 AUDIO - AGC1 to AGC5 Automatic Gain Control Registers

AGCSET1 = I²C Address = Page-1: 188(0xBC), µC Address = 0xA1BC
Def. User
Set. Type
Gain control programmable in 1.5 dB steps. For example 0h = 0 dB, ,
[3:0] TARGET 2h RW
1h = -1.5 dB and Fh = -22.5 dB.
Delay Time =
2^(x+6)*base_time sec Delay Time: BASETIME_CTRL_SIGN and BASETIME_CTRL_MAG
[7:4] DELAY 2h RW Delay base time is (0xBF bit[7] and bit[6:5]) defines AGC function operation basetime
configured by unit.
{basetime_ctrl_sign, mag}
AGCSET2 = I²C Address = Page-1: 189(0xBD), µC Address = 0xA1BD
Def. User
Set. Type
2^(n+9)*base_time, n>10, Attack time is the time that it takes the AGC to ramp down across its
[3:0] ATTACK 0h RW
use n=10 gain range.
Attack time is the time that it takes the AGC to ramp up across its
[7:4] DECAY 0h RW 2^(n+11)*base_time
gain range

AGCSET3 = I²C Address = Page-1: 190(0xBE), µC Address = 0xA1BE

Def. User
Set. Type
000000b = -24 dB
[5:0] THRESHOLD 000000b RW -72 dB ~ -24 dB, in 1.5 dB per step
100000b = -72 dB
0 = Disable
6 AGCEN_RIGHT 0b RW Right Channel AGC Enable
1 = Enable
0 = Disable
7 AGCEN_LEFT 0b RW Left Channel AGC Enable
1 = Enable
AGCSET4 = I²C Address = Page-1: 191(0xBF), µC Address = 0xA1BF
Def. User
Set. Type
00000b = 0 dB
[4:0] MIN_GAIN 00000b RW 0 ~ 30 dB, 1.5 dB per step
10100b = 30 dB
000 = a, 001 = 2a, 010 =
BASETIME_CTRL
[7:5] 000b RW 4a, 011 = 8a, 101 = a/2, AGC basetime unit. a = 1/(8 x 44100) second
_MAG
110 = a/4, 111 = a/8
AGC5_MISC = I²C Address = Page-1: 192(0xC0), µC Address = 0xA1C0
Def. User
Set. Type
FASTEST_ATTACK 0 = Not Disabled
0 0b RW Disable fastest attack when >85% peak
_DIS 1 = Disabled
2.15.21 AUDIO - DAC0/1 Control Register Set

DAC_CTRL = I²C Address = Page-1: 193(0xC1), µC Address = 0xA1C1
Def. User
Set. Type

2.15.22 AUDIO - Source Control for Output Converters Registers

There are 4 output converters available: I2SOUT1, I2SOUT2, DAC0 and DAC1. Each may select one of the 4 available
digital data sources: I2SIN1, I2SIN2, ADC0 or ADC1. The output converters assume the characteristics of the selected
source. There is no rate translation. If I²S port 1 is routed to I²S port 2 then the rates of both ports must be the same. If
the rates are not the same, then the output from the sink port will be forced to 0 and will retain the rate programmed for
that port. If data widths are not the same, the data will be truncated or zero-padded as necessary. If an ADC is chosen
as the source for an I²S output then the I²S output characteristics will be used to set the ADC rate and data width. If an
ADC is connected to both I2SOUT1 and I2SOUT2, the characteristics of I2SOUT1 will be used. If a DAC is connected to
an ADC and the ADC is not connected to an I²S port, the ADC and DAC will default to 48 kHz/24-bit.
I2S1_SOURCE: I²C Address = Page-1: 194(0xC2), µC Address = 0xA1C2
Def. User
Set. Type
00b = I2SIN1
I2S1_SOURCE_SE 01b = I2SIN2
[1:0] 00b RW I2S1 source select
L 10b = ADC0
11b = ADC1
I2S2_SOURCE: I²C Address = Page-1: 195(0xC3), µC Address = 0xA1C3
Def. User
Set. Type
00b = I2SIN1
I2S2_SOURCE_SE 01b = I2SIN2
L 10b = ADC0
11b = ADC1
DAC0_SOURCE: I²C Address = Page-1: 196(0xC4), µC Address = 0xA1C4
Def. User
Set. Type
00b = I2SIN1
DAC0_SOURCE_S 01b = I2SIN2
[1:0] 00b RW DAC0 source select
EL 10b = ADC0
11b = ADC1
DAC1_SOURCE: I²C Address = Page-1: 197(0xC5), µC Address = 0xA1C5
Def. User
Set. Type
00b = I2SIN1
DAC1_SOURCE_S 01b = I2SIN2
EL 10b = ADC0
11b = ADC1
2.15.23 AUDIO – Class D BTL Amplifier Source Control Register

There are 4 audio sources available for the BTL amplifier. The left and right sources may be selected independently. The
DAC and mixer outputs are a nominal -6 dBV and are amplified at the output port to achieve the desired output level.
CLASSD_SOURCE: I²C Address = Page-1: 198(0xC6), µC Address = 0xA1C6
Def. User
Set. Type
00b = Mixer
01b = DAC0
[1:0] RIGHT_SEL 00b RW 10b = DAC1 Class-D right source select
11b = LINE IN
00b = Mixer
01b = DAC0
[3:2] LEFT_SEL 00b RW 10b = DAC1 Class-D left source select
11b = LINE IN
0 = Normal
6 RIGHT_MUTE 0b RW 1 = Mute ADC2-right(for class-D) mute
0 = Normal
7 LEFT_MUTE 0b RW 1 = Mute ADC2-left (for class-D) mute

2.15.24 AUDIO - Source control for Line Output Register

There are 4 audio sources available for the Line Output port. The left and right sources may be selected independently.
The DAC and mixer outputs are a nominal -6 dBV and are amplified at the output port to achieve the desired output level.
LINE_OUT_SCTRL: I²C Address = Page-1: 199(0xC7), µC Address = 0xA1C7
Default User
Setting Type
00b = Mixer
01b = DAC0
[1:0] RIGHT_SEL 00b R/W 10b = DAC1 Right line-out select
11b = Line-in
00b = mixer
01b = DAC0
[3:2] LEFT_SEL 00b R/W 10b = DAC1 Left line-out select
11b = line-in
0 = Mute
4 MUTE 1b R/W 1 = Normal operation
5 RESERVED 0b R/W RESERVED
00 = 0 dB
01b = +3 dB
[7:6] LOG 10b R/W 10b = +6 dB Line-out Port Gain
11b = Reserved
2.15.25 AUDIO - Source control for Headphone Output Register

There are 3 audio sources available for the Headphone Output port. The left and right sources may be selected
independently. The DAC and mixer outputs are a nominal -6dBV and are amplified at the output port to achieve the
desired output level.
I²C Address = Page-1: 200(0xC8), µC Address = 0xA1C8, Offset = 0xC8
Default User
Setting Type
00b = Mixer
01b = DAC0
[1:0] RIGHT_SEL 00b R/W 10b = DAC1 Right headphone output select
11b = Line-in
00b = Mixer
01b = DAC0
[3:2] LEFT_SEL 00b R/W 10b = DAC1 Left headphone output select
11b = Line-in
0 = Mute
4 MUTE 0b R/W 1 = Normal operation
00b = 0 dB
01b = +3 dB
[7:6] HPG 0b R/W 10b = +6 dB Headphone gain
11b = Reserved
2.15.26 AUDIO – Audio I2S1 Port Configuration 1

I²C Address = Page-1: 201(0xC9), µC Address = 0xA1C9, Offset = 0xC9
Def. User
Set. Type
00b = 16
01b = 20
[1:0] BIT_PER_SAMP 00b RW
10b = 24
11b = RESERVED
[4:2] DIV 000b RW 0 ~ 7 = div 1 ~ 8
00b = x1 or less
01b = x2
[6:5] MULT 00b RW
10b = RESERVED
11B = RESERVED
0b = 48 kHz
7 BASE_RATE 0b RW
1b = 44.1 kHz

2.15.27 AUDIO – Audio I2S1 Port Configuration 2

I²C Address = Page-1: 202(0xCA), µC Address = 0xA1CA, Offset = 0xCA
Def. User
Set. Type
00b = I2S
01b = Left justified
[1:0] FRMT 00b RW Link format
10b = Right justified
11b = RESERVED
0b = Disabled
2 RXEN 0b RW Rx enable
1b = Port Rx enabled
0b = Normal operation
3 LR_SWAP 0b RW Swap left and right at output enable
1b = L and R swap
0b = Normal Operation
4 WSINV 0b RW Invert word clock
1b = Invert word clock
5 BCLKINV 0b RW Invert bit clock
1b = Invert bit clock
0b = Slave (only)
6 MSS 0b RW Master/slave
1b = Master
0b = Disabled
7 TXEN 0b RW Tx enable
1b = Port Tx enabled
2.15.28 Audio I2S2 Port Configuration 1

I²C Address = Page-1: 203(0xCB), µC Address = 0xA1CB, Offset = 0xCB
Def. User
Set. Type
00b = 16
01b = 20
[1:0] BIT_PER_SAMP 00b RW
10b = 24
11b = RESERVED
[4:2] DIV 000b RW 0 ~ 7 = div 1 ~ 8
00b = x1 or less
01b = x2
[6:5] MULT 00b RW
10b = RESERVED
11B = RESERVED
0b = 48 kHz
7 BASE_RATE 0b RW
1b = 44.1 kHz
2.15.29 Audio I2S2 Port Configuration 2

I²C Address = Page-1: 204(0xCC), µC Address = 0xA1CC, Offset = 0xCC
Def. User
Set. Type
00b = I2S
01b = Left justified
[1:0] FRMT 00b RW Link format
10b = Right justified
11b = RESERVED
0b = Disabled
2 RXEN 0b RW Rx enable
1b = Port Rx enabled
0b = Normal operation
3 LR_SWAP 0b RW Swap left and right at output enable
1b = L and R swap
4 WSINV 0b RW Invert word clock
1b = Invert word clock
5 BCLKINV 0b RW Invert bit clock
1b = Invert bit clock
0b = Slave (only)
6 MSS 0b RW Master/slave
1b = Master
0b = Disabled
7 TXEN 0b RW Tx enable
1b = Port Tx enabled

2.15.30 AUDIO - Audio Subsection Power Control 1 Register

I²C Address = Page-1: 209(0xD1), µC Address = 0xA1D1, Offset = 0xD1
The Audio Subsection provides gross and fine power control. This register controls large blocks of the Audio Subsection.
Def. User
Set. Type
LINE_IN_D2S_PWD 0 = Not powered down Line Input D2S power down
0 0b RW
1 = Powered down
DIG _PWD 0 = Not powered down DIGITAL path power down (I²S)
1 0b RW
1 = Powered down
VREF_PWD 0 = Not powered down Reference power down
2 0b RW
1 = Powered down
0 = Not powered down ADC power down
3 ADC_PWD 0b RW
1 = Powered down
0 = Not powered down DAC power down
4 DAC_PWD 0b RW
1 = Powered down
0 = Normal operation
5 STANDBY 0b RW Low power mode
1 = Standby mode
[7:6] RESERVED RW RESERVED

The Audio Subsection provides gross and fine power control. This register controls individual DAC and ADC channels of
the Audio Subsection.
Def. User
Set. Type
DAC0L_PWD 0 = Not powered down Power down Left half of DAC0
0 0b RW
1 = Powered down
DAC0R_PWD 0 = Not powered down Power down Right half of DAC0
1 0b RW
1 = Powered down
DAC1L_PWD 0 = Not powered down Power down Left half of DAC1
2 0b RW
1 = Powered down
DAC1R_PWD 0 = Not powered down Power down Right half of DAC1
3 0b RW
1 = Powered down
ADC0L_PWD 0 = Not powered down Power down Left half of ADC0
4 0b RW
1 = Powered down
ADC0R_PWD 0 = Not powered down Power down Right half of ADC0
5 0b RW
1 = Powered down
ADC1L_PWD 0 = Not powered down Power down Left half of ADC1
6 0b RW
1 = Powered down
ADC1R_PWD 0 = Not powered down Power down Right half of ADC1
7 0b RW
1 = Powered down

The Audio Subsection provides gross and fine power control. This register controls individual DAC and ADC channels of
the Audio Subsection.
Def. User
Set. Type
0 RESERVED 0h RW RESERVED
HP_VIRTBUF_PWD 0 = Not powered down Power down Headphone Virtual Ground Buffer
1 0b RW
1 = Powered down
HP_RIGHT_PWD 0 = Not powered down Power down Right channel of Headphone out
2 0b RW
1 = Powered down
HP_LEFT_PWD 0 = Not powered down Power down Left channel of Headphone out
3 0b RW
1 = Powered down
LINEOUT_RIGHT_PWD 0 = Not powered down Power down Right channel of Line out
4 0b RW
1 = Powered down
LINEOUT_LEFT_PWD 0 = Not powered down Power down Left channel of Line out
5 0b RW
1 = Powered down
ADC2_RIGHT_PWD 0 = Not powered down Power down Right half of ADC2
6 0b RW
1 = Powered down
ADC2_LEFT_PWD 0 = Not powered down Power down Left half of ADC2
7 0b RW
1 = Powered down

3.0 CHARGER MODULE

Battery Charger, including switching buck regulator, charger, ideal diode and precision reference
CHARGER FEATURES CHARGER DESCRIPTION

High Efficiency Switch Mode Pre-Regulator for System The CHARGER module is the input power manager for
Power (VSYS) the P95020. It consists of the switch-mode Battery
Programmable USB or Wall current limit Charger, a Precision Reference and an Ideal Diode. It
(100mA/500mA/1A/1.5A/2A) also generates the VSYS power-on-reset when the system
Low Headroom Linear Charger is powered up or when a battery or power adapter is
1.5A Maximum Charge Current attached.
Internal 180mIdeal Diode + External Ideal Diode
The CHARGER consists of three power sources:
Automatic load prioritization
Independent Die-Temperature Sensor for Charger VBUS: Wall Adapter or USB provided power
Battery Temperature Monitor VBAT: Battery on VBAT will either deliver power to VSYS
Optional Discharger for Battery Safety through the ideal diode or be charged from VSYS via the
Independent Precision Bandgap Reference charger.
Battery Voltage Monitor VSYS: Output voltage of the Switch Mode Pre-Regulator
Power-On Reset Circuit and Input Voltage of the Battery Charger.
VBUS INPUT 106

107
ILIM / CLSEN
112
P
P
Register Pre-Regulator: VSYS 108
109
Interface Buck + UVLO
SW 104
105
clk1k
PGND 102
103
P
Die Temperature ICHRG

113
Sensor Linear Charger,
Safety Discharger,
Ideal Diode & P
Ref_Gnd Precision Control VBAT 110

111
A
Reference
Battery Voltage
Monitor
NTC Battery
Battery 115
Pack
Temperature
VNTC
Sensor 116
Power-On
POR Reset
Figure 9 – Charger Block Diagram
3.1 CHARGER - OVERVIEW

The Charger operation is hardware autonomous with software redundancy and configuration. On powerup it is configured
for a generic charging algorithm by default, however this is mask defined. Input current limiting selection is set by current
limit configuration register on powerup. After powerup the current limit can be set by GPIO4/CHRG_ILIM (write INT_ILIM
of Current Limit Configuration Register to 0), low stands for 500mA current limit while high stands for 1.5A current limit.
The GPIO pin configuration is defined in the GPIO_TSC Module and the Current Limit Configuration is defined in the
CHARGER MODULE. Both Charger and GPIO_TSC settings must be consistent to ensure that the P95020 works
properly. For example, if the charger registers are programmed such that current limiting is set via an external pin then
that GPIO must also be properly set in the GPIO_TSC registers to prevent it from being assigned to other functions.
3.2 CHARGER – SUB-BLOCKS
The CHARGER block includes the following sub- blocks:

A switching Pre-Regulator to regulate/power the system power (VSYS) when adapter input is present
A low-headroom Linear Charger which charges the Li-Ion/Li-Poly battery when adapter input is present and the battery is
not fully charged, and optionally discharges the battery for safety when the battery temperature is too high and the
battery is fully charged.
A Die-Temperature Sensor which monitors the die temperature so hardware autonomous actions can be taken to lower
the charging current when the die-temperature is too high;
A Battery Temperature Monitor which monitors the battery pack temperature through the NTC pin, charging is paused
when the battery‟s temperature is out of range (higher than 40°C or lower than 0°C);
A precision Bandgap for a reference for the charging voltage control;
A Battery Voltage Monitor which monitors the VBAT level solely for the charger (not for system level monitoring);
A Power-On Reset circuit which generates a reset for the system when VSYS is first powered on.
A Configuration Register Block with Register Access Interface, which allows system to access registers implemented
in this module.
3.3 CHARGER – DC ELECTRICAL CHARACTERISTICS
3.3.1 CHARGER - Buck Regulator Electrical Characteristics
Unless otherwise specified, typical values at TA =25C, VBUS = 5V, TA = -40°C to +85°C, COUT=10µF, L=2.2µH, CIN=1µF, CHRG_BAT=3.8V, RICHRG=1K,
RCLSEN=600
VBUS Input Supply Voltage 4.35 5.5 V
1x 90 95 100
5x 440 470 500
IBUSLIM Input Current Limit 10x 950 1000 1050 mA
15x 1425 1500 1575
20x 1900 2000 2100
1x 9
5x 9
IVBUSQ VBUS Quiescent Current 10x 15 mA
15x 15
20x 15
1x 250
5x 250
mA /
RCLSEN Ratio of Measured VBUS Program Current 10x 1000
mA
15x 1000
20x 1000
1x 0.239
5x 1.195
VCLSEN CLSEN Detect Voltage In Current Limit 10x 0.598 V
15x 0.837
20x 1.195
Rising edge 3.95
V
VBUS_UVLO VBUS Under Voltage Lockout
Hysteresis 200 mV
1X,5X,10X,15X,20X Modes,
VSYS System Output Voltage (During Charging) 0 V < VBAT <4.2 V 3.6 VBAT+0.3 4.5 V
IOUT = 0 mA
FOSC Switching Frequency 1.7 2 2.3 MHz
RHS High Side Switch On Resistance 0.18 
RLS Low Side Switch On Resistance 0.30 
IPEAKLIM Peak Switch Current Limit

1x, 5x modes 1 
10x, 15x, 20x modes 4
DMAX PWM Max Duty Cycle 100 %
tSOFTSTART Soft Start Rise Time 1 ms
ILEAKSW Leakage Current Into SW pin VBUS=0V, VSW=4.5V 1 µA

3.3.2 CHARGER – Battery Charger Electrical Characteristics

Unless otherwise specified, typical values at TA =25C, VBUS = 5V, TA = -40°C to +85°C, CHRG_BAT=3.8V, RICHRG=1K, RCLSEN=600, CLOAD=3300 pF
VFLOAT Battery Regulated Output Voltage 4.10 4.20 4.22 V
Constant Current Mode charge Current,
1X (minimun charging current limit) 100
ICHG RICHRG =1K , step 100mA mA
15X (Maximun charging current limit) 1500
(1X,~15X programmable)
100mA to 200mA (1X ~ 2X) -15 +15 %
IACC Charger Current Accuracy
300mA to 1500mA (3X ~ 15X) -10 +10 %
ITRKL = 100, 200mA or constant
1000
hPROG Ratio of IBAT to ICHRG pin current current/voltage mode mA/mA
ITRKL = 25, 50, 75, 125, 150, 175mA 500
ITRKL Trickle charge current 7 step 25mA/step 25 175 mA
VTRKL Trickle voltage Threshold Voltage 2.5 2.8 V
ITR_ACC Trickle Current Accuracy -10 +10 %
Trickle voltage Threshold Voltage
VTRKL_accuracy -5 5 %
accuracy
VRCV_HYSIS Trickle voltage hysteresis 100 mV
100 mA mode 90 110
ITERM Charge termination current mA
50 mA mode 45 55
tBATBAD Bad Battery Termination Time 0.5 Hours
TLIM Junction Temperature in Constant
Note 1 110 °C
Temperature Mode (thermal loop)
RON_DIODE Internal Ideal diode power FET on
180 m
resistance
Battery Operation At System Off
IBAT_SYSOFF No Adapter Input 100 μA
Condition
VTS1 Hot Temperature Threshold (NTC) 33 35 37 %VNTC
VTS2 Cold Temperature Threshold (NTC) 74 76 78 %VNTC
VTS3 Discharge Temperature Threshold (NTC) 18 20 22 %VNTC
VTS4 NTC Disable Threshold Voltage 0 2 3 %VNTC
Notes:
1. Guaranteed by design and/or characterization.
3.4 CHARGER – TYPICAL PERFORMANCE CHARACTERISTICS
Pre-Regulator
Efficiency vs Load Current
VBUS =5.0V, VSYS =3.7V
100%
90%
EFFICIENCY (%)
80%
70%
60%
50%
40%
30%
20%
10%
0%
0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00
LOAD CURRENT (A)
Figure 10 – Pre-Regulator Efficiency vs Load Current VBUS = 5.0V, VSYS = 3.7V

Pre-Regulator Load Regulation

VBUS = 5.0V, VSYS = 3.7V
3.7
3.65
VSYS (V)
3.6
3.55
3.5
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (A)
Figure 11– Pre-Regulator Load Regulation VBUS = 5.0V, VSYS = 3.7V
Ichrg (A) vs. Temperature (C)
1.2
1
ICHRG (A)
0.8
0.6
0.4
0.2
0
-40 10 60 110
TEMPERATURE (C)
Figure 12 – Battery Charge Current vs Temperature
3.5 CHARGER - REGISTER ADDRESSES

The Charger can be controlled and monitored by writing 8-bit control words to the various registers. The Base addresses
are defined in Table 3 – Register Address Global Mapping on page 20.
3.5.1 CHARGER - Current Limit Configuration Register

Def. User
Set. Type
[2:0] I_LIM 000b RW (See Table 8) Current Limit Setting
7 INT_ILIM 1b RW (See Note 1) Current Limit Source

Note 1 – If INT_ILIM = ‘1’, use I_LIM_n bits to define the input current limiting. If INT_ILIM = ‘0’ use external primary pin GPIO4/CHRG_ILIM,
GPIO4/CHRG_ILIM = 0: 500mA; GPIO4/CHRG_ILIM = 1: 1.5A.
Table 8 – Register 0xA090 (0x90) Current Limit (I_LIM)

Settings Bits [2:0]
Bit 2 Bit 1 Bit 0 Description
0 0 0 Peak Current Limit = 100 mA
3.5.2 CHARGER - Charging Configuration Register

Def. User
Set. Type
[3:0] CHG_CUR 0h RW (See Table 10) Charging Current (via sense resistor) = CHG_CUR x 100 mA
(See
[5:4] CHG_VOL 00b RW Maximum Battery Voltage
Table 9)
Table 9 – Register 0xA091, (0x91) Charging Maximum

Voltage (CHG_VOL) Settings, Bits [5:4]
Bit 5 Bit 4 Description
0 0 4.10 Volts
0 1 4.15 Volts
1 0 4.20 Volts
1 1 N/A
Table 10 – Register 0xA091, (0x91) Charging Current Limit via Sense Resistor (CHG_CUR)
Settings, Bits [3:0]
Bit Current Bit Current Bit Current Bit Current
Setting Limit Setting Limit Setting Limit Setting Limit
0000 100 mA 0100 400 mA 1000 800 mA 1100 1200 mA
0001 100 mA 0101 500 mA 1001 900 mA 1101 1300 mA
0010 200 mA 0110 600 mA 1010 1000 mA 1110 1400 mA
0011 300 mA 0111 700 mA 1011 1100 mA 1111 1500 mA
3.5.3 CHARGER - Charging Termination Control Register

Def. User
Set. Type
[1:0] CHG_TERM 00b RW (See Table 11) Charging Termination Time and method after enter CV mode
CHG_TERM = 00; Termination Timer = TERM_TIMER x 2 minutes
[6:2] TERM_TIMER 00001b RW
CHG_TERM = x1; Termination Timer = TERM_TIMER x 10 minutes
1 = 100mA
7 TERM_CUR 0b RW Termination Current
0 = 50mA
Table 11 – Register 0xA092 (0x92) Charging Termination Time (CHG_TERM) Settings Bits [1:0]
0 0 Charge terminates when timer expires. Timer starts counting only once termination current is reached.
0 1 Charge terminates after timer expires. Timer start counting after enter CV mode.
1 0 Charge terminates when termination current is reached.
Charge terminates when either timer expires (start timer after enter CV mode) or termination current is
1 1
reached.
3.5.4 CHARGER - Application Settings Register

Def. User
Set. Type
1 = 3.95 V
0 UVLO_VOL 0b RW Under-Voltage Lockout
0 = 4.15 V
(See
Battery Good Voltage Threshold, lower than this voltage will be charged
[4:3] BATGD_VOL 11b RW
with recovery charge method
Table 13)
[7:5] REC_CHCUR 011b RW (See Table 12) Battery Recovery Charge Current Control

Table 12 – Register 0xA093 (0x93) Battery Recovery

Charge Current Control Settings Bits [7:5]
Bit 7 Bit 6 Bit 5 Description
0 0 0 25 mA
0 0 1 50 mA
0 1 0 75 mA
0 1 1 100 mA
1 0 0 125 mA
1 0 1 150 mA
1 1 0 175 mA
1 1 1 200 mA
Table 13 – Register 0xA093, (0x93) Battery Good Voltage

Threshold Settings, Bits [4:3]
0 0 2.50 Volts
0 1 2.60 Volts
1 0 2.70 Volts
1 1 2.80 Volts
3.5.5 CHARGER - Special Control Register

Def. User
Set. Type
1 = Disable
0 DIS_CHARGER 0b RW Disable Charger
0 = Enable
1 = Disable
1 DIS_RCH 0b RW Disable Recharge
0 = Enable
1 = Disable
2 DIS_NTC 0b RW Disable NTC-Related Function
0 = Enable
1 = Disable
3 DIS_CV 0b RW Disable CV Loop
0 = Enable
1 = Disable
4 DIS_CC 0b RW Disable CC Loop
0 = Enable
0: Charging is diabled when Vsys is lower than the 3.6V “instant-
1 = Charging with Priority on” voltage.
5 DIS_INST_ON 0b RW
0 = System Load with Priority 1: Reduce charge current when Vsys is lower than the 3.6V
“instant-on” voltage.
3.5.6 CHARGER - Status 1 Register

Def. User
Set. Type
1 = Adpater Inserted
0 IN_STAT N/A R Adapter Inserted or not inserted
0 = Adapter Not Inserted
1 = Battery Too Cold
1 BAT_COLD N/A R Battery too cold
0 = Battery Temp OK
1 = Battery Too Hot
2 BAT_HOT N/A R Battery too hot
0 = Battery Temp OK
[4:3] CHMODE N/A R (See Table 14) Current Charger Mode
1 = Bat Unrecoverable
5 BAT_FAULT N/A R Battery Fault, battery voltage low and can not be recovered
0 = Bat Chargeable
1=Timer Terminated
6 CHRG_TIMEOUT N/A R Charge Cycle Terminated by Timer
0=Not Timer Terminated
1=Current Is Limited
7 CL_STATUS N/A R Input Current Limiting Status
0=Current Not Limited
Table 14 – Register 0xA095, (0x95) Current Charger Mode
Settings, Bits [4:3]
0 0 Charger On Hold
0 1 Battery Recovery Charge
1 0 Constant Current Mode
1 1 Constant Voltage Mode

3.5.7 CHARGER - Status 2 Register

Def. User
Set. Type
1 = Discharging
0 ANTISW_DISCH N/A R Anti-Swell Discharge Status
0 = Not Discharging
1 = NTC disabled
1 NTC_INVALID N/A R NTC function disabled by NTC short to GND
0 = NTC enabled
1 = Charging
4 IN_CHRG N/A R In Process of Charging
0 = Not Charging
1 = Charge
Complete
5 CHRG_DONE N/A R Charge Complete
0 = Charge Not
Complete
1 = VSYS < 3.6V
6 VSYS_LT36 N/A R VSYS < 3.6 V
0 = VSYS ≥ 3.6V
1 = Temp > 120°C
7 TEMP_HI N/A R 1: Charger thermal sensor detected Temperature > 120°C
0 = Temp ≤ 120°C
3.5.8 CHARGER - Interrupt Status Register

Def. User
Set. Type
1 = IN_STAT Changed
0 ADAPTER_INT 0b RW1C Adapter Input Status Changed
0 = IN_STAT Not Changed
1 = CL_STATUS Changed
1 CUR_LIM_INT 0b RW1C Current Limit Status Changed
0 = CL_STATUS Not Changed
1 = Charge Done status low to high
2 CHRG_DONE_INT 0b RW1C Set when rising edge of CHRG_DONE status detected
0 = Charge Done status not change
[7:3] RESERVED 00000b RW
3.5.9 CHARGER - Interrupt Enable Register

Def. User
Set. Type
1 = Interrupt
Enabled
0 ADAPTER_INT_EN 1b RW Adapter Input Interrupt Enable
0 = Interrupt Not
Enabled
1 = Interrupt
Enabled
1 CUR_LIM_INT_EN 0b RW Current Limit Interrupt Enable
0 = Interrupt Not
Enabled
1 = Interrupt
CHRG_DONE_INT_ Enabled
2 0b RW Charging DONE Interrupt Enable
EN 0 = Interrupt Not
Enabled
[7:3] RESERVED 00000b RW
3.5.10 CHARGER - RESERVED Registers:

Do not write to these registers. They are all RESERVED registers.
Thru = Page-0: 159(0x9F), µC Address = 0xA09F
3.6 CHARGER - PRE-REGULATOR
The Pre-Regulator is a buck converter which can provide currents up to 2A. It monitors the external input voltage and,
when this voltage is high enough, it regulates VSYS to 3.6V or (VBAT+0.3V) whichever is greater. The regulator will stop
running if the input voltage is too low (UVLO).
This block will generate a status of whether the adapter input (VBUS) is ready/powered so system will be aware of the
power source of the whole system, and can adjust the operating parameters accordingly.
The average input current is monitored and limited by the current limit settings. A resistor (600 from CLSEN to ground
determines the upper limit of the current drwan from the VBUS pin. A fraction of the VBUS current is send to the CLSEN pin
when the synchronous switch of the Pre-Regulator is on. Several VBUS current limit settings are available via input pin or

current limit configuration registers. If INT_ILIM (bit7) of current limit configuration register (0xA090) is 1, the current limit
is defined by I_ILIM[2:0]. If INT_ILIM is 0, the current limit is defined by GPIO4/CHRG_ILIM pin. Low stands for 500mA
current limit while high stands for 1.5A current limit. The default setting is 100mA when VSYS is not ready at start up.
When VSYS is ready, the current limit value is obtained from the internal register setting, which can be a default setting
(power up) or dynamic setting (after the external application processor programs it).
VSYS drives both the system load and the battery charger. If the combined load does not cause the switching regulator to
exceed the programmed input current limit, VSYS will track approximately 0.3V above the battery. By keeping the voltage
across the battery charger low, efficiency is optimized because power lost to the linear battery charger is minimized.
Power available to the external load is therfore optimized.
If the combined system load at VSYS is large enough to cause the switching power supply to reach the programmed input
current limit, VSYS will drop. Depending on the configuration, the battery charger will reduce its charge current when the
VSYS drop below 3.6V to enable the external load to be satisfied.
If the voltage at VBAT is below 3.3V and the load requirement does not cause the switching regulator to exceed the
programmed input current limit, VSYS will regulate at 3.6V. If the load exceeds the available power, VSYS will drop to a
voltage between 3.6V and the battery voltage. Figure 10 shows the range of possible voltages at VSYS as function of
battery voltage.
For very low battery voltage, due to limited input power, charging current will tend to pull VSYS below the 3.6V “instant-on”
voltage. If instant-on operation under low battery conditions is a requirement then DIS_INST_ON of Charger Special
Control Register (0xA094) should be set to 0. An under voltage circuit will automatic detects that VSYS is falling below 3.6V
and disable the battery charging. If maximun charge current at low battery voltage is preferred, the instant-on function
should be disabled by setting DIS_INST_ON to 1. If the load exceed the current limit at VBUS and the system is not in the
instant-on mode, the battery charger will reduce its charge current when under voltage circuit detects VSYS is falling below
3.6V.
VSYS
4.5V
4.2V
3.9V
3.6V
3.3V
3.0V
2.7V
2.4V
VBAT
2.4V 2.7V 3.0V 3.3V 3.6V 3.9V 4.2V
Figure 13 – VSYS Regulation Curve (Tracking VBAT )
3.7 IDEAL DIODE FROM VBAT TO VSYS

The charger has and internal ideal diode as well as a controller for an optional external ideal diode. The ideal diode
controller is always on and will respond quickly whenever VSYS drops below VBAT. If the load current increases beyond the
power allowed from the switching regulator, additional power will be pulled from the battery via the ideal diode.
Furthermore, if power to VBUS (USB or wall power) is removed, then all of the application power will be provided by the
battery via the ideal diode. The ideal diode consists of a precision amplifier that enables a large on-chip P-channel
MOSFET transistor whenever the voltage at VSYS is approximately 15mV below the voltage at VBAT. The resistance of the
internal ideal diode is approximately 180mIf this is sufficient for the application, then no external components are
necessary. However, if more current is needed, an external P-channel MOSFET transistor can be added from VBAT to

VSYS. When an external P-channel MOSFET transistor is present, the CHRG_GATE pin of P95020 drives its gate for
automatic ideal diode control. The source of the external P-channel MOSFET should be connected to VSYS and the drain
should be connected to VBAT.
3.8 CHARGER - CHARGER/DISCHARGER
The system includes a constant-current/constant-volatge battery charger with automatic recharge, automatic termination
by termination current and safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out
of temperature charge pausing.
Battery Preconditioning
When a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. If the battery
voltage is below VTRKL, typically 2.8V, an automatic trickle charge feature sets the battery charge current to recover charge
current (7 step 25mA/step programmable by Application Setting Register). If the low voltage persists for more than ½
hour, the battery charger automatically terminates and indicates via battery fault flag in the Status 1 Register that the
battery is defective. Once the battery voltage is above VTRKL, the battery charger begins charging in full power constant
current mode. The current delivered to the battery will try to reach ICHG (step 100mA, 1X ~15X programmable by Charging
Configuration Register), the battery charger may or may not be able to charge at the full programmed rate. The external
load will always be prioritized over the battery charge current. The USB (or Wall adapter) current limit programming will
always be observed.
Charge Termination
When the voltage on the battery reaches the pre-programmed float voltage (4.1V or 4.2V), the battery charger enters
constant voltage mode and the charge current will decrease as the battery becomes fully charged.The charger offers
several methods to terminate a charge cycle by setting the Charging Termination Control Register bits[1:0]. Refer to the
register definition section for the details.
Intelligent Start and Automatic Recharge
When the charger is initially powered on, the charger checks the battery voltage. If the VBAT pin is below the recharge
threshold of 3.9V (which corresponds to approximately 50-60% battery capacity), the charger enters charge mode and
begines a full charge cycle. If the VBAT pin is above 3.9V, the charger enters standby mode and does not begine charging.
This feature reduces unnecessary charge cycle thus prolongs battery life. When the charger is in standby mode, the
charger continuously monitors the voltage on the VBAT pin. When the voltage drops below 3.9V and the temperature below
40°C, the charge cycle is automatically restarted and the safety timer and termination timer (if time termination is used) is
reset to 50% of the programmed time. This feature eliminates the need for periodic charge cycle initiations and ensures
the battery is always fully charged.
Battery Temperature Monitor
The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to the battery
pack. To use this feature, connect the NTC thermistor, RNTC, between the NTC and ground and a resistor, RNOM, from
VNTC to the NTC pin. RNOM should be a 1% resistor with a value equal to the value of the chosen NTC thermistor at
25°C(R25). For applications requiring greater than 750mA of charging current, a 10k NTC thermistor is recommended.
The charger will pause charging when the NTC thermistor drops to 0.54 times the value of R25 or approximately 5.4k. For
a Vishay “Curve 1” thermistor, this corresponds to approximately 40°C. As the temperature drops, the resistance of the
NTC thermistor rises. The charger will also pause charging when the value of the NTC thermistor increase to 3.25 times
the value of R25. For Vishay “Curve 1” this resistance, 32.5k, corresponds to approximately 0°C. Grounding the NTC pin
disables the NTC charge pausing function.
There is also a battery-discharge feature: when the battery is full and battery temperature go beyond 60°C, the NTC
thermistor drops to 0.25 times the value of R25. The charger can discharge the battery to 3.9V for safety
The VNTC pin output is dynamically enabled to save power. The NTC measurement is triggered every 5 seconds. Each
measurement takes 16ms.
3.9 CHARGER - THERMAL MONITORING
A thermal sensor is used in charging control, An internal thermal feedback loop reduces the charge current if the die
temperature attempt to rise above the preset value of approximately 120°C. This feature protects the charger from
excessive temperature and allows the pushing of the limits of the power handling capability of a given circuit board without
the risk of damagingThis thermal sensor is not used for system level die-temperature detection.
3.10 CHARGER - POWER ON RESET
A Power-On reset circuit will generate a reset when the VSYS power goes from low to high. The signal is used to reset all
the logic powered directly or indirectly by VSYS.

4.0 CLOCK GENERATOR MODULE

 High-quality, high-frequency external clock outputs The P95020 includes a highly accurate, low power clock
synthesizer designed exclusively for portable applications.
generated from a TCXO input or a crysal contected
The P95020 will generate high quality, high-frequency
between HXTALIN and HXTALOUT.
clock outputs from a 12 MHz, 13 MHz, 19.2 MHz or 26
 32.768 kHz crystal oscillator or 32.768 kHz clock input MHz TCXO input or crystal oscillator. The P95020‟s clock
for system start-up generator (CKGEN) module also includes a 32 kHz
 3.3V core operating voltage oscillator and output, which are connected to a separate
low power supply, to facilitate system start-up.
 1.2V/1.8V TCXO output voltage
 3.3V SYS_CLK, USB_CLK and 32KHZ clock output
voltages
VDDIO_CK
VDDIO_CK
12MHz
TCXO_OUT2
48MHz
VDD_CKGEN33
SYS_CLK
HXTAL VDD_CKGEN33
PLL dividers 24MHz
OSC
VDDIO_CK
USB_CLK
VDD_CKGEN33
CLK32K
Xtal oscillator,
32KHZ_OUT2
RC-Oscillator
I2C
SUB-BLOCK
MICROCONTROLLER
SUB-BLOCK
UPPER BYTE
OFFSET: 0xA0
CKGEN PLL CONFIGURATION REGISTER

0x34 [7:0]
CKGEN_GND
PLL STATUS REGISTER
0x35 [7:0]
32KHZ_CLKIN/
32KHZ_OUT1/
TCXO_OUT1
HXTALOUT/
XTALOUT
HXTALIN/
TCXO_IN
XTALIN
Figure 14 – Clock Generator Block Diagram
4.1 CKGEN - PIN DEFINITIONS

PIN # PIN_ID DESCRIPTION
041 32KHZ_OUT2 Buffered 32.768 kHz Output #2
042 CKGEN_GND PLL Analog Ground
32KHZ_CLKIN: External 32.768 kHz clock input
043 32KHZ_CLKIN/XTALIN
XTALIN : Input pin when used with an external crystal
XTALOUT: Output pin when used with an external crystal
044 XTALOUT/32KHZ_OUT1 32KHZ_OUT1: When XTALIN is connected to a 32 kHz input this pin can be a 32 kHz output when bit 4 of
the CKGEN_PLL_STATUS register is set to 1.
045 VDD_CKGEN18 Internal 1.8V CKGEN LDO. Connect filter capacitor from this pin to CKGEN_GND
046 HXTALOUT/TCXO_IN HXTALOUT: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz Crystal oscillator output

TCXO_IN: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz TXCO Clock Input

047 VDD_CKGEN33 Internal 3.3V CKGEN LDO. Connect filter capacitor from this pin to CKGEN_GND
HXTALIN: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz Crystal Oscillator Input
048 HXTALIN/TCXO_OUT1
TCXO_OUT1: Buffered TXCO_IN/HXTAL Clock Output #1, 32.768 kHz Output, 24 MHz PLL Output
049 TCXO_OUT2 Buffered TXCO_IN/HXTAL Clock Output #2, 12 MHz PLL Output, 48 MHz PLL Output
050 SYS_CLKOUT 12 MHz Output or Buffered Output of TCXO_IN/HXTAL
051 CKGEN_GND PLL Analog Ground
052 USB_CLKOUT 24 MHz or 48 MHz Output
053 VDDIO_CK Power Supply Input for TCXO_OUT1 and TCXO_OUT2 (1.1V – 1.9V)
4.2 CKGEN - OSCILLATOR CIRCUIT ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VDD_CKGEN33 = 3.3V, VDD_CKGEN18 = 1.8V, VSYS = 3.8V, TA = -40°C to +85°C,

VDD_CKGEN33 Internal LDO Regulator 2.97 3.3 3.63 V
VDD_CKGEN18 Operating Voltage Internal LDO Regulator 1.62 1.8 1.98 V
VDDIO_CK Power Input for TCXO_OUT1 and 1.1 1.9 V
TCXO_OUT2
IDD_CKGEN33 4 mA
IDD_CKGEN18 Supply Current 1 mA
VDDIO_CK 2 mA
VIH TCXO_IN High Level Input 0.7xVDD_ VDD_CKG V
Voltage CKGEN18 EN18 +
0.3
VIL TCXO_IN Low Level Input -0.3 0.3xVDD_ V
Voltage CKGEN18
VIH 32KHZ_CLKIN High Level Input 0.7x VLD0_LP + V
Voltage VLD0_LP 0.3
VIL 32KHZ_CLKIN Low Level Input -0.3 0.3x V
Voltage VLD0_LP
VOH Output High for SYS_CLK, IOH = -4mA 0.7xVDD_ V
USB_CLK CKGEN33
VOL Output Low for SYS_CLK, IOL = 4mA 0.3xVDD_ V
USB_CLK CKGEN33
VOH Output High for 32KHZ_OUT2 IOH = -1mA 0.7xVDD_ V
CKGEN33
VOL Output Low for 32KHZ_OUT2 IOL = 1mA 0.3xVDD_ V
CKGEN33
VOH Output High for TCXO_OUT VDDIO_CK = 1.8V, IOH = -4mA 0.7xVDDI V
O_CK
VOL Output Low for TCXO_OUT VDDIO_CK = 1.8V, IOL = 4mA 0.3xVDDI V
O_CK
VOH Output High for TCXO_OUT VDDIO_CK = 1.2V, IOH = -1mA 0.7xVDDI V
O_CK
VOL Output Low for TCXO_OUT VDDIO_CK = 1.2V, IOL = 1mA 0.3xVDDI V
O_CK
fo_CLK32 Input Frequency 32 kHz Clock 32.768 kHz
fo_CLKTCXO Input Frequency TCXO_IN 12MHZ, 13MHZ, 19.2MHZ,
26MHZ
ESRCLK32 Series Resistance 45 k
CL_CLK32 Load Capacitance 6 pF
tOR/tOF Output Rise Time/Fall Time Between 20% to 80%, 5.0 ns
32 kHz output, Note 1
SYS_CLK, USB_CLK output,
Note 3
Other outputs, Note 1
tSKEW Output-Output Skew TCXO_1 to TXCO_2 ±50 ps
IOS Short Circuit Current Clock outputs ±70 mA
RO Output Impedance 20 
DCLOCKOUT Output Clock Duty Cycle, 40 60 %
Oscillator Buffered Output
DCLOCKOUT Output Clock Duty Cycle, PLL 45 55 %
Output
FSYN-ERR Frequency Synthesis Error 0 ppm

STJITTER 24, 48 MHz Output 200 ps

Short Term Jitter (peak-to-peak) 32 kHz Output 300 ns
From minimum VDD_CKGEN18 and 3 ms
Power-up Time VDD_CKGEN33 to outputs stable to
tPU ±1% Note 2
From stable crystal 32kHz input to 300 ms
stable output
Notes:
1. Measured with a 5pF load.
2. Power-up time for TCXO derived output frequencies only after TCXO has stabilized.
4.3 CKGEN - PLL CONTROL
The PLL in the CKGEN module is powered on/off by setting bits [2:0] in the CKGEN_PLL_CFG register as shown below.
S2 S1 S0 PLL behavior
0 0 0 PLL OFF
PLL power up with 26MHz TCXO_IN as
0 0 1
reference clock
PLL power up with 32kHz XTAL_IN as
0 1 0
reference clock
PLL power up with 26MHz TCXO_IN
0 1 1
as reference clock
1 0 0 PLL OFF
1 0 1
reference clock
1 1 0
reference clock
PLL power up with 19.2MHz TCXO_IN
1 1 1
as reference clock
The 12 MHz and 48 MHz outputs are enabled/disabled by setting bits [7:6] in the CKGEN_PLL_CFG register. One or
both of the clock outputs will be enabled when a “1” is written into the corresponding register location for the output in
question.
4.4 CKGEN – OSCILLATOR CIRCUIT
The CKGEN module may use an external 32.768 kHz crystal connected to the XTALIN pin. The oscillator circuit does not
require any external resistors or capacitors to operate. Table 15 specifies several crystal parameters for the external
crystal. The typical startup time is less than one second when using a crystal with the specified characteristics.
Table 15 - Crystal Specifications
SYMBOL PARAMETER MIN TYP MAX UNITS COMMENTS
fo Nominal Frequency 32.768 kHz
ESR Series Resistance 80 k
CL Load Capacitance 12 pF
4.5 CKGEN - CKGEN POWER SOURCE

The CKGEN module receives its power from an on-chip LDO. The CKGEN power is controlled via the “PSTATE_ON” bit
in the Power State and Switch Control Register (see section 13.3.10). Setting that register is automatic whenever there is
an interrupt targeting the embedded processor pending. The “PSTATE_ON” bit can be cleared by writing a logic “1” if
software wants to power down the CKGEN. Please be aware that powering down the CKGEN should be the last
operation by the software, since once CKGEN is powered down, there will be no clock for the internal register access bus
and I²C. The P95020 has a minor delay when the PSTATE_ON bit is cleared to allow the “cleaning” access to be
finished.
When CKGEN is powered, the 8M clock will be available so the I²C/processor will be active. The chip‟s registers can be
accessed. However, the PLLs will still not be on. To turn on the PLLs, S2:S0 registers need to be set.
4.6 CKGEN – CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added

by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result
in the clock running fast. Pay attention to PC board layout for isolating the crystal and oscillator from noise.
4.7 CKGEN – CLOCK GENERATOR REGISTERS
4.7.1 CKGEN – CLOCK GENERATOR PLL CONFIGURATION REGISTER
Def. User
Set. Type
000b = PLL off
001b = PLL on, 26MHz
TCXO_IN as reference clock
010b = PLL on, 32kHz
XTAL_IN as reference clock
011b = PLL on, 26MHz
TCXO_IN as reference clock
[2:0] S2/S1/SO 000b R/W
100b = PLL off
101 = PLL on, 12MHz
TCXO_IN is reference clock
110b = PLL on, 13 MHz
111b = PLL on, 19.2 MHz
0b = 2 MHz
3 CLK2M_RATE 0b R/W Tuch Screen Controller Clock
1b = 1 MHz
0b = +/- 1%
4 SSC_DELTA 0b R/W SSC frequency offset setting
1b= +/- 2%
0b = Disabled
5 SSC_EN 0b R/W DCDC 24MHz clock SSC enable
1b = Enabled
0b = Disabled
6 SYS_CLK_OUT_EN 1b R/W SYS_CLK clock output enabled
1b = Enabled
0b = Disabled
7 USB_CLK_OUT_EN 1b R/W USB_CLK clock output enable
1b = Enabled
4.7.2 CKGEN – PLL STATUS REGISTER

Def. User
Set. Type
0b = Not locked
0 PLL_LOCK1 0b R Main PLL lock status
1b = Locked
0b = Disabled
1 TCXO1_EN 0b R/W TCXO #1 enable
1b = Enabled
0b = Disabled
2 TCXO2_EN 0b R/W TCXO #2 enable
1b = Enabled
0b = Disabled
4 32KOUT1_EN 0b R/W 32K clock #1 enable
1b = Enabled
0b = Disabled
5 32KOUT2_EN 0b R/W 32K clock #2 enable
1b = Enabled
0b = Unstable
6 32K_STABLE 0b R 32K oscillator or input stable
1b = Stable
7 RESERVED 0b R RESERVED

4.7.3 CKGEN – CKGEN CONFIGURATION REGISTER

I²C Address = Page-0: 61(0x3D), µC Address = 0xA03D
Def. User
Set. Type
0b = HXTALIN/TCXO_OUT1 is HXTALIN and
HXTALOUT/TCXO_IN is HXTALOUT HXTALIN/TCXO_OUT1 and
0 OEB_HXTAL 1b R/W
1b = HXTALIN/TCXO_OUT1 is TCXO_OUT1 HXTALOUT/TCXO_IN Select
and HXTALOUT/TCXO_IN is TCXO_IN
0b = Output is 48MHz clock from PLL
1 OUT48M_C 0b R/W USB_CLK Select
2 OUT12M_C 0b R/W SYS_CLK Select
1b = Output is from HXTALOUT/TCXO_IN
00b = TCXO_OUT2 is from
HXTALOUT/TCXO_IN
[4:3] TCXO2_C 00b R/W 01b = TCXO_OUT2 is 12 MHz clock from PLL TCXO_OUT2 Select
10b = 11b = TCXO_OUT2 is 48 MHz clock from
PLL
00b = TCXO_OUT1 is from
HXTALOUT/TCXO_IN
[6:5] TCXO1_C 0b R/W 01b = TCXO_OUT1 is from 32KHZ_CLKIN TCXO_OUT1 Select
10b = 11b = TCXO_OUT1 is 24 MHz clock from
PLL
0b = VDDIO_CK is 1.8V, TCXO_OUT1/2 drive
strength weak
7 TCXO_HV_ENB 0b R/W VDDIO_CK
1b = TCXO VDDIO_CK is 1.2V, TCXO_OUT1/2
drive strength strong

5.0 RTC MODULE

 Real Time Clock (RTC) Counts Seconds, Minutes, The low power serial real-time clock (RTC) device has two
programmable time-of-day alarms. Address and data are
Hours, Day, Date, Month and Year (with Leap-Year
transferred serially through the I²C bus. The device
Compensation Valid Up to year 2100
 Two time-of-day alarms provides seconds, minutes, hours, day, date, month and
 Low power year information. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either 24-hour format or 12-hour format with
AM/PM indicator.
5.1 RTC - GENERAL DESCRIPTION

The Real-Time Clock (RTC) block is a low-power clock/date device with two programmable time-of-day/date alarms. The
clock/date provides seconds, minutes, hours, day, date, month and year information. The date at the end of the month is
automatically adjusted for months with fewer than 31 days, including corrections for leap years. The clock operates in
either the 24-hour or 12-hour format with an AM/PM indicator. The RTC cannot be disabled while the system is powered
on. The register settings and logic are only reset the first time the system is powered on by inserting either the wall
adapter or the battery. After reset, the time keeping registers are reset and must be synchronized to the real time by
programming its time keeping registers. The alarm interrupts are disabled by default.
The time and date information is set and monitored by writing and reading the appropriate register bytes. Sections 5.2
and 5.3 below show the RTC TIMEKEEPER and RTC DATE registers. The contents of the time and date registers are in
BCD format. The RTC block can be run in either 12-hour or 24-hour mode. Bit 6 of the HOUR register is defined as the
12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In 12-hour mode, bit 5 is the PM bit with
logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). All hour values, including the
alarms, must be re-entered whenever the TIME_12 mode bit is changed. The century bit (bit 7 of the month register) is
toggled when the YEAR register overflows from 99 to 0. The days register increments at midnight. Values that
correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday
and so on). Illogical time and date entries result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal
registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers at
the time of reading address pointing to zero. The countdown chain is reset whenever the seconds register is written.
Write transfer occurs when the processor bus receives a write command. To avoid rollover issues, once the countdown
chain is reset, the remaining time and date registers must be written within 0.5 second.
The RTC block contains two time-of-day/date alarms. The alarms can be programmed (via the alarm enable and INT_EN
bits of the control registers defined in section 5.5) to activate the interrupt (INT) output when an alarm match condition
occurs. Bit 7 of each of the time of day/date alarm registers are mask bits (Table 2). When all the mask bits for each
alarm are logic 0 an alarm occurs only when the values in the timekeeping registers 00h to 04h match the values stored in
the time-of-day/date alarm register. The alarms can also be programmed to repeat every second, minute, hour, day or
date. Table 16 shows the possible settings.
Table 16 - Alarm mask bits
DY1 A1M4 A1M3 A1M2 A1M1 Alarm rate
X 1 1 1 1 Alarm once per second
X 1 1 1 0 Alarm when seconds match
X 1 1 0 0 Alarm when minutes and seconds match
X 1 0 0 0 Alarm when hours, minutes, and seconds match
0 0 0 0 0 Alarm when date, hours, minutes, and seconds match
1 0 0 0 0 Alarm when day, hours, minutes, and seconds match
DY2 A2M4 A2M3 A2M2 A2M1 Alarm rate

X 1 1 1 1 Alarm once per second
X 1 1 1 0 Alarm when seconds match
X 1 1 0 0 Alarm when minutes and seconds match
X 1 0 0 0 Alarm when hours, minutes, and seconds match
0 0 0 0 0 Alarm when date, hours, minutes, and seconds match
1 0 0 0 0 Alarm when day, hours, minutes, and seconds match

The DY1 bit (bit 6 of the day/date alarm 1 value register) control whether the alarm value stored in bits 0 to 5 of that
register reflects the day of the week or the date of the month. If DY1 is written to a logic 0, the alarm is the result of a
match with date of the month. If DY1 is written to a logic 1, the alarm is the result of a match with day of the week. The
DY2 bit serves the same function for the day/date alarm 2 value register.
The RTC block checks for an alarm match once per second. When the RTC register values match the alarm register
settings, the corresponding Alarm Flag (A1_FLAG or A2_FLAG) bit is set to logic 1. If the corresponding Alarm Interrupt
Enable “A1_EN” or “A2_EN” is also set to logic 1, the alarm condition activates the INT signal. The INT remains active
until the alarm flag is cleared by the user.
5.2 RTC - TIMEKEEPER REGISTERS
The time for the RTC module can be controlled and monitored by writing and reading 8-bit control words to the various
registers described below.
5.2.1 RTC_SEC – RTC Seconds Register

The full range of the seconds counter is 0 through 59.
Def. User
Set. Type
[3:0] SECOND 0h R/W 0000 = 0, 0001 = 1, etc. Second counter, BCD format, low bits. Range: 0~9
[6:4] SECOND_10 000b R/W 000 = 0, 001 = 1, etc. Second counter, BCD format, high bits. Range: 0~5
7 RESERVED R/W RESERVED
5.2.2 RTC_MIN – RTC Minutes Register

The full range of the minutes counter is 0 through 59.
Def. User
Set. Type
[3:0] MINUTE 0h R/W 0000 = 0, 0001 = 1, etc. Minute counter, BCD format, low bits. Range: 0~9
[6:4] MINUTE_10 000b R/W 000 = 0, 001 = 1, etc. Minute counter, BCD format, high bits. Range: 0~5
5.2.3 RTC_HR – RTC Hours Register

The full range of the hour counter is 1 through 12 when 12-hour mode is selected, or 0 through 23 when 24-hour mode is
selected.
Def. User
Set. Type
[3:0] HOUR 0h R/W Hour counter, BCD format, low bits. Range: 0~9
4 HOUR_10 0b R/W Hour counter, BCD format, high bits. LSB of HOUR_10.
When 12-hour mode is selected, 1 = PM, 0 = AM
5 PM 0b R/W
When 24-hour mode is selected, this bit is MSB of HOUR_10
1 = 12-hour mode is
selected
6 TIME_12 0b R/W 12-hour or 24-hour mode selection bit.
0 = 24-hour mode is
selected
5.3 RTC - DATE REGISTERS

The date for the RTC module can be controlled and monitored by reading and writing 8-bit control words to the various
registers described below.
5.3.1 RTC_DAY – RTC Day Register

Def. User
Set. Type
[2:0] DAY 000b R/W Day counter, BCD format. Range: 1~7
[7:3] RESERVED R/W RESERVED

5.3.2 RTC_DATE – RTC Date Register

The full range of the date counter is 1 through 31.
Def. User
Set. Type
[3:0] DATE 1h R/W Check default Date counter, BCD format, low bits. Range: 0~9
[5:4] DATE_10 00b R/W Date counter, BCD format, high bits. Range: 0~3
5.3.3 RTC_MONTH – RTC Month Register

The full range of the month counter is 1 through 12.
Def. User
Set. Type
[3:0] MONTH 1h R/W Check default Month counter, BCD format, low bits. Range: 0~9
4 MONTH_10 0b R/W Month counter, BCD format, high bit. Range: 0~1
1 - 100 years
7 CENTURY 0b R/W Century bit is toggled when the year counter overflows from 99 to 0.
0 = 0 year
5.3.4 RTC – Year Register

The full range of the year counter is 0 through 99.
Def. User
Set. Type
[3:0] YEAR 0h R/W Year counter, BCD format, low bits. Range: 0~9
[7:4] YEAR_10 0h R/W Year counter, BCD format, high bit. Range: 0~9
5.4 RTC - ALARM REGISTERS

The two alarms supported by the RTC module can be controlled and monitored by writing 8-bit control words to the
various registers described below.
5.4.1 RTC_AL1_SEC – RTC Second Alarm 1 Value Register

Def. User
Set. Type
[3:0] SECOND_VAL1 0h R/W Second alarm value, BCD format, low bits. Range: 0~9
SECOND_10_VAL
[6:4] 000b R/W Second alarm value, BCD format, high bits. Range: 0~5
1
7 A1M1 0b R/W Alarm 1, mask bit 1
5.4.2 RTC_AL1_MIN – RTC Minute Alarm 1 Value Register

Def. User
Set. Type
[3:0] MINUTE_VAL1 0h R/W Second alarm value, BCD format, low bits. Range: 0~9
[6:4] MINUTE_10_VAL1 000b R/W Second alarm value, BCD format, high bits. Range: 0~5
5.4.3 RTC_AL1_HR – RTC Hour Alarm 1 Value Register

Def. User
Set. Type
[3:0] HOUR_VAL1 0h R/W Hour alarm value, BCD format, low bits. Range: 0~9
4 HOUR_10_VAL1 0b R/W Hour alarm value, BCD format, high bits. LSB of HOUR_10_VAL.
When TIME_12_VAL equals to 1: 1 = PM, 0 = AM
5 PM_VAL1 0b R/W
When TIME_12_VAL equals to 0, this bit is MSB of HOUR_10_VAL.
1 = 12-hour alarm mode is
selected
6 TIME_12_VAL1 0b R/W 12-hour alarm or 24-hour alarm mode selection bit.
selected

5.4.4 RTC_AL1_DAY – Day or Date Alarm 1 Value Register

Def. User
Set. Type
Day alarm value or date alarm value, low bits. BCD format.
[3:0] DAY_DATE_VAL1 0h R/W When DY equals to 1, This value is day alarm value, Range: 1~7.
When DY equals to 0, This value is date alarm value, Range: 0~9
[5:4] DATE_10_VAL1 00b R/W Date alarm value, BCD format, high bits. Range: 0~3
1 = last 4 bits of this
register are day alarm
value.
6 DY1 0b R/W Day/Date alarm select
0 = last 4 bits of this
register are date alarm
value.
5.4.5 RTC_AL2_SEC – Second Alarm 2 Value Register

Def. User
Set. Type
[3:0] SECOND_VAL1 0h R/W Second alarm value, BCD format, low bits. Range: 0~9
SECOND_10_VAL
[6:4] 000b R/W Second alarm value, BCD format, high bits. Range: 0~5
1
5.4.6 RTC_AL2_MIN – Minute Alarm 2 Value Register

I²C Address = Page-0: 76(0x4C), µC Address = 0xA04C
Def. User
Set. Type
[3:0] MINUTE_VAL2 0h R/W Second alarm value, BCD format, low bits. Range: 0~9
[6:4] MINUTE_10_VAL2 000b R/W Second alarm value, BCD format, high bits. Range: 0~5
5.4.7 RTC_AL2_HR - Hour Alarm 2 Value Register

Def. User
Set. Type
[3:0] HOUR_VAL2 0h R/W Hour alarm value, BCD format, low bits. Range: 0~9
4 HOUR_10_VAL2 0b R/W Hour alarm value, BCD format, high bits. LSB of HOUR_10_VAL.
When TIME_12_VAL equals to 1: 1 = PM, 0 = AM
5 PM_VAL2 0b R/W
When TIME_12_VAL equals to 0, this bit is MSB of HOUR_10_VAL.
selected
6 TIME_12_VAL2 0b R/W 12-hour alarm or 24-hour alarm mode selection bit.
selected
5.4.8 RTC_AL2_DAY – Day or Date Alarm 2 Value Register

Def. User
Set. Type
Day alarm value or date alarm value, low bits. BCD format.
[3:0] DAY_DATE_VAL2 0h R/W When DY equals to 1, This value is day alarm value, Range: 1~7.
When DY equals to 0, This value is date alarm value, Range: 0~9
[5:4] DATE_10_VAL2 00b R/W Date alarm value, BCD format, high bits. Range: 0~3
1 = last 4 bits of this register are day alarm value.
6 DY2 0b R/W
0 = last 4 bits of this register are date alarm value.
5.5 RTC - INTERRUPT REGISTERS

The interrupts for the RTC module can be controlled and monitored by writing 8-bit control words to the various registers
described below.

5.5.1 RTC_INT_CTL – RTC Interrupt Control Register

Def. User
Set. Type
1: interrupt enable
0 A1_EN 0b R/W Alarm 1 interrupt enable
0: interrupt disable
1: interrupt enable
1 A2_EN 0b R/W Alarm 2 interrupt enable
0: interrupt disable
5.5.2 RTC_INT_ST – RTC Interrupt Status Register

A logic „1‟ in the A1_FLAG bit indicates that the time matched the value programmed into the registers for alarm 1. If the
A1_EN bit is set to a logic „1‟ at the time the A1_FLAG goes to logic „1‟, the INT pin will be asserted. The A1_FLAG is
cleared when a logic „1‟ is written to this register location. This bit can only be written to logic „1‟. Attempting to write a
logic „0‟ leaves the value unchanged.
A logic „1‟ in the A2_FLAG bit indicates that the time matched the value programmed into the registers for alarm 2. If the
A2_EN bit is set to a logic „1‟ at the time the A2_FLAG goes to logic „1‟, the INT pin will be asserted. The A2_FLAG is
cleared when a logic „1‟ is written to this register location. This bit can only be written to logic „1‟. Attempting to write a
logic „0‟ leaves the value unchanged.
Def. User
Set. Type
1: time match alarm 1 value
0 A1_FLAG 0b RW1C Alarm 1 interrupt flag
0: No match
1: time match alarm 2 value
1 A2_FLAG 0b RW1C Alarm 2 interrupt flag
0: No match
5.6 RTC RESERVED REGISTERS

5.6.1 RTC - RESERVED Registers

6.0 GENERAL PURPOSE TIMERS

6.1 GENERAL PURPOSE TIMERS – GENERAL DESCRIPTION
The P95020 includes two independent general purpose timers. The first is an 8-bit General Purpose Timer that operates
on a user-selectable time base of 32.768 kHz, 1024 Hz, 1Hz, or 1 Minute. The second is an 8-bit Watchdog Timer that
operates on a user-selectable time base of 8Hz, 1Hz, 0.5Hz, or 1 Minute
6.1.1 GENERAL PURPOSE TIMER

To use the General Purpose Timer (GP), an 8-bit value must be loaded in to the General Purpose Timer Count Register
and a time base (count interval) value must also be loaded into bits [1:0] of the General Purpose Timer Timebase
Register. The General Purpose Timer can then be enabled by writing a logic „1‟ into bit 0 (GPT_EN) of the General
Purpose Timer Enable Register. The General Purpose Timer will then begin counting and continue until the count value
is equal to the value specified in the General Purpose Timer Count Register (timeout value). When the timeout value is
reached, the GPTIMEOUT bit is set to a logic „1‟ in the Timer Interrupt Status Register. If the General Purpose Timer
Interrupt has been enabled by setting bit 0 in the Timer Interupt Register to a logic „1‟ then an interrupt is generated to
alert the system that the timeout value has been reached. THE GPTIMEOUT bit is cleared by writing a logic „1‟ to the
GPTIMEOUT bit in the Timer Interrupt Status Register. Following the interrupt, the General Purpose Timer will stop and
reset to 0. Bit 0 of the General Purpose Timer Enable Register is also reset to 0 following the interrupt. However, the
content of General Purpose Timer Count Register and the General Purpose Timer Timebase Value Registers are
maintained and the count cycle can be repeated by writing a logic „1‟ to GPT_EN. When the General Purpose Timer is
counting, writing a logic „0‟ to GPT_EN will reset and stop the timer.
6.1.2 WATCHDOG TIMER

To use the Watchdog Timer (WD), an 8-bit value must be loaded in to the Watchdog Timer Count Register and a time
base (count interval) value must also be loaded into bits [5:4] of the General Purpose Timer Timebase Register. The
Watchdog Timer can then be enabled by writing a logic „1‟ into bit 0 (WDT_EN) of the Watchdog Timer Enable Register.
The Watchdog Timer will then begin counting and continue until the count value is equal to the value specified in the
Watchdog Timer Count Register (timeout value). When the timeout value is reached, the WDTIMEOUT bit is set to a
logic „1‟ in the Timer Interrupt Status Register. If the Watchdog Timer Interrupt has been enabled by setting bit 4 in the
Timer Interrupt Register to a logic „1‟ then an interrupt is generated to alert the system that the timeout value has been
reached. THE WDTIMEOUT bit is cleared by writing a logic „1‟ to the WDTIMEOUT bit in the Timer Interrupt Status
Register. Following the interrupt, the Watchdog Timer will stop and reset to 0. Bit 0 of the Watchdog Timer Enable
Register is also reset to 0 following the interrupt. The Watchdog Timer can be reset anytime during the count interval by
writing a logic „1‟ to bit 4 of the Watchdog Timer Enable Register before the timer times out to prevent an interrupt from
being generated. After reset the Watchdog Timer restarts automatically.
6.2 GENERAL PURPOSE TIMERS – REGISTERS
6.2.1 PCON_GPT - GENERAL PURPOSE TIMER GLOBAL ENABLE REGISTER
Def. User
Set. Type
0 = Disabled Enable GPT. Disabled GPT retains time value settings but the clock
0 GPT_G_EN 0b R/W
1 = Enabled is gated (low power mode).
6.2.2 WATCHDOG TIMER ENABLE REGISTER

Def. User
Set. Type
0 = Reset
0 WDT_EN 0b R/W Watchdog timer enable/disable
1 = enable count
Write 1 to reset. Read
4 WDT_RST 0b R/W1A Watchdog timer reset. Write 1 to reset. Read always returns 0.
always returns 0.

6.2.3 GENERAL PURPOSE TIMER ENABLE REGISTER

Def. User
Set. Type
0 = Reset
0 GPT_EN 0b R/W General Purpose Timer Enable
1 = Enable Count
6.2.4 TIMER INTERRUPT STATUS REGISTER

Def. User
Set. Type
1: Reached Timeout Count
0 GPTIMEOUT 0b RW1C 0: Timeout Count Not General Purpose Timer Timeout. Write „1‟ to clear.
Reached
[3:1] RESERVED 000b R/W RESERVED
1: Reached Timeout Count
4 WDTIMEOUT 0b RW1C 0: Timeout Count Not Watchdog Timer Timeout. Write „1‟ to clear.
Reached
6.2.5 GENERAL PURPOSE TIMER COUNT REGISTER

Def. User
Set. Type
User programmed number
[7:0] GPTIME FFh R/W General Purpose Timer Count
of cycles to timeout
6.2.6 WATCHDOG TIMER COUNT REGISTER

Def. User
Set. Type
User programmed number
[7:0] WDTIME FFh R/W Watchdog Timer Count
of cycles to timeout
6.2.7 GENERAL PURPOSE TIMER TIMEBASE REGISTER

Def. User
Set. Type
00: 32.768 kHz
01: 1024 Hz
[1:0] GPTB 00b R/W General Purpose Timer Timebase
10: 1 Hz
11: 1 Minute
00: 8 Hz
01: 1 Hz
[5:4] WDTB 00b R/W Watchdog Timer Timebase
10: 0.5 Hz
11: 1 Minute
6.2.8 TIMER INTERRUPT ENABLE REGISTER

Def. User
Set. Type
1: Enabled
0 GPT_INTEN 0b R/W General Purpose Timer Interrupt Enable
0: Disabled
1: Enabled
4 WDT_INTEN 0b R/W Watchdog Timer Interrupt Enable
0: Disabled

6.2.9 GP TIMER - RESERVED Registers

Thru = Page-0: 175(0xAF), µC Address = 0Xa0AF

7.0 DC_DC MODULE

To use the DC_DC regulators, the CKGEN PLLs need to be powered on since the DC_DC needs a 24 MHz clock to
operate. To turn on DC_DC regulators, the global enable bits need to be programmed to “enable”. First, program the
DC_DC voltage/ current limit settings and then set the “enable” bit for that particular DC_DC regulator.
The DC_DC Module can be controlled and monitored by writing 8-bit control words to the various registers. The Base
addresses are defined in Table 3 – Register Address Global Mapping on page 20.
Table 17 – DC-DC Block Registers (Including the CLASS_D BTL Power Bridge)
Size I²C Base
Name Description Register Definition Location
(Bytes) Address Address
BUCK500_0 (BC0) 2 Page-0: 128(0x80) 0xA080 Buck Converter #0, 500 mA Page 76 Section 8.2
BUCK500_1 (BC1) 2 Page-0: 128(0x82) 0xA082 Buck Converter #1, 500 mA Page 76 Section 8.2
BUCK1000 (BC2) 2 Page-0: 128(0x84) 0xA084 Buck Converter #2, 1000 mA Page 76 Section 8.2
LED_BOOST 2 Page-0: 128(0x86) 0xA086 LED_BOOST LED Driver, Including Sinks Page 83 Section 0
BOOST5 2 Page-0: 128(0x88) 0xA088 BOOST5 5V Boost Converter Page 89 Section 0
CLASS_D 4 Page-0: 140(0x8A) 0xA08A CLASS_D BTL Power Bridge Page 93 Section 11.1
RESERVED 2 Page-0: 140(0x8E) 0xA08E RESERVED
Vsys GND
BUCK500_0
500 mA BUCK
Block
Control/
Status BUCK500_1
500 mA BUCK
BUCK1000
Register 1 A BUCK
Register access
Access Package
bus interface
Interface Pins
BOOST5
1.5A BOOST
Reference
& Bias
LED_BOOST
LED Power
LED_BOOST
Current-Sinks
Class D
CLASS_D
Signal
Power Stage
Processing
Figure 15 DC_DC Block Diagram

8.0 2MHz, 500mA & 1000mA SYNCHRONOUS BUCK REGULATORS

There are three Buck Converters in the P95020. They are
 Output Voltage from 0.75V to 3.70V identical except for their output current ratings.
 Programmable in 25mV steps
 Default is mask programmed The two BUCK500 power supplies (BUCK500_0 and
 Current Output: BUCK500_0: 500 mA
BUCK500_1) each provide 0.75V to 3.70V at up to
500 mA.
BUCK500_1: 500 mA
BUCK1000: 1000 mA The BUCK1000 power supply provides 0.75V to 3.70V at
 Peak Efficiency up to 93% up to 1000 mA.
 Current Mode Control, internally compensated All Buck Converters are internally compensated, each
requiring a single input bypass capacitor and an output
 Selectable Operation in PWM or PFM Mode filter consisting of one L and one C component.
 Initialization and Power Sequencing can be controlled APPLICATIONS
by a host & registers The primary usage is to power Digital Cores, Application
 Short Circuit Protection and Programmable Cycle by Processors, and RF Power Amplifiers.
Cycle Overcurrent Limit
 Internal inductor current sensing
 Four (4) preset current limit steps:
25%, 50%, 75% and 100% of full current limit
 Soft Start - Slew Rate Controlled

BUCK500_0_IN
BUCK
CONTROL BUCK500_0 BUCK500_0_OUT
REGISTER &
STATUS STEP_DOWN
CONVERTER
BUCK500_0_GND
500mA
BUCK VOUT ADJ

REGISTER 0.75V TO 3.7V BUCK500_0_FDBK
REGISTER
ACCESS BUS
INTERFACE
BUCK500_1_IN
BUCK
CONTROL BUCK500_1 BUCK500_1_OUT
REGISTER &
STATUS STEP_DOWN
CONVERTER
BUCK500_1_GND
500mA
BUCK VOUT ADJ

REGISTER 0.75V TO 3.7V BUCK500_1_FDBK
REFERENCE
& BIAS
BUCK1000_IN
BUCK
CONTROL BUCK1000 BUCK1000_OUT
REGISTER &
STATUS STEP_DOWN
CONVERTER
BUCK1000_GND
1000mA
BUCK VOUT ADJ

REGISTER 0.75V TO 3.7V BUCK1000_FDBK
Figure 16 – BUCK500 / BUCK1000 Block Diagram

8.1 BUCK1000 & BUCK500 - PIN DEFINITIONS
DIAGRAM ID Pin # BUCK500_0 Pin # BUCK500_1 Pin # BUCK1000
FEEDBACK 085 BC0_ FDBK 081 BC1_FDBK 077 BC2_FDBK
GND 086 BC0_GND 082 BC1_GND 078 BC2_GND
OUT 087 BC0_OUT 083 BC1_OUT 079 BC2_OUT
VIN 088 BC0_IN 084 BC1_IN 080 BC2_IN
8.2 BUCK1000 & BUCK500 - ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA=25C, VIN = VSYS =3.8V, TA = -40°C to +85°C (VIN must be connected to VSYS)
SYMBOL DESCRIPTION CONDITIONS MIN TYP MAX UNIT
VIN Input voltage VIN = VSYS 3.0 4.5 V
VOUT Programmable Output Voltage Range Note 2 0.75 3.70 V
VOUT Output Voltage Step Size 25 mV
OVERALL VIN = 3.0V to 4.5V, IOUT = 0 to Imax,
Overall Output Voltage Accuracy -3 +3 %
Note 1, Note 3
Maximum Output Current in PFM Mode,
(BUCK500) 100
IOUT-PFM VIN = 3.0V to 4.5V, Note 1, Note 3 mA
Maximum Output Current in PFM Mode, 200
(BUCK1000)
Maximum Output Current in PWM Mode,
500
IOUT-PWM (BUCK500) VIN = 3.0V to 4.5V, Note 1, Note 3 mA
1000
Maximum Output Current in PWM Mode,


(BUCK1000)
Full Scale Cycle by Cycle Current Limit
(BUCK500) 0xA081 [3:2], 0xA083 [3:2], 650 1050
ICLP mAPK
Full Scale Cycle by Cycle Current Limit 0xA085 [3:2] both bits set to 1 1200 1800
(BUCK1000)
ICLP Cycle by Cycle Current Limit Step Size 4 preset levels 25 %
ISCP is a secondary current
Switch Peak Short Circuit Current (BUCK500) 1.3
ISCP protection to prevent over current APK
Switch Peak Short Circuit Current (BUCK1000) 2.25
runaway.
High Side Switch On Resistance (BUCK500) 0.5
RDS-ON-HS ISW = -50mA 
High Side Switch On Resistance (BUCK1000) 0.25
Low Side Switch On Resistance (BUCK500) 0.5
RDS-ON-LS ISW = 50mA 
Low Side Switch On Resistance (BUCK1000) 0.25
fPWML PWM Mode Clock Frequency (Low) Note 1, Note 4, Note 6 1 MHz
fPWMH PWM Mode Clock Frequency (High) Note 1, Note 4, Note 6 2 MHz
DMAX PWM Mode Max Duty Cycle 100 %
tON(MIN) Minimum Output On Time 75 ns
tSFTSLEW Soft Start Output Slew Rate 12.5 mV/µs
IQS Not operating – Shutdown Mode 1 µA

IQPFM Quiescent Operating Current Operating (No Load) PFM Mode 60 µA
IQPWM Operating (No Load) PWM Mode 3.5 mA
Note 1, Note 5
Shutdown Mode, VSW=4.5V,
ILEAKSW Leakage Current Into SW pin, 1 µA
DCDC_GLOBAL_EN (0x05)=0;
Shutdown Mode, VIN = 4.5V,
ILEAKVIN Leakage Current Into VIN pin VSW=0V 1 µA
DCDC_GLOBAL_EN (0x05) = 0;
IFDBK Input Current Into FDBK pins Operation Mode -1 +1 µA
ZFDBK_OFF FDBK Pull Down Resistance in Shutdown Shutdown Mode 7.1 k
UVLO Under Voltage Lock Out Threshold VSYS Rising 2.85 2.95 V
UVLOHYST Under Voltage Lock Out Hysteresis 150 mV
Notes:
2. Maximum output voltage limited to (VIN - IPEAK x RDS-ON_P).
3. Component value is COUT =22 µF, L=4.7µH, CIN=10µF.
4. Buck clock will be coming from external crystal through PLL. The resultant frequency will be in 1% range from the
nominal.
5. BUCK1000, BUCK500 control register addresses / bits.
Description Address (I2C) Value

Not Operating Buck#0 (500mA) 0x05 [0:0] = 0
Buck#1 (500mA) 0x05 [1:1] = 0
Buck#2 (1000mA) 0x05 [2:2] = 0
Operating (No Load) PFM Mode Buck#0 (500mA) 0x80 [0:0] = 1
Buck#1 (500mA) 0x82 [0:0] = 1
Buck#2 (1000mA) 0x84 [0:0] = 1
Operating (No Load) PWM Buck#0 (500mA) 0x80 [0:0] = 0
Mode Buck#1 (500mA) 0x82 [0:0] = 0
Buck#2 (1000mA) 0x84 [0:0] = 0
6. Buck regulator clock frequency control register addresses.
Description Address (I2C) Value

1 MHz Buck#0 (500mA) 0x80 [1:1] = 0
Buck#1 (500mA) 0x82 [1:1] = 0
Buck#2 (1000mA) 0x84 [1:1] = 0
2 MHz Buck#0 (500mA) 0x80 [1:1] = 1
Buck#1 (500mA) 0x82 [1:1] = 1
Buck#2 (1000mA) 0x84 [1:1] = 1
8.3 BUCK CONVERTERS – TYPICAL PERFORMANCE CHARACTERISTICS

Buck500_0 PWM efficency Vinp 3.8V
100
90
80
efficency %
70
60
50
40
30
1 10 100 1000
load mA
efficiency % 1.8V efficiency % 3.3V efficiency % 1.2V
Figure 17 – BUCK500 DC-DC Regulator Efficiency vs Load Current PWM Mode
Buck1000 PWM efficiency Vinp 3.8V
100
90
80
efficiency %
70
60
50
40
30
1 10 100 1000
Load mA
efficiency % 1.2V efficiency % 1.8V efficiency % 3.3V
Figure 18 – BUCK1000 DC-DC Regulator Efficiency vs Load Current PWM Mode

Buck500_0 PFM efficiency Vinp 3.7V Vout 2.30V
88
87.5
87
86.5
86
efficiency
85.5
85
84.5
84
83.5
83
82.5
0 2 4 6 8 10 12 14 16
load mA
Figure 19 – BUCK500 DC-DC Regulator Efficiency vs Load Current PFM Mode
8.4 BUCK1000 & BUCK500 - REGISTER ADDRESSES

All three Buck Converters can be controlled and monitored by writing 8-bit control words to either the Output Voltage
Register or the Control Register. The Base addresses are defined in Table 3 – Register Address Global Mapping on page
20. The offset addresses are defined as the Base Address in the following table.
Table 18 – BUCK500_0, BUCK500_1 and BUCK1000 Register Addresses
Output Voltage Register Control Register
Name Description
I²C Address Base Address I²C Address Base Address
BUCK500_0 Buck Converter # 0 (500 mA) Page-0: 128(0x80) 0xA080 Page-0: 129(0x81) 0xA081
BUCK500_1 Buck Converter # 1 (500 mA) Page-0: 130(0x82) 0xA082 Page-0: 131(0x83) 0xA083
BUCK1000 Buck Converter # 2 (1000 mA) Page-0: 132(0x84) 0xA084 Page-0: 133(0x85) 0xA085
8.4.1 BUCK500 & BUCK1000 - Output Voltage Registers: (See Table 18 above for addresses)
The Output Voltage Register contains the Enable bit and the Output Voltage setting bits.
Def. User
Set. Type
[See
[6:0] VOUT RW (See Table 19) Output Voltage = VOUT * 0.025V + 0.75V
]
1 = Enable
7 ENABLE 0h RW Enable Output
0 = Disable
Table 19 – Output Voltage Register Settings, Bits [6:0]

Bit Output Bit Output Bit Output Bit Output Bit Output
Setting Voltage Setting Voltage Setting Voltage Setting Voltage Setting Voltage
0000000 0.750 0011000 1.350 0110000 1.950 1001000 2.550 1100000 3.150
0000001 0.775 0011001 1.375 0110001 1.975 1001001 2.575 1100001 3.175
0000010 0.800 0011010 1.400 0110010 2.000 1001010 2.600 1100010 3.200
0000011 0.825 0011011 1.425 0110011 2.025 1001011 2.625 1100011 3.225
0000100 0.850 0011100 1.450 0110100 2.050 1001100 2.650 1100100 3.250
0000101 0.875 0011101 1.475 0110101 2.075 1001101 2.675 1100101 3.275
0000110 0.900 0011110 1.500 0110110 2.100 1001110 2.700 1100110 3.300
0000111 0.925 0011111 1.525 0110111 2.125 1001111 2.725 1100111 3.325
0001000 0.950 0100000 1.550 0111000 2.150 1010000 2.750 1101000 3.350
0001001 0.975 0100001 1.575 0111001 2.175 1010001 2.775 1101001 3.375
0001010 1.000 0100010 1.600 0111010 2.200 1010010 2.800 1101010 3.400
0001011 1.025 0100011 1.625 0111011 2.225 1010011 2.825 1101011 3.425
0001100 1.050 0100100 1.650 0111100 2.250 1010100 2.850 1101100 3.450
0001101 1.075 0100101 1.675 0111101 2.275 1010101 2.875 1101101 3.475
0001110 1.100 0100110 1.700 0111110 2.300 1010110 2.900 1101110 3.500
0001111 1.125 0100111 1.725 0111111 2.325 1010111 2.925 1101111 3.525

Bit Output Bit Output Bit Output Bit Output Bit Output
Setting Voltage Setting Voltage Setting Voltage Setting Voltage Setting Voltage
0010000 1.150 0101000 1.750 1000000 2.350 1011000 2.950 1110000 3.550
0010001 1.175 0101001 1.775 1000001 2.375 1011001 2.975 1110001 3.575
0010010 1.200 0101010 1.800 1000010 2.400 1011010 3.000 1110010 3.600
0010011 1.225 0101011 1.825 1000011 2.425 1011011 3.025 1110011 3.625
0010100 1.250 0101100 1.850 1000100 2.450 1011100 3.050 1110100 3.650
0010101 1.275 0101101 1.875 1000101 2.475 1011101 3.075 1110101 3.675
0010110 1.300 0101110 1.900 1000110 2.500 1011110 3.100 1110110 3.700
0010111 1.325 0101111 1.925 1000111 2.525 1011111 3.125
Note – Contains an initial 0.75V offset. Performance and accuracy are not guaranteed with bit combinations above 1110110.
8.4.2 BUCK1000 & BUCK500 - Control Register: (See Table 18 for addresses)
The Control Register contains the Current Limit setting bits, Control bits and Status bits.
Def. User
Set. Type
1 = PFM mode
0 PWM_PFM 0 RW PWM/PFM Mode Select
0 = PWM mode
1 = 2 MHz
1 CLK_SEL 1 RW Clock Frequency
0 = 1 MHz
[3:2] I_LIM 3h RW (See Table 20) Cycle by Cycle Current Limit (%)
1 = Fault
4 SC_FAULT N/A R Short Circuit Fault
0 = OK
1 = Power Good
5 PGOOD N/A R 0 = Power Not Power Good
Good
1 = Enable writes to
BUCK 3 MSB bits in
DAC
7 DAC_MSB_EN 1b RW BUCK VOUT 3 MSB bits write protection
0 = Disable writes to
BUCK 3 MSB bits in
DAC
Table 20 – Control Register Cycle by Cycle Current Limit (I_LIM) Settings

for Bits [3:2] [Note ]
Bit
Bit 3 Description
2
0 0 Current Limit = 25 %
Note – Current Limit is at maximum when bits [3:2] are both set to 1.
8.5 BUCK1000 & BUCK500 - ENABLING & DISABLING

There are two methods of disabling each Buck Converter: the Global Enable bit and the local ENABLE bit (Output Voltage
Register, Bit 7). Table 21 shows the interoperation of the two methods.
Table 21 – Interoperability of enabling/disabling methods vs. loading default values.

Internal POR Global Enable ENABLE ON/OFF status REGISTER VALUE STATUS
0 X 0 OFF PREVIOUS SETTINGS
0 0 X OFF PREVIOUS SETTINGS
0 1 1 ON PREVIOUS SETTINGS
1 X X OFF LOAD DEFAULT VALUES
8.5.1 BUCK1000 & BUCK500 - Initialization and Power-Up

During an IC re-initialization or “cold boot” an internal POR disables the Buck Converter and loads the default values into
the registers. The default values are only loaded into the registers when there is a POR event.
The default settings for the Output Voltage Register are:
Function Default Setting
Local Enable Bit Disabled
3.3V (BUCK500_0)
Output Voltage 1.8V (BUCK500_1)
1.2V (BUCK1000)
The default settings for the Control Register are:


Current Limit 100%
Clock Frequency 2 MHz
Operating Mode PWM
After the external POR releases, the individual Global Enable bits can be set to HIGH. Since the default value of the local
ENABLE bit is LOW, the supply will not start at this time.
To enable a converter, the local ENABLE bit is set to HIGH by writing the voltage value to the Output Voltage Register.
The Output Voltage value must be included each time the converter is enabled or disabled. There is a default value for
each converter that can be read and written back along with the ENABLE bit or a different value can be written. When the
ENABLE bit becomes set the Buck Converter will then enter its soft-start sequence, and transition to the programmed
voltage.
NOTE: Changes to the Output Voltage Register settings can be written directly without disabling the converter.
8.5.2 BUCK1000 & BUCK500 - Normal Disabling / Enabling

Setting either the Global Enable bit to LOW or the local ENABLE bit to LOW will turn off the Buck Converter.
The Global Enable bit‟s sole purpose is to shut down the converter into its lowest power shutdown mode. It is not
intended to be used to toggle the Buck Converter off and on. Proper operation is only guaranteed by toggling the
ENABLE bit once the Global Enable bit is set HIGH to take it out of low power shutdown mode.
8.5.3 BUCK1000 & BUCK500 - Soft Start Sequence

There is a 50 µs delay after the ENABLE bit is set and then an internal counter ramps up, requiring 80 µs/volt from zero to
the programmed Output Voltage setting. Once the Soft Start sequence is initiated, any changes to the values in the
Output Voltage Register are ignored until the Soft Start sequence is complete.
8.5.4 BUCK1000 & BUCK500 - Current Limit Protection

The Buck Converter includes pulse by pulse peak current limiting circuitry for over-current conditions. The limit can be set
at various percentages of maximum setting (See Table 20). During an over-current condition the output voltage is allowed
to drop below the specified voltage and will be indicated by the status of the PGOOD bit. When the over-current state is
ended the output returns to normal operation.
8.5.5 BUCK1000 & BUCK500 - Short Circuit Protection

The Buck Converter includes short-circuit protection circuitry. When a short circuit occurs, the output will be latched into a
disabled mode and a fault will be indicated in the SC_FAULT bit. The local ENABLE bit must be first toggled LOW and
then back to HIGH again to clear the short circuit latch. Any subsequent Short Circuit will override the local ENABLE bit
setting and re-latch the output to a disabled mode.
8.6 BUCK1000 & BUCK500 - APPLICATIONS INFORMATION
VIN = 3.8V
VIN
CONTROL &
MONITORING CIN
BUCK FEEDBACK
L
CONTROLLER VOUT
OUT
1 2
COUT
GND
Figure 20 – BUCK500 or BUCK 1000 Applications Diagram
8.6.1 BUCK500 - Recommended External Components

ID Description
CIN 10 µF, 10V, Ceramic, X5R
COUT 22 µF, 10V, Ceramic, X5R
L 4.7 µH, 1.5A (for 1 MHz or 2 MHz operation)

8.6.2 BUCK1000 - Recommended External Components

ID Description
CIN 10 µF, 10V, Ceramic, X5R
COUT 22 µF, 10V, Ceramic, X5R
4.7 µH, 3.0A (for 1 MHz operation)
L
4.7 µH, 3.0A (for 2 MHz operation)

9.0 HIGH EFFICIENCY 10 LED BOOST CONVERTER AND SINKS

The LED BOOST is a current mode PWM boost converter that
 Fully controllable by a host or I2C interface provides power to one or two strings of white or colored LEDs as
 Peak efficiency > 88% with two strings of 10 LEDs used in LCD displays and keyboard backlighting. The converter
is fully compensated and requires no additional external
 Low Shutdown Current (<1uA) components for stable operation at a user-selectable switching
frequency of either 1MHz or 500kHz. The converter also
 0.5MHz or 1MHz fixed frequency low noise operation includes two regulated current sink drivers with internal FETs,
providing two outputs each containing the same number of LEDs
 Supports up to two (2) strings of 3 to 10 up to 25 mA each or a single (combined) output up to 50 mA
total. Safe operation is ensured by a user programmable over-
series-connected white LEDs
current limiting function and by output over-voltage protection.
 Programmable Sink current:
0-25 mA per string or 0-50mA for one string only REQUIREMENTS
 Half range setting also available
1. Both LED strings must contain the same number of
 Soft Start and Sink Current Slew Rate Control LEDs with similar forward voltage drops for each LED.
 Programmable Over-Current Limit through external 2. The block requires one external NFET and an external
Schottky diode (rated ≥ 45V for 10 White LEDs in series).
sense resistor The output power is limited by the voltage and current
 Programmable Output Voltage Protection through ratings of the external FET and Schottky diode.
external resistor divider 3. If only one LED string is used, SINK1 and SINK2 must
be shorted together. The maximum current and current
 UVLO shutdown protection per programming step for the combined strings can
remain at full (50 mA total, 0.78 mA/step) or can be
reduced (25 mA total, 0.39 mA/step).
VIN
L
VIN
+ PWM
GATE
LOGIC DRV
-
+ + ISENSE
CSA
+ - R3
INTERFACE
INTERNAL
GND
CLK R1
OC - +
+ 0.15V
-
1.2V
OV - VSENSE
+ Vref
R2
+
SHDN
EA -
- SINK1
SOFT START Rc
& SHUTDOWN SINK2
CONTROL IDAC &

Cc
SINKS
IDAC PROGRAM BUS
Figure 21 – White LED Boost & Sink Driver Block Diagram

9.1 LED_BOOST - ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VIN=VSYS = 3.8V, VPGND=VDGND=0V, VLED_BOOST_SINK=0.9V, TA = -40°C to +85°C, COUT=1µF,
L=22µH
If tied to other than
VIN LED Boost Input Voltage 3.0 5.5 V
VSYS = 3.0V to 4.5V
LEDREG LED Boost Regulation Voltage 0.90 V
Trip level of
VOVP OVP Trip Voltage 1.15 1.25 V
LED_BOOST_VSENSE input
VISENSE Current Sense Maximum Voltage VSYS = 3.0V to 4.5V 150 180 210 mV
IBIAS Input Bias Current For OVP and Isense -0.1 0.1 µA
TGRISE LED_BOOST_GATE Pin Rise Time CGATE = 1nF 12 ns
TGFALL LED_BOOST_GATE Pin Fall Time CGATE = 1nF 7 ns
LED_BOOST_ISET 0x86 [4:0],
0.78 25
ISINK_FULL LED Current Range – Full Scale LED_BOOST_SCALE 0x86 [6:6] = mA
0.39 12.5
0 - Half Scale, 1 - Full Scale
ISINK_FULL LED Current Step Size (LSB) – Full Scale 0.78 mA
ISINK_HALF LED Current Step Size (LSB) – Half Scale 0.39 mA
LEDSLEW LED Current Step Slew Rate ILED Change From 5mA to 20mA 1/32 LSB/us
InitACC Initial Current Accuracy ISINK = 20 mA, VSINK = 0.9V -5 +5 %
LED_BOOST_CTRL 0x87 [1:1] = 0
fCLKL Main Clock (Low) 0.5 MHz
=0.5 MHz, Note 1
LED_BOOST_CTRL 0x87 [1:1] = 1
fCLKH Main Clock (High) 1.0 MHz
= 1.0 MHz, Note 1
DCLOCK Max Gate Output Duty Cycle 94 %
tON(MIN) Minimum Output On Time 100 ns
IQPS VLED_BOOST_VIN Shutdown Current VLED_BOOST_VIN = 4.5V 1 µA
IDD Operating Current Note 2 1.6 mA
VSYS Rising. (Shared DC/DC, LDOs
UVLO Under Voltage Lock Out Threshold 2.85 2.95 V
except Pre-DC/DC)
Notes:
1. Guaranteed by design and/or characterization
2. Value does not include current through external components
9.2 LED_BOOST – TYPICAL PERFORMANCE CHARACTERISTICS
LED_Boost Efficiency (%) vs. Iout (mA)

with two strings of 10 LEDs
100%
90%
80%
EFFICIENCY (%)
70%
60%
VIN = 4.5V
50%
VIN = 3.8V
40%
30%
20%
10%
0%
0 10 20 30 40 50
IOUT (mA)
Figure 22 – LED Boost Efficiency vs Load Current (two srings of 10 LEDs)

LED_Boost EFFICIENCY vs. VIN

with two strings of 10 LEDs
100%
90%
80%
EFFICIENCY (%)
70%
60%
IOUT = 40mA
50%
IOUT = 20mA
40%
30%
20%
10%
0%
3 3.5 4 4.5 5 5.5
VIN (V)
Figure 23 – LED Boost Efficiency vs VIN (two srings of 10 LEDs)
9.3 LED_BOOST - REGISTER SETTINGS

Output Current Register and Control Register control and monitor the LED_BOOST Driver. The controller can be
programmed by writing 8-bit control words to these registers.
The Base addresses are defined in Table 3 – Register Address Global Mapping on page 20.
9.3.1 LED_BOOST - Output Current Register

The Output Current Register contains the Enable Bit and the Sink Current settings.
Def. User
Set. Type
Sink Current (See Table 22)
If LED_BOOST_SCALE (Bit 6) = 1, use Full Scale values:
Full Scale = 0.78 mA
[4:0] LED_BOOST_IOUT 00000b RW LED Current = IOUT * 0.78 mA + 0.78 mA
Half Scale = 0.39 mA
If LED_BOOST_SCALE (Bit 6) = 0, use Half Scale values:
LED Current = IOUT * 0.39 mA + 0.39 mA
1 = Full Current Scale
6 LED_BOOST_SCALE 1b RW Current Scale
0 = Half Current Scale
1 = Enable
7 LED_BOOST_ENABLE 0b RW Enable Output Voltage
0 = Disable
Table 22 – Register 0xA086 (0x86) IOUT Current Settings for Bits [4:0], Half Scale and Full Scale
Bit Current (mA) Bit Current (mA) Bit Current (mA) Bit Current (mA) Bit Current (mA)
Setting Half Full Setting Half Full Setting Half Full Setting Half Full Setting Half Full
00000 0.39 0.78 00111 3.13 6.25 01110 5.86 11.72 10101 8.59 17.19 11100 11.33 22.66
00001 0.78 1.56 01000 3.52 7.03 01111 6.25 12.50 10110 8.98 17.97 11101 11.72 23.44
00010 1.17 2.34 01001 3.91 7.81 10000 6.64 13.28 10111 9.38 18.75 11110 12.11 24.22
00011 1.56 3.13 01010 4.30 8.59 10001 7.03 14.06 11000 9.77 19.53 11111 12.50 25.00
00100 1.95 3.91 01011 4.69 9.38 10010 7.42 14.84 11001 10.16 20.31
00101 2.34 4.69 01100 5.08 10.16 10011 7.81 15.63 11010 10.55 21.09
00110 2.73 5.47 01101 5.47 10.94 10100 8.20 16.41 11011 10.94 21.88
Note – Current Output contains an initial offset of 0.39 mA for Half Scale or 0.78 mA for Full Scale.

9.3.2 LED_BOOST - Control Register

This Register contains clock select settings
Def. User
Set. Type
1 = 1.0 MHz
1 LED_BOOST_CLK_SEL 1b RW Clock Frequency
0 = 0.5 MHz
[5:4] RESERVED N/A R RESERVED
9.4 LED_BOOST - ENABLING & DISABLING

There are two methods of disabling the LED_BOOST Converter: the Global Enable bit and the local ENABLE bit (Output
Current Register, Bit 7). Table 23 shows the interoperation of the two methods.

9.4.1 LED_BOOST - Initialization and Power-Up

During an IC re-initialization or “cold boot” an internal POR disables the LED_BOOST Converter and loads the default
values into the registers. The default values are only loaded into the registers when there is a POR event.
The default settings for the Output Current Register are:
Scale High
Output Current 0.78 mA

After the internal POR releases, the Global Enable bit can be set to HIGH. Since the default value of the local ENABLE
bit is LOW, the converter will not start at this time.
To enable the converter, the local ENABLE bit is set to HIGH by writing a “1” to the Output Current Register. The Output
Current value must be included each time the converter is enabled or disabled. The default value for the converter can be
read and written back along with the ENABLE bit or a different value can be written. When the ENABLE bit is set, the
LED_BOOST Converter will begin its soft-start sequence, ending at the programmed current.
NOTE: Changes to the Output Current Register settings can be written directly without disabling the converter.
9.4.2 LED_BOOST - Normal Disabling / Enabling

Setting either the Global Enable bit to LOW or the local ENABLE bit to LOW will turn off the LED_BOOST Converter.
intended to be used to toggle the LED_BOOST Converter off and on. Proper operation is only guaranteed by toggling the
ENABLE bit HIGH once the Global Enable bit is set HIGH to take it out of low power shutdown mode.
9.4.3 LED_BOOST - SOFT START

The LED BOOST uses the combination of a reduced initial current limit setting with the slow charge of its large internal
compensation capacitor to affect a controlled ramp of the output supply. This limits the inrush current and consequently
helps eliminate drooping in the input supply during the ramp up

9.4.4 LED_BOOST - SLEW CONTROL

Slew Control forces the two sink currents to be ramped up or down in time steps of 32 µs per LSB from the previous
current setting to the newly programmed current setting. It is important to wait until Slew Control is complete before again
changing the current setting because any changes to the programmed sink current level are ignored while Slew Control is
ramping.
9.5 LED_BOOST – Over-Voltage Protection
Output over-voltage protection is provided through the LED_BOOST_VSENSE pin. If the input level of this pin rises above
1.2V (nominal) then the error amplifier is reset and the boost converter will re-enter soft start). The converter will hiccup
indefinitely if the the over-voltage condition remians. Persistent hiccup will indicate a real fault condition such as an open
LED string or simply that the the over-voltage trip is incorrectly set.
The over-voltge trip is set by tying a resistor divider between the output capactior node and gnd and to the
LED_BOOST_VSENSE pin. The resistor divder is shown in figure 14 below. The values of R1 and R2 calculated using
the following equations:
1.2V xV IN 1 V IN
R2  x R1   R2
1.1 x 1A 0.9V  n x V LED 1A Equation 1
9.6 LED_BOOST – Over-Current Limiter
The LED boost converter requires a sense resistor to be placed between the source of the Nch MOSFET and GND. This
sense resistor is used for both current mode control and over-current limiting.
9.7 LED_BOOST - APPLICATIONS INFORMATION
VIN = 3.0 to 5.5V

LED_BOOST_VIN 090
CIN L
VEXT = 3.0 to 5.5V
BOOST LED_BOOST_GATE 092 2 1
CONTROLLER CEXT
SW1
D1 VOUT ≈ n*VLED+VSINK
LED_BOOST_ISENSE 091
LED1_n LED2_n
R3
I_total
CONTROL & LED_BOOST_PGND2 093
MONITORING R1
LED_BOOST_VSENSE 089
R2 LED1_0
COUT
I1
SINK LED_BOOST_SINK1 094
LED2_0
CONTROLLER I2
LED_BOOST_SINK2 095
Figure 24 – LED_BOOST Application Schematic
 VIN External Voltage is used to power the gate driver for the external NFET, SW1.
 VEXT = 3.0 to 5.5V, connects externally to the inductor and system power
 LED_BOOST can be set via R1 and R2 to provide a protection voltage between VEXT and 40V for protecting capacitor
COUT in case the LED strings open. This voltage should be set below the voltage rating of COUT.
 The LED_BOOST converter monitors the current sense elements in the sink blocks and reduces its output voltage as
necessary to keep the headroom voltage as low as possible to minimize losses.
9.7.1 LED_BOOST - Application Specific Operating Parameters

These parameters are dependent upon external components and as such are neither specified nor tested but are included for application reference.
Unless otherwise specified, performance is measured @ VIN = 3.8V, VEXT = 5.0V and TA = 25°C
Symbol Parameter Min Typ Max Unit Comment
VPROTECT Protection Voltage Range VEXT 40 V Select R1 and R2 to set. [See Equation 1 ]
RDS-ON External NFET Drain-Source Resistance 0.400  VIN = 5.0V, TJ = 25°C

Symbol Parameter Min Typ Max Unit Comment

IRIP Output Current Ripple 1 % 45 mA load, COUT = 1 F
 Efficiency 80 % VIN = 5.0V, IOUT = 40 mA total
Note – To within 1% of final value, based on Application Schematic (See Figure 24) with 20% to 80% load change.
LED_BOOST - Recommended External Components

ID Description Part No Manufacturer
CIN Capacitor, Ceramic, 1.0 µF 10V, X5R C0402X5R100-105KNE Venkel
CEXT Capacitor, Ceramic, 10 µF, 10V, X5R C0603X5R100-106KNP Venkel
COUT Capacitor, Ceramic, 1.0 µF, 50V, X7R ECJ-3YX1H105K Panasonic
L Inductor, 22 µH, 1.05A B82462G4223M EPCOS
R1 Resistor, See Equation 1 to calculate value Panasonic
R2 Resistor, See Equation 1 to calculate value Panasonic
R3 Resistor, 0.15 ohm, 1/8W ERJ-2BSFR15X Panasonic
SW1 N_FET, 45V, 2.0A RTR020N05 ROHM
D1 Diode, Schottky, 50V, 1 A MSS1P5-E3/89A Vishay/General Semiconductor

10.0 BOOST5 – 1.5A, SYNCHRONOUS PWM BOOST CONVERTER

The BOOST5 is a synchronous, fixed frequency boost
 Current Mode Control, internally compensated converter, delivering high power to the Class D Audio
Power Amplifier and LDOs requiring input voltages greater
 Operation in PWM Mode than the system voltage. Capable of supplying 5.0V at
700mA, the device contain an internal NMOS switch and
 Peak Efficiency up to 91% PMOS synchronous rectifier.
 Initialization and Power Sequencing can be controlled A switching frequency of 1.0MHz minimizes solution
footprint by allowing the use of tiny, low profile inductors.
by host & registers
The current mode PWM design is internally compensated,
 Output Voltage adjustable in 50mV steps reducing external parts count.
from 4.05V to 5.0 V
 Current Output: 700mA continuous at 5V (VIN ≥ 3.6V)

 Inductor Peak Current Limit / Soft Start
 Internal current sensing determines
peak inductor current
 Soft Start circuitry
VIN = (3.0V TO 4.5V)

BOOST5_SW1 2 1
075
073
BOOST5_SW2
CIN
OPTIONAL
SCHOTTKY
CONTROL &
MONITORING SR1
VOUT = (4.05V TO 5.0V)
074
BOOST5_OUT
PWM CONTROLLER
COUT
SW1
PGND1
076
Figure 25 – BOOST5 Block Diagram

10.1 BOOST5 - ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VEXT=VSYS = 3.8V, VBOOST5_OUT=5V, TA = -40°C to +85°C,
VIN Input Voltage (External) 3.0 4.5 V
VOUT Programmable Output Voltage Range V IN cannot be higher than VOUT 4.05 5.0 V
Note 2
VOUT Output Voltage Step Size 0.050 V
VSYS =3.0V to 4.5V
Note 1
VO-PWM Overall Output Voltage Accuracy COUT=20µF, and L=2.2µH -3 +3 %
SETPOINT Output Voltage Set Point Accuracy Measure at the BOOST5_OUT pin -2 +2 %
ILOUT-PEAK Peak Inductor Current Limit 0xA089 [3:2] = 11b 1.5 1.7 2.0 A
RDS-ON-HS Synchronous Rectifier On Resistance ISW = -50mA 0.18 
RDS-ON-LS Low Side Switch On Resistance ISW = 50mA 0.18 
Synchronous Rectifier Operation
ISRTH +40 mA
Threshold Current
fPWML Clock Frequency (Low PWM Mode) Crystal Note. 0.5 MHz
fPWMH Clock Frequency (High PWM Mode) Crystal Note. 1.0 MHz
Operating, Non-Switching, No Load
IQN Quiescent Operating Current 0.75 mA
BOOST5_OUTPUT 0x88 [7:7] =1 (Enable)
DMAX Maximum PWM Duty Cycle 90 %
tON(MIN) Minimum Low Side Switch On Time 100 ns
ILEAKSW Leakage Current Into SW pin Shutdown Mode, VSW = 4.5V 1 µA
ILEAKVOUT Leakage Current Into VOUT pin Shutdown Mode, VOUT = 5.0V, VSW = 0V 1 µA
UVLO Under Voltage Lock Out Threshold VSYS Rising 2.85 2.95 V
Notes:
1. Guaranteed by design and/or characterization
2. External Schottky diode is required between BOOST5_OUT and BOOST5_SW if VOUT is 4.5V or greater.
3. Clock will be coming from external crystal through PLL. The resultant frequency will be in 1% range from the
nominal.
10.2 BOOST5 - REGISTER SETTINGS
Register 0xA088 and Register 0xA089 control and monitor the BOOST5 Power Supply. The regulator can be
programmed by writing 8-bit control words to these registers. The Base addresses are defined in Table 3 – Register
Address Global Mapping on page 20.
10.2.1 BOOST5 - Output Voltage Register

The Output Voltage Register contains the Enable Bit and the Output Voltage settings
Def. User
Set. Type
(See Table
[4:0] BOOST5_VOUT 10011b RW Output Voltage = BOOST5_VOUT * 0.05V + 4.05V
24)
1 = Enable
7 ENABLE 0b RW Enable BOOST5
0 = Disable
Note – Default voltage setting VOUT = 5.00 V.
Table 24 – Register 0xA088 Output Voltage Bit Setting [4:0]

Bit Output Bit Output Bit Output
Setting Voltage Setting Voltage Setting Voltage
00000 4.05 00111 4.40 01110 4.75
00001 4.10 01000 4.45 01111 4.80
00010 4.15 01001 4.50 10000 4.85
00011 4.20 01010 4.55 10001 4.90
00100 4.25 01011 4.60 10010 4.95
00101 4.30 01100 4.65 10011 5.00
00110 4.35 01101 4.70
Note – Contains an initial 4.05V offset.

10.2.2 BOOST5 - Control Register

The Control Register contains Power Good, Peak Current Limit and Clock Select settings
Def. User
Set. Type
0 RESERVED 0b RW
1 = 1.0 MHz
1 CLOCK_SEL 1b RW Clock Frequency
0 = 0.5 MHz
[3:2] I_LIM 11b RW [See Table 25] Peak Current Limit
4 RESERVED 0b RW
1 = Power Good
5 PGOOD 0b R Power Good
0 = Power Bad
Table 25 – Register 0xA089 (0x89) Peak Current Limit (I_LIM) Settings Bits [3:2]
0 0 Peak Current Limit = 25 %
1 1 Peak Current Limit = 100 % A
Note – Peak Current Limit is maximum when bits [3:2] are both set to 1.
10.3 BOOST5 - ENABLING & DISABLING

There are two methods of disabling the BOOST5 Converter: the Global Enable bit and the local ENABLE bit. Table 26
shows the interoperation of the two methods.

10.3.1 BOOST5 - INITIALIZATION AND DEVICE POWER-UP

During an IC re-initialization or “cold boot” an internal POR disables the BOOST5 Converter and loads the default values
into the registers. The default values are only loaded into the registers when there is a POR event.
The default settings for the Output Voltage Register are:
Output Voltage 5.0V
Current Limit 100%
After the POR releases, the Global Enable bit can be set to HIGH. Since the default value of the local ENABLE bit is
LOW, the supply will not start at this time.
To enable the BOOST5 converter, the local ENABLE bit is set to HIGH by writing a “1” to the Output Voltage Register.
The Output Voltage value must be included each time the converter is enabled or disabled. The default value for the
converter is read and written back along with the ENABLE bit or a different voltage can be written. When the ENABLE bit
becomes set the BOOST5 Converter enters its soft-start sequence, ending up at the programmed voltage.
NOTE: Changes to the Output Voltage Register settings can be written directly without disabling the converter.
10.3.2 BOOST5 - Normal Disabling / Enabling

Setting either the Global Enable bit to LOW or the local ENABLE bit to LOW will turn off the BOOST5 Converter.
intended to be used to toggle the BOOST5 Converter off and on. Proper operation is only guaranteed by toggling the
ENABLE bit HIGH once the Global Enable bit is set HIGH to take it out of low power shutdown mode.

10.3.3 BOOST5 - STARTUP AND SOFT START

There is a direct path from VIN through the external inductor (L) into the BOOST5_SWn pins, through SR1 to the
BOOST5_OUT pin which directly charges the output capacitor (C OUT) to ~VIN. During startup the converter continues
charging to the programmed Output Voltage using Soft Start. During the Soft Start sequence the BOOST5 limits the peak
inductor current for the first 500 µs.
The Voltage value in the Output Voltage Register may be changed during the Soft Start sequence.
10.3.4 BOOST5 - PEAK CURRENT LIMITING

During normal operation the BOOST5 converter provides Cycle by Cycle current limiting. If the output voltage drops
below VIN then current limiting is no longer possible (See Section 10.3.3).
10.4 OUTPUT DIODE
Use a schottky diode such as an MSS1P5-E3/89A or equivalent if the converter output voltage is 4.5V or greater. The
schottky diode carries the output current for the time it takes for the synchronous rectifier to turn on. Do not use ordinary
rectifier diodes, since the slow recovery times will compromise efficiency. A schottky diode is optional for output voltages
below 4.5V.
10.5 BOOST5 - APPLICATIONS INFORMATION
 VIN (3.0 to 4.5V) typically comes from VSYS
 The approximation output current capability versus VIN value is given in the equation below.
IOUT = η x [ILOUT-PEAK – VIN x D / ( 2 x L x f ) ] x ( 1 - D )
Where:
η = estimated efficiency
ILOUT-PEAK = peak current limit value (1.5A)
VIN = Input voltage
D = steady-state duty ratio = (VOUT - VIN )/ VOUT
f = switching frequency (1.0MHz typical)
L = inductance value (2.2uH)
 BOOST5 provides 4.05 to 5.0V to the CLASS_D Audio Power Bridge and (optionally) LDOs requiring 5V input.
VIN = 3.0 to 4.5V
CONTROL &
MONITORING
5V CLASS_D AUDIO
POWER BRIDGE
BOOST5
LDOs
(OPTIONAL)
Figure 26 – BOOST5 Applications Diagram
 This block DOES NOT PROVIDE full short circuit protection. When the output voltage drops below the input voltage
there is a direct path through the inductor and internal synchronous rectifier (SR1) directly to the output capacitor.
The BOOST5 power supply block is designed to provide power to the CLASS_D Audio Amplifier and LDOs requiring
input voltage greater than the system voltage. External devices powered by this IP block are expected to provide
their own short circuit protection.
 Recommended External Components
ID Description Part No Manufacturer
CIN Capacitor, Ceramic, 22 µF 6.3V, X5R C0603X5R6R3-226MNE Venkel
COUT Capacitor, Ceramic, 22 µF, 6.3V, X5R C0603X5R6R3-226KNP Venkel
L Inductor, 2.2 µH, 2.6A CDRH3D23HPNP-2R2P SUMIDA
D1 Diode, Schottky, 50V, 1 A MSS1P5-E3/89A Vishay/General Semiconductor

11.0 CLASS_D BTL POWER OUTPUT STAGE

The CLASS_D BTL Output is intended to be the Power
 Single Supply, (+3.0 to 5.0V) Stage for the CLASS_D audio amplifier. It contains a
 Controllable by host & registers logic interface and two half-bridges that consist of
complementary FET output transistors with integrated
 Short circuit protection gate drivers. It has programmable short circuit protection.
When driven by the P95020‟s CLASS_D Digital Logic, it is
capable of meeting standard EMI requirements when
operating in “filterless” (no L-C output filter) configuration.
11.1 CLASS_D - ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, PVDD = 5V, TA = -40°C to +85°C, RL=8
Po Output Power PVDD = 5V, RL = 4Ω, THD+N = 10%) 2.5 W
(4Ω, 5V, 2W)
AMP Amplifier Efficiency  PVDD = 5V, RL = 4Ω, 2W
82 %
4Ω, 5V, 1W
PVDD driven by external 0.4 %
5V supply
THD+N Total harmonic distortion + Noise 8Ω, 5V, 1W
PVDD driven by external 0.2 %
5V supply
FPWM_AUDIO PWM frequency Note 1, Note 2 352.8 kHz
VNOISE Output voltage noise (4Ω, 5V) 90 µV
IIDLE Idle current (Mute, no load) 1 uA
PVDD Input voltage 3.0 5.0 V
ISC Short circuit protection current limit 2.0 A
IQ-PVDD PVDD supply current (Power-Down) Sum of currents 1 µA
IQNL PVDD supply current Switching, No Load 6.0 mA
fPWM PWM frequency Note 1, Note 2 352.8 kHz
tr Rise time Resistive load 1 2 5 ns
tf Fall time Resistive load 1 2 5 ns
IQ PVDD quiescent current Mute, No load 3.6 mA
Notes:
2. Clock will be coming from external crystal through PLL. Resultant frequency will be within 1% range from the
nominal.

11.2 CLASS_D – TYPICAL PERFORMANCE CHARACTERISTICS
ClassD Efficiency into 4 Ohm

"ClassD Efficiency"
90
85
80
75
Efficiency (%)
70
65
60
55
50
45
40
0.0 0.5 1.0 1.5 2.0 2.5
Output Power (W)
Figure 27 – Clss D BTL Efficiency vs Outpout Power (4 ohm speaker)
11.3 CLASS_D – REGISTER SETTINGS

Register pair (0x8A, 0x8C) and register pair (0x8B, 0x8D) control and monitor the CLASS_D BTL Power Output Stage.
Each half-bridge can be programmed by writing 8-bit control words to these registers.
Both Registers in each pair must be programmed identically. The Base addresses are defined in Table 3 – Register
Address Global Mapping on page 20. The offset addresses are defined as Base Address in the following table.
11.3.1 CLASS_D - Control Registers:

This Register pair contains Enable, Short Circuit Threshold and Dead-Time settings. They must be set identically.
Def. User
Set. Type
[3:2] SCTHR_CLASS_D 01b RW (See Table 27) Short Circuit Threshold
1 = Enable
7 ENABLE_CLASS_D 0b RW Master Enable
0 = Disable
Table 27 – Peak Short Circuit Detect Level Settings for Bits [3:2]
0 0 Short Circuit Threshold = 10% of F/S Voltage
Note – Short Circuit detect threshold is set as a percentage of full scale output voltage.

11.3.2 CLASS_D - Operation Registers:

This Register pair contains Short Circuit Disable and Fault settings. They must be set identically.
Def. User
Set. Type
1 = Fault
4 FAULT_CLASS_D 0b R Short Circuit Detected
0 = No Fault
1 = Disable SC Protect
6 SC_DISABLE_CLASS_D 0b RW Disable Short Circuit Protection
0 = Normal SC Protect
11.3.3 CLASS_D - Reserved Registers:

These registers are reserved and should not be written to.
11.4 CLASS_D - AUDIO INTERFACE AND DECODE

The audio functions of the CLASS_D BTL Power Output are controlled with internal logic level timing signals from the
Audio Module. (See Sections 2.12 in the AUDIO MODULE)
11.5 CLASS_D - SHORT CIRCUIT PROTECTION CIRCUITRY
The CLASS_D BTL Power Output includes protection circuitry for over-current conditions. Setting the SC_DISABLE to
HIGH will disable Short Circuit protection.
When SC_DISABLE is set to LOW and a short circuit occurs, all output FETS will be latched into a disabled mode (all
output FETS off). The short circuit latch is autonomously reset by the AUDIO Module.
11.6 CLASS_D - APPLICATIONS INFORMATION
11.6.1 CLASS_D - Recommended External Components
ID Qty Description
CIN1 1 Capacitor Ceramic 1.0 µF 10V 10% X7R 0805
CIN2 1 Capacitor 330 µF6.3V Elect FK SMD
CSNUB 1 Capacitor, Ceramic, 220 pF, 10%, X7R, 0402
RSNUB 1 Resistor, 5.1 Ohm, ¼ Watt

12.0 TSC MODULE - ADC AND TOUCH SCREEN CONTROLLER

The P95020 includes a Touch Screen Controller and a General Purpose ADC. These functions make use of external I/O
that can also be used as General Purpose I/O (GPIO) when the Touch Screen Controller and General Purpose ADC are
not in use. This section will describe the operation of the Touch Screen Controller.
 ADC – Analog to Digital Converter The P95020 includes an ADC subsystem which operates
 12-bit 62.5 ksps successive approximation ADC in two modes: Touch Screen Mode and General Purpose
measures 8 channels ADC Mode. In Touch Screen Mode there are four input
 User-programmable conversion parameters pins reserved for the 4-wire resistive touch screen outputs
 Auto shut-down between conversions and a pen-down status signal is available to notify the host
processor. In General Purpose ADC Mode, the pins used
 TSC – Touch Screen Controller to connect the touchscreen in Touchscreen Mode are
 4-wire simple touch screen controller used as general purpose analog signal inputs.
 Screen touch detection and interrupt generation
 Automatic (master) mode for touch location
measurement
VDD
2.5V
BUF
REF
ADC0/X+ CH1
ADC1/X- CH2
ADC2/Y+ CH3
X- Y- GND X+ Y+ Vref
ADC3/Y- CH4
Dual 3 to 1 MUX
REF- REF+
VBAT 1MHz ADC_CLK
R2 12-bit SAR ADC DIV/2 CKGEN
R1
MUX
VTEMP FSM logic control
VSYS
ICHRG
ADC Data
Control /status
registers
Result
registers
Pen interrupt and

PENDOWN
wake-up on touch
INT
Figure 28 – ADC & Touchscreen Controller Block Diagram

12.1 ADC AND TOUCH SCREEN CONTROLLER ELECTRICAL CHARACTERISTICS


VDD Input Voltage 3 5.5 V
IDD_TSC Touch Screen Controller Excluding Sensor Current 3 mA
Supply Current
RES ADC Resolution 12 bits
DNL ADC differential non- -1 1 LSB
linearity
INL ADC integral non -2 2 LSB
linearity
Refvol Internal Reference Note 1 2.475 2.5 2.525 V
Voltage Level Accuracy
Refacc Internal Reference 2 %
Voltage Accuracy
Rsw Sensor Driver Switch 20 
resistance
RBAT VBAT Battery Input Divider End to End Resistance 67.6 
Resistance
BATR Battery Resistive Divider R1/(R1+R2) 0.5925
Ratio
EBATR Battery Resistive Divider 1 %
Error
Notes:
1. May be subject to the constraints of power supply voltage and battery volt
12.2 ADC AND TOUCH SCREEN CONTROLLER PIN DEFINITIONS
ADC1 : X- pin to 4-wire resisitive touch-screen
002 ADC1 / GPIO6 / Analog general purpose auxiliary input channel 2
ADC3 : Y- pin to 4-wire resisitive touch-screen
ADC2 : Y+ pin to 4-wire resisitive touch-screen
ADC0 : X+ pin to 4-wire resisitive touch-screen
/ Analog general purpose auxiliary input channel 1
005 ADC0 / GPIO9 /MCLK_IN
MCLK_IN : Master Clock Input
117 ADCGND / GND_BAT ADCGND & GND_BAT: Shared analog ground pin for ADC and battery charger.
12.3 ADC AND TOUCH SCREEN CONTROLLER OPERATION

The ADC and TSC module comprises of the following functions:
 4-wire touch screen controller
 General purpose analog signal measurement
 On-die temperature and voltage monitoring, including low voltage and high temperature detectors
ADC_TSC_EN and clock generator PLL (0xA034[2:0] default value is 00b, PLL off) need to be enabled if any of the above
mentioned function needs to work. Since the ADC and Reference voltage is powered on only when a measurement is
scheduled, the power consumption will be low if there is no frequent measurements been configured.
The A/D converter is limited to 12-bit resolution, the conversion clock run at 1MHz and conversion takes 12 clock cycles.
The 1MHz clock will be coming from external cystal through PLL.
12.3.1 TOUCH SCREEN MODE

In this mode, pin GPIO6/7/8/9 are supposed to connected to the pin X-/Y-/Y+/X+ of a 4 wire resistive touch screen. The
pen-down detection circuit will be active automatically. When the screen is touched, the pen-down detect it and aserted
PENDOWN signal (mapped to GPIO1) to notify the processor. PENDOWN event could also (if programmed) trigger the
processor interrupt via the interrupt signal (mapped to GPIO5) of the chip. The touch screen controller operates in master
measurement mode. When touched, the controller will automatically initiate the X, Y (and Z1, Z2 if configured)
measurement when the pen-down status is detected. After the convertion is done the result is stored into result registers
and pen-down detection circuit will be back to work. Measurement will restart automatically as long as the pen-down

status is still valid. The PENDOWN (GPIO1) pin will be asserted whenever there is a valid measurement result stored in
the X/Y/Z1/Z2 register. It will be kept asserted until pendown status is not valid.
In the touch screen mode, the other internal monitoring channels (BAT, TEMP,VSYS and ICHRG) are still active for
measurement when the panel is not touched.
PEN-DOWN DETECTION
The pen-down detection circuit is only active in touch screen mode and is automatic (H/W autonomous). The detection
circuit is deactivated during measurements and reactivated after each measurement is completed to continue monitoring
the pen-down status. When touch screen detection is enabled, the Y- driver is ON and connected to GND and the X+ pin
is internally pulled to VDD through a 50KΩ resister. When the touch screen is touched, the X+ pin is pulled to GND
through the touch screen and PENDOWN goes high. The system will wait the amount of time defined by
PENDOWN_TIMER in the TSC Configuration Register to determine if the pen-down event is valid. If the pen-down event
is valid, an X/Y/Z1/Z2 measurement will begin.
VDD
OPEN CIRCUIT 50Kohm

Y+
PENDOWN
TOUCH
SCREEN X+
Y-
ON
Control
logic
PEN DETECT
ENABLE
PEN-DOWN DETECTION Function Block Diagram.
TSC – MEASURING TOUCH SCREEN LOCATION (X/Y)

When a PENDOWN valid event occurs the touch screen controller will automatically initiate an X/Y location measurement.
AVERAGE_SEL_TSC
Each measurement can be configured to be done 2 times (as defined in the Average Timer Select Register)
and then averaged. The results of the averaged conversions will then be stored into the Result Registers provided the
PENDOWN status remains valid througout a user-defined time (PENUP_TIMER). X/Y measurements will continue to be
made as long as the PENDOWN status remains valid. Each successive X/Y result will overwrite the previous location
written to the X Measurement and Y Measurement Result Registers.
VDD VDD
X+ Y+
REF+ REF+
R-touch
ADC ADC
Y- Y+ X- X+
REF- REF-
X- Y-
GND GND
Measure X-Position Measure Y-Position

TSC – MEASURING TOUCH SCREEN PRESSURE (Z1/Z2)

The user can configure whether pressure measurements will be taken by writing to the Pressure Measure Control bits in
the TSC Configuration Register. When measuring touch screen pressure, two parameters (Z1 and Z2) are measured
automatically. Along with the X/Y measurement, these values can be used to calculate the touch-resistance (RTOUCH) with
a formula such as:
X  Z2 
RTOUCH  R X  PLATE    1
4096  Z1 
Where RX-PLATE is the X-plate panel resistance.
VDD
VDD
Y+ Y+
REF+ REF+
R-touch
R-touch
ADC ADC
X- X+ X- X+
REF- REF-
Y- Y-
GND GND
Measure Z1-Position Measure Z2-Position
12.3.2 GENERAL PURPOSE ADC MODE

In this mode, GPIO6/7/8/9 are analog general purpose auxiliary signal inputs ADC1/ADC3/ADC2/ADC0. There are also
other four internal signals connect to ADC input multiplexer: BAT, TEMP, VSYS and ICHRG. Those signals are for battery
voltage, die temperature, system voltage and charging current measurement.
ADC AUTO POWER DOWN MODE

In this mode, the ADC and internal reference is usually off. When a measurement is either scheduled by internal timer or
external request, the device powers up the ADC and internal reference, and waits for the internal reference to settle. Then
the signal acquisition starts. The ADC and the reference will be powered down after all the outstanding
scheduled/requested tasks are finished. All the measurement channels will be served in a round robin manner.
ADC ALWAYS ON MODE

In this mode, the ADC is always powered up and the internal ADC reference is always on. The internal reference remains
fully powered after completing a sequence. All the measurement channels will be served in a round robin manner.
12.3.3 SYSTEM MONITORING AND ALERT GENERATION

There are four internal channels support scheduled measurement and monitoring:
 Battery voltage (VBAT) measurement
 Die Temperature (VTEMP) measurement
 Vsys Level (VSYS) measurement
 Battery charging current (CHRG_ICHRG) measurement
Among those, three of them are with alert signal generation:
 Battery voltage
 Die temperature
 Vsys level
Measured results are saved in dedicated result registers and compared with pre-defined spec limits. If it is out of the limit,
an alert (map to processor interrupt) signal can be asserted and alert status will be set.

12.4 ADC AND TOUCH SCREEN CONTROLLER REGISTERS

12.4.1 PCON Register – ADC_TSC ENABLE REGISTER
Def. User
Set. Type
Enable ADC or Touch screen controller. When disabled, the
0 = Disabled
0 ADC_TSC_EN 0b RW ADC_TSC module retains the configuration register settings but the
1 = Enabled
clock is gated (low power mode).
12.4.2 REAL TIME MEASUREMENT STATUS REGISTER

I²C Address = Page-0: 192(0xC0), µC Address = 0xA0C0
Def. User
Set. Type
0 = No Alert Pendown status in touch screen mode. Alert will be asserted when
0 PENDOWN 0b R
1= Alert Exists pendown detected. Deassert when pendown is not detected.
0 = No Alert
1 THI_ALERT 0b R Temperature higher than specified status
1= Alert Exists
0 = No Alert
2 TLO_ALERT 0b R Tempreature lower than specified status
1= Alert Exists
0 = No Alert
3 BHI_ALERT 0b R Battery voltage higher than specified status
1= Alert Exists
0 = No Alert
4 BLO_ALERT 0b R Battery voltage lower than specified status
1= Alert Exists
0 = No Alert
5 VSYSHI_ALERT 0b R VSYS higher than specified status
1= Alert Exists
0 = No Alert
6 VSYSLO_ALERT 0b R VSYS lower than specified status
1= Alert Exists
0 = No Alert
7 BLO_EXT_ALERT 0b R Battery voltage extremely low status
1= Alert Exists
12.4.3 X MEASUREMENT / AUXILIARY CHANNEL 1 RESULT REGISTER

Def. User
Set. Type
[11:0] RESULTS_CH1 000h R X position voltage in TSC mode / Channel 1 voltage in ADC mode
[15:12] RESERVED R RESERVED
12.4.4 Y MEASUREMENT / AUXILIARY CHANNEL 2 RESULT REGISTER

Def. User
Set. Type
[11:0] RESULTS_CH2 000h R Y position voltage in TSC mode / Channel 2 voltage in ADC mode
12.4.5 Z1 MEASUREMENT/ AUXILIARY CHANNEL 3 RESULT REGISTER

Def. User
Set. Type
[11:0] RESULTS_CH3 000h R Channel-3 voltage (ADC mode) or Z1 (TSC mode)
12.4.6 Z2 MEASUREMENT / AUXILIARY CHANNEL 4 RESULT REGISTER

Def. User
Set. Type
[11:0] RESULTS_CH4 000h R Channel-4 voltage (ADC mode) or Z2 (TSC mode)

12.4.7 VBAT MEASUREMENT RESULT REGISTER

I²C Address = Page-0: 202(0xCA), µC Address = 0xA0CA
Def. User
Set. Type
[11:0] RESULTS_VBAT 000h R Battery converted voltage
RESULTS_VBAT
VBAT = 4.2
4096
12.4.8 VTEMP MEASUREMENT RESULT REGISTER

I²C Address = Page-0: 203(0xCB), µC Address = 0xA0CB
I²C Address = Page-0: 204(0xCC), µC Address = 0xA0CC
Def. User
Set. Type
[11:0] RESULTS_VTEMP 000h R Temperature converted voltage
TEMP = RESULTS_VTEMP 0.114822 – 278.2565
12.4.9 VSYS MEASUREMENT RESULT REGISTER

I²C Address = Page-0: 205(0xCD), µC Address = 0xA0CD
I²C Address = Page-0: 206(0xCE), µC Address = 0xA0CE
Def. User
Set. Type
[11:0] RESULTS_VSYS 000h R VSYS measurement result
RESULTS_VSYS
VSYS = 5.0
4096
12.4.10 CHRG_ICHRG RESULT REGISTER

I²C Address = Page-0: 207(0xCF), µC Address = 0xA0CF
Def. User
Set. Type
[11:0] RESULTS_CHRG 000h R CHRG_ICHRG measurement result
RESULTS_CHRG hPROG
ICHRG = 2.5
RCHRG_ICHRG
hPROG : Ratio of IBAT to ICHRG pin current
12.4.11 ADC CONFIGURATION REGISTER

Def. User
Set. Type
0: General Purpose ADC Mode
0 SYSMODE 0b R/W System mode select
1: Touch Screen Mode
0: ADC Auto Power Down
2 POWERMODE 0b R/W Power mode select
1: ADC Always On

12.4.12 MEASUREMENT STATUS INTERRUPT ENABLE REGISTER

Def. User
Set. Type
0 = Disabled
0 PENDOWNEN 0b R/W Pendown status interrupt enable
1= Enabled
0 = Disabled
1 THI_ALERTEN 0b R/W Temperature higher than specified status interrupt enable
1= Enabled
0 = Disabled
2 TLO_ALERTEN 0b R/W Temperature lower than specified status interrupt enable
1= Enabled
0 = Disabled
3 BHI_ALERTEN 0b R/W Battery voltage higher than specified status interrupt enable
1= Enabled
0 = Disabled
4 BLO_ALERTEN 0b R/W Battery voltage lower than specified status interrupt enable
1= Enabled
0 = Disabled
5 VSYSHI_ALERTEN 0b R/W VSYS higher than specified status interrupt enable
1= Enabled
0 = Disabled
6 VSYSLO_ALERTEN 0b R/W VSYS lower than specified status interrupt enable
1= Enabled
0 = Disabled
7 BLO_EXT_ALERTEN 0b R/W Battery voltage extremely low status interrupt enable
1= Enabled
12.4.13 CHANNEL 1 AUTOMATIC MEASUREMENT ENABLE REGISTER

Def. User
Set. Type
0 = Disabled
0 CH1AUTOEN 0b R/W Enable automatic measurement
1= Enabled
[7:4] CH1P 0h R/W 0000 = 0, 0001 = 1, etc. Automatic measurement will occur every 2CH1P miliseconds

Def. User
Set. Type
0 = Disabled
1= Enabled

Def. User
Set. Type
0 = Disabled
1= Enabled

Def. User
Set. Type
0 = Disabled
1= Enabled

12.4.17 VSYS AUTOMATIC MEASUREMENT ENABLE REGISTER

Def. User
Set. Type
0 = Disabled
0 VSYSAUTOEN 0b R/W Enable automatic measurement
1= Enabled
[7:4] VSYSP 0h R/W 0000 = 0, 0001 = 1, etc. Automatic measurement will occur every 2VSYSP miliseconds
12.4.18 CHRG_ICHRG AUTOMATIC MEASUREMENT ENABLE REGISTER

Def. User
Set. Type
0 = Disabled
0 CHRGIAUTOEN 0b R/W Enable automatic measurement
1= Enabled
[7:4] CHRGIP 0h R/W 0000 = 0, 0001 = 1, etc. Automatic measurement will occur every 2CHGP miliseconds
12.4.19 TEMPERATURE AUTOMATIC MEASUREMENT ENABLE REGISTER

Def. User
Set. Type
0 = Disabled
0 TAUTOEN 0b R/W Enable automatic measurement
1= Enabled
[7:4] TP 0h R/W 0000 = 0, 0001 = 1, etc. Automatic measurement will occur every 2TP miliseconds
12.4.20 BATTERY AUTOMATIC MEASUREMENT ENABLE REGISTER

I²C Address = Page-0: 218(0xDA), µC Address = 0xA0DA
Def. User
Set. Type
0 = Disabled
0 BAUTOEN 0b R/W Enable automatic measurement
1= Enabled
[7:4] BP 0h R/W 0000 = 0, 0001 = 1, etc. Automatic measurement will occur every 2BP miliseconds
12.4.21 VSYS RANGE HIGH SPEC REGISTER

I²C Address = Page-0: 219(0xDB), µC Address = 0xA0DB
I²C Address = Page-0: 220(0xDC), µC Address = 0xA0DC
Def. User
Set. Type
[11:0] VSYSHI FFFh R/W High voltage specification for VSYS signal monitoring
12.4.22 VSYS RANGE LOW SPEC REGISTER

I²C Address = Page-0: 221(0xDD), µC Address = 0xA0DD
I²C Address = Page-0: 222(0xDE), µC Address = 0xA0DE
Def. User
Set. Type
[11:0] VSYSLO 000h R/W Low voltage specification for VSYS signal monitoring
12.4.23 BATTERY RANGE HIGH SPEC REGISTER

I²C Address = Page-0: 223(0xDF), µC Address = 0xA0DF
I²C Address = Page-0: 224(0xE0), µC Address = 0xA0E0
Def. User
Set. Type
[11:0] BATHI FFFh R/W High specification for battery voltage monitoring

12.4.24 BATTERY RANGE LOW SPEC REGISTER

Def. User
Set. Type
[11:0] BATLO 000h R/W Low specification for battery voltage monitoring
12.4.25 TEMPERATURE HIGH SPEC REGISTER

Def. User
Set. Type
[11:0] TEMPHI FFFh R/W High specification for temperature monitoring
12.4.26 TEMPERATURE LOW SPEC REGISTER

Def. User
Set. Type
[11:0] TEMPLO 000h R/W Low specification for temperature monitoring
12.4.27 TEMPERATURE EXTREMELY HIGH STATUS AND CONTROL REGISTER

Def. User
Set. Type
0 = Temperature lower than 155°C
0 TEMP_EXT_HI 0b R Die Temperature higher than 155°C
1 = Temperature higher than 155°C
0 = Disable
4 TEMP_EXT_HI_ALERTEN 0b R/W Temperature extremely high interrupt enable
1 = Enable
12.4.28 TEMPERATURE SENSOR CONFIGURATION REGISTER

Def. User
Set. Type
Power up or down detector for battery lower than 3.0V
0 = Power up detector
1 PD_SH_SENSOR 0b R/W or temperature higher than 155°C. The power of the
1 = Power down detector
detector is ~30uA.
12.4.29 AVERAGE TIMER SELECT REGISTER

I²C Address = Page-0: 234(0xEA), µC Address = 0xA0EA
Def. User
Set. Type
000 = No average
001 = Average 2 values
010 = Average 4 values Average count select for internal system monitoring
[2:0] AVERAGE_SEL_SYS 000b R/W
011 = Average 8 values channels.
Others = Reserved
000 = No average
[5:3] AVERAGE_SEL_TSC 000b R/W Average count select for channels 1/2/3/4.
Others = Reserved

12.4.30 TSC CONFIGURATION REGISTER

I²C Address = Page-0: 235(0xEB), µC Address = 0xA0EB
Def. User
Set. Type
00 = 128 µs
01 = 1.02 ms
[1:0] PENDOWN_TIMER 00b R/W Pen-down debounce timer
10 = 8.19 ms
11 = 32.77 ms
00 = 128 µs
01 = 512 µs
[3:2] PENUP_TIMER 00b R/W Pen-up update safety timer
10 = 2.05 ms
11 = 8.19 ms
00 = No pressure measure
PRESSURE_MEASURE_ 01 = Measure Z1 only
[5:4] 00b R/W Pressure measure control
CTRL 10 = Reserved
11 = Measure Z1 and Z2
00 = 12 µs
01 = 24 µs Timer period from channel select to sample
[7:6] SEL_DELAY_TIMER 00b R/W
10 = 48 µs acquisition. Channel 1/2/3/4 only.
11 = 96 µs
12.4.31 MEASUREMENT INTERRUPT PENDING STATUS REGISTER

I²C Address = Page-0: 236(0xEC), µC Address = 0xA0EC
Def. User
Set. Type
Pen-down in TSC mode status. Allert will be aserted
0 = No alert pending
0 PENDOWN_PENDING 0b RW1C whenever ther is a valid measurement result stored in
1 = Alert pending
the X/Y/Z1/Z2 register, write 1 to clear alert.
1 THI_ALERT_PENDING 0b RW1C Temperature higher than spec. status
1 = Alert pending
2 TLO_ALERT_PENDING 0b RW1C Temperature lower than spec. status
1 = Alert pending
3 BHI_ALERT_PENDING 0b RW1C Battery voltage higher than spec. status
1 = Alert pending
4 BLO_ALERT_PENDING 0b RW1C Battery voltage lower than spec. status
1 = Alert pending
5 VSYSHI_ALERT_PENDING 0b RW1C VSYS higher than spec. status
1 = Alert pending
6 VSYSLO_ALERT_PENDING 0b RW1C VSYS lower than spec. status
1 = Alert pending
7 BLO_EXT_ALERT_PENDING 0b RW1C Battery votlage extremely low status
1 = Alert pending
12.4.32 TEMPERATURE EXTREMELY HIGH INTERRUPT PENDING STATUS REGISTER

I²C Address = Page-0: 237(0xED), µC Address = 0xA0ED
Def. User
Set. Type
0 TEMP_EXT_HI_PENDING 0b RW1C Die temperature higher than 155°C status
1 = Alert pending
12.4.33 VSYS RANGE MARGIN REGISTER

I²C Address = Page-0: 238(0xEE), µC Address = 0xA0EE
Def. User
Set. Type
[3:0] VSYS_MARGIN 0h RW Margin for VSYS signal monitoring
12.4.34 BATTERY RANGE MARGIN REGISTER

I²C Address = Page-0: 239(0xEF), µC Address = 0xA0EF
Def. User
Set. Type
[3:0] BAT_MARGIN 0h RW Margin for battery signal monitoring

12.4.35 TEMPERATURE RANGE MARGIN REGISTER

I²C Address = Page-0: 240(0xF0), µC Address = 0xA0F0
Def. User
Set. Type
[3:0] TEMP_MARGIN 0h RW Margin for temperature signal monitoring
12.4.36 MARGIN REGISTER GENERAL DESCRIPTION

All margin registers are used to implement a hysteresis for alert/interrupt signal generation:
For xxx_HI_int, only when

Result > threshold + margin
Status will be asserted. When
Result <= threshold - margin
Status will be de-asserted.
For xxx_Lo_int, only when

Result < threshold – margin
Status will assert. When
Result >= threshold + margin
Status will be de-asserted.
Threshold bit
11 10 9 8 7 6 5 4 3 2 1 0
map
Margin bit
+/- 0 0 0 0 0 0 0 0
map
The 4 bits of margin registers are mapped to threshold as figure above. If sum (+/-) operation result is larger than 0xfff or
smaller than 0, then 0xfff or 0 will be used as the real threshold setting.
12.4.37 Equation
12.4.38 ADC - RESERVED Registers

I²C Address = Page-0: 236(0xF1), µC Address = 0xA0F1
Thru = Page-0: 255(0xFF), µC Address = 0xA0FF

13.0 PCON MODULE – POWER CONTROLLER AND GENERAL PURPOSE I/O

PCON Module is the power controller of the device. It also manages the registers associated with GPIO and CKGEN.
13.1 GPIO PIN DEFINITIONS
13.1
117 GND_BAT/ADCGND GND_BAT & ADCGND: Shared analog ground pin for battery charger and ADC
118 DGND Digital Ground
119 POR_OUT Power-On Reset Output, Open-drain Output, Active Low
120 SW_DET Switch Detect Input
121 GPIO1 / SW_OUT / PENDOWN SW_OUT: Switch Detect Output
PENDOWN: Pen down
122 GPIO2 / LED1
LED1: Charger LED # 1 Indicates charging in progress
123 GPIO3 / LED2
LED2: Charger LED # 2 Indicates charging complete
124 GPIO4 / CHRG_ILIM
CHRG_ILIM
001 GPIO5 / INT_OUT
INT_OUT : Interrupt Output
002 GPIO6 / ADC1
ADC1 : ADC Input Channel 1 (X-)
003 GPIO7 / ADC3
ADC3 : ADC Input Channel 3 (Y-)
004 GPIO8 / ADC2
ADC2 : ADC Input Channel 2 (Y+)
005 GPIO9 / ADC0 / MCLK_IN ADC0 : ADC Input Channel 0 (X+)
MCLK_IN : Master Clock Input
006 GPIO10
13.2 POWER STATES

P95020 device has two hardware power states.
OFF State:
P95020 enters OFF state after the first time battery insertion. The system power (VSYS ) is provided by the battery via the
ideal diode. VSYS powering up will issue a power-on-reset to reset all the logic on the device to default state and P95020
enters OFF state. In this state;
 32K crystal oscillator (or associate RC oscillator) is running and generates 32k/4k/1k clocks.
 The RTC module is enabled and the RTC registers are maintained.
 The always on LDO is enabled and provides power to system.
 The power switch detection (SW_DET) circuit is running.
 Ideal diode driver is running.
 All regulators, touch screen controller and audio are in power down or inactive mode.
 Wait for interrupts to wake up CPU and bring system to ON state.
ON State:
P95020 enters ON state after momentarily pressing and releasing a button attached to SW_DET or AC adaptor insertion.
The CKGEN (Clock generator module) power is enabled and the 8MHz I2C and processor clock is available.
13.3 POWER SEQUENCING BY EMBEDDED MICROCONTROLLER
Pending embedded uP interrupt will trigger the following actions;
Hardware actions:
 Set PSTATE_ON bit of POWER STATE AND SWITCH CONTROL REGISTER (0xA031) to 1, turn on the power
of CKGEN (VDD_CKGEN18, VDD_CKGEN33) and hence 8MHz (processor and I2C clock) clock is available.
 Turn on the power of Embedded Microcontroller (VDD_EMBUP18) and release processor reset automatically
after 4ms. Processor start to execute code stroed in the internal ROM or external ROM.
Firmware actions:
 Embedded microcontroller (6811) sub-system start with the boot sequence.

 The firmware (boot sequence) starts with checking whether the external ROM is available (read EX_ROM bit in
the global registers). If it exists, load the EX_ROM data into internal RAM. Other wise, execute code in the
internal ROM.
 Firmware execute the code according the context and interrupt to sequence the power.
 After the sequence is done, processor enter low power mode and wait for interrupts.
13.4 POWER ON RESET OUTPUT (POR_OUT)

The POR_OUT pin is an open drain GPIO output pin which controlled by firmware as part of the power up sequence. This
signal is used to reset the devices in the system that are powered by P95020 device while the power is not yet ready. The
output state of POR_OUT is defined by the power up sequence.
13.5 POWER SWITCH DETECTOR (SW_DET)
The PCON module also includes special power switch detection circuitry to provide a “push-on/push-off” interface via the
switch detect (SW_DET) pin. By connecting a button to this pin, three different events can be triggered. The first is a
short switch interrupt (>100ms) which is generated by momentarily pressing and releasing a button attached to SW_DET.
The second is a medium switch interrupt which is generated by pressing and holding the button and releasing it after 2
seconds (configurable to 2/3/4/5 seconds). The status of each of these switches can be monitored in the Switch Control
Register (0xA031). The third switch function is triggered when the button is pressed and held for longer than 15 seconds.
This event will not generate an interrupt but will generate system reset and force P95020 into OFF state.
13.6 GPIO GENERAL DESCRIPTION

The GPIO pins are turned on and off using the GPIO Off Register. This register is used like a multiplexer to allow the
GPIO and TSC/ADC subsystems to share external pins. When in GPIO mode (GPIO_OFF bits set to logic „0‟) the GPIO
Function Register configures the pin to operate as a GPIO or some other special function such as a status LED output. If
not configured to perform a special function, each GPIO can be configured as an input or output by setting the
corresponding bit in the GPIO Direction Register.
When configured as an output, each GPIO pin can be configured as a CMOS output or an open drain output by setting
the corresponding bit in the GPIO Output Mode Register. Each GPIO pin configured as an output will reflect the value
held in the GPIO Data Register with a logic „0‟ causing the pin to be low and a logic „1‟ causing the pin to be high.
Reading from the GPIO Data Register will return the last value written to it.
When configured as an input, each GPIO can be configured as level or edge sensitive by setting the corresponding bit in
the GPIO Input Mode Select Register. When set to level sensitive, the corresponding bit in the GPIO Data Register will
follow the logic level of the GPIO pin. When set to edge sensitive the corresponding bit in the GPIO Data Register will
change from a logic „0‟ to a logic „1‟ when the input transitions from low to high (rising edge) or high to low (falling edge) as
determined by the setting in the GPIO Input Edge Select Register. The value in the GPIO Data Register will remain a
logic „1‟ until a logic „0‟ is written into the register throuigh host or I2C interface. In level sensitive mode, writing to the
GPIO Data Register through host or I2C will have no effect.
When configured as an input, a GPIO may also generate an interrupt. Interrupts are always edge sensitive. The GPIO
Input Edge Select Register is used to select which edge, rising or falling, is used to generate an interrupt. When as edge
is detected, the GPIO Interrupt Status Register will show a logic „1‟ in the corresponding bit and an interrupt will be
generated provided the appropriate bit has been enabled by writing a logic „1‟ to the GPIO Interrupt Enable Register. The
GPIO Interrupt Status Register is cleared by writing a logic „1‟ to the appropriate bit. Writing a logic „0‟ will have no effect.
13.7 PCON REGISTERS
13.7.1 GPIO DIRECTION REGISTER
Def. User
Set. Type
0 = Input
[10:1] GPIO_DIR 0000000000b R/W Each bit sets the corresponding GPIO to either input or output
1 = Output
13.7.2 GPIO DATA REGISTER


Def. User
Set. Type
Pins configured as an output will reflect the value held in the
GPIO_DAT register. The GPIO_DAT register will follow the logic
level at the pin for pins configured as a level sentitive inputs. The
[10:1] GPIO_DAT 0000000000b R/W GPIO_DAT register will change from a 0 to a 1 when the input
transitions state from low to high (rising edge) or high to low
(falling edge) as determined by the GPIO INPUT EDGE SELECT
register for pins configured as level sensitive inputs.
13.7.3 GPIO INPUT MODE SELECT REGISTER

Def. User
Set. Type
0 = Level sensitive, GPIO_DAT reflects the input data for the
0 = Level
corresponding GPIO; 1 = Edge sensitive, rising/falling edges
sensitive
[10:1] GPIO_IN_MODE 0000000000b R/W trigger interrupts as defined in GPIO_IN_EDGE. Requires the
1 = Edge
associated bit in the GPIO Direction Register to be set as an
sensitive
input.
13.7.4 GPIO INTERRUPT ENABLE REGISTER

Def. User
Set. Type
0 = Interrupt
Disabled
[10:1] GPIO_INT_EN 0000000000b R/W Each bit enabled/disables the corresponding GPIO interrupt
1 = Interrupt
Enabled
13.7.5 GPIO INPUT EDGE REGISTER

Def. User
Set. Type
0 = Rising edge
trigger 0 = Rising edge generates interrupt. 1 = Rising edge and
[10:1] GPIO_IN_EDGE 1111111111b R/W
1 = Rising and falling edge generates interrupt.
falling edge trigger
13.7.6 GPIO INTERRUPT STATUS REGISTER

Def. User
Set. Type
0 = No interrupt
[10:1] GPIO_INT_STATUS 0000000000b RW1C Event is defined by GPIO_IN_EDGE register
1 = Interrupt
13.7.7 GPIO OUTPUT MODE REGISTER

Def. User
Set. Type
0 = CMOS output
[10:1] GPIO_OUT_MODE 1111111111b R/W Sets the output mode for each corresponding GPIO
1 = Open drain output

13.7.8 GPIO OFF REGISTER

Def. User
Set. Type
0 = GPIO on Each bit shuts off the corresponding GPIO allowing the external
[10:1] GPIO_OFF 1111100000b R/W
1 = GPIO off pin to be used for the TSC or ADC functions.
13.7.9 GPIO FUNCTION REGISTER

Def. User
Set. Type
Sets GPIO1 to operate as a normal GPIO or as a switch detect or
1 GPIO1_SWO_PD 1b R/W 1 = Switch detect output
PENDOWN detect
or PENDOWN
2 GPIO2_LED1 1b R/W 1 = GPIO2 will be charger Sets GPIO2 to operate as a normal GPIO or as charger LED1
LED1
3 GPIO3_LED2 1b R/W 1 = GPIO3 will be charger Sets GPIO3 to operate as a normal GPIO or as charger LED2
LED2
4 GPIO4_CHRG_ILIM 1b R/W 1 = GPIO4 will be Sets GPIO4 to operate as a normal GPIO or as CHRG_ILIM
CHRG_ILIM
Sets GPIO5 to operate as a normal GPIO or as an interrupt
5 GPIO5_INT_OUT 1b R/W 1 = GPIO will be interrupt
output
output
0 = GPIO1 is switch
Sets GPIO1 as switch detect or PENDOWN detect when
6 GPIO1_PENDOWN 0b R/W detect output
GPIO1_SWO_PD = 1
1 = GPIO1 is PENDOWN
0 = Active low
7 PENDOWN_POL 0b R/W Sets PENDOWN polarity
1 = Active high
13.7.10 POWER STATE AND SWITCH CONTROL REGISTER

Def. User
Set. Type
0 = Switch inactive
0 SW_DET_STATUS_0 0b RW1C Short switch detect
1 = Switch active
0 = Switch inactive
2 SW_DET_STATUS_2 0b RW1C Medium switch detect
1 = Switch active
When PSTATE _ON = 0 the clock generator is powered off and
0 = Off
4 PSTATE_ON 0b RW1C only the 32 kHz clock will be available. When PSTATE_ON = 1
1 = On
the clock generator is on.
13.7.11 GPIO SWITCH INTERRUPT ENABLE

Def. User
Set. Type
0 = Interrupt
disabled
0 SSW_INT_EN 1b R/W Short switch interrupt enable
1 = Interrupt
enabled
0 = Interrupt
disabled
2 MSW_INT_EN 1b R/W Medium switch interrupt enable
1 = Interrupt
enabled
0 = System reset
disabled
4 RST_OVER_TEMP 0b R/W Enable system reset at temperatuer above 155°C
1 = System reset
enabled

0 = System reset
disabled
5 RST_UNDER_VOL 0b R/W Enable system reset at low system voltage (VSYS < 3.0V)
1 = System reset
enabled
0 = System reset
disabled Enable system reset when DC2DC module detects UVLO
6 RST_DC2DC_UVLO 0b R/W
1 = System reset condition
enabled
13.7.12 DCDC INTERRUPT ENABLE

Def. User
Set. Type
0 = Interrupt
BUCK_500_0_FAULT_INT disabled
0 0b R/W BUCK_500_0 fault interrupt enable
_EN 1 = Interrupt
enabled
0 = Interrupt
BUCK_500_1_FAULT_INT disabled
1 0b R/W BUCK_500_1 fault interrupt enable
_EN 1 = Interrupt
enabled
0 = Interrupt
BUCK_1000_FAULT_INT_ disabled
2 0b R/W BUCK_1000 fault interrupt enable
EN 1 = Interrupt
enabled
0 = Interrupt
disabled
3 BST5_FAULT_INT_EN 0b R/W BOOST5 fault interrupt enable
1 = Interrupt
enabled
0 = Interrupt
disabled
4 BST40_FAULT_INT_EN 0b R/W BOOST40 fault interrupt enable
1 = Interrupt
enabled
0 = Interrupt
disabled
5 CLSD_FAULT_INT_EN 0b R/W CLASSD fault interrupt enable
1 = Interrupt
enabled
13.7.13 POWER ON RESET STATE CONTROL REGISTER

Def. User
Set. Type
0=0 POR_OUT pin state control. POR_OUT pin should be pulled
0 POR_OUT 0b R/W
1 = Hi-Z high by an external resistor
13.7.14 MID-BUTTON CONFIGURATION REGISTER

Def. User
Set. Type
00 = 2 sec.
01 = 3 sec.
[1:0] MID_BTN_CFG 00b R/W Mid-button push duration configuration.
10 = 4 sec.
11 = 5 sec.
13.7.15 OTHER PCON REGISTERS

I²C Address = Page-0: 52(0x34), µC Address = 0xA034 (See Section 4.7)
I²C Address = Page-0: 56(0x38), µC Address = 0xA038 (See Section 2.15.2)
I²C Address = Page-0: 39(0x39), µC Address = 0xA039 (See Section 12.4.1)
I²C Address = Page-0: 58(0x3A), µC Address = 0xA03A (See Section 6.2.1)
I²C Address = Page-0: 61(0x3D), µC Address = 0xA03D (See Section 4.7)

13.7.16 GPIO RESERVED REGISTERS

I²C Address = Page-0: 59(0x3B), µC Address = 0xA03B,
Thru Page-0: 63(0x3F), µC Address = 0xA03F

14.0 HOTSWAP MODULE

The HOTSWAP module is intended to provide an output
 Controlled via external pin or internal registers voltage that tracks the input voltage with minimal DC
losses (up to 150mA max.). The primary purpose for these
 Current Output 150mA maximum. outputs is to provide short circuit protection to peripheral
devices such as SD cards when connected to the host
 Overcurrent / Short Circuit Protection device. The input supply to the switches is shared though
each switch has an independent, active high, control
input.
VSYS
HSCTRL1
I2C
SUB-BLOCK
SW Ctrl HSO1
FORCE INTERNAL
SWITCH CTRL
HSPWR
REGISTER HS_CTRL_REG
BUS 0x36 [4:0]
SW Ctrl
HSO2
MICROCONTROLLER HSCTRL2
SUB-BLOCK
UPPER BYTE OFFSET: 0xA0
Figure 29 – Hotswap Block Diagram
14.1 HOT SWAP (LOAD SWITCHES) – ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, VHSPWR=4.5V, TA = -40°C to +85°C,

VHSPWR Input voltage Range Mosfet Inputs 3.0 3.3 5.5 V
VSYS =4.5V,HSPWR = 3.3V, IOUT=0
HS_CTRL_REG
IQ(SW-ON) Quiescent Current from HSPWR 24 uA
0x36 [3:0] = 1= ON
VSYS = 4.5V,HSPWR = 3.3V, HSCTRL1,

HSCTRL2 = GND
IQ(SW-OFF) Off-Supply Current from HSPWR 1 uA
HS_CTRL_REG
0x36 [3:0] = 0 = OFF
RDS(ON) On Resistance VHSPWR = 3.0V to 5.0V 1.2 1.6 
ILIM (MIN) Current Limit VHSPWR = 3.0V to 5.0V 180 250 mA
tRESP Current Limit Response Time 10 µs
HSCTRL1, HSCTRL2, Input Low 0.3 x
VIL VHSPWR = 3V to 4.5V V
Voltage VHSPWR
HSCTRL1, HSCTRL2, Input High 0.7 x VHSPWR
VIH VHSPWR = 3V to 4.5V V
Voltage VHSPWR + 0.3
IOSINK HSCTRL1, HSCTRL2 Leakage 1 uA
tOFF Turn-Off Time VHSPWR = 5V Note 1 1 µs
tON Turn-On Time VHSPWR = 5V Note 1 15 µs
Notes:
1. Guaraneteed by design and/or characterization.

14.2 HOTSWAP – TYPICAL PERFORMANCE CHARACTERISTICS
Hotswap #1 RDSON vs. Temperature
1.7
1.6
1.5
RDSON (ohm)
1.4
VSYS = 3.6V
VSYS = 4.5V
1.3
1.2
1.1
1
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
TEMPERATURE (C)
Figure 30 – Hotswap #1 ON Resistance vs Temperature
Hotswap #2 RDSON vs. Temperature
1.7
1.6
1.5
RDSON (ohm)
1.4
VSYS = 3.6V
VSYS = 4.5V
1.3
1.2
1.1
1
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
Tem perature (C)
Figure 31 – Hotswap #2 ON Resistance vs Temperature

14.3 HOTSWAP – PIN DEFINITIONS

097 HSCTRL1 Hot Swap Control Input 1
098 HSO1 Hot Swap Output 1
099 HSPWR Hot Swap Switches Power Input
100 HSO2 Hot Swap Output 2
101 HSCTRL2 Hot Swap Control Input 2
14.4 PCON REGISTER - HOTSWAP CONFIGURATION

Def. User
Set. Type
0 = SW2 OFF
0 FORCE_SW2_ON 0b RW Force SW2 On
1 = SW2 ON
0 = SW1 OFF
1 FORCE_SW1_ON 0b RW Force SW1 On
1 = SW1 ON
0 = NORMAL SW2
2 FORCE_SW2_EN 0b RW Force SW2 Enable
1 = FORCE SW2
0 = NORMAL SW1
3 FORCE_SW1_EN 0b RW Force SW1 Enable
1 = FORCE SW1
0 = HSCTRL1 (1 turns on the switch) Inverts Hotswap Control Pin Polarity
4 CTRL_INV 0b RW
1 = HSCRTL1 (0 turns on the switch)
Notes:
To enable HOTSWAP Switch 1, first program FORCE_SW1_ON to 1 then enable the switch by programming
FORCE_SW1_EN to 1 or by forcing the HSCTRL1 to high (for CTRL_INV = 0).

15.0 I2C_I2S MODULE

 I²C Master supports interface to external ROM The P95020‟s I²C master port is intended for I²C ROM
access only. The contents of an external ROM that are
 I²C Slave supports interface to external I²C Masters attached to the I²C Master port are automatically read into
an internal 1.5 kbyte shadow memory. The I²C Master
 400 kHz fast I2C protocol port conforms to the 400 kHz fast I²C bus protocol and
supports 7-bit device/page addressing.
 Two I²S interfaces The P95020‟s I²C Slave port follows I2C bus protocol
during register reads or writes that are initiated by an
 Access arbiter that arbitrates the access request from external I²C Master (typcially an application processor).
I2C slave or embedded microcontroller The I²C Slave port operates at up to 400 kHz and
supports 7-bit device/page addressing.
 Interrupt handler which merge or re-direct the interrupts
from functional module to internal or external processor The P95020 includes two I²S interfaces that provide audio
inputs to the Audio Module described in Section 2.0.
15.1 I2C_I2S - PIN DEFINITIONS
Pin # PIN_ID DESCRIPTION
054 EX_ROM ROM Select. EX_ROM = 1, read contents of external ROM into internal shadow memory. EX_ROM = 0, read contents
of internal ROM.
055 DGND Digital Ground (1)
056 I2S_BCLK2 I²S Bit Clock Channel 2
057 I2S_WS2 I²S Word Select Channel 2
058 I2S_SDOUT2 I²S Serial Data OUT Channel 2
059 I2S_SDIN2 I²S Serial Data IN Channel 2
060 I2S_BCLK1 I²S Bit Clock Channel 1
061 I2S_WS1 I²S Word Select (Left/Right) Channel 1
062 I2S_SDOUT1 I²S Serial Data OUT Channel 1
063 I2S_SDIN1 I²S Serial Data IN Channel 1
064 I2CS_SCL I²C Slave clock
065 I2CS_SDA I²C Slave data
066 I2CM_SCL I²C Master clock
067 I2CM_SDA I²C Master data
068 GND GND : Ground
15.2 I²C SLAVE

15.2.1 I²C Slave - Address and Timing Mode
The I²C ports on the P95020 operate at a maximum speed of 400 kHz. The I²C slave address that the P95020 responds
to is defined in the I2C_SLAVE_ADDR global register. The default I²C device address after reset is 0101010, and can be
changed by firmware during the start up sequence.
The I²C slave supports two interface timing modes: Non-Stretching and Stretching.
In Non-Stretching Mode, the I²C slave does not stretch the input clock signal. The registers are pre-fetched to speed up
the read access in order to meet the 400 kHz speed. This is the default mode of operation and is intended for use with
I²C masters that do not supporting clock stretching.
In Stretching Mode, the I²C slave may stretch the clock signal (hold I2CS_SCL low) during the ACK / NAK phase (byte
level stretching) when the internal read access request is not finished. Stretching is not supported during write accesses.
15.2.2 I²C Slave - Write/Read Operation

The configuration and status registers for the various functional blocks are mapped to 3 consecutive 256 byte pages. The
page ID is encoded to 0,1, and 2. The definition and mapping is defined in Table 3 – Register Address Global Mapping
on page 20. The first 16 bytes in any of the 3 pages map to the same set of global registers. The “current active page” ID
for I²C access is defined in the global page ID register.
The I²C uses an 8-bit register address (Reg_addr in below) to define the register access start address in an I²C access in
the current page. The register address can be programmed by writing the register value immediately after device
address. Subsequent write accesses will be directed to the register defined by the register address in the current active
page. Read accesses will return the register defined by the register address. The register address is incremented
automatically byte-per-byte during each read/write access.

S 0101010 W A Reg_addr A Data[reg_addr] A Data[reg_addr+1] A Data[…] A Data[reg_addr+n] A P
Data[reg_addr+n+ Data[reg_addr+n+ Data[reg_addr+n+

S 0101010 R A A Data[reg_addr] A Data[reg_addr]+1
Data[...] A N P
1] 2] m]
S 0101010 W A Reg_addr A Sr 0101010 R A Data[reg_addr] A Data[reg_addr]+1

Data[reg_addr+1] A Data[reg_addr+2] N P
S 0101010 R A Data[reg_addr+3] A Data[reg_addr+4]

Data[reg_addr] A Data[reg_addr]+1
Data[...] A Data[reg_addr+k] N P
Sr: Repeat
Legend: S: Start
Start
R:Read (1) W:Write (0) A:ACK N:NAK P:Stop
2
Figure 32 – I C Read / Write Operation
15.3 INTERRUPT DISPATCHER

The interrupt dispatcher of the P95020 directs interrupts to the internal or external processor according to the INT_DIR
configuration stored in the ACCM Register. Please note that the configuration register is in the same address space of
other functional modules and hence can be accessed by internal and external processor. Interrupts mapped to the
internal processor are merged and dispatched to embedded microcontroller. Interrupts mapped to the external processor
are merged and dispatched to the external pin (INT_OUT). To ease the interrupt indexing of the external processor, two
interrupt index registers (one for internal and the other for external) are defined to reflect the status of different types of
interrupt status bits. Please note that the index register is just reflects the interrupt status of the various modules and
there are no real registers implemented. Therefore, clearing a particular interrupt status must be performed in the module
which generated the interrupt.
15.4 ACCESS ARBITER
Access request from I²C slave and embedded processor will be arbitrated with strict high priority to I²C. The access is split
to byte-perbyte basis.
15.5 DIGITAL AUDIO DATA SERIAL INTERFACE
Audio data is transferred between the host processor and the P95020 via the digital audio data serial interface, or audio
bus. The audio bus on this device is flexible, including left or right justified data options, support for I²S protocols,
programmable data length options.
The audio bus of P95020 can be configured for left or right justified, I²S slave modes of operation. These modes are all
MSB-first, with data width programmable as 16, 20, 24 bits.
The world clock (I2S_WS1 or I2S_WS2) is used to define the beginning of a frame. The frequency of this clock
corresponds to the maximum of the selected ADC and DAC sampling frequency. The bit clock (I2S_BCLK1 or
I2S_BCLK2) is used to clock in and out the digital audio data across the serial bus. Each port may be programmed for 8
kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.050 kHz, 24 kHz, 44.1 kHz, 48 kHz, 88.2 kHz or 96 kHz sample rate.

15.6 I2C_I2S – INTERFACE TIMING
15.6.1 I2C Interface Timing
tSCL
tSCLHIGH tSCLLOW
IICSCL
tSTOPH tBLF tSDAS tSDAH
tSTARTS
IICSDA
Parameter Symbol Min. Typ. Max. Unit

Std. 100
SCL Clock Frequency tSCL - - kHz
Fast 400
Std. 4.0
SCL High Level Pulse Width tSCLHIGH - - µs
Fast 0.6
Std. 4.7
SCL Low Level Pulse Witdh tSCLLOW - - µs
Fast 1.3
Bus Free Time Between Std. 4.7
tBUF - - µs
STOP and START Fast 1.3
Std. 4.0
START Hold Time tSTARTS - - µs
Fast 0.6
Std. 0 3.45
SDA Hold Time tSDAH - µs
Fast 0 0.9
Std. 250
SDA setup time tSDAS - - ns
Fast 100
Std. 4.0
STOP Setup Time tSTOPH - - µs
Fast 0.6
Table 28 – I2C Interface Timing

15.6.2 I2S Interface Timing – I2S Slave Mode
Left Channel Right Channel

I2S_WS
10 11 11 17
16 16
I2S_BCLK
14 14 14 14
13 13 13 13
I2S_SDIN 23 22 1 0 8 dummy bits 23 22 1 0 8 dummy bits 23 22
15 15 15 15 15
I2S_SDOUT 23 22 1 0 8 dummy bits 23 22 1 0 8 dummy bits 23 22
Parameter Notation Symbol Min. Typ. Max. Unit

I2S_BCLK Cycle Time 10 tCYC 1/64 x Fs - - ns
I2S_BCLK Pulse Width High 11 tCH 0.45 x P - 0.55 x P ns
I2S_BCLK Pulse Width Low 11 tCL 0.45 x P - 0.55 x P ns
I2S_WS Set-up Time To I2S_BCLK 16
tWS 10 - - ns
High
I2S_WS Hold Time to I2S_BCLK High 17 tWH 10 - - ns
I2S_SDIN Set-up Time to I2S_BCLK 13
tDS 10 - - ns
High
I2S_SDIN Hold Time to I2S_BCLK 14
tDH 10 - - ns
High
I2S_SDOUT Delay Time from 15
tDD - - 10 ns
I2S_BCLK Falling Edge
Table 29 – I2S Interface Timing
Notes: Fs = 8 to 96 kHz, P = I2S_BCLK period

15.7 GLOBAL REGISTER SETTINGS (I²C-page 0)

Global Registers are used by the Access Manager, which includes an I²C Slave and Bus Arbiter. For easy access from
the I²C slave interface (by default 256 Bytes oriented) the first 16 registers of each page are global for all the pages
(Page 0 thru Page 3). The Base addresses are defined in Table 3 – Register Address Global Mapping on page 20.
15.7.1 Global Register – RESET_ID

I²C Address = Page-x: 00(0x00), µC Address = 0xA000
Def. User
Set. Type
[6:0] ID 1010101b R Chip ID
0 = Normal Master Reset. Write “1” to this register to trigger a system reset.
7 RESET 0b RW1A
1 = System Reset System reset will reset P95020 device into OFF state.
15.7.2 Global Register – PAGE_ID

Def. User
Set. Type
[1:0] PAGE 00b RW Page ID
15.7.3 Global Register – DCDC_FAULT

Def. User
Set. Type
0 = Normal
0 BUCK500_0_FAULT 0b R Fault in 500 mA Buck Converter #0
1 = Fault
0 = Normal
1 BUCK500_1_FAULT 0b R Fault in 500 mA Buck Converter # 1
1 = Fault
0 = Normal
2 BUCK1000_FAULT 0b R Fault in 1000 mA Buck Converter
1 = Fault
0 = Normal
3 BOOST5_FAULT 0b R Fault in BOOST5 Converter
1 = Fault
15.7.4 Global Register – LDO_FAULT

Def. User
Set. Type
0b 0 = Normal
0 LDO_050_0_FAULT R Fault in LDO_050_0
1 = Fault
0b 0 = Normal
1 = Fault
0b 0 = Normal
1 = Fault
0b 0 = Normal
1 = Fault
0b 0 = Normal
1 = Fault
0b 0 = Normal
1 = Fault
0b 0 = Normal
1 = Fault
0b 0 = Normal
7 LDO_LP_FAULT R Fault in LDO_LP
1 = Fault

15.7.5 Global Register – LDO_GLOBAL_EN

Def. User
Set. Type
0b RW 0 = Disabled
0 LDO_050_0_ENABLE Enable LDO_050_0
1 = Enabled
0b RW 0 = Disabled
1 = Enabled
0b RW 0 = Disabled
1 = Enabled
0b RW 0 = Disabled
1 = Enabled
0b RW 0 = Disabled
1 = Enabled
0b RW 0 = Disabled
1 = Enabled
0b RW 0 = Disabled
1 = Enabled
15.7.6 Global Register – DCDC_GLOBAL_EN

Def. User
Set. Type
0b RW 0 = Disabled
0 BUCK500_0_ENABLE Enable BUCK500_0 Converter
1 = Enabled
0b RW 0 = Disabled
1 BUCK500_1_ENABLE Enable BUCK500_1 Converter
1 = Enabled
0b RW 0 = Disabled
2 BUCK1000_ENABLE Enable BUCK1000 Converter
1 = Enabled
0b RW 0 = Disabled
3 BOOST5_ENABLE Enable BOOST5 Converter
1 = Enabled
0b RW 0 = Disabled
4 LED_BOOST_ENABLE Enable LED_BOOST Converter
1 = Enabled
0 = Disabled
7 CLASS_D_ENABLE 0b RW Enable Class D BTL Power Stage
1 = Enabled
15.7.7 Global Register – EXT_INT_STATUS INDEX

Def. User
Set. Type
External interrupt status index.
[31:0] EXT_INT_STATUS 00000000h R Please refer to below. Note that the actual interrupt status bit is implemented in the
individual functional modules.
15.7.8 Global Register – INT_INT_STATUS INDEX

I²C Address = Page-x: 10(0x0A), µC Address = 0xA00A
I²C Address = Page-x: 11(0x0B), µC Address = 0xA00B
I²C Address = Page-x: 12(0x0C), µC Address = 0xA00C
I²C Address = Page-x: 13(0x0D), µC Address = 0xA00D
Def. User
Set. Type
Internal interrupt status index.
[31:0] INT_INT_STATUS 00000000h R Please refer to below. Note that the actual interrupt status bit is implemented in the
individual functional modules.

The following table lists the bit mapping for interrupt direction control and internal / external processor interrupt status
index register.
Table 30 - Interrupt Source Mapping

Byte Bit
Mapping
ID Field
0 RESERVED
1 GPIO1 (Pin 121)
2 GPIO2 (Pin 122)
3 GPIO3 (Pin 123)
0
4 GPIO4 (Pin 124)
5 GPIO5 (Pin 001)
6 GPIO6 (Pin 002)
7 GPIO7 (Pin 003)
0 GPIO8 (Pin 004)
1 GPIO9 (Pin 005)
2 GPIO10 (Pin 006)
3 RESERVED
1 4 Short_SW
5 RESERVED
6 Mid_SW
“Both” flag, only meaningful for interrupt direction control.
7
If this bit is set, interrupts will be dispatched to both internal and external processors.
0 WatchDog (Time-out)
1 GPTimer (Time-out)
2 RTC_Alarm1 (Time-out)
3 RTC_Alarm2 (Time-out)
2
4 LDO Fault - A „1‟ indicates that one of the LDOs (Register 0xAx03, at least one of bits [7:0]) has faulted.
5 DCDC Fault – A „1‟ indicates that one of the DC to DC Converters (Register 0xAx02, at least one of bits [3:0]) has faulted.
6 Charger (Adapter in/charging state change)
7 ClassD Fault – The CLASS_D BTL Power Output has faulted. (Registers 0xA08B & 0xA08D, bit 4 must be set in both regs.)
0 Touch screen Pendown
1 Die temperature high (High temperature defined in A0E4h/A0E3h)
2 Battery voltage low
3 VSYS voltage low
3
4 ADC other interrupt except temperature high, battery low and VSYS low
5 Battery voltage extremely low (3.0V)
6 Die temperature extremely high (>155°C)
7 RESERVED
15.7.9 Global Register – I2C_SLAVE_ADDR

I²C Address = Page-x: 14(0x0E), µC Address = 0xA00E
Def. User
Set. Type
0101010b
[7:1] I²C_SLAVE_ADDR RW I²C slave address (Default = 0b0101010)
(2Ah)
15.7.10 Global Register – I2C_CLOCK_STRETCH

I²C Address = Page-x: 15(0x0F), µC Address = 0xA00F
Def. User
Set. Type
0 = Disabled
0 STRETCH_EN 0b RW I²C interface stretch function enable
1 = Enabled
0 = Disabled
1 CLK_GATE_EN 0b RW I²C interface clock-gating (for low power) function enable
1 = Enabled

15.8 ACCM REGISTERS
INT_DIR CONFIGURATION: I²C Address = Page-0: 16(0x10), µC Address = 0xA010

Def. User
Set. Type
Please refer to
[31:0] INT_DIR FFFF77FFh RW Interrupt direction (“1” map to internal processor).
above.
EXT_INT_DATA_IN: I²C Address = Page-0: 20(0x14), µC Address = 0xA014
Def. User
Set. Type
External processor generated interrupt associated data. External
[7:0] EXT_INT_DATA 00h RW
processor write to this register will set EXT_INT_STATUS bit.
EXT_INT_STATUS_IN: I²C Address = Page-0: 21(0x15), µC Address = 0xA015
Def. User
Set. Type
0 = Normal operation External processor interrupt status
0 EXT_INT_STATUS 0b RW1C
1 = Interrupt
INT_INT_DATA_IN: I²C Address = Page-0: 22(0x16), µC Address = 0xA016
Def. User
Set. Type
Internal processor generated interrupt associated data. Internal
[7:0] INT_INT_DATA 00h RW
processor write to this register will set INT_INT_STATUS bit
INT_INT_STATUS_IN: I²C Address = Page-0: 23(0x17), µC Address = 0xA017
Def. User
Set. Type
0 = Normal operation Internal processor interrupt status
0 INT_INT_STATUS 0b RW1C
1= Interrupt
UP_CONTEXT: I²C Address = Page-0: 24(0x18), µC Address = 0xA018
Def. User
Set. Type
[15:0] UP_CONTEXT 0000h RW Reserved for Processor context
DATA_BUF: I²C Address = Page-0: 26(0x1A), µC Address = 0xA01A
Def. User
Set. Type
Can be read or write by internal or external processor, this
[31:0] DAT_BUF 00000000h RW
register is for interprocessor communication.
CHIP_OPTIONS: I²C Address = Page-0: 30(0x1E), µC Address = 0xA01E
Def. User
Set. Type
4 EX_ROM 0b R EX_ROM pin value
[7:6] CHIP_OPT 00b R Chip metal option (metal changeable bit in metal fixed version)
DEV_REV: I²C Address = Page-0: 31(0x1F), µC Address = 0xA01F
Def. User
Set. Type
[7:0] DEV_REV 00h R Device revision

16.0 LDO MODULE

The P95020 includes two types of LDOs for external use:
 Four external use LDOs with current output up to 50mA normal LDOs (NMLDO) and one low-power, always on
 Initialization and power sequencing controlled by an LDO (LPLDO). There are seven NMLDOs which are
external CPU or the Embedded Microcontroller powered by external power inputs. The LPLDO is
 Output voltage adjustable in 25mV steps from 0.75V powered by VSYS. All of the external use LDOs share a
to 3.7V common ground pin.
 Programmable Overcurrent / Short Circuit Protection The P95020 also includes LDOs which are used by other
functional blocks within the device. The LDOs used by
 Three external use LDOs with current output up to the Audio module (LDO_AUDIO_18 and LDO_AUDIO_33)
150mA are powered by a dedicated power input. The remaining
 Initialization and power sequencing controlled by an internal-use LDOs are powered by VSYS.
external CPU or the Embedded Microcontroller
The power-up of each LDO is controlled by a built-in
 Output voltage adjustable in 25mV steps from 0.75V current-limiter. After each LDO is enabled, its current-
to 3.7V limiter will be turned-on (~100-200 s) and then the LDO
 Programmable Overcurrent / Short Circuit Protection will ramp up to the configured current-limit setting.
One user-selectable (3.0V or 3.3V), always-on low-power
The global enable control and each local enable control
LDO
(defined in each local LDO register) are AND-ed together
 10mA maximum output current to enable each specific LDO.
 Programmable Over Current / Short Circuit Protection
VDD_CKGEN18
VDD_CKGEN33
CKGEN_GND
LDO_LP
DGND
VSYS
LDO_IN1
VDD_CKGEN18 VDD_CKGEN33
DACVOUT: 0x60 [6:0]

LDO_150_0 LDO_150_0
DACILIM: 0x61 [1:0]
DACVOUT: 0x62 [6:0] LDO_150_1

GLOBAL POR
LDO_150_1
Internal Sub-Blocks
DACILIM: 0x63 [1:0]
DACVOUT: 0x64 [6:0]

LDO_150_2 LDO_150_2
REGISTER BUS DACILIM: 0x65 [1:0]

VOUTSEL33_30
LDO_LP 0x72 [0:0]
I2C/I2S
SUB-BLOCK
LDO_GND
LDO_IN2
DACVOUT: 0x66 [6:0]

MICROCONTROLLER LDO_50_0 LDO_50_0
SUB-BLOCK
DACILIM: 0x67 [1:0]
UPPER BYTE OFFSET: 0xA0
DACVOUT: 0x68 [6:0]

LDO_50_1 LDO_50_1
DACILIM: 0x69 [1:0]

LDO
EMBUP18
DACVOUT: 0x6A [6:0] LDO_50_2

LDO_50_2
DACILIM: 0x6B [1:0]
DACVOUT: 0x6C [6:0]

LDO_50_3 LDO_50_3
DACILIM: 0x6D [1:0]

VDD_AUDIO33 VDD_AUDIO18
VDD_AUDIO33
LDO_IN3
AGND
Figure 33 – LDO_050 / LDO_150 Block Diagram

16.1 LDO - PIN DEFINITIONS

023 VDD_AUDIO33 Filter capacitor for internal 3.3V audio LDO. Do not draw power from this pin.
029 LDO_GND Common GROUND for all LDOs.
030 LDO_IN3 Input Voltage to AUDIO LDOs (VDD_AUDIO33 & VDD_AUDIO18)
031 LDO_LP Always-On Low Power LDO for RTC.
032 LDO_050_3 50 mA LDO Output #3
033 LDO_IN2 Input Voltage to LDO_050_3, LDO_050_2, LDO_050_1 and LDO_050_0.
038 LDO_IN1 Input Voltage to LDO_150_2, LDO_150_1 and LDO_150_0.
045 VDD_CKGEN18 Filter Capacitor for Internal 1.8V CKGEN LDO
047 VDD_CKGEN33 Filter Capacitor for Internal 3.3V CKGEN LDO
16.2 LDO - LDO_150 & LDO_050 ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VIN1=VIN2=VSYS= 3.8V, TA = -40°C to +85°C, COUT=CIN=1µF

VIN1, VIN2 Input Voltage Requirements 3 5.5 V
VOUT Output Voltage Range 0.75 3.7 V
VSTEP Output Voltage Step Size 25 mV
Iout = 0 to Rated Current
VO Output Accuracy VIN = 3V to 5.5V -4 +4 %
Over Line And Load Conditions
(IRATED/3 load) 74 150

VDROPOUT Dropout voltage (VIN-VOUT) (IRATED/2 load) 102 200 mV
(IRATED load) 210 300
Note 1
LDO_050 50
IRATED Maximum Rated Output Current mA
LDO_150 150
Maximum Programmable Current LDO_050 65 125
ILIM mA
Limit LDO_150 195 375
% of
Maximum
ISTEP_SIZE Current Limit Step Size 25
Programmable
Current Limit
LDO150_0 @ 0x61 [1:0];
LDO150_1 @ 0x63 [1:0];
% of
LDO150_2 @ 0x65 [1:0];
Maximum
ILIM_RANGE Current Limit Programming Range LDO50_0 @ 0x67 [1:0]; 25 100
Programmable
LDO50_1 @ 0x69 [1:0];
Current Limit
LDO50_2 @ 0x6B [1:0];
LDO50_3 @ 0x6D [1:0];
Standard Operation All Three

LDOs Active, Measured At
VIN_IN1
Quiescent Current Into LDO_150
IQ150 40 53 µA
(IN#1)
LDO150_0 @ 0x60 [7:7] = 1;
LDO150_1 @ 0x62 [7:7] = 1;
LDO150_2 @ 0x64 [7:7] = 1;
Standard Operation All Four

LDOs Active, Measured At
VIN_IN2
Quiescent Current Into LDO_50
IQ50 53 71 µA
(IN#2) LDO50_0 @ 0x66 [7:7] = 1;
LDO50_1 @ 0x68 [7:7] = 1;
LDO50_2 @ 0x6A [7:7] = 1;
LDO50_3 @ 0x6C [7:7] = 1;
Notes:
1. Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its
nominal value measured at 1V differential. Not applicable to output voltages less than 3V.

16.3 LDO – TYPICAL PERFORMANCE CHARACTERISTICS
LDO_50_n Load Regulation
3.4
3.38
3.36
VOUT (V)
3.34
3.32
3.3
3.28
3.26
0 5 10 15 20 25 30 35 40 45 50
Load (mA)
Figure 34 – LDO_050_n 50mA LDO Load Regulation
LDO_150_n Load Regulation
3.4
3.38
3.36
Vout (V)
3.34
3.32
3.3
3.28
3.26
0 25 50 75 100 125 150
Load (mA)
Figure 35 – LDO_150_n 150mA LDO Load Regulation

16.4 LDO - LDO_LP - ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VIN=VSYS = 3.8V, TJ = 0°C to +85°C, COUT=CIN=1µF

VSYS SYS Input Voltage Requirements 3 5.5 V
VOUT Output Voltage TA=25C, Over Line And Load 3.15 3.3 3.45 V
VDROPOUT Dropout voltage (VIN-VOUT) IOUT = 10 mA, Note 2. 150 TBD mV
IOUT Output Current 10 mA
Notes:
2. Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its
nominal value measured at 1V differential. Not applicable to output voltages less than 3V.
16.5 LDO - LIST OF ALL LDOS
LDO Name Source VOUT Comments For Module
0.75V –
LDO_150 LDO_IN1 150 mA max. LDO External Usage
3.7V
0.75V –
LDO_050 LDO_IN2 50 mA max. LDO External Usage
3.7V
LDO_LP VSYS 3.3 / 3.0 Always on LDO, selectable 3.3V or 3.0V output voltage
VDD_CKGEN33 VSYS 3.3 Turn On/Off depending on PSTAT_ON register (Cyrus “ON” flag) CKGEN
VDD_CKGEN18 VSYS 1.8 Turn On/Off depending on PSTAT_ON register (Cyrus “ON” flag)
VDD_AUDIO33 LDO_IN3 3.3 Can be turned on/off via enable bits in LDO_AUDIO18 and AUDIO &
VDD_AUDIO18 LDO_IN3 1.8 LDO_AUDIO33 registers CLASS_D_DIG
VDD_EMBUP18 VSYS 1.8 Turn On/Off depending on whether there is an interrupt pending EMBUP
16.6 LDO – REGISTER SETTINGS

The LDO Module can be controlled and monitored by writing 8-bit control words to the various registers. The base
addresses are defined in Table 3 – Register Address Global Mapping on page 20.
16.6.1 LDO_150 AND LDO_050 – OPERATION REGISTERS

The Output Voltage Registers for the LDO_150 & LDO_050 LDOs contain the enable bit and setting bits for the output
voltage.
LDO_150_0 = I²C Address = Page-0: 96(0x60), µC Address = 0xA060
LDO_050_2 = I²C Address = Page-0: 106(0x6A), µC Address = 0xA06A
LDO_050_3 = I²C Address = Page-0: 108(0x6C), µC Address = 0xA06C
Def. User
Set. Type
Output Voltage =
Performance and accuracy are not guaranteed with bit combinations
[6:0] VOUT [] RW VOUT * 25 mV +
above 1110110.
750 mV
1 = Enable LDO local enable bit for the LDO_150 and LDO_050 LDOs
7 ENABLE 0b RW
0 = Disable Reserved bit for LDO_050_0

16.6.2 LDO_150 AND LDO_050 – CONTROL REGISTERS

The Control Registers contains bits for setting the Current Limit.
LDO_050_2 = I²C Address = Page-0: 107(0x6B), µC Address = 0xA06B
LDO_050_3 = I²C Address = Page-0: 109(0x6D), µC Address = 0xA06D
Def. User
Set. Type
[1:0] I_LIM 00b RW (See Table 31) Current Limit (%)
Table 31 – Control Register Current Limit (I_LIM) Settings for Bits [1:0]
0 0 Current Limit = 120 % of Rating
Note – Current Limit is at maximum when bits [1:0] are both set to 0.
16.6.3 VDD_AUDIO18 LDO REGISTER

The VDD_AUDIO18 Register contains the enable bit and the output voltage bit.
Def. User
Set. Type
0 = 1.8 V
0 SEL_15V 0b RW Select VDD_Audio18 Output Voltage (1.8V or 1.5V)
1 = 1.5 V
0 = Not Enabled
7 EN_AUDIO18 0b RW Enable VDD_AUDIO18 LDO
1 = Enabled
16.6.4 VDD_AUDIO33 LDO REGISTER

The VDD_AUDIO33 Voltage Register contains the enable bit and the output voltage bits.
Def. User
Set. Type
Output Voltage =
Default = 3.3 V. Performance and accuracy are not guaranteed with bit
[6:0] VOUT 1100110b RW VOUT * 25 mV +
combinations above 1110110 (3.7V).
750 mV
0 = Disable
7 EN_AUDIO33 0b RW Enable Audio_33 LDO
1 = Enable
16.6.5 EXTERNAL LDO POWER GOOD REGISTER

The LDO_STATUS1 Register contains the power good bits for the LDO_150 and LDO_050 LDOs.
Def. User
Set. Type
0 LDO_150_0_PG N/A R Power Good Status for LDO_150_0
2 LDO_150_2_PG N/A R 0 = Power NOT Power Good Status for LDO_150_2
3 LDO_050_0_PG N/A R Good Power Good Status for LDO_050_0
4 LDO_050_1_PG N/A R 1 = Power IS Good Power Good Status for LDO_050_1

16.6.6 INTERNAL LDO POWER GOOD REGISTER

The LDO_STATUS2 Register contains power good bits for internal LDOs: VDD_AUDIO33, VDD_CKGEN18 and
VDD_CKGEN33.
Def. User
Set. Type
0 VDD_AUDIO33_PG N/A R Power Good Status for AUDIO33 LDO
0 = Power NOT Good
1 VDD_CKGEN18_PG N/A R Power Good Status for CKGEN18 LDO
1 = Power IS Good
2 VDD_CKGEN33_PG N/A R Power Good Status for CKGEN33 LDO
00000
b
16.6.7 LOW POWER LDO VOLTAGE REGISTER

The LDO_LP Voltage Register contains one voltage select bit.
LDO_LP_VOL: I²C Address = Page-0: 114(0x72), µC Address = 0xA072
Def. User
Set. Type
0 = 3.3 V
0 LDO_LP_VOL 0b RW Select “Always-On” LDO Output Voltage (Default = 3.3V, Optional = 3.0V)
1 = 3.0 V
16.6.8 EXTERNAL LDO FAULT INTERRUPT ENABLE REGISTER

The EXT_LDO_FAULT_INT_EN Register contains the fault interrupt enable bits for the 7 external LDOs.
LDO_FAULT: I²C Address = Page-0: 115(0x73), µC Address = 0xA073
Def. User
Set. Type
0 LDO_050_0_FLT_INT_EN 0b RW Fault interrupt enable for LDO_050_0
0 = Disable
1 = Enable
16.6.9 LDO - INT_LDO_FAULT_INT Interrupt Register

The INT_LDO_FAULT_INT Register contains contains the Fault Status bits for the internal LDOs
Def. User
Set. Type
0 VDD_AUDIO33_FLT 0b R Fault in VDD_AUDIO33 regulator
1 VDD_CKGEN18_FLT 0b R 0 = No Fault Fault in VDD_CKGEN18 regulator
2 VDD_CKGEN33_FLT 0b R 1 = Fault Exists Fault in VDD_CKGEN33 regulator
3 LDO_LP_FAULT 0b R Fault in LDO_LP regulator
16.6.10 LDO SECURITY REGISTER

I²C Address = Page-0: 119(0x77), µC Address = 0xA077h
Def. User
Set. Type
0 = Access allowed Allows or blocks the user from programming bit 4 in all of the external LDO
0 LDO_SEC_0 0b RW
1 = Access blocked Output Voltage Registers.
1 LDO_SEC_1 0b RW
2 LDO_SEC_2 0b RW

16.6.11 LDO - RESERVED Registers

Thru Page-0: 127(0x7F), µC Address = 0xA07F

17.0 EMBUP – EMBEDDED MICROCONTROLLER SUBSYSTEM & I/O

The Embedded Microcontroller (EMBUP) of the P95020
 Power Up/Down Sequencing can operate in one of two modes: mixed mode or stand-
alone mode. In mixed mode, both the internal
 Eliminates the need for the AP or another external
controller (PLD/PIC) to perform this function. microcontroller and an external Application Processor
(AP) can also control some or all of the P95020
 Improves system power consumption by offloading this task subsystems. In stand-alone mode, the EMBUP
from the higher power application processor. completely offloads power sequencing and other functions
General monitoring and action based on external or from the application processor so that the processor can
internal events such as: perform other functions or spend more time in sleep
 ADC Result mode.
 Power Supply Fault Monitoring
The microcontroller core runs at 8 MHz with a 1.8V power
 Other System Interrupts supply and can be shut off if required. It interfaces
through VSYS level signals (3.0 to 5.5V) and supports the
following functions:
Device initialization
Power sequencing for power state transitioning
Keyboard scanning
Enable/Disable of all Interfaces and Sub-Modules
17.1 OVERVIEW
Module Interrupts Interrupts Usage
ACCM Message signaling 1 Internal /external processor communication
CHGR Adapter In/ Charging state change 3 Charger state detection
CLASSD-Driver Fault 1
DCDC Fault 1
GPTIMER General purpose timer, Watchdog timer 2
LDO Fault 1
GPIO GPIO/SW_DET 10/2 System power on/off
RTC Alarm-1, Alarm-2 2
TSC Pendown 1
Die temperature high,
TSC Battery voltage low, 3
VSYS voltage low
17.2 FUNCTIONAL DESCRIPTION

After a Power on Reset (POR), the P95020 embedded microcontroller will look for the presence of an external ROM via
the EX_ROM pin. If an external ROM is present, the P95020 embedded microcontroller will disable the internal ROM,
and load the contents into a 1.5 KB internal RAM from which it can be executed. If no external ROM is present, then the
internal ROM will be used for program code.
The P95020 embedded microcontroller will execute the start-up sequence contained in the internal or external ROM and
will set the various registers accordingly (all internal registers are available for manipulation by an external application
processor through the I²C interface at all times). Once the registers have been programmed, the embedded
microcontroller will either run additional program code or go into standby until an interrupt or other activity generates a
wake event. Various events will be customer specific but could include power saving modes, sleep modes, over-
temperature conditions, etc.
Contention caused by requests from both the embedded microcontroller and external processor is resolved through a bus
arbitration scheme. There is no support for data concurrency in the register set. The P95020 will execute the latest (last)
data/command programmed into any individual control register(s) regardless of the source (embedded microcontroller or
external application processor). Care should be taken during the code development stage to avoid command contention.
17.3 ON-CHIP RAM & ROM
Memory Type Size
ROM 4 k Bytes Maximum
RAM 1.5 k Bytes Maximum
17.4 I²C SLAVE INTERFACE

Please see the separate I2C_I2S Module in Section 15.0 for details (including register definitions).

17.5 PERIPHERALS
The peripherals of the subsystem are comprised of a timer, an interrupt controller and an I²C master. The embedded
processor‟s peripherals are not visible to the external application processor.
The I²C master is used to optionally load data or code from an external serial EEPROM. The target EEPROM address is
hardwired to 1010000. The P95020 supports EEPROMs using 16-bit addressing in the range of 4 kB to 64KB.
17.6 INTERRUPT CONTROLLER
17.6.1 OVERVIEW
The interrupt controller is built in to the EMBUP core and is only used to monitor subsystem interrupts.
CHGR:
Charger LDO DCDC I2CS_OTP
FAULT
TSCD: touch pendown

GPTIMER
screen digital
ACCM: AP
CKGEN RTC I2C-Slave/Bus TSCA
Arbiter
GPIO_TSCA
EMBUP INT
Embedded uP
subsystem, I2C PCON: GPIO Pendown
Master Power controller
HSWP:
AUDIO CLASSD_DIG
Hot swap
Figure 36 - Top level Interrupt routing
17.6.2 INTERRUPT HANDLING SCHEME

Each of the different functional modules may generate interrupts and these interrupts can be enabled or disabled using
their associated interrupt enable registers. The generated interrupts may also be handled by either the internal
microcontroller or an external processor. The interrupts generated from the functional modules are routed to the access
manager (ACCM) module. The ACCM module will direct the interrupts to the appropriate processor (internal or external)
according to the configurable defined in the ACCM Register.
Please note that there is no hardware level protection in to prevent interrupts that have been processed by one processor
from being cleared by the other other processor. Care must be taken in software to prevent this usage scenario.

18.0 APPLICATIONS INFORMATION

18.1 EXTERNAL COMPONENTS
The P95020 requires a minimum number of external components for proper operation.
18.2 DIGITAL LOGIC DECOUPLING CAPACITORS
As with any high-performance mixed-signal IC, the P95020 must be isolated from the system power supply noise to
perform optimally. A decoupling capacitor of 0.01 μF must be connected between each power supply and the PCB
ground plane as close to these pins as possible. For optimum device performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
18.3 CLASS_D CONSIDERATIONS
The CLASS_D amplifier should have one 330uF and one 0.1uF capacitor to ground at its VDD pin.
The CLASS_D output also should have a series connected snubber consisting of a 5.1 ohm, 0603 resistor and a 220pF
capacitor across the speaker output pins. No other filtering is required.
The CLASS_D BTL plus and minus output traces must be routed side by side in pairs.
18.4 SERIES TERMINATION RESISTORS
Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
18.5 I²C EXTERNAL RESISTOR CONNECTION
The SCK and SDATA pins can be connected to any voltage between 1.71 V and 3.6 V.
18.6 CRYSTAL LOAD CAPACITORS
To save discrete component cost, the P95020 integrates on-chip capacitance to support a crystal with CL=10 pF. It is
important to keep stray capacitance to a minimum by using very short PCB traces between the crystal and device. Avoid
the use of vias if possible.
18.7 PCB LAYOUT CONSIDERATIONS
For optimum device performance and lowest output phase noise, the following guidelines should be observed.
1. The 0.01μF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to each VDD pin
should be kept as short as possible, as should the PCB trace to the ground via.
2. The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead they should be separated and away from other traces.
3. To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output.
4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the P95020. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used by the device.
18.8 POWER DISSIPATION AND THERMAL REQUIREMENTS
The power dissipated in the P95020 will depend primarily 120
on the total internal power dissipation and the junction 110
temperature. Careful consideration must be given to the 100
overall thermal design. Actual thermal resistance JA 90

80
must be determined at the customer‟s end product level,
Rated Power (%)
70
being based on the end package design parameters and
60
available device internal cooling. See Figure 37 for
50
required package power de-rating. 40
30
18.9 TYPICAL BLOCK PERFORMANCE
20
CHARACTERISTICS GRAPHS 10
This section is TBD. -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
Junction Temperature (°C)
Figure 37 – Power Derating Curve (Typical)

18.10 APPLICATIONS REFERENCE DESIGN(S)

This section is TBD.
19.0 SOLDERING PROFILE

This section is TBD.
20.0 PACKAGE OUTLINE DRAWING

20.1 LLG124 PACKAGE OUTLINE

20.2 NQG132 PACKAGE OUTLINE (Exposed Die Paddle Size D2 = E2 = 5.5 mm)
21.0 ORDERING INFORMATION

Part / Order Number Shipping Packaging Package Temperature
P95020ZLLG Tubes 124-pin LLGA 0 to +70 C
P95020ZLLG8 Tape and Reel 124-pin LLGA 0 to +70 C
P95020ZLLGI Tubes 124-pin LLGA -40 to +85 C
P95020ZLLGI8 Tape and Reel 124-pin LLGA -40 to +85 C
P95020ZNQG Tubes 132-pin QFN 0 to +70 C
P95020NQG8 Tape and Reel 132-pin QFN 0 to +70 C
P95020ZNQGI Tubes 132-pin QFN -40 to +85 C
P95020ZNQGI8 Tape and Reel 132-pin QFN -40 to +85 C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from
its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any
other applications such as those requiring extended temperature ranges, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or
specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.

Innovate with IDT. Contact:
www.IDT.com
For Sales For Tech Support
800-345-7015 www.idt.com/
408-284-8200
Fax: 408-284-2775
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks
of Integrated Device Technology, Inc.. Accelerated Thinking is a service mark of Int4grated Device Technology, Inc. All other brands, product names and
marks are or may be trasdemarks or registered trademarks used to identify products or services of their respective owners.

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Audio, Power Management P95020

OVERVIEW KEY FEATURES

Revision 0.7.10 1 ©2010 Integrated Device Technology, Inc.

Real Time Clock

RAM CLASS_D Amp

BUCK1000 (1000 mA DC-DC)

Figure 1 – P95020 Block Diagram.

Revision 0.7.10 2 ©2010 Integrated Device Technology, Inc.

Revision 0.7.10 3 ©2010 Integrated Device Technology, Inc.

5.0 RTC MODULE ......................................................................................................................................................... 66

Revision 0.7.10 4 ©2010 Integrated Device Technology, Inc.

15.4 ACCESS ARBITER ........................................................................................................................................... 117

Figure 1 – P95020 Block Diagram. ......................................................................................................................................... 2

Revision 0.7.10 5 ©2010 Integrated Device Technology, Inc.

Table 1 – LLG124 Pin Functions by Pin Number (See Figure 2) ........................................................................................... 9

Revision 0.7.10 6 ©2010 Integrated Device Technology, Inc.

GPIO6/ADC1 002 092 LED_BOOST_GATE

LDO_LP 031 063 I2S_SDIN1

LDO CKGEN I2C_I2S

Figure 2 – P95020 Pinout Diagram (LLG124)

Revision 0.7.10 7 ©2010 Integrated Device Technology, Inc.

LDO_LP A18 A37 I2S_SDOUT1

Figure 3 – P95020 Pinout (NGQ132)

Revision 0.7.10 8 ©2010 Integrated Device Technology, Inc.

PIN FUNCTIONS BY PIN NUMBER

Revision 0.7.10 9 ©2010 Integrated Device Technology, Inc.

MODULE PIN # PIN NAME DESCRIPTION I/O TYPE

Revision 0.7.10 10 ©2010 Integrated Device Technology, Inc.

MODULE PIN # PIN NAME DESCRIPTION I/O TYPE

Table 2 - NQG132 Pin Functions by Pin Number (see Figure 3)

Revision 0.7.10 11 ©2010 Integrated Device Technology, Inc.

MODULE PIN # PIN NAME DESCRIPTION I/O TYPE

Revision 0.7.10 12 ©2010 Integrated Device Technology, Inc.

MODULE PIN # PIN NAME DESCRIPTION I/O TYPE

Revision 0.7.10 13 ©2010 Integrated Device Technology, Inc.

MODULE PIN # PIN NAME DESCRIPTION I/O TYPE

I/O LEVELS BY TYPE

Revision 0.7.10 14 ©2010 Integrated Device Technology, Inc.

ABSOLUTE MAXIMUM RATINGS

Revision 0.7.10 15 ©2010 Integrated Device Technology, Inc.

RECOMMENDED OPERATING CONDITIONS

DIGITAL INTERFACES - DC ELECTRICAL CHARACTERISTICS

I2C SLAVE - ELECTRICAL CHARACTERISTICS

I2S - ELECTRICAL CHARACTERISTICS

GPIO - ELECTRICAL CHARACTERISTICS

Revision 0.7.10 16 ©2010 Integrated Device Technology, Inc.

OVERALL POWER CONSUMPTION

AUDIO POWER CONSUMPTION

Revision 0.7.10 17 ©2010 Integrated Device Technology, Inc.

5V Boost DC-DC Buck

Figure 4 – Overall System Functional Diagram.

Revision 0.7.10 18 ©2010 Integrated Device Technology, Inc.

1.1 FUNCTIONAL MODES

External Processor Control

Combined Internal and External Processor Operation

Revision 0.7.10 19 ©2010 Integrated Device Technology, Inc.

1.2 REGISTER MAP

Revision 0.7.10 20 ©2010 Integrated Device Technology, Inc.

1.3 BYTE ORDERING AND OFFSET