Notes:: Computer Organization
Notes:: Computer Organization
Notes:: Computer Organization
ORGANIZATION
TOPIC FOR THE WEEK: 8086/8088 Architecture
NOTES:
Intel released the world’s first p in 1971. The 4004 is a 4-bit p with
maximum memory of only up to 4,096 4-bit memory locations (2,048
bytes). It only has 45 instructions and was used in very limited
applications such as early video games and small p-based controllers.
2. In 1973, Intel released the 8080. The 8080 can address a total of
65,536 bytes and can execute an ADD instruction in 2 s only.
In 1978, Intel released the 8086 p and a year later the 8088. Both are
16-bit p’s and can execute instructions in as little as 400 ns. Both can
address a total of 1,048,576 bytes or 524,288 16-bit words.
The main difference between the 8086 and the 8088 is the size of their
external data bus. The external data bus of the 8088 is only 8-bits wide
while that of the 8086 is 16-bits wide (take note the internal data bus of
the 8088 is 16-bits wide). The reason for this is that many designers still
wanted to use the cheaper 8-bit support and peripheral chips in their 16-
bit systems.
The 8088 was the p used by IBM in their Personal Computer (PC), the
PC XT, and the Portable Computer.
CODE: CSP107
Page 1 of 11
COMPUTER Basic 8086/8088 Architecture
ORGANIZATION
EU BIU
NOTES:
The bus interface unit is the part of the CPU that interfaces with the rest
of the PC. Its name comes from the fact that it deals with moving
information over the processor data bus, the primary conduit for the
transfer of information to and from the CPU. It has bus controller that is
responsible for responding to all signals that go to the processor, and
generating all signals that go from the processor to other parts of the
system.
The EU extracts instructions from the top of the queue in the BIU,
decodes them, generates operand addresses if necessary, passes them
to the BIU and requests it to perform the read or write bus cycles to
memory or I/O, and performs the operation specified by the instruction
on the operands.
CODE: CSP107
Page 2 of 11
COMPUTER During execution of the instruction, EU tests the status and control flags
ORGANIZATION and updates them based on the results of executing the instruction. If the
queue is empty, the EU waits for the next instruction byte to be fetched
and shifted to the top of the queue.
NOTES: When the EU executes a branch or jump instruction, it transfers control
to a location corresponding to another set of sequential instructions.
Whenever this happens, the BIU automatically resets the queue and
then begins to fetch instructions from this new location to refill the queue.
To
8086 D0 to D15
Data Bus Memory
System
and I/O
Control Bus
RD, WR, M/IO
A0 to A19
Address Bus
To
D0 to D7
Memory
8088 and I/O
Data Bus
System
The M/IO’ (or IO/M’) signal is for selecting the memory or I/O of the
system. If it is logic 0, then memory is selected; if it is logic 1, I/O is
selected.
Logical Memory
FFFFFH
FFFFEH
FFFFDH
1M
Figure 3.
Bytes
Logical
00002H Memory Map
00001H
00000H
CODE: CSP107
Page 3 of 11
COMPUTER It starts at memory location 00000H and extends to location FFFFFH.
ORGANIZATION The logical memory is 8 bits wide.
A 16-bit word of memory begins at any byte address and extends for two
consecutive bytes. For example, the word at location 00122H is stored
NOTES: at byte 00122H and 00123H with the least significant byte stored in
location 00122H.
Physical Memory
The physical memory is the actual organization of the memory that the
hardware designers see. The physical memory map of the 8088 is
identical to its logical memory map.
FFFFFH FFFFEH
FFFFDH FFFFCH
FFFFBH FFFFAH
512 K 512 K
Bytes Bytes
00005H 00004H
00003H 00002H
00001H 00000H
16 bits
The advantage of this organization is that the 8086 can read or write a
16-bit word in one operation (provided the addresses of the data are
even). The 8088 requires two reads or writes to transfer 16 bits of data.
CODE: CSP107
Page 4 of 11
COMPUTER Register Structure of the 8086/8088
ORGANIZATION
All forms of programming depend upon a clear understanding of the
internal register structure of the p.
NOTES: 8 Bits 8 Bits
AH AL AX Accumulator
BH BL BX Base General
Purpose
CH CL CX Count Register
DH DL DX Data
SP Stack Pointer
BP Base Pointer Pointer and
SI Source Index Index
DI Destination Index Registers
IP Instruction Pointer
CS Code Segment DS
Data Segment SS Segment
Stack Segment ES Registers
Extra Segment
Flags
16 Bits
General Purpose Registers. These are used in any manner that the
programmer wishes. Each is addressable as a 16-bit register (AX, BX,
CX, DX) or as two 8-bit registers (AH, AL, BH, BL, CH, CL, DH, and DL).
CODE: CSP107
Page 5 of 11
COMPUTER Pointer and Index Registers
ORGANIZATION
Pointer and Index Registers. Although the pointer and index registers
are also general purpose in nature, they are more often used to index or
NOTES: point to the memory location holding the operand data for many
instructions.
CODE: CSP107
Page 6 of 11
COMPUTER Conditional Flags (cont…)
ORGANIZATION
4. Carry Flag (CF) - b0
NOTES: An addition causes this flag to be set to 1 if there is a carry out of the
MSB, and a subtraction causes it to be set to 1 if a borrow is needed.
Example 1
1.
0010 0011 0100 0101
+ 0011 0010 0001 1001
0101 0101 0101 1110
SF = 0 ZF = 0 PF = 0 CF = 0 AF = 0 OF = 0
In this example, the sign flag (SF) is 0 since the MSB is 0, the zero flag
(ZF) is 0 since the result is nonzero, the parity flag (PF) is 0 since the
low-order 8 bits or the first 8 bits from the least significant bit (LSB) has
odd number of ones, the carry flag (CF) is 0 since there is no carry out of
the most significant bit (MSB), the auxiliary flag (AF) is 0 since there is
no carry out of bit 3 and overflow flag (OF) is 0 since there is no carry
into the MSB and no carry out of the MSB.
2.
SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 OF = 1
In this example, the sign flag (SF) is 1 since the MSB is 1, the zero flag
(ZF) is 0 since the result is nonzero, the parity flag (PF) is 1 since the
low-order 8 bits or the first 8 bits from the least significant bit (LSB) has
even number of ones, the carry flag (CF) is 0 since there is no carry out
of the most significant bit (MSB), the auxiliary flag (AF) is 1 since there is
a carry out of bit 3 (b3) and overflow flag (OF) is 1 since there is a carry
into the MSB and no carry out of the MSB.
CODE: CSP107
Page 7 of 11
COMPUTER Example 2
ORGANIZATION
1.
0101 0100 0011 1001
NOTES: + 0100 0101 0110 1010
1001 1001 1010 0011
SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 OF = 1
In this example, the sign flag (SF) is 1 since the MSB is 1, the zero flag
(ZF) is 0 since the result is nonzero, the parity flag (PF) is 1 since the
low-order 8 bits or the first 8 bits from the least significant bit (LSB) has
even number of ones, the carry flag (CF) is 0 since there is no borrow by
the most significant bit (MSB), the auxiliary flag (AF) is 1 since there is a
borrow by bit 3 (b3) and overflow flag (OF) is 1 since there is a borrow by
the MSB and no borrow from the MSB.
2.
0001 0010 0011 0100
+ 0100 1010 1110 0000
0101 0101 0001 0100
SF = 0 ZF = 0 PF = 0 CF = 0 AF = 0 OF = 0
In this example, the sign flag (SF) is 1 since the MSB is 1, the zero flag
(ZF) is 0 since the result is nonzero, the parity flag (PF) is 0 since the
low-order 8 bits or the first 8 bits from the least significant bit (LSB) has
odd number of ones, the carry flag (CF) is 1 since there is a borrow by
the most significant bit (MSB), the auxiliary flag (AF) is 0 since there is
no borrow by bit 3 (b3) and overflow flag (OF) is 0 since there is a
borrow by the MSB and a borrow from the MSB.
Example 3
Perform the following arithmetic operation and determine the state of the
conditional flags.
1. 70A3H + E757H
2. FE58H + 01A8H
CODE: CSP107
Page 8 of 11
COMPUTER Exercises
ORGANIZATION
Perform the following arithmetic operation and determine the state of the
conditional flags.
NOTES:
1. AA45H + 4678H
2. 234FH + 34CDH
3.
0110 0010 1010 0000
+ 1001 1101 0110 0000
0000 0000 0000 0000
SF = 0 ZF = 1 PF = 1 CF = 1 AF = 0 OF = 0
Control Flags
If set, the 8086/8088 will enter into a single-step mode. In this mode, the
CPU executes one instruction at a time.
CODE: CSP107
Page 9 of 11
COMPUTER Segment Registers and Memory Segmentation
ORGANIZATION
Even though the 8086/8088 has a 1MB memory address space, not all
this memory can be active at any one time.
NOTES:
64 KB
Segment
Base Address
.
.
.
64 KB
Data
Segment
.
Offset .
.
Base Address
Both segment base address and offset are 16 bits long. Therefore, the
lowest-addressed byte in a segment has an offset of 0000H and the
highest-addressed byte has an offset of FFFFH.
CODE: CSP107
Page 10 of 11
COMPUTER Example 1
ORGANIZATION
Determine the physical address of the following:
Computing for the physical address is just getting the sum of the
physical segment base address and the offset address. The
physical segment base address is the segment base address
shifted 4 bits to the left or simply appends 0 before the least
significant bit (LSB).
Take note that the offset address is sometimes called the effective
address.
Example: 1234H:0022H
Example 2
Exercise
CODE: CSP107
Page 11 of 11