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    Clock Gating - Semicon Shorts

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    Sai Uttej Mandala
    Clock gating is a technique to reduce power consumption by stopping the clock signal when it is not needed. There are two main approaches: simple clock gating uses an AND gate but can introduce glitches, while latch-based clock gating uses a latch to create a glitch-free gated clock signal by holding the previous value when the clock is high. Additional points discuss how tools perform clock gating insertion during synthesis and how enable signals are typically derived from software or hardware.

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    Clock Gating - Semicon Shorts

    Uploaded by

    Sai Uttej Mandala
    125 views4 pages
    Clock gating is a technique to reduce power consumption by stopping the clock signal when it is not needed. There are two main approaches: simple clock gating uses an AND gate but can introduce glitches, while latch-based clock gating uses a latch to create a glitch-free gated clock signal by holding the previous value when the clock is high. Additional points discuss how tools perform clock gating insertion during synthesis and how enable signals are typically derived from software or hardware.

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    clock gating concepts

    Original Title

    Clock Gating – Semicon Shorts

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    Clock gating is a technique to reduce power consumption by stopping the clock signal when it is not needed. There are two main approaches: simple clock gating uses an AND gate but can introduce glitches, while latch-based clock gating uses a latch to create a glitch-free gated clock signal by holding the previous value when the clock is high. Additional points discuss how tools perform clock gating insertion during synthesis and how enable signals are typically derived from software or hardware.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    125 views4 pages

    Clock Gating - Semicon Shorts

    Uploaded by

    Sai Uttej Mandala
    Clock gating is a technique to reduce power consumption by stopping the clock signal when it is not needed. There are two main approaches: simple clock gating uses an AND gate but can introduce glitches, while latch-based clock gating uses a latch to create a glitch-free gated clock signal by holding the previous value when the clock is high. Additional points discuss how tools perform clock gating insertion during synthesis and how enable signals are typically derived from software or hardware.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Semicon Shorts

    Clock Gating
    Let us discuss clock gating in simplest terms.

    Definition:
    Technique to switch off the clock when not in use. It reduces the switching activity
    and hence, saves dynamic power, without affecting the design functionality.

    Simplest Clock Gating


    Naming:
    ‘en’: Enable signal.
    ‘clk’: The non-gated original cloc
    ‘g_clk’: Gated clock (off when not in use)
    Working:
    When ‘en’ is 1: Clock goes to the next flop
    When ‘en’ is 0: Clock to the next flop is blocked by AND gate.
    Pros and Cons:
    ++ Simple, easy to code, consumes less area

    — Can cause glitches in the gated clock. (If the change in ‘en’ occurs when clk is ‘1’
    as given, it causes glitches in the gated clock.)

    Latch Based Clock Gating


    Use a latch (level-sensitive) to create a glitch-free clock gating cell.
    Naming:
    ‘en’: Enable signal.
    ‘clk’:clk’:
    ‘g The Gated
    non clock
    gated(off
    original
    whenclock
    not in use)
    g_clk
    clk : The
    ‘latch’: : D-latch
    Gated
    non-gated
    clock (off
    original
    when
    (negatively clock
    not in use)
    triggered i.e. allows the input to pass when clk is ‘0’ )

    Glitch Free Behavior


    This is a modification of simplest clock gating, by introducing a negative latch as
    shown. When clock is ‘1’, the latch doesn’t allow the glitch in ‘en’ signal to pass to the
    latch output ‘Q’. It holds the previous value when clk signal was ‘0’, hence eliminating
    the glitch in gated clock.
    Additional Points
    The clock gating insertion is mostly done by the tools nowadays, while
    performing the synthesis operation. The above circuits discussed are referred as
    ICGs (Integrated Clock Gating Circuits), which are added by the tool based on
    the commands given by the engineers.
    The ‘en’ signal used in the design can come from software, or can be a hardware
    generated signal. The simplest example of hardware derived enable is: ‘en’ is
    the XOR output of the ‘D’ and ‘Q’ of the next gated flop. This way, ‘en’ is 1 only
    when the value of ‘D’ and ‘Q’ differs i.e. flip-flop value needs to be updated.
    We discussed a negative latch and AND based circuit above. Glitch free gated
    clock can also be derived by a positive latch and an OR gate circuit. The
    diagram is as follows:

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