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    CS2203 - Computer Organization - MTE1 Paper

    Uploaded by

    Ushashi Nandi
    This document appears to be an exam for a Computer Organization course. It contains 5 questions related to computer architecture topics like control unit design, cache memory, and memory organization. The questions assess understanding of concepts like control signal generation, instruction execution sequences, encoding techniques, cache hit/miss calculations, and memory mapping. Students are asked to write logic functions, draw circuits, perform calculations, and analyze memory access patterns.

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    CS2203 - Computer Organization - MTE1 Paper

    Uploaded by

    Ushashi Nandi
    46 views2 pages
    This document appears to be an exam for a Computer Organization course. It contains 5 questions related to computer architecture topics like control unit design, cache memory, and memory organization. The questions assess understanding of concepts like control signal generation, instruction execution sequences, encoding techniques, cache hit/miss calculations, and memory mapping. Students are asked to write logic functions, draw circuits, perform calculations, and analyze memory access patterns.

    Original Description:

    computer organization questions

    Original Title

    CS2203_Computer Organization_MTE1 Paper (1)

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    This document appears to be an exam for a Computer Organization course. It contains 5 questions related to computer architecture topics like control unit design, cache memory, and memory organization. The questions assess understanding of concepts like control signal generation, instruction execution sequences, encoding techniques, cache hit/miss calculations, and memory mapping. Students are asked to write logic functions, draw circuits, perform calculations, and analyze memory access patterns.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    46 views2 pages

    CS2203 - Computer Organization - MTE1 Paper

    Uploaded by

    Ushashi Nandi
    This document appears to be an exam for a Computer Organization course. It contains 5 questions related to computer architecture topics like control unit design, cache memory, and memory organization. The questions assess understanding of concepts like control signal generation, instruction execution sequences, encoding techniques, cache hit/miss calculations, and memory mapping. Students are asked to write logic functions, draw circuits, perform calculations, and analyze memory access patterns.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    Reg.No.

    Faculty of Engineering
    School of Computing and IT
    Department of CSE
    IV SEM. B.Tech.
    Even Semester Mid Term-I Examination 2021-22
    CS2203 Computer Organization

    Time: 1 Hour MAX.MARKS: 20

    Instructions to Candidates
    • Attempt all Questions.
    • Draw freehand circuit diagrams showing proper connections between various units.
    • Missing data, if any, may be assumed suitably.
    • Calculator is allowed.

    Q. No. Question Script Marks


    1 Consider a hypothetical hardwired control unit which support four [4]
    control signals S0, S1, S2, S3 and three instructions I1, I2 and I3.
    Each instruction requires four microoperations at time steps T1, T2,
    T3 and T4 to execute. The table given below shows the control
    signals required for each microoperation, for execution of each
    instruction.
    Write down the logic functions required to generate control signals
    CO1
    S0 and S1 and show the corresponding circuit.

    I1 I2 I3
    T1 SO S0 S0
    T2 S2, S3 S2 S1, S2
    T3 S1 S3 S1, S3
    T4 S0 S2, S3 S0, S2
    2 Write down the control sequence for the following instructions [4]
    (given as operation source destination) considering three-bus
    organization of the datapath. CO1
    (i) ADD (R1), R2
    (ii) BRANCH LABEL

    3 In a hypothetical processor having single-bus organization of the [4]


    datapath, the control signals are encoded using micro-programmed
    control unit. Consider there are total 55 control signals, and these CO1
    control signals can be divided into 4 mutually exclusive sets
    containing 15, 15, 8 and 17 control signals.

    Page 1 of 2
    (i) Determine the control word size for horizontal, vertical
    and hybrid/diagonal (mutually exclusive) encoding
    techniques.
    (ii) Calculate the control store size required for execution of
    instruction ADD R1, R2 using horizontal, vertical and
    hybrid/diagonal (mutually exclusive) encoding
    techniques.

    4. Consider a 4-way set associative mapped cache. The size of cache [4]
    memory is 1 MB and there are 12 bits in the tag. Calculate the size CO3
    of main memory.
    5. Suppose that a byte-addressable computer has a processor with two [4]
    caches, one for instructions and one for data. A 100×100 array
    NUM[100][100] of numbers, each occupying one byte, is stored in
    main memory locations 0000 through 270F. Instruction cache
    contains the following array-initialization loop for initializing the
    array.

    for (int j = 0; j < 100; j++)


    for (int i = 0; i < 100; i++) CO3
    A[i][j] = 0;

    Fully associative data cache is initially empty and consists of 10


    blocks with block size of 100 bytes. Assuming LRU replacement
    policy, answer the following:
    (i) How many cache-misses would occur if the elements of the array
    are stored in column order in the main memory?
    (ii) Repeat part (i) assuming the elements are stored in row order.

    Page 2 of 2

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