Design, Control and Analysis of A Fault Tolerant Soft-Switching DC-DC Converter For High Power High Voltage Applications

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2684832, IEEE
Transactions on Power Electronics
Design, Control and Analysis of a Fault Tolerant

Soft-Switching DC-DC Converter for High Power
High Voltage Applications
Tao Li, Leila Parsa, Senior Member IEEE
Dialog Semiconductor, Department of Electrical Engineering,
675 Campbell Technology Parkway Suite 150, University of California, Santa Cruz,
Campbell, CA 95008, USA Santa Cruz, CA 95064, USA
taoli.rpi@gmail.com leila@ieee.org
Corresponding author: Dr. Tao Li, 1850 Nantucket Circle Apt 348, Santa Clara, CA, 95054, Tel: 518-256-3968, Email:
taoli.rpi@gmail.com
Partially presented in APEC 2016, Long Beach, CA, March 20th-24th
Abstract— A modular isolated soft-switching DC-DC converter which can offer two levels of fault tolerance is proposed.
A typical application is the wind energy conversion system (WECS) used in offshore series-DC wind farm concept. The
converter consists of input-parallel-output-series (IPOS) connected modules. Each module is a full bridge DC-DC con-
verter with active rectifier, which can achieve zero voltage switching (ZVS) for all primary side switches and zero current
switching (ZCS) for all secondary side switches and diodes. Under normal operation, the converter is operated with
secondary phase-shifted modulation. When tolerable fault occurs in certain module, reconfiguration method ensures
uninterrupted operation for the system. Additionally, modular structure provides another level of fault tolerance. More
benefits of IPOS structure include reduced input current and output voltage of each module, module shedding capability,
reduced ripple content due to interleaving, intrinsic balancing and scalable control method. Both normal and faulty
operation are simulated and also verified by scaled-down prototype experiment.
Index Terms—DC-DC power converters, fault tolerance, zero current switching, zero voltage switching, interleaving.
0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2684832, IEEE
I. INTRODUCTION
Renewable energy research has received a lot of attention with the growing concern for challenges like global warming and
fossil fuel depletion. Wind energy is one of the most mature forms of renewable energy. Global cumulative installed wind capacity
passed 369 GW at the end of 2014, and is projected to reach 666 GW by 2019 [1]. Offshore wind farms generally enjoy stronger
and more consistent wind velocity, arouse less acoustic pollution concern, and are adjacent to major demand centers. Though
operational offshore wind generation is only about 12 GW, a total capacity of nearly 250 GW is announced globally [1], [2]. With
the increasing distance from wind farm to shore, traditional HVAC transmission system will suffer from substantial loss in cables.
Comparatively, HVDC transmission system would only have 50%-70% of cable loss [3]. Therefore HVDC solution may have
lower overall loss for remote wind farms. The overall economical break point is around 100 km. A major part of cost goes to the
offshore platforms, which are usually much costlier for HVDC than for HVAC systems [4]. One solution is the series-DC based
wind farm shown in Fig. 1 [5]–[13]. The output of permanent magnet synchronous generator (PMSG) is converted by WECS.
Then the DC outputs of WECS are series connected to reach HVDC voltage level. Each WECS can be installed locally at the wind
turbine, thus eliminating the need for substation platform.
Fig. 1. Series-DC wind farm
DC/DC converter is the key component in WECS as it needs to ensure continuous current flow in the HVDC line. Moreover,
fault tolerance is highly desired for DC-DC converter, especially for high power high voltage applications such as offshore wind
farm. One major reason for converter failure is semiconductor device malfunction, i.e. short circuit fault (SCF) and open circuit
fault (OCF) [14], [15]. SCF is usually caused by wrong gate voltage or intrinsic failure. SCF can lead to shoot-through fault and
consequently damage other parts of the system. Therefore in many commercially available drivers, the detection and protection
of SCF is a standard built-in feature [16]. An OCF may happen due to lifting of bonding wires, driver fault or SCF-induced IGBT
rupture. Unlike SCF, OCF typically will not cause abrupt system failure. Nevertheless, OCF will cause DC voltage offset, which
leads to reduced performance, transformer saturation, and higher voltage stress on healthy switches.
Fault tolerant control strategy usually includes three subtasks: fault detection, fault identification/location and reconfiguration
action [14]. In [15], fault diagnosis and protection methods are reviewed for SCF and gate driver induced OCF of IGBTs in
inverters. More recently, [17] categorizes converter fault tolerant techniques into switch-level, leg-level, module-level and system-
level. However, the surveys are focused on fault tolerant techniques developed for inverters. Many methods are not applicable to
DC-DC converters as information from Park’s transformation or space vectors are utilized. A non-isolated multilevel modular
capacitor-clamped DC-DC converter (MMCCC) and corresponding fault tolerant method is proposed in [18]. Redundant modules
in offline mode are required by the proposed method. Both SCF and OCF tolerance for a H-bridge with auxiliary leg and selector
cells (HBALSC) converter are achieved at the cost of many voltage/current sensors as well as one auxiliary leg [19]. Authors of
[20] proposed a fault tolerant strategy based on monitoring inductor current slope that can detect both SCF and OCF in less than
one switching cycle for simple boost converter. However, aforementioned converters are not suitable for high power application
such as series-DC wind farm. Fault detection method based on monitoring flying capacitor voltage of three-level parallel resonant
converter (PRC) is presented in [21]. Nevertheless, neither fault identification nor reconfiguration action is discussed. A general
fault detection and identification method for both SCF and OCF in most PWM converters is proposed in [14]. This method com-
pares the measured magnetic component voltage with the theoretical voltage calculated based on gate signals. However, as instan-
taneous values are used, switch turn-on delay and inevitable measurement delays may cause false alarm. The pulse shapes of DC-
link current are used to detect both SCF and OCF for a full bridge ZVS converter in [22]. The method does not require high-
resolution A/D converter, but cannot provide fault identification and reconfiguration.
Phase shift full bridge (PSFB) converter featuring inductive output filtering is found in many literature targeting series-DC
wind farm application [7], [9]. Pei et al. proposes an OCF tolerant strategy for the PSFB converter [16]. The averaged voltage
across transformer primary winding is used as fault indicator. After the fault is detected, phase shift is set at 0.5 in order to obtain
more information from transformer voltage level and pinpoint the OCF switch.
Comparatively, the DC/DC converter studied in this paper is based on IPOS connected secondary phase-shifted full bridge
(SPS-FB) converter. ZVS is achieved for all primary switches and ZCS is achieved for all secondary switches and diodes. Com-
pared to PSFB converter, the SPS-FB converter has larger soft-switching range, less circulating current and diode reverse recovery
current [23]–[25]. The main focus is to develop corresponding fault tolerant strategy using voltages across DC blocking capacitor
and lower switches. The converter can provide both switch-level and module-level fault tolerance. Switch-level fault tolerance
can deal with OCF of any switch and SCF at secondary switches, allowing the faulty module to operate at reduced performance.
When other faults occur, module-level tolerance can isolate the faulty module without disrupting the operation of healthy modules.
Soft-switching can be retained in post-fault operation. The fault induced output voltage/current dip can be compensated by healthy
modules without additional boosting stage.
The paper is organized as follows. Section II presents the topology of the proposed converter and its healthy operation. The
advantages of IPOS structure are also explained. Section III analyzes different fault scenarios and develops the fault detection,
identification and reconfiguration methods. Simulation and experimental setup, results and discussion are presented in section IV.
Finally, section V concludes this paper.
II. CONVERTER TOPOLOGY
The schematic drawing of proposed converter is shown in Fig. 2. Each building block is a SPS-FB converter that achieves
ZVS for primary switches and ZCS for secondary switches and diodes. The converter is suitable for series-DC wind farm appli-
cation. The converter takes a voltage input, which can be easily obtained from three-phase voltage source converter (VSC) or
diode rectifier bridge. The output is designed to be a current source and interface with current source converters (CSC). Thus,
there is no output capacitor which is prone to fault. Compared to voltage output configuration, the proposed scheme has advantages
such as simple structure and reliable short-circuit protection [7]. Fuse should be included at the input side of each module, which
is denoted as Fi in Fig. 2.
A. Operation principle of a single module
Only brief description of operation principle and modeling will be provided, since comprehensive analysis for a single mod-
ule has been covered in [24]. In steady state, the converter has twelve half-cycle symmetric operation modes. On primary side,
diagonal switches are operated in pairs, and complementary (with proper deadtime 𝑡𝑑 ) to the other pair. Secondary switches
have a duty ratio of 0.5 and are phase-shifted by ϕ compared to corresponding primary switch pairs. The key waveforms during
normal operation are shown in Fig. 3. If small soft transition modes during [t1, t4], [t5, t6], [t7, t10] and [t11, t0+Ts] are ignored,
where Ts is the switching cycle length, the module works as a full bridge isolated buck converter. By selecting appropriately
sized filters, input voltage Vin and output current Io can be considered constant over a switching cycle. Soft-switching is achieved
via clamped resonance between transformer leakage inductance Llk and resonant capacitor Cr. All secondary switches can be
zero current switched for entire load range. In contrast, the following inequality should be valid to ensure zero voltage switching
for primary switches:
2
Llk  Vin 
  (1)
Cr  I o 
Fig. 2. Proposed IPOS SPS-FB converter
Thus, the size of Cr is inversely proportional to ZVS range. DC capacitors can be used if resonant capacitors are placed across
primary switches instead of across transformer primary winding. Value of each DC capacitor should be Cr/2. Comparatively, Cb
is the DC blocking capacitor that protects transformer from saturation incurred by asymmetric gate signals, etc. Therefore, Cb
should be large enough that it would not influence normal operation.
Let us define duty ratio D as the overlap between primary and secondary switch gating signals, i.e.:
t7  t5
D . (2)
Ts
D is the ideal duty ratio when all resonant modes are ignored and the converter is treated as a full bridge isolated buck converter.
The effective duty ratio Deff is defined as:
M Vo I
Deff    in , (3)
2n 2nVin 2nI o
where M is the normalized voltage transfer ratio, and a bar dictates the average value over a switching cycle. Form input/output
energy balance, we have:
  L I  CV 
Ts Iin  nI o 2  DTs  lk o   r in  . (4)
  nVin  nI o 
Therefore, duty ratio loss can be calculated as:
2 Llk I o CrVin

Vin Io
Dloss  , (5)
2nTs
and effective duty ratio is:

Deff  D  Dloss  D . (6)
The inequality is found based on (1). As expected, Deff is smaller than D, indicating a slightly reduced output voltage compared to
hard switching case. For the parameters in (5), Vin, Llk and Cr are considered constant for a given design, whilst Io may vary with
the load level. Therefore Dloss increases with output current, and maximum duty ratio loss Dloss,max can be obtained at rated output
current. To facilitate the following discussion, two sets of design parameters are listed in Table I. Using the values from Table I,
Dloss,max is 0.0048 for full scale design and 0.009 for prototype design. The relationship of Dloss versus normalized output current
Fig. 3. Normal operation waveforms of one module
is plotted in Fig. 4. The lines are limited to the range that output current would satisfy the soft-switching constraint in (1). Full
scale design can retain ZVS until around 0.279 p.u. output current, corresponding to around 7.78% of rated power. Prototype
design can retain ZVS until around 0.708 p.u. output current, corresponding to around 50% rated power. The ZVS range is decided
by the selected prototype parameters in Table I, which are limited by available lab equipment.
Fig. 4. Duty ratio loss vs. output current
TABLE I. DESIGN PARAMETERS
Full scale design Prototype design

Power P 1.25 MW 3 kW
Input voltage Vin 1 kV 150 V
Output current Io 208 A 10 A
Leakage inductance Llk 30 µH 9 µH
Resonant capacitance Cr 100 nF 20 nF
Switching frequency fs 2 kHz 20 kHz
Transformer turns ratio n= N s N p 2.5 1
DC blocking capacitance Cb 1 mF 10 µF
Output filtering inductance Lo 50 mH 0.6 mH
Magnetizing inductance Lm 40 mH 1.2 mH
Rated phase shift ϕ0 0.09 0.12
Number of modules k 3 3
B. IPOS benefit
Let subscript “mod” stand for the corresponding quantity for single module. When k modules are connected in IPOS manner,
the following benefits are introduced:
1) Higher output voltage
Module output voltages are stacked to a higher value.
Vo  kVo , mod (7)
Vo , mod  2nDeff Vin

(8)
2) Lower input current
Input current is split between all modules, allowing lower current capability switches such as high voltage high power
MOSFETs to be used.
I in , mod  I in k (9)
3) Module shedding to improve efficiency
During light load condition, the converter can deliver power using only a fraction of all modules. Therefore, each deployed
module is operating closer to rated value, yielding a higher overall efficiency.
4) Reduced ripples
By properly interleaving the gate signals for each module, input current and output voltage ripples can be greatly reduced. As
1
a result, the required passive filters Cin and Lo sizes are also decreased. For this converter, a phase shift of should be inserted
2k
between adjacent modules to achieve symmetrical interleaving.
5) Intrinsic balancing
Unlike input series output series (ISOS) or input parallel output parallel (IPOP) converters, IPOS converter has intrinsic
balancing if common duty cycle is applied to all modules.
Input voltage, effective duty ratio and transformer turns ratio are the three elements that affect module output voltage. Mis-
matches in parameters will not unbalance the system. First, all the converter modules have the same effective input voltage
(Vin-2VCE(SAT)), where VCE(SAT) is collector-emitter saturation voltage of switch. All primary bridges are parallel connected and
Vin is the same. Due to the positive thermal coefficient of IGBTs, the difference in VCE(SAT) will be minimized when a tempera-
ture imbalance occurs due to the heating of the IGBT with the lower saturation voltage. Second, differences in resonant param-
eters Cr and Llk will create mismatch in Deff though all modules have the same output current Io and phase shift ϕ. Module with
smaller Cr or larger Llk has lower Deff, and therefore lower average output voltage and power. However, from Fig. 4, it is clear
that Dloss is a very small quantity, and the mismatch of Dloss would be even smaller. Therefore, the most significant cause of
output voltage mismatch is difference in turns ratio, which is also negligible with modern manufacturing technology [26].
If there is no delay in switching, average output voltage from each module can be found by (8). Mismatches in switch turn-
on/off delays do not introduce unbalance either. If all switches within certain module are delayed for the same amount of time,
the only consequence would be a less effective output interleaving: this is equivalent to changing the phase shift between mod-
ules. If switches within certain module are delayed differently, then small DC component could be generated in high frequency
link, which should be blocked by Cb.
6) Scalable control method
The control of the IPOS converter is similar to the control of a single module, regardless of k. Stability is guaranteed as 𝐼𝑜 and
𝑉𝑖𝑛 are the same for all modules.
C. Controller design
Output current rather than voltage is the control target in this converter. It is convenient to connect the outputs of several
converters sharing the same output current command in series to further increase the power rating. Transition modes should be
small enough with proper design parameters so that they can be ignored during control design process. For example, with the
values in Table I, the transition modes only take up 2.1% and 6.6% of the switching cycle in full scale and prototype design
respectively.
Given the symmetry of the IPOS structure, the average model of the converter would be the similar to that of a single module.
If constant resistive load is considered, following equation holds from volt-second balance of output inductor:
dio
Lo  io R  Vo  2kDeff nVin  k 1  2  nVin . (10)
dt
Therefore, the transfer function from the ϕ to io can be written as:
IO  s  2knVin
G i  s    . (11)
 s sLo  R
Conventional PI controller can be designed to regulate output current according to reference value. Actual phase shift com-
mand sent to modulator would be the difference between rated phase shift ϕ0 and the output of controller. The modulator then
generates the carrier waves accordingly. This simple control method delivers stable operation for both steady state and transient
under healthy conditions, which is later verified by simulation and experiment. The converter is immune to instabilities caused by
parameter mismatches as discussed previously. Unlike ISOS or IPOP topologies, inter-modular balancing control is not necessary.
To further demonstrate the advantages of proposed converter, the control-to-output relationship is plotted in Fig. 5. All data
points are obtained via detailed model that considers transition modes. Each line is a linear fit of data points of matching design.
Only load range that can achieve ZVS is shown. As can be seen, a linear relationship exists between control parameter ϕ and
output Io, which is valid for the entire soft-switching range. Therefore, output is less sensitive to slight variation of ϕ than dual
active bridge derived topologies. Hence resolution requirement for phase shift timer is reduced [27].
Fig. 5. Linear control-to-output relationship
III. FAULT TOLERANT CONTROL
In this section, the consequences of several fault scenarios are first summarized. Then the method for detecting fault and its
location is introduced. The proposed converter can provide two levels of fault tolerance. Several types of faults can be tolerated
intrinsically or via the switch-level tolerance. Other faults, including SCF of any primary switch can be tackled by module-level
tolerance. The proposed fault tolerant strategy requires only 3k voltage sensors for a converter consisting of k modules.
A. Fault scenarios analysis
In following discussion, assume the converter is composed of k identical modules and the fault occurs at module #i.
1) Scenario 1: OCF at secondary switch
Leakage inductance current may be disrupted if OCF occurs at one of the secondary switches while it is conducting. Output
current can still flow through other paths without interruption. Voltage stress across healthy switches will not be affected. How-
ever, average current through leakage inductance will no longer be zero during post-fault transient. Oscillation will occur in trans-
former voltage, with frequency determined by Lm and Cb. Maximum amplitude of transformer primary voltage will be approxi-
4Vin
mately . The oscillation will rapidly attenuate and transformer voltage will return to normal levels. Therefore, this scenario

does not require additional attention.
For module #i, power transfer during the half cycle when the OCF switch should have turned on is now stopped by the fault.
In steady state, this scenario can be regarded as setting ϕ=0.5 for half switching cycle. The total power transferred can still be
regulated by the phase shift of the other half cycle and other healthy modules. Based on (10):
 1
I o R  Vo   k   1  21  nVin , (12)
 2
where ϕ1 is post-fault phase shift under OCF at secondary switch. In order to sustain the same output current, the following
relationship should be valid:
4k0  1
1  . (13)
4k  2
Thus, if the calculated ϕ1 is still in the allowed range, output current can maintain pre-fault value [24]. However, maximum
power that can be transferred will decrease. Also, primary switches will no longer be zero voltage switched, which calls for
provisions in thermal design.
2) Scenario 2: SCF at secondary switch
If SCF occurs at one of the secondary switches, the impact on transformer voltage and peak voltage across other switches are
negligible. For module #i, power transfer during the half cycle when the SCF switch should have turned off is now at maximum
due to the fault. In steady state, the scenario can be regarded as setting ϕ=0 for half cycle. Total power transferred can still be
regulated by the phase shift of the other half cycle and other healthy modules. Based on (10):
k   2k  12 
Io R  Vo    nVin
, (14)
where ϕ2 is post-fault phase shift under SCF at secondary switch. In order to sustain the pre-fault output current:
2k
2  0 . (15)
2k  1
Typically, ϕ2 is still in the allowed range since the design value for rated phase shift ϕ0 is normally smaller than 0.25 in order to
get a reasonable voltage transfer ratio. The minimum power that can be transferred will increase but the converter can operate
safely at full load.
3) Scenario 3: OCF at primary switch
Unlike secondary switch faults, voltage applied to primary side will have a DC component when OCF occurs at one of the
primary switches. The converter can still function, but DC blocking capacitor Cbi will be biased. During steady state, the equiv-
alent input voltage of module #i is Vin/2:
 1
I o R  Vo   k   1  23  nVin (16)
 2
where ϕ3 is post-fault phase shift under OCF at primary switch. In order to maintain the same output current:
4k0  1
3  (17)
4k  2
As can be seen, ϕ3 equals ϕ1, which means the effect of OCF at one primary switch is similar to OCF at one secondary switch.
With careful design, ϕ1 and ϕ3 can stay within the allowed range. Power transfer capability will decrease, same as scenario 1. A
more severe problem is that the other switch on the same leg will have to withstand much higher voltage spikes, if the anti-
parallel diode of the faulty switch is also open. For example, if OCF occurs at S4i and D4i is also open, Cri voltage will no longer
be clamped by input voltage during [t9, t10]. Peak voltage across S3i will increase if the fault is not dealt with.
4) Scenario 4: SCF at primary switch
When SCF takes place at any of the primary switches, the converter is prone to a shoot-through fault, which calls for imme-
diate attention. The faulty module has to be isolated from the system to stop damage from spreading.
B. Fault detection and location
Since SCF usually leads to drastic consequence, the detection and protection method must be very fast. Therefore, SCF
protection circuit is usually incorporated in gate drivers for industrial applications [16]. The driver will turn off the switch once
potential SCF happens, resulting in an open circuit. Therefore, only OCF detection, location and reconfiguration method is
considered in this paper.
Based on the analysis of scenario 1 and 3, DC component of the voltage across Cb is a good indicator of OCF fault. The
detectable faults and resultant vCbi behaviors are summarized in Table II. During normal operation, only minor DC bias will exist
in vCb due to asymmetrical gate signals, etc. When OCF occurs at module #i, vCbi will deviate from zero. From Table II, it is
obvious that monitoring vCbi alone cannot provide exact fault location. Thus, average voltages across the lower primary switches,
i.e. vS2i and vS4i are also sensed to obtain further information about the fault.
If OCF occurs at one of the lower primary switches, then the corresponding sensor output will drop. If OCF occurs at one of
the upper primary switches, then the sensor across the lower switch on the same leg will have higher output. Lastly, if OCF
occurs at one of the secondary switches, then none of the outputs of switch voltage sensors will be affected. The fault detection
and location method is shown in Fig. 6. For example, assume S4i suddenly suffers from OCF. Then vCbi will drop and average
voltage across S4i will increase beyond normal. Now the fault can be identified as S4i OCF, but not S1i OCF. Once the fault is
detected and located, the converter can be reconfigured, as will be described in next subsection.
TABLE II. DETECTABLE FAULTS AND CORRESPONDING VCBI BEHAVIOR
OCF fault vCbi

S1i or S4i Drop
S2i or S3i Rise
S5i Oscillate starting from negative half cycle
S6i Oscillate starting from positive half cycle
Fault detection and

location
vcbi
Rise above Drop below

threshold threshold
vcbi value
vS2i vS4i ~0 vS2i vS4i
OK
Yes Yes
S2i OCF vS2i too high? vS2i too low? S1i OCF
No No
Reconfigure Reconfigure
Yes Yes
S3i OCF vS4i too low? vS4i too high? S4i OCF
Reconfigure No No Reconfigure
S6i OCF S5i OCF
Fig. 6. Flow chart of fault detection and location method
C. Reconfiguration method
Once OCF at primary switch is located, then the signal for the faulty switch will be set to low. The switch on the same leg, as
well as all secondary switches will be turned on permanently. The gate signals for primary switches on the other leg will remain
unchanged. For example, once OCF at S4i is identified, gate signal for S4i will be set to low, whilst gate signals for S3i, S5i and S6i
will be high permanently. Gate signals for S1i and S2i will remain unchanged. Then the faulty module will essentially be reconfig-
ured into an asymmetric half bridge (AHB) converter operating in open loop, as shown in Fig. 7. The duty ratios of S1i and S2i
remain at around 50% (with appropriate deadtime), transferring as much power as possible [28]. After the reconfiguration, the
switches on the healthy leg, namely S1i and S2i will still remain zero voltage switched. Faults at other primary switches can be
detected, located and tolerated in a similar manner. If the fault is located at secondary switches, then according to previous analysis,
no actions need to be taken.
Fig. 7. Equivalent topology after S4i OCF and reconfiguration
If non-tolerable faults (SCF at primary switches) happen, the modular structure provides an additional level of fault tolerance.
If gate driver has built-in SCF protection, then it will automatically block all gate signals to SCF module. Otherwise, fuse will first
disconnect the input side of the faulty module. Then SCF module will be securely bypassed by blocking all its gate signals when
both average voltages across both vS2i and vS4i have dropped below certain threshold. Output current can freewheel through the
1
diode leg formed by D7i and D8i, assuming module #i is bypassed. Phase shift between healthy modules is adjusted to to
2( k  1)
maintain symmetrical interleaving.
IV. SIMULATION AND EXPERIMENT RESULTS

In this section, simulation and experiment results are presented to validate previous analysis. Pure resistive load is used in both
simulation and experiment. Therefore when fault happens and the power transfer capability is severely impaired, to maintain same
output current level will not be possible. On the other hand, if output is connected to constant current load, output voltage will
vary freely with input power.
Fig. 8. Output current step response and fault tolerant control
A. Simulation validation
Simulations are carried out in PLECS for both sets of parameters listed in Table I. For simplicity, only results for full scale
design are shown in Fig. 8. The simulation starts with zero initial conditions and current reference iref = 208 A at t= 0. At t= 10
ms, iref steps to 104 A and at t=20 ms it steps back to 208 A. The output current keeps tracking reference value in approximately
2 ms. At t= 30 ms, a timed relay switch is used to imitate S43 OCF. The fault is detected and located in approximately 2.1 ms,
when reconfiguration method is applied. After the reconfiguration, output current settles at around 200 A despite the reference
value. This indicates post-fault converter is already operating at maximum capacity as ϕ has reached its lower limit. At t=40 ms,
module #3 is bypassed and Io gradually drops to around 160 A, approximately 77% of reference value.
B. Experiment results
A prototype has been constructed with parameters listed in second column of Table I. The design purpose is quick concept
validation so the implementation has not been optimized for volume nor efficiency. Hardware-in-the-loop (HIL) fast prototyping
method is used in development process. First, control system is set up in LabVIEW and converter circuit model is set up in Mul-
tisim. Co-simulation between LabVIEW and Multisim is conducted to evaluate the control performance. The verified control is
then implemented in real time (RT) controller cRIO-9082 using LabVIEW. The cRIO is configured to FPGA interface mode,
allowing full access to its embedded FPGA chip. Both levels of fault tolerant control and user interface are realized in RT oper-
ating system, while SPS modulator and ADC are implemented on the FPGA. The power stage of the prototype is shown in Fig.
9. The components used in prototype construction are listed in Table III.
Since IGBT will be the choice of component in full scale design, it is also used in the prototype. Therefore, 1.2kV 50A IGBT
modules are used due to their availability. The efficiency measured at different load and input conditions are summarized in Fig.
Fig. 9. Prototype converter consisting of 3 modules
TABLE III. PROTOTYPE COMPONENT LIST
Component Part No./Description

Switches S1i~S6i Powerex CM50DU-24F, 1200 V/50 A IGBT
Diode D5i~D8i IXYS DSEI2x61-12B, 1200 V/52 A fast recovery
Cbi Vishay MMKP383 double metallized
polypropylene film capacitors, 750 VDC
Cin Mallory electrolytic capacitor, 450 VDC
Gate driver Concept 6SD106EI, 6-pack driver
Voltage sensor LEM LV-25, Hall effect sensor
Current sensor LEM LA-55P, Hall effect sensor
Transformer Core: E-E cores of Metglass AMCC50
Wire: MWS 60/36, 5 branches of 47 turns each
Output inductor Implemtented by two identical 0.3 mH inductors
Cores: E-E cores of Magnetics 00K5528E060
Wire: MWS 125/40, 4 branches of 40 turns each
Real time controller NI cRIO-9082 with 2*NI 9401, NI 9205, NI 9263
10. At 150 V input and 10.21 A load, efficiency is 87.9% with 3 modules operating. It is to be noted that voltage drops across
IGBT and diode are relatively high at prototype voltage and current level. Out of the total loss of 432 W, the conduction loss of
semiconductors are estimated to be 211 W based on datasheets. The prototype efficiency will be greatly improved using
MOSFETs as switches. As for full scale design, the efficiency is estimated to be around of 97.51% at full load. Moreover, mod-
ule shedding can improve efficiency at light load condition, as shown in Fig. 10.
Steady state operation under healthy condition is verified. Gate driver outputs of S13 and S53 are shown in channel 1 and 2 of
Fig. 11. Transformer secondary voltage vs3 and current iLlk3 shown in channel 3 and 4 both match the theoretical steady state
waveforms in Fig. 3. ZVS of primary switch and ZCS of secondary switch during healthy operation at rated values are demon-
strated in Fig. 12. Since the gate signals of each module is phase shifted by 1/6 switching cycle, output current has very small
ripple, as shown in Fig. 13. Then closed-loop experiment is performed. In the experiment, current reference iref steps from 5 A to
10 A. Current reference command, PI controller output and converter output current are plotted in Fig. 14. Output current tracks
reference value in approximately 400µs. In steady state, PI output is approximately zero, therefore the actual phase shift between
S1i and S5i is just ϕ0.
Fig. 11. S 13
Steady state operation (CH1: vGE S 53
, CH2: vGE , CH3: v s 3 , CH4:
Fig. 10. Efficiency measurement
iLlk 3 )
S 13 S 53
Fig. 12. Soft switching during healthy operation (CH1: vGE , CH2: vGE ,
Fig. 13. S 41
Interleaving (CH1: vGE S 42
, CH2: vGE S 43
, CH3: vGE , CH4: io )
CH3: vS13 , CH4: iS 53 )
Next, switch-level fault tolerant control is tested and presented in Fig. 15. S43 OCF is triggered by blocking its gate signal. Due
to limited number of oscilloscope channels, the signals of fault triggering and fault detection based on vCb3 are combined and
shown in channel 1. The rising edge stands for the moment of fault triggering, and the falling edge stands for the moment of fault
detection. Channel 2 shows the moment that fault is located is indicated. Sensor readings of vCb3, vS43 are filtered and shown in
channel 3 and 4 with their corresponding thresholds. After the fault, vCb3 decreases as expected. The fault is detected and located
in 160 µs, and the reconfiguration method is activated. In Fig. 16, probe-measured vCb3 and io are shown in channel 3 and 4. Output
current is supported by healthy modules and the dip is very small. According to measurement, pre-fault io value is 10.35 A, and
post-fault value is 9.87A. After the reconfiguration, the switches on healthy leg, i.e. S13 and S23 are still zero voltage switched, as
shown in Fig. 17. In Fig. 18, DC blocking capacitor voltage of healthy module #2 is shown in channel 2. As can be seen, neither
fault nor reconfiguration method will disrupt the operation of healthy modules or trigger false positive in other modules. Experi-
ment results of secondary switch OCF is shown in Fig. 19. Now, S53 OCF is triggered by blocking its gate signal. Fault can be
detected by vCb3 as shown in channel 1, but average voltage across S23 and S43 are not affected. Therefore, the controller decides
that it has encountered a secondary OCF and will not deploy any reconfiguration method. As can be seen, DC blocking capacitor
Fig. 14. Closed loop output current step response (CH1: PI output, CH2: Fig. 15. Primary switch OCF (CH1: Fault triggered/detected; CH2: fault
iref , CH4: io ) located; CH3: vCb3 processed; CH4: vS 43 processed)
Fig. 16. Primary switch OCF (CH1: Fault triggered/detected; CH2: fault Fig. 17. S 13
Post-fault zero voltage switching (CH2: vGE ; CH3: vS13 )
located; CH3: vCb3 ; CH4: io )
Fig. 18. Fault effect on other modules (CH1: Fault triggered/detected; Fig. 19. Secondary switch OCF (CH1: Fault triggered/detected; CH2:
CH2: vCb 2 ; CH3: vCb3 ; CH4: io ) vCb 2 ; CH3: vCb3 ; CH4: io )
Fig. 20. Module-level tolerance (CH3: vCb3 ,CH4: io )
voltages of other modules are not affected. The output current is about 9.92 A in post-fault steady state, and ripple is still below
10%. Finally, the response of vCb3 and io when module-level tolerant control is applied are shown in Fig. 20. When module #3 is
bypassed, output current is freewheeling through D73 and D83. Phase shift of module #1 and #2 reaches minimum, and output
current drops to 8.91A.
V. CONCLUSION
In this paper, a novel fault tolerant isolated DC/DC converter suitable for series-DC offshore wind farm application is proposed.
The converter is controlled by secondary phase shift modulation. ZVS is achieved for all primary switches and ZCS is achieved
for all secondary switches and diodes during healthy operation. The converter has relatively large soft-switching range and linear
control-to-output relationship.
Fault detection and location method based on monitoring DC blocking capacitor voltage and lower switch voltage is proposed.
Switch-level tolerance not only prevents the fault from spreading but also allows full utilization of healthy components. The
functioning switches within the faulty module still remain soft switched. Additionally, module-level tolerance can isolate a module
with non-tolerable fault from the system. Output current can freewheel through the diode leg without any disruption. Simulation
and HIL experiment results both verify the proposed converter operation and effectiveness of fault tolerant control.
ACKNOWLEDGEMENT
This work was supported primarily by the Engineering Research Center Program of the National Science Foundation and the
Department of Energy under NSF Award Number EEC-1041877 and the CURENT Industry Partnership Program.
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Design, Control and Analysis of A Fault Tolerant Soft-Switching DC-DC Converter For High Power High Voltage Applications

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This article has been accepted for publication in a future issue of this journal, but has not been

Design, Control and Analysis of a Fault Tolerant

operation are simulated and also verified by scaled-down prototype experiment.

turbine, thus eliminating the need for substation platform.

Fig. 1. Series-DC wind farm

modules without additional boosting stage.

Finally, section V concludes this paper.

II. CONVERTER TOPOLOGY

A. Operation principle of a single module

for primary switches:

Fig. 2. Proposed IPOS SPS-FB converter

should be large enough that it would not influence normal operation.

The effective duty ratio Deff is defined as:

energy balance, we have:

Therefore, duty ratio loss can be calculated as:

and effective duty ratio is:

Fig. 3. Normal operation waveforms of one module

Fig. 4. Duty ratio loss vs. output current

TABLE I. DESIGN PARAMETERS

Full scale design Prototype design

the following benefits are introduced:

1) Higher output voltage

Module output voltages are stacked to a higher value.

Vo  kVo , mod (7)

Vo , mod  2nDeff Vin

2) Lower input current

3) Module shedding to improve efficiency

module is operating closer to rated value, yielding a higher overall efficiency.

between adjacent modules to achieve symmetrical interleaving.

balancing if common duty cycle is applied to all modules.

link, which should be blocked by Cb.

6) Scalable control method

𝑉𝑖𝑛 are the same for all modules.

Therefore, the transfer function from the ϕ to io can be written as:

Fig. 5. Linear control-to-output relationship

III. FAULT TOLERANT CONTROL

A. Fault scenarios analysis

1) Scenario 1: OCF at secondary switch

does not require additional attention.

relationship should be valid:

provisions in thermal design.

2) Scenario 2: SCF at secondary switch

safely at full load.

3) Scenario 3: OCF at primary switch

alent input voltage of module #i is Vin/2:

4) Scenario 4: SCF at primary switch

B. Fault detection and location

considered in this paper.

TABLE II. DETECTABLE FAULTS AND CORRESPONDING VCBI BEHAVIOR

OCF fault vCbi

Fault detection and

Rise above Drop below

vS2i vS4i ~0 vS2i vS4i

S6i OCF S5i OCF

Fig. 6. Flow chart of fault detection and location method

no actions need to be taken.

Fig. 7. Equivalent topology after S4i OCF and reconfiguration

maintain symmetrical interleaving.