Design of High Performance 1-Bit Hybrid Adder
Design of High Performance 1-Bit Hybrid Adder
Design of High Performance 1-Bit Hybrid Adder
CERTIFICATE
This is to certify that the project report entitled Design of high performance 1-bit
Hybrid Adder (VLSI) being submitted by
External Examiner
ACKNOWLEDGEMENT
This project is an acknowledgement to the inspiration, drive and technical assistance
contributed by many individuals. This project would have never seen light of this day without the
help and guidance we have received. We would like to express our gratitude to all the people
behind the screen who helped us to transform an idea into a real application.
It’s our privilege and pleasure to express our profound sense of gratitude to Amritha Sajja,
Guide Department of ECE for her guidance throughout this dissertation work.
BY
LIKHITHA KACHAM 18H61A0428
VASANTH MEKALA 18H61A0436
SRUJAN PATLOLLA 18H61A0444
DECLARATION
We hereby declare that the result embodied in this project report entitled “Design of
high performance 1-bit Hybrid Adder(VLSI)” is carried out by us during the year
2021-2022 for the partial fulfillment of the award of Bachelor of Technology in
Electronics and Communication Engineering, from ANURAG GROUP OF
INSTITUTION. We have not submitted this project report to any other Universities /
Institute for the award of any degree.
BY
ABSTRACT
Technology evolution increased the demand for high performance and energy
efficient circuits.To meet the design criteria for the modern period, circuit designers
are often facing a dilemma to make trade-offs among area, delay and power
consumption.Along with number of devices used in the circuit should be less and
circuit should occupy less area, consume less power is the major challenge for the
designers.
Basic circuit used in most of the circuit designs is an ADDER. In digital addition,Full
Adder works as the most important elementary block.The improved version of the full
adder design brings overall improvement in the arithmetic units.
This project is an 18-transistor full adder cell based on the full swing hybrid
logic.Hybrid Adder is designed using metal oxide semiconductors(CMOS),Pass
Transistors,Transistor gates.This circuit is designed using Cadence tool with 90nm
technology.Further the proposed adder results of propagation delay is compared with
existing Adder circuits.
Major aim to design this circuit is to enhance the performance of the circuit by
decreasing its propagation delay.
CHAPTER 1
INTRODUCTION
1.1 Introduction:
The addition operation plays the major role because several complex operations are
dependent on addition.In digital addition,full adder works as the most important
elementary building block.Despite having several existing full adder designs, the urge
for new designs continues to address the increasing throughput requirements.
Each circuit has its own specialization like; a circuit can increase the performance and
other can decrease the usage of area etc.A hybrid Adder which consists of different
elements which altogether works as an adder is preferred than initial adder circuit
design to make the adder reach the requirements.
The circuit designed in this project used to increase the performance of the adder by
decreasing its delay. Also few parameters of the adder are compared with already
existing Hybrid Adders.
CHAPTER 2
LITERATURE SURVEY
On the basis of output voltage, full adder circuits are classified into two categories:
Full swing and non full swing. Full swing circuits have output voltage levels equal to
Vdd or gnd without involving threshold voltage drop issue. Non full swing circuits
considers threshold voltage and suffers from threshold voltage drop.
On the basis of logic style, full adder circuits are classified into two categories:
Single logic and hybrid logic. Single logic circuits uses only one logic style whereas
hybrid logic circuits uses at least two logic styles. Pass transistor based single logic
full adder is the oldest circuit of all. But the drawback in this design is its suffers
threshold voltage drop. To overcome this complementary symmetry CMOS(CCMOS)
is designed. But in CCMOS large number of transistors are used which leads to high
area utilization and it consists of high input impedance which results in slower
working of the circuit.
So instead of using single logic circuits, now designers are interested to design the
hybrid circuits of full adder. Main aim to design hybrid logic circuit is to optimize the
above mentioned drawbacks and to bring better performance. Full adder designed
using the combination of CCMOS and Pass Transistors enhanced the signal strength
but it also resulted in speed issue.
To overcome all the above issues, full adder structure is formed using XOR-XNOR
circuit simultaneously. But usage of this circuits should be well enough to avoid
signal delay, slower generation of signal. To reduce delays, parallel connection of
XOR-XNOR connection is suitable. But this circuit involves more usage of transistors
which may result in high input impedance.
In order to avoid all these, the circuit we designed consists of transmission gates and
pass transistors. This circuit is constructed in a way to perform XOR and XNOR
operations. This circuit involves at least one full swing path which results to avoid
voltage degradation phenomenon. Circuit also involves parallel combination to reduce
the delay and this circuit does not involve any feedback connection which results in
reduction of delay.
CHAPTER 3
SOFTWARE AND HARDWARE REQUIREMENTS
3.1.1 INTRODUCTION:
This section will guide through all the steps to run Cadence remotely over SSH
through a Linux terminal.The following steps are:
Step 1: Start a Linux session in the computer Lab PLT-0105 and logon to your Linux
account using your U. Laval IDUL/NIP.
Step 2: Open a new terminal window. Select Applications-> System Tools -> terminal
and press the Enter key. If you get the following message: “Are you sure you want to
continue connecting (yes/no)?” type yes and then press the Enter key.
Step 4: Enter your password and press the Enter key. You should now be connected to
cmcnode-1 over SSH.
Step 5: Create a working directory by typing the following commands into the
terminal:
bash-4.0$ cd Labs
Step 6: For Launching Cadence, type “startCds” in the terminal window and press the
Enter key. From the cmc_kits_view pop-up window, choose the180-nm technology or
90nm technology or any other technology kit and click run.
The Command Interpreter Window (CIW) is opening. The CIW gives an access to
the multiple tools of the Cadence suite.
A library is a collection of cells, such as NOT, AND, NAND, etc. These cells contain
several views, including “schematic”, “layout”, “extracted” and “symbol”.
Open the Library manager: In the CIW window, go to tools -> library manager. The
library manager window opens, has shown in Fig. 3. The left column is listing the
available libraries for the current kit. The “analogLib” and the “cmosp18” libraries
contain all the necessary components to complete this Lab. The center column is
listing the available cells for each library. A cell is a specific building block i.e. a
circuit that belongs to a specific library. The right column is listing the several
available views of each cell (extracted, layout, schematic, etc.).
Extracted view: contains a representation of the netlist that has been extracted
from a layout view.
Layout view: contains the mask representations of the silicon devices and wiring.
Step 1: In the Library manager, go to file -> new library. Then, type in the name of
the new library, for example Label1, and click OK.
Step 3: In the new pop-up window, select “cmosp18” as the technology file, and then
click OK.
This is to know,how to create a simple schematic with the Schematic editor and how
to simulate a digital circuit using Spectre. It also explains how to simulate the
characteristics of a CMOS circuit and how to obtain its parameters. In order to work
efficiently with the Schematic editor, there are few direct keys for the most frequently
used commands as shown in table.
Step 9: Make sure that your schematic is identical and press “x” to save your work, or
alternatively, select design -> save and check.
Step 2: Choose a model file in order to simulate the circuit with the right parameters.
In the Analog design environment window, go to the Setup menu, select “model
library”, and type in
CMC/kits/cmosp18.5.2/models/spectre/spectre445_mixed/mm018.csc
Step 3: Type in “tt” in the section box and click the add button. Then, click OK
before closing the windows.
Step 4: Go to session -> options and choose AWD for waveform tool. Analog
waveform display (AWD) is a waveform display tool that is included with the spectre
simulator in order to print simulation results.
Step 5: Go to the Analyses menu, select Analyses -> choose. In the Choosing
Analyses window, click dc at Analysis and select save DC operating point. Click OK.
Step 6: Click the traffic green light button to run the simulation. Messages will appear
in the CIW window indicating that the simulation has completed successfully .
The major aim of this hybrid full adder circuit is to decrease the propagation delay of
the circuit. The actual design of the circuit using Cadence tool is as follows:
The simulation waveforms of the “sum” and “carry” circuits are as follows :
Delay simulation waveform is as follows:
2.
252.3ps
Partha.Bhattacharyya-Performance
Analysis of a Low-Power High-
Speed Hybrid 1-bit Full Adder
Circuit.
Hybrid Adder using 18 transistors which are of pass transistors, transmission gates
and cmos transistors is successfully designed using cadence tool. The respective sum
and carry waves are also simulated using cadence tool. Propagation delay is also
calculated and the result is compared with few existing designs and the results are
tabulated.
FUTURE SCOPE:
This Hybrid circuit can be used in any logic circuit which mostly concentrates on less
propagation delay which results in high performance of the circuit.
REFERENCES
3.Hasan, M., et al.: Comprehensive study of 1‐bit full adder cells: review,performance
comparison and scalability analysis. SN Applied Sciences.3(6), 644 (2021).
4.Kandpal, J., et al.: High‐speed hybrid‐logic full adder using high‐performance 10‐T
XOR–XNOR cell. IEEE Trans. Very Large ScaleIntegr. Syst. 28(6), 1413–1422
(2020).
5.Sharma, A., Sohal, A., Kaur, H.J.: Sleepy CMOS‐sleepy stack (SC‐SS): a novel
high speed, area and power efcient technique for VLSI circuit design. J. Circ.
Syst.Comput. 28(12) (2019).
6.Hasan, M., et al.: Gate diffusion input technique based full swing and scalable 1‐bit
hybrid full adder for high performance applications. Eng.Sci. Technol. An Int. J.
23(6), 1364–1373 (2020).