Ces User

Constraint Editor System™ (CES) User’s
Manual
Software Version EE 7.9.4
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Table of Contents
Chapter 1
CES Quick References and Work Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Quick Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Quick Reference - CES Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Quick Reference - CES GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
File Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
View Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Filters Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Quick Reference - CES Constraint Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Trace and Via Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Clearances Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Z-Axis Clearances Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Nets Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Parts Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Noise Rules Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CES Work Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Schematic-Design Work Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PCB-Layout Work Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 2
CES Overview and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
CES Constraint-Driven Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
CES Constraint-Driven Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Concurrent Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Creating PCB Rule Areas Through Rule-Area Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Creating Net Classes to Group Rule-Area Nets More Extensively . . . . . . . . . . . . . . . . . . 48
Creating Constraint Classes to Group and Define Net Constraints . . . . . . . . . . . . . . . . . . 49
Verifying Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Verifying Simulated Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Before You Begin Using CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Differential Pairs Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Importing a Layout Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Importing a 2005.x Ces.prefs File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DxDesigner-CES-Expedition PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Keyin Netlist-CES-Expedition PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Expedition TeamPCB and XtremePCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Understanding Electrical Nets and Physical Nets in CES . . . . . . . . . . . . . . . . . . . . . . . . . 53
Constraint Editor System (CES) Users Manual, EE 7.9.4 3

Table of Contents
Automatically Recognized Topologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Electrical Nets Defined Through a Package With More Than Two Pins . . . . . . . . . . . . . . 55
Starting and Exiting From CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Starting CES in Standalone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Viewing Constraint Database Log Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Cross Probing Between Design Systems and CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Cross Probing From the Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Setting Up CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Specifying Design Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Setting Display Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Setting General Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Setting Units for the CES Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Specifying Other Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Reusing Settings in External Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Modifying Simulation Settings and Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Modifying Simulation Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Modifying Simulation Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Customizing the Display of CES Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Folder Location of ces.ini Customization File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Customizing CES Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Modifying Toolbars to Create Custom Sets of Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Creating New Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Specifying General Toolbar Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Resetting a Toolbar to the Default Grouping of Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Customizing the Constraint Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Creating Custom Spreadsheet Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Sharing Your Constraint Set With Other Users . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Associating user.cns Files With a Mentor Software Release . . . . . . . . . . . . . . . . . . . . . . . 91
Adding Custom Menu Selections to the Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Customizing Command Shortcut Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Default Keyboard Shortcuts Provided With CES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Selecting or Creating Valor NPI Design Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Sharing Valor NPI Design Centers Among Team Members . . . . . . . . . . . . . . . . . . . . . . . 96
Chapter 3
CES Constraint Spreadsheet Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Defining Constraints With CES Spreadsheets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Understanding Constraint Hierarchy and Overrides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Organization of CES Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Selecting CES Spreadsheet Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Identifying Spreadsheet Icons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Resizing Spreadsheet Columns and Rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Zooming the Display of Spreadsheet Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Expanding and Collapsing Spreadsheet Rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Sorting Constraint Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Deleting Constraint Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Copying and Pasting Constraint Values Between Separate Invocations of CES . . . . . . . . 113
Searching for Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4 Constraint Editor System (CES) Users Manual, EE 7.9.4

Table of Contents
Filtering Spreadsheet Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Filtering the CES Spreadsheet by Row Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Resetting the Spreadsheet to its Default View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Creating Constraint Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Working Concurrently With Other Users . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Adding Comments to Your Constraint Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Viewing Constraint Reference Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Viewing Cell Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Viewing Design Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Checking Constraints and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Correcting CES Diagnostics Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Validating Constraints Against PCB Actuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Updating Actuals Displayed in CES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Clearing Actuals From the CES Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Highlighting Constraint Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Sharing PCB Actuals With Front-End CES Sessions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Viewing All Constraint Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Updating Electrical Net Data and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Resolving Existing Constraint Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Painting Rules to Reuse Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Rolling Back and Undoing Constraint Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Supported Undo/Redo Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Viewing and Reverting to Parent Cell Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Saving Constraint Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Chapter 4
Net Class Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Creating Net Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Creating Net Class Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Adding Nets to a Net Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Adding Power Nets to a Net Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Creating a Net Class From an Existing Net Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Deleting Net Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Chapter 5
Constraint Class Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Creating Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Creating Constraint Class Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Adding Nets to a Constraint Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Defining Bus Constraint Classes Automatically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Determining Nets That Comprise a Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Creating a Constraint Class From an Existing Constraint Class . . . . . . . . . . . . . . . . . . . . . . 151
Deleting Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Chapter 6
Rule-Area Scheme Creation and Clearance Rule Definition . . . . . . . . . . . . . . . . . . . . . . . 153
Creating Rule Area Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
(Minimum) Scheme Clearances and Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table of Contents
Specifying Trace and Via Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Defining Via Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Creating Clearance Rule Sets for Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Defining Embedded Resistor Clearance Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Defining SMD Clearance Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Assigning Class-To-Class Clearance Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Assigning Z-Axis Class-To-Class Clearance Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Assigning Package Clearance Type Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Determining Package Sides and Ends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Specifying General Clearance Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Copying, Renaming, and Deleting Rule-Area Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Resetting Clearance Rules to the Master Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Chapter 7
Net Constraint Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Specifying General Net Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Specifying Topologies for Nets and Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
The Difference Between From-Tos and Pin Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Handling Multiple Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Differential-Pair Topology Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Changing Topology Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Creating Pin Sets to Construct Advanced Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Overriding Trace Width Constraints for From-Tos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Defining Pin Pairs for Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Including Internal Component-Pin Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Defining Discrete Component Pin Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Specifying Delay Rules for Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Defining a Routing Tolerance for All Nets Within a Constraint Class . . . . . . . . . . . . . . . 193
Specifying Maximum Length as a Percentage Above Manhattan Length . . . . . . . . . . . . . 193
Net Delay Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Matching Delay Rules Among Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Matching Delay Tolerance at the Constraint Class Level . . . . . . . . . . . . . . . . . . . . . . . . . 197
Defining Formulas to Create Net Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Including Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Entering Multiple Formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Solving Formulas to Check for Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Complex Formula Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Creating Constants and Variables for Delay Rules and Formulas. . . . . . . . . . . . . . . . . . . . . 203
Using Free Variables to Constrain Delay by Group Only . . . . . . . . . . . . . . . . . . . . . . . . . 203
Specifying Simulated Delay Rules for Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Signal Edge Rates and Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Matching Simulated Delay Rules Among Nets or Constraint Classes . . . . . . . . . . . . . . . . 207
Defining Overshoot and Ringback Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Understanding Static and Dynamic Overshoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Modifying I/O Designer FPGA Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Defining Constraints for Single-Pin Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table of Contents
Chapter 8
Parallelism and Crosstalk Rule Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Determining When to Use Parallelism or Crosstalk Rules . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Parallelism Rules Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Defining Parallelism Rules for Stack-Up Layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Parallelism Rule Definition Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Assigning Parallelism Rules to Nets and Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . 218
Navigating to Assigned Parallelism Rules From the Nets Page . . . . . . . . . . . . . . . . . . . . . 220
Defining Crosstalk Rules for Nets and Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Chapter 9
Differential Pair Creation and Pair Rule Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Defining Differential Pairs Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Defining Differential Pairs Automatically. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
IBIS Model [Diff_Pin] Section Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Assigning Rules to Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Differential-Pair Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Chapter 10
Constraint Template Creation and Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Creating Constraint Templates to Capture Net Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . 231
Developing Libraries of Constraint Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Constraints and Values Stored With Each Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Applying Constraint Templates to Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Applying Constraint Templates From the Nets Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Matching Devices More Precisely When Applying Constraint Templates . . . . . . . . . . . . 236
Modifying Pin Matching for an Applied Constraint Template. . . . . . . . . . . . . . . . . . . . . . 237
Updating a Net With Constraint Template Changes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Reusing Constraint Templates in External Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Chapter 11
CES Constraints Export and Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Exporting CES Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Exporting Constraints in Encrypted XML Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Exporting Constraints in Encrypted CSV Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Exporting Constraints in Encrypted ASCII Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Decrypting and Encrypting Exported Constraint Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Importing CES Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Importing Constraints in Encrypted XML Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Importing Constraints in Encrypted CSV Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Working With the CSV Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Chapter 12
Stackup Display and Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Viewing or Modifying Stackup Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Correlating Layer Names Among Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Stackup Editing Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Table of Contents
Chapter 13
Part-Model Assignment Verification and Part Constraints Definition . . . . . . . . . . . . . . . 261
IBIS Models Delivered With CES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Specifying Available Part Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Specifying Model Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Specifying Individual Model Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Understanding Relative Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Verifying Default Model Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Automatic Assignment of IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
IBIS Models or Technology Models? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Assigning Models to Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Updating Part Model Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Reloading Model Directories and Individual Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Overriding IBIS Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Defining Thermal Constraints for Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Importing Pin Package Length Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Example PinPkgLengths.txt File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Chapter 14
Signal Integrity Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Sending Nets to HyperLynx LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Updating CES Dynamically With HyperLynx LineSim Changes . . . . . . . . . . . . . . . . . . . 274
Sending Nets to ICX Pro Explorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Creating Constraint Templates to Capture Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . 276
Updating CES With Constraint Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Chapter 15
Design Tool Update. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Managing Design Changes Between Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Communicating Design Changes Between Schematic and Layout . . . . . . . . . . . . . . . . . . 281
CES Synchronization of Constraint Databases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Resolving Schematic Constraint Conflicts Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Viewing Constraint Resolution Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Synchronizing Constraint Data Between Schematics and CES. . . . . . . . . . . . . . . . . . . . . . . 286
Sending Schematic Data to Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Sending DxDesigner Schematic Data to Expedition PCB . . . . . . . . . . . . . . . . . . . . . . . . . 286
Synchronizing Constraint Data Between CES and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Sending Layout Data to Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Appendix A
CES Constraint Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Using This Constraint Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Supported Design Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Trace and Via Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Via Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Table of Contents
Trace Width Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Trace Width Typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Trace Width Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Typical Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Differential Typical Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Differential Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Clearances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Trace To Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Trace To Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Trace To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Trace To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Trace To SMD Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Pad To Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Pad To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Pad To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Via To Via. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Via To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Via To SMD Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Plane To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Embedded Resistor To Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Embedded Resistor To Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Embedded Resistor To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Embedded Resistor To Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
EP Mask To Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
EP Mask To Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
EP Mask To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
EP Mask To Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Z-Axis Clearances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Trace To Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Trace To Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Trace To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Trace To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Trace To SMD Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Hierarchical Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Net Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Template Name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Template Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Topology Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Topology Ordered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Stub Length Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
# Vias Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Max Restricted Layer Length External. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Table of Contents
Max Restricted Layer Length Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

From To Constraints Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
From To Constraints Trace Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
From To Constraints Z0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Length or TOF Delay Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Length or TOF Delay Min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Length or TOF Delay Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Length or TOF Delay Manhattan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Length or TOF Delay Min Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Length or TOF Delay Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Length or TOF Delay Tol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Length or TOF Delay Delta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Length or TOF Delay Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Formulas Formula. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Formulas Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Static Low Overshoot Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Static High Overshoot Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Dynamic Low Overshoot Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Dynamic High Overshoot Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Ringback Margin High Min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Ringback Margin Low Min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Non-Monotonic Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Single Ended Characteristic Impedance Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Single Ended Characteristic Impedance Tol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Simulation Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Simulation Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Simulated Delay Edge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Simulated Delay Min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Simulated Delay Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Simulated Delay Max Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Simulated Delay Match To . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Simulated Delay Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Simulated Delay Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Simulated Delay Tol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Differential Pair Tol Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Convergence Tolerance Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Distance to Convergence Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Separation Distance Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Differential Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Differential Impedance Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Differential Impedance Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
I/O Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Hierarchical Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Qty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Part Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
IBIS Component Name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

Table of Contents
Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
IBIS Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Schematic Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Topology Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Pin Package Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Pin Package Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Thermal Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Thermal Power Scaling Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Thermal Theta-jc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Thermal Casing Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Thermal Junction Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
I/O Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Noise Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Noise Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Constraint Class or Electrical Net Name Victim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Constraint Class or Electrical Net Name Aggressor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Parallelism Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Crosstalk Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Crosstalk Sim Actual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Crosstalk Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Appendix B
CES Command-Line Tools Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
cons2ascii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
cons2csv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
cons2xml . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
csv2dat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
ImportPinPackageLength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Index
End-User License Agreement

Table of Contents

Chapter 1
CES Quick References and Work Flows
Welcome to the “Constraint Editor System™ (CES) User’s Manual.” This section includes
quick references and work flows that will help you get up, running, and comfortable with CES
in a minimal amount of time.
Quick Help
Please click within the following illustration for single-click access to a wide variety of topics
covered in this manual.
Figure 1-1. Constraint Editor System (CES) Quick Help

Quick Reference - CES Commands

You can use this reference to quickly find specific CES commands. They are organized
alphabetically by design object and then action/task. You can also print this quick reference to
keep it handy while you use CES.
Click within the Topic column to jump to the corresponding topic for one of the following
commands. When viewing this documentation from your web browser, to open this quick
reference in a standalone browser window, click here.
Table 1-1. CES Commands

Design Action CES Command Topic
Object
Bus Define CES Spreadsheet > Nets tab > “Defining Bus
constraint (auto) Edit menu > Auto Bus Constraint Classes
class Automatically” on
page 148
Clearance Assign CES Spreadsheet > Clearances “Assigning Class-To-
rule set tab > Clearances toolbar > Class Clearance
Rules” on page 165
Clearance Create Navigator > expand Schemes > “Creating Clearance
rule set right-click a scheme > New Rule Sets for
Clearance Rule Schemes” on
page 158
Constant Create CES Spreadsheet > Nets tab > “Creating Constants
Edit menu > Variables > Edit and Variables for
Delay Rules and
Formulas” on
page 203
Constraint Export File > Export > Constraints “Exporting
Constraints in
Encrypted ASCII
Format” on page 244
Constraint Import File > Import > Constraints “Importing CES
Constraints” on
page 245
Constraint Rollback File > Rollback Changes “Rolling Back and
Undoing Constraint
Changes” on
page 135
Constraint Search Find toolbar > “Searching for
Constraints” on
page 113

Table 1-1. CES Commands (cont.)

Object
Constraint View Info CES Spreadsheet > right-click a “Viewing Constraint
constraint cell > Constraint Help Reference
Information” on
page 123
Constraint Add nets CES Spreadsheet > Nets tab > “Adding Nets to a
class Edit menu > Assign Nets to Constraint Class” on
Classes page 147
Constraint Copy Navigator > expand Constraint “Creating a
class constraints Classes > right-click a constraint Constraint Class
class > Clone From an Existing
Constraint Class” on
page 151
Constraint Create Navigator > right-click Constraint “Creating Constraint
class Classes > New Constraint Class Classes” on page 145
Constraint Rename Navigator > expand Constraint “To Rename a
class Classes > right-click a constraint Constraint Class” on
class > Rename page 147
Constraint Create CES Spreadsheet > Nets, Parts, or “Creating Constraint
group Constraint Templates tab> Group Groups” on page 118
pulldown > Edit Constraint
Groups >
Constraint Apply CES Spreadsheet > Nets tab > “Applying Constraint
template Edit menu > Apply Constraint Templates to Nets” on
Template page 233
Constraint Create CES Spreadsheet > Nets tab > “Creating Constraint
template right-click an electrical net ( ) > Templates to Capture
Create Constraint Template Net Constraints” on
page 231
Constraint Reuse File > Export > Constraints “Reusing Constraint
template (external) Templates in External
Designs” on page 239
Default rules Revert Navigator > expand Schemes > “Resetting Clearance
right-click a scheme > Reset to Rules to the Master
(Master) Scheme” on page 177
Design Set up Edit > Design Preferences “Specifying Design
configuratio Preferences” on
n page 59


Object
Differential Create (auto) CES Spreadsheet > Nets tab > “Defining Differential
pair Pairs toolbar > Pairs Automatically”
on page 224
Differential Create CES Spreadsheet > Nets tab > “Defining Differential
pair (manual) select two nets > Pairs toolbar > Pairs Manually” on
page 223
Differential Specify CES Spreadsheet > Nets tab > “Specifying Delay
pair delay rules Group pulldown > Delays and Rules for Nets” on
Lengths page 192
Discrete pin Define CES Spreadsheet > Parts tab > “Defining Pin Pairs
pair right-click a top-level discrete > for Nets” on page 188
Create Pin Pairs
Formula Define CES Spreadsheet > Nets tab > “Defining Formulas
design object row > Formulas to Create Net
Formula cell Relationships” on
page 199
Formula Solve CES Spreadsheet > Nets tab > “Solving Formulas to
Pairs toolbar > Check for Errors” on
page 202
From-to Define CES Spreadsheet > Nets tab > set “To Manually Define
Topology Type to Custom > Netline Ordering
Topology toolbar > (From-Tos) for a
Specific Net” on
page 182
General Specify CES Spreadsheet > Clearances “Specifying General
clearance tab > Clearances toolbar > Clearance Rules” on
rules page 174
Net Explore SI CES Spreadsheet > Nets tab > “Sending Nets to
right-click an electrical net ( ) > HyperLynx LineSim”
Display Net in > HyperLynx on page 273
LineSim
Net Explore SI CES Spreadsheet > Nets tab > “Sending Nets to ICX
right-click an electrical net ( ) > Pro Explorer” on
Display Net in > ICX Pro page 275
Explorer
Net Specify CES Spreadsheet > Nets tab > “Specifying Delay
delay rules Group pulldown > Delays and Rules for Nets” on
Lengths page 192


Object
Net class Add Nets CES Spreadsheet > Trace & Via “Adding Nets to a Net
Properties tab > Edit menu > Class” on page 141
Assign Nets to Classes
Net class Copy Navigator > expand Net Classes > “Creating a Net Class
constraints right-click a net class > Clone From an Existing Net
Class” on page 142
Net class Create Navigator > right-click Net “Creating Net
Classes > New Net Class Classes” on page 139
Net class Rename Navigator > expand Net Classes > “To Rename a Net
right-click a net class > Rename Class” on page 141
Package Assign CES Spreadsheet > Clearances “Assigning Package
clearance tab > Clearances toolbar > Clearance Type
type rules Rules” on page 170
Parallelism Assign CES Spreadsheet > Noise Rules “Assigning
rules tab > Pairs toolbar > Parallelism Rules to
Nets and Constraint
Classes” on page 218
Parallelism Define Edit > Parallelism Rules > Define “Defining Parallelism
rules Parallelism Rules Rules for Stack-Up
Layers” on page 216
Parallelism Navigate CES Spreadsheet > Nets tab > “Navigating to
rules right-click a net or constraint class Assigned Parallelism
> Navigate to Parallelism Rule Rules From the Nets
Page” on page 220
Part model Assign CES Spreadsheet > Parts tab > “Assigning Models to
IBIS Component Name and Parts” on page 265
Technology cells >
Part model Make Edit > Simulation > Model Search “Specifying Available
available Path Part Models” on
page 261
Part model Verify Data > Model Audit Report “Verifying Default
Assignments Model Assignments”
on page 263
Pin package Import File > Import > Pin Package “Importing Pin
lengths Lengths Package Length
Values” on page 269


Object
Pin pair Define CES Spreadsheet > Nets tab > “To Define All Pin
(auto) Pairs toolbar > Pairs Automatically”
on page 189
Pin pair Define CES Spreadsheet > Nets tab > net “To Define Pin Pairs
(manual) row > Edit menu > Pin Pairs > Manually” on
Add Pin Pairs page 189
Pin pair Specify CES Spreadsheet > Nets tab > “Specifying Delay
delay rules Group pulldown > Delays and Rules for Nets” on
Lengths page 192
Pin set Create CES Spreadsheet > Nets tab > net “Creating Pin Sets to
row > Topology toolbar > > Construct Advanced
> , , , , or > select pins Topologies” on
> Finish page 184
Rule-area Create Navigator > right-click Schemes “Creating Rule Area
scheme > New Scheme Schemes” on
page 153
Stackup Edit General toolbar > “Viewing or
Modifying Stackup
Properties” on
page 259
Topology Specify CES Spreadsheet > Nets tab > net “Specifying
(custom) row > Topology toolbar > > Topologies for Nets
and Constraint
Topology Specify (pre- CES Spreadsheet > Nets tab > net “Specifying
defined) row > Topology toolbar > , , Topologies for Nets
, , or and Constraint
Trace & via Override CES Spreadsheet > Nets tab > “Overriding Trace
rules widths From To Constraints Trace Width Width Constraints for
(from-to) cell From-Tos” on
page 187
Trace & via Specify CES Spreadsheet > Trace & Via “Specifying Trace
rules Properties tab > expand a scheme and Via Rules” on
page 154
Units Set Setup > Settings > Display Units “Setting Units for the
and Notation CES Spreadsheet” on
page 66


Object
Variables Create CES Spreadsheet > Nets tab > “Creating Constants
Edit menu > Variables > Edit and Variables for
Delay Rules and
Formulas” on
page 203
Variables Find CES Spreadsheet > Nets tab > “To Find Variable
references Edit menu > Variables > Find References” on
Variables Reference page 205
Z-axis Assign CES Spreadsheet > Z-Axis “Assigning Z-Axis
clearance Clearances tab > Clearances Class-To-Class
rule set toolbar > Clearance Rules” on
page 168
Z-axis Create CES Spreadsheet > Z-Axis “Creating Clearance
clearance Clearances tab > right-click Rule Sets for
rule set existing rule set > New Z-Axis Schemes” on
Clearance Rule page 158

Quick Reference - CES GUI

You can use this reference to quickly determine the purpose of specific menu selections
available through the CES graphical user interface. You can also print this quick reference to
keep it handy while you use CES.
Click within the right column of the tables below to view the topic associated with a specific
menu selection. When viewing this documentation from your web browser, to open this quick
reference in a standalone browser window, click here.
File Menu
Read a command’s purpose or click within the Topic/Purpose column to view the
documentation associated with a specific File menu command.
Table 1-2. File Menu Selections

Menu Command Topic/Purpose
File > Rollback Changes “Rolling Back and Undoing Constraint Changes” on
page 135
File > Open Project Open a .prj file when you launch CES in standalone mode.
File > Close Project Close a .prj file you opened in standalone CES.
File > Reload Project Reload a .prj file you opened in standalone CES.
File > Page Setup Set up paper and orientation options for printing.
File > Print Setup Set up your printer.
File > Print Preview View preview of a print job.
File > Print Print CES Spreadsheet content.
File > File Viewer “Viewing Constraint Database Log Files” on page 57
File > Import > Layout “Importing a Layout Template” on page 52
Template
File > Import > Constraints “Importing Constraints in Encrypted XML Format” on
page 245
File > Import > Constraints “Importing Constraints in Encrypted CSV Format” on
from encrypted CSV page 246
File > Import > Constraint “Reusing Constraint Templates in External Designs” on
Template page 239
File > Import > Settings “Reusing Settings in External Designs” on page 70
File > Import > Preferences “Importing a 2005.x Ces.prefs File” on page 52
File

Table 1-2. File Menu Selections (cont.)

File > Import > Pin Package “Importing Pin Package Length Values” on page 269
Lengths
File > Export > Constraints “Exporting Constraints in Encrypted XML Format” on
page 241
File > Export > Constraints “Exporting Constraints in Encrypted ASCII Format” on
to encrypted ASCII page 244
File > Export > Constraints “Exporting Constraints in Encrypted CSV Format” on
to encrypted CSV page 243
File > Export > Constraint “Reusing Constraint Templates in External Designs” on
Template page 239
File > Export > Settings “Reusing Settings in External Designs” on page 70
File > Export > Actuals “Sharing PCB Actuals With Front-End CES Sessions” on
page 131
File > Exit Exit CES.
Edit Menu
documentation associated with a specific Edit menu command.
Table 1-3. Edit Menu Selections

Edit > Undo Undo last operation.
Edit > Redo Redo last undo operation.
Edit > Cut Cut selection.
Edit > Copy Copy selection.
Edit > Paste Paste selection.
Edit > Delete Delete selection.
Edit > Rule Painter “Painting Rules to Reuse Constraints” on page 134
Edit > Find “Searching for Constraints” on page 113
Edit > Pin Pairs > Add Pin “Defining Pin Pairs for Nets” on page 188
Pairs
Edit > Pin Pairs > Auto Pin “To Define All Pin Pairs Automatically” on page 189
Pair Generation

Table 1-3. Edit Menu Selections (cont.)

Edit > Pin Pairs > Auto “To Define Only Simulation Pin Pairs Automatically” on
Simulation Pin Pair page 190
Generation
Edit > Netline Order “To Manually Define Netline Ordering (From-Tos) for a
Specific Net” on page 182
Edit > Diff Pairs > Diff Pair “Defining Differential Pairs Manually” on page 223
from Selected Nets
Edit > Diff Pairs > Auto “Defining Differential Pairs Automatically” on page 224
Assign Diff Pairs
Edit > Assign Nets to “Adding Nets to a Net Class” on page 141
Classes
Edit > Auto Bus “Defining Bus Constraint Classes Automatically” on
page 148
Edit > Parallelism Rules > “Defining Parallelism Rules for Stack-Up Layers” on
Define Parallelism Rules page 216
Edit > Parallelism Rules > “Assigning Parallelism Rules to Nets and Constraint
Assign Parallelism Rules Classes” on page 218
Edit > Clearances > Assign “Assigning Package Clearance Type Rules” on page 170
Package Type Clearances
Edit > Clearances > Reset to “Resetting Clearance Rules to the Master Scheme” on
Master page 177
Edit > Clearances > General “Specifying General Clearance Rules” on page 174
Clearances
Edit > Clearances > Class to “Assigning Class-To-Class Clearance Rules” on page 165
Class Clearance Rule
Edit > Clearances > Z-Axis “Creating Clearance Rule Sets for Schemes” on page 158
Clearances
Edit > Clearances > Z-Axis “Assigning Z-Axis Class-To-Class Clearance Rules” on
Class to Class Clearance page 168
Rule
Edit > Constants and “Creating Constants and Variables for Delay Rules and
Variables > Edit Formulas” on page 203
Edit > Constants and “To Find Variable References” on page 205
Variables > Find Variables
Reference
Edit > Via Assignments “Defining Via Assignments” on page 157

Table 1-3. Edit Menu Selections (cont.)

Edit > Simulation > “Modifying Simulation Settings” on page 71
Simulation Settings
Edit > Simulation > “Modifying Simulation Stimulus” on page 77
Simulation Stimulus
Edit > Simulation > SI “Specifying Model Libraries” on page 262
Library Search Paths
Edit > Apply Constraint “Applying Constraint Templates to Nets” on page 233
Template
Edit > Constraint “Customizing the Constraint Set” on page 86
Definitions
Edit > Constraint Groups “Creating Constraint Groups” on page 118
Edit > Stackup “Viewing or Modifying Stackup Properties” on page 259
View Menu
documentation associated with a specific View menu command.
Table 1-4. View Menu Selections

View > Expand > Selected | “Expanding and Collapsing Spreadsheet Rows” on
All page 109
View > Collapse > Selected “Expanding and Collapsing Spreadsheet Rows” on
| All page 109
View > Reset Row Heights “To Reset Rows to Their Default Heights” on page 108
View > Reset Column “To Reset Columns to Their Default Widths” on page 108
Widths
View > Reset View Reset the spreadsheet to the default appearance for row
heights and columns widths, and collapse rows.
Views > Tabs “To Toggle the Display of Specific Windows and
Window Elements” on page 80
View > Navigator “To Toggle the Display of Specific Windows and
View > Output “To Toggle the Display of Specific Windows and

Table 1-4. View Menu Selections (cont.)

View > Status Bar “To Toggle the Display of Specific Windows and
View > Remotely Modified “Working Concurrently With Other Users” on page 121
Data > Refresh
View > Remotely Modified “Working Concurrently With Other Users” on page 121
Data > Enable Indication
View > Toolbars “To Toggle the Display of Specific Windows and
View > Toolbars > “Customizing CES Toolbars” on page 81
Customize
Setup Menu
documentation associated with a specific Setup menu command.
Table 1-5. Setup Menu Selections
Setup > Settings “Specifying Design Preferences” on page 59 and “Setting
Up CES” on page 59
Setup > Cross Probing “Cross Probing Between Design Systems and CES” on
page 58
Setup > Shortcuts “Customizing Command Shortcut Keys” on page 93
Filters Menu
documentation associated with a specific Filters menu command.
Table 1-6. Filters Menu Selections

Filters > Enabled “Filtering Spreadsheet Data” on page 115
Filters > Cumulative Mode “To Enable Cumulative Mode” on page 116
Filters > Drill-down “Filtering Spreadsheet Data” on page 115
Filtering
Filters > Levels “To Filter the Spreadsheet by Row Type” on page 117
Filters > Levels > Reset “To Reset the View of Data Rows to All” on page 116

Tools Menu
documentation associated with a specific Tools menu command.
Note
Most Tools menu selections are only available in standalone CES sessions that are
launched on an Expedition Enterprise Flow: DxDesigner design.
Table 1-7. Tools Menu Selections

Tools > Dashboard Launch the Mentor Graphics Dashboard.
Tools > DxDesigner Launch DxDesigner.
Tools > ICX Pro Explorer Launch ICX Pro Explorer.
Tools > I/O Designer Launch I/O Designer.
Tools > Constraint Launch Constraint Template Editor.
Template Editor
Tools > CES Diagnostics “Checking Constraints and Synchronization” on page 124
Tools > Constraint “Resolving Schematic Constraint Conflicts Manually” on
Resolution Manager page 284
Tools > iCDB Server Launch Server Manager.
Manager
Tools > iCDB Project Launch Auto Backup Utility.
Backup
Tools > Valor NPI “Selecting or Creating Valor NPI Design Centers” on
page 95
Tools > Customize “Adding Custom Menu Selections to the Tools Menu” on
page 92
Data Menu
documentation associated with a specific Data menu command.
Table 1-8. Data Menu Selections

Data > Constraint “Viewing All Constraint Violations” on page 132
Violations
Data > Solve All Formulas “Solving Formulas to Check for Errors” on page 202

Table 1-8. Data Menu Selections (cont.)

Data > Update > Simulation “To Update ICX Pro Verify Simulation Results” on
Results page 133
Data > Update > IBIS Pin “Updating Part Model Constraints” on page 266
Type & Defaults
Data > Actuals > Import “Sharing PCB Actuals With Front-End CES Sessions” on
Layout Actuals page 131
Data > Actuals > Import “Sharing PCB Actuals With Front-End CES Sessions” on
Thermal Actuals page 131
Data > Actuals > Clear All “Clearing Actuals From the CES Spreadsheet” on
Pages page 130
Data > Actuals > Clear This “Clearing Actuals From the CES Spreadsheet” on
Page page 130
Data > Actuals > Update “To Update All Net Actuals” on page 130
All
Data > Actuals > Update “To Update Selected Net Actuals” on page 130
Selected
Data > Clear All “Deleting Constraint Values at the Object or Design
Constraints Level” on page 111
Data > Clear All Custom Delete all custom constraints you created.
Constraint Definitions
Data > Clear All Custom Delete all custom tabs you created.
Tabs
Output Menu
documentation associated with a specific Output menu command.
Table 1-9. Output Menu Selections

Output > Model Audit “Verifying Default Model Assignments” on page 263
Report
Output > Design Statistics “Viewing Design Statistics” on page 124
Output > Check Constraints “Checking Constraints and Synchronization” on page 124
Synchronization
Output > Show iCDB Provides a short report of clients and sub-clients who are
Clients currently working on the same design.

Table 1-9. Output Menu Selections (cont.)

Output > Report Comments “To View Comments” on page 122

Quick Reference - CES Constraint Spreadsheet

You can use this reference to quickly determine how to best utilize the design constraints you
can define through CES. Constraints are grouped by CES Spreadsheet page and ordered as they
appear on a specific spreadsheet page. You can also print this quick reference to keep it handy
while you use CES. When viewing this documentation from your web browser, to open this
quick reference in a standalone browser window, click here.
CES Constraint Reference: To get more information about a specific constraint, click the CES
Constraint name as it appears in one of the quick-reference tables below. Clicking a
constraint name brings you to the corresponding topic for a constraint, all of which are located
in the CES Constraint Reference (appendix A in the table of contents).
CES Constraint Spreadsheet Pages

Click one of the following links to go to a specific constraint spreadsheet quick-reference:
• “Trace and Via Properties Summary” on page 28

• “Clearances Summary” on page 29
• “Z-Axis Clearances Summary” on page 32
• “Nets Summary” on page 32
• “Parts Summary” on page 40
• “Noise Rules Summary” on page 41
Trace and Via Properties Summary

Please refer to the following table for trace and via property constraint quick-reference
information.
Table 1-10. Trace & Via Properties

CES Constraint Purpose
“Index” on page 292 Displays the layer number for a board layer. This
constraint is also displayed on the Clearances page and Z-
Axis Clearances page.
“Type” on page 293 Displays the type of printed circuit board layer (for
example, signal, power, or ground). This constraint is also
displayed on the Clearances page.
“Via Assignments” on Defines the via assignment for a net class.
page 294

Table 1-10. Trace & Via Properties (cont.)

“Route” on page 295 Defines whether the board layer is routed during PCB
fabrication. You can define Route individually or for all
board layers of a net class.
“Trace Width Minimum” Defines the minimum acceptable trace width. You can
on page 296 define Trace Width Minimum individually or for all board
layers of a net class.
“Trace Width Typical” on Defines the typical acceptable trace width. You can define
page 297 Trace Width Typical individually or for all board layers of
a net class.
“Trace Width Expansion” Defines the expansion, or maximum acceptable trace
on page 298 width.You can define Trace Width Expansion individually
or for all board layers of a net class.
“Typical Impedance” on Defines signal impedance for the Trace Width Typical
page 299 constraint. When you enter a value into the Trace Width
Typical cell, impedance at this width is calculated and
placed into the Typical Impedance cell.
“Differential Typical Defines signal impedance for trace segments that are part
Impedance” on page 300 of a differential pair. This value is calculated and updated
automatically when you modify Trace Width Typical,
Typical Impedance, or Differential Spacing.
“Differential Spacing” on Defines the required parallel distance between trace
page 301 segments that comprise a differential pair. You can define
Differential Spacing individually or for all board layers of
a net class.
Clearances Summary
Please refer to the following table for clearance constraint quick-reference information.
Table 1-11. Clearances
constraint is also displayed on the Trace & Via Properties
page and Z-Axis Clearances page.
“Type” on page 304 Displays the type of printed circuit board layer (for
example, signal, power, or ground). This constraint is also
displayed on the Trace & Via Properties page.

Table 1-11. Clearances (cont.)

“Trace To Trace” on Defines the minimum clearance distance between trace
page 305 segments. You can define Trace to Trace individually or
for all board layers of a clearance rule.
“Trace To Pad” on page 306 Defines the minimum clearance distance between traces
and pads. You can define Trace To Pad individually or for
all board layers of a clearance rule.
“Trace To Via” on page 307 Defines the minimum clearance distance between traces
and vias. You can define Trace To Via individually or for
“Trace To Plane” on Defines the minimum clearance distance between traces
page 308 and planes. You can define Trace To Plane individually or
“Pad To Pad” on page 310 Defines the minimum clearance distance between pads.
You can define Pad To Pad individually or for all board
layers of a clearance rule.
“Pad To Via” on page 311 Defines the minimum clearance distance between pads
and vias. You can define Pad To Via individually or for all
board layers of a clearance rule.
“Pad To Plane” on page 312 Defines the minimum clearance distance between pads
and planes. You can define Pad To Plane individually or
“Trace To SMD Pad” on Defines the minimum clearance distance between the pads
page 309 of surface mount devices and traces. You can define Trace
To SMD Pad individually, or for all board layers of a
clearance rule.
“Via To SMD Pad” on Defines the minimum clearance distance between the pads
page 315 of surface mount devices and vias. You can define Via To
SMD Pad individually, or for all board layers of a
clearance rule.
“Via To Via” on page 313 Defines the minimum clearance distance between vias.
You can define Via To Via individually or for all board
“Via To Plane” on page 314 Defines the minimum clearance distance between vias and
planes. You can define Via To Plane individually or for all
“Plane To Plane” on Defines the minimum clearance distance between planes.
page 316 You can define Plane To Plane individually or for all

Table 1-11. Clearances (cont.)

“Embedded Resistor To Defines the minimum clearance distance between the
Trace” on page 317 resistive material of embedded thick-film resistors and
traces. You can define Embedded Resistor To Trace
individually or for all board layers of a clearance rule.
Pad” on page 318 resistive material of embedded thick-film resistors and
pads. You can define Embedded Resistor To Pad
Via” on page 319 resistive material of embedded thick-film resistors and
vias. You can define Embedded Resistor To Via
Resistor” on page 320 resistive material of embedded thick-film resistors. You
can define Embedded Resistor To Resistor individually or
“EP Mask To Trace” on Defines the minimum clearance distance between the
page 321 production mask of embedded thin-film resistors and
traces. You can define EP Mask To Trace individually or
“EP Mask To Pad” on Defines the minimum clearance distance between the
page 322 production mask of embedded thin-film resistors and
pads. You can define EP Mask To Pad individually or for
“EP Mask To Via” on Defines the minimum clearance distance between the
page 323 production mask of embedded thin-film resistors and vias.
You can define EP Mask To Via individually or for all
“EP Mask To Resistor” on Defines the minimum clearance distance between the
page 324 production mask of embedded thin-film resistors and the
resistive material of embedded thick-film resistors. You
can define EP Mask To Resistor individually or for all

Z-Axis Clearances Summary

Please refer to the following table for z-axis clearance constraint quick-reference information.
Table 1-12. Z-Axis Clearances

constraint is also displayed on the Trace & Via Properties
page and Clearances page.
“Trace To Trace” on Defines the minimum clearance distance between trace
page 327 segments located on different signal layers. You can
define Trace To Trace individually or for all board layers
of a clearance rule.
“Trace To Pad” on page 328 Defines the minimum clearance distance between traces
and pads located on different signal layers. You can define
Trace To Pad individually or for all board layers of a
clearance rule.
“Trace To Via” on page 329 Defines the minimum clearance distance between traces
and vias located on different signal layers. You can define
Trace To Via individually or for all board layers of a
clearance rule.
“Trace To Plane” on Defines the minimum clearance distance between traces
page 330 and planes located on different signal layers. You can
define Trace To Plane individually or for all board layers
“Trace To SMD Pad” on Defines the minimum clearance distance between the pads
page 331 of surface mount devices and traces located on internal
signal layers. You can define Trace To SMD Pad
individually, or for all board layers of a clearance rule.
Nets Summary
Please refer to the following table for net constraint quick-reference information.
Table 1-13. Nets
CES Constraint Group Purpose
“# Pins” on page 334 Displays the number of pins that comprise the
net.

Table 1-13. Nets (cont.)

“Analog” on page 335 Defines the net as analog and prevents physical
nets that comprise an electrical net from being
merged into an electrical net or differential pair.
You cannot define differential pair nets as
Analog. You can define Analog individually or
for all nets of a constraint class.
“Bus” on page 336 Defines the constraint class as a bus. Nets within
the constraint class should be limited to those
nets that comprise the bus.
“Net Class” on page 337 Displays the name of the net class to which the
net belongs.
“Template Name” on Optionally, defines the constraint template to
page 338 which the net is assigned. You can define
Template Name individually or for all nets of a
constraint class.
“Template Status” on Displays the synchronization status of the net
page 339 with regard to the current values stored in the
constraint template.
“Topology Type” on Defines the topology type used for routing,
page 340 which can be an automatic routing pattern, or
custom routing pattern that you define. You can
define Topology Type individually or for all nets
of a constraint class.
“Topology Ordered” on For Topology Type Custom or Complex,
page 342 displays whether the custom topology type has
undergone netline ordering, which is required for
each user-specific topology type.
“Stub Length Max” on Defines the maximum stub length that can be
page 343 created when routing this net as a custom,
complex, or chained Topology Type. You can
define Stub Length Max individually or for all
nets of a constraint class.
“# Vias Max” on page 344 Defines the maximum number of vias that can be
created when routing a net. This constraint value
must be between 1 and 1000. You can define #
Vias Max individually or for all nets of a
constraint class.


“Max Restricted Layer Defines the maximum trace length that can be
Length External” on routed on external restricted board layers. You
page 345 can define Max Restricted Layer Length External
individually or for all nets of a constraint class.
“Max Restricted Layer Defines the maximum trace length that can be
Length Internal” on routed on internal restricted board layers. You
page 346 can define Max Restricted Layer Length Internal
individually or for all nets of a constraint class.
“From To Constraints Defines the board layer on which to route a from-
Layer” on page 347 to for a non-differential net that uses Topology
Type Custom. You can define From To
Constraints Layer individually for each from-to
that is part of a non-differential net.
“From To Constraints Trace Optionally defines the trace width to which to
Width” on page 348 route a from-to. You can only define this
constraint for non-differential nets that use a
custom Topology Type. You also must define
From To Constraints Layer before you can enter
a value for this constraint. You can define From
To Constraints Trace Width individually for each
from-to.
“From To Constraints Z0” Displays an impedance calculation based on the
on page 349 trace width override value defined in From To
Constraints Trace Width.
“Length or TOF Delay Defines the delay type for a net, which can be
Type” on page 350 controlled electrically (TOF) or physically
(Length). You can define Length or TOF Delay
Type individually, for pin pairs, for differential
pairs, or for all nets of a constraint class.
“Length or TOF Delay Defines the minimum acceptable physical
Min” on page 351 routing length or signal propagation delay (for
example, time) between design connections. You
can define Length or TOF Delay Min
individually, for pin pairs, for differential pairs,
or for all nets of a constraint class.
“Length or TOF Delay Defines the maximum acceptable physical
Max” on page 353 routing length or signal propagation delay (for
example, time) between design connections. You
can define Length or TOF Delay Max
individually, for pin pairs, for differential pairs,


“Length or TOF Delay Displays the Manhattan net length. This length is
Manhattan” on page 355 replaced with Length or TOF Delay Actual when
the net is routed.
“Length or TOF Delay Min Displays the straight line length between two pin
Length” on page 356 pairs when both components are placed. This
length is replaced with Length or TOF Delay
Actual when the net is routed.
“Length or TOF Delay Defines a match character or string (for example,
Match” on page 357 1) you can use to group nets for similar length or
time of flight delay routing. You can apply
Length or TOF Delay Match individually, for pin
pairs, or for differential pairs.
“Length or TOF Delay Tol” Introduces a tolerance range around the net
on page 358 routing delay requirements for nets that duplicate
a Length or TOF Delay Match (for example, 1).
You can also define this constraint at the
constraint class level without the pre-requirement
of defining a match character or string.
“Length or TOF Delay Displays estimates for routing results that can be
Delta” on page 359 achieved without constraint modification.
“Length or TOF Delay Displays the range of length or time of flight
Range” on page 360 actuals for all nets and/or constraint classes that
are part of the same match group.
“Formulas Formula” on Defines a formula that can be used to create
page 361 delay relationships between nets and pin pairs.
You can define Formulas Formula individually
or for pin pairs.
“Formulas Violation” on Displays formula violation information based on
page 362 the Formulas Formula constraint.
“Static Low Overshoot Defines the maximum low DC voltage
Max” on page 363 (minimum) that a buffer can withstand without
permanent damage to the buffer. You can define
Static Low Overshoot Max individually, for
differential pairs, or for all nets of a constraint
class. This value is defined in an IBIS model
through the S_overshoot_low keyword.


“Static High Overshoot Defines the maximum high DC voltage that a
Max” on page 365 buffer can withstand without permanent damage
to the buffer. You can define Static High
Overshoot Max individually, for differential
pairs, or for all nets of a constraint class. This
value is defined in an IBIS model through the
S_overshoot_high keyword.
“Dynamic Low Overshoot Defines an available, smaller low operating
Max” on page 367 voltage (below minimum) limit for the signal that
is to not exceed a specific duration. This voltage
limit should not be met or exceeded, but allow
for the signal to go lower than Static Low
Overshoot Max, while never equaling Dynamic
Low Overshoot Max. You can define Dynamic
Low Overshoot Max individually, or for all nets
of a constraint class. These values are defined in
an IBIS model through the D_overshoot_low and
D_overshoot_time keywords.
“Dynamic High Overshoot Defines an available, larger high operating
Max” on page 369 voltage (above maximum) limit for the signal
that is to not exceed a specific duration. This
voltage limit should not be met or exceeded, but
allow for the signal to go higher than Static High
Overshoot Max, while never equaling Dynamic
High Overshoot Max. You can define Dynamic
High Overshoot Max individually, for
differential pairs, or for all nets of a constraint
class. These values are defined in an IBIS model
through the D_overshoot_high and
“Ringback Margin High Defines the minimum allowed difference
Min” on page 371 between the high switching threshold (Vinh) and
a ringback wave. You can define Ringback
Margin High Min individually, for differential
“Ringback Margin Low Defines the minimum allowed difference
Min” on page 372 between the low switching threshold (Vinl) and a
ringback wave. You can define Ringback Margin
Low Min individually, for differential pairs, or


“Non-Monotonic Edge” on Defines a non-monotonicity requirement for the
page 373 rising edge, falling edge, or both signal edges.
You can define Non-Monotonic Edge
individually, for differential pairs, or for all nets
of a constraint class. For example, when you set
Non-Monotonic Edge to Rising, an error is
reported only if the rising signal edge is non-
monotonic.
“Single Ended Defines the single-ended characteristic
Characteristic Impedance impedance for net traces. You can define Single
Value” on page 374 Ended Characteristic Impedance Value
“Single Ended Introduces a tolerance range around Single
Characteristic Impedance Ended Characteristic Impedance Value. You can
Tol” on page 375 define Single Ended Characteristic Impedance
Tol individually, for differential pairs, or for all
“Simulation Settings” on , Defines the simulation settings to use when
page 376 generating actual values for Nets Spreadsheet
Overshoot/Ringback and Simulated Delays
groups. You can define Simulation Settings
“Simulation Stimulus” on , Defines the simulation stimulus to use when
page 378 generating actual values for Nets Spreadsheet
Overshoot/Ringback and Simulated Delays
groups. You can define Simulation Stimulus
“Simulated Delay Edge” on Defines the simulated delay edge to constrain,
page 379 which controls the switching time between signal
states. You can define Simulated Delay Edge
individually, for differential pairs, for pin pairs,
“Simulated Delay Min” on Defines the minimum acceptable simulated delay
page 381 for the Simulated Delay Edge value (for
example, Rise or Fall). You can define Simulated
Delay Min individually, for differential pairs, for
pin pairs, or for all nets of a constraint class.


“Simulated Delay Max” on Defines the maximum acceptable simulated
page 382 delay for the Simulated Delay Edge value (for
example, Rise:Fall or Both). You can define
Simulated Delay Max individually, for
differential pairs, for pin pairs, or for all nets of a
constraint class.
“Simulated Delay Max Defines a maximum acceptable range of
Range” on page 383 difference between Simulated Delay Actual Min
and Simulated Delay Actual Max for the
Simulated Delay Edge value (for example, Fall
or Both). You can define Simulated Delay Max
Range individually, for differential pairs, for pin
“Simulated Delay Match Defines the hierarchical level of matching for the
To” on page 384 Simulated Delay Match constraint. You can
match to the constraint class, net, or pin-pair
level. You can define Simulated Delay Match To
“Simulated Delay Match” Defines the electrical net, pin pair, or constraint
on page 385 class to which to match the Simulated Delay
constraints (for example, Simulated Delay Edge,
Simulated Delay Min, and Simulated Delay
Max). You can define Simulated Delay Match
“Simulated Delay Offset” Introduces a positive or negative offset (for
on page 387 example, 50 ns or -50 ns) from Simulated Delay
Min and Simulated Delay Max when matching
the simulated delay of an electrical net or
constraint class (Simulated Delay Match). You
can define Simulated Delay Offset individually,
for differential pairs, for pin pairs, or for all nets
“Simulated Delay Tol” on Introduces a tolerance range (for example, 5 ns)
page 388 around Simulated Delay Min and Simulated
Delay Max when matching the simulated delay
of an electrical net or constraint class (Simulated
Delay Match). You can define Simulated Delay
Tol individually, for differential pairs, for pin


“Differential Pair Tol Max” Defines the tolerance of the time of flight or
on page 389 length delay between differential pairs. You can
define Differential Pair Tol Max individually for
each differential pair.
“Convergence Tolerance Defines the maximum allowed difference in trace
Max” on page 390 length from pads to the point where traces start
routing differentially at the Differential Spacing
constraint. You can define Convergence
Tolerance Max individually for each differential
pair.
“Distance to Convergence Defines the maximum distance that differential
Max” on page 391 traces are allowed to route before they converge
as a differential pair. The distance value is the
combination of segment lengths. Convergence is
met when traces start routing at the Differential
Spacing constraint.You can define Distance to
Convergence Max individually for each
differential pair.
“Separation Distance Max” Defines the maximum allowed distance that
on page 392 differential traces are allowed to route at a
spacing greater or less than the Differential
Spacing constraint. You can define Separation
Distance Max individually for each differential
pair.
“Differential Spacing” on Displays the required parallel distance between
page 393 trace segments that comprise a differential pair.
When separate spacing values are defined for
each board layer, CES displays the values as a
colon-separated list (for example, 5:8).
“Differential Impedance Defines the target differential impedance. You
Target” on page 394 can define this constraint for differential pairs.
“Differential Impedance Introduces a tolerance range around Differential
Tolerance” on page 395 Impedance Target. You can define this constraint
for differential pairs.
“I/O Standard” on page 396 Defines the technology standard for an FPGA
signal net. You can define I/O Standard
individually, or for all nets of a constraint class.

Parts Summary
Please refer to the following table for part constraint quick-reference information.
Table 1-14. Parts

“Hierarchical Path” on Displays the hierarchical component path, when
page 398 applicable.
“Part Number” on page 399 Displays the part number for a design component.
“Qty” on page 400 Displays the number of times a part is used throughout
your design.
“Part Type” on page 401 Displays the part-type value associated with a design
component.
“Series” on page 402 Defines whether a series-class component (for example,
resistor) should actually be considered a series element,
and therefore not used for electrical net generation. You
can define Series for parts and part instances.
“IBIS Component Name” Defines the IBIS model used for a part. You can define
on page 403 IBIS Component Name individually, or for all instances of
a part.
“Technology” on page 404 Defines the technology model used for a part. You can
define Technology individually, or for all instances of a
part.
“Value” on page 405 Defines the electrical value associated with a discrete part,
which can be resistance, inductance, or capacitance. You
can define Value individually or for all instances of a part.
“IBIS Pin Type” on Displays the IBIS pin type for a pin instance.
page 406
“Schematic Pin Type” on Displays the schematic pin type for a pin instance.
page 407
“Topology Pin Type” on Defines the chaining pin type for a pin instance. Chaining
page 408 pin types are source, load, or terminator (S, L, or T).
“Pin Package Length” on Defines a pin's internal package length between the
page 409 substrate and dielectric layers of the component. This
constraint is commonly used to define wire bonding
length.
“Pin Package Delay” on Defines a pin's internal package delay between the
page 410 substrate and dielectric layers of the component. This
constraint is commonly used to define the delay for wire
bonding.

Table 1-14. Parts (cont.)

“Thermal Power Defines a part’s power dissipation as a subset of the total
Dissipation” on page 411 amount of power needed to run the component.
“Thermal Power Scaling Defines a part instance’s scaling factor with regard to
Factor” on page 412 power dissipation.
“Thermal Theta-jc” on Defines a part’s junction-to-casing thermal resistance.
page 413 This is also commonly referred to as die-to-package heat
resistance.
“Thermal Casing Defines a part’s maximum allowable temperature for the
Temperature Limit” on component casing or package.
page 414
“Thermal Junction Defines a part’s maximum allowable temperature for
Temperature Limit” on component junctions. A component junction is also
page 415 commonly referred to as a die.
“I/O Standard” on page 416 Displays the defined technology standard for an FPGA
signal net. When on the CES Spreadsheet Nets page, you
can define I/O Standard individually, or for all nets of a
constraint class.
Noise Rules Summary

Please refer to the following table for noise rule constraint quick-reference information.
Table 1-15. Noise Rules
“Noise Type” on page 418 Defines the noise type for a specific parallelism rule
and/or Crosstalk Max constraint and Crosstalk Level.
“Constraint Class or Defines the victim constraint class or electrical net of the
Electrical Net Name aggressor-victim relationship.
Victim” on page 419
“Constraint Class or Defines the aggressor constraint class or electrical net of
Electrical Net Name the aggressor-victim relationship.
Aggressor” on page 420
“Parallelism Rule” on Defines the parallelism rule for a class-to-class or net-to-
page 421 net parallelism relationship.
“Crosstalk Max” on Defines the maximum acceptable crosstalk that a net or all
page 422 nets within a constraint class can be subjected to as victim
nets. You can define Crosstalk Max individually or for all

Table 1-15. Noise Rules (cont.)

“Crosstalk Sim Actual” on Displays the actual value for Crosstalk Max based on ICX
page 424 Pro Verify calculations.
“Crosstalk Level” on Defines the signal state of the victim net in a crosstalk
page 425 relationship.

CES Work Flows
CES Work Flows

The two main work flows for CES are illustrated below. Although these work flows indicate the
typical order of constraint entry and modification for schematic and PCB engineers, your order
of operations may be different.
The following work flows are included:
• Schematic design – This work flow begins with creating and defining constraint classes,
which hold electrical, signal integrity, and high-speed signal integrity constraints. Along
the way, different types of constraint assignments are made. Some of these include
topology types, simulated delay rules, and overshoot and ringback requirements. The
final step is to send schematic constraint data to your layout design representation
through forward annotation.
• PCB layout – This work flow starts with creating and defining both rules-area schemes
and net classes. These groupings hold physical constraints for board layers and nets.
Along the way, different types of constraint assignments are made. Some of these
include trace and via rules, clearance rule sets, and package-type clearances. The final
step is to send layout constraint data to your schematic design representation through
back annotation.

CES Work Flows
Schematic-Design Work Flow

Click within the following illustration to view the topic for a specific step within this work
flow.
Figure 1-2. Schematic-Design Work Flow

CES Work Flows
PCB-Layout Work Flow

Click within the following illustration to view the topic for a specific step within this work
flow.
Figure 1-3. PCB-Layout Work Flow
Related Topics
• “CES Constraint-Driven Design” on page 47

CES Work Flows

Chapter 2
CES Overview and Setup
This section is an introduction to CES that provides an overview of CES and constraint-driven
design flows. It also includes information about invocation, setup, and application
customization. At a minimum, please make sure to read “Before You Begin Using CES” on
page 49. It includes important information for each PCB design flow that uses CES. Please refer
to the table of contents for the full listing of topics included in this section.
CES Constraint-Driven Design

Constraint Editor System (CES) gives you the ability to concurrently define and refine design
constraints in a common environment that is accessible from many Mentor Graphics
Corporation schematic entry and PCB layout design systems. By using CES, you can bridge the
gap between specific front-end and back-end design systems to efficiently streamline and
maintain the design constraints that result in bringing PCB solutions to market. All without
much of the costly research and development expenses that are associated with multiple design
revisions for a single product release.
Figure 2-1. Common Constraint Environment Resulting in Accurate Schematic

Design and PCB Layout Views
See also: Click within the above illustration to view related CES topics.
CES Constraint-Driven Design Flows

CES supports the following constraint-driven design flows:
• DxDesigner®-Expedition® PCB

CES Constraint-Driven Design
• Design Architect™ /Board Architect™-Board Station® XE

• Design Architect/Board Architect-Board Station RE
• Design Capture™/DesignView™-Expedition PCB
• Keyin netlist-Expedition PCB
Note
CES is only available in iCDB design flows. CES is not available in any DxDesigner
Netlist flows (for example, DxDesigner netlisting to Expedition PCB).
Concurrent Design Process

CES supports concurrent design process, which is the ability to have multiple engineers work
on schematic-entry or PCB-layout design constraints simultaneously. This means that a front-
end or back-end database can be modified at the same time by multiple engineers, and each user
sees the constraint changes made by other users in real time. Using a team approach, design
efficiency increases while design time is lowered. Forward and back annotation is still used to
communicate changes between schematic and layout design representations. For more
information, please refer to “Working Concurrently With Other Users” on page 121.
Creating PCB Rule Areas Through Rule-Area Schemes

Beginning with the Master scheme, rule-area schemes give you the ability to segment areas of a
board into distinct regions and then apply physical/manufacturing rules to each area using the
default net class in the Trace & Via Properties spreadsheet (Default) and the default rules in the
Clearances spreadsheet (Default Rule).
For example, when a certain area of a board contains many critical connections between
components, you can define a board area that encompasses this region, and then apply trace and
via rules (for example, trace width or number of vias) that promote signal integrity within this
critical board area. For more information, please refer to “Creating Rule Area Schemes” on
page 153.
Creating Net Classes to Group Rule-Area Nets More

Extensively
After you define (Default) class and (Default Rule) constraints for a rule-area scheme, which
creates the general constraint values for a scheme, you can create additional net classes within a
scheme to further group nets with physical requirements that are not fully satisfied by the
scheme's default net class constraints.
There is no limit to the number of classes, or hierarchical classes within a specific net class. You
can separate nets into increasingly constrained sub-groupings to implement requirements for

Before You Begin Using CES
nets that generate the most demanding signal integrity challenges. For more information, please
refer to “Creating Net Classes” on page 139.
Creating Constraint Classes to Group and Define Net

Constraints
Starting with the (All) constraint class, you can define net constraints and then create additional
constraint classes and hierarchical constraint classes under a particular constraint class. Unlike
net classes, which give you the ability to group and define board property constraints, you use
constraint classes to group and define electrical and signal integrity constraints such as net
properties, crosstalk estimations, and length or time of flight delays. For more information,
please refer to “Creating Constraint Classes” on page 145.
Verifying Design Constraints

When physical routing results are back-annotated from a router (for example, Board Station RE
or Expedition PCB) into CES, the physical routing results can be used to verify specific CES
constraints. Physical routing results that are brought into CES are called actuals.
When CES is connected in such a manner, the CES Constraint Spreadsheet is updated to include
the actual value/routing results as well as a clear visual indication of how well the constraint(s)
associated with an actual are performing. For example, when the actual delay for a net is too
close to either its minimum or maximum delay constraint, or exceeding either value, the CES
field that displays the actual is backlighted in red or yellow to indicate that the actual exceeds,
or comes close to exceeding, the constraint threshold. For more information, please refer to
“Validating Constraints Against PCB Actuals” on page 128.
Verifying Simulated Constraints

When you use ICX® Pro™ Verify as part of your constraint-driven design flow, you can
generate actuals for simulated constraints like edge-rate delays, and overshoot/ringback
voltages. On the CES Spreadsheet Nets page, the Simulated Delays and Overshoot/Ringback
constraint groups require ICX Pro Verify for actuals generation. For more information, please
refer to “Updating Electrical Net Data and Results” on page 133.

In preparation for using CES, please make sure that you are aware of the following general
considerations and requirements:
• Beginning with the 7.9.2 releases, the initial view of CES has been streamlined to
present you with just the core set of spreadsheet pages, toolbars, and navigator nodes.
All existing functionality is still available. For information on displaying spreadsheet

pages and toolbars that are no longer displayed by default, please refer to “Customizing
the Display of CES Windows” on page 79.
The first time you launch CES within a 7.9.2 release, your existing ces.ini file is created
as a backup in your WDIR folder with the filename ces.old.ini. In the event that you
want to restore CES to the custom view you had prior to the 7.9.2 release, you can
import this file with the File > Import > Settings menu selection.
• During invocation, CES checks to see if your WDIR variable includes at least one
writable location. When this requirement is not met, CES will not be launched, and will
provide a message box stating that “CES cannot be launched. At least one entry in the
environment variable WDIR must be a writable directory.” To fix this, you must adjust
your WDIR variable to include at least one writable location.
• When you launch CES on a read-only .prj file, CES will open in read-only mode. When
CES unexpectedly opens in read-only mode, you should check to ensure that the .prj file
is not flagged as read-only and is instead writable.
• In the event that CES reports an error message that includes a UID number (for example,
“507,692,52”), you should run CES Diagnostics to check constraints and attempt to fix
the error. For more information, please refer to “Checking Constraints and
Synchronization” on page 124.
• When your design includes them, single-pin nets are represented as a unified net called
“(Net0)-1:X”. You must access this special net when assigning Net0 nets to a constraint
class and net class, or when defining single-pin net constraints. For more information,
please refer to “Defining Constraints for Single-Pin Nets” on page 212.
• When rolling back constraint changes made in CES, the forward and back annotation
indicator lights for your design flow do not reflect these undo actions. For example, after
you make a single change in back-end CES and then rollback that change, your back-
end system will still indicate that you need to perform back annotation.
• In the event that you receive the following message (or a similar message): “Violations
in the iCDB have been detected. Affected objects and constraints will remain disabled in
the CES user interface. Please contact Customer Support for assistance.” You must
contact customer support to resolve the database issue and return to your normal CES
operating environment.
• Depending on the design flow you are using, the invocation tool from which you
launched CES may or may not save your changes by default. In order to keep from
losing CES data, please ensure that you understand the unique save process of your
design system, and use it appropriately to save CES constraints within each applicable
session. For example, DxDesigner automatically saves schematic data and CES
constraints, but PCB layout tools require an explicit save before they will write PCB
layout changes and CES constraints to disk. When making CES change in a session
launched from a PCB layout tool, it is important understand the following:

o All changes made in CES are reflected in the layout invocation tool after you exit
CES.
o You can send pending CES changes to the layout tool during the active CES session.
To do so, at the bottom-right corner of your PCB layout tool, click the rightmost
status indicator to load the changes into the back-end.
• When working in CES sessions launched from Expedition PCB, you cannot change
reference designator prefixes through the CES settings dialog box. To update these
prefixes in your back-end CES database, please modify them in a CES session launched
from the front-end, and then forward annotate.
• A constraint cell will show ‘#’ when the precision is too low to display a meaningful
value. For example, 0.000435 V shows ‘#’ when the precision is set to 3. With precision
set to 4, it shows ‘0.0004’. To set precision, please refer to “To Set Notation” on
page 68.
• When exporting constraints, CES uses the native concurrent unit type. When
reimporting constraints into CES, you must set the unit type afterward.
• This version of CES includes the following additional keyboard shortcuts:
o To highlight all data on a spreadsheet page, press Ctrl+A.
o To switch between dockable windows, press Ctrl+Tab.
• In this version, z-axis clearances are not applied between segments of the same net.
• For this version, only I/O Standard is accessible and modifiable through CES. All other
I/O Designer constraints are not available for this version.
• An electrical net will not be created when both ends of a series component (for example,
resistor) are connected to the same instance of a device.
• For this version, cross probing will not work correctly when multiple cross probe servers
are running. To make sure that just one cross probe server is running, turn on cross
probing from CES (Setup > Cross Probing) or the schematic or layout design tool from
which you launched CES.
Differential Pairs Conversion

When CES converts differential pairs between CES database formats, some differential pairs
may not convert successfully; however, they are preserved in the old format and are still valid.
In the event that this occurs, CES provides a dialog box that indicates that some differential
pairs could not be converted, and CES has marked these with the pin icon. In order to redefine
one or more of these differential pairs, you must delete them.

Note
You do not need to redefine differential pairs that could not be converted to the 2007 CES
database format. Although CES preserves these differential pairs in the previous format,
they are still applicable to your 2007 design.
Figure 2-2. Differential Pair That was not Converted
When deleting differential pairs marked with a pin icon, another dialog box is displayed that
indicates that each net that comprises the differential pair might be merged into another
electrical net, removing the ability to recreate the current differential pair.
Importing a Layout Template

When your design data is limited to just schematic data, you can import a layout template into
CES sessions launched from your front-end design system. For example, a DxDesigner design
with no back-end data is a candidate for this import option. Doing so is useful when a logic
engineer wants to define physical constraints based on an accurate board-layer configuration
before the first forward annotation has occurred, or a back-end design exists at all.
To Import a Layout Template

1. From the File menu, click Import, and then click Layout Template.
2. From the Import Layout Template dialog box, next to Select layout template, click the
dropdown, and then click the template you want to use.
3. After you are sure of your selection, click OK.
Caution
After you associate a layout template with your design, whether through this procedure or
in your PCB layout design system, when you load the design in CES, the Output window
displays information about the layout template. This information includes the number of
layers in the template. It is important to understand that this information does not
necessarily reflect the actual number of layers, or other stackup information for the actual
design. You will get the same report even if you make changes to the stackup.
Importing a 2005.x Ces.prefs File

In versions of CES prior to 7.x, CES stored some settings in a preferences file called Ces.prefs
that was written to the top level of your WDIR location. To make the transition between a
2005.x release and 7.x easier, you can import your preferences file into CES 7.x. It is important

to note that CES no longer writes this preferences file. Importing a Ces.prefs file is intended to
be an optional, one-time transition step between releases.
To Import 2005.x CES Preferences

1. From the File menu, click Import, and then click Preferences File.
2. From the Open dialog box, navigate to the .prefs file that you want to load, and then
click OK.
DxDesigner-CES-Expedition PCB
When using this flow, please be aware of the following considerations and requirements:
• You must have a DxDesigner concurrency license (dxconcurrent) in order to use

multiple copies of DxDesigner-CES or standalone CES on the same design.
• You can only define the Plane to Plane constraint at the (Master) scheme level. You
cannot define it for user-created schemes or rule areas. For more information about this
constraint, please refer to “Plane To Plane” on page 316.
Keyin Netlist-CES-Expedition PCB

When using a keyin netlist to represent design connectivity instead of traditional schematic
capture data, forward annotate before you begin using CES to modify constraint data. Aside
from standard communication of design changes, you only have to perform this step once. You
can do so before or after you enable CES in a keyin netlist flow.
Expedition TeamPCB and XtremePCB

TeamPCB (used for concurrent PCB design) and XtremePCB (used for dynamic/interactive
group PCB design) are integrated to use CES in this release. However, CES has limited support
with TeamPCB. Constraints you define using CES are carried forward to the split designs.
When you are editing a split design, you can change constraints on the Trace & Via Properties
and Clearance tabs inside CES. However, that information only applies to the current split
design and will not be joined with the main design. Other tabs within CES are not editable
inside a split partition.
Understanding Electrical Nets and Physical Nets in CES

It is important to understand that CES automatically populates the Nets spreadsheet with
electrical nets and physical nets based on the following definitions that are unique to CES:
• Physical net (pNet) – A physical net ( ) is a net where all pins of the net are connected
by a trace, via, or plane segment.

• Electrical net (eNet) – An electrical net ( ) is made up of one or more physical nets that
are connected together logically or electrically through (usually passive) components.
Electrical nets are automatically created by CES when you invoke it. A common
example of an electrical net containing two physical nets is one where Net A and Net B
are connected through a series resistor. Electrically, the signal on Net A goes through the
resistor and continues on through Net B as if it were all one net. The most trivial case of
an electrical net is a single physical net that is not connected to any other physical nets
through passive components.
Electrical nets that include two or more physical nets are indicated as such on the Nets
page of the CES Spreadsheet. A ^^^ suffix is added to the end of the net name as it
appears in the first column (Constraint Class/Net/*).
Note: An electrical net will not be created when both ends of a series component (for
example, resistor) are connected to the same instance of a device.
Definitions for other objects like differential pairs, components, and terminators are not unique
to CES.
Automatically Recognized Topologies

CES automatically recognizes two termination strategies when considering differential pairs
within the context of electrical nets. In these cases, some connections are ignored, resulting with
orphaned physical nets. In both of the following cases, the connections are ignored so that the
two poles of the differential pair can remain separate, allowing for the differential pair to be
recognized:
• Standard parallel termination – When the two poles of a differential pair are joined
through a resistor, the resistor connection is ignored by CES. Doing so keeps the two
poles of the pair from being joined into a single electrical net.
• Alternative parallel termination – When the two poles of a differential pair are joined
through two resistors (with a capacitor taking the net to ground), the connection through
the resistors is ignored by CES. Doing so keeps the two poles of the pair from being
joined into a single electrical net.

Starting and Exiting From CES
Figure 2-3. Differential Pair Topologies Automatically Recognized by CES
In both of the above cases, the receiving component is determined to be a differential receiver if
the component has an IBIS model that contains a diff pin statement for the pin; or, the
component has no IBIS model but two inputs exist on the same symbol or part instance, and the
inputs are connected by a signal resistor or a pair of resistors in parallel.
Electrical Nets Defined Through a Package With More

Than Two Pins
CES will create electrical nets through parts with more than two pins when both CES, and the
part are configured correctly. For example, you could set up a 4-pin resistor pack for this usage.
In order for CES to do this, the following requirements must be met:
• The reference designator prefix for the part must be defined as an available discrete
component prefix (for example, RN).
• You must define pin pairs across the entire part. For example, when the part has four
pins, two pin pairs must be defined. Doing so maps the pins so the route through the
resistor pack is known. For more information, please refer to “Defining Discrete
Component Pin Pairs” on page 191.
• The CES Spreadsheet Parts page Series constraint is set to enabled/on for the part.

Because CES is a design constraint system that can be used to display and modify the design
constraints produced by and intended for many of Mentor Graphic Corporation's front-end and
back-end PCB design solutions, you can start CES through a host of MGC applications. Please
refer to the table below to determine the command you must use to launch CES from an
associated MGC PCB design tool.

When users invoke multiple CES sessions from the same design tool on the same design, all
sessions are read-write. For example, after you launch CES from DxDesigner, your co-workers
can launch CES from the same DxDesigner design and concurrently make changes. This is
especially useful for large designs that require multiple schematic and layout designers working
simultaneously on each end.
Prerequisites
• Your WDIR environment variable must include at least one writable location or
directory. CES will not launch until you satisfy this requirement.
To Start CES
Refer to the following table to launch CES from one of the following schematic capture or PCB
layout design tools.
Table 2-1. Starting CES

Design Tool Menu Path
Design Capture Tools > Edit Constraints
DesignView Workspace > Integration
View tab > Constraints
DxDesigner Tools > Constraint Editor
System
Expedition PCB Setup > Constraints
Results
CES opens and displays the constraint set for the front-end or back-end design. When the .prj
file for the design is read-only, CES opens in read-only mode as well.
Starting CES in Standalone Mode

You can start CES in standalone mode (independently), from both the Windows Start menu and
the Mentor Graphics Dashboard. Please refer to the procedures below for the appropriate
instructions.
To Start CES From the Start Menu

1. From the Start menu, in your Mentor Graphics program folder, expand Constraint
Entry, and then click Constraint Editor System.
2. From the Open Project dialog box, browse to the .prj file for your design, and then click
Open.

To Start CES From the Dashboard

From the Mentor Graphics Dashboard, with a project actively selected, expand Board-Level
(PCB) Design Toolbox, and then double-click Constraint Editor System.
To Exit From CES

From the CES main window, click x, or from the File menu, click Exit.
Viewing Constraint Database Log Files

CES uses a database to interact with the host design system and any available concurrent users.
To view the associated log files, from the File menu, click File Viewer.
Tip: To learn more about using the File Viewer, from its Help menu, click Contents.
Folder Structure and Location of CES Log Files

CES log files (.log) are created and written within each design folder, using subfolders to
distinguish between the concurrent snapshot name, block name, machine name, and user name.
Within each log file folder, you will find log files named based on the date and time that the
CES session was started. Each time CES is closed and reopened, a new set of log files is added
to the directory. Please see below for the individual directory structures that exist for front-end
and back-end CES sessions.
Schematic Log Files Folder Structure

<design_folder>\CES\LogFiles\<snapshot_name>\<block_name>\<machine_name>\<user_
name>
Example: C:\Phone_design_1\CES\LogFiles\DxD\keypad\psmith-lt\psmith
For DxDesigner only, in the event that fromtos and/or pin pairs cannot be copied while copying
or updating a reuse block, or when copying sheets, one or both of the following log files are
written to capture the missing fromtos or pin pairs:
• MissingFromtos_<time/date stamp>.log – You can use this log file to determine which
fromtos are now missing from CES due to an action performed in DxDesigner.
• MissingPinpairs_<time/date stamp>.log – You can use this log file to determine which
pin pairs are now missing from CES due to an action performed in DxDesigner.
Layout Log Files Folder Structure

name>

Cross Probing Between Design Systems and CES
Example: C:\Phone_design_1\CES\LogFiles\keypad_Layout_Temp\keypad\psmith-lt\psmith
Cross Probing Between Design Systems and

CES
You can enable cross probing between CES and the design system from which you launched
CES. Cross probing, also known as cross select, works in a bi-directional fashion. When you
select a design object in your schematic capture of PCB layout design system, the design object
is also selected in CES. Selecting a design object in CES results in your design system making
the same selection.
Tip: You can set up CES to enable cross probing by default. To learn how to do this,
please refer to “Setting Up CES” on page 59.
Regardless of your level of experience with CES and its spreadsheet display of design objects
and constraints, cross probing is usually the most efficient method of selecting design objects.
In terms of precision, it is the most accurate way to ensure that you are modifying constraints of
the appropriate target net.
To Cross Probe From Your Design System to CES

1. From the Setup menu, click to enable Cross Probing.
Alternative: From the General toolbar, click .
2. In your schematic capture or PCB layout software, click a design object (for example,
net or component).
Result: The design object is selected in CES.
To Cross Probe From CES to Your Design System

1. From the Setup menu, click to enable Cross Probing.
2. From the CES Constraint Spreadsheet, click the leftmost column of a design object. or
press Ctrl+J to select the current row.
Example: In the following illustration, the PCI constraint class is selected for cross
probing.

Setting Up CES
Figure 2-4. Cross Probing From CES
Cross Probing From the Navigator

When enabled, you can also cross probe from the Navigator to select all nets that are part of a
hierarchical object like a constraint class or net class. When you do so, your invocation tool will
select all associated nets from within your logic or layout environment.
Setting Up CES
You can specify CES options to customize the most appropriate CES environment for a design.
These settings, as well as the settings associated with the units that are displayed within the
spreadsheet editor, are unique to each design that you work with in CES. Because CES saves
settings as part of each design, you have the ability to maintain custom settings for each design
that you work with in CES.
Specifying Design Preferences

You can specify design configuration preferences such as default tolerances for time and
distance delay, the parallelism mode to use, reference designator prefixes, and voltage
assignments for power nets. Design preferences are settings that affect an entire design rather
than specific design objects (for example, layers or nets).
Note
As an alternative, you can use a configuration file to specify some preferences. For more
information, please refer to “Using a Configuration File to Specify Design Preferences”
on page 63.
To Set Design Configuration Preferences

1. From the Setup menu, click Settings.
2. From the Settings dialog box, click Design Configuration.
3. Under Default tolerances, specify a default physical and electrical tolerance for delay.
This is the allowable deviation for any delay constraints you define in CES.
4. Under Parallelism mode, specify whether the router should report parallelism hazards
cumulatively, or separately for each segment. When in cumulative mode, each segment

Setting Up CES
that comprises a group will report a hazard. For example, when the parallel run length
needs to be less than 400th, and each of the three segments in a group are 134th, each
segment will show a violation although they all appear to be 266th shorter than required.
The violations are reported because the sum of 134th + 134th + 134th is 402th, which is
greater than 400th.
Note: For cumulative calculations, segments smaller than 100th are ignored and not
used to produce the cumulative length. Using the above example, five 98th segments
result in a mathematical total of 490th, but because each segment is less than 100th, all
are ignored by the router and no hazard would be reported.
5. Under Pin Package, in the Propagation Delay field, modify the velocity value as needed
to reflect an accurate signal speed through pin package connections. This value is used
in conjunction with the Pin Package Length constraint of the Parts page to calculate Pin
Package Delay, when requested. (The default value is 0.000165 ns/th.)
6. To change the number of seconds a user can reserve a constraint cell for editing while
working concurrently, in the Maximum locking timeout field, enter a different value.
7. After you finish, click OK.
To Specify Electrical Net Preferences

Note
You can only modify electrical net preferences when in a CES session launched from the
front-end or standalone CES.

2. From the Settings dialog box, under Design Configuration, click Electrical Net.
3. Specify the maximum number of physical nets that may comprise an electrical net. This
setting controls the number of electrical nets that are automatically created when you
invoke CES. Using too low of a setting may cause CES to create too many electrical
nets. Too high of a setting could cause CES to create too few electrical nets, each of
which contains many physical nets. For more information, please refer to
“Understanding Electrical Nets and Physical Nets in CES” on page 53.
4. Specify the net pin count threshold to use to determine whether a net is potentially a
signal net or a power net.
Tip: Identify the power net in your design with the smallest number of pins, and then set
this value to that number minus one. For example, if the smallest power net in a design
contains 30 pins, set this value to 29. In some cases, the default value of 25 might be too
high. In the event that a power net includes just 20 pins, you would need to set this value
to 19. Otherwise, the power net would show up on the Nets page of the CES
Spreadsheet.

Setting Up CES
5. Specify whether IBIS part models should be used for electrical nets.
6. For component names, specify whether IBIS names (for example, icx_part_model)
should be used for mapping purposes. By default, the part model name is used.
To Specify Discrete Component Prefixes

Note
You can only modify discrete component prefixes when in a CES session launched from
the front-end or standalone CES.

2. From the Settings dialog box, under Design Configuration, click Discrete Component
Prefixes.
3. Specify all possible reference designator prefixes for the parts in your design. Please
keep the following things in mind:
• When your design flow includes reuse blocks, you must include special reference
designator prefixes that support reuse blocks. They are of the format #_<type>. For
example #_R supports resistors in reuse blocks, and #_C supports capacitors in reuse
blocks. To be safe, for each prefix that you have defined, you should also include an
additional prefix in this format.
• When your design uses reference designators that are of the format YYYRNN
(schematic sheet, reference designator prefix, unique instance), append a # to each
discrete component prefix that you define here. For example, instead of using just C
to define the discrete component prefix for capacitors, use #C.
• When a part type has instances with multiple reference designators, CES determines
that a part is a discrete if at least one of the refdes prefixes is specified. For example,
part type RES has instances R1 -> R10 and X1 -> X10. When either R or X are in the
list, the part and its instances will all be considered resistors.
In the following example illustration, each discrete component has at least two defined prefixes.
Connectors have three prefixes: P, J, and PJ. Resistors have four prefixes: R, RR, RN, and RP.

Setting Up CES
Figure 2-5. Example Reference Designator Prefixes
Note
After you finish modifying discrete component prefixes, CES automatically re-generates
electrical nets. In order to update layout, you must package the design and forward
annotate.
2-Pin Schematic Symbols

Resistor packs with 2-pin schematic symbols are properly identified as series connections.
When you are using the DxDesigner-Expedition PCB constraint-driven design flow, any
combination of 2-pin or full-pack symbols are identified as series devices. In the other flows
(for example, Design Architect-Board Station XE), you must use 2-pin schematic symbols to
ensure CES recognition.
To Specify Powers and Grounds

2. In the Settings dialog box, under Design Configuration, click Powers and Grounds.
Tip: You can modify the voltage value for an existing power net or ground net by
clicking within its Voltage field to change it. To delete one or more existing power net
or ground net designations, use click, Ctrl-click, or Shift-click, and then click .
3. To create one or more power nets or ground nets, click .
4. From the Select Power Nets dialog box, enter a net name filter, or leave the default entry
(*) to select from all nets, and then click .
5. From the list of proposed nets, click the check box associated with each power net or
ground net you want to add, and then click OK.
Tip: To select all listed nets, click . To unselect all nets, click . To clear your list of
selected nets and restart the net selection process, click . Nets with a pin count that
exceeds the threshold will be selected automatically.
6. For each power net or ground net you chose, enter a Voltage value.

Setting Up CES
Example: Each ground net will typically require a voltage value of 0.0000.
7. For each power net you chose that requires constraints, select Visible.
Using a Configuration File to Specify Design Preferences

As an alternative approach to specifying design preferences through the CES GUI, you can use
a preferences file (.prefs) to define some of these design characteristics. For example, you can
specify power and grounds nets, the numerical pin threshold for determining whether a net is a
signal net or a power net, and reference designator prefixes.
Prerequisites
• None.
Procedure
1. Exit CES.
2. In an ASCII text editor, create a file named ces.prefs.
3. Copy and paste the content of the example preferences file below into your ASCII text
editor.
4. Modify the example content in your ASCII text editor to specify appropriate values.
5. Save ces.prefs to your WDIR location.
6. Restart CES.
Results
CES will now read any defined preferences from this file instead of GUI definitions that you
had specified previously.
Example ces.prefs File

(preferences
(section CES
(pref DSN_POWERS "+12V=12.0" "+5V=5.0" "-12V=-12.0" "-5V=-5.0"
"GND=0.0" "VCC=5.0" "VDD=5.0" "VEE=-5.2" "VSS=0.0" )
(pref DSN_MAXENETS 10)
(pref DSN_BIGNETPINCOUNT 50)
(pref DSN_DEF_DISTANCE_TOL 254000)
(pref DSN_DEF_TIME_TOL 0.015)
(pref DSN_DISCRETES "RESISTOR=R,RN,RP" "CAPACITOR=C"
"INDUCTOR=L,FB" "DIODE=CR,D" "CONNECTOR=J,P")))

Setting Up CES
Setting Display Options

Please use the procedure below to set display options for CES.
To Set Display Settings

2. From the Settings dialog box, click Display.
3. Under Window Settings, specify whether CES should crossprobe between itself and
schematic-entry or layout, by default.
Note: When setting display options for CTE, Set the default crossprobing mode to ON is
intentionally grayed out and not available.
4. To turn on cross probing from the Navigator, click to enable its checkbox.
5. Click to enable row, column, or header highlighting and indication of remotely modified
cells. Both are useful when working concurrently.
6. To show row numbers, click to enable the associated checkbox.
7. Enable or disable Show scrolling buttons for tabs to include the left and right arrow
buttons next to the tabs you use to select specific CES Spreadsheet pages.
8. Enable or disable the CES splash screen by clicking the appropriate checkbox.
9. To automatically show differences between parent and child objects, click to enable the
associated checkbox.
Setting General Options

Please use the procedure below to set general options for CES.
To Set General Options

2. From the Settings dialog box, under Display, click General.
3. Under Initial Zoom Level, specify the default size of spreadsheet fonts and rows by
entering a percentage value. As you increase this value, the size of spreadsheet fonts
increase.

Setting Up CES
4. Under Inactive Draw Combobox Buttons, specify when CES should display
comboboxes within a spreadsheet field. When you enable this option, any cell that can
display a dropdown list will always display the down arrow box. When disabled, the
dropdown box for a cell is displayed after you click within the respective cell.
5. Under Spin Edit Control, specify whether integer value spreadsheet fields should
display up and down arrows beside them when clicked. These arrows are used to
increase or decrease the integer value within a cell without using the keyboard.
6. Choose the preferred action of the LMB when you double-click it. You can choose
expand cell, rename cell, or no action.
7. Choose the preferred action that occurs after you press the Enter key within a cell. You
can choose to move to up, down, left, or right from the current cell.
8. Under Tolerances, specify the following values:
• Design tolerance of CES constraints compared against actual back-annotated design
values. In the Constraint violation warning field, enter a percentage value.
Example: When the Constraint violation warning field contains 90%, actual values
that are ninety or a greater percentage of the associated constraint value are
highlighted in yellow to indicate an actual that is close to the acceptable constraint
value. When the actual value exceeds the constraint value, the field is highlighted in
red.
• Acceptable threshold CES uses when applying constraint templates to nets. In the
Template match threshold field, enter a percentage value. For less similarity, reduce
this value; for more similarity, increase this value.
9. Under Change Impact Dialog, specify what should happen when you attempt to change
a child constraint override at the parent constraint level:
• Change all affected values – Replace all child values with the value entered at the
parent constraint level. Does not show the Change Impact Prompt dialog box.
• Keep all overrides but change others – Replace only the child values that match the
old parent value. Does not show the Change Impact Prompt dialog box.
• Always prompt user for all values – Prompt for all values using the Change Impact
Prompt dialog box, whether the current value is an override or not.
Note: For more information on how these settings affect your constraint editing
environment, please refer to “Choosing From Among Change Impact Actions” on
page 101.
To Set Fonts and Colors


Setting Up CES

2. From the Settings dialog box, under Display, click Fonts and Colors.
3. Specify the header font and cell font appearances for defaults, constraints, and
properties.
4. Specify the header font, cell font, and background color appearance settings for actuals,
read-only values, static values, and disabled cells.
5. To help you identify changes made by concurrent CES users, specify background colors
and cell fonts for edited cells and locked cells.
6. To change the appearance of cells you modify from within CES, change the current
settings for Modified cells.
7. Specify the background cell color used to indicate violations of type caution or error.
8. Specify the background color for other/hierarchical items like Different, Default Value,
and Override Value.
9. Specify the color used to indicate the presence of a comment mark.
10. Specify the color and font used to display content in the CES Output window. Although
the heading for this column of the dialog box states that all colors are background colors,
Font, Error, Warning, and Path rows are used to set textual colors.
Setting Units for the CES Spreadsheet

You can specify the units CES displays for the different types of constraint data. When you set
these units, CES uses your preferences to format the display and entry of values into CES. The
design units you use in a specific front-end or back-end system are not modified by units setting
that you make in CES. Because units that you specify for a design in CES are used on a design-
by-design basis, you can use different units for each design that you work with in CES.
In addition to setting the units to use and display, you can also specify the precision and format
of electrical units that CES displays. For example, you can use engineering notation with a
precision of three digits after the decimal point, scientific notation with two digit post-decimal
point precision, or choose not to format electrical units and display full precision.
To Set Display Units

2. From the Settings dialog box, under Display, click Display Units.

Setting Up CES
3. From the Display Units page, for each unit type, specify the unit and precision that you
want to use. Please refer to the table below if you need help determining the meaning of
a specific unit.
Example: For linear values, to use millimeters, click within its Unit field, and then click
to select mm.
Result: After you modify the unit and precision for a specific unit type, the associated
Example field updates to show you a preview of the display unit setting as values will
appear in the CES Spreadsheet.
4. Optionally, to keep your units synchronized with the back-end design system, click to
enable the check box.
Table 2-2. Available Display Units

Unit Type Unit
Linear You can choose from the following units:
• in – inch
• th – thousandth of an inch
• mm – millimeter
• um – micrometer
• nm – nanometer
Angle You can choose from the following units:
• deg – degree
• rad – radian
• ' – foot
• " – inch
Capacitance You can choose from the following units:
• F – farad
• mF – millifarad
• uF – microfarad
• nF – nanofarad
Voltage You can choose from the following units:
• kV – kilovolt
• V – volt
• mV – millivolt
• uV – microvolt
• nV – nanovolt

Setting Up CES
Table 2-2. Available Display Units (cont.)

Unit Type Unit
Inductance You can choose from the following units:
• H – henry
• mH – millihenry
• uH – microhenry
• nH – nanohenry
Power You can choose from the following units:
• kW – kilowatts
• W – watts
• mW – milliwatts
• uW – microwatts
• nW – nanowatts
Velocity You can choose from the following units:
• in/ns – inch per nanosecond
• m/s – meter per second
• %c – percentage of the speed of light
Resistance You can choose from the following units:
• MOhm – mega-ohm
• KOhm – kilo-ohm
• Ohm – ohm
• mOhm – milli-ohm
• uOhm – micro-ohm
Time You can choose from the following units:
• s – second
• ms – millisecond
• us – microsecond
• ns – nanosecond
• ps – picosecond
Current You can choose from the following units:
• A – ampere
• mA – milliampere
• uA – microampere
• pA – picoampere
Temperature This unit type is expressed in degree Celsius (degC).
Theta This unit type is expressed in degree Celsius per watt
(degC/W).
To Set Notation

Setting Up CES
2. From the Settings dialog box, under Display, click Notation.

3. From the Notation page, under Electrical units, specify the format and precision you
want to use for electrical units.
Example: To use SPICE format with a precision of 5, click the radio button next to
SPICE, and in its associated Precision field, enter 5.
Rule: When you do not want to format electrical units and want to use full precision,
click the Do not format electrical units and use full precision check box.
Rule: When the precision is too low to display a meaningful value, a constraint cell will
display ‘#’ instead of a number.
4. Under Regional settings, specify the decimal point symbol to use, the number of digits
to display after the decimal point, and other associated electrical unit display properties.
5. To suppress the display of trailing zeros, click to activate the Suppress trailing zeros
check box.
Example: When using engineering format with a precision of 5, a spreadsheet value of
8.12300 would be displayed as 8.123. Without suppressing trailing zeros, all five post-
decimal values are displayed.
Specifying Other Preferences

Please use the procedure below to set additional options for CES.
To Specify Other Preferences

Note
You can modify certain actuals preferences when in a CES session launched from the
back-end. The remaining preferences must be modified from a front-end CES session.

2. From the Settings dialog box, click Other.
3. To have CES automatically display updated actuals produced by your layout tool during
interactive routing, under Actuals, activate the Layout Dynamic update checkbox.
Note: To do the same for thermal actuals, click to enable Thermal Dynamic update.
4. To automatically update actuals upon CES invocation, under Actuals, activate the Auto
update on start up checkbox.

Setting Up CES
5. To automatically export actuals to schematic capture for display in CES, under Actuals,
click to enable Export actuals to front-end. Actuals are exported each time they are
updated, whether manually or automatically.
6. To show alerts in CES front-end sessions that updated actuals can be imported, under
Actuals, click to activate the appropriate checkbox. When this option is enabled a small
message will appear above the CES Spreadsheet each time new actuals become
available.
7. To automatically run CES diagnostics upon exit, activate the associated checkbox.
8. To automatically update nets that use a constraint template when any of the constraint
template values are updated, click to activate Automatically apply templates. When
activated, you never need to re-apply constraint templates to individual nets to which
they are assigned.
9. To store log files generated during your CES session locally at your WDIR location,
click to enable the appropriate checkbox.
Note: By default, this checkbox is enabled. When you disable this checkbox, log files
are stored in the project directory for the design.
10. To modify existing custom spreadsheet pages and create new ones, activate Enable
custom tab modification.
11. When cross probing from CES, to have your logic or layout tool select no more than a
maximum number of nets, enter a value in the Maximum number of selected nets field.
12. Specify how old a log file needs to be before archiving it.
Reusing Settings in External Designs

You can reuse your CES environment settings in other designs. You do so by exporting to a file,
and then importing that file in any external CES session. This is useful for maintaining the
workgroup standards of a large design team, or reusing your own design settings.
To Reuse Settings
1. From the File menu, click Export, and then click Settings.
2. From the Export Settings dialog box, specify a path and filename, and then click Save.
3. Optionally, communicate this settings file (.ini) to other engineers.
4. In any external CES design, from the File menu, click Import, and then click Settings.
5. In the Import Settings dialog box, select the settings file saved previously (for example,
workgroup.ini), and then click Open.

Modifying Simulation Settings and Stimulus
Deploying Corporate CES Settings

Another use for exportation of a settings file is to place it in a corporate WDIR location to which
all users on a design team point. By placing the settings file at the corporate/public location, you
can easily deploy the same CES settings to all users on the team. To do so, after you export the
settings file, rename it to ces.ini, and then place it in the corporate WDIR location. In order for
each user machine to consume these settings, each user must delete any ces.ini files that are in
their local WDIR directories.
It is important to understand that at any time after the corporate ces.ini file is consumed, when a
user saves changes to their CES settings, a local ces.ini file will be written to their local WDIR,
and supersede the corporate file. Depending on how your design team might use a corporate
ces.ini file, you could have to create and communicate explicit policy instructions regarding
modification of CES settings.
For example, one usage would be to place a corporate ces.ini file, but also expect users to
change some settings as part of their local CES environment, and therefore have a local ces.ini
written to their machine. With this approach, all settings would be the same initially, but over
time specific settings could be customized by each user as they require.

When you use ICX Pro Verify as part of your CES constraint-driven design flow, you can
modify the simulation stimulus and settings used by ICX Pro Verify to generate actuals data that
are displayed on the CES Spreadsheet Nets page (Simulated Delays group and
Overshoot/Ringback group). The Noise Rules page also displays an ICX Pro Verify simulation
actual as the Crosstalk Sim Actual cell. Aside from modifying existing simulation templates and
stimulus, you can also create new ones.
Note
In order to modify simulation settings and stimulus, you must be using ICX Pro Verify
within your design flow.
Common Tasks
• “Modifying Simulation Stimulus” on page 77
Modifying Simulation Settings

You can modify simulation settings used by ICX Pro Verify to alter measurement, simulation
engine, coupling, and corner-case simulation options. For example, you can choose among
ADMS, ICXSIM, and HSPICE simulation engines while allowing for simulator substitution,
when appropriate.

To Modify Simulation Settings

1. From the Edit menu, click Simulation, and then click Simulation Settings.
Note: When the CES Spreadsheet Constraint Templates page is active, you must make
another page active to enable these menu options.
2. From the Simulation Settings dialog box, modify any appropriate settings. After you
finish, click OK. Refer to the tables below for a description of each option.
Please refer to the following table for simulation settings.
Table 2-3. Simulation Settings (Measurement Tab)

Option Description
Start cycle Determines which pulse is used to start the measurement.
The valid start cycle is an integer between 1 and 300.
End cycle Determines which pulse is the last measurement point.
The valid end cycle is an integer between 1 and 300 and
must be larger than the start cycle value.
Edge The edge is selected by using the dropdown arrow and
selecting Rising, Falling, or Both from the drop down list.
Corner case Gives you the ability to select the corner case within the
symbol model. If not selected, the model determines the
corner case.
Total crosstalk only A single simulation is used to measure crosstalk on the
victim net. During the simulation, all aggressor nets are
actively driven.
Total plus individual The simulation described in the first mode is used to
contributions measure total crosstalk for each of the specified victim
states. If there is more than one aggressor, simulations are
performed to find the crosstalk due to each aggressor. In
these simulations, only the aggressor whose contribution
is to be measured is transitioned, all other aggressor nets
are tri-stated or driven to a fixed logic level. In these
simulations, drivers on the driven nets are selected as in
the first mode.
Victim logic states Defines the victim logic states simulated during crosstalk
analysis.

Please refer to the following table for coupling settings.
Table 2-4. Simulation Settings (Coupling Tab)

Option Description
Include trace to trace If checked, Delay and SI simulation include nets that are
coupling electrically coupled to the target net for simulation.
Pin to Pin If this option is checked, coupling within the package of
devices are modeled during simulation. To use this feature
successfully requires the device to have an IBIS model
that utilizes a separate package section or file to provide
mutual inductances and capacitances between pins.
Self-coupling If this option is checked, any coupling between traces is
modeled in the simulation, and they are evaluated during
simulation. Self coupling has a significant effect for traces
that double back upon themselves (serpentines). The
disadvantage of this option is that it increases simulation
effort.
Arbitrary angles If this option is unchecked, the simulator assumes that
traces that are not parallel to each other are not electrically
coupled. If this option is checked, the electrical coupling
for traces that are in close proximity (as defined by the
remaining settings) but not parallel are modeled. Enabling
this option increases trace-modeling accuracy for traces
that are not parallel or at ninety degrees. It also
significantly increases the amount of processing that must
be performed when the trace geometries are extracted and
add additional elements to the circuit that must be
simulated, both of which increase the simulation effort.
Consider nets within Only the nets within the specified distance are considered
for electrical coupling. The values in this field is validated
as being positive and less than 500 (th).
Ignore segments shorter Any aggressor net segments that are shorter than this
than length are ignored during crosstalk simulation of the
analyzed net.
Trace to area fill coupling Enabling this feature improves the accuracy of trace
modeling and increases trace extraction and simulation
times.

Table 2-4. Simulation Settings (Coupling Tab) (cont.)

Option Description
Stimulus for neighboring This setting has the following selections:
nets
• Passive – Neighboring nets are held at a fixed state. If
all the drivers on a neighboring net are tri-stated, the
neighboring net is not driven. If they cannot be tri-
stated, the neighboring nets are low logic state.
• Switch with – Neighboring nets are driven with the

same stimulus as the net being simulated.
• Switch against – Neighboring nets are driven with the

opposite stimulus as the net being simulated.
• Independent – The neighboring net uses the stimulus

specified when it is a target net. This option is used
when the Simulation Control dialog “Simulation
settings” field, “Use CES net spreadsheet” radio
button is selected. In this case each target net can
independently be assigned an appropriate stimulus.
Please refer to the following table for additional simulation settings.
Table 2-5. Simulation Settings (Settings Tab)
Option Description
Simulation engine This setting has the following selections:
• Auto – The system attempts to use the fastest

simulator that is compatible with the available models.
• Fixed – This radio button enables the dropdown list to

be displayed (ICX Sim, ADMS, and HSPICE). From
the dropdown list, select the simulator. If at simulation
time the simulator cannot be used, an error message is
reported in the Simulation Status dialog box.
Simulation resolution This setting has the following selections:
• Auto – The system determines the time step for the

simulator based on heuristics that include the fastest
driver nominal edge rate obtained from the IBIS
models of the selected nets.
• Fixed – You must enter the simulation time step value.

This value must be a positive, real number from 0 to
less then 1000 with no more than two decimal places.

Table 2-5. Simulation Settings (Settings Tab) (cont.)

Option Description
Simulation run time This setting has the following selections:
• Auto – This option allows the system to determine the

simulation run time. The system ensures that the
simulation run time is as long as it is required to
simulate all specified measurement cycles. The tool
also adds additional simulation time for the net to
settle to a reasonably steady state. This additional time
is chosen using a heuristic that takes in to account the
total time of flight for the net.
• Fixed – The option allows you to specify the

simulation time as an absolute value.
Modeling of interconnect This setting has the following selections:
losses
• Lossless – The transmission lines are perfect
conductors (no loss).
• DC Lossy – The trace material is used to calculate

conductor DC losses.
• AC Lossy – The traces AC and DC losses are

calculated and has the greatest accuracy.
Non-monotonic models Because allowing simulation with non-monotonic IV
curves is dangerous and may cause non-convergence
during simulation due to loading conditions, only
advanced users should enable this checkbox. When it is
enabled, simulation preview generates warnings for these
types of curves. When it is disabled, simulation preview
generates errors, and will not allow simulation.

Table 2-5. Simulation Settings (Settings Tab) (cont.)

Option Description
Via modeling This setting has the following selections:
• Advanced model – This option allows the tool to

estimate the inductance and capacitance of each via
based on its individual geometry. The resulting values
are used to characterize a Pi network models for the
vias.
• Single Pi network – This option allows you to enter the

capacitance and inductance values to characterize the
Pi network model that is used for all vias with a
particular span in the design, regardless of their
geometries. The Setup > Setup Parameters dialog via
characteristics is used for modeling.
• Simple star network – This option allows you to enter

the capacitance and inductance values that are used to
characterize the Star network model that is used for all
vias with a particular span in the design, regardless of
their geometries.
To Create a New Simulation Settings Template

2. From the Simulation Settings dialog box, next to the Simulation setting template field,
click .
3. From the Create new simulation settings template dialog box, specify a name, the initial
values to use for the new template, and then click Create.
To Load an Existing Simulation Settings Template

2. From the Simulation Settings dialog box, next to the Simulation setting template field,
click .
3. From the Load into current simulation settings template dialog box, specify the use of
system defaults, or click to enable Load from the template below, and then click the
browse button to select a template.

Note: When loading from the template below, make sure you click a template in the
Available Templates box.
4. After you finish, click Load.
Modifying Simulation Stimulus

You can modify simulation stimulus settings used by ICX Pro Verify to control cycle and pulse
times, bit patterns, and sequence repetition.
To Modify Simulation Stimulus

1. From the Edit menu, click Simulation, and then click Simulation Stimulus.
2. From the Stimulus dialog box, modify any appropriate settings. After you finish, click
OK. Refer to the tables below for a description of each option.
Note: To switch to an advanced stimulus, enable Advanced stimulus, and then click
Advanced Stimulus Editor.
Please refer to the following table for basic stimulus settings.
Table 2-6. Stimulus Settings (Basic Stimulus)

Option Description
Initial state This is the starting state of the stimulus, before the first
transition. The options are High, Low, and Model. The
Model option uses the state from the IBIS model (low for
non-inverting). Your selection may cause the Cycle and
pulse times display to change.
First transition The value is the time from the initial state to the first
transition of the stimulus (0.001 to 100).
Cycle and pulse times Look at the arrows defining a region of the waveform. The
top number defines the cycle time. The bottom two values
define the pulse times of the cycle (0.001 to 100 (ns)).
Frequency Signal frequency. For example, to enter 100 megahertz,
type 100M.
Duty Cycle The percentage of time the signal is in its logic high (i.e.
active) state.

Please refer to the following table for advanced stimulus settings.
Table 2-7. Stimulus Settings (Advanced Stimulus)

Option Description
Sequence This setting has the following selections:
• PRBS (pseudo random bit sequence) – The random

bits determined by the Bit order field. For example, if
the Bit order field is 5, the sequence length is 2 e5 -1 or
31. The initial State defines the start of the stimulus.
• Toggling – Is a sequence of 2-bits 0 and 1. The initial

State defines the start of the stimuli.
• 8B/10B or K character – Is a sequence length of 10-

bits. The 8B/10B is an IBM encoding method for 8-bit
data into 10-bit transmission characters. The K
characters are control characters. The Character value
of Dxx.y is used for characters and Kxx.y is used for
control characters.
• USB 2.0 compliance – Is a sequence that meets the

USB 2.0 specification.
• Custom – Is a sequence of bits, which you create, or

you can use the Load button to select a bit pattern. Use
the cursor and right mouse button to create your own
pulse sequence. Click the rise and fall edges and drag
the mouse for number of pulses. Use the Save button
to save your custom pulse train.
Bit interval The time duration of one bit.
Period The time from rising edge to the next rising edge or from
falling edge to falling edge.
Duty cycle The percentage of time the signal is in its logic high (i.e.
active) state.
Sequence repetitions Use this field to define the number of times you want the
sequence to be repeated.
Amount (p-p) The amount of jitter, peak-to-peak, and the % of the
period or time determines the width.
Distribution The distribution is Gaussian (noise on a bell curve) or
uniform.
Skip first Skip the specified number of bits.
Show Number of signal eyes to show.

Customizing the Display of CES Windows
To Create a New Simulation Stimulus

2. From the Stimulus dialog box, next to the Name field, click .
3. From the Create new stimulus dialog box, specify a name, the use of system defaults, or
click to enable Copy from the existing stimulus below, and then click the browse button
to select a stimulus.
Note: When copying from the existing stimulus below, make sure you click a stimulus
in the Available Stimuli box.
4. After you finish, click Create.
To Load an Existing Simulation Stimulus

2. From the Stimulus dialog box, next to the Name field, click .
3. From the Load into current stimulus dialog box, specify the use of system defaults, or
click to enable Load from the stimulus below, and then click the browse button to select
a template.
Note: When loading from the stimulus below, make sure you click a stimulus in the
Available Stimuli box.
4. After you finish, click Load.
Related Topics
• “Validating Constraints Against PCB Actuals” on page 128
Related Constraints
• “Simulation Settings” on page 376
• “Simulation Stimulus” on page 378

You can customize the display of CES windows to design the most efficient work environment
for the completion of CES tasks. You can toggle the display of specific windows, arrange
windows in a tiled or cascaded fashion, and change the position of toolbars and browser

windows. By activating preservation of display settings, you can maintain a custom work
environment.
Caution
Beginning with the 7.9.2 releases, the initial view of CES has been streamlined to present
you with just the core set of CES Spreadsheet pages and CES toolbars. All existing
functionality is still available.
To Toggle the Display of Specific Windows and Window Elements

From the View menu, click to toggle the display of a specific window or an element that
appears inside a certain window. You can use the following list to determine window
customization that results from the inclusion or exclusion of each selection:
• Tabs – Toggle this set of selections to display or exclude specific pages of the CES
Spreadsheet (for example, Nets or Noise Rules).
• Navigator – Also known as the browser, toggle this set of selections to display or
exclude the hierarchical listing of CES design elements (such as schemes, net classes,
and constraint classes).
Tip: Clicking the right mouse button on browser items often displays context-sensitive
menus that give you the ability to perform operations directly from within the browser
tree.
• Output – Toggle this setting to display or exclude the CES log/output window.
• Status Bar – Toggle this setting to display or exclude the status bar that appears at the
very bottom of the application.
• Toolbars – Toggle this set of selections to display or exclude one of the many CES
toolbars.
Note: To quickly show all toolbars, click All. To show only the default toolbars, click
Default.
To Change the Position of Windows and Toolbars

1. Click-hold the window or toolbar handle of the interface element you want to move.
Note: Window handles are double bars displayed horizontally or vertically depending
on the orientation of a window. Toolbar handles are located around the perimeter of
each toolbar.
2. Move the interface element to position it within CES.

Customizing CES Toolbars
Folder Location of ces.ini Customization File

CES application customizations, which exclude design settings and preferences, are stored
locally for each user at one of the operating-system specific folder locations listed below. This
file includes user customizations for CES windows, toolbars, command shortcut keys, user-
created constraint groups, and any other GUI customizations you can make to CES that are not
related to design preferences or the overall constraint set.
Windows Locations
The GUI customization file (ces.ini) is stored at one of the following locations:
• c:\Documents and Settings\<user>\Application Data\MentorGraphics\<software

version>\ces.ini
Example: c:\Documents and Settings\psmith\Application
Data\MentorGraphics\7.9.2EE\ces.ini
• c:\Users\<user>\AppData\Local\MentorGraphics\<software version>\ces.ini
Example: c:\Users\psmith\AppData\Local\MentorGraphics\7.9.2EE\ces.ini
Unix Location
The GUI customization file (ces.ini) is stored at the following location:
• $HOME/.config/MentorGraphics/<software version>/ces.ini
Example: $HOME/.config/MentorGraphics/7.9.2EE/ces.ini

You can customize CES toolbars to create custom sets and groupings of buttons, create new
toolbars, and specify general toolbar display options. In the event that you do not want to keep
your modifications to an existing toolbar, you can reset it to its default grouping of buttons.
Customization of CES toolbars can help to increase the efficiency with which you use CES by
making it easier to access just the toolbar buttons you use. This is helpful to most users because
utilizing only a subset of CES functions is common for many members of a design team.
Prerequisites
• None.
General Tasks
You can customize CES toolbars in the following ways:
• “Modifying Toolbars to Create Custom Sets of Buttons” on page 82

• “Creating New Toolbars” on page 83

• “Specifying General Toolbar Options” on page 84
• “Resetting a Toolbar to the Default Grouping of Buttons” on page 85
Modifying Toolbars to Create Custom Sets of Buttons

You can modify CES toolbars to change the order of buttons displayed on a toolbar, add toolbar
buttons to it, and remove toolbar buttons from it. For example, when you only use half of the
buttons on a specific toolbar, you may find it useful to reorder the buttons on the toolbar such
that those that you use are all displayed in the leftmost position of the toolbar instead of being
spread out among the entire width of the toolbar.
Prerequisites
• None.
Procedure
1. From the View menu, click Toolbars, and then click Customize.
Alternative: Right-click any CES toolbar, and then click Customize.
2. From the Customize dialog box, click the Commands tab, and then do any of the
following:
• To add a button to a toolbar, click the appropriate group selection within the
Categories list box, and then in the list of buttons, double-click and drag a button to a
specific CES toolbar at the top of the GUI.
• To remove a button from a toolbar, at the top of the GUI, double-click a toolbar
button and then drag it to any area below the collection of toolbars (for example,
Navigator).
• To move a button within a toolbar, or from one toolbar to another, at the top of the
GUI, double-click a toolbar button, and then drag it to another toolbar location.
3. After you finish making changes to one or more toolbars, click OK.
Results
The display of one or more toolbars is now changed to reflect the modifications you have made.

Related Topics
“Customizing CES Toolbars” on page 81 “Creating New Toolbars” on page 83
“Specifying General Toolbar Options” on “Resetting a Toolbar to the Default Grouping
page 84 of Buttons” on page 85
Creating New Toolbars

You can create new toolbars that did not exist previously. Adding a new toolbar takes CES
toolbar customization to the extreme by grouping buttons based on a new set unique to you as a
user. A common use for the functionality is to create a user-based toolbar that includes all of the
buttons that you use most frequently. Because of the large number of toolbar buttons that CES
provides, making your custom set can help you be more efficient with CES when you use just a
specific subset of its functionality.
Prerequisites
• None.
Procedure
2. From the Customize dialog box, click the Toolbars tab, and then click New.
3. From the New Toolbar dialog box, in the text field, enter a name for the new toolbar (for
example, “pats_CES_toolbar”), and then click OK.
Results
The new toolbar is available for modification. To learn how to add buttons to it or change its
contents, please refer to “Modifying Toolbars to Create Custom Sets of Buttons” on page 82.
Example of Deleting a New Toolbar

In the following example, you want to delete a custom toolbar that you created but no longer
need.
2. From the Customize dialog box, click the Toolbars tab.
3. In the Toolbars listing, click the name of the new toolbar, and then click Delete.
4. After you finish click OK.

5. As a result, the toolbar is no longer available.
Example of Renaming a New Toolbar

In the following example, you want to rename a custom toolbar that you created previously.
2. From the Customize dialog box, click the Toolbar tab.
3. In the Toolbars listing, click the name of the new toolbar.
4. In the Toolbar name text box, enter a different name for the custom toolbar.
6. As a result, the toolbar is renamed and associated with the new name.
Related Topics
“Customizing CES Toolbars” on page 81 “Modifying Toolbars to Create Custom Sets
of Buttons” on page 82
“Specifying General Toolbar Options” on “Resetting a Toolbar to the Default Grouping
page 84 of Buttons” on page 85
Specifying General Toolbar Options

You can specify general toolbar options to control the size and appearance of toolbar buttons.
You can also control whether tooltips are displayed when you hover the mouse cursor over a
toolbar button.
Prerequisites
• None.
Procedure
3. Click to enable or disable any of the following checkboxes:
• Show Tooltips – Displays a descriptive text box when you hover the mouse cursor
over a tooltip.

• Cool Look – Displays toolbar buttons with a more modern graphical appearance.
Results
Your modifications to these settings are applied.
Related Topics
“Creating New Toolbars” on page 83 “Resetting a Toolbar to the Default Grouping
Resetting a Toolbar to the Default Grouping of Buttons

You can reset a toolbar to display its default listing of buttons, as well as the default order in
which those toolbar buttons are displayed. Doing so is especially useful when you make
changes to a toolbar that are too extensive and you want to start over to capture just the useful
modifications. In some cases, you may have temporarily modified a toolbar and simply want to
reset it to its default display of buttons.
Prerequisites
• The toolbar you want to reset must have been customized in some way.
• The toolbar must be a default toolbar that you did not create.
Procedure
3. In the listing of toolbars, click the appropriate toolbar, and then click Reset.
Results
The toolbar now displays all of its default buttons, and all of the buttons are in the default order.

Customizing the Constraint Set
Related Topics
“Creating New Toolbars” on page 83 “Specifying General Toolbar Options” on
page 84

You can customize the constraint set displayed through the CES Spreadsheet to fit your needs
and that of your design team. When making customizations, you can add entirely new
constraints to specify all of their properties. You can only modify existing constraints to control
whether they are read-only or hidden. Changes you make are stored in a file called user.cns in
your WDIR location.
Please be aware of these important guidelines:
• When your WDIR includes multiple locations, only user.cns at the first writable path is
updated to include your changes.
• Because a user.cns file must exist at all WDIR locations, CES will initially place one at
each location when one does not already exist. After that, it will only write changes to
the first writable path.
• user.cns files are not supported between releases. All user.cns files need to be specific to
a certain release (for example, EE 7.9.3). For more information, please refer to
“Associating user.cns Files With a Mentor Software Release” on page 91.
Caution
Customizations to the constraint set are something that a design team should only do
before starting design development. After you put a custom user.cns in place, you should
not modify it or make a different user.cns available. Custom constraint sets are tied to
each specific user.cns file. Changing the available user.cns file during the course of
design development will cause the loss of custom constraints and data that you cannot
regain.
Therefore, it is critical that the machines of all team members use the same corporate or
design-specific user.cns file. For more information, please refer to “Sharing Your
Constraint Set With Other Users” on page 89. In the event that you move the design to a
different machine, ensure that it has access to the necessary user.cns file for the design
before you load the design. When working with a design backup that you restore at a later
point in time, you must ensure that the correct user.cns file is available to the design
before you load the design.

Prerequisites
• There must be one or more writable folder locations specified in your WDIR variable.
When a user.cns file exists at each of the folder locations, at least one of these files must
be writable.
• You are the only user who is modifying the constraint set when the user.cns file that will
be updated is in a shared WDIR location. CES concurrency of any kind is not supported
while customizing the constraint set.
To Change the Constraint Set

1. From the Edit menu, click Constraint Definitions.
Alternative: From the CES Spreadsheet, right-click a constraint column, and then click
Constraint Definitions. Now that you are in the context of a specific constraint, please
proceed to step 4.
2. From the Constraint Definitions dialog box, use the Page dropdown to select the
spreadsheet page for which you want to modify an existing constraint or a new
constraint.
Tip: To differentiate between standard constraints and user-created constraints, you can
use the Filter dropdown to select the constraint types to display.
3. At this point, you can perform any of the following tasks:
• To modify an existing constraint to control whether it is read-only or hidden, from
the Constraint dropdown, select a base constraint.
• To create a user constraint, click , type a name for the new constraint, and then
click OK.
4. For user constraints only, you can now specify Header, Title, Data type, Default value,
and other attributes of the constraint. The Data type field controls whether the constraint
has an associated Unit type, Min value, and Max value.
Note: To display the unit type in a constraint heading, append “(%U)” to the heading
text (for example, “Crosstalk (%U)”).
5. For user constraints only, when applicable, you can use Min value and Max value to set
the acceptable boundaries for a constraint. When the user enters a constraint value that is
outside of this boundary, CES uses its backlighting mechanism to visually indicate the
range breach.
6. When creating a user constraint, use the Levels selection to specify the spreadsheet-page
levels for which the constraint should be associated.
7. For both user constraints and base constraints, you can click the associated check box to
make the constraint read only and/or hidden.

8. For user constraints only, in the Constraint description text field, enter or modify the
description for the constraint.
9. To make more adjustments to the constraint set, return to step 2. After you finish
changing the constraint set, click Apply.
To Delete a User-Created Constraint

1. From the Edit menu, click Constraint Definitions.
2. From the Constraint Definitions dialog box, use the Page dropdown to select the
spreadsheet page for which you want to delete a user-created constraint.
3. Using the Constraint dropdown, select the constraint, and then click .
Tip: To quickly delete all custom constraint definitions, from the Data menu, click Clear
All Custom Constraint Definitions.
Creating Custom Spreadsheet Pages

In addition to adding to the list of constraints on a preexisting spreadsheet page, you can also
create new spreadsheet pages and populate them with your own selection of constraints and
rows. Each custom spreadsheet page is different from the standard pages in that they do not
have any rows or columns by default. Much like the Noise Rules spreadsheet page, they begin
completely blank. You must add rows to start populating them.
Prerequisites
• Custom tab modification must be enabled. To do so, from the Setup menu, click
Settings. From the Settings dialog box, click Other, and then ensure that Enable custom
tab modification is activated.
To Create a Custom Spreadsheet Page

1. At the bottom of the CES Spreadsheet, next to the Constraint Templates tab, click .
Result: A new custom tab is added to the Navigator, and the list of selectable tabs at the
bottom of the CES Spreadsheet.
2. At this point, you should rename the page. To do so, right-click the name of the page,
and then click Rename. Type a new name, and then press Enter.
3. To customize the listing of rows, you can do any of the following things:
• To add a row, from the Navigator, right-click the name of the page, and then click
New Custom Object.
• To copy a row, from the CES Spreadsheet, right-click a row, and then click Clone.

• To change the name of a row, from the CES Spreadsheet, right-click a row, and then
click Rename. Type a new name, and then press Enter.
• To delete a row, from the CES Spreadsheet, right-click a row, and then click Delete.
4. To customize the listing of columns, please refer to “Customizing the Constraint Set” on
page 86.
Renaming and Deleting Custom Tabs

After you create one or more spreadsheet pages, you can rename them and delete them as
needed. To do so, right-click a custom tab, and then, depending on the task you want to
accomplish, click Rename Tab or Delete Tab.
Tip: To quickly delete all custom tabs, from the Data menu, click Clear All Custom
Tabs.
Sharing Your Constraint Set With Other Users

When working with a team of engineers who need to use the same custom constraint set, you
can share your <WDIR>/user.cns file with other members of the team. How you deploy this
files depends on the infrastructure of your organization and the goals you want to accomplish.
Please see below for a few different deployment methodologies. Generally, the only users who
will deploy a user.cns for team use are either a design lead or administrator.
user.cns Requirements for Remote Server Usage and Project Concurrency

Please be aware of the following user.cns requirements when using RSCM:
• When a user’s machine has the environment variable RSCM_ENV_CONFIG defined, it

is important to understand that the WDIR definition in the file rscm.env.cfg takes
precedence over their WDIR environment variable. In this case, users must ensure that
the WDIR variable in rscm.env.cfg is the same as the WDIR definition used by the team.
• The administrative user who runs the RSCM service for a design must have write access
to at least one directory specified in the WDIR definition.
Enterprise Methodology
The most efficient way to use the same custom constraint set within a design team relies upon
having a corporate WDIR location to which each user machine points. By placing user.cns in
the corporate WDIR location, each user machine will read from the common constraint set.

Caution
Before copying an updated user.cns file into a corporate WDIR folder that is shared by a
design team, ensure that none of the users have CES open or are currently accessing the
file.
To use this approach, the WDIR environment variable on each user’s machine should include
the following three paths, and in the following order:
• Writable local WDIR folder (for example, c:\WDIR).

• Read-only Corporate WDIR folder (for example, \\common\corp_WDIR).
• Read-only pointer to %SDD_HOME%\standard.
Note: user.cns files are not supported between releases. All user.cns files need to be
specific to a certain release (for example, EE 7.9.3). For more information, please refer
to “Associating user.cns Files With a Mentor Software Release” on page 91.
Based on the unique folder paths in the above items, the WDIR variable would be the following:
c:\WDIR;\\common\corp_WDIR;%SDD_HOME%\standard
Note
On Windows, when including network paths in your WDIR environment variable, they
must be listed as full network paths and cannot be listed as mapped drives.
Using this approach provides the benefits of a corporate environment where various CES users
would be able to:
• Edit standard and custom constraints concurrently.

• Add their own user-defined constraints while not changing corporate/standard
constraints. (Please refer to the cautionary statement in “Customizing the Constraint
Set” on page 86 for important information about maintaining access to custom
constraints and their values.)
• Maintain separate interface settings for each user.
• Efficiently and accurately benefit from a common corporate set of rules.
Small-Group Methodology
Although it is not recommended, when you do not have a corporate WDIR location, you can
place the file in a public location and then provide instructions for other team members to copy
it into the WDIR directory on their respective machines.
Manually managing the deployment and updates to your team’s user.cns file is not an optimal
or efficient approach, and it can easily result in inconsistent constraint sets among your user

base. If you are not yet using a shared WDIR location, now is a great time to include one in your
design environment.
Constraint Sets Based on User Roles

In some cases, you might want to have custom constraint sets for specific user roles. For
example, if you are the constraint administrator for a design project or team, you might want to
grant access to specific constraints to just certain members of the team while hiding them from
the rest of the team, or making them read-only. By default, all CES users have access to all
constraints, so reducing accessibility to some key constraints can help to ensure constraints
integrity. In an example case, a constraint administrator could create a few or more different
user.cns files and then provide the appropriate user.cns file to each team member based on their
role within the design team.
Associating user.cns Files With a Mentor Software

Release
Because user.cns files are not supported between releases, you need to ensure that each Mentor
software release that you use has access to its own unique user.cns file or file set for that release.
In the event that your WDIR includes multiple folder locations, the user.cns file in each location
must be specific to a single Mentor software release.
There are two recommended approaches:
• Store the unique user.cns files for each release somewhere else, and swap them in and
out of your WDIR locations when you change Mentor software releases.
• Use different WDIR folders for each Mentor software release.
An Example Scenario
Here is an example WDIR that includes three folder locations and is based on an enterprise
methodology: c:\WDIR;\\common\corp_WDIR;%SDD_HOME%\standard
Using the first approach, you would copy two unique user.cns files, each into one location
(C:\WDIR and \\common\corp_WDIR). The first one is the writable user-specific copy. The
second one is the read-only corporate constraint set. You would not need to replace the
%SDD_HOME%\standard file because the SDD_HOME location is always release specific.
Using the second approach, you would not need to replace the two user.cns files because you
would instead have a unique set of WDIR folders for each Mentor software release. For
example, c:\WDIR_EE_793;\\common\corp_WDIR_EE_793;%SDD_HOME%\standard. Once
again, the SDD_HOME location is always release specific and by nature unique.

Adding Custom Menu Selections to the Tools Menu
Note
For additional information on this topic, please refer to the topic “Automating the License
and WDIR Configurator Settings” in the Managing Mentor Graphics Systems Software
manual.
Related Topics
“Customizing the Constraint Set” on page 86 “Sharing Your Constraint Set With Other
Users” on page 89
Adding Custom Menu Selections to the Tools

Menu
You can add menu selections to the customize the Tools menu. Doing so makes it easier to
access external programs that you use in conjunction with CES, or as part of your constraint-
driven design flow. Menu selections that you add to CES are appended to the bottom of the
preexisting Tools menu selections. Any ordering changes or deletions that you make can not
include the standard menu selections.
Prerequisites
• None.
Procedure
1. From the Tools menu, click Customize.
2. From the Customize dialog box, click New, and then complete the following fields:
• Menu Text – The display name you want to associate with the custom menu
selection.
• Command – The executable file to run when the custom menu selection is clicked.
To specify the command, click the browse button, navigate to the appropriate folder
and filename, and then click Open.
• Arguments – Optionally, an argument string to append to the command. Your
argument string can also include the following variables:
o {CESDir} – CES directory of the active project.
o {ProjectDir} – Top-level directory of the active project.
o {ProjectFile} – Filename of the .prj for the active project.
• Initial Directory – Optionally, a directory to use other than the current working
directory. This is useful when the command will generate run-time files that need to

Customizing Command Shortcut Keys
be stored in a different location. To specify an initial directory, click the browse

button, navigate to the appropriate folder, and then click OK.
3. Optionally, you can do any of the following things:
• To edit an existing custom menu selection, in the Menu Contents list box, click the
appropriate row, and then modify any of the fields described in step 2 of this
procedure.
• To change the order of a custom menu selection, in the Menu Contents list box, click
the appropriate row, and then click Move Up or Move Down.
• To delete a custom menu selection, in the Menu Contents list box, click the
appropriate row, and then click Remove.
4. After you finish adding custom menu selections or modifying existing custom menu
selections, click OK.
Results
The bottom of the Tools menu is updated to reflect your changes.

You can customize command shortcut keys to associate key combinations with commands that
do not already have them, change existing key combinations, and assign multiple shortcut
combinations to a single command. For example, when CES does not include what you consider
to be an intuitive shortcut combination for a command, you can remove the existing command,
and then define your own shortcut combination. The alternative is to simply add an additional
shortcut combination that you consider to be more intuitive; in other words, easier to remember.
Prerequisites
• To execute and test the accessibility of some CES commands through shortcut
combinations, you must have a design loaded in order to access all functionality.
Procedure
1. From the CES Setup menu, click Shortcuts.
2. From the Customize dialog box, in the list box of Commands, click to select a
command, and then do any of the following things:
• To create a new shortcut combination, click New, and then do the following things:
i. When the New Shortcut dialog box appears, key-in the combination you would
like to use. It can consist of Ctrl, Shift, Alt, and then a letter key, number key, or
F# key (e.g Ctrl+Shift+Alt+F8).

ii. After you finish pressing the appropriate shortcut key combination, visually
verify that it is correct, and then click OK.
• To delete a shortcut, in the Current shortcuts list box, click a shortcut, and then click
Remove.
3. Optionally, to remove all user-defined shortcuts and reset the list of shortcuts to just the
defaults, click Remove All.
4. After you finish adding, modifying, or deleting shortcut combinations, click OK. In the
event that you made changes that you do not want to keep, click Cancel.
Results
Your additions, removals, and changes to key combinations are now stored. You can now use
them to access CES commands.
Related Topics
“Default Keyboard Shortcuts Provided With
CES” on page 94
Default Keyboard Shortcuts Provided With CES

Please refer to the table below for the list of all keyboard shortcuts that are provided with CES.
The table is ordered with respect to the layout of the CES menu system. Commands that do not
have menu selections are listed at the end of the table.
Table 2-8. CES Keyboard Shortcuts

Menu Command/Command Default Shortcut(s)
File > Open Project Ctrl+O
File > Print Ctrl+P
File > Import > Constraints Ctrl+I
File > Export > Constraints Ctrl+E
Edit > Undo Ctrl+Z
Alt+Backspace
Edit > Redo Ctrl+Y
Edit > Cut Ctrl+X
Shift+Delete
Edit > Copy Ctrl+C
Ctrl+Insert
Edit > Paste Ctrl+V
Shift+Insert

Selecting or Creating Valor NPI Design Centers
Table 2-8. CES Keyboard Shortcuts

Menu Command/Command Default Shortcut(s)
Edit > Find Ctrl+F
Help F1
Display constraint help Shift+F1
Find phrase F3
Zoom full F6
Zoom in F7
Zoom out F8
Related Topics
“Customizing Command Shortcut Keys” on
page 93

You can select from available Valor NPI Design Centers to choose the one that your layout tool
uses when you launch Valor NPI to perform analysis. A Design Center is a Valor NPI feature
that defines the rule set used during design for manufacturing analysis. When you need to make
a new Design Center, you can create one.
Note
It is important to understand that by default, Design Centers that you or other team
members create cannot be shared. In order to do this, you must configure your Valor NPI
environment in a specific way to support this usage. For more information, please refer to
“Sharing Valor NPI Design Centers Among Team Members” on page 96.
Prerequisites
• You use Valor NPI as part of your design flow.
• When selecting a Design Center, at least one must already be available.
Procedure
1. From the Tools menu, click Valor NPI, and then click one of the following menu
selections:
• Select Design Center - From the dialog box, use the dropdown to select the Design
Center you want to use, and then click OK.

Tip: To clear the active Design Center, choose the blank row.
• Create Design Center - From the dialog box, type a name for the new Design
Center, and then click OK. Complete the steps in the Design Process Wizard.
Note
When you choose to create a new Design Center, you may first be presented with the
Valor License Configuration dialog box. From here, you can verify the selection and
ordering of licenses. To keep this dialog box from showing again, activate the appropriate
checkbox.
Results
Depending on how you choose to use the above procedure, you either created a new Design
Center, or selected an existing Design Center. When you choose a Design Center, the CES
status bar is updated to show your selection:
Related Topics
“Sharing Valor NPI Design Centers Among
Team Members” on page 96
Sharing Valor NPI Design Centers Among Team Members

By default, users create their own Design Centers. When using Valor NPI as part of a team
environment, you may want to share a set of Design Centers among a group of team members.
Doing so ensures that everyone is using the exact same set of Design Centers when this is
preferable.
Prerequisites
• Your team uses Valor NPI as part of their design flow.
Procedure
1. The team needs to decide upon a network location for the shared Design Centers (for
example, Z:\shared_design_centers). Please refer to the Valor NPI documentation for
details about how to choose a location for your Design Centers.
2. All users who want to be part of the share must ensure that their VALOR_ENV_FILE
environment variable points to the proper folder that contains the env file. CES reads the
VALOR_DIR variable in that env file to find the folder that contains the Design Centers.

Results
The design team now uses a shared network location for all Design Centers. Any team member
who is configured this way can create, modify, and select from the shared set of Design Centers.
Typically, the user who sets up the shared space would be responsible for creating the set of
Design Centers.
Related Topics
“Selecting or Creating Valor NPI Design
Centers” on page 95


Chapter 3
CES Constraint Spreadsheet Usage
This section covers CES Constraint Spreadsheet usage. Some of the topics included are
constraint definition, searching, filtering, and grouping. This section also provides information
about constraint validation, constraint reuse through rule painting, and saving constraint
changes. Please refer to the table of contents for the full listing of topics included in this section.
Defining Constraints With CES Spreadsheets

The CES interface for entry and modification of constraint data is a spreadsheet that is separated
in to pages. Each page corresponds to specific types of constraint data. The constraints located
on some spreadsheet pages are further groupable by listing only a pre-defined subset of a
constraint set. For example, while working in the Nets tab of the CES Constraint Spreadsheet,
you can choose to list just Net Properties, Differential Pairs, or Delays and Lengths constraints.
Note
As you work with constraints on each CES Spreadsheet page, you will notice that some
constraints are listed on multiple pages. Changing a constraint value on any page that
includes it results in the change appearing on each page. For example, the Index and Type
constraints appear on both the Trace & Via Properties and Clearances spreadsheet pages.
While entering or modifying the data on each of these pages, you can search for net and
constraint data, filter data, sort data, and validate constraints against actuals that were produced
during routing simulation. Nets assigned to the classes you define here will obey associated
constraints during interactive routing.
Common Tasks
• “Understanding Constraint Hierarchy and Overrides” on page 100
• “Selecting CES Spreadsheet Pages” on page 105
• “Identifying Spreadsheet Icons” on page 106
• “Resizing Spreadsheet Columns and Rows” on page 108
• “Zooming the Display of Spreadsheet Pages” on page 108
• “Expanding and Collapsing Spreadsheet Rows” on page 109
• “Sorting Constraint Pages” on page 109
• “Deleting Constraint Values at the Constraint Level” on page 110

Understanding Constraint Hierarchy and Overrides

CES uses hierarchy extensively for two main purposes. The first is to organize and maintain
relationships between different types of objects. For example, pins on a part, or nets in a
differential pair. CES attempts to maintain the important relationships between constraint
objects and values, especially those used by other tools such as Expedition PCB.
The other purpose is to provide a convenient way to group objects (nets, for example) into
classes that share the same constraints. This grouping gives you the ability to define constraints
once for an entire group. Another example usage of classes could be to group nets that are the
same type. Overall, hierarchical grouping gives you the ability to organize your design data and
make your job easier.
For example, by grouping 32 bus nets into the same constraint class, you can quickly assign a
single constraint value to the class and propagate it down (for example, # Vias Max) instead of
manually assigning the same value to each of the 32 nets. When you need to deviate from a
constraint class value, you can enter an override value into one or more net rows while
maintaining the class value for all other nets in the class.
To help make it clear which constraint values under a hierarchical object have overrides, CES
can highlight the background of the parent-level cells. To turn on this type of highlighting,
please refer to “To Set Display Settings” on page 64. In the following illustration, you can see
that although the component row defines the same IBIS Component Name value for each
component instance row, R2 and R4 have overrides that replace parent value.
Figure 3-1. Component Model Overrides at the Instance Level
In the above illustration, yellow is used to highlight parent overrides. To set the background
color CES uses, please refer to “To Set Fonts and Colors” on page 65. In addition to choosing
this highlighting color, you can review and modify the overall color scheme CES uses to
highlight constraint violations like errors and cautions. These are just a couple examples of how
CES uses cell highlighting to indicate data conditions.

Blank Cells at the Constraint Class Level are not Considered When
Determining Overrides
An override is defined as a value that is different from a value at a higher level of hierarchy.
When moving a net into a different constraint class, CES does not consider an empty or blank
constraint class level cell as a value when determining if there is an override in its hierarchy.
For example, you have a net that defines # Vias Max at the net level. You then move the net into
a constraint class that has a blank entry for this constraint. Doing so will preserve # Vias Max at
the net level when you instruct CES to change the old value. This is because the blank entry is
not viewed as a value. Therefore, the net level value is not an override.
Choosing From Among Change Impact Actions

CES should not change your data without you being warned about it. For this reason, you are
either prompted or presented with a warning dialog box. Depending on how you have CES
configured, you can disable the warning dialog box. The purpose of the warning dialog box is to
alert you to the hierarchical impact of changing a parent constraint value. As explained in
“Understanding Constraint Hierarchy and Overrides” on page 100, parent and child objects are
linked for the purpose of quickly and accurately defining constraints and values for groups of
nets through constraint classes, net classes, and other parent/child object relationships.
Whether you have a parent object expanded or collapsed in the spreadsheet, overrides in a child
object are always identified when you attempt to change a value at the parent-constraint level.
CES propagates the new value (or not) based on how you have it configured. In some cases,
CES will not propagate the new value due to the requirement of a specific rule. For a list of
these, please refer to “Required Propagation Rules That CES Maintains” on page 103.
CES brings up this warning dialog box when all of the following conditions are met:
• Your setting for the Change Impact Dialog is not set to “Always prompt user for all
values.”
• You have not already enabled the “Don’t ask me again in this session” checkbox in the
warning dialog box.
• You are changing more data than what you typed in.
When you are presented with this warning dialog box, to go ahead with the change based on
your settings, click OK. To instead not make the change, click Cancel.
Caution
The primary purpose of this warning dialog box is to make you aware that a value you are
changing has hierarchical impact. The secondary purpose is to let you know that a CES
setting controls how overrides are handled. To modify the Change Impact Dialog setting,
please refer to “To Set General Options” on page 64.

For example, you have a constraint class that defines # Vias Max as 3. Out of the five nets in the
constraint class, you define this constraint as 5 for two of them. A change to the value at the
constraint-class level would cause CES to use this setting to determine whether you still want to
keep the override value of 5 for the two nets that use the value.
Figure 3-2. Constraint Class With Two Constraint Overrides
Choices regarding hierarchical propagation are not limited to net classes and constraint classes.
Any parent/child relationships that include overrides at the child level will cause CES to use the
Change Impact Dialog setting when you attempt to change a parent value. In the example
illustration below, an electrical net has an override at the physical net level for Length or TOF
Delay Min.
Figure 3-3. Electrical Net Override at Physical Net Level
Changing the electrical net value for this constraint would cause the Change Impact Dialog
setting to be used. Depending on how you have CES configured, the override value for physical
net DCONN24 would either be kept, replaced, or you would instead be prompted for the action
to take.
Prerequisites
• The procedure below is only valid when the Change Impact Prompt dialog box has been
displayed automatically by CES. This is because you have CES configured to give you
the ability to choose which child values will take on the new parent value. To modify
this setting, please refer to “To Set General Options” on page 64.

Procedure
1. From the Change Impact Prompt dialog box, for each child object, select from the
following actions, and then click OK:
• Change to new value – Replace the child value with the new parent value.
• Keep current value – Retain the child value.
Notes:
• To use the selected action for all child objects that are left, click to activate the
following checkbox: Do this for all remaining constraints
• As you are using the Change Impact Prompt dialog box, you can stop reviewing or
changing values by clicking Exit at any time. Doing so retains any changes that you
have made thus far, but skips any child objects that remain.
Results
Values for each child object are retained or replaced, respectively.
Related Topics
“Understanding Constraint Hierarchy and
Overrides” on page 100
Required Propagation Rules That CES Maintains

There are some cases where the Change Impact Dialog setting is irrelevant. This is due to object
and constraint relationships that CES must maintain in order for certain aspects of the constraint
set to be valid.
Please refer to the following list of required rules and their explanations:
• Net Class value for differential pairs and electrical nets – This value must be the same
for physical nets that are part of an electrical net, electrical nets that are part of a
differential pair, and the differential pair. CES maintains this relationship on the Nets
page and Constraint Templates page.
Exception: There is an exception to this rule when an electrical net contains multiple
physical nets. In this case, each physical net can have a different Net Class value from
the electrical net and differential pair.
• Template value for differential pairs – The constraint template assigned to a differential
pair is also assigned at the electrical net level. CES maintains this relationship on the
Nets page.
• Topology Type value for differential pairs and electrical nets – This value must be the
same for physical nets that are part of an electrical net, electrical nets that are part of a

differential pair, and the differential pair. CES maintains this relationship on the Nets
page.
Exception: There is an exception to this rule when an electrical net contains multiple
physical nets. In this case, each physical net can have a different Topology Type value
from the electrical net and differential pair.
• Length or TOF Delay Type value for differential pairs and electrical nets – This value
must be the same for physical nets that are part of an electrical net, electrical nets that
are part of a differential pair, and the differential pair. CES maintains this relationship on
the Nets page and Constraint Templates page.
• Length or TOF Delay Match value for differential pairs – This value must be the same
for electrical nets that are part of a differential pair, and at the differential pair level. CES
maintains this relationship on the Nets page and Constraint Templates page.
• Trace Width Minimum, Typical, and Expansion values – CES maintains mathematical
relationships among these constraints. For example, Minimum cannot be greater than
Typical, and Expansion cannot be less than Typical.
Organization of CES Constraints

CES constraint data is organized in to the following spreadsheet pages:
• Trace & Via Properties – Board-layer transmission constraints like via assignments,
routing, trace width, and typical impedance.
• Clearances – Same-layer clearance constraints like trace to trace, pad to trace, via to
plane, resistor to pad, and mask to pad.
• Z-Axis Clearances – Adjacent-layer clearance constraints like trace to trace, trace to
pad, trace to via, trace to plane, and trace to SMD pad.
• Nets – This spreadsheet page contains the largest number of constraints, which fall into
the following categories:
o I/O – FPGA constraints like I/O standard.
o Net properties – General net constraints like analog, bus, net class, number of pins,
and topology type.
o Diff Pair – Differential pair constraints like tolerance, convergence distance
tolerance, distance to convergence, and separation distance.
o Overshoot/Ringback – Signal reflection constraints like simulation class, static and
dynamic low and high overshoot, high and low ringback, and monotonic edge.
o Simulated Delays – Edge-rate delay constraints like simulated delay type, minimum,
maximum, and maximum range.
o Template – Net template constraints like name and status.

o Delays and length – Length or time of flight delay constraints like type, minimum,
maximum, match, tolerance, and formulas.
• Parts – Part constraints like part number, quantity, part type, value, IBIS component
name, and technology.
• Noise Rules – Neighboring-net constraints like noise type, constraint class or electrical
net name from and to, parallelism rule, and crosstalk max.
• Constraint Templates – Superset of constraints that includes many of those from each
CES Spreadsheet page for reuse as intellectual property for other nets and designs.
Selecting CES Spreadsheet Pages

You can select the active spreadsheet page in a variety of ways. In addition, you can choose to
display only a subset of constraints displayed on large spreadsheet pages. For example, you can
temporarily display just Diff Pair constraints on the Nets page. By doing so, you can more easily
focus on the constraints related to differential pairs.
To Select a CES Spreadsheet Page Using the Tabs

At the bottom of the current spreadsheet, click a spreadsheet tab. In the illustration below, the Z-
Axis Clearances tab is selected.
Figure 3-4. Selected Spreadsheet Page: Z-Axis Clearances
Here are some tips for customizing and using the display of spreadsheet tabs:
• CES gives you the ability to display just certain tabs so that you can show and hide tabs
as needed. To do so, right-click the listing of tabs, and then click to show or hide specific
tabs. You can also click to show All Tabs, or click to show just Default Tabs.
• When you cannot see all spreadsheet tabs, use the arrow buttons to scroll through the
tabs (when this setting is enabled). You can also resize the right edge of the tab listing to
increase or decrease the amount of space used to display the tabs.
To Select a CES Spreadsheet Page Using the Navigator

You can click within the Navigator to select among the different spreadsheet pages that are
available in CES. For example, after clicking Constraint Classes, the CES Spreadsheet Nets
page becomes active.

Note
CES gives you the ability to display just certain nodes of the Navigator so that you can
show and hide nodes as needed. To do so, right-click within the whitespace of the
Navigator, and then from the listing of nodes, click to show or hide specific nodes. You
can also click to show All Nodes, or click to show just Default Nodes.
To Display Only Specific Constraint Types on a Spreadsheet Page

You can do this in any of the following ways:
• At the top of a spreadsheet page, click the Group dropdown, and then select a constraint
type.
• Right-click within a spreadsheet page, click Group, and then click the constraint type.
For example, to display just net property type constraints of the Nets spreadsheet page, click the
Group dropdown, and then click Net Properties.
To Display All Constraint Types on a Spreadsheet Page

You can do this in any of the following ways:
• From the Group dropdown, click All.

• Right-click within a spreadsheet page, click Group, and then click All.
Identifying Spreadsheet Icons

As you work with the CES Spreadsheet, you will notice that each row includes an icon. Each
icon indicates a different type of design object. Icons are provided to make design-object
identification clear and efficient. For example, you can easily distinguish between electrical and
physical nets based on the icon beside a row on the Nets page of the spreadsheet. Please use the
following table to determine the type of design object that is represented by each icon.
Table 3-1. Design Object and Spreadsheet Icon Correlation

Design Object Spreadsheet Icon
Board layer
Clearance rule
Component
Component instance
Constraint class
Constraint template
Differential pair

Table 3-1. Design Object and Spreadsheet Icon Correlation (cont.)

Design Object Spreadsheet Icon
Electrical net
From-to
Net class
Physical net
Pin
Pin pair
Rule-area scheme
Z-axis clearance rule
Note
Electrical nets that include two or more physical nets are indicated as such on the Nets
page of the CES Spreadsheet. A ^^^ suffix is added to the end of the net name as it
appears in the first column (Constraint Class/Net/*).
Locking of Constraints
When working in any concurrent design environment, the CES Spreadsheet automatically locks
constraint values or objects that are being changed by another user in a separate instance of
CES. After the user finishes making their change, the lock is removed, and the value is once
again editable by other users. For example, two schematic designers are modifying constraints
from within CES sessions launched from DxDesigner. Because both users are working on the
same constraint database, CES displays lock icons ( ) in the other user’s environment as each
applicable constraint or object is modified.
A constraint or object lock is always removed when any of the following things occurs:
• The user who initiated the change finishes their modification(s).

• All clients are disconnected.
• The server is down.
To Determine Which User Has a Constraint Locked

Hover your mouse cursor over the locked constraint. The tooltip that is displayed shows the user
account that currently has the constraint locked for editing.

Resizing Spreadsheet Columns and Rows

As you work with CES constraint data, you may find it useful to resize specific columns or
rows. For example, by reducing the size of a column, you can provide more display room for
other columns located on the same spreadsheet page. On the other hand, by increasing the size
of a column, you can provide more display room for the content in that column.
To Resize Spreadsheet Columns

1. In the columns heading of a spreadsheet, hover your mouse over the vertical separation
between columns until the mouse icon changes to the resize icon. This is depicted in the
following illustration.
Figure 3-5. Preparing to Resize Constraint/Class/Net/* Column
2. Click-hold and then drag right or left to increase or reduce the size of the column.
3. After the column has been resized appropriately, release the mouse button.
To Reset Columns to Their Default Widths

From the View menu, click Reset Column Widths.
To Resize Spreadsheet Rows

1. In the leftmost cell of spreadsheet row, hover your mouse over the horizontal separation
between rows until the mouse icon changes to the resize icon.
2. Click-hold and then drag up or down to increase or reduce the size of the row.
3. After the row has been resized appropriately, release the mouse button.
To Reset Rows to Their Default Heights

From the View menu, click Reset Row Heights.
Zooming the Display of Spreadsheet Pages

You can increase and decrease the magnification level of CES Spreadsheet pages. Because each
spreadsheet page stores its own zoom level, you can customize the magnification level of
specific pages for your unique display purposes.

Tip: To quickly set the same magnification level for all CES Spreadsheet pages, use the
Setup > Settings menu selection. Using the Initial Zoom Level option, you can globally
control the initial spreadsheet magnification level.
To Zoom the Display of the Active CES Spreadsheet Page

Do one of the following:
• To increase magnification, press F7.

• To decrease magnification, press F8.
• To set magnification to 100%, press F4.
Expanding and Collapsing Spreadsheet Rows

You can expand and collapse the available rows on a CES Spreadsheet page. You can expand or
collapse just the selected rows, all rows, or a single row.
To Expand or Collapse a Single Spreadsheet Row

Click the + or - symbol to the left of the row.
To Expand Multiple Spreadsheet Rows

1. When you want to expand specific rows, use Ctrl-click to select each row that is
preceded with a + symbol.
2. From the View menu, to expand selected rows, click Expand, and then click Selected.
To expand all rows, click Expand, and then click All.
To Collapse Multiple Spreadsheet Rows

1. When you want to collapse specific rows, use Ctrl-click to select each row that is
preceded with a - symbol.
2. From the View menu, to collapse selected rows, click Collapse, and then click Selected.
To collapse all rows, click Collapse, and then click All.
Sorting Constraint Pages

You can sort nets/objects listed on a CES Spreadsheet page in both ascending and descending
order. Because this function is based on spreadsheet context, a sort will include all/most child
rows, or just the parent rows. For example, sorting from the Clearances page does not affect the
order of board layers ( ).

To Sort Constraint Pages

With CES Spreadsheet page that you want to sort as the active page, perform one of the
following actions:
• To sort in ascending order, from the Sort toolbar, click . Or, right-click within the
spreadsheet, click Sort, and then click Ascending.
• To sort in descending order, from the Sort toolbar, click . Or, right-click within the
spreadsheet, click Sort, and then click Descending.
Deleting Constraint Values

You can delete constraint values at both the constraint level and the object level. When deleting
values at the constraint level, you select individual constraint cells that you previously defined
but want to clear. When deleting values at the object level, you delete the entire set of
constraints for a given object and all child-member objects that are part of the top-level object.
General Tasks
You can delete constraint values in the following ways:
• “Deleting Constraint Values at the Constraint Level” on page 110

• “Deleting Constraint Values at the Object or Design Level” on page 111
Deleting Constraint Values at the Constraint Level

When you want to delete one or more constraint values at the cell level, CES gives you the
ability to do so through both the keyboard and the mouse. Please refer to the following
procedure for deletion of constraint values at this level.
Prerequisites
• None.
Procedure
1. From the CES Spreadsheet, click a constraint cell to select the value for deletion.
Tip: To select multiple constraint values, use Ctrl-click and Shift-click.
2. Press the Delete key; or, right-click, and then click Delete.
Results
One or more constraint cells are now clear/empty.

Related Topics
“Deleting Constraint Values” on page 110 “Deleting Constraint Values at the Object or
Design Level” on page 111
Deleting Constraint Values at the Object or Design Level

You can delete constraint values at the object level to quickly empty the set of defined
constraints for a net, constraint class, net class, or even your entire design. For example, after
applying a constraint template to the wrong net, you can quickly clear the new constraint values
using the appropriate procedure below.
When deleting constraint values at the object level, it is important to understand that all
removable constraints within the object’s hierarchy are cleared. For instance, clearing a
constraint class results in deleting all constraint values for each net within the constraint class.
This is in addition to any constraints defined at the constraint-class level.
When you delete constraint values at the object level, any default constraint values are not
cleared. This method of deletion is often times thought of as a way to easily “reset” a net or
design object.
Prerequisites
• When your goal is to clear all constraint values within a design, you must be running a
CES session launched from the front-end design system. In addition, your invocation of
CES must be the only session.
Procedure
Please refer to one of the following procedures based on the object you want to clear:
• To clear all constraints from a design object, please complete the following steps:
a. From the leftmost column of the CES Spreadsheet, right-click a design object, and
then click Clear Constraints.
b. From the message box that appears, optionally activate one or more checkboxes,
when appropriate, and then click Yes.
• To clear all constraints from your design, please complete the following steps:
a. From the Data menu, click Clear All Constraints.
b. From the confirmation dialog box that appears, please note the location of the design
backup that will be created, and then click Yes only if you are sure you want to clear
all user-defined constraints from the design.

Results
All non-default constraint values for an object (and its children object) or a design, are deleted.
Related Topics
“Deleting Constraint Values” on page 110 “Deleting Constraint Values at the Constraint
Level” on page 110
“Restoring to a Constraints Backup After
Clearing All Constraints” on page 112
Restoring to a Constraints Backup After Clearing All Constraints

You can restore all constraint values to their previous state after clearing all constraint values
through use of the Data > Clear All Constraints command. Generally speaking, the manual
process of restoring constraints would only be performed after you had cleared all constraints in
error.
Caution
When performing this manual unzip/copy/paste process, it is critical that you do not open
or unpack any additional files in the archive. For the purpose of maintaining data
integrity, please follow the procedure below precisely
Prerequisites
• You must have cleared all constraints to produce a CES backup.
Procedure
1. Close any software tools that are presently open on the current design. This includes all
Mentor tools and any non-Mentor tools.
2. Navigate to the following design folder: <design_path>\CES\Backup
3. Unzip the backup file (.zip) at that location. In the event that there are multiple backup
files, you can use the date_time encoded in the file prefix to determine which backup
you want to use.
4. Use the content of the unzipped backup file to replace the design data at the following
location: <design_path>\database
Results
All constraint values are restored.

Searching for Constraints
Related Topics
“Deleting Constraint Values at the Object or
Design Level” on page 111
Copying and Pasting Constraint Values Between

Separate Invocations of CES
When you have multiple invocations of CES loaded at the same time, you can copy and paste
spreadsheet values displayed in one invocation to the same spreadsheet of one or more other
invocations. Because CES does not restrict the cells between which you can copy and paste, it is
important to make sure that you select identical cells of the appropriate spreadsheet page.
You can use the copy and paste functionality on all CES Spreadsheet pages. It is important to
note that the functionality is not available for use with tables and cells of dialog boxes.

You can search for data within CES Spreadsheet pages to locate specific nets or select multiple
nets to perform operations on groups of nets. By doing so, you can quickly find or select
specific nets within large, complex design structures. You can also search spreadsheets for
constraint data.
When searching for specific nets, you can step through the list of all nets based upon the search
criteria you provide. When selecting multiple nets, you can filter the display of CES data based
upon a net-name or constraint-value criterion.
Tip: To quickly search for the first occurrence of any text string, from the Find toolbar,
enter the text string into the text box, and then click the button to the left. To find the next
occurrence, click the search button again.
To Search for Spreadsheet Data

1. From the Edit menu, click Find.
Alternative: From the Find toolbar, click .
2. From the Find dialog box Find what field, enter the text you want to find.
Example: To find and step through all nets of the form /N$2050 - /N$2059, use
/N$205? as your search string. To find and step through all nets that begin with /N$2,
enter /N$2*. Please note that this is not a regular-expression search example.
3. Specify the direction in which you want to search by selecting Forward or Backward.
4. To view additional search preferences, click More, and then use the following options:

• To search a page other than the current page, click the Page dropdown, and then
click to specify your search scope.
• To search sequentially by rows or columns, click the Search dropdown, and then
click to specify the direction.
• To search constraint values, or constraint comments, click the Look In dropdown,
and then click to specify the appropriate criterion.
• To match the exact capitalization or case sensitivity of the search string, click to
enable Match Case.
• To find only full matches and not partial ones (for example, you do not want
searches for “100” to find “1000” and “10000”), click to enable Match entire cell.
• To search using regular expressions, click to enable Use regular expressions, but
please keep the following in mind:
o Standard wildcard characters (for example, * and ?) behave much differently in
that they include matching--or not--to the preceding character. For example, a
regular expression search for “n*t” would match “at”, “nt”, “net”, “about”, and
many other words that begin with any character and end with “t”. Conversely, a
regular expression search for “n?t” would only match “at”, “nt” and “net” of the
results of the above asterisk example.
o * matches 0 or more of the preceding character, not just any character unless you
precede it with the period character (“.”).
o ? matches 0 or 1 of the preceding expression.
o There are additional wildcard characters that you can use.
o You can search using ranges of characters.
o For more information about using regular expressions properly, please refer to
the wealth of information available on this subject that you can find on the
internet or in dedicated textbooks.
• To enable searching of spreadsheet rows that are currently not expanded, click to
enable Drill-down searching
5. After you finish configuring your search, click Find Next or Find All.
• When you search with Find Next, the first relevant cell is highlighted. To find the
next cell that matches your criteria, click Find Next again.
• When you search with Find All, CES augments the dialog box to show a table of all
matching cells. You can cross probe between the table of search results and the
spreadsheet by clicking a cell in the results table.

Filtering Spreadsheet Data

Unlike search, when you filter a spreadsheet page the display of data rows is restricted to those
that match the string criteria. After you perform an initial filter, you can further restrict the
display of data rows by cumulatively filtering the remaining data rows. After you finish
working with a subset of nets, you can reset the spreadsheet page to display all data rows.
Filter is useful when you want to focus on a specific group of data rows without worrying about
modifying constraint data on rows that do not apply to a specific subset. For example, by
filtering data rows on the Nets spreadsheet page, you can display only those rows that
correspond to just the nets that comprise a data bus. With this view, it is easy to make sure that
your constraint modifications are restricted to just those bus nets.
Note
CES filters just spreadsheet rows that are expanded. To filter all rows of a spreadsheet
page, from the Filters menu, click to enable Drill-down Filtering.
Other Common Tasks

• “Filtering the CES Spreadsheet by Row Type” on page 117
To Filter Spreadsheet Data

1. From the Filters menu, click Enabled.
Alternative: When the Filters - Main toolbar is enabled (View > Toolbars > Filters -
Main), from the Filters - Main toolbar, click .
Note: Make sure that Filter mode is now on. When it is, the CES Spreadsheet is
augmented to include an additional row at the top for entering the filter string.
2. In the column for which you want to filter spreadsheet data, click the dropdown in the
filter cell, and then perform one of the following tasks:
• To use a default filter, select from among Sort Ascending, Sort Descending, (All),
and (All Non Empty).
• To create a custom filter, click (Custom...), and then perform the following steps:
i. From the Custom Autofilter dialog box, click the dropdown in the box to the left,
and then click to specify how the custom filter will apply to the filter string you
use.
ii. In the box to the right, enter the filter string you want to use.
iii. For additional filtering options, click the More button, and then specify any of
the following options:
- To match case sensitivity, click to enable Match case.

- To toggle cumulative mode filtering, click the appropriate check box.

- To toggle filtering of non-expanded spreadsheet rows, click Drill-down
filtering.
- To instead use a regular expression, click to enable the appropriate check box,
and then enter the regular expression you want to use.
iv. After you finishing configuring your filter, click Apply.
3. To reduce the display of spreadsheet data (rows) by adding another column criterion,
return to step 2. You can also further filter a column by which you have already filtered.
For example, after filtering the Nets spreadsheet Constraint Class/Net/* column to
display a subset of rows based upon net name, you can cumulatively filter the subset by
net name again.
Rule: You must enable cumulative mode before you can filter using additional criteria.
To Enable Cumulative Mode

From the Filters menu, click Cumulative Mode.
Result: The Cumulative Mode menu item includes a check mark.
To Show the Parent Row of a Child Row

When you have filtered out the parent row of a constraint row (for example, constraint-class
row of an electrical-net row), but need to re-enable it, you can do so by right-clicking the child
row, and then clicking Show Parent.
To Reset the View of Data Rows to All

After you finish working with a subset of spreadsheet data rows, from the Filters menu, click
Levels, and then click Reset.
Example of Filtering the Nets Page to Display Only Electrical Nets (^^^)
In this example, you are interested in displaying only true electrical nets on the CES
Spreadsheet Nets page to focus your current constraint definition task. Because net names can
often times be quite long, and the true electrical net identifier is appended to the end of a net
name (^^^), filtering to display just these nets ensures that you are working on only electrical
nets without having to expand the column width of the Constraint Class/Net/* column to verify
the existence of the electrical net identifier.
To Filter and Display Only Electrical Nets

1. With the CES Spreadsheet Nets page active, expand the constraint class that you want to
work in.

2. With filtering enabled, in the filter row of the Constraint Class/Net/* column, click the
filtering dropdown, and then click (Custom...).
3. In the Custom Autofilter dialog box, set the filter to equals, and then in the box to the
right, enter the following: *^^^
4. After you finish setting the custom filter, click Apply.
Result: The spreadsheet is reduced to display just electrical nets that are part of the (All)
constraint class.
Filtering the CES Spreadsheet by Row Type

When working on CES spreadsheet pages, you can specify the row types that CES displays. For
example, when the active spreadsheet page is Nets, you can choose to display a subset of data
rows that includes only from-tos, pin pairs, and electrical nets. It is important to note that each
spreadsheet page has one or more default row types that are always enabled (for example, the
constraint classes row of the Nets page is always displayed).
Figure 3-6. Filters - Levels Toolbar (Left Side) Showing Nets Page Selections
The above illustration shows the Filters - Levels toolbar from the perspective of the Nets
spreadsheet page being active. The toolbar changes the display of active buttons depending on
the spreadsheet page you are on. As you can see above, five of the eight selections are enabled.
A blue box around each active row type indicates this state.
To Filter the Spreadsheet by Row Type

With a specific spreadsheet page active, from the Filters menu, click Levels, and then click to
choose the row types you want to display.
Alternatives:
• When the Filters - Levels toolbar is enabled (View > Toolbars > Filters - Levels), from
it, click a button to toggle the display of a specific row type. Those that are active have
an outline box around them.
• When the Filters - Main toolbar is enabled (View > Toolbars > Filters - Main), from it,
click . From the Filter Levels dialog box, click to toggle the levels that you want to
display, and then click Apply.
Example: To filter the CES Spreadsheet Parts page to include part pin rows, with the Parts
page active, from the Filter menu, click Levels, and then click to turn on Part Pin.

Resetting the Spreadsheet to its Default View
To Display All Row Types

From the Filters menu, click Levels, and then click All.
To Display No Row Types

From the Filters menu, click Levels, and then click None.
Resetting the Spreadsheet to its Default View

After you work with the CES Spreadsheet for one or more sessions, you may find it necessary to
return it to its default view. When you do so, you can quickly reset the appearance of the
following elements:
• View of available spreadsheet tabs

• Level toggling
• Active constraint group
• Removal of filters and filtering
• Row expansion
To Reset the Spreadsheet to its Default Appearance

From the View menu, click Reset View. This command resets the appearance of row heights
and column widths, and collapses all spreadsheet rows.
Creating Constraint Groups

You can create groups that include a subset of all constraints displayed on either the Nets, Parts,
or Constraint Templates CES Spreadsheet pages. For example, when your constraint
modifications are limited to a common subset of Nets spreadsheet constraints, you can create a
group that includes just those constraints. Doing so gives you the ability to increase the
efficiency with which you modify constraints. When managing other co-workers, creating
unique groups can help to ensure that their focus remains on the appropriate constraint subsets.
Note
Because constraint groups are a subset of all constraints located on a spreadsheet page,
modifying a spreadsheet constraint while in a group view results in the change appearing
in all views.
In the following illustration, a user has created two constraint groups that serve as custom
subsets of the CES Spreadsheet Nets page.

Figure 3-7. Constraint Groups Example
The My Delays Group is a subset containing all delay constraints, both simulated and time of
flight. The other group, My Actuals Group, contains all actual values that are available from the
Nets page of the CES Spreadsheet.
You can modify constraint groups that you create, and also those that are included with CES by
default. The only group that you cannot modify is All. To provide you with greater flexibility,
CES supports two ways of populating and modifying the contents of a constraint group. The
recommended approach is from directly within the CES Spreadsheet.
To Create a Constraint Group

1. From the CES Spreadsheet Nets, Parts, or Constraint Templates page, click the
Group pulldown, and then click Edit Constraint Groups.
Alternative: From the Edit menu, click Constraint Groups.
2. From the Edit Constraint Groups dialog box, click .
3. From the Create New Constraint Group dialog box, enter a name for the group, and then
click OK.
4. Click Apply.
5. Modify or populate the contents of the constraint group in one of the following ways:
• “To Modify a Constraint Group From Directly Within the CES Spreadsheet” on
page 120.
Note: This is the recommended method. You can drag-and-drop columns and
visually review your progress while you make your changes.
• “To Modify a Constraint Group From Within the Constraint Groups Dialog Box” on
page 120.

To Modify a Constraint Group From Directly Within the CES Spreadsheet

Group pulldown, and then select the group you want to modify.
2. Do any of the following things:
• To show specific, hidden constraint columns, right-click the column heading after
which you want to insert columns, and then click Unhide Column(s). From the Add
Column(s) to Group dialog box, select one or more constraints, and then click OK.
Note: When you are working with a new constraint group that you created
previously but did not populate, all available columns are hidden.
• To move a column, use click-drag to move it to a different position within the
spreadsheet.
• To hide specific columns, use click or Ctrl-click to select the column headings, right-
click one of the column headings, and then click Hide Column(s).
• To hide all columns, right-click any column heading, and then click Hide All
Columns.
To Modify a Constraint Group From Within the Constraint Groups Dialog

Box
2. From the Edit Constraint Groups dialog box, click the Select constraint group
dropdown, and then click the constraint group you want to modify.
3. From the Constraints assigned to group list, perform any of the following tasks:
• To remove one or more constraints, use click or Ctrl-click, and then click .
• To remove all constraints, click .
• To add constraints, from the All constraints list, select the constraints that you want
to appear in the group by doing any of the following:
o To add one or more constraints, use click or Ctrl-click, and then click .
o To add all constraints, click .
• To move one or more constraints up or down in the list order, use click or Ctrl-click,
and then click or .
• To move one or more constraints to the top or bottom of the list, use click or Ctrl-
click, and then click or .
Tip: When moving constraints, it can be helpful to keep constraints and their actuals
together.

Working Concurrently With Other Users
4. After you finish modifying a constraint group, click OK or Apply.
To Delete One or More Constraint Groups

2. From the Edit Constraint Groups dialog box, perform any of the following tasks:
• To delete one constraint group, click the Select constraint group dropdown, click the
constraint group you want to delete, and then click .
• To delete all constraint groups, click .
To Restore the Contents of a Default Group

2. From the Edit Constraint Groups dialog box, click the Select constraint group
dropdown, click the default group you want to restore (for example, Delays and
Lengths), and then click .

When multiple users are working on the same front-end or back-end CES database, your CES
session can be updated in real time to highlight the changes of other users. You do so by
enabling indication of remotely modified cells. This causes CES to highlight the background
color of cells that change in any concurrent sessions.
Another way that CES helps ensure effective concurrent design is by temporarily locking a
constraint or object when it is being modified in a parallel session. For more information, please
refer to “Locking of Constraints” on page 107.
To Show Indication of Remotely Changed Constraints

From the View menu, click Remotely Modified Data, and then click to activate Enable
Indication.
To Refresh the Display of Remote Changes

From the View menu, click Remotely Modified Data, and then click Refresh.
You can also change the background color CES uses to indicate remote modifications. For more
information, please refer to “Setting Up CES” on page 59.

Adding Comments to Your Constraint Changes

To help both yourself remember why you made certain changes and also make it clear to other
users working on the same constraint, you can add comments to individual cells on any page of
the CES Spreadsheet. Doing so is especially useful when you want to help ensure that another
user does not change a constraint value that is important to your individual designer goals.
To Add a Comment to a Cell

1. From the CES Spreadsheet, right-click a cell, and then click Insert Comment.
Alternative: From the Comment toolbar, click .
2. From the Comment dialog box, in the text field, enter your comment.
3. Click Apply or Close.
Result: The cell is updated to include a red marker in its upper-right corner to indicate
that a comment has been added to it.
To Edit a Comment
1. From the CES Spreadsheet, right-click a cell that includes a comment, and then click
Edit Comment.
2. From the Comment dialog box, in the text field, modify the comment.
3. Click Apply or Close.
To Delete a Comment
From the CES Spreadsheet, right-click a cell that includes a comment, and then click Delete
Comment.
To View Comments
You can view your comments and those of all other users in the following ways:
• To see a single comment, hover the mouse cursor over a cell that includes a comment.
• To cycle from one comment to the next, from the Comment toolbar, click (next) or
(previous).
• To generate a report that lists all comments, from the Output menu, click Report
Comments.

Viewing Constraint Reference Information
Viewing Constraint Reference Information

The CES User’s Manual includes a full constraint reference. You can access it directly from the
Constraint Spreadsheet, and from within the table of contents (appendix chapter A). A quick-
reference version of this reference chapter is also available. When using the quick reference, if
you need more information, click a constraint name to go to its CES Constraint Reference entry,
which usually includes a graphic to help you understand its purpose within your design.
As an example, in the illustration below, the CES Constraint Reference graphic for the
differential pair constraint Convergence Distance Tolerance is shown.
Figure 3-8. CES Constraint Reference Example Illustration
You can also open the topic for a specific constraint while working within the CES Spreadsheet.
To do so, please refer to the appropriate procedure below.
To Open a Constraint Topic From the CES Spreadsheet

Right-click a constraint cell, and then click Constraint Help.
Viewing Cell Properties

While you are working in the CES Spreadsheet, you can view all properties that are associated
with a constraint cell. This is unlike the constraint reference in that all descriptive and
programmatic information is displayed, and in a modeless dialog box from within CES. As you
activate different constraint cells, the Properties browser is updated to show the appropriate cell
information.
Prerequisites
• The environment variable CES_ENABLE_PROPS must exist; otherwise, cell property
information is not visible.
Procedure
1. From any page of the CES Spreadsheet, right-click a cell, and then click Properties.
Alternative: From the View menu, click to enable Properties.

Viewing Design Statistics
2. From the Properties browser, you can now view all available cell properties.
3. For properties that do not have a default image associated with them, you can optionally
add one from your available library of images, or remove one that you associated
previously. Please refer to the following short procedures:
• To associate an image or change the associated image, in the Image row, click
Browse, and then from the Open File dialog box, browse to the location and
filename of an image file, and then click OK.
• To remove an image or disassociate it, in the Image row, below the Browse button,
click Reset.
Related Topics
• “Quick Reference - CES Constraint Spreadsheet” on page 28
• “CES Constraint Reference” on page 289
Viewing Design Statistics

You can generate a detailed report of design statistics that includes object, connectivity, and
constraint information. It includes totals for each data point (for example, total constraints) and
top-level information like snapshot, block, and EE software installation.
To View Statistics
1. From the Output menu, click Design Statistics.
2. For information about specific numbers that are reported, please refer to the table below.
Technology Parts Versus Technology Models

The number of “Technology Parts” provided in this report provides a count of those used in the
back-end design system. These technology parts are editable only in the back-end design
system, but they are also stored in CES and available in this report. This number does not refer
to the number of technology models available in CES.
Checking Constraints and Synchronization

You can check constraints to verify the data integrity of your local CES database. This is
especially useful when starting with a migrated design. Constraints checking provides
information and errors for multiple aspects of design object relation and net assignment. You
can also check synchronization between your CES database and that of the complimentary
design system’s, front-end or back-end, respectively.

To Check Constraints Synchronization Between the Front-End and Back-

End
1. From the Output menu, click Check Constraints Synchronization.
2. To view the report that was created, click Yes.
In the event that synchronization checking fails, please ensure that you are properly connected
to appropriate client systems. You can also view the report for more information.
To Check Constraints
1. From the Tools menu, click CES Diagnostics.
2. To view the report that was created please refer to the Output window, CES Diagnostics
tab.
Result: The report shows the results of many diagnostics tests. Each test indicates
whether the CES data has passed or failed. In the event that a test has failed, and the
error is automatically fixable by CES, the report will show a link at the bottom that gives
you the ability automatically fix all errors that fall into this category.
Optional: You can cross probe from the report to problematic design objects by clicking
a link on any available error rows.
Correcting CES Diagnostics Errors

After you check constraints integrity, the status bar of CES will display one of the following
types of exclamation points when your CES database has integrity problems:
• Red exclamation point – Please contact customer support to get help with fixing these
problems. You will need their assistance.
• Yellow exclamation point – Please attempt to fix these problems yourself by using CES
documentation to make changes based on the reported errors.
When your CES database does not have any integrity problems, the status bar does not display
an indicator. It only displays an indicator in the event that there is problematic data. It is
important to understand that CES will display some errors that are not fixable through CES.
Instead, you would have to do so through your schematic capture program, or another piece of
software. In these cases, the error report tries to make it clear that the error must be fixed outside
of CES.
To Fix All Automatically Fixable Errors

In the event that you have errors that can be fixed automatically by CES, you can click a link at
the bottom of error report to do so.

Note
After you have CES fix errors, it will reload when necessary. This is to ensure that CES
shows the correct constraint data based on changes that occurred during the process of
making automatic fixes.
To Fix Errors That Must be Fixed Manually

In the event that you have CES errors that can only be fixed manually in CES, you should use
CES documentation to make the appropriate fixes. In some cases, the error will provide a link to
the exact documentation that you must use to fix the error.
Listing of CES Diagnostics Tests

Each of the diagnostics tests that CES performs is described in the table below. This
information is in the tooltip that CES displays when you hover the mouse over a specific test in
the report.
Table 3-2. CES Diagnostics Tests

Test Purpose
CES database initialization Checks if CES database is correctly initialized.
Net class name unique Checks if net class name is unique on given level of
hierarchy.
Constraint class name Checks if constraint class name is unique on given level of
unique hierarchy.
Scheme and clearance rule Checks if scheme names and clearance rule names are
name unique unique.
Clearance rule in all Checks if clearance rule exists in all schemes.
schemes
Net class in all schemes Checks if all rule-area schemes include all defined net
classes.
Layer consistency Checks if layers contain all required and valid data.
Layer in all net classes Checks if all net classes include the full listing of board
layers.
Layer in all z-axis clearance Checks if layer exists in all z-axis clearance rules.
rules
Victims and aggressors Checks if victims and aggressors in noise rules exist.
valid
Component valid Checks if all components are valid in terms of references
to pins.
Pin in net and component Checks if pin belonging to net also belongs to component.

Table 3-2. CES Diagnostics Tests (cont.)

Test Purpose
Component name unique Checks if all component names are unique within the
design.
Pin sets consistency Checks if pins in pin sets belong to physical net.
Physical net unique Checks if physical net name is unique.
Pin reference to net valid Checks if pin has a proper reference to physical net.
Electrical net unique Checks if electrical net name is unique.
Electrical net consistency Checks if all electrical nets contain correct physical nets.
Analog nets consistency Checks if each analog electrical net consists of only one
physical net.
All used constraint classes Checks if all constraint classes used by electrical nets and
valid differential pairs exist in the design.
All used net classes valid Checks if all net classes used by electrical nets and
differential pairs exist in the design.
Differential pair with two Checks if all differential pairs have two existing and
electrical nets different electrical nets.
Electrical nets belonging to Checks if electrical nets belonging to differential pair have
differential pair assigned to the same net class.
the same net class
Unique pin pairs in Checks if pin pairs in electrical net are unique.
electrical net
Connection pin pairs in Checks if valid connection pin pairs exist in electrical nets
electrical net that contain multiple physical nets.
Power net topology Checks if power net has the proper topology.
Unique fromtos in physical Checks if all fromtos in physical net are unique.
net
Fromto in only one net Checks if pin referenced by fromto belongs to the same
physical net as the fromto.
Constraints consistency Checks consistency of constraints. This test also reports
empty constraints.
Default objects Checks if standard and default objects exist for schemes,
clearance rules and net classes.
Mapping of schematic and Checks if all schematic nets and physical nets are mapped
physical nets correctly.
Reference designator vs. Checks if attribute 'Ref Designator' is the same as CES
component name component name.

Validating Constraints Against PCB Actuals
Table 3-2. CES Diagnostics Tests (cont.)

Test Purpose
Via span valid Checks if the via span is valid.
Unique virtual pin names Checks if virtual pin names are unique in the design.
Schemes and rules in all Checks if all schemes exist for class to class clearance
class to class clearance rules rules.
Unique template names Checks if template names are unique in the design.
Valid template Checks if content of constraint templates are valid.
All used package clearance Checks if each package clearance-type rule is fully
type rules valid defined.
Physical net topology Checks if physical net topologies are consistent. This test
also checks for virtual pins in complex topologies.

You can validate CES constraint data against actual PCB data to determine whether specific
constraint values need to be modified to better promote signal integrity and routing
requirements.
Actuals displayed in CES are provided through one of two mechanisms:
• AutoActive – Calculates all actuals except for simulation actuals, which are calculated
by ICX Pro Verify.
• ICX Pro Verify – Calculates simulation actuals (for example, Crosstalk Sim Actual,
Simulated Delay Actual Range, and so on). Simulation actuals usually include a
button in the actual field.
Note
The CES actuals menu selections referenced in this section are only available in CES
sessions launched from a back-end design system. When you want to work with actuals
in a front-end CES session, please refer to “Sharing PCB Actuals With Front-End CES
Sessions” on page 131.
Common Tasks
• “Updating Actuals Displayed in CES” on page 129
• “Clearing Actuals From the CES Spreadsheet” on page 130
• “Highlighting Constraint Differences” on page 130
• “Sharing PCB Actuals With Front-End CES Sessions” on page 131

• “Viewing All Constraint Violations” on page 132
To Validate Constraints
1. From the Data menu, click Connect to Board Station RE/Expedition.
Note: Typically, when you launch CES it is automatically connected to Board Station
XE/RE or Expedition PCB. This menu option is not present when you are already
connected.
2. When you do not have CES configured to automatically update actuals on start-up, from
the Data menu, click Actuals, and then click Update All to show actuals on the CES
Spreadsheet.
Note: When automatic display of actuals is not enabled, you must perform this step each
time you launch a new invocation of CES.
Tip: To make the display of actuals a seamless part of your back-end or front-end CES
session, there are several settings you can enable. For more information, please refer to
“To Specify Other Preferences” on page 69.
When constraint validation is available, you can easily see which constraints are resulting in
actuals that are approaching or exceeding a constraint threshold, or moving out of a minimum
and maximum constraint range. To make such distinctions clear, CES backlights actual
spreadsheet fields with one of two colors, which respectively indicate whether an actual is out
of range, or close to being out of range. During the process of setting up CES, you can specify
the backlight colors that CES uses.
Figure 3-9. CES Color-Codes Actuals to Indicate Violations
Rule: In order to perform this type of validation, you must update routing results from a
supported router (for example, Board Station XE or Expedition PCB).
Updating Actuals Displayed in CES

When engineering efforts are being performed simultaneously in both CES and the router to
which CES is connected, you may want to periodically update/refresh the actuals that are in
CES to reflect changes to actuals produced by the router.

To Update All Net Actuals

From the Data menu, click Actuals, and then click Update All.
To Update Selected Net Actuals

1. On a CES Spreadsheet page, click, Ctrl-click, or Shift-click to select one or more nets.
Rule: In order to update net actuals, cross probing must be enabled. To do so, from the
Setup menu, click to enabling Cross Probing.
2. From the Data menu, click Actuals, and then click Update Selected.
Clearing Actuals From the CES Spreadsheet

In some cases, you may want to clear the actual values displayed on one or more CES
Spreadsheet pages. Please use the following procedures to clear actual data from the
spreadsheet.
To Clear Actuals From All Spreadsheet Pages

From the Data menu, click Actuals, and then click Clear All Pages.
To Clear Actuals From the Current Spreadsheet Page

From the Data menu, click Actuals, and then click Clear This Page.
Highlighting Constraint Differences

By having CES highlight all constraint differences, you can more-easily see which constraint
values are exceeded by actual values. When in this mode of operation, CES also highlights
hierarchical constraint differences. For example, an electrical net comprised of two physical
nets has three separate constraint values for # Vias Max. Based on net hierarchy, the sum of the
two physical net values equals the electrical net value. This is an accepted hierarchical
constraint difference that is easier to verify in this mode. In the example illustration below, each
physical net has a # Vias Max value of 2. The higher-level electrical net value for # Vias Max is
4, which is the correct value based on constraint hierarchy (that is, sum of the two physical net #
Vias Max values).

Figure 3-10. Hierarchical Constraint Differences
To Highlight Constraint Differences

From the View menu, click Update Differences.
To Clear Highlighted Differences

From the View menu, click Clear Differences.
Sharing PCB Actuals With Front-End CES Sessions

Although PCB actuals are generated as part of back-end constraint calculations, you can also
share those values with front-end CES sessions. This is especially useful when the logic
engineers on your design team are interested in the actual values that are being generated on the
back end. This is also helpful for promoting general cohesion between design-team members.
The team member who performs which of the actions in the procedure below will vary
depending on your design process. For a small design team, a single person might perform the
procedure in its entirety. For large design teams working on very complex designs, a schematic
designer would typically make a call or send an email to request that a PCB layout engineer
perform step 1 to export actuals. An alternative to that approach would be to adopt a process
where actuals are exported at multiple, scheduled times each day, or automatically each time
they are updated.
Streamlining the Process of Sharing Actuals

There are several settings you can enable to make the display of actuals a nearly automatic part
of your front-end CES session. To do this, you must enable unique settings in both front-end
CES and back-end CES, respectively. For general information on these settings, please refer to
“To Specify Other Preferences” on page 69. The procedure below points out each setting as it
relates to streamlining the manual process.
Prerequisites
• None.

Procedure
1. In a back-end invocation of CES, from the File menu, click Export, and then click
Actuals.
Alternative: You can have CES do this automatically each time you update actuals by
enabling a setting in your back-end invocation. From the Setup menu, click Settings.
From the Settings dialog box, click Other, and then under Actuals, enable the following
option: Export actuals to front-end.
2. From the Output log window, verify that the actual values have been successfully
exported.
For example: “Expedition actuals side file was exported on Thu Mar 08 16:22:22 2012.”
3. In a front-end invocation of CES, from the Data menu, click Actuals, and then click
Import Layout Actuals. To include thermal values, click Import Thermal Actuals as
a second selection.
Tip: You can configure your front-end invocation of CES such that you are notified
when updated actuals are available for import. To do this, from the Setup menu, click
Settings. From the Settings dialog box, click Other, and then under Actuals, enable the
following option: Show alert that new actuals can be imported.
Tip: To further facilitate the sharing of actuals data between the front-end and back-end,
you can enable an additional setting to automatically update CES actuals upon start up.
When used together with the settings mentioned in the above procedure, back-end CES
automatically updates actual values when you load it, which in turn causes them to be
exported to front-end CES. The next time you open front-end CES, the updated actual
values from the back end are automatically pulled in.
You can enable this setting separately in each invocation of CES. To do this, from the
Setup menu, click Settings. From the Settings dialog box, click Other, and then under
Actuals, enable the following option: Auto update on start up.
Results
Actual values are displayed in the front-end invocation of CES in the appropriate actual cells of
CES Spreadsheet.
Viewing All Constraint Violations

Aside from locating constraint violations within specific pages of the CES Spreadsheet, you can
quickly generate a list of all actuals that are producing constraint violations. The Constraint
Violations dialog box is modeless, so you can conveniently keep it on screen for prolonged
periods of time. To update its display, click Refresh.

Updating Electrical Net Data and Results
To View All Constraint Violations

1. From the Data menu, click Constraint Violations.
2. From the list of Constraint cautions and violations, refer to the Constraint and Object
columns to determine problematic constraints.
3. Optionally, do any of the following:
• To display just violations, click to enable the Show only violations check box.
• To hide any revised constraint rows, click to enable the Show only unrevised check
box.
• To mark a constraint as revised, click to enable its Revised check box.
Alternative: To do this from the CES Spreadsheet, right-click a constraint cell, click
Mark As, and then click Revised.
• To cross probe to the CES Spreadsheet row to which a constraint caution or violation
refers, click a list row.
Alternative: To move up or down one row in the violations list while cross probing,
click or .
Updating Electrical Net Data and Results

After you assign IBIS models to parts, electrical nets are automatically updated to include
changes based on the technology information in your IBIS models. When a new IBIS model
requires two or more existing electrical nets to be joined, CES resolves existing constraint
values.
When you are using ICX Pro Verify as part of your constraint-driven design flow, you can
update CES to ensure that it includes the most recent simulation actuals produced by ICX Pro
Verify. Simulation actuals include simulated delay constraints and overshoot/ringback
constraints (for example, Simulated Delay Max Range, Dynamic High Overshoot Max, and so
on).
Note
In order to use these features, you must have an Electrical CES license.
To Update ICX Pro Verify Simulation Results

From the Data menu, click Update, and then click Simulation Results.

Painting Rules to Reuse Constraints
Resolving Existing Constraint Values

When two or more existing electrical nets are joined into a larger electrical net due to new IBIS
model assignments, CES resolves the unique constraint values in each constituent net based on
the following rules:
• The minimum Simulated Delay Min constraint value is used; the maximum Simulated
Delay Max constraint value is applied.
• The minimum Ringback Low Max constraint value is used; the maximum Ringback
High Max constraint value is applied.
• The minimum Static Low Overshoot Max constraint value is used; the maximum Static
High Overshoot Max constraint value is applied.
• Dynamic Low Overshoot Max and Dynamic High Overshoot Max constraint values are
removed from the new electrical net.

You can quickly copy all constraint values that you define in a spreadsheet row into the rows of
other design objects that will benefit from these values. When painting rules to copy constraint
values, it is important to remember that the design object from which you copy must be the
same as the design object to which you copy.
For example, when reusing the constraint values of a specific net row, make sure that you apply
them to another net row. It is the same type of design object.
To Copy Constraint Values of One Spreadsheet Row to Another Row

1. From the CES Spreadsheet, click a scheme, net class, constraint class, layer, or net row,
and then from the Edit menu, click Rule Painter.
2. Click the spreadsheet row for which you want to apply the copied constraint values.
3. Continue clicking additional rows to paint these rules where appropriate.
4. To turn off the Rule Painter, from the Edit menu, click Rule Painter.
Example of Copying Board Layer Constraint Values to Another Board Layer

1. From the CES Spreadsheet Trace & Via Properties page, expand a scheme, a net class,
and then click the layer that holds the constraint values you want to duplicate.
2. From the Edit menu, click Rule Painter.
3. From the CES Spreadsheet, click the row of the layer to which you want to apply the
duplicate constraint values.

Rolling Back and Undoing Constraint Changes
4. To apply these values to another layer, click it. When you finish, from the Edit menu,
click Rule Painter to disable rule painting.
Rolling Back and Undoing Constraint Changes

You can revert constraint changes made at any time during your current CES session. This
includes all commands for which undo/redo is supported. For example, modifying constraint
classes and net classes, adding clearance rules, and creating differential pairs. For a full listing
of supported actions, please refer to the table below.
Note
When rolling back constraint changes made in CES, the forward and back annotation
indicator lights for your design flow do not reflect these undo actions. For example, after
you make a single change in back-end CES and then rollback that change, your back-end
system will still indicate that you need to perform back annotation.
To Roll Back All Constraint Changes

1. From the File menu, click Rollback Changes.
2. From the Rollback Changes dialog box, click Rollback.
Note: The Status column displays “Pending,” “In Progress,” “Conflict,” or “Restored”
for each row. Each entry starts out as pending. When you successfully roll back a
change, the field displays “restored.” For undo actions that take longer to process you
will see “in progress” displayed before it is moved to a resolved state. When a change
cannot be undone due to change conflicts, the Status field indicates this condition.
In addition to rolling back all changes, CES also supports an enhanced interface for undoing or
redoing multiple changes, beginning with the most recent undo or redo action. For example,
after making three consecutive constraint changes, you can quickly use the standard CES GUI
to undo all three changes without pressing Ctrl-Z multiple times. This approach also gives you a
visual indication of the most recent changes that can be undone.
When undoing or redoing changes, all actions following the selected action are also reverted or
restored. For example, when you create three net classes, beginning with Net Class A and
ending with Net Class C, undoing the creation of Net Class B results in the deletion of Net Class
A as well.
To Undo One or More Changes

1. From the General toolbar, next to , click the dropdown button.
2. In the list of changes you can undo, hover over one or more changes, and then click.

Viewing and Reverting to Parent Cell Values
To Redo One or More Changes

1. From the General toolbar, next to , click the dropdown button.
2. In the list of changes you can redo, hover over one or more changes, and then click.
Supported Undo/Redo Actions

You can roll back, undo, and redo the following CES changes.,
Table 3-3. Supported Undo/Redo Actions

Design Object Actions
Clearance rule Add, remove, and rename.
Constraint Add, change, propagate,
rule painter, copy, and
paste.
Constraint class Net assignment to class,
add, remove, and rename.
Differential pair Add, remove, and auto-
assign.
Net class Net assignment to class,
add, remove, and rename.
Noise rule Add and remove.
Pin pair Auto pin-pair, manual pin-
pair, and remove.
Rule-area scheme Add, remove, and rename.
Template Rename.
Z-axis clearance rule Add, remove and rename.
Viewing and Reverting to Parent Cell Values

You can view the parent value of a constraint cell to determine the assigned value at the next,
upper level of hierarchy. For example, when you have a constraint class that includes a large
number of nets, and many of the values for a specific constraint differ from the value at the
constraint class level, you can view the value at the constraint-class level without having to
change your place on the CES Spreadsheet.
In addition to viewing parent values, you can also revert an overridden value to its parent value,
when it is appropriate to do so. In the event that you have filtered the listing of spreadsheet
rows, you can also show a parent row when it is hidden from view.

Saving Constraint Changes
Prerequisites
• None.
Procedure
1. From the CES Spreadsheet, right-click the cell of interest, and then do one of the
following things:
• To see what the cell value is at the next, upper level of hierarchy, click Show Parent
Value. As a result, the Output log window is updated to include a new line of text
that displays this value.
• To revert the cell value to value of the parent cell, click Reset to Parent Value.
• In the event that you are using row filtering and the row for a parent cell is hidden,
you can click Show Parent to enable display of the hidden parent row.
Results
Depending on the task you wanted to accomplish, you now know the value of a parent cell, have
reset an overridden cell to its parent cell value, or enabled display of a parent row that was
hidden due to row filtering.

After you make constraint changes through the CES Spreadsheet and other constraint-entry
mechanisms, they are saved automatically in your front-end or back-end CES database;
however, the changes may not persist unless you perform a save in the tool from which you
launched CES (for example, Expedition PCB).
Caution
Some design tools automatically save your design data (for example, DxDesigner).
Depending on the tool from which you launched CES, you may not have to explicitly
save. Please refer to the documentation for your design tool for information about saving
design changes in your invocation tool.
To Save Constraint Changes

You can do this in the following ways:
• After you exit a CES session, from the invocation tool, save your design (if required).
• When working in a CES session launched from the back-end, at the bottom-right corner
of your PCB layout tool, click the rightmost status indicator to load the changes into the
back-end, and then save your design in the PCB layout software.


Chapter 4
Net Class Creation
This section covers net class creation. Some of the topics included are creation of net classes,
net addition, and determination of net class assignments. This section also provides information
about creating a net class from an existing net class, and deletion of net classes. Please refer to
the table of contents for the full listing of topics included in this section.
Creating Net Classes

You can create net classes to group specific types of nets and then define board-level
physical/manufacturing constraints for multiple nets. For example, you can group nets based on
their function, or level of importance within a design. When grouping nets based on function,
you might classify them to differentiate power and ground nets from signal nets. Net class
constraints are located on the CES Spreadsheet Trace & Via Properties page.
When grouping nets based on their level of design importance, you could classify them to
differentiate critical nets in a design from non-critical nets. For example, a critical net class
could contain data nets that serve as the connections between microprocessors and other critical
connections that require a high-degree of signal integrity.
Note
Initially, all nets are assigned to the (Default) net class.
Creating Net Class Hierarchy

After you create a net class, you can create classes that are hierarchically arranged below it. For
example, after creating a top-level class for all signal nets (for example, “Signal Nets”) in a
design, you could add hierarchy to the net class by creating additional classes that sit below
“Signal Nets” to further group the collection of nets that comprise this net class. In the example
below, the Signal Nets class contains two additional classes, which are “Critical Nets” and
“Non-Critical Nets.”

Net Class Creation
Creating Net Classes
Figure 4-1. Navigator Showing Signal Nets Class with Two Additional
Hierarchical Classes
Tip: From the CES Navigator, you can drag and drop net classes into other net classes to
create or redefine hierarchy. When your goal is to drag multiple net classes at the same
time, after you use Ctrl-click to select them, you must continue to hold the Ctrl key while
you drag them.
When creating net class hierarchy, a common approach is to create additional levels of
hierarchy on an as-needed basis. For example, as you define common constraint values for a
class of nets, you may find that several of the nets benefit from most of the constraint values, but
require unique values for a few constraints. In this case, you can create a subclass for these
“more challenging” nets, move those nets into this subclass, and then modify the constraint
values that need more work. You do not need to redefine the other, working constraints because
each subclass is created to include the constraint values of its parent class.
To Create a Net Class

1. From the Navigator, right-click Net Classes, and then click New Net Class.
Alternative: From the CES Spreadsheet Trace & Via Properties page, right-click a
scheme, and then click New Net Class.
2. Replace the default name “<user>_New” with a name for the net class.
Rule: Net class names can contain up to 128 characters but cannot include the “/” or “!”
characters. Spaces are allowed in net class names.
Tip: Use a name that reflects the purpose of the class. For example, when creating a net
class that will contain only signal nets, replace “New” with “Signal Nets.”
To Create Hierarchy Under a Net Class

1. From the Navigator, expand Net Classes. Right-click a net class, and then click New.
Alternative: From the CES Spreadsheet Trace & Via Properties page, expand any
scheme, right-click a net class, and then click New.

Net Class Creation
Adding Nets to a Net Class
2. Replace the default name “<user>_New” with a unique name for the hierarchical net
class.
Note: You can create multiple levels of hierarchy.
To Rename a Net Class

1. From the Navigator, expand Net Classes.
2. Right-click a net class, click Rename, type a new name, and then press Enter.
Adding Nets to a Net Class

After you create a net class, you must define the group of nets that comprise the net class. By
default, each net class that you create contains no nets or constraint definitions. When you want
to create a net class that includes the constraint definitions of an existing net class, you do so by
creating a net class from an existing class instead of creating a new net class.
Note
Each net can belong to no more than one net class.
Other Common Tasks

• “Adding Power Nets to a Net Class” on page 142
To Add Nets to a Net Class

1. With the CES Spreadsheet Trace & Via Properties page active, from the Edit menu,
click Assign Nets to Classes.
Alternatives:
• From the Navigator, expand Net Classes, right-click a net class, and then click
Assign Nets.
• From the CES Spreadsheet Nets page, select one or more nets, right-click a selected
net, and then click Assign Net(s) to Net Class. From the Select Net Class dialog
box, select a net class, and then click OK. When using this option, you do not need
to finish this procedure.
2. From the Assign Physical Nets to Net Class dialog box, specify the net class from which
you want to select nets by clicking the Source Net Class dropdown, and then clicking a
net class.
Example: When you are adding nets to your first custom class you can select from all
nets in the design by specifying the Default class as the source.

Net Class Creation
Creating a Net Class From an Existing Net Class
3. Specify the net class to which you want to add nets by clicking the Target Net Class
dropdown, and then clicking a net class.
4. Under the nets in source net class listing, specify the nets that you want to add to the
target class.
Tip: To select multiple nets, you can use Ctrl-click, Shift-click, or click-drag. To select
nets by name, in the field below the list of source nets, enter a search string, and then
click . To sort the list of nets, click the Net Name label. You can also move nets
individually by double-clicking a specific source net.
5. Click , and then click Apply or OK.
Tip: Before clicking OK, make sure that the list of target nets is accurate. To remove
any nets from the list of target nets, click to select them, and then click .
Result: The target nets are added to the net class; these nets are no longer a part of the
source class from which they originated.
Example of Adding All Available Nets in a Source Net Class to a Target Net
Class
1. From the Assign Physical Nets to Net Class dialog box, specify a source net class, and
then specify a target net class.
2. Click , and then click OK.
Example of Swapping All Nets in One Net Class With All Nets in Another
Net Class
1. From the Assign Physical Nets to Net Class dialog box, specify a source net class, and
then specify a target net class.
Adding Power Nets to a Net Class

Because power nets are not displayed on the CES Spreadsheet Nets page by default, you must
use the Assign Physical Nets to Net Class dialog box to move them from the (Default) net class
to another net class for more specific board-layer constraint definitions. To do so, please use the
above procedure, “To Add Nets to a Net Class” on page 141.
Creating a Net Class From an Existing Net Class

You can create a new net class from an existing class to quickly create one that includes the
same constraint definitions as the source net class. For example, after creating a base net class
for most signal nets in your design, you can duplicate it, and then modify the constraint
definitions in the new class.

Net Class Creation
Deleting Net Classes
Tip: It is important to remember that creating a net class from an existing net class copies
constraints and not nets. After you create a copy, make sure you assign the appropriate
nets to it.
To Create a Net Class From an Existing Net Class

1. From the Navigator, expand Net Classes, right-click a net class, and then click Clone.
2. Right-click the name of the clone/copy, click Rename, and then enter a different name.
3. Specify the group of nets that comprise the new class by assigning nets to this net class,
and removing nets from it.
4. Modify the physical constraint values defined in this class such that they are appropriate
for the nets you added to this class in the previous step.
Related Topics
• “Adding Nets to a Net Class” on page 141

You can delete net classes that you no longer require. Prior to deleting a net class, make sure it
is the appropriate class to delete. Before deletion of a net class, CES prompts you to verify that
you have selected the intended net class. After you delete a net class, you can re-add it to the list
of net classes using undo or rollback.
Prerequisites
• Empty the contents of the net class by moving each net contained within it to a different
class.
• Remove any net class sub-hierarchy (that is, child net classes within the parent net
class).
• Delete references to the net class in any class-to-class clearance rules.
To Delete a Net Class

From the Navigator, expand Net Classes, right-click a net class, and then click Delete or press
the Delete key.

Net Class Creation

Chapter 5
Constraint Class Creation
This section covers constraint class creation. Some of the topics included are creation of
constraint classes, net addition, and auto-creation of bus constraint classes. This section also
provides information about creating a constraint class from an existing constraint class, and
deletion of constraint classes. Please refer to the table of contents for the full listing of topics
included in this section.
Creating Constraint Classes

You can create constraint classes to group specific nets and then define electrical and signal
integrity constraints such as length or time-of-flight delay values and overshoot/ringback
voltages. Constraint class constraints are located on the CES Spreadsheet Nets and Noise Rules
pages. After you create a constraint class, you can create more constraint classes below it to
create hierarchy among nets within a constraint class. By doing so, you can apply general
constraints to all nets within the constraint class hierarchy, and then apply more specific
electrical, signal integrity, and high-speed signal integrity constraints to the nets that make up
the further groupings of constraint classes.
For example, after creating a constraint class that contains a dozen similar critical nets and
applying the same rules to each net in the constraint class, you find that two or three of the nets
in the constraint class do not promote signal integrity when they use a few of the rules
designated in the top-level constraint class. To assign slightly different rules to these nets that
require a higher-level of signal integrity, you can create a constraint class within the top-level
constraint class, move these critical nets into the hierarchical constraint class, and then modify
specific electrical rules.
Note
At first, all nets are automatically assigned to the (All) constraint class.
Creating Constraint Class Hierarchy

After you create a constraint class, you can create more constraint classes that are hierarchically
arranged below it. For example, after creating a top-level class for all bus nets (for example,
“Bus Nets”) in a design that should share many of the same electrical rules, you could add
hierarchy to the constraint class by creating additional classes that sit below “Bus Nets” to
further group the collection of nets that comprise this constraint class. In the example below, the
Bus Nets constraint class contains two additional classes, which are “8-bit” and “16-bit.”

Creating Constraint Classes
Figure 5-1. Navigator Showing Bus Nets Constraint Class With Two Additional
Hierarchical Classes
Tip: From the CES Navigator, you can drag and drop constraint classes into other
constraint classes to create or redefine hierarchy. When your goal is to drag multiple
constraint classes at the same time, after you use Ctrl-click to select them, you must
continue to hold the Ctrl key while you drag them.
To Create a Constraint Class

1. From the Navigator, right-click Constraint Classes, and then click New Constraint
Class.
Alternative: From the CES Spreadsheet Nets page, right-click a constraint class, and
then click New Top Level Class.
2. Replace the default name “<user>_New” with a name for the constraint class.
Rule: Constraint class names can contain up to 128 characters but cannot include the “\”
or “!” characters. Spaces are allowed in constraint class names.
Tip: Use a name that reflects the purpose of the constraint class. For example, when
creating a constraint class that will contain only signal nets, replace “New” with “Signal
Nets.”
To Create Hierarchy Under a Constraint Class

1. From the Navigator, expand Constraint Classes. Right-click a constraint class, and then
click New.
Alternative: From the CES Spreadsheet Nets page, right-click a constraint class, and
then click New.

Adding Nets to a Constraint Class
2. Replace the default name “<user>_New” with a unique name for the hierarchical
constraint class.
Note: You can create multiple levels of hierarchy.
To Rename a Constraint Class

1. From the Navigator, expand Constraint Classes.
2. Right-click a constraint class, click Rename, type a new name, and then press Enter.
Adding Nets to a Constraint Class

After you create a constraint class, you can assign nets to it. By default, each constraint class
you create contains no nets or constraint definitions. When you want to create a constraint class
that includes the constraint definitions of an existing constraint class, you do so by creating a
constraint class from an existing constraint class instead of creating a new constraint class.
Note
Each net can belong to no more than one constraint class.
To Add Nets to a Constraint Class

1. With the CES Spreadsheet Nets page active, from the Edit menu, click Assign Nets to
Classes.
Alternatives:
• From the Navigator, expand Constraint Classes, right-click a constraint class, and
then click Assign Nets.
• From the CES Spreadsheet Nets page, select one or more nets, right-click a selected
net, and then click Assign Net(s) to Constraint Class. From the Select Constraint
Class dialog box, select a constraint class, and then click OK. When using this
option, you do not need to finish this procedure.
2. From the Assign Nets to Constraint Class dialog box, specify the constraint class from
which you want to select nets by clicking the Source Constraint Class dropdown, and
then clicking a constraint class.
Example: When you are adding nets to your first custom constraint class you can select
from all nets in the design by specifying the (All) constraint class as the source.
3. Specify the constraint class to which you want to add nets by clicking the Target
Constraint Class dropdown, and then clicking a constraint class.
4. Optionally, limit the source and target net listings to just physical nets. To do so, click to
enable Use physical nets.

Defining Bus Constraint Classes Automatically
5. Under the nets in source constraint class listing, specify the nets that you want to add to
the target class.
Tip: To select multiple nets, you can use Ctrl-click, Shift-click, or click-drag. To select
nets by name, in the field below the list of source nets, enter a search string, and then
click . To sort the list of nets, click .
6. Click , and then click Apply or OK.
Tip: Before clicking OK, make sure that the list of target nets is accurate. To remove
any nets from the list of target nets, click to select them, and then click .
Result: The target nets are added to the constraint class; these nets are no longer a part
of the source class from which they originated.
Example of Adding All Available Nets in a Source Constraint Class to a

Target Constraint Class
1. From the Assign Nets to Constraint Class dialog box, specify a source constraint class,
and then specify a target constraint class.
Example of Swapping All Nets in One Constraint Class With All Nets in
Another Constraint Class
1. From the Assign Nets to Constraint Class dialog box, specify a source constraint class,
and then specify a target constraint class.
Note: When you create a new constraint class while the Assign Nets to Constraint Class
dialog box is displayed, the drop down lists are updated appropriately.

You can automate the process of defining and adding nets to unique constraint classes to group
all nets that comprise a bus. Automating this saves time and reduces the instance of error when
performing this task manually. After you give CES the approval to create each constraint class
and move the appropriate nets into the new classes, the Bus constraint for each resultant
constraint class is enabled.
Note
The Bus constraint is used to indicate that your PCB layout software should enable bus
planning and routing capabilities for a specific constraint class.
Depending on your constraint-entry process, you will define bus classes before or after creating
constraint classes. Regardless of the process you use, CES makes it easy to keep track of the

previous constraint class to which you assigned a net by creating a bus class as a sub-class of the
original class. For example, when you automatically create bus classes for nets that originate
from the default constraint class, (All), each new constraint class is a sub-class of the (All) class.
Note
After nets are assigned to newly created bus constraint classes, each net in the class is
assigned to a single net class.
Determining Nets That Comprise a Bus

CES uses one of three methods to determine which nets it should suggest for grouping as a new
constraint class:
• Digit suffix – CES suggests constraint classes using nets that include numeric characters
at the end of a net name (for example, MicroNet0 and MicroNet1). The resultant
constraint class name is the common part of the net name (for example, MicroNet).
Default: The default match type is Digit suffix.
• Bus nets – CES suggests constraint classes using nets that include typical bus-net
characters (for example, ~ and _) within a net name. The name of the resultant constraint
class includes a digit range at the end that indicates the number of nets in this class. For
example, Primary_Bus[3:0] means that this bus constraint class will includes four nets:
net zero, net one, net two, and net three.
• Custom net match string – Enter a custom search string using letters, numbers and
wildcard characters like “*” and “?”. This method is especially useful when one of the
above methods cannot be used due to an uncommon naming convention for nets.
To Define Bus Constraint Classes Automatically

1. With the CES Spreadsheet Nets page active, from the Edit menu, click Auto Bus.
2. From the Auto Assign Bus dialog box, in the Electrical Net Match String pulldown,
specify the match type you want to use, and then click .
Result: Under Proposed busses, CES creates a row for each suggested bus. The
Suggested Bus Name cell indicates the new constraint class name that appropriate nets
will be moved into.
3. Optionally, to have CES group bus nets into constraint classes that contain no fewer than
a specific number of nets, activate the Minimum Bus Width checkbox, and then modify
the numerical value in the field to the right to reflect your requirement.
4. You should now verify the suggested nets for each proposed bus constraint class. To do
so, next to the Suggested Bus Name, click .

5. From the Assign Nets to New Bus Constraint Class dialog box, under Nets in new bus
constraint class, verify that the list of nets is appropriate (or make adjustments), and then
click OK. You can perform the following tasks with this dialog box:
• To move a suggested net out of the list, keeping it in its present constraint class, click
.
• To move a net from an existing constraint class into the list of nets that will comprise
the new bus constraint class, use the Existing Constraint Classes pulldown and the
Nets in existing constraint class list to select the appropriate nets, and then click .
6. From the Auto Assign Bus dialog box, select the proposed bus constraint classes that
you want to create by placing a checkmark beside each appropriate Suggested Bus
Name.
Note: By default, all proposed bus constraint classes are marked for creation. To quickly
de-select all rows, click . To quickly select all rows, click .
Rule: The Net Classes cell for each proposed bus constraint class lists all net classes that
the proposed list of nets are currently assigned to. After a bus constraint class is created,
each net is moved into the first net class listed in the Net Classes cell.
7. For the proposed constraint classes you select, resolve any naming errors, which are
indicated by shading the background color of a Suggested Bus Name cell. In the
following example, the backslash character needs to be removed from the Suggested
Bus Name to satisfy syntax requirements.
Figure 5-2. Suggested Bus Name With a Syntax Problem (Backslash Character)
8. After you select the proposed bus constraint classes to create, and resolve any naming
errors, click OK.
Result: CES creates a new constraint class for each proposed bus that you selected and
moves the appropriate nets into the new constraint classes.
Related Constraints
• “Bus” on page 336

Creating a Constraint Class From an Existing Constraint Class
Creating a Constraint Class From an Existing

Constraint Class
You can create a constraint class from an existing one to quickly duplicate the same electrical
and signal integrity rules and use them as the starting point for a new constraint class. For
example, after creating a constraint class that defines many rules for signal nets, you can
duplicate it, add specific nets to it, and then modify the rules that were copied over from the
original constraint class to make them appropriate for another group of nets.
Note
When you create a constraint class from an existing constraint class, the nets in the
existing constraint class remain in that constraint class.
To Create a Constraint Class From an Existing Constraint Class

1. From the Navigator, expand Constraint Classes, right-click a constraint class, and then
click Clone.
2. Right-click the name of the clone/copy, click Rename, and then enter a different name.
3. Specify the group of nets that comprise the new class by adding nets to this constraint
class.
4. Modify the constraint values defined in this class such that they are appropriate for the
nets you added to this class in the previous step.
Related Topics
• “Adding Nets to a Constraint Class” on page 147
Deleting Constraint Classes

After you delete a constraint class, any nets that were assigned to it are returned to the (All)
constraint class. Before deleting a constraint class, make sure it is the appropriate class to delete.
Before deletion of a constraint class, CES prompts you to verify that you have selected the
appropriate constraint class. After you delete a constraint class, you can re-add it to the list of
constraint classes using undo or rollback.
Tip: Although it is not required, before you delete a constraint class you may want to
empty its contents by moving nets to a different class, removing any constraint class
hierarchy, and deleting design-object references to the constraint class. By default, CES
reassigns nets of a constraint class to the (All) constraint class after deletion.

Deleting Constraint Classes
To Delete a Constraint Class

From the Navigator, expand Constraint Classes, right-click a constraint class, and then click
Delete.
Alternative: Click a constraint class, and then press Delete.

Chapter 6
Rule-Area Scheme Creation and Clearance
Rule Definition
This section covers rule-area scheme creation and clearance constraint definition. Some of the
topics included are trace and via rule specification, clearance-rule set creation, and class-to-
class clearance rule assignment. This section also provides information about package type
clearance rules, general clearance rules, and how to reset clearance rules. Please refer to the
table of contents for the full listing of topics included in this section.
Creating Rule Area Schemes

You create rule area schemes to represent defined rule areas on a PCB. After you create a
scheme, you can define trace and via rules and clearance rule sets to which only nets crossing or
within that board area must adhere.
You can separate areas of a board, and then manage constraint requirements for each board area
independently from global rules. Global rules can be heavily constrained due to the
requirements of relatively small collections of critical nets that cross through concentrated
board areas.
To Create a Rule-Area Scheme

1. From the Navigator, right-click Schemes, and then click New Scheme.
2. Replace the default name “<user>_New” with a unique name for the scheme.
Rule: Spaces are allowed in rule-area scheme names.
(Minimum) Scheme Clearances and Widths

The rules within the (Minimum) scheme reflect the minimum clearances and widths defined
across all net classes within each scheme. Because these rules are generated on the fly, you
cannot change them directly. Because each rule area can have a different net class scheme, and
because each net class scheme can have a full set of widths and clearances, it may be difficult to
tell if some of the rules have been set below the minimum acceptable rules for manufacturing.
By using the minimum scheme, you can verify that you are not violating manufacturing
minimums within any of the schemes that you have created.

Rule-Area Scheme Creation and Clearance Rule Definition
Specifying Trace and Via Rules
Note
Typically, you do not assign the minimum net class scheme to a rule area on the board;
however, when you have an area that requires the absolute minimum clearances that you
defined across all other net class schemes, you can assign this scheme to a rule area in
your design.
Due to the nature of the minimum scheme, it will not always include all class-to-class clearance
rules, but instead the clearance rule with the minimum constraint value among duplicates. For
example, when you have a clearance rule between class A and class B in the Master scheme,
and an additional scheme you created defines the same relationship between class A and class
B, the minimum scheme includes the clearance rule with the lowest constraint value.

After you create a scheme to represent a rule area on a PCB, you can specify the trace and via
rules to which nets within the rule area must adhere. You can simultaneously define trace and
via rules for all board layers for nets in a net class, or you can do so individually for each board
layer.
When specifying trace and via rules, you can define values such as minimal, typical, and
expansion trace widths, typical impedance, and differential pair spacing. You can also override
these values for from-tos that must be routed on specific board layers.
Note
When you change the value for typical trace width, the field solver uses the existing
board stackup to calculate typical impedance. When you change the value for typical
impedance, the field solver is used to calculate typical width.
Common Tasks
• “Defining Via Assignments” on page 157
To Specify Trace and Via Rules

1. From the CES Spreadsheet Trace & Via Properties page, expand a scheme.
Alternative: From the Navigator, expand Schemes, expand a specific scheme, and then
click Trace & Via Properties.
2. Expand the Default physical net class, or a unique physical net class that you created
previously, and then define trace and via rules in one of the two following ways:
• To simultaneously define trace and via rules for all board layers, in the physical net
class name row (for example, Default), specify Route, Trace Width, Typical
Impedance, and Differential Spacing rules.

Example: To specify a Trace Width Minimum value of 8 th for all board layers for
nets that are a part of the Default physical net class, enter 8 in the Minimum field,
and then press Enter. CES updates each board layer to include this Minimum Trace
Width value.
• To individually define trace and via rules for each board layer, in the appropriate
board layer row (for example, SIGNAL_1), specify Route, Trace Width, Typical
Impedance, and Diff Pair Spacing rules.
Rule: When specifying layers to route, you must do so in the (Master) scheme.
When working on a net class in the Master scheme and you change a net class via to
(None), all user-defined schemes automatically change to (None) for that net class.
Example: To specify a Trace Width Expansion value of 12 th for board layers one
and two of the Default physical net class, in the SIGNAL_1 and SIGNAL_2 rows,
enter 12 in the Expansion field.
Propagating Trace Width Rules Through Layers for Hierarchical Net

Classes
When your CES constraint and object data for a design includes hierarchical net classes, you
can quickly assign unique trace width constraints to each instance of a signal or plane layer as it
appears in all child net classes. Doing so makes it easy to allow for deviations from net class
hierarchy when you need to allow for larger or smaller trace widths when traces are on a certain
board layer.

In the example illustration below, you can see that trace width constraints become more tightly
constrained at deeper levels of net class hierarchy. However, the Trace Width Minimum
constraint for layer SIGNAL_3 is even more tightly constrained through the entire net class
hierarchy. One reason for the usage you see below is for trace congestion on this layer. With a
smaller minimum value, it is easier to ensure that no traces will be routed any larger than
needed.
Figure 6-1. Example of Defining Trace Width Rule for SIGNAL_3 in all Lower
Levels of Net Class Hierarchy
To replicate this, you would simply enter “0.02” within the Parent_Class row for SIGNAL_3.
After you press Enter, CES gives you the option to apply that same value to each instance of
layer SIGNAL_3 within the lower levels of net-class hierarchy. This approach becomes even
more beneficial when you have many child-level net classes and need to quickly and accurately
define a constraint deviation without having to enter it multiple times.

Defining Via Assignments

You can assign a specific via to a net class when the default via is not suitable. When defining
via assignments, you can choose from the default, none, or any available vias. For all via
assignments other than default, the CES Spreadsheet indicates the specification with "Custom"
in the Via Assignments field.
Tip: The vias that are available for assignment are only those in your local library. To
make additional vias available, you must use Library Services in Library Manager to
export them from your Central Library to the local library.
To Define Via Assignments

1. From the CES Spreadsheet Trace & Via Properties page, expand a scheme.
2. In the Via Assignments field of the net class for which you want to define or modify a
via assignment, click .
Alternative: Click a net class spreadsheet row, and then from the Edit menu, click Via
Assignments.
3. From the Via Assignments dialog box, in the Net Class Via column, click the pulldown
to specify a different via assignment.
Tip: When defining multiple via assignments simultaneously, to set all to the default
assignment, click Set to Default.
Note: Optionally, you can use the dropdown buttons to change the Scheme and Net
Class you want to modify.
4. Repeat step 3 as needed. When you are finished, click OK or Apply.

Creating Clearance Rule Sets for Schemes
Example of Net Class Via Assignments

In the example of the Via Assignment dialog box below, two of three rows have a Net Class Via
set to other than the default via. This custom via assignment is for the (Master) scheme. The net
class “DiffPair” is a sub-class of the Default net class.
Related Topics
• “Overriding Trace Width Constraints for From-Tos” on page 187

After you create a scheme to represent a rule area on a PCB, you can specify clearance rules to
which net objects within the rule area must adhere. You can define clearance rules such as Trace
to Pad, SMD Pad to Trace, Resistor to Via, and Via to Plane. Different net classes often require
unique design rules in order to maintain signal integrity during transmission. By creating
clearance rule sets, you can address these requirements. Because CES handles conflicts between
rule set constraints, when one does occur, the larger clearance value is used.
You can also define z-axis clearance rules like Trace to Trace and SMD Pad to Trace. Unlike
standard clearance rules, which control spacing between design objects on the same signal
layer, z-axis clearance rules control spacing between design objects on different signal layers.
Z-axis clearance rules are especially important for high-speed designs where net density is very
tight.

Note
The (Default Rule) and (Default Z-Axis Rule) clearance rule sets contain the default
clearances for a design. When assigning clearance rule sets between net classes, the
values in (Default Rule) are used by default; however, (Default Z-Axis Rule) values are
not used by default. You must explicitly assign them, or the rules of a different z-axis
clearance rule set, between net classes.
It is important to note that z-axis clearance rules are absolutes based on just clearance. No
exceptions are made as a result of layer-direction bias. For example, when dielectric thickness is
smaller than a z-axis clearance constraint, no applicable trace is allowed to run over or under
another trace. This is still the case if the traces cross at right angles. Currently, z-axis clearances
are not applied between segments of the same net.
Common Tasks
• “Defining Embedded Resistor Clearance Rules” on page 163
• “Defining SMD Clearance Rules” on page 165
To Create a Clearance Rule Set

1. From the Navigator, expand Schemes, right-click a specific scheme, and then click New
Clearance Rule.
Alternative: From the CES Spreadsheet Clearances page, right-click a scheme, and
then click New Clearance Rule.
2. Replace the default name “<user>_New” with a unique name for the clearance rule set.
Spaces are allowed in clearance rule set names.
Result: You can now edit the values of any scheme except for the (Minimum) scheme.
The (Minimum) scheme contains non-editable clearance rules that are the minimum
values across all schemes.
To Define Clearance Rules for a Rule Set

1. From the CES Spreadsheet Clearances page, expand the (Master) scheme, or a
previously defined scheme.
2. Expand the clearance rule set for which you want to define clearance rules, and then
make your definitions in one of two ways:
• To simultaneously define clearance rules for all board layers, in the clearance rule
set name row (for example, (Default Rule)), specify any appropriate clearance rules.
Example: When your distance unit is thousandths, to specify a Trace To Trace
separation of 15 for all board layers, in the (Default Rule) row, enter 15 into the

Trace field of the Trace To heading, and then press Enter. CES updates each board
layer to include this Trace to Trace value.
• To individually define clearance rules for each board layer, in the appropriate board
layer row (for example, PHYSICAL_2), specify any appropriate clearance rules.
Example: To specify a Trace To Trace separation of 12 for board layer two, in that
row, enter 12 in the Trace field of the Trace To heading.

Note
Clearance rules are not applied to your design until you create associations between
specific net classes. To do so, please refer to “Assigning Class-To-Class Clearance
Rules” on page 165.
To Create a Z-Axis Clearance Rule Set

1. From the CES Spreadsheet Z-Axis Clearances page, right-click an existing z-axis
clearance rule set, and then click New.
2. Replace the default name “<user>_New” with a unique name for the clearance rule set.
Spaces are allowed in z-axis clearance rule set names.
To Define Z-Axis Clearance Rules for a Rule Set

From the CES Spreadsheet Z-Axis Clearances page, expand the clearance rule set for which
you want to define clearance rules, and then make your definitions in one of two ways:
• To simultaneously define clearance rules for all board layers, in the clearance rule set
name row, specify any appropriate clearance rules. Please refer to the following
example.
• To individually define clearance rules for each board layer, in the appropriate board
layer row, specify any appropriate clearance rules. Please refer to the following
example.
Note
Z-axis clearance rules are not applied to your design until you create associations
between specific net classes. To do so, please refer to “Assigning Z-Axis Class-To-Class
Clearance Rules” on page 168.

Example of Defining Differential Pair Spacing Between Channels and Ports

In this example, you have two ports, each of which consist of four differential pairs (eight
channels). You want to define unique constraint values to control spacing between differential
pairs (a), spacing between differential-pair traces (b), and spacing between traces of each port
(c). The following illustration depicts these spacing requirements.
Figure 6-2. Three Trace-Spacing Requirements
To Define These Spacing Requirements

1. From the CES Spreadsheet Nets page, define Differential Spacing as (a) in each
constraint class that includes one of these differential pairs.
2. Create separate net classes for each port, and then assign each set of respective
differential pairs into these new net classes (for example, Port_1 and Port_2).
3. Create two clearances rule sets. One for nets within a port (b), and another for nets
between ports (c).
4. From the CES Spreadsheet Clearances page, perform the following tasks:
• For the nets within a port clearance rule set (for example, Within_Port), define Trace
to Trace as (b).
• For the nets between ports clearance rule set (for example, Across_Ports), define
Trace to Trace as (c).
5. Assign the following class-to-class clearances rules:
• Within_Port between net class Port_1 and net class Port_1.
• Within_Port between net class Port_2 and net class Port_2.

• Across_Ports between net class Port_1 and net class Port_2.
Defining Embedded Resistor Clearance Rules

When your design includes embedded resistive components like thick-film and thin-film
resistors, you can define spacing requirements between these parts and conductive board
elements (for example, traces, pads, vias), and other resistors. Embedded resistors are typically
located on internal board layers but can also be placed on external board layers.
The difference between thick-film resistors and thin-film resistors is the production process
used to create each type of resistor. Thin-film resistors are typically “subtractive” because they
are created through an etching process. Thick-film resistors are typically “additive” because
they are instead printed on metal electrodes.
In the following illustration, each internal board layer has one embedded resistor. There are not
any embedded resistors on external board layers in this example. This illustration does not
depict a difference between the types of embedded resistors included below.
Figure 6-3. Embedded Resistors on Each Internal Board Layer
The clearance area that you define with each Resistor to <object> and EP Mask to <object>
constraint is depicted in the illustration below. As you can see, thick-film resistor clearance is
based on protective-mask/overglaze adjacency. Clearance of thin-film resistors is based on
production-mask adjacency.

Figure 6-4. Embedded Resistor Clearances Defined by These Constraints
Unlike embedded resistors, you do not need to define unique clearance rules for embedded
capacitive components. Standard pad clearance constraints (for example, Trace to Pad, Pad to
Pad, and Pad to Plane) handle their clearance requirements. Examples of embedded capacitive
components are mezzanine, screen-printed, and interdigitated capacitors.
To Define Thick-Film Resistor Clearance Rules

From the CES Spreadsheet Clearances page, define the following constraints for an entire
clearance rule set, or individually for each board layer of a rule set:
• “Embedded Resistor To Trace” on page 317

• “Embedded Resistor To Pad” on page 318
• “Embedded Resistor To Via” on page 319
• “Embedded Resistor To Resistor” on page 320
To Define Thin-Film Resistor Clearance Rules


Assigning Class-To-Class Clearance Rules
• “EP Mask To Trace” on page 321

• “EP Mask To Pad” on page 322
• “EP Mask To Via” on page 323
• “EP Mask To Resistor” on page 324
Note
“Mask” refers to the production mask of a thin-film resistor. It does not mean solder
mask.
Defining SMD Clearance Rules

When your design includes surface mount devices (SMD), you can define spacing requirements
between the pads of these devices and conductive board elements (for example, traces and vias).
SMDs are also commonly referred to as surface mount technologies (SMT).
To Define SMD Clearance Rules

• “Trace To SMD Pad” on page 309

• “Via To SMD Pad” on page 315
To Define Z-Axis SMD Clearance Rules

From the CES Spreadsheet Z-Axis Clearances page, define the following constraints for an
entire clearance rule set, or individually for each board layer of a rule set:
• “Trace To SMD Pad” on page 331

After you create clearance rule sets for a rule-area scheme, you can assign class-to-class
clearance rules that maintain special clearances between specific net classes. To define
additional net classes, please refer to “Creating Net Classes” on page 139. By doing so, you can
apply the rules you previously defined in a clearance rule set to one or more pairs of physical net
classes to maintain adjacency relationships between nets. When selecting net classes to
associate with a clearance rule, you can quickly specify all net classes by using the (All) row.
Note
Class-to-class clearance rules are obeyed between the top-level net classes to which they
are assigned. Any sub-level net classes in the top-level classes will not obey these rules.

To Assign a Class-To-Class Clearance Rule

1. With the CES Spreadsheet Clearances page active, from the Clearances toolbar, click
; or, from the Edit menu, click Clearances, and then click Class to Class Clearance
Rule.
2. From the Class to Class Clearances dialog box, In the Net Class to Class Clearance
Rules for Scheme pulldown, select a scheme.
3. In the grid display under Source Net Class(es), click within an editable cell to select the
rule to use between two specific net classes.
Tip: To simultaneously assign the same rule to multiple cells, use Ctrl-click and Shift-
click to select a group of cells. After you have selected the last cell, you must continue
holding Ctrl or Shift while you make the rule selection.
4. Continue making rule assignments between net classes.
5. When you want to assign class-to-class clearance rules for a different scheme, return to
step 2.
Rule: Those that you do not explicitly define (i.e. empty cells) use (Default Rule)
although the cells appear as empty. This assignment in the matrix is hardcoded into the
top-left cell.
Example of Clearance Rule Assignments

In the following example, there are four net classes (10th, 20th, 30th, and 40th), and the
(Default) net class. There are also four clearance rules of the same name. Each of the clearance

rules defines all clearance constraints to the same value as the name of the clearance rule set.
The clearance constraints defined for (Default Rule) are all set to 5 th.
The common names for net classes and clearance rule sets is only for the illustrative purposes of
this example, but you may find it useful to group nets into classes based on this style of naming.
Here is a listing of all clearance rule assignments based on the above dialog box example:
• (Default Rule) is the hardcoded assignment between all net classes, (All) and (All). If all
other cells in this picture where empty, (Default) would be the only rule assigned
between every possible pairing of net classes. The middle callout in the above picture is
an example of this. If it is blank, it uses (Default Rule).
• The clearance rule 10th is assigned between the net class 10th and all other net classes.
• The clearance rule 10th is assigned between the net class 20th and itself. This means that
nets within this class can use smaller clearances (based on the definitions in the rule set).

Assigning Z-Axis Class-To-Class Clearance Rules
To Delete a Class-To-Class Clearance Rule

.
2. From the Class to Class Clearances dialog box, In the Net Class to Class Clearance
Rules for Scheme pulldown, select a scheme.
3. Click the row of an existing class-to-class clearance rule assignment, and then click the
blank selection.
4. After you finish deleting assignments, click OK.
Related Topics
• “Creating Clearance Rule Sets for Schemes” on page 158
Assigning Z-Axis Class-To-Class Clearance

Rules
After you create z-axis clearance rule sets, you use the same spreadsheet page to assign class-to-
class clearance rules that maintain unique clearances between specific net classes. By doing so,
you can apply the rules you previously defined in a z-axis clearance rule set to one or more pairs
of physical net classes to control adjacency relationships between nets. When selecting net
classes to associate with a clearance rule, you can quickly specify all net classes by using the
(All) row. To define additional net classes, please refer to “Creating Net Classes” on page 139.
Note
When you update your PCB board stackup after already having defined z-axis clearances
in CES, the clearance rules will become invalid. You must re-enter them and assign them
again.
When assigning these clearance rules between net classes, you can only create relationships for
the (Master) scheme; however, they are used for all rule areas (rule-area schemes). For example,
when your design includes ten user-created rule-area schemes, assigning a z-axis clearance rule
set between net class A and net class B results in those ten schemes and the (Master) scheme
using the assignment.
The following illustration shows z-axis trace to trace relationships for two net classes. Because
the net classes contain mostly high-speed nets, that by nature are driving fast edge rates, it is
important to specify adjacent layer clearances between their net objects.

Assigning Z-Axis Class-To-Class Clearance Rules
Figure 6-5. Example Z-Axis Trace to Trace Minimums
Depending on the number of adjacent layers that separate two design objects, z-axis clearance
rules may not be necessary. For this purpose, you can disable these rules when the number of
layers between design objects exceeds a certain amount. For example, after applying a z-axis
clearance rule set named “Fast_Clocks” to net class A and net class B, you specify that the
maximum depth is 5 layers. As a result, Trace to Trace distances between nets in class A and B
will not be obeyed when validating z-axis distances between layers one and seven, two and
nine, and so on.
Note
Class-to-class clearance rules are obeyed between the top-level net classes to which they
are assigned. Any sub-level net classes in the top-level classes will not obey these rules.
To Assign a Z-Axis Class-To-Class Clearance Rule

1. With the CES Spreadsheet Z-Axis Clearances page active, from the Clearances toolbar,
click ; or, from the Edit menu, click Clearances, and then click Z-Axis Class to
Class Clearance Rule.
2. In the grid display under Source Net Class(es), click within an editable cell to select the
rule to use between two specific net classes.
Tip: To simultaneously assign the same rule to multiple cells, use Ctrl-click and Shift-
click to select a group of cells. After you have selected the last cell, you must continue
holding Ctrl or Shift while you make the rule selection.
3. Optionally, to specify a maximum layer depth between design objects, in the cell you
just edited, click . From the Setup Z-Axis Clearance dialog box, click the Max layer
depth dropdown, select a maximum value, and then click OK.
To specify a maximum layer depth that includes all layers, from the Max layer depth
dropdown, select 0. It is important to understand, though, that because of the shielding
effects of plane layers, as soon as a plane layer is encountered, all layers after the plane
layer are ignored. For example, when you define a rule for layer one of an eight layer
board and set the depth to 0, a plane layer that exists as layer four would cause the rule to
apply between just layers one and two, and layers one and three.

Assigning Package Clearance Type Rules
Example: When specifying a maximum layer depth of 3, nets within classes governed
by the clearance rule are not required to obey it unless they are separated by no more
than three board layers.
4. Continue making rule assignments between net classes.
Rule: Those that you do not explicitly define (empty cells) do not use (Default Z-Axis
Rule).
To Delete a Z-Axis Class-To-Class Clearance Rule

1. With the CES Spreadsheet Z-Axis Clearances page active, from the Clearances toolbar,
click .
2. Click the row of an existing class-to-class clearance rule assignment, and then click the
empty selection, which is the first in the list.
3. After you finish reverting assignments, click OK.

You can assign clearance rules to each package type to specify the required amount of clearance
distance between a package type and all other design components that come close to it on a
board layer. Each package type clearance rule you define can be followed for the top of the
board, its bottom, or both the top and bottom sides. This gives you the ability to create more
spacing or less spacing between components depending on the assembly technique used when
placing components on the board, the soldering techniques used, or both. For example, you can
define a package type clearance rule for integrated circuit flip chips that requires a bottom-side
clearance of 200 th between this component type and all other design objects.
Note
When using Expedition PCB as part of your design flow, unique package types you
create in the Cell Editor of that PCB layout tool will show up in CES as part of the drop-
down list of selectable package types. To create a unique package type in Expedition
PCB, you must use the Clearance Type field of the Cell Editor. For more information,
please refer to the documentation for Expedition PCB.
In addition to defining package clearance type rules, you can also define package-type-to-
package-type rules. These rules give you the ability to specify directional component clearances
between specific package types for packages on the top, bottom or both layers.
Other Common Tasks

• “Determining Package Sides and Ends” on page 173

To Assign Package Clearance Type Rules

; or, from the Edit menu, click Clearances, and then click Assign Package Type
Clearances.
2. From the Package Clearance Type Rules dialog box, to the right of Package type
clearance override rules, click to create a new rule.
3. In the Package Clearance Type cell, click .
4. From the Select Package Type dialog box, select a package type (for example, IC -
BGA), and then click OK.
5. In the Side cell, click to specify board layer side of top, bottom, or both sides.
6. In the Clearance cell, specify the required clearance distance for this package type.
Rule: This clearance defines the required distance between this package type and all
other design objects.
To Assign Package-Type-to-Package-Type Rules

.
2. If you have not done so already, create two package clearance type rules to associate
before you continue to step 3.
3. From the Package Clearance Type Rules dialog box, next to Package type to package
type clearance override rules, click to create a new rule.
4. In the Pkg Clr Type cell of the new row, click to select the first Package clearance type
override rule you created.
5. In the second Pkg Clr Type cell, click to select the second Package clearance type
override rule you created.
6. In the Side, Direction, and Clearance cells, specify the side, direction, and clearance
distance between package types, and then click OK.
Note: The direction types “Side to End” and “End to Side” are unique and therefore
must be defined separately. Here are definitions for each direction you can choose:
• All – Top, bottom, left, and right sides of one component type to the top, bottom,
left, and right sides of another component type.
• Side to Side – Left and right sides of one component type to the left and right sides
of another component type.
• End to End – Top and bottom ends of one component type to the top and bottom
ends of another component type.

• Side to End – Left and right sides of one component type to the top and bottom ends
• End to Side – Top and bottom ends of one component type to the left and right sides
To Delete a Package Clearance Type Rule

.
2. From the Package Clearance Type Rules dialog box, under Package type clearance
override rules, click a row, and then click .
Tip: To select multiple rules, use Ctrl-click.
To Delete a Package-Type-to-Package-Type Rule

.
2. From the Package Clearance Type Rules dialog box, under Package type to package
type clearance override rules, click a row, and then click .
Tip: To select multiple package type to package type clearance rules, use Ctrl-click.
Example of Assigning a Package-Type-to-Package-Type Rule for Both

Layer Sides and All Directions
In this example, you want to assign a package-type-to-package-type rule between Discrete -
Chip components and IC - Flip Chip parts. Each of these package types already has a package
clearance type rule that requires a clearance distance of 50 th between instances of these
components and all other board objects. However, when these components are in the same
vicinity of a board layer, you require a clearance distance of 500 th between them, and for all
directions.
To Assign a Package-Type-to-Package-Type Rule Between These

Components
.
2. From the Package Clearance Type Rules dialog box, next to Package type to package
type clearance override rules, click .
3. In the first Pkg Clr Type cell of the new row, select Discrete - Chip.
4. In the second Pkg Clr Type cell, select IC - Flip Chip.
5. In the Side cell, select Both, and then in the Direction cell, select All.

6. In the Clearance cell, enter 500. After you finish, the bottom portion of the Package
Clearance Type Rule dialog box should look like the following illustration.
Figure 6-6. Discrete - Chip to IC - Flip Chip Clearance Rule
Determining Package Sides and Ends

In order to define the appropriate directional clearance rules between packages, you need to
know which parallel “sides” of a package are defined in your layout system as the sides, and
which are defined as the ends.
The illustration below depicts the difference between side-to-side, end-to-end, side-to-end, and
end-to-side clearances between directional package type clearance rules based on the package
orientation within Cell Editor.
Figure 6-7. Package-Type-to-Package-Type Directional Clearances
How a package cell is oriented in Cell Editor controls what the sides and ends are. The sides are
always on the left and right, and the ends are always top and bottom. Therefore, if you change
the orientation of a cell, the definition changes accordingly. In the illustration above, the long
sides are left and right (sides), and the short sides are top and bottom (ends). In the illustration
below from Cell Editor, the orientation on the right would correspond to the directional
clearances above.

Specifying General Clearance Rules
Figure 6-8. Cell Editor Showing Different Orientations for the Same Package
Cell
You might be wondering why side-to-end and end-to-side are not the same. Although you can
define them as if they are, having the ability to define clearances based on “which side” and
“which end” give you greater flexibility. For example when the end of an IC-BGA is next to the
side of an IC-SIC, you might want more clearance than when the side of an IC-BGA is next to
the end of an IC-SIC. Commonly, a distinction like this is used to provide a greater or lesser
amount of room depending on adjacency of component pins. Some components have the same
number of pins on sides and ends, while others have pins on just sides or ends. How you define
these clearances can vary greatly based on the unique footprint of each component, and the
clearance relationships you want to create between them.
When defining end-to-side and side-to-end rules, it is important not to define redundant rules.
For each pairing of package types, they only need a single end-to-side rule and one side-to-end
rule for the purpose of defining all clearance requirements. For two example packages A and B,
you would define just one of each set of the following rules, but not both:
• End A to side B, side A to end B

• Side B to end A, end B to side A
Note
When you assign a package-type-to-package-type rule, the package top and bottom
clearances you defined in each package clearance type rule are overridden by the
clearances defined in the package adjacency rule.

You can specify general clearance rules to define clearance values between design objects that
you do not specify through the CES Spreadsheet Clearances page. Unlike spreadsheet clearance

constraints, general clearance rules are specified irrespective of net class relationships. For
example, the minimum distance between testpoint centers is a general clearance rule that is set
globally and not defined by relationships between net classes. For a complete listing of general
clearance rules, please refer to the table below.
To Specify General Net Class Clearance Rules

; or, from the Edit menu, click Clearances, and then click General Clearances.
2. From the General Clearance Rules dialog box, modify the rules that have an editable
value. Editable rule values are set against a white background. Please refer to the table
below for explanations of each general clearance rule.
3. After you finish modifying general clearance rule values, click OK.
Table 6-1. General Clearance Rules

Rule Purpose
Cavity Inside Edge to Parts Defines the minimum acceptable distance between the
inside edge of a cavity and all parts.
Cavity Outside Edge to Defines the smallest acceptable distance between the
Non-Plane Conductor outside edge of a cavity and all non-plane conductors.
Cavity Outside Edge to Defines the minimum acceptable distance between the
Plane Conductor outside edge of a cavity and all plane conductors.
Cavity Edge to Cavity Edge Defines the smallest acceptable distance between a cavity
edge and all other cavity edges.
Contour, Cavity & Defines the minimum acceptable distance between a
Mounting Hole to Mounting mounting hole (including contour and cavity) and all other
Hole mounting holes.
Contour & Mounting Hole Defines the smallest acceptable distance between a
to Non-Plane Conductor mounting hole and all non-plane conductors.
Contour & Mounting Hole Defines the minimum acceptable distance between a
to Plane Conductor mounting hole (including contour) and all plane
conductors.
Placement Outline to Defines the smallest acceptable distance between a
Placement Outline placement outline and all other placement outlines.
Placement Outline to Defines the minimum acceptable distance between a
Placement Obstruct placement outline and all placement obstructs.
Placement Outline to Board Defines the smallest acceptable distance between a
Edge placement outline and all board edges.
Trace to Resistor Defines the minimum acceptable distance between a trace
segment and all resistors.

Copying, Renaming, and Deleting Rule-Area Schemes
Table 6-1. General Clearance Rules

Rule Purpose
Pad to Resistor Defines the smallest acceptable distance between a pad
and all resistors.
Testpoint Center to Defines the minimum acceptable distance between the
Testpoint Center center of a testpoint and all other testpoint centers.
Copying, Renaming, and Deleting Rule-Area

Schemes
You can copy, rename, and delete rule-area schemes. For example, by copying a rule-area
scheme for which you have defined trace and via rules and clearance rule sets, you can rename
the copy, and then make modifications to that rule-area scheme to reuse the majority of its
constraint definitions on another area of the board.
As you make changes to your schemes, you can also undo or rollback those changes to return
one or more schemes to a previous design state. For example, after deleting a specific rule-area
scheme, you can quickly re-add it without having to manually recreate it.
In addition to copying top-level schemes, you can copy specific clearance rule sets contained
within a scheme. This is useful when you want to duplicate only a subset of scheme, instead of
an entire PCB rule area.
Caution
When you rename a scheme, all rule areas within that scheme are automatically reset to
those in the (Master) scheme. You must go into the PCB system and reset the rule areas to
use the new scheme created as a result of renaming the scheme.
To Copy a Rule-Area Scheme

1. From the Navigator, expand Schemes.
Alternative: Locate a scheme using the CES Spreadsheet Trace & Via Properties page
or Clearances page.
2. Right-click a scheme name, and then click Clone.
Result: The scheme is copied and given the following default name:
“<user>_<scheme>_clone”
3. Rename the copy by hovering over it and then clicking once.
4. Modify the name of the scheme, and then press Enter.

Resetting Clearance Rules to the Master Scheme
To Rename a Rule-Area Scheme

2. Right-click a scheme name, and then click Rename.
Alternative: You can also modify the name of a scheme by clicking it once, and then
waiting for it to become editable.
3. Modify the name of the scheme, and then press Enter.
To Delete a Rule-Area Scheme

2. Right-click a scheme name, and then click Delete.
Rule: You cannot delete the (Master) and (Minimum) schemes.

For rule-area schemes that you created, you can reset trace and via properties and clearances to
match the (Master) scheme. The (Master) scheme, which is also known as the default rule set,
typically represents the majority of the clearance and width values for a board. These values are
used by default for board areas that do not have user-created schemes and rule areas assigned to
them.
Resetting all or a subset of the constraints stored in a scheme to the (Master) scheme is most
useful when you are sure that further modifications to a user-created scheme will not result in
appropriate constraint values. Starting over with the default rule set gives you the ability to
“start fresh” by modifying values of a user-created scheme with the default rules as the starting
point.
To Reset Clearance Rules to the (Master) Scheme

1. From the Navigator, expand Schemes, right-click a scheme, and then click Reset to
(Master).
2. Verify that the Area Scheme field lists the appropriate scheme.
3. By default, all constraint types are preselected. Click to de-select constraint types that
you do not want to reset to the (Master) scheme, and then click OK.

Example: To exclude resetting Minimum Widths and Typical Widths, click to de-select
these sets of constraint values.
Example of Resetting Class-To-Class Clearances and Expansion Widths to

Those of the (Master) Scheme
In this example, you want to reset just the class-to-class clearance rules and expansion widths of
user-created scheme “SchemeA” to those of the (Master) scheme.
To Reset This Subset of Constraints

1. From the Navigator, expand Schemes, right-click SchemeA, and then click Reset to
(Master).
2. From the Reset to (Master) dialog box, click Unselect all, and then click to select the
following constraint types:
• Class to Class clearances
• Expansion Widths
3. Verify that the Area Scheme field lists the scheme that you want to reset to the constraint
values of the master scheme, and then click OK.

Chapter 7
Net Constraint Definition
This section covers net constraint definition. Some of the topics included are specification of
general constraints, topologies, and delay rules. This section also provides information about
definition of formulas, overshoot and ringback constraints, and I/O Designer FPGA constraints.
Please refer to the table of contents for the full listing of topics included in this section.
Specifying General Net Constraints

You can use CES to specify general net properties such as topology type and the maximum
number of vias that can be applied to a net. You can specify general net properties individually
for each net, or simultaneously by assigning a property value to a constraint class. When
specifying a single property value for multiple nets through a constraint class assignment, each
net in the constraint class is updated to include the single property value.
Tip: To view all constraints instead of those that are of a specific type (for example, net
properties, delays and lengths, or overshoot/ringback), from the Group pulldown, select
All.
To Specify General Properties for Nets

1. With the CES Spreadsheet Nets page active, from the Group pulldown, click Net
Properties.
Note: These constraints are also displayed as part of the All group, but you may find
it easier to work with general net constraints when the CES Spreadsheet Nets page
displays only them.
2. You can specify these properties in one of two ways:
• To simultaneously define a property for all nets in a constraint class, in the constraint
class name row, enter a value into a property field (for example, # Vias Max), and
then press Enter.
Result: Each net in the constraint class is updated with this value.
• To individually define a property of a specific net, in the net row, enter a value into a
property field.

Specifying Topologies for Nets and Constraint Classes
Specifying Topologies for Nets and Constraint

Classes
You can assign pre-defined and custom topology types to specific nets and constraint classes.
When you assign a topology type to a constraint class, all nets within the class take on the
topology type designation. The available pre-defined topology types are MST , Chained ,
TShape , Star , and HTree . When a pre-defined topology type is not appropriate for a
specific net, you can manually define netline ordering.
When you assign a topology type to a net or constraint class, or manually create a unique
topology ordering, you are defining the order in which the router etches transmission lines and
other physical mechanisms that aid in the propagation of electrical signals. CES provides router
instruction in the form of from-tos, each of which is composed of two design or component pins
that respectively designate the router to etch from one pin to another pin.
Note
MST topology type disregards the Stub Length Max constraint. You do not need to define
this constraint when the topology type is MST (Minimum Spanning Tree).
Other Common Tasks

• “Creating Pin Sets to Construct Advanced Topologies” on page 184
The Difference Between From-Tos and Pin Pairs

Often times, from-to relationships can be confused with pin pair designations. To better
understand these separate design attributes, please refer to the following definitions:
• Net line ordering/from-tos – Ordered, physical pairings of component pins that instruct
the router where to etch from and to when creating physical transmission lines (traces).
• Pin pairs – Electrical pairings of component pins that are created for the purpose of
defining electrical relationships between component pins in the form of constraints.
Handling Multiple Loads

When there are at least two loads, a virtual pin is created to join all of the sources. The loads are
then balanced from the joining virtual pin. This procedure is followed for TShape, Star, and
HTree topology types.

Differential-Pair Topology Definition

When specifying topologies for differential pairs, both nets that make up the pairing ultimately
take on the same topology definition. This is whether you define topology type for one net in the
pair, or at the differential-pair level. After you make your selection, it is automatically applied at
each level.
Note
Differential pairs are typically used for high-speed signals, so you will want to order and
constrain them as such. The layout system will not order a net that has been defined as
MST or Chained, and can route these types of topologies anyway it needs to complete the
route. For this reason, MST and Chained are not selectable for differential pairs. The only
valid topology types are the remaining ones that force the layout system to order the
route. This is a layout limitation that CES enforces.
When you manually define netline ordering, both nets result with the same ordering definition.
Whether in whole or as a starting point, it depends on net similarity:
• In the case of symmetrical nets, after you manually define netline ordering for one net, it
is automatically applied to the other net.
• When you have a differential pair that is comprised of asymmetrical nets, you would
first manually define netline ordering for the net with the most pins. After you complete
that process, the ordering is stored as a temporary constraint template, and you are
presented with the Constraint Template Matching dialog box. Through it you can
modify the ordering as needed for the other net that makes up the differential pair.
CES applies this approach with the goal of making the netline ordering process as efficient as
possible. Due to the relative, common characteristics of nets used to create most differential
pairs, a strategy that leverages re-use of manual netline ordering is a natural solution.
To Specify Topology Type for a Net or Constraint Class

1. With the CES Spreadsheet Nets page active, from the Group pulldown, click Net
Properties.
Warning: When you change a topology type from Custom or Complex to a pre-defined
topology type, all pin pairs, from-tos, and virtual pins are deleted. When changing
between Custom and Complex topology types, you have the option of preserving pin
pairs.
it easier to work with topology constraints when the CES Spreadsheet Nets page
displays only them.

2. In the spreadsheet row of the net or constraint class to which you want to assign a
topology type, click the Topology Type field, and then select a pre-defined topology
type (MST, Chained, TShape, HTree, or Star), Custom, or Complex.
Alternative: From the Topology toolbar, click a topology type button to specify a pre-
defined topology type ( , , , , or ), or a custom topology ( ).
Tip: To simultaneously specify a pre-defined topology type for multiple nets, use Ctrl-
click, and then from the Topology toolbar, click a topology type button.
Rule: After you choose Custom or Complex, the next step is to perform netline ordering
to define the custom topology type. When you include pin sets as part of a Custom
topology, it is automatically changed to Complex to indicate the usage of pin sets.
To Manually Define Netline Ordering (From-Tos) for a Specific Net

1. From the CES Spreadsheet Nets page, click the row of the net for which you want to
manually define netline ordering, and then from the Topology toolbar, click .
Alternative: After you click a net row, from the Edit menu, click Netline Order.
Rule: Before you can define netline ordering for a net, you must set the topology type
constraint to Custom or Complex.
2. From the list of available pins, click a row to select the From pin.
Pin sets: When defining from-tos between pin sets, select pin sets instead of pins in both
the From and To fields. Also, you can select both types of objects.
3. From the list of available pins, click a row to select the To pin.
4. Verify the From pin and To pin fields, and then click .
Note: When the From pin and To pin fields do not contain the correct pins, click to
clear the designation.
Note
As you create from-tos, you may find that not enough source (S) pins or load (L) pins
exist, and you cannot create a valid topology. When this occurs, you must exit the dialog
box and switch to the CES Spreadsheet Parts page. From there, you can change the
Topology Pin Type constraint of one or more relevant component pins, and then start this
procedure over again.
5. Repeat steps 2 through 4 for each from-to you want to create. After you finish, click
OK.

Tip: To automatically create pin pairs from each from-to, enable the Automatically
create pin pairs from from-tos checkbox. In the following example, five pin pairs were
created, each matching a from-to.
To Delete a Manually Defined Netline Order From-To

From the list of defined netline order from-tos, click a row, and then click .
Tip: To delete all defined netline order from-tos, click .
Changing Topology Type

Whenever you change the Topology Type constraint for a net or constraint class, any pin pairs,
fromtos, and virtual pins defined for the net, or individual nets in the constraint class, can be
lost. However, in the case of switching from Custom to Complex (or vice-versa), you can
preserve pin pairs that are not associated with virtual pins.
Changing topology type is not a concern when a net does not have unique definitions associated
with the topology type. In many cases, changing topology type is a simple action of just going
from one topology type to another.
In the event that changing the topology type will result with losses like those listed above, CES
notifies you of this fact, and gives you the ability to choose which Topology Type values to
change to the new value, and which to keep with their current value, therefore preserving the
additional definitions that are part of the present topology type. The procedure below explains
the options you have in this case.

Prerequisites
• None.
Procedure
1. In the event that changing topology type will result with losses, the Net Topology
Change dialog box is presented. From it, select one of the following options, and then
click OK:
• Prompt before changing the topology for each net – Prompt individually for each net
to specify whether to keep the current topology type or change to the new one. As a
result, a Yes/No dialog box will appear for each affected net.
• Change the topology type for all nets without prompting – Change the topology type
for all affected nets.
• Disregard the topology change for all nets without prompting – Cancel out of the
change, preserving the existing topology type for all affected nets.
Optional: When changing from Custom to Complex, or Complex to Custom, you can
preserve pin pairs. To do so, activate the following checkbox: Preserve pin pairs not
associated with virtual pins.
Results
The existing Topology Type value is changed or preserved for one or more nets depending on
your choices.
Related Topics
“To Specify Topology Type for a Net or “Topology Type” on page 340
Constraint Class” on page 181
Creating Pin Sets to Construct Advanced Topologies

When a net contains a large number of pins, sometimes the best approach to constructing an
advanced topology is to group pins into subsets called pin sets. For example, a 16-pin net that
requires characteristics of both T-shape and chained topology types is a good candidate for pin
sets. This would result in three pin sets, consisting of two 3-pin T-shape topologies and one 10-
pin chained topology. After you create pin sets, you can define from-to relationships between
pin sets, and pin sets and pins. You can also create higher-level pin sets by grouping existing pin
sets into new pin sets.
To Create a Pin Set

1. From the CES Spreadsheet Nets page, click the row of the net for which you want to
create a pin set, and then from the Topology toolbar, click .

2. From the Netline Order dialog box, click one of the following topology types:
• – T-shape, which automatically balances load branches, though the trunk branch
may not match. T-shape is used exclusively for constructs that include three objects
(pins or pin sets).
• – Chained, which chains all selected pins between the first and last pins you
select. No virtual pins are created for this type of pin set.
• – Minimum spanning tree, which connects selected pins in the best way possible
based on physical location. No virtual pins are created for this type of pin set.
• – Balanced, which requires the distance between the virtual pin and all pins in the
pin set to be equal.
• – Unbalanced, which performs no automatic balancing. This is especially useful
when you want to specify unequal constraints on branches of the pin set.
3. From the available pins / pin sets listing, click each pin that should comprise the pin set;
then click Finish.
Rule: When defining a T-shape pin set, you can select no more than three pins. For
chained pin sets, make sure that you click the start pin first and the end pin last.
Result: The pin set is added to the listing of Available pins / pin sets. The Pin/Set and
Type columns indicate that a row is a pin set by including the topology type in their text
(for example, CH 1 or Chained). Also, the Set Contents column includes a button.
To Change the Order of Pin-Set Pins

1. From the Netline Order dialog box, in the row of a pin set, click .
2. From the Pin Set Order dialog box, click a pin to move, and then click or .
3. Repeat step 2 for each pin for which you want to change its order; then click Apply.
To Delete Pin Sets

From the Netline Order dialog box, you can do this in one of the following ways:
• Click the row of an individual pin set, and then click .

• To delete all pin sets, click .
Example of a Complex Net Topology

In the following example, a complex net topology is constructed for a net that has nine pins.
This net topology is considered complex because it uses both pin sets and from-tos. This
complex net topology includes a T-shaped pin set, a chained pin set, and an MST pin set. It
connects each of the three pin sets, all of which include just three pins, with two from-tos.

First, here is a visual of the complex net topology that we are going to create. It is important to
note that the standard pins are shown as blue. The virtual pins created for the T-shaped pin set
are shown as green to distinguish them from the preexisting, or standard pins.
Figure 7-1. Visual of Complex Net Topology
Next, here is what the Netline Ordering dialog box would look like for the purpose of defining
this complex net topology. The steps you would use to create it are listed after the picture of the
dialog box.

Figure 7-2. Netline Ordering of a Complex Net Topology
To create the above netline ordering, or one that is similar, you would have to use the following
steps:
1. Create a T-shaped pin set (T_1) using pins R3-2, RT1-2, and U1-14.
2. Create a chained pin set (CH_1) using pins U2-14, U3-14, and U4-20.
3. Create an MST pin set (MST_1) using pins U5-14, U6-1, and U7-8.
4. Connect pin sets T_1 and CH_1 by creating a from-to between pins RT1-2 and U2-14.
5. Connect pin sets T_1 and MST_1 by creating a from-to between pins U1-14 and U5-14.
Overriding Trace Width Constraints for From-Tos

You can optionally override the trace width constraints (for example, Trace Width Typical or
Trace Width Minimum) defined for the net as part of its trace and via rules. Doing so gives you
the ability to specify trace width on a pin-to-pin basis, in effect, overriding the net class trace
width for certain pin pairs.

Defining Pin Pairs for Nets
Prerequisites
• The net's Topology Type must be Custom.
• The net must have gone through netline ordering.
• The net can not be part of a differential pair.
• Filters > Levels > FromTo must be enabled in order to view CES Spreadsheet rows for
from-tos.
To Override Trace Width Constraints for a Specific From-To

1. From the CES Spreadsheet Nets page, in the From To Constraints Layer cell, ensure that
the appropriate board layer has been selected.
2. In the From To Constraints Trace Width cell, enter the override value.
Result: Based on the trace width override you entered, the From To Constraints Z0
constraint is updated to display the calculated impedance.

You can define pin pairs for nets manually, semi-automatically, and automatically. When
automating the pin pair definition process for one or more nets, you should verify the accuracy
of the pin pair definitions that CES produces. When a specific pin pair definition is not
appropriate, you can manually define that pin pair.
You use pin pairs to define constraints for specific nets that result from the linking of two pins.
Although pin pairing can be thought of as a physical coupling, a pin pair only defines a
relationship that governs an electrical net property. For example, you can define a pin pair
between an output pin of a microprocessor and an input pin of another microprocessor that are
part of the same net. You can then constrain the signal delay between these pins such that it
stays within a specific threshold, or minimum and maximum. Here is an example. of this.

Note
You can define pin pairs for nets that are of topology type TShape , HTree , Star ,
Custom , or Complex. You cannot define pin pairs for nets that are of topology type
Chained or MST .
Tip: After you define specific pairs of pins, the CES Spreadsheet column referring to a
pin pair designation is preceded with a icon. Be careful not to confuse this icon with
the resultant icon of non-graphical netline ordering ( ), which you use to create from-to
relationships.
To Define Pin Pairs Manually

1. From the CES Spreadsheet Nets page, click a net row. From the Edit menu, click Pin
Pairs, and then click Add Pin Pairs.
2. From the Define Pin Pairs dialog box, click to create a new pin pair relationship.
Optional: To make any internal EBD pins available for pin-pair definition, click .
(You must have an Electrical CES license to use this feature).
3. Click the Start Pin field, and then select a pin.
4. Click the End Pin field, and then select a pin.
Tip: To automatically create a pin pair, click instead of selecting the End Pin.
5. Repeat steps 2 through 4 for each pin pair you want to manually define.
6. After you finish defining pin pairs, click OK.
To Define Pin Pairs Semi-Automatically

2. From the Define Pin Pairs dialog box, click to create a new pin pair relationship.
3. Click the Start Pin field, and then select a pin.
4. Click .
Result: CES fills the End Pin field.
5. Repeat steps 2 through 4 for each pin pair you want to semi-automatically define.
6. After you finish defining pin pairs, click OK.
To Define All Pin Pairs Automatically

From the CES Spreadsheet Nets page, click a net row, and then from the Pairs toolbar, click .

Alternative: After you click a net row, from the Edit menu, click Pin Pairs, and then click
Auto Pin Pair Generation.
To Define Only Simulation Pin Pairs Automatically

From the CES Spreadsheet Nets page, right-click a net row, and then click Auto Simulation
Pin Pair Generation.
Alternative: After you click a net row, from the Edit menu, click Pin Pairs, and then click
Auto Simulation Pin Pair Generation.
Note
Simulation pin pairs are only pairings of load pins and source pins. No other pin
combination is a valid simulation pin pairing.
To Delete One or More Pin Pairs

2. From the Add Pin Pairs dialog box, click to select one or more pin pairs, and then click
.
3. After you finish deleting pin pairs, click OK.
Including Internal Component-Pin Delay

When you want to constrain signal delay such that it includes internal component-pin delays,
you can construct pin pairs using electrical board description (EBD) pins. When using EBD
pins, both pins of the pin pair must be of this pin type. Depending on your design methodology,
you might begin the constraint process for some pin pairs by including EBD pins at the start, or
instead, later change some standard pin pairs to EBD pin pairs to solve design challenges.
Note
In order to assign EBD pin pairs, you must have an Electrical CES license.
The following illustration depicts the physical difference between an external (that is, standard)
pin pair and an internal EBD pin pair.

Figure 7-3. Standard and EBD Pin Pairs
As you can see, the physical length of the connection between pin pairs is longer for EBD pin
pairs because internal component connections are included in addition to the trace segment
between external pins. After you create an EBD pin pair, you can specify delay and simulated
delay (signal edge rate) constraints.
Defining Discrete Component Pin Pairs

When your design includes complex discrete components like resistor packs, you can define pin
pairs for such components. You can define discrete pin pairs manually, or automatically based
on single-inline and dual-inline pin pairing.
Note
Before you can define discrete pin pairs, you must add the reference designator prefix
your design uses for resistor packs (for example, RP, RN, or both). To do so, from the
Setup menu, click Settings. From the Settings dialog box, under Design Preferences,
click Discrete Component Prefixes, and then in the Resistor cell, add your additional
reference designators. For example, when both RP and RN are used as reference
designators for resistor packs, and R is the one used for resistors, this cell will now
contain all three (for example: R, RN, RP).
To Define Discrete Pin Pairs

1. From the CES Spreadsheet Parts page, right-click a top-level discrete part that begins
with the reference designator prefix you added above (for example, RN), and then click
Create Pin Pairs.
2. From the Define Discrete Pin Pairs dialog box, perform one of the following tasks:
• To define pin pairs manually, click , and then click within the Start Pin and End
Pin cells to select each pin-pair pin. Repeat this step for each pin pair you want to
create.
Tip: To delete a pin pair, click its row, and then click .
• To define pin pairs automatically, click or to create dual-inline or single-inline
pin pairings.
3. After you finish defining discrete pin pairs, click OK.

Specifying Delay Rules for Nets

You can specify delay rules for nets, differential pairs, and pin pairs. When specifying delay
rules, you can do so based on physical or electrical properties. For example, to specify delay
from an electrical perspective, use time of flight instead of length. Time of flight is an electrical
observance that is defined by the duration of time for signal propagation between two points
(for example, pins).
Conversely, to specify delay from a physical perspective, use length instead of time of flight.
Length delay is a physical rule that defines the minimum and maximum trace distance between
pins. When a delay rule of this type is put in place, the router uses these minimum and
maximum values to determine an acceptable trace distance between the minimum and
maximum range. For example, setting Length or TOF Delay Min to 100 th and Length or TOF
Delay Max to 300 th would give the router a range of 200 th between these minimum and
maximum values.
Note
When specifying delay rules, you can use both types of delay rules within CES; however,
depending on your design requirements, you might use a single delay type exclusively.
Common Tasks
• “Matching Delay Rules Among Nets” on page 195
To Specify Delay Rules for Nets

1. With the CES Spreadsheet Nets page active, from the Group pulldown, click Delays
and Lengths.
it easier to work with delay constraints when the CES Spreadsheet Nets page displays
only them.
2. In the row of the net for which you want to specify delay rules, use the available
constraint fields to define delay based on length or time of flight. Here is a length
example.
Note: When you want to include the length or time of flight of vias that are part of a net,
you can express those inclusions by entering larger values that approximate the
appropriate increases to the overall length or time. Based on the above example, you
might instead use 150 for Min and 350 for Max.

Defining a Routing Tolerance for All Nets Within a

Constraint Class
Aside from defining general minimum and maximum delay constraints for nets within a
constraint class, you can also assign a tolerance to an entire constraint class through use of the
Length or TOF Delay tolerance (“Tol”) constraint. Doing so gives the router greater room to
increase or decrease the length of trace connections during routing operations. It is important to
understand that the tolerance is only displayed at the constraint-class level, but it is by default
used by all lower-level objects (for example, sub-level constraint classes and electrical nets).
Child-level constraint classes within a parent constraint class use the defined tolerance of the
parent constraint class by default; however, you can define a tighter tolerance at the child-class
level. In the event that you want to specify a tighter tolerance at the net level, you can do so by
defining a match relationship and then specifying a tolerance for the matched group of nets. To
do so, please refer to “Matching Delay Rules Among Nets” on page 195.
Specifying Maximum Length as a Percentage Above

Manhattan Length
You can use a net's Manhattan length plus a fixed percentage to specify the value used for the
maximum length constraint (Length or TOF Delay Max). Manhattan length is calculated in your
associated PCB layout tool. You can specify a length of Manhattan plus 1% or greater (for
example, 1%, 200%, 400%, or larger).
Note
Manhattan length values used in CES are not validated.
To Specify Maximum Length as Manhattan Length

In the Length or TOF Delay Max field, enter a value of 1 or more, and follow it with a
percentage symbol (%).
Example: To use a length that is 120% of the Manhattan length, enter 20%. To use a length that
is 500% of Manhattan length, enter 400%. To specify a length as close as possible to the
Manhattan length, enter 1%. This is depicted below.

Net Delay Calculations

When you define a time of flight or length delay constraint for an entire net instead of a pin pair,
delay is calculated by combining the trace segment lengths between each pin in the net. When
the delay method is time of flight, each trace segment length is converted to corresponding
delay values based on trace length and the propagation velocity associated with the board layer
on which a trace segment is located. When the calculated length or time of flight delay is less
than the minimum constraint for the net, one of the trace segments is increased to satisfy the
specified minimum delay.
Note
For electrical nets, the physical length of any devices that join physical nets is included in
the length calculation when available.
In order for delay to be calculated, the following requirements must be met:
• The layer stackup must have at least one plane layer (ground or voltage).
• The dielectric layers must have a valid thickness (greater than 0) and a valid dielectric
constant (greater than or equal to 1).
• The signal and plane layers must have a valid thickness (greater than 0).
Delay Value Default

When one or more of the above requirements is not met, a delay value based on the default
propagation velocity is used. This default value is 170 ps/inch (2.04 ns/ft).
Example of Specifying a Length Delay Rule for a Net Pin Pair

1. In the Type field of the pin pair for which you want to specify a length delay rule, click,
and then select Length.
2. In the Min field, enter a value for the minimum acceptable trace length between pins.
3. In the Max field, enter a value for the maximum acceptable trace length between pins.
Example: In the illustration below, the user chose a minimum value of 1000 th, and a
maximum value of 1500 th. Notice that this pin pair delay rule is a single instance that
does not have a match relationship or match tolerance associated with it.

Figure 7-4. Net Pin Pair With a Length Delay Rule
Matching Delay Rules Among Nets

By creating match groups, you can use the delay rules you define for a single net or pin pair as
the delay rule for multiple nets and/or pin pairs. You can also create match groups that do not
include minimum or maximum delay rules, but instead are matched only within a range. You
accomplish delay matching by setting up a match relationship, and optionally, a match
tolerance. The match feature of CES delay rule specification is especially useful when you want
to use the same time-of-flight or length delay range for bus nets, and similar design components
that lend themselves to rule reuse. When using match groups, all nets or pin pairs with the same
group identifier will be routed to the same length or delay within the tolerance.
Rules
• Match group identifiers that include multiple characters must begin with an alphabetical
character. After which, you can use any combination of alphabetical and numerical
characters, and underscores.
• A single match group can contain any combination of electrical nets, physical nets, and
pin pairs.
• When you do not set a tolerance for the matched group, the default tolerances for the
design are used. For information about how to review or set these values, please refer to
“Specifying Design Preferences” on page 59.
To Define a Match Relationship

1. In the Match field of an electrical net, physical net, or pin pair row, enter a match
identifier (for example, 1, a2, or b_3).
2. Optionally, in the tolerance (“Tol”) field, specify a tolerance (that is, length or delay
range that design objects must be within).
Example: To specify a tolerance of 100 th, type 100, and then press Enter. All design
objects that use this match relationship must be within 100 th of each other.

3. For each net for which you want to match this delay rule, in the Match field of each row,
type the match identifier (for example, 1, a2, or b_3) you specified in step 1, and then
press Enter.
Example of Specifying a Matched Time of Flight Delay for Several Pin Pairs
1. In the Type field of the pin pair for which you want to specify a time of flight delay rule,
click, and then select TOF.
2. In the Min field, enter a value for the minimum acceptable time of flight between pins.
3. In the Max field, enter a value for the maximum acceptable time of flight between pins.
4. In the Match field, enter an alphanumeric identifier for this time of flight delay rule.
Optional: Enter a tolerance value.
5. In the Match field of the net pin pairs for which you want to use this time of flight delay
rule, type the match identifier you chose in step 4.
Example: In the illustration below, the user chose a minimum acceptable value of 40 ns,
and a maximum acceptable value of 80 ns. The match identifier is set_a and has a
tolerance value of 5 ns. The user assigned this time of flight delay rule to the three net
pin pairs below it by entering set_a in each Match field. This match relationship means
that each of the four pin pairs must have a time of flight between 40 ns and 80 ns, and
their respective values must be within 5 ns of each other (for example, 60 ns, 61 ns, 63
ns, and 64 ns).
Figure 7-5. Net Pin Pair With a Time-Of-Flight Delay Rule
Example of Matching Length Delay Only by Tolerance

In this example, you are not concerned with the minimum and maximum length values to which
several nets will be matched, just the tolerance of the match group. As you can see in the
illustration below, the length of each net must be within 50 th of each other.

Figure 7-6. Matching by Just Tolerance
Related Topics
• “Defining Pin Pairs for Nets” on page 188
Matching Delay Tolerance at the Constraint Class Level

In addition to matching delay rules among nets, you can also match delay tolerance based on
constraint classes and their hierarchy. Doing so gives you the ability to easily ensure that all nets
within a constraint class end up with delay values that do not exceed a specific tolerance.
Furthermore, when you have parent constraint classes that include child constraint classes, or
even more extensive hierarchy, you can define a tolerance at each level. For example, at the
parent constraint class level, you might define a tolerance of 50 th, while at a child constraint
class level a tolerance of 25 th.
Matching delay tolerance at the constraint class level does not limit you from creating tolerance
matches among specific nets. This is regardless of whether the nets are part of the same
constraint class. For example, after matching delay tolerance within a constraint class to 100 th,
you can then create a match group with a tighter tolerance (for example, 50 th), and associate a
subset of nets within the constraint class with the match group. You can also associate nets that
do not belong to the constraint class with the match group.
Prerequisites
• You must have one or more constraint classes and nets assigned to constraint classes.
Procedure
1. From the CES Spreadsheet Nets page, in the Length or TOF Delay tolerance (“Tol”) cell
of the constraint class of interest, enter a tolerance value.
Note: Length or TOF Delay tolerance (“Tol”) cells are always editable for constraint
classes. Unlike net rows, you do not need to define a value in a Match cell in order to
make a tolerance (“Tol”) cell accessible.
2. Optionally, when there are sub-level/child constraint classes for which you want to
define tighter tolerances, enter a value in the associated Length or TOF Delay tolerance

(“Tol”) cell. The tolerance value for a child constraint class must be smaller than that of
the parent or child constraint class above it.
Results
The tolerance values will now be used during routing.
Simple Example of Matching Delay Tolerance by Constraint Class

In this example, all nets within a constraint class are specified to be matched to within 100 th of
each other. To provide tighter tolerance for a subset of nets, two match groups are created. One
requires ADDRESS0 and ADDRESS1 to be matched to within 75 th. The other requires PCS0
and PCS1 to be matched to within 50 th. The four other nets in the class respect the matching
requirement defined at the constraint class level.
Figure 7-7. Simple Example of Tolerance Matching by Constraint Class
Complex Example of Matching Delay Tolerance by Constraint Class

In this example, a more complex usage of tolerance matching is shown. The parent constraint
class High_Speed_Nets has a tolerance requirement of 100 th. The child constraint class
High_Speed_Bus_Nets has a tighter tolerance of 50 th. To allow for even tighter tolerances
within the child constraint class, two match groups are created. The first requires that two nets
are matched within a tolerance of 30 th. The other requires that four nets are matched within a
tolerance of 15 th. All other nets in the parent or child class respect the matching requirement
defined at the relevant constraint class level.

Defining Formulas to Create Net Relationships
Figure 7-8. Complex Example of Tolerance Matching by Constraint Class

You can define formulas to create relationships between nets, pin pairs, or differential pairs. By
doing so, you can set up delay relationships among similar design objects that would benefit
from such associations. For example, you can set one pin pair delay to equal the delay of
another (=), specify that the delay of one net must be greater than or less than the delay of
another (> or <), add or subtract the delay of one pin pair to or from the delay of another. You
can also include constants and variables to define net and pin pair delay with even more detail.
Common Tasks
• “Including Tolerance” on page 200
• “Entering Multiple Formulas” on page 201
• “Solving Formulas to Check for Errors” on page 202
• “Complex Formula Examples” on page 202
To Define a Formula
1. From the CES Spreadsheet Nets page, in the Formulas Formula cell of the net, pin pair,
or differential pair for which you want to define a formula, construct a formula using

available constants, variables, and accepted operators (=, >, <, +, -). Refer to the
following examples, which show common formula applications:
• A+3 – Length or delay equals constant A plus 3 units.
• B-2 – Length or delay equals constant B minus 2 units.
• >{\NET1\} – Length or delay must be greater than that of NET1.
• <{\NET01\} – Length or delay must be less than that of NET1.
• ={\NET01\} – Length or delay must be equal to another value.
Rule: Formulas assume ns unit of measure. When you are working with a different unit
of measure (for example, th), you must include it after the hardcoded value (for
example, 1000th).
2. After you enter an operator that requires a reference object (=, >, <), click the name cell
of the electrical net, physical net, differential pair, or other object that you want to use as
the reference. You can also type the object name, but clicking is recommended because
it is far more accurate and efficient when you have the option to do so.
Rule: The reference object must be same type as the object for which you are defining
the formula. For example, when you define a formula for a net, the reference object must
also be a net.
Note: CES distinguishes between electrical and physical nets that you include in
formulas by encasing them with bracket symbols or pipe symbols (for example,
{\<electrical net name\} or |\<physical net name>\|).
Note: When including virtual pins, they must appear in the form \VP#\-\VP#\. For
example, to include virtual pin number 12, enter the following: \VP12\-\VP12\
Including Tolerance
You can include tolerance in your formulas to introduce a range around a formula value. For
example, when you require length delay for several nets to be larger than 3000 th, but a
tolerance of 100 th is acceptable (that is, minimum value can be 2900 th), you can include the
tolerance in your formula.
To Include a Tolerance
At the end of the formula, enter +/-, the tolerance, and then the unit of measure.
Example: =2000th+/-100th specifies that the length delay can be between 1900th and 2100th.

Note
When you do not include a tolerance, the default tolerances for the design are used. For
information about how to review or set these values, please refer to “Specifying Design
Preferences” on page 59.
Tolerance Limitations
When you specify very small tolerances, it is important for these values to be no smaller than
0.012 th or 0.002 ps. Using tolerance values below these limitations can cause errors to occur
while CES solves a formula. Tolerance limitations are a general rule, but there are exceptions.
For example, in a net that is part of a match group, the tolerance limitation may need to be
divided by the number of netlines, effectively making the smallest possible tolerance much
larger (for example, 0.048 th).
Note
Formula errors associated with tolerances below the limitations do not affect tuning. The
layout system will always tune based on the provided tolerance. For example, entering a
tolerance of 0.01 th will cause CES to report a formula error, but layout tuning will use
the tolerance.
Entering Multiple Formulas

When you want to define two or more formulas for a net or pin pair, you must separate formulas
with the # character and include the net, pin pair, or differential pair name in each formula that
appears after the initial formula.
For example, when you want to set the delay constraint of a pin pair (for example, \U1\-
\3\@\U2\-\3\) to be equal to a pre-defined constant (for example, A) and less then a specific
value (for example, 800 th), the correct cell notation is =A#\U1\-\3\@\U2\-\3\<800th. The #
symbol defines an AND relationship between formula one (=A) and formula two (\U1\-
\3\@\U2\-\3\<800th).
Note
When entering multiple formulas, the net, pin pair, or differential pair name must
immediately follow the # symbol. When you type the # symbol, CES automatically adds
the name. In the event that it does not, to quickly and accurately add an object name to a
formula, click its name cell.

Solving Formulas to Check for Errors

After you define formulas, you can check them for errors by solving all formulas in your design.
When you do so, CES attempts to compute net and pin pair delay values based upon the
formulas that you have entered. After it is finished, you are notified of any formulas that contain
syntactic or semantic errors through the log file. In addition, cells that contain erroneous
formulas are also highlighted to make them easier to find.
To Solve Formulas
With CES Spreadsheet Nets page active, from the Pairs toolbar, click ; or, from the Data
menu, click Solve All Formulas.
Complex Formula Examples

Please refer to the following example formulas that show instances of complex usage:
• “Example Formula Matching Length Delay Within a Bus and Between Busses” on
page 202
• “Example Formula Where the Sum of Two Net Lengths Must be Less Than a Certain
Distance” on page 203
Example Formula Matching Length Delay Within a Bus and Between

Busses
In this example, you want to match the length delay for eight pin pairs that comprise a bus with
a tolerance of +/- 1.27 mm. In addition, you want to match the length delay of this bus between
specific external bus pin pairs with a tolerance of +/- 12.7 mm.
To Construct This Formula

1. Create two variables. One for within bus (for example, withinbus) matching and the
other for between bus (for example, betweenbusses) matching.
2. In the Formulas Formula cell of the first pin pair, enter =withinbus+/-1.27mm#<pin pair
name>=betweenbusses+/-12.7mm
Rule: CES automatically adds the pin pair name after you press #.
Example: When the pair name is C1\-\1\@\C1\-\5\, the formula would be =withinbus+/-
1.27mm#C1\-\1\@\C1\-\5\=betweenbusses+/-12.7mm
3. For the seven remaining pin pairs, enter or copy this formula in the Formulas Formula
cell.
4. For each external pin pair that you want to match between the pin pairs of this bus,
include =betweenbusses+/-12.7mm in the Formulas Formula cell.

Creating Constants and Variables for Delay Rules and Formulas
Example: When a pin pair already includes its own length formula (for example,
>50mm), append it to the end (>50mm#<pin pair name>=betweenbusses+/-12.7mm).
This formula requires that the pin pair length delay be greater than 50 millimeters AND
match the betweenbusses value calculated during routing. The tolerance of the final
value can be +/- 12.7 millimeters. Here is a depiction of this formula in the cell.
Example Formula Where the Sum of Two Net Lengths Must be Less Than a
Certain Distance
In this example, you need the cumulative length of two nets to be less than 5000 th. The two
nets are B1 and B2.
To Construct This Formula

1. In Formulas Formula cell for net B1, type the following: < 5000th -
2. Click net B2. Doing so adds this net to the Formulas Formula cell for net B1, resulting
with the following, completed definition: < 5000th -{\B2\}
Creating Constants and Variables for Delay

Rules and Formulas
You can create constants and variables to use when defining length and delay formulas within
the CES Spreadsheet in the Formulas Formula field. Creation and application of constants and
variables is a way to provide delay rule consistency across multiple nets or pin pairs within a
design. After you create constants or variables, you can delete specific entries that you no longer
need. You can also find variable references to view net or pin pair formulas that include
variables.
Using Free Variables to Constrain Delay by Group Only

Unlike constants, you never associate a pre-defined value with a variable, nor do you set a
variable to a specific value within the Formulas Formula cell of a net, pin pair, or differential
pair row. Variables, also known as “free variables,” give you the ability to constrain delay of
several objects by group, with no regard for the delay value that is produced automatically, or
manually during routing. For example, when you want the length delay of 16 nets that comprise
a bus to route to the same length, but you do not care what the length is, you can set each net
equal to this free variable (for example, =samelength) and allow the router to determine the
length to which to match each net.

Creating Constants and Variables for Delay Rules and Formulas
To Create Constants and Variables

1. With the CES Spreadsheet Nets page active, from the Edit menu, click Constants and
Variables, and then click Edit.
2. From the Constants and Variables List dialog box, make sure that the tab that
corresponds to the data type you want to create is selected (Constants or Variables), and
then click .
3. In the Name field, enter a name for the new constant or variable.
Rule: Constant and variable names can contain alphabetic characters (a - z) and
numerals (0 - 9). They cannot contain only numerical characters.
4. When defining a constant, in the Value field, enter a value for the new constant.
5. After you finish creating constants and variables, click OK.
In the example, three variables have been created. As you can see, variables do not have
assigned values.
To Delete Specific Constants or Variables

Variables, and then click Edit.
2. From the Constants and Variables List dialog box, use the tabs at the bottom to view
available constants or variables.
3. Click the constant or variable row you want to delete, and then click .
Tip: To select multiple constants or variables, use Ctrl-Click.

Specifying Simulated Delay Rules for Nets
4. After you finish deleting constants and variables, click OK.

In the example below, const_a and const_c are selected for deletion.
To Find Variable References

Variables, and then click Find Variables Reference.
2. From the Variables Reference dialog box, perform one of the following tasks:
• To expand or collapse the listing of nets or pin pairs for a variable, click the +/-
button
• To select a net or pin pair within the CES Spreadsheet, double-click a specific net or
pin pair
Related Topics
• “Defining Formulas to Create Net Relationships” on page 199

You can specify simulated delay rules to constrain the edge rates of individual electrical nets or
constraint classes by time. When using ICX Pro Verify in conjunction with CES, you can
accurately simulate actual values for these constraints to determine how closely they match.
ICX Pro Verify gives you the ability to test these constraints with multiple simulators, and
simulation settings, which makes it easy to verify sets of unique electrical requirements, corner
cases, and extreme corner cases.

Note
In order to use these constraints, you must have an Electrical CES license. In order to
calculate actual values for these constraints, you must be using ICX Pro Verify within
your design flow.
Common Tasks
• “Matching Simulated Delay Rules Among Nets or Constraint Classes” on page 207
When constraining delay through simulation, you can choose to constrain one or more signal-
edge properties with unique or identical minimum and maximum delay values. You can also
specify the maximum acceptable range between the actual values produced by simulation of
these minimums and maximums. When you are constraining based on range, but not actual
values, use Simulated Delay Max Range without defining minimum and maximum simulated
delay values to design source-synchronous busses where the absolute delay is not important, but
limiting the skew between bus nets is critical.
Unlike the constraints in the Delays and Lengths group of the CES Spreadsheet Nets page,
which you use to define the total delay for a net, simulated delay constraints control the
switching times between signal states. These states are formally referred to as the edge rates of a
signal, which are the following types:
• Rising edge – The amount of time it takes the signal to switch between low and high
signal states (off to on).
• Falling edge – The amount of time it takes the signal to switch between high and low
signal states (on to off).
Signal Edge Rates and Crosstalk

Constraining edge rates is a crucial component of signal integrity. It is directly related to
crosstalk. The speed of transition as a signal switches between its low and high states causes a
spike in interference energy from the switching net (aggressor) to others net in its vicinity
(victims). The faster a signal switches, the more interference energy it produces. Although you
can space parallel trace segments to account for strong EMI fields generated by fast edge rates,
slowing down edge rates is the best solution when adding extra trace length is not an option.
To Specify Simulated Delay Rules for Nets

1. With the CES Spreadsheet Nets page active, from the Group pulldown, click
Simulated Delays.
it easier to work with simulated delay constraints when the CES Spreadsheet Nets page
displays only them.

2. In the row of the net or constraint class for which you want to specify simulated delay
rules, click within the Simulation Settings cell, click the dropdown, and then select a
simulation template.
3. In the Simulation Stimulus cell, click the dropdown, and then select a simulation
stimulus.
4. Click within the Simulated Delay Edge cell to select the signal edge to constrain.
5. In the Simulated Delay Min and Simulated Delay Max cells, enter the target minimum
and maximum delays.
Rule: When the Simulated Delay Edge is set to Rise:Fall, enter unique minimum and
maximum delays by separating them with a colon (:).
6. Optionally, to specify a maximum range between the actual values produced for
Simulated Delay Min and Simulated Delay Max, in the Simulated Delay Max Range
cell, enter a value.
Note: Specify unique Rise:Fall values with a colon (for example, 20:30). In the example
below, unique rise and fall values are being used.
Matching Simulated Delay Rules Among Nets or

Constraint Classes
You can match the simulated delay constraints of a net or constraint class to use the same values
for another net or constraint class. When matching simulated delay values between a constraint
class and a net, the mean of the delay range for nets in the constraint class is used as the
matching simulated delay.
When matching simulated delay rules, the electrical net or constraint class to which you are
matching does not need to include defined constraints for Simulated Delay Min, Simulated
Delay Max, or Simulated Delay Max Range. By keeping these constraints undefined you can
specify edge rate commonality between multiple nets without constraining the common edge
rate to a specific value.
To Match Simulated Delay Among Nets

1. From the CES Spreadsheet Nets page, in the row of the net, differential pair, pin pair, or
constraint class for which you want to match simulated delay values, in its Simulated
Delay Match To cell, click to select the hierarchical level to which to match.

2. In the Simulated Delay Match cell, click .

3. From the Simulated Delay Match dialog box, click an appropriate hierarchical object,
and then click OK.
Result: The Simulated Delay Match cell now displays this design object, and the
Simulated Delay Offset and tolerance (“Tol”) constraints are accessible.
4. Optionally, specify an offset and/or tolerance.
Example: When matching Simulated Minimum Delay of 200 ns, entering an offset of -
50 and a tolerance of 10 means that Simulated Delay Actual Match Min must be
between 140 ns and 160 ns (that is, 200 ns -50 ns = 150 ns +/-10).
Example of Matching Simulated Delay Between Two Nets Without Defining

Specific Delay Values
In this example, you want to match both the rising and falling edges of two electrical nets, but
you are not interested in specifying appropriate minimum and maximum delay values, or the
maximum range between these values. Your concern is that the signal edges of these nets match
within a certain tolerance. The specific delay values are not of concern.
To Set Up This Simulated Delay Match Relationship

1. From the CES Spreadsheet Nets page, in the row of the electrical net you want the other
net to match, click within the Simulated Delay Edge cell, and then click Both.
2. Make sure that the Simulated Delay Min, Max, and Max Range cells are empty.
3. In the row of the electrical net you want to match to another net, in the Simulated Delay
Match To cell, click to select Net.
4. In the Simulated Delay Match cell, click .
5. From the Simulated Delay Match dialog box, click the electrical net you used in step 1,
and then click OK.
6. In the Simulated Delay tolerance (“Tol”) cell that is now accessible, enter a tolerance.
Example: In the illustration below, electrical nets DATA1 and DATA2 are matched.
DATA2 includes a tolerance of +/-10 for all actual values that are produced during ICX
Pro Verify simulation.

Defining Overshoot and Ringback Constraints
Figure 7-9. Simulated Delay Matching Between DATA1 and DATA2

You can define overshoot and ringback constraints to specify voltage requirements that
maintain component operability and signal integrity. The four overshoot constraints define the
high point, low point, extreme high point, and extreme low point voltage thresholds that the
specific logic components (for example, microprocessors) of a net can handle. Unlike logic
thresholds, which dictate the voltage levels needed to switch a component between logic states,
voltage thresholds are maximums and minimums that must be adhered in order to maintain
operability. Because of the small size and delicate nature of electronic components, too little or
too much voltage can cause irreversible damage, rendering them useless. In the illustration
below, you can see that logic thresholds are between the overshoot thresholds, with dynamic
thresholds encapsulating both logic and static thresholds.
Figure 7-10. Static and Dynamic Overshoot in Relation to Logic Thresholds
Ringback constraints, which are not depicted in the above illustration, give you the ability to
define the amount of ringback voltage a net can sustain while in its logic high or logic low state.
Too much ringback, also called feedback, can cause a component to haphazardly switch
between logic states. This is why it is important to define the maximum acceptable amount of
ringback energy individually for each logic state.
Note
Overshoot constraints must be rail-relative (rr) where rr = VLmin – abs for low and rr =
abs – VHmax for high.
Other Common Tasks

• “Understanding Static and Dynamic Overshoot” on page 211

Note
In order to use these constraints, you must have an Electrical CES license. In order to
calculate actual values for these constraints, you must be using ICX Pro Verify within
your design flow.
To Define Overshoot and Ringback Constraints

1. With the CES Spreadsheet Nets page active, from the Group pulldown, click
Overshoot/Ringback.
it easier to work with simulated delay constraints when the CES Spreadsheet Nets page
displays only them.
2. In the row of the net or constraint class for which you want to specify overshoot and
ringback constraints, click within the Simulation Settings cell, click the dropdown, and
then select a simulation template.
3. In the Simulation Stimulus cell, click the dropdown, and then select a simulation
stimulus.
4. In the Static Low Overshoot Max and Static High Overshoot Max cells, enter minimum
and maximum operating voltages.
5. Optionally, in the Dynamic Low Overshoot Max and Dynamic High Overshoot Max
cells, enter a lower minimum and higher maximum operating voltage, followed by a :
character and the duration of time each voltage can be sustained before CES should
report an error.
Example: To define a Dynamic High Overshoot Max constraint of 6 volts for 3
nanoseconds, enter 6:3.
6. In the Ringback High Min and Ringback Low Min cells, enter the maximum amount of
ringback voltage that is acceptable for high and low signal states.
7. In the Non-Monotonic Edge cell, use the dropdown to specify whether transitions
between signal states must be non-monotonic for the rising edge, falling edge, or both
edges.
In the example below, ringback values have been defined, and both the rising and falling edges
must be non-monotonic.

Modifying I/O Designer FPGA Constraints
Understanding Static and Dynamic Overshoot

Static and dynamic overshoot are two distinct types of overshoot that are often times confused
with each other. Static overshoot is unidimensional. The high and low values you use will
maintain component operability for an infinite duration. Dynamic overshoot is bidimensional.
Each extended high or low value is accompanied by a precise duration. Specification of this
duration is what makes dynamic overshoot possible. Although these durations are usually
extremely short, sometimes they are the key to solving design problems.
Tip: To learn more about each overshoot constraint, please refer to the CES Constraint
Reference (appendix chapter A).
Example of Defining Dynamic Overshoot Constraints With a 5 ns Limit

In this example, you have already assigned static overshoot constraints to a net. Static Low
Overshoot Max is set to .5, and Static High Overshoot Max is set to 5. Now, you want to define
the net's dynamic overshoot constraints and apply a duration of 5 nanoseconds to both Dynamic
Low Overshoot Max and Dynamic High Overshoot Max. The 5 ns value means that CES will
not report an error as long as the overshoot value is not met or exceeded for a continuous time-
period greater than 5 ns. The dynamic overshoot constraints you will define here are 1 and 5.5.
To Define These Overshoot Constraints

1. In the Dynamic Low Overshoot Max cell, enter 1:5, and then press Enter.
2. In the Dynamic High Overshoot Max cell, enter 5.5:5, and then press Enter.
Result: The net now has a fully-defined set of static and dynamic overshoot constraints.
In the illustration below, you can see that both dynamic overshoot constraints are
applicable for a duration of no more than 5 ns.
Figure 7-11. Dynamic Overshoots With a 5 ns Duration Limit
Modifying I/O Designer FPGA Constraints

You can modify I/O Designer field-programmable gate array (FPGA) constraints to define
technology standards. Because FPGA constraints are synchronized between front-end CES and
I/O Designer, modifications in either tool will result in an update across your schematic-capture
design flow. When you want to update these constraints across your entire design flow, you can

Defining Constraints for Single-Pin Nets
do so with standard forward-annotation processes. For more information about these

constraints, please refer to the following constraint reference topics:
• “I/O Standard” on page 396
Note
Only I/O Standard is accessible and modifiable through CES. All other I/O Designer
constraints are not available.
To Modify I/O Designer FPGA Constraints

1. With the CES Spreadsheet Nets page active, from the Group pulldown, click I/O.
Note: Because most I/O Designer constraints are defined by pin or pin pairs, make sure
that Filters > Levels > Pins and Pin Pairs are enabled.
2. In the row of the net, constraint class, pin, or pin pair for which you want to modify an
I/O Designer constraint, select or enter a value.
In the following example, the I/O Standard constraint has been set to SMBUS for net
OUTPUT1.

You can define a subset of constraint values for single-pin nets, which are also commonly
referred to as Net0 nets. The constraints you can define are located on the CES Spreadsheets
Nets page. Constraint cells that you cannot define are grayed out and not editable. In addition to
defining constraint values for Net0 nets, you can also assign this grouping of nets to a constraint
class and net class. Including them in a specific net class gives you the ability to define
clearances.
Within CES, all single-pin nets have one entry. Therefore, you define rules for all Net0 nets as a
group. Incidentally, all single-pin nets will be part of the same constraint class and net class.
Whether you have 200 single-pin nets, or just two, CES refers to them as “(Net0)-1:X”.
Prerequisites
• To give your layout system the ability to produce single-pin nets, from its Project
Integration dialog box, click to enable the following check box: Assign single pin nets to
unused pins, enabling fanout

Note: After you enable this checkbox, you must run forward annotation before the net
“(Net0)-1:X” will be visible in any CES sessions, those launched from your front-end or
back-end design system.
• Your design must contain at least one single-pin net.
Procedure
1. From the CES Spreadsheet Nets page, locate the following net row: (Net0)-1:X
2. Modify the subset of constraint cells that are available to (Net0)-1:X for definition.
Available constraints are modifiable, and not displayed as blank or read-only.
In the example illustration below, the “(Net0)-1:X” row has been enabled. It is part of the (All)
constraint class.
Results
The constraint changes you have made to (Net0)-1:X now apply to the entire grouping of single-
pin nets.


Chapter 8
Parallelism and Crosstalk Rule Creation
This section covers parallelism and crosstalk rule creation. Some of the topics include
determining when to use parallelism and crosstalk rules, defining parallelism rules for stack-up
layers, and assigning parallelism rules to nets and constraint classes. This section also provides
information about the definition of crosstalk rules for nets and constraint classes. Please refer to
the table of contents for the full listing of topics included in this section.
Determining When to Use Parallelism or

Crosstalk Rules
Before you define crosstalk rules for nets or constraint classes, or parallelism rules for stack-up
layers and then assign them to nets or constraint classes, you should have an understanding of
how parallelism and crosstalk rules differ to determine which rule type you want to use with
your design:
• Crosstalk rules give you the ability to specify the maximum amount of acceptable
interference energy (mV) for specific nets and constraint classes. Accordingly, the
hazard system displays violations that it encounters. Each crosstalk rule that you create
consists of two nets or constraint classes. The first object is the victim, and the second
object is the aggressor.
• Parallelism rules give you the ability to define pairings of net properties that specify
acceptable distances and parallelism run lengths between specific nets and net classes.
When Hazards identifies a distance/length pairing that has been breached, you can have
it resolve such violations through use of the Resolve button for the set of hazards. For
same layer parallelism rules, the router uses these rules to avoid creating violations
when running a Tune Crosstalk pass. The router does not use parallelism rules with the
Route pass or No Via Bias pass.
Parallelism Rules Hierarchy

When you assign multiple parallelism rules between nets, CES uses the rule with the lowest
level of hierarchy. For example, you assign parallelism rule PR1 to Net A and Net B. These nets
are grouped into separate constraint classes. When you assign a different parallelism rule (for
example, PR2) between these two constraint classes, Net A and Net B will use the net-to-net
parallelism rule instead of the class-to-class rule.
The hierarchy CES uses to determine parallelism-rule usage obeys the following order:

Defining Parallelism Rules for Stack-Up Layers
1. Net to net
2. Net to (All Nets)
3. Class to class
4. Class to (All Classes)

You can create rules that define parallelism for net segments that are on the same layer, adjacent
layers, or both. When you do so, you specify a combination of edge-to-edge spacing between
segments and the maximum length that segments can run in parallel without violation. By
defining parallelism rules, you can help control the amount of crosstalk by restricting excessive
segment parallelism. Before defining parallelism rules, you should have an understanding of
when to use parallelism and crosstalk rules.
When defining parallelism rules, you can create as many edge-to-edge and maximum length
combinations as you require. For example, a parallelism rule that contains two edge-to-edge and
maximum length combinations for net segments on the same layer might specify that segments
with an edge-to-edge spacing of 10 th can run parallel for no more than 1000 th, while those
with an edge-to-edge spacing of 5 th can run parallel for no more than 500 th.
Figure 8-1. Example Parallelism Rule
In the above example, the same layer trace segment Edge / Edge rules are more restrictive than
the corresponding adjacent layer trace segment rules.

Parallelism Rule Definition Methodologies

Depending on your design practices, you may define parallelism rules all at once, individually,
or as a mixture of these two methodologies as you work with the nets in a design. When
defining multiple rules, the method of parallelism rule creation explained in this topic gives you
the ability to quickly define multiple rules, making it best suited for this purpose. When defining
or refining individual rules, you can use the CES Spreadsheet Noise Rules page.
To Define Parallelism Rules

1. With the CES Spreadsheet Noise Rules page active, from the Pairs toolbar, click .
Alternative: From the Edit menu, click Parallelism Rules, and then click Define
Parallelism Rules.
2. From the Define Parallelism Rules dialog box, next to the Parallelism rules heading,
click , and then change the default name of the new rule (“New”) to a meaningful title.
Tip: Instead of creating a new rule, you can also use an existing parallelism rule as a
clone and then modify it to meet the needs of the unique rule. To do so, in the list of
existing parallelism rules, click one, and then click .
3. Define an edge-to-edge spacing and maximum length combination for each same layer
rule or adjacent layer segment rule you want this parallelism rule set to include by
performing one of the following tasks:
• To define a same layer segment rule, next to the Same layer segments heading, click
, and then enter an Edge / Edge value and a Max Parallel Len value.
• To define an adjacent layer segment rule, next to the Adjacent layer segments
heading, click , and then enter an Edge / Edge value and a Max Parallel Len value.
Tip: You can also create adjacent layer segment rules by cloning same layer segment
rules. To do so, next to Adjacent layer segments, click . When cloning, all rules are
recreated. You can remove rules that are not needed by clicking a row, and then clicking
.
4. After you finish entering edge-to-edge and maximum parallel length combinations, click
Apply.
Rule: The maximum length value associated with an edge-to-edge value cannot be
greater than the maximum length value associated with a larger edge-to-edge value. For
example, after you define an edge-to-edge and maximum length combination of 10 th
and 1200 th, an edge-to-edge value of 8 th must be accompanied by a maximum length
value that is less than the maximum length value of the previous set (that is, 1200 th).

Assigning Parallelism Rules to Nets and Constraint Classes
Note: When you enter incorrect values, the cell background is changed to red and the
data in the cell is not saved until you correct the value.
Related Topics
• “Determining When to Use Parallelism or Crosstalk Rules” on page 215
Assigning Parallelism Rules to Nets and

Constraint Classes
After you define parallelism rules, you can apply them to specific pairs of nets and constraint
classes by creating net-to-net or class-to-class parallelism rule assignments. Each parallelism
rule assignment includes two specific nets or constraint classes, and the parallelism rule to
which they must adhere. In addition, you can also apply all parallelism rules that you have
created to the nets or constraint classes that comprise a parallelism rule assignment.
Figure 8-2. Example of Assigned Parallelism Rule
In the above example illustration, the noise rule Bus1 assigns parallelism rule PR1 between all
nets in the Memory constraint class.
Common Tasks
• “Navigating to Assigned Parallelism Rules From the Nets Page” on page 220
To Assign Parallelism Rules to Nets or Constraint Classes

Alternative: From the CES Spreadsheet Noise Rules page, click , and then modify
the Noise Type, Constraint Class or Electrical Net Name Victim and Aggressor, and
Parallelism Rule fields using the appropriate field selector. For example, because Class-
Class is the default parallelism type, when assigning a net-to-net parallelism rule, click
to change this field to Net-Net. When assigning parallelism rules using the Assign
Parallelism Rules dialog box, you can access it from the Edit menu by clicking
Parallelism Rules, and then clicking Assign Parallelism Rules.
2. From the Assign Parallelism Rules dialog box, In the Noise rule type field, specify a net-
to-net or class-to-class assignment.

3. From the list of available electrical nets or constraint classes, select the nets or constraint
classes that will comprise the first half of the pairing (that is, reference nets or classes),
and then next to the Victim constraint class(es) or Victim electrical net(s) box, click .
Tip: To select multiple nets or constraint classes, you can use Ctrl-click, Shift-click, or
click-drag. To select nets or constraint classes by name, in the field below the list of
source nets or net classes, enter a search string, and then click .
4. From the list of nets or constraint classes, select the nets or constraint classes that will
comprise the second half of the pairing (that is, apply rules to nets or constraint classes),
and then next to the Aggressor constraint class(es) or Aggressor electrical net(s) box,
click .
Note: When assigning a parallelism rule to constraint classes, you can select all
constraint classes by using the (All Classes) selection. The selection (All) refers to the
default constraint class (All).
Tip: When you want to check for same net or same constraint class parallelism, select
the nets or constraint classes you chose in step 3.
5. In the Parallelism rule box, select a specific parallelism rule, and then click Apply.
Crosstalk: You can also define a maximum crosstalk value for these pairings of
electrical nets or constraint classes. To do so, in the Max crosstalk box, enter the
maximum amount of crosstalk that the victim nets or constraint classes can receive from
the aggressor nets or constraint classes.
Tip: Before clicking Apply, make sure that the lists of nets or constraint classes is
accurate. To remove any nets or constraint classes from either list, click to select them,
and then click the corresponding .
To View Detailed Parallelism Rule Information During Assignment

2. From the Assign Parallelism Rules dialog box, to the right of the Parallelism rule
dropdown, click .
Result: The Define Parallelism Rules dialog box is displayed.
Example of Assigning a Parallelism Rule Between a Single Constraint Class

and All Other Constraint Classes
In this example, you want to assign a parallelism rule between nets in a single constraint class
with nets in all other constraint classes. The parallelism rules includes both same-layer and
adjacent-layer segment edge-to-edge and maximum parallelism rule lengths. The nets in the
single constraint class are critical nets with strict net parallelism requirements.

To Assign a Parallelism Rule Between a Single Constraint Class and All

Other Constraint Classes
1. From the Assign Parallelism Rules dialog box, in the Noise rule type field, make sure
Class to Class is selected.
2. From the list of Available constraint class(es), select the single constraint class to
associate with all other constraint classes, and then next to the Victim constraint
class(es) list, click .
3. From the list of Available constraint class(es), select the (All Classes) row, and then next
to the Aggressor constraint class(es) list, click .
4. In the Parallelism rule box, click the dropdown, and then select the parallelism rule to
assign between the single constraint class and all other constraint classes, and then click
OK. In the illustration below the Noise Rules spreadsheet shows that parallelism rule
G10L100/G15L150 is assigned between constraint class HT_CONN_IN and all other
constraint classes.
Figure 8-3. Single Constraint Class and All Other Constraint Classes
Parallelism Rule Assignment
Navigating to Assigned Parallelism Rules From the Nets

Page
As you work with the CES Spreadsheet Nets page to define constraints for individual nets and
constraint classes, you can quickly navigate to the parallelism rules assigned to a net or
constraint class. By doing so, you can easily and accurately determine any parallelism-rule
assignments for a design object.
To Navigate to Assigned Parallelism Rules

From the CES Spreadsheet Nets page, right-click a net or constraint class, and then click
Navigate to Parallelism Rule.
Result: The Noise Rules page becomes active, and any parallelism rules assigned to the design
object are highlighted.
Related Topics
• “Creating Constraint Classes” on page 145
• “Defining Parallelism Rules for Stack-Up Layers” on page 216

Defining Crosstalk Rules for Nets and Constraint Classes
Defining Crosstalk Rules for Nets and Constraint

Classes
You can define crosstalk rules for pairs of nets and constraint classes to specify the maximum
crosstalk value for nets and constraint classes as part of an aggressor-victim relationship. Before
applying crosstalk rules to specific nets or constraint classes, you should have an understanding
of when to use parallelism and crosstalk rules.
When you define a maximum crosstalk value, you can also specify the victim net's signal state
(for example, Low or High) that is most susceptible to crosstalk. Because crosstalk is a
complicated matter that presents unique challenges based upon signal state, you can define
multiple crosstalk rules to specify constraints for aggressor-victim net and constraint class pairs.
For example, when Net B is in a low state, you can restrict the maximum crosstalk from Net A
to 10 mV. However, when Net B is in a high state, you can require that the maximum crosstalk
from Net A is no more than 5 mV.
To Define Crosstalk Rules for a Net or Constraint Class

1. With the CES Spreadsheet Noise Rules page active, right-click within the spreadsheet,
and then click New Rule.
2. In the Noise Type cell, click to specify whether the aggressor-victim relationship is Net-
to-Net or Class-to-Class (constraint class).
3. In the Constraint Class Or Electrical Net Name Victim field, click the browse button,
select the victim net or constraint class, and then click OK.
4. In the Constraint Class or Electrical Net Name Aggressor field, click the browse button,
select the aggressor net or constraint class, and then click OK.
5. In the Crosstalk Max cell, enter the maximum amount of crosstalk the victim net or
constraint class can receive from the aggressor.
6. Optionally, in the Crosstalk Level cell, click to select the signal state or states of the
victim net or constraint class using the following guidelines:
• High – The victim net is on (in its high state). The voltage level is at or above the
high threshold (for example, 5.1 V).
• Low – The victim net is off (in its low state). The voltage level is at or below the low
threshold (for example, 0.9 V).
• Tristate – The victim net is off, but a small voltage still flows from the receiver to
ground (for example, 0.5 V).
Result: The Crosstalk Max value is now the constraint for a specific net-to-net
relationship, or for all victim nets in a constraint class when receiving crosstalk from the
aggressor nets in another constraint class.

Defining Crosstalk Rules for Nets and Constraint Classes
Example of Defining Two Nets as Both Aggressors and Victims

In this example, you want to define two net-to-net crosstalk relationships to specify how Net A
and Net B should be constrained when each net is an aggressor or victim of the other. In this
case when Net A is the aggressor of victim Net B, the maximum crosstalk value Net B can
receive from Net A is 5 mV. Conversely, when Net B is the aggressor of victim Net A, the
maximum crosstalk value Net A can receive from Net B is 10 mV. In addition, both victim nets
must meet this constraint during all signal states.
To Define Two Nets As Both Aggressors and Victims

1. From the CES Spreadsheet Noise Rules page, click , and then in the Noise Type cell,
click Net-to-Net.
2. In the Constraint Class Or Electrical Net Name Victim field, click the browse button,
select Net A, and then click OK.
3. In the Constraint Class or Electrical Net Name Aggressor field, click the browse button,
select Net B, and then click OK.
4. In the Crosstalk Max cell, enter 10. In the Level cell, click to select All.
5. Repeat steps 1 through 4, and this time specify Net B as the victim net, Net A as the
aggressor net, and a Crosstalk Max value of 5.
Example: In the following illustration, net MICROAD4 can be susceptible to 10 mV of
crosstalk from net 50M_CLK. Conversely, when the aggressor-victim role is reversed,
net 50M_CLK can receive no more than 5 mV of crosstalk from net MICROAD4.
Figure 8-4. MICROAD4 and 50M_CLK Are Defined As Both Aggressor and
Victim Nets
Related Topics
• “Determining When to Use Parallelism or Crosstalk Rules” on page 215

Chapter 9
Differential Pair Creation and Pair Rule
Definition
This section covers differential pair and pair rule definition. Some of the topics included are
manual definition of differential pairs, and automatic definition of differential pairs. This
section also provides information about assigning rules to differential pairs. Please refer to the
Note
When any previously defined differential pairs now include a “push pin” next to them,
please refer to “Differential Pairs Conversion” on page 51.
Defining Differential Pairs Manually

You can manually define differential pairs by selecting the two electrical nets ( ) to define as
the differential pair. After you define a differential pair, the CES Spreadsheet Nets page is
updated to include the designation.
When you can match differential pairs by net name, you should consider creating differential
pairs automatically. By doing so, you can create differential pairs more efficiently. For more
information, please refer to “Defining Differential Pairs Automatically” on page 224.
Prerequisites
• Nets that you define as differential pairs must be part of the same constraint class and net
class.
• The nets must be electrical nets.
• Each net must include two or more pins. You cannot make differential pairs from single-
pin nets.
To Define Differential Pairs Manually

1. From the CES Spreadsheet Nets page, use Ctrl-click to select two electrical nets ( ),
and then from the Pairs toolbar, click .
Alternative: After you select two electrical nets, right-click either net, and then click
Create Diff Pair; or, from the Edit menu, click Diff Pairs, and then click Diff Pair
from Selected Nets.

Differential Pair Creation and Pair Rule Definition
Defining Differential Pairs Automatically
2. Optionally, to give the differential pair a unique name instead of its system-defined
name, right-click the differential-pair cell, and then click Rename. Now that the cell is
editable, type a new name, and then press Enter.
Figure 9-1. Differential Pair Example
After you create a differential pair, delay cells at the pair level could be highlighted to indicate
errors. This happens when each of the electrical nets you used to create the differential pair had
different delay values defined previously. To remove the error highlighting, you need to define
delay values at the differential-pair level.
To Delete a Differential Pair Designation

From the CES Spreadsheet Nets page, click a differential pair row ( ), and then press Delete.
To select multiple rows for simultaneous deletion, use Ctrl-click and Shift-click.
Related Topics
• “Assigning Rules to Differential Pairs” on page 227

You can automatically define differential pairs to quickly construct them from specific nets.
After you have CES automatically construct differential pairs based on a net name criterion,
IBIS model information, or regular expressions, you can select from the proposed list of
differential pairs to choose those that you want to create. After you create specific differential
pairs, the CES Spreadsheet Nets page is updated to include them.
The process of automatically creating differential pairs is not always a viable method. It
depends on whether your nets have naming characteristics, or IBIS models assigned to
components, that allow for identification of complimentary nets.
Prerequisites
• In order to automatically define differential pairs based on IBIS models, you must have
an Electrical CES license.
• Nets that comprise a differential pair must be part of the same net class and constraint
class.

To Automatically Define Differential Pairs

1. With the CES Spreadsheet Nets page active, from the Pairs toolbar, click .
Alternative: With the CES Spreadsheet Nets page active, from the Edit menu, click
Diff Pairs, and then click Auto Assign Diff Pairs.
2. From the Auto Assign Differential Pairs dialog box, In the Assign by field, select one of
the following assignment methods:
• Net Name – Group nets into differential pairs based on net naming conventions.
• IBIS Models – Group nets into differential pairs based on differential pin definitions
in available IBIS models. (You must have an Electrical CES license.)
Note: After selecting this method, click , and then proceed to step 5.
• Regular Expression – Group nets into differential pairs based on regular-expression
search criteria. When using this assignment method, search results for the Pair net
name field (step #4) will not be displayed when there are no search results for the
Net name field (step #3), even when they do exist.
The advantage of regular expressions is that you can use them to create more precise
net matching searches. In the event that the Net Name assignment method would not
work, you could create a regular expression that would identify certain pairs of
differential nets.
3. In the Net name field, enter a search criterion. For example, when assigning by net
name, you could use a search criterion of *_P when you know that each net with this
suffix should be paired with a net of the same name that uses a different suffix.
Tip: To view the list of electrical nets in your design, click Preview Nets. Doing so can
be helpful when you are entering criteria in the Net name field and Pair net name field.
After you are done reviewing the content of the Electrical Nets dialog box, click OK.
4. In the Pair net name field, enter an appropriate search criterion based on the Net name
search criterion you provided in step 3, and then click .
Example: When assigning by net name, a complimentary suffix to the example in step 3
(*_P) might be *_N. In the illustration below, you can see how the Net name and Pair

net name fields were used to discover five pairs of nets that may be candidates for
differential pair creation.
Note
It is important to understand that the Net name field takes precedence over the Pair net
name field. This comes in to effect when the net name string or regular expression string
you enter would result with the same net showing up in both the Electrical Net column
and Pair Net column. In these cases, the nets will show up in the Electrical Net column
only.
5. Unless you chose to assign by regular expressions, skip to the next step. In this case, the
Match Differential Pairs dialog box appears. For each pair row that was proposed based
on your regular expressions, you can click within the Pair Net column to select an
alternate pair net, when appropriate. After you finish making adjustments, click Accept.
Note: When two electrical nets on the same row do not match, the Pair Net cell is
highlighted in red. You can hover over a red cell or refer to the Output window to
determine the cause of the conflict (for example, the two nets do not belong to the same
net class).
6. In the list of proposed differential pairs, click to select the differential pairs that you
want to use, and then click Apply.
Tip: To select all proposed differential pairs, click . To unselect all differential pairs,
click .

Assigning Rules to Differential Pairs
Result: Differential pairs that you define automatically are indicated on the spreadsheet
in the same manner as differential pairs that you define manually.
7. Optionally, to give one or more differential pairs unique names instead of their system-
defined names, from the CES Spreadsheet, right-click a differential-pair cell, and then
click Rename. Now that the cell is editable, type a new name, and then press Enter.
After you automatically create one or more differential pairs, delay cells at the pair level could
be highlighted to indicate errors. This happens when each of the electrical nets that were used to
create a differential pair had different delay values defined previously. To remove error
highlighting, you need to define delay values at the differential-pair level.
To Delete a Differential Pair

From the CES Spreadsheet Nets page, click a differential-pair row ( ), and then press Delete.
IBIS Model [Diff_Pin] Section Declarations

Nets that are connected to a receiver or bidirectional pin in the [Diff_Pin] section of an IBIS
model are always simulated as differential pairs. This is true regardless of whether you define
the nets as differential pairs within CES. However, the router you use with CES will only enable
differential pair routing/constraints when you have defined a pairing in CES.

After you manually or automatically define differential-net pairings, you can assign rules
(constraint values) to each differential pair. Unlike many CES constraints, you cannot assign the
same rules to multiple differential pairs by grouping them into constraint or net classes. You
must define rules individually for each net pair.
Differential-Pair Rules
You can assign the following differential-pair rules/constraints:
• “Differential Pair Tol Max” on page 389 – Length or delay tolerance of the pair. For
example, when you need a set of differential pairs routed to a matched length or time of
flight delay, you can use this rule to define a very tight pair tolerance, but also define a
more loose matched group tolerance.
• “Convergence Tolerance Max” on page 390 – Maximum allowed difference in trace
length distance from a pad to the point where the traces start routing differentially at
Differential Spacing.
• “Distance to Convergence Max” on page 391 – Maximum allowed trace distance from a
pad to the point where the traces start routing differentially at Differential Spacing.

• “Separation Distance Max” on page 392 – Maximum allowed distance that differential
traces are allowed to be routed at a spacing greater or less than Differential Spacing.
• “Differential Spacing” on page 393 – Spacing at which differential pair traces must be
routed. Differential spacing is defined per layer. This is a reference field (read only)
when accessed from the Differential Pair tab. To modify this value, use the Trace & Via
Properties page, Diff Pair Spacing constraint.
• “Differential Impedance Target” on page 394 – Defines the target differential
impedance. When this constraint cannot be met, Differential Spacing is used.
• “Differential Impedance Tolerance” on page 395 – Introduces a tolerance around
Differential Impedance Target. You can define this constraint for each differential pair,
or individually for each net that comprises a differential pair.
To Assign Differential-Pair Rules

1. From the CES Spreadsheet Nets page, click the row of the differential pair ( ) to which
you want to assign differential-pair rules.
Tip: To limit the Nets spreadsheet to a subset of constraints that includes only
differential pair constraints, from the Group dropdown, click Differential Pair
Properties.
2. Click in a specific differential-pair rule field (for example, Differential Spacing), and
then enter an appropriate value.
3. Repeat step 2 to define more differential pair rules.
Example of Defining a Matched Group Tolerance and Pair Tolerance

By defining both a matched group tolerance and differential pair tolerance, you can specify
length or delay tolerances for differential pairs at the individual net and pair level. For example,
for three differential pairs consisting of six total nets, you first define a matched group tolerance
of 100 th to give the router the ability to route each of these nets such that the difference
between the longest and shortest net is less than or equal to 100 th. Because these six nets
comprise three differential pairs, you are also concerned about the difference in length between
each pair of nets that makes up a differential pair. To account for this, you define a pair
tolerance of 20 th to ensure that the maximum difference between net lengths at the differential
pair level is no greater than 20 th.

Figure 9-2. Differential Pairs With Two Types of Tolerances Defined
To Define a Matched Group Tolerance and Pair Tolerance

1. From the CES Spreadsheet Nets page, specify a Match and Tol for one net of the
intended matched group.
2. For the nets that will use this matched group tolerance, enter the match number you
choose in step 1 into the Match field of each appropriate net row.
Example: In the example above, you would specify the match and tolerance in the
spreadsheet row of one of the nets, and then enter the match number into the Match field
of the remaining nets.
3. From the CES Spreadsheet Nets page, specify an acceptable Pair Tol for each
differential pair that is comprised of the nets for which you defined a matched group
tolerance in step 2.
Example: In the example above, you would define a pair tolerance of 20 th for the three
differential pairs that are based upon the nets for which you defined a matched group
tolerance.
Related Topics
• “Defining Differential Pairs Manually” on page 223
• “Defining Differential Pairs Automatically” on page 224


Chapter 10
Constraint Template Creation and Reuse
This section covers constraint template creation and reuse. Some of the topics included are
creation of constraint templates, and application of constraint templates. This section also
provides information about constraint-template reuse in external designs. Please refer to the
Creating Constraint Templates to Capture Net

Constraints
You can create constraint templates to capture net constraints for reuse on similar nets within
your current design and external designs. Creating a constraint template for a single bus net is a
common application that could promote both design-internal and external constraint template
reuse. For example, after specifying the constraints that promote signal integrity for one bus net
within a 64-bit bus (that is, 64 total bus nets), you can quickly create a constraint template based
upon that net, and then apply the template to the other sixty-three bus nets that comprise the bus.
By exporting this constraint template, you can then import it into designs that have a common
bus structure, and reuse the constraint template to duplicate characteristics that promote signal
integrity for similar nets.
Note
When you modify constraint values from the CES Spreadsheet Constraint Templates
page, just the values in the template are changed. The originating values, which come
from other spreadsheet pages, are not modified.
To Create a Constraint Template

1. From the CES Spreadsheet Nets page, right-click an electrical net ( ), and then click
Create Constraint Template.
2. In the name field and optional description field, enter suitable identifiers for this
constraint template, and then click OK.
Tip: Enter a name and description that promotes the highest potential for proper reuse
among other designers and yourself.
3. The constraint template is created and now available from the CES Spreadsheet
Constraint Templates page for review or modification.
Optional: At this point you can define the Device Matching Pattern cell (for example,
QU988*) for one or more devices in the constraint template. It is a regular expression.

Creating Constraint Templates to Capture Net Constraints
By doing so, you can create name matching requirements that are used when the
constraint template is applied to a net. For more information about this cell, and when
you might use it, please refer to its description in “General Template Values” on
page 233.
To Rename a Constraint Template

1. From the CES Spreadsheet Constraint Templates page, right-click the name of the
constraint template, and then click Rename.
2. Type a new name, and then press Enter.
To Delete a Constraint Template

From the CES Spreadsheet Constraint Templates page, click the name of the constraint
template you want to delete, and then press Delete.
Developing Libraries of Constraint Templates

Because constraint templates capture all constraints defined for a specific net, constraint
templates are an extremely powerful and efficient way to reuse constraint specifications that
have resulted in or will result in faster progression from design concept to market placement. At
any time during or after the design creation process, you can export constraint templates to a
common directory to build a library of reusable design constraint sets that will streamline the
design creation process for future designs that contain many of the same connection
requirements between parts.
Tip: When developing a library of constraint templates, you should consider making it
accessible to all designers within your group when appropriate. By doing so, you can
leverage common design constraints and promote consistency.
Constraints and Values Stored With Each Template

When you create a constraint template, it combines net values and constraints to produce the
template. It does so by using internal CES database information, constraint definitions you have
made on the CES Spreadsheet Nets, Parts, and Noise Rules pages, and appropriate selections
from specific CES dialog boxes.
Please refer to the following table, which includes a description of each template cell that does
not originate from another spreadsheet page. For all other cells (for example, Formulas

Applying Constraint Templates to Nets
Formula), please refer to “Quick Reference - CES Constraint Spreadsheet” on page 28 or “CES
Constraint Reference” on page 289.
Table 10-1. General Template Values

Template Value Description
Template Name Name of the constraint template.
Description Description of constraint template, if provided.
Device Orig Name Name of the source object.
Device Matching Pattern Defines a regular-expression device name matching
pattern (e.g. QU988*) that becomes a requirement when
you apply the constraint template to a net. This is an
optional value. Here are some examples of when you
might use it:
• When automatic pin matching does not work precisely

or produce the needed outcome.
• When a group of nets includes one or more of the same
component.
As a side note, you generally would not need to define this

value when all components in a net are unique. This is
because the automatic pin matching process would have
no issues during application of the constraint template.
Device Type Part number of the source component.
Device Model IBIS model of the source object.
Device Value Discrete value of the source object, when available.
Pin Type Pin type of the source pin.
Pin Number Pin number of the source pin.
Pin Net Template net for the pin.
Pin Model Pin model of the source object.
Pin Set Type Type of pin set (e.g. balanced or unbalanced).
Pin Set Pins Pins included in pin set.
Net Constraint Class Constraint class to which the originating net belongs.

After you create a constraint template to capture net constraints, you can apply it to one or more
nets. It is important to understand that all constraints that can be defined within a template are

overwritten for a net during the application process. This includes constraint values within a
template that are “blank” or undefined.
When you apply a constraint template to a net, you should make sure that the net to which you
are applying it is an appropriate candidate for the constraint set defined in the template. During
the application process, which includes the process of elaboration, CES performs an analysis to
determine whether the target net is suitable for the constraint template. Depending on the
required level of similarity you defined while setting up CES, the potential for net application
will vary. By modifying the CES setting that dictates this similarity requirement, you can
specify how similar candidate nets must be to the net from which the constraint template
originated.
Tip: To modify the similarity requirement between constraint templates and net
candidates, from the Setup menu, click Settings, and then under Display, click General.
Now, change the Template match threshold. For example, to specify a lesser similarity
requirement, enter a smaller percentage value.
Guidelines for Applying Constraint Templates to Differential Pairs

When applying a constraint template to a differential pair, the constraint template must have
been created from a differential pair. For example, when you only have constraint templates
based off of single nets, trying to apply a constraint template to a differential pair will result
with no available constraint templates for selection. In some cases, you might want to apply a
single-net constraint template to each net that will comprise a differential pair before you create
the differential pair.
Guidelines for Applying Constraint Templates to Nets With Virtual Pins

When you apply a template that contains virtual pins, it will only be applied correctly to nets
when the following conditions are met:
• They are of the same topology type.

• They contain the same number of virtual pins.
For example, you create a template from a net that is topology type star and has two virtual pins.
You then try to apply the template to a net that is topology type TShape and also includes two
virtual pins. Because both the topology type and the number of virtual pins do not match, the
template is applied incorrectly. In fact, the net’s two virtual pins and fromtos are deleted.
Other Common Tasks

• “Applying Constraint Templates From the Nets Page” on page 236
• “Matching Devices More Precisely When Applying Constraint Templates” on page 236
• “Modifying Pin Matching for an Applied Constraint Template” on page 237

• “Updating a Net With Constraint Template Changes” on page 238
To Apply a Constraint Template to One or More Nets

1. With the CES Spreadsheet Nets page active, from the Edit menu, click Apply
Constraint Template.
2. From the Select Nets for Constraint Template Application dialog box, enter a Net Name
Filter to select the appropriate nets to which to apply the constraint template, and then
click .
3. In the Constraint Template field, use the pull down to select a constraint template.
4. Under the list of Proposed nets, use the checkbox next to each net to uncheck the nets to
which you do not want to apply the constraint template. While you are working with the
list of proposed nets, you can perform any of the following tasks:
• To apply the constraint template to all checked nets without exiting this dialog box,
to the right of the Proposed nets heading, click .
• To select all Proposed nets, click .
• To deselect all Proposed nets, click .
• To clear the list of Proposed nets and start over, click .
5. After you have tested and selected the nets to which you want to apply the constraint
template, click OK.
Optional: After you finish, the Constraint Template Matching dialog box is displayed,
which lets you modify pin matching. For more information, please refer to “Modifying
Pin Matching for an Applied Constraint Template” on page 237.
To Apply A Constraint Template from the Constraint Templates Page

1. With the CES Spreadsheet Constraint Templates page active, right-click a template
name row, and then click Assign nets.
2. From the Assign nets to template dialog box, use click and Ctrl-click to select one or
more nets.
Alternative: Use the search box, and optionally wildcard characters, to quickly select a
group of nets that match a name criteria.
3. After you finish highlighting the appropriate nets, click OK.

Applying Constraint Templates From the Nets Page

CES provides multiple methods of applying constraint templates to nets. The methods described
in the above procedures are generally more suitable for working with large numbers of nets. The
method described in the procedure below is useful when you want to work with a finite number
of nets by selecting individual nets on the CES Spreadsheet Nets page.
To Apply Constraint Templates From the Nets Page

1. Right-click an electrical net ( ), and then click Apply Constraint Template. To select
multiple nets, use Ctrl-click or Shift-click.
Tip: You can also apply a constraint template at the constraint-class level, but doing so
is only for propagation to the nets inside the constraint class. For this reason, the
constraint template will not be directly applied to the constraint class. This is because
constraint templates are meant to be applied to nets and not object hierarchy.
2. From the Select Constraint Template dialog box, select the constraint template to apply
to one or more nets.
3. When applying constraint templates to nets, specify whether the nets should be moved
into the constraint (electrical and signal integrity) and/or net (physical) classes defined
in the template. To make these specifications, click the check boxes associated with
Apply Constraint Class and Apply Net Class, and then click OK.
Example: To move nets into just the net class defined in the constraint template, make
sure that only Apply Net Class is checked.
Result: The Constraint Template Application Report dialog box shows the
compatibility between a constraint template and nets. It also applies the constraint
template to the selected nets when you begin this procedure with the right-click, Apply
Constraint Template command.
Matching Devices More Precisely When Applying

Constraint Templates
When automatic pin matching does not work as precisely as needed, you can define the Device
Matching Pattern value for one or more components in a constraint template. You can also
define this template value when you expect this to be the case. Here is a detailed example of
when you would use this value:
1. There is a set of nets that contain the following identical components: QU9881,
QU9882, and QU9883. These components have pins that are part of a netline topology.

2. You create a constraint template from the first net in the set. In the template, component
QU9881 is now defined as Dev1.
3. In the template, you define the Device Matching Pattern value for component Dev1 as
QU988*.
4. Now, when you apply the constraint template to the nets containing QU9882 and
QU9883, the Dev1 component is matched to these components. In essence, the pins will
create the same netline topology.
Modifying Pin Matching for an Applied Constraint

Template
You can modify pin matching for each net that is associated with a constraint template. After
you apply a constraint template to a net, the Constraint Template Matching dialog box is
automatically displayed. You can also display this dialog box when you need to update pin
matching.
The Constraint Template Matching display uses both color coding and numbering to show how
well a constraint template matches the net to which it is applied. The following are very
important fields of the dialog box:
• Pins Template – Displays the number of pins in the template.

• Pins Net – Displays the number of pins in the net.
• Pins Matched – Displays the number of net pins that have been matched to template
pins.
When matching constraint templates to nets, good matches are indicated with green color
coding of the Pins Net and Pins Matched fields. Red color coding indicates that there is not
sufficient matching. Yellow is used to show that the matching is not good, but it may be
suitable. In the following example illustration, green color coding is used to indicate that all 5of
the pins in the constraint template have been matched. The matching table at the bottom shows
which objects are matched to the template objects.

Figure 10-1. Example of Pin Matching Between Template and Net
To Modify Pin Matching

1. From the CES Spreadsheet Nets page, right-click the row of a net that is associated with
a constraint template, and then click Update Pin Matching.
2. From the Constraint Template Matching dialog box, in the table at the bottom, click the
right column of a pin row to change the net pin associated with one of the available
template pins.
Rule: Each template pin can only be associated with a single net pin.
3. After you finish making changes, click OK or Apply.
Updating a Net With Constraint Template Changes

After you modify the constraint definitions in a constraint template, nets associated with the
constraint template may not be updated automatically to include the template changes. When
they remain static, they reflect the constraint values that were stored in the template at the time
the constraint template was applied to the net. In these cases, you must update one more nets
associated with the constraint template to include the current constraint values with each net.
CES will only automatically update a net to actively reflect the template values when you have
it configured to do so. To modify this setting, from the Setup menu, click Settings, and then

Reusing Constraint Templates in External Designs
from the Settings dialog box, click Other. Under Constraint Templates, activate or clear the
Automatically apply templates checkbox, based on the desired behavior.
Tip: To make it easier to determine when changes have occurred and a net does not
reflect the current constraint values stored in the associated template, please refer to the
CES Spreadsheet Nets page, Template Status constraint.
To Manually Update a Net With Modified Template Values

From the CES Spreadsheet Nets page, right-click the row of a net that is associated with a
constraint template, and then click Reapply Constraint Template.
Figure 10-2. Status Cell Indicating Differences Between Net and Template
Related Topics
• “Creating Constraint Templates to Capture Net Constraints” on page 231
Reusing Constraint Templates in External

Designs
After you create one or more constraint templates, you can reuse them by exporting them to a
file, and then importing that file into the external design you intend for reuse. Each .cts file
(encrypted XML format) you export includes all constraint template definitions associated with
a CES database.
For example, after defining the physical, electrical, and signal integrity constraints for a net that
serves as the critical connection between two common components for a product line, you can
make the constraint template available for reuse by storing it in a common or collaborative
network directory. You and the other designers in your group now have the ability to reuse this
constraint template in similar designs by applying it to specific nets that benefit from the
constraint set.
To Reuse a Constraint Template in an External Design

1. Export CES constraint templates (File > Export > Constraint Templates) to a .cts file.
Alternative: To export a single template, from the Constraint Templates page, right-
click the template row, and then click Export Selection.
2. Launch CES on the design for which you want to reuse these constraint templates.

Reusing Constraint Templates in External Designs
3. From the File menu, click Import, and then click Constraint Templates.
4. From the Import Constraint Template dialog box, select a file of the type you want to
import (based on the following guidelines), and then click Open:
• .cts files – Constraint templates you exported from CES.
• .ctm files – Constraint templates you saved from within CTE, the constraint template
editor.
5. You can now apply the imported templates as needed. For more information, please
refer to the related topic below.
Related Topics
• “Exporting Constraints in Encrypted ASCII Format” on page 244
• “Importing CES Constraints” on page 245
• “Applying Constraint Templates to Nets” on page 233

Chapter 11
CES Constraints Export and Import
This section covers the export and import of CES constraints, which give you the ability to
reuse and modify constraint information. It includes several topics, each of which provides
procedures you use to accomplish these tasks.
Exporting CES Constraints

You can export CES constraints to capture constraints to a data file for the purpose of importing
them into CES at a later time, or decrypting and viewing the constraint data in an external
program. You can export CES constraints in the proprietary encrypted XML format (.cts),
encrypted CSV format (.ecsv), and proprietary encrypted ASCII format (.cs_).
General Tasks
You can export and process constraint data in the following ways:
• “Exporting Constraints in Encrypted XML Format” on page 241

• “Exporting Constraints in Encrypted CSV Format” on page 243
• “Exporting Constraints in Encrypted ASCII Format” on page 244
• “Decrypting and Encrypting Exported Constraint Data” on page 244
Exporting Constraints in Encrypted XML Format

You can export constraints in encrypted XML format (.cts) for the purpose of later importing
the constraint set that you chose to export. Because you cannot decrypt this format, you would
use this method when you do not need to edit the data, but simply want to import it into the
same design or another design. Typically, you would export data in this format for the purpose
of creating constraint backups, or making constraint templates available for reuse.
When exporting, you can either start with the entire constraint set and then reduce the total
amount of constraint data, or select just the spreadsheet rows you want to export. Depending on
the amount of data you want to capture, one of the two procedures below is more appropriate for
your purpose.
Note
You can also export CES constraints into proprietary encrypted XML format (.cts) using
a command-line tool. For more information, please refer to “cons2xml” on page 431.

Procedure
1. From the File menu, click Export, and then click Constraints.
2. From the CES - Export Constraints dialog box, specify the following, and then after you
finish, click Export:
• Data scope as all data or just specific pages. To select the pages to export, click to
activate the Selected pages radio button, and then click to highlight one or more
spreadsheet pages.
Note: When exporting just specific pages, referenced objects between the Nets page
and the Constraint Templates page are not included unless both pages are selected,
or you enable the Include referenced objects check box.
• Whether you want to include Default Constraints, User constraints, Objects
hierarchy, and Attributes.
• In the Description field, optionally, modify the textual description for the exported
data set. To do so, click to activate the Edit description check box, and then modify
the description.
3. From the Export Constraints dialog box, specify a filename and location for the
constraint data file you want to export, and then click Save.
To Export Only Selected Nets or Spreadsheet Rows

1. From the CES Spreadsheet, use click or Ctrl-click to select the row or rows you want to
export.
2. After you finish making your selections, right-click, and then click Export Selection.
3. From the Export Selected Constraints dialog box, specify the following options, and
then after you finish, click Export:
• When applicable, referenced objects between the Nets page and the Constraint
Templates page.
• Whether you want to include Default Constraints, User constraints, Objects
hierarchy, and Attributes.
• In the Description field, optionally, modify the textual description for the exported
data set. To do so, click to activate the Edit description check box, and then modify
the description.
4. From the resultant Export Constraints dialog box, specify a filename and location for the
constraint data file you want to export, and then click Save.

Related Topics
“Exporting CES Constraints” on page 241 “Importing CES Constraints” on page 245
“Reusing Constraint Templates in External
Designs” on page 239
Exporting Constraints in Encrypted CSV Format

You can export constraints in encrypted CSV format (.ecsv) for the purpose of producing
constraint data files that are similar to the encrypted ASCII format, but simplified with regard to
the reading and sorting of data. The encrypted CSV format is more explicit and easier for
external programs to read and write. It is important to note that over time, the encrypted ASCII
format will eventually become obsolete. Encrypted CSV is the recommended format.
Note
You can also export CES constraints into the encrypted CSV format (.ecsv) using a
command-line tool. For more information, please refer to “cons2csv” on page 429.
Prerequisites
• CES Diagnostics must report no issues in order for export to run.
Limitations
• Via assignments are not exported.
• Constraints are exported in hard-coded display units.
Procedure
1. From the File menu, click Export, and then click Constraints to encrypted CSV.
2. From the Export Constraints to Encrypted CSV dialog box, specify a filename and
location for the constraint data file you want to export, and then click Save.
Results
A single .ecsv file is created for all CES data. The file uses the units settings defined in CES.
The order of constraints is based on the default column order in CES for each page. When the
file already exists, a new one is created with an incremental suffix. For example,
<filename>_1.ecsv, <filename>_2.ecsv, etc.
After the export finishes processing, a log file for the export is written to the following location:
name>\csv_export_<date_time>.log

In the event that the log file contains errors or warning, and is not clean, the File Viewer
automatically displays it for you to review.
Related Topics
“Exporting CES Constraints” on page 241 “Decrypting and Encrypting Exported
Constraint Data” on page 244
“Importing Constraints in Encrypted CSV
Exporting Constraints in Encrypted ASCII Format

You can export constraints in encrypted ASCII format (.cs_) for the purpose of producing
constraint data files that you can then decrypt and view in an external application. You cannot
re-import encrypted ASCII format.
Note
You can also export CES constraints into the encrypted ASCII format (.cs_) using a
command-line tool. For more information, please refer to “cons2ascii” on page 428.
Procedure
1. From the File menu, click Export, and then click Constraints to encrypted ASCII.
2. From the Export Constraints to ASCII dialog box, specify a filename and location for
the constraint data files you want to export, and then click Save.
Results
Separate encrypted ASCII files are produced: one for each spreadsheet page and one for the
board stackup. Now that you have exported the file set, you can decrypt them as needed.
Related Topics
“Exporting CES Constraints” on page 241 “Decrypting and Encrypting Exported
Decrypting and Encrypting Exported Constraint Data

After you export constraint data in the encrypted ASCII format (.cs_) or encrypted CSV format
(.ecsv), you can decrypt those data files. You would commonly use the decrypted ASCII data to
generate reports of your design, prepare design reviews, or perform automated verification of
constraint data with external programs.

Importing CES Constraints
The purpose of working with decrypted CSV data is to view or modify it in an external
spreadsheet application that supports the CSV format. In the event that you do modify the CSV
data, or create CSV files from scratch for import, you must encrypt the data files before
importing them into CES.
Prerequisites
• You have the following license: cesencryption
• You have exported encrypted ASCII constraint data or encrypted CSV constraint data;
or, you have decrypted CSV that you want to encrypt.
Procedure
1. Verify that you have met all of the above prerequisites.
2. Run the following command with the appropriate arguments: “csv2dat” on page 433

You can import CES constraints for the purpose of reusing constraints and templates between
designs, when applicable, or to load a large number of constraints instead of entering them by
hand. When using import for the second purpose, you must be working in the CSV format.
After you import, you can set the unit type associated with the constraint set if the native setting
is not ideal. You can import .cts data files and .ecsv data files.
General Tasks
You can import and work with constraint data in the following ways:
• “Importing Constraints in Encrypted XML Format” on page 245

• “Importing Constraints in Encrypted CSV Format” on page 246
• “Working With the CSV Format” on page 249
Importing Constraints in Encrypted XML Format

You can import CES constraints and templates that you exported in encrypted XML format
(.cts) during an earlier CES session. By importing CES constraints that are stored in a data file,
you can easily work with constraint data that you, or another engineer saved at a previous time.
For example, when you are having trouble developing constraints for a specific net, you can
export your best-guess CES constraint data to a file, send it to another engineer (for example, a
signal integrity expert), and then that person can import your constraints in their CES
environment to help create the appropriate constraint solution.

Note
You can also import CES constraints in the proprietary encrypted XML format (.cts)
using a command-line tool. For more information, please refer to “cons2xml” on
page 431.
Notes on Import
• Via definitions and settings are not updated during the import process.
• When name changes have occurred after you export constraints, constraint values may
not be properly imported.
• After you import, you may want to set the display units for the constraint set. For more
information, please refer to “Setting Units for the CES Spreadsheet” on page 66.
Importing Constraints Between Designs

When you import constraints from one design to another, it is important to understand that the
following requirements and implications exist:
• In order for a net to become updated with the constraints stored in the exported file, the
net name must be an exact match between CES databases. For example, if the CES
database into which you are importing constraints contains net A1 but the exported
constraints file does not, no updates will be made to net A1 as a result of the import.
• For nets that have matching names between the CES database and the exported
constraints file, all constraint values for those nets will be overwritten.
Procedure
1. From the File menu, click Import, and then click Constraints.
2. From the Import Constraints dialog box, select the constraint file (.cts) you want to load,
and then click Open.
3. Optionally, set the display units for the constraint set. For more information, please refer
to “Setting Units for the CES Spreadsheet” on page 66.
Related Topics
“Importing CES Constraints” on page 245 “Exporting Constraints in Encrypted XML
Importing Constraints in Encrypted CSV Format

You can import constraints in encrypted CSV format (.ecsv) for the purpose of loading a large
number of constraints instead of entering them by hand. Typically, physical constraints such as

clearances, trace widths, and similar values. For example, you could import a large number of
package type clearance rules and overrides.
Encrypted CSV files you import can include just a single constraint table, or multiple tables. For
example, one file you might choose to import could include just general clearances and
clearances, while another could include all constraint tables that you can import. Before you
start an .ecsv import operation, the CES database is backed up through iCDB Project Backup.
Note
You can only import CES constraints in encrypted CSV format (.ecsv) using a command-
line tool. For more information, please refer to “cons2csv” on page 429.
Prerequisites
• Encrypted CSV import is controlled release functionality. You must have a special
license to use this functionality.
• You encrypted the .csv file into an .ecsv file using the command “csv2dat” on page 433.
• The stackup must already be defined for the project. Stackup definition or updates are
not supported.
Limitations
• Encrypted CSV import is not supported in an Enterprise Design Manager flow.
• Concurrent import is not supported.
• Just front-end snapshot import is fully supported. Please contact Mentor Graphics for
help when importing into a back-end snapshot.
• Import will run regardless of issues found through CES Diagnostics. It is strongly
recommended that you correct your design prior to importing.
Notes on Import
• Via definitions and settings are not updated during the import process.
• During this process, CES checks the syntax of the encrypted CSV file to validate its
components. This includes the CSV header, table names, display units, columns
(whether any are missing, redundant, or unknown), required values (whether any are
missing), unknown levels, and values.
• Integers and real numbers (“doubles”) are examined to determine if they fall within a
required range.
• When a file includes net constraint data or constraint template data, CES checks the
content during import.

Procedure
1. Verify that you have met the above prerequisites, and then run the command “cons2csv”
on page 429 with the appropriate arguments.
Results
After the import finishes processing, a log file for the import is written to the following location:
name>\csv_import_<date_time>.log
At this point, you may want to set the display units for the constraint set. For more information,
please refer to “Setting Units for the CES Spreadsheet” on page 66.
Related Topics
“Importing CES Constraints” on page 245 “Decrypting and Encrypting Exported
“Exporting Constraints in Encrypted CSV “ECSV Importer Error and Warning Codes”
Format” on page 243 on page 248
“Example CSV Files” on page 250 “Guidelines for CSV Files” on page 253
ECSV Importer Error and Warning Codes

Please refer to the table below for the full listing of ECSV importer code numbers and their
corresponding code names. You may find this information useful in the event that an import
operation will not complete, or even run at all, for a certain file.
Table 11-1. ECSV Importer Codes
Code Number Code Name
0 EIC_ResOk
1 EIC_ResOkWithErrors
2 EIC_ResOkWithWarnings
3 EIC_ResCmdSyntaxError
4 EIC_ResIOFileError
5 EIC_ResError
6 EIC_ResLicError
7 EIC_ResCesChkWarnings
8 EIC_ResCesChkErrors
10 EIC_ResCESPIError

Table 11-1. ECSV Importer Codes (cont.)

Code Number Code Name
11 EIC_DatabaseCannotOpen
12 EIC_DatabaseCannotLoad
13 EIC_DatabaseCannotLock
14 EIC_DatabaseCannotBeginTrans
15 EIC_DatabaseCannotCommitTrans
16 EIC_DatabaseCannotBackup
40 EIC_ResSyntaxValError
41 EIC_SyntaxQuoteMissing
42 EIC_SyntaxColumnMissing
43 EIC_SyntaxColumnRedundant
44 EIC_SyntaxColumnUnknown
45 EIC_SyntaxRequiredValueMissing
46 EIC_SyntaxLevelUnknown
47 EIC_SyntaxLevelNotAllowed
48 EIC_SyntaxValueInvalid
49 EIC_SyntaxValueRedundant
100 EIC_ContentError
101 EIC_ResContentNAWarning
102 EIC_ContentObjectMissing
150 EIC_ImportError
Related Topics
“Importing Constraints in Encrypted CSV
Working With the CSV Format

Although you can edit CSV files with an ASCII text editor, the best way to modify them is with
a spreadsheet application that supports the CSV format. This method is recommended because
the display of constraint data will look more familiar through a spreadsheet display. In addition,
there is the chance that you could accidentally remove one or more delimiters when using an
ASCII text editor.

Note
The value separator/delimeter you must use in these CSV files is a semicolon (;).
Prerequisites
• Encrypted CSV import is controlled release functionality. You must have a special
license to use this functionality.
• You decrypted one or more .ecsv files into .csv files using the command “csv2dat” on
page 433.
General Topics
• “Example CSV Files” on page 250
• “Guidelines for CSV Files” on page 253
Example CSV Files

Please refer to the example CSV files below, each of which represents what a CSV file looks
like in a spreadsheet application that supports the CSV format. The first example is a CSV file
that includes the following three constraint tables:
• Class to class clearances

• Z-Axis class to class clearances
• Package type clearance rules
Notice that two of the three constraint tables do not specify a value for “Display Units.” This
means that the constraints will be imported to match the unit type used for the constraints in
CES, or the constraints specified in the table do not have an associated unit type. For the third
constraint table, the unit type specified is th. In the event that CES does not use the same unit
type for those constraints, they will be converted from th to the CES unit type upon import. For
example, 500 th would be converted to 0.5 inches when the CES unit type for linear is inches.
Table 11-2. CSV File That Includes Multiple Constraint Tables

Table Class to class clearances
Display Units
Date 2012-03-21 13:52
Description Description
Scheme From Net Class To Net Class Clearance rule

(Master) (All) (All) (Default Rule)

Table 11-2. CSV File That Includes Multiple Constraint Tables (cont.)
(Minimum) (All) (All) (Default Rule)
BGA_RULE1 (All) (All) (Default Rule)
(Master) (Default) (Default) 10th
(Master) CLOCKS (All) 10th
(Master) CLOCKS CLOCKS 5th
(Master) DIFF_PR (All) 5th
(Master) DIFF_PR DIFF_PR 20th
(Master) POWER (All) 20th
(Master) POWER POWER 35th
(Minimum) (Default) (Default) 10th
(Minimum) CLOCKS (All) 10th
(Minimum) CLOCKS CLOCKS 5th
(Minimum) DIFF_PR (All) 5th
(Minimum) DIFF_PR DIFF_PR 20th
(Minimum) POWER (All) 20th
(Minimum) POWER POWER 35th
Table Z-Axis class to class clearances

Display Units
Date 2012-03-21 13:51
From Net Class To Net Class Z-Axis Clearance rule Max Layer Depth
CLOCKS (All) Rule1 2
CLOCKS CLOCKS Rule1 1
DIFF_PR (All) Rule2 4
DIFF_PR DIFF_PR Rule2 2
POWER (All) Rule1 2
POWER (Default) Rule1 1
POWER POWER Rule2 3

Table 11-2. CSV File That Includes Multiple Constraint Tables (cont.)
Table Package type clearance rules
Display Units th
Date 2012-03-21 14:00
Package Type Side Clearance

IC-DIP Both 15
General Top 21
Buried Bottom 12
The next example is a CSV file that includes just one constraint table, Z-Axis class to class
clearances. Notice that this table does not specify a value for “Display Units”. This is because
the constraints specified in the table do not have an associated unit type.
Table 11-3. CSV File That Includes a Single Constraint Table

Table Z-Axis class to class clearances
Display Units
Date 2012-03-21 13:51
From Net Class To Net Class Z-Axis Clearance rule Max Layer Depth
CLOCKS (All) Rule1 2
CLOCKS CLOCKS Rule1 1
DIFF_PR (All) Rule2 4
DIFF_PR DIFF_PR Rule2 2
POWER (All) Rule1 2
POWER (Default) Rule1 1
POWER POWER Rule2 3
Simple CSV File Shown in an ASCII Text Editor

Here is the same CSV file (from the table above) shown as it would appear in an ASCII text
editor. Notice that the value separator/delimiter used is a semicolon (;) and not a comma.
Table;Z-Axis class to class clearances;

Display Units;

Date;2012-03-21 13:51;
Description;Description;
From Net Class;To Net Class;Z-Axis Clearance rule;Max Layer Depth;

CLOCKS;(All);Rule1;2;
CLOCKS;CLOCKS;Rule1;1;
DIFF_PR;(All);Rule2;4;
DIFF_PR;DIFF_PR;Rule2;2;
POWER;(All);Rule1;2;
POWER;(Default);Rule1;1;
POWER;POWER;Rule2;3;
Related Topics
“Importing Constraints in Encrypted CSV “Guidelines for CSV Files” on page 253
Guidelines for CSV Files

In order to import an encrypted CSV file that (.ecsv) you produced from a .csv file, it must
follow certain guidelines. This includes ensuring that all required fields are available for each
constraint table in the file, the proper separation between constraint tables is present, and more.
Before familiarizing yourself with the information provided in this topic, it is recommended that
you look at some “Example CSV Files” on page 250.
Note
The value separator/delimeter you must use in these CSV files is a semicolon (;).
CSV Files Contain Constraint Tables That Consist of Sections

The following illustration shows you the sections that are required for each constraint table in a
CSV file. The CSV file represented by this illustration consists of a single constraint table.
Figure 11-1. Structure of a CSV File Containing One Constraint Table
Here is a description of each section:

• CSV Information Section - It identifies the type of constraints supplied in the constraints
section, the display units used, the date, and a description.
Note
“Table” and “Display Units” are the only required values in this section, though you can
leave “Display Units” blank when you do not want to specify a unit type, or are not
required to. For examples of this usage, please refer to “Example CSV Files” on
page 250.
• CSV Separator (one or more new lines) - A visual separation in the file that is used to
separate the information section from the constraints section, or the constraints section
from the next information section.
• CSV Constraints Section - It contains the constraint values that you want to import.
You can also include multiple constraint tables in a single CSV file. The following illustration
depicts a CSV file that contains two constraint tables. Notice that a CSV separator is used
between the two constraint tables.
Figure 11-2. Structure of a CSV File Containing Two Constraint Tables

Table Name Field in CSV Information Section

One of the two required fields in the CSV Information Section is the type of constraint table.
This field is not only required but also must match precisely to one of the names in the reference
table below (for example, “Z-Axis class to class clearances”).
Please note that currently not all constraint tables are supported for import at this time.
Unsupported constraint tables are indicated with an * in the listing of table names below.
Table 11-4. Constraint Tables
Valid Table Names
Class to class clearances
Clearance rules
Constraint templates *
Constants & variables *
General clearances
Nets *
Noise rules *
Package type clearance rules
Package type to package type clearance rules
Parallelism rules *
Parts *
Power & ground *
Stackup *
Traces
Via assignments
Z-Axis class to class clearances
Z-Axis clearance rules
Although the “Table” in a CSV Information section must be one of the above names, this does
not include case-sensitivity. For example, you could use either “Clearance rules” or
“CLEARANCE RULES”. Both would work.
Display Units Field in CSV Information Section

The second of the two required fields in the CSV Information Section is the “Display Units”
field. Although this field is required, you do not need to supply a value for some tables. When
you do want to provide a value, or are required to, you must use one (or more) of the display

units in the reference table below. For more information, please refer to “Constraint Tables and
Required Unit Type Declarations” on page 256.
It is important to note that these values are case sensitive. Please note that currently most unit
types are not supported for import. Unsupported unit types are indicated with an * in the table
below.
Table 11-5. Valid Display Units

Unit Type Display Units (Case Sensitive)
Linear in th mm um nm
Angle * deg Rad ‘ “
Capacitance * F mF uF nF
Voltage * V mV uV nV
Inductance * H mH uH nH
Power * W mW uW nW
Velocity * in/ns m/s %c
Resistance MOhm kOhm Ohm mOhm uOhm
Time * s ms us ns ps
Current * A mA uA nA pA
Temperature * degC
Theta * degC/W
When a constraint table includes constraints of multiple unit types, you can list them all by
separating them with a | character (for example, th|ns).
The table below shows you which constraint tables require you to declare one or more unit types
through the “Display Units;” statement. After the table, you can find a short list of guidelines
you must follow when making these declarations.
Table 11-6. Constraint Tables and Required Unit Type Declarations

Table Name Required Unit Types
Clearance rules <linear>
Example: Display Units th;

Constraint templates <linear>|<resistance>|<voltage>|<time>
Example: Display Units th|Ohm|mV|ps;

Table 11-6. Constraint Tables and Required Unit Type Declarations (cont.)
Table Name Required Unit Types
General clearances <linear>
Example: Display Units in;

Nets <linear>|<resistance>|<voltage>|<time>
Example: Display Units in|mOhm|V|ns

Noise rules <voltage>
Example: Display Units mV;

Package type clearance <linear>
rules
Package type to package <linear>
type clearance rules
Parallelism rules <linear>

Parts <time>|<temperature>|<power>|<theta>|<linear>
Example: Display Units ns|degC|W|degC/W|in;

Stackup <linear>|<resistance>
Example: Display Units th|Ohm;

Traces <resistance>|<linear>
Example: Display Units Ohm|th;

Via assignments None.
Z-Axis clearance rules <linear>

When specifying required unit type declarations, you must follow these rules:
• You can use whichever order you like for the unit types, but each required type must be
part of the declaration.
• You must only define a unit type once. Multiple declarations for the same unit type will
cause import to fail.

CSV Constraints Section

The CSV Constraints Section is the largest section in a constraint table. This is because it
specifies the constraint values that you want to import. When modifying the data in one or more
of these sections, please be aware of the following things:
• You have the option of using engineering/scientific notation for constraint values (for
example, 1.25E+6).
• For boolean values, you have the option of using “true” for 1/on and “false” for 0/off.
• You can assign a different display unit to any constraint value simply by putting it after
the value. For example, when the constraint table specifies “Display Units” of th, you
can put a value like 0.1mm in one or more cells.
• The order of columns is not important, but all column headings must be present. You
cannot import a table with any missing column headings.
• The order of rows is not important, but each row must contain all values. You cannot
import a table with any missing values; however, you can import empty values
(semicolon only) to preserve the current CES data.
• You can enclose data in double quotes when it makes sense to do so. For example:
Description;“Warning: Cannot import constraint: ““PLANE_TO_PLANE””
for layer ““ONE/AAA”””;
Related Topics
“Importing Constraints in Encrypted CSV “Example CSV Files” on page 250

Chapter 12
Stackup Display and Modification
This section covers stackup display and modification. It includes a single topic, viewing or
modifying stackup properties. This topic includes critical sub-topics that you should read and
understand prior to using the CES Stackup Editor.
Viewing or Modifying Stackup Properties

You can view or modify the properties of the stackup associated with a CES design to visualize
a cross section of the PCB and evaluate the effects of changing parameters of the materials used
in the board construction.
The term stackup refers to the layering of conductive and dielectric materials that make up a
printed circuit board. The characteristics of these materials (for example, thickness, dielectric
constants, and conductivity) and how they are ordered determine the electrical characteristics
(for example, nominal impedance) of the PCB's traces.
Caution
Because the CES stackup editor is designed to give you the ability to analyze the effects
of changing parameters on the electrical characteristics of traces, it allows for the entry of
any value for the material properties. There are a limited number of materials available
for the actual construction of a PCB. The list of materials and their actual characteristics
should be available from the PCB manufacturer. This list of materials limits the material
parameters available and also constrains the order in which they may be stacked. For a
useful stackup analysis, the material properties used should come from the
manufacturer’s supplied information.
Prerequisites
• Read and understand the information in “Correlating Layer Names Among Design
Tools” on page 260.
• Read and understand the information in “Stackup Editing Limitations” on page 260.
Procedure
1. From General toolbar, click , or, from the Edit menu, click Stackup.
See also: For detailed parameter and usage information on the CES Stackup Editor,
please refer to the Stackup Editor Help. This help system is accessible through the
dialog box Help buttons and Help > Contents menu selection of the Stackup Editor.

Stackup Display and Modification
Viewing or Modifying Stackup Properties
Correlating Layer Names Among Design Tools

The CES Spreadsheet, CES Stackup Editor, and your PCB layout system use slightly different
nomenclature when referring to unique board-layer types. Please refer to the following table for
an understanding of how these names correlate among design tools. PCB layout systems include
Expedition PCB, Board Station XE, and Board Station RE.
Table 12-1. Board-Layer Name Correlation
CES Spreadsheet CES Stackup Editor PCB Layout System
Signal Signal Signal
Solid Plane Solid Plane Plane
Mixed Split/Mixed Signal
Flood Signal Flooded Signal Flooded
Because CES deals with just signal-layer nets, dielectric layers displayed in the CES Stackup
Editor do not appear in the constraint spreadsheets.
Stackup Editing Limitations

The Mentor Graphics PCB layout tool you are using determines the level of functionality
available in the CES Stackup Editor. Parameters can be changed for evaluation purposes but
any changes made cannot be saved. In the Expedition Enterprise flow, stackup changes are
propagated to the layout tool.
You need to be aware of the following things when changing the stackup in CES:
• Changing the stackup on a board that has routing done in the PCB tool can have serious
consequences on the work done in the layout tool. For example, removing layers from
the stackup could easily result in lost routing if there are traces on the layer removed.
• Adding and removing layers can result in a stackup that is not manufacturable. The PCB
fabrication process is a series of layer lamination and drilling operations. Insertion of
layers in the CES stackup editor can result in a stackup that contains via spans that
cannot be drilled.
For the above reasons it is strongly recommended that addition or removal of layers be done
only in the PCB layout tool. The PCB layout tool has functions to move layers within the stack
and to alter or add via spans to prevent loss of work done in layout and ensure that the resulting
design can be manufactured.
Note

Chapter 13
Part-Model Assignment Verification and Part
Constraints Definition
This section covers model library definition, part model assignment, and model verification.
Mentor Graphics signal integrity tools get part pin characteristics for the purpose of simulation
from IBIS models. The IBIS model definitions for parts in your design are specified in the Parts
grid within CES. Please refer to the table of contents for the full listing of topics included in this
section.
IBIS Models Delivered With CES

CES comes with a set of IBIS models that you can use to model an array of component
technologies. This collection of over ten thousand model files is available within your
installation tree at the following location:
• Expedition Enterprise 7.x: <Install location>\7.xEE\mgc_ibis_lib

In addition, there are other IBIS models available at the following location:
• Expedition Enterprise 7.x: <Install location>\7.xEE\SDD_HOME\hssd\models\ibis\tech

You can also search your Mentor Graphics software installation for other .ibs files.
Specifying Available Part Models

You can specify the group of models that is available within CES for part assignment. When
making part models available to CES, you can update the group to include all model files stored
in a local or network directory, or just a single model file. CES supports IBIS (I/O Buffer
Information Specification) component models. In addition to the standard IBIS model file
format (.ibs), you can also use IBIS EBD (electrical board definition) model files (.ebd).
Note
In order to use this feature, you must have an Electrical CES license.
Other Common Tasks

• “Specifying Individual Model Files” on page 262
• “Understanding Relative Paths” on page 263

Part-Model Assignment Verification and Part Constraints Definition
Specifying Available Part Models
Specifying Model Libraries

You can add directories, remove existing directory entries, and change the order of directories
searched and displayed within the IBIS Model Browser. It is important to understand that CES
treats a file system directory containing IBIS models as a library. Use the procedures below to
make libraries available for model assignment and determine the order in which they are
searched.
To Add a Directory to the Model Search Path

1. From the Edit menu, click Simulation, and then click SI Library Search Paths.
another page active to enable this menu option.
Alternative: To access this dialog box from the IBIS Model Browser, at its top right,
click .
2. From the SI Library Search Paths dialog box, click .
3. In the new row that appears in the IBIS Libraries listing, enter the directory path, or click
the browse button to navigate to the path and select it.
To Remove a Directory From the Model Search Path

2. From the SI Library Search Paths dialog box, in the listing of IBIS Libraries, click the
directory you want to remove, and then click .
To Change the Search/Display Order of Model Directories

2. From the SI Library Search Paths dialog box, in the listing of IBIS Libraries, click the
directory for which you want you to change its order, and then click or to move the
directory up or down within the list.
Result: The IBIS Model Browser Directories / Components list is updated to reflect the
new order.
Specifying Individual Model Files

When you want to make one or more single model files available to CES, you can add
individual IBIS and EBD files to the group of available models. You can use both methods of
model specification interchangeably. For example, after specifying one or more model file
directories (libraries), you can add a dozen individual model files to complete the specification
of available models.

Verifying Default Model Assignments
To Add an Individual Model File

1. With the CES Spreadsheet Parts page active, in any IBIS Component Name or
Technology cell, click .
2. From the IBIS Model Browser, click .
3. From the Open dialog box, browse to the model file (.ibs or .ebd), select it, and then
click Open.
Result: All models included in the model file are now available within CES.
Understanding Relative Paths

When you enter a relative path, an attempt is made to fully resolve the path. On Windows, this
includes pre-pending the current drive letter from which CES was launched. When the path
does not exist, you are prompted with a dialog box asking whether you want to keep the path as
it is, or reject it. When you keep it, the unresolved path will be used.

The first time you launch CES on a design, it automatically assigns models to parts by matching
design components with part models located in the subfolders of your design folder. In order to
ensure that these assignments are correct, you should verify them using the content generated by
the Model Audit Report. When one or more assignments are incorrect or unavailable, you must
manually assign the correct model.
Note
To Verify Default Part Model Assignments

1. From the Output menu, click Model Audit Report.
2. From the Model Audit Report that CES produced, scroll its content to locate instances of
ERROR and WARNING lines.
3. For each instance, locate its row on the CES Spreadsheet Parts page, and then do one of
the following things:
• Assign the correct model to the part.
• Specify additional available part models, and then assign the correct model to the
part.

Automatic Assignment of IBIS Models

IBIS models you selected from within in your schematic capture or PCB layout design tool will
automatically be assigned in CES when the following conditions are met:
• The model matches the pinout of the part.

• The model parses without error.
• The PART_NO property for the part matches an IBIS Component name in an (.ibs) file
that resides in one of the SI Library search paths. For more information, please refer to
“Specifying Available Part Models” on page 261.
Hierarchical Assignment Process

CES uses the following assignment hierarchy to set the default IBIS Component Name value for
each part:
1. When you provide the IBIS component attribute on a symbol that is contained in a part
instance, it is used as the default IBIS component name. If this attribute is set on more
than one symbol that maps to a particular part instance, CES decides which wins based
on its established rules.
2. User provided IBIS component name for the entry in the PDB corresponding to the part
instance.
3. CES searches the IBIS library for a component with the same name as the PCB part
name. When it finds a case insensitive match, it uses this value.
4. CES searches the IBIS library for a component with the same name as the symbol name
for the part instance in the PDB. When it finds a case insensitive match, it uses this
value.
5. When the part instance has a Technology value, CES searches for an IBIS component
that matches the technology. When it finds a match, it uses this value.
6. When the part instance is a simple passive component that is included in the list below,
the IBIS component name is set to one of the following values:
• R_by_value (resistor)
• C_by_value (capacitor)
• L_by_value (inductor)
• RC_by_value (RC terminator)
• RThev_by_value (thevenin terminator)
7. When the part instance is not a simple passive component, diode, or connector, the
default IBIS component name is set to “generic”. The IBIS library provided with the

IBIS Models or Technology Models?
release always contains a supporting IBIS component named “generic” to support this
type of assignment.
Note
The only case where CES sets IBIS Component Name to reference a component that does
not exist is when you explicitly set a name in the schematic or PDB, and it does not exist.
Related Topics
• “Assigning Models to Parts” on page 265
IBIS Models or Technology Models?

Although you can assign an IBIS model and a technology model to a single part, when both are
present, the IBIS Component Name model is used. IBIS models provide greater detail than
technology models, which model pins based on pin type.
IBIS models include dedicated pin models for each component pin. For example, an IBIS model
for a sixteen pin component will include sixteen individual pin models. A technology model
used for the same component may include three or four pin models (that is, one for each type of
pin for the sixteen pin set).
Assigning Models to Parts

You can assign models to parts to specify the component technology used during ICX Pro
Verify design verification. In most cases, each part will already include a model assignment.
When an assignment is incorrect, you can change the model associated with a part. Because pin
information is stored in each part model, these designations are also used by CES to construct
accurate electrical nets.
Note
Common Tasks
• “Updating Part Model Constraints” on page 266
• “Reloading Model Directories and Individual Models” on page 267
To Assign a Model to a Component

1. From the CES Spreadsheet Parts page, in the row of the component to which you want
to assign a model, in its IBIS Component Name or Technology cells, click .

2. From the IBIS Model Browser, under Directories / Components, click a specific
directory, or click All to display models in all directories that are available to CES.
Tip: To select multiple directories but not all directories, use Ctrl-click and Shift-click.
To search for a directory, in the Search directory field, enter a search string, and then
click .
3. In the Component list, click the model you want to assign to the component.
Tip: To search for a model when the Component list includes a large number of models,
in the Search component field, enter a search string, and then click .
4. The above three steps define the IBIS model for the part. Many parts are configurable,
and the pin characteristics change depending upon how they are configured. To
accommodate this, the IBIS model may contain multiple pin models for a given pin. To
ensure accurate simulations, it is important that the correct pin model be selected for
these pins. The IBIS Model Browser indicates pins for which multiple models are
available by coloring the Pin cell yellow in the Pin Model Types table. To change a pin
model:
a. In the Pin Model Types field, click the dropdown, and then click a specific pin type
you want to view or change (for example, Output), or All to display all pins of the
part.
b. In the table below the Pin Model Types field, click in the Model cell of the pin you
want to change, and then select the pin model from the drop down list.
Tip: To change the display of this table, use the Select by Pin and Select by Model
radio buttons.
5. Click OK to apply the model assignment.
To Edit a Model File

From the IBIS Model Browser, select a model file from the Component list, and then do one of
the following things based on the editor you want to use:
• To use the ICX Pro Visual IBIS Editor, click .

• To use the Quick Model Wizard, click .
Information on the use of each of the above editors is available from the Help menu of the
respective editor.
Updating Part Model Constraints

You can update the IBIS Pin Type part model constraint to reflect accurate pin designations.
Doing so also updates default values.

To Update IBIS Pin Types

With the CES Spreadsheet Parts page active, from the Data menu, click Update, and then click
IBIS Pin Type & Defaults.
Reloading Model Directories and Individual Models

When one or more of your model directories or models are located in a network folder, it is best
practice to occasionally reload those model directories or individual models. By doing so, you
can make sure that the model data available to CES is the most current. You should also reload
model information when you make changes to any model directories or individual models on
your local machine.
Note
Reloading a model directory refreshes all individual models contained within it.
To Reload Model Directories

1. With the CES Spreadsheet Parts page active, in any IBIS Component Name or
Technology cell, click .
2. From the IBIS Model Browser, under Directories / Components, select one or more
model directories:
• Select all model directories by clicking the All row.
• Select two or more model directories by using Ctrl-click and Shift-click to highlight
the appropriate rows.
• Select just a single model directory by clicking it.
3. Click .
To Reload an Individual Model

From the IBIS Model Browser, in the list of available models, click a row, and then next to the
Search component field search button, click .
Tip: To adjust the list of available models, use the directory selections under Directories /
Components. For example, to list all available models, click All.
Related Topics
• “Specifying Available Part Models” on page 261
• “Updating Electrical Net Data and Results” on page 133

Overriding IBIS Values
Overriding IBIS Values

For discrete components, Thevenin terminators, and AC terminators that reference IBIS
models, you can override the discrete values stored in them by entering values directly into
CES. For example, although the IBIS model for a resistor specifies resistance as 50 ohms, you
want to temporarily change the value to 60 ohms.
To Override a Value
1. From the CES Spreadsheet Parts page, in an appropriate IBIS Component Name cell,
enter one of the following override types:
• C_by_value – Capacitance by value.
• L_by_value – Inductance by value.
• R_by_value – Resistance by value.
• RC_by_value – AC terminator by value.
• RThev_by_value – Thevenin terminator by value.
2. In the Value cell, enter one or more override values based on the following guidelines:
• For C_by_value, L_by_value, and R_by_value, enter a single override value.
• For RC_by_value, enter a resistance and a capacitance value, and separate them with
a colon (for example, 75:5).
• For RThev_by_value, enter two resistance values, and separate them with a colon
(for example, 75:75).
Example: In the following illustration, a resistor model has been changed to a Thevenin
terminator with resistance values of 75 ohms and 50 ohms.
Figure 13-1. Thevenin Terminator by Value
Defining Thermal Constraints for Parts

You can define thermal constraints within CES for the purpose of defining constraint values that
must be adhered to within your HyperLynx Thermal testing environment. Presently, these
constraints are only supported by that simulation tool. For more information about a specific

Importing Pin Package Length Values
thermal constraint, please refer to one of the constraint reference topics listed in the procedure
below.
Prerequisites
• To make use of any values you define for these constraints, you must be using
HyperLynx Thermal as part of your design flow.
Procedure
1. From the CES Spreadsheet Parts page, you can define constraint values for each of the
following thermal constraints:
• “Thermal Power Dissipation” on page 411
• “Thermal Power Scaling Factor” on page 412
• “Thermal Theta-jc” on page 413
• “Thermal Casing Temperature Limit” on page 414
• “Thermal Junction Temperature Limit” on page 415
Results
Any thermal constraints you define for the design will be included as requirements in your
HyperLynx Thermal simulation environment.

You can import pin package length values from a side file instead of manually entering values
for one or more Pin Package Length constraints. This task shows you how to use the CES GUI
to import the side file, but you can instead use a command-line utility to do so. For more
information, please refer to “ImportPinPackageLength” on page 434.
Note
In some cases, an IC vendor will provide a ready-to-use side file for one or more ICs. In
any event, the pin package length data will always come from the IC vendor.
Prerequisites
• You must have the appropriate side file: PinPkgLengths.txt
Procedure
1. From the File menu, click Import, and then click Pin Package Lengths.

2. From the Import Pin Package Lengths dialog box, navigate to and select a
PinPkgLengths.txt file.
3. Optionally click to enable the following checkbox: Set 0 when pin package lengths are
not specified. This checkbox set values to 0 for any pin package lengths that are not
specified in the side file. This only applies to pins of part numbers defined in the side
file. Otherwise, the existing values in CES are kept, when defined.
4. Review your selections, and then click Import.
Results
The CES Parts page is updated to display the imported values.
Related Topics
“Pin Package Length” on page 409 “Example PinPkgLengths.txt File” on
page 271

Example PinPkgLengths.txt File

The following example file shows a PinPkgLengths.txt file that contains definitions for two part
numbers. Units are in thousandths of an inch, and this is specified with the first line.
UNITS TH
PART_NUMBER ASIC_AS_0_SOIC_28P_25_394X236_I
5 100
8 200
1 100
7 200
3 200
4 100
2 100
6 200
PART_NUMBER AT25HP512_SOIC_8P_50_197X236_IC
1 100
2 100
3 100
4 100
5 150
6 150
7 150
8 150
As you can see from above, the pin package length definitions do not need to be ordered
chronologically. The first part number lists them out of order while the second part number lists
them in chronological order.
Caution
Comma symbols are not supported in these files, even if you have CES configured to use
commas instead of periods for decimal points.


Chapter 14
Signal Integrity Exploration
This section cover signal integrity exploration and enhancement with HyperLynx® LineSim®
and ICX Pro Explorer. Some of the topics included are sending nets out for signal integrity
analysis, and creating constraint templates to capture enhancements. This section also provides
information about updating CES with constraint enhancements. Please refer to the table of
contents for the full listing of topics included in this section.
Sending Nets to HyperLynx LineSim

You can export one or more electrical nets from the Nets page of the CES Spreadsheet to a
LineSim free-form schematic. In LineSim, you can run “what if” experiments to find physical
and electrical net properties that satisfy signal integrity and other performance requirements.
When you send a net from CES to HyperLynx LineSim, the board stackup for the design is
included to ensure simulation accuracy.
From LineSim, you can dynamically update CES with LineSim changes; or, export a constraint
template file that can be imported back into CES at a later time. It is important to note that some
information can be lost when transitioning your net data from a free-form schematic to a
constraint template file. For instructions regarding exporting a constraint template file from
LineSim, please refer to HyperLynx LineSim documentation or search the InfoHub to locate
this information.
Figure 14-1. CES-HyperLynx LineSim Design Flow
Prerequisites
• HyperLynx 8.0 or newer must be installed on the same computer as CES.
• HyperLynx must use or include the same IBIS search paths as CES.
Limitations
• Resistor and capacitor packages can be modeled with IBIS models in CES, however
HyperLynx does not support IBIS package models. On the other hand, HyperLynx
supports series elements described in IBIS/EBD files for IC components. This means

Sending Nets to HyperLynx LineSim
that resistors and capacitors with three or more pins, and assigned IBIS/EBD models, are
exported to the free-form schematic as IC components with assigned models. Only those
signal pins of passive network packages that are connected inside it (that is, belonging to
the same electrical net) are exported.
• Unconnected pins on the net have no topology information. These pins will be
connected in a “chained” routing topology that you can verify and edit in the free-form
schematic.
• Exported connectors are modeled in the free-form schematic as ICs with no model
assignment.
To Send Nets to HyperLynx LineSim

From the CES Spreadsheet Nets page, right-click a single electrical net ( ) or multiple
highlighted electrical nets (ten maximum), click Display Net in, and then click HyperLynx
LineSim.
Result: When HyperLynx 8.0 or newer is installed on the same computer, LineSim
automatically opens and displays the net in the free-form schematic editor. The exported free-
form schematic (FFS) and HyperLynx project (PJH) files are written to
\<projects_folder>\<project_name>\HighSpeed\HyperLynx\PreLayoutLineSim<net_name>.
For example,
C:\mentor_projects\test_project\HighSpeed\HyperLynx\PreLayoutLineSim\data1.ffs.
Related Topics
• “Updating CES With Constraint Enhancements” on page 279
Updating CES Dynamically With HyperLynx LineSim

Changes
As opposed to exporting a constraint template file to capture net enhancements you make in
HyperLynx LineSim, you can instead update CES nets with your changes on-the-fly as you
work within HyperLynx LineSim.
Prerequisites
• You must be using HyperLynx version 8.2 or newer.
• The CES session from which you exported one or more nets must be active.
Procedure
1. From the HyperLynx LineSim Export menu, click Constraint Template.
2. Activate Update CES with generated template, and then click OK.

Sending Nets to ICX Pro Explorer
Results
The changes are loaded into CES.
Related Topics
“Sending Nets to HyperLynx LineSim” on
page 273

You can send single nets from CES to ICX Pro Explorer to explore constraint enhancements for
nets that produce a large number of hazardous actuals in CES. By working with these nets in
ICX Pro Explorer, you can determine net and constraint changes that produce sufficient signal
integrity results. After you enhance a trace model schematic (net topology) in ICX Pro Explorer,
you can run simulation on just this topology, and analyze the results to determine which net and
constraint changes increase the integrity of the signal propagated by the net. This work flow is
captured in the following illustration.
Figure 14-2. CES-ICX Pro Explorer Design Flow
As the above flow diagram indicates, you can send a CES net directly to ICX Pro Explorer for
signal integrity exploration and enhancement work. Typically, you use CES constraint actuals
and hazard information displayed in your PCB system to determine which nets need ICX Pro
Explorer exploration.
After you send a net from CES, any modifications you make to it from within ICX Pro Explorer
are not reflected in CES until after you complete the update process. In addition, actual values
generated in the ICX Pro Explorer Simulation Results Spreadsheet are not displayed in CES.
To Send a Net to ICX Pro Explorer

From the CES Spreadsheet Nets page, right-click an electrical net ( ), click Display Net in,
and then click ICX Pro Explorer.
When sending a net, the following unit values from CES are included as necessary: Linear,
Ohms, Time, and Voltage. Based on your constraint definitions, some or all of these unit values
are accurately displayed in the SRS and CTE.

Related Topics
• “Updating CES With Constraint Enhancements” on page 279
Creating Constraint Templates to Capture Enhancements

After you enhance the signal integrity of a net topology from within ICX Pro Explorer, you can
create a constraint template to capture those enhancements for later application in CES.
Although a constraint template you create for a net will include any net topology enhancements
that you made while refining component and transmission line symbol properties, you can also
make additional net topology changes using the fields displayed by the Constraint Template
Editor. For example, you can modify high-speed constraints like overshoot, ringback, and
simulated delay (signal edge-rate delay).
Because multiple constraint templates can be displayed at the same time, you can also paint
rules to quickly reuse suitable constraints that you defined in one constraint template, without
having to hand-enter the rules into additional constraint templates.
Other Common Tasks

• “Reducing the Display of CTE Constraints” on page 277
• “Importing Constraint Templates” on page 278
• “Deleting Constraint-Template Objects” on page 278
To Create a Constraint Template

From the ICX Pro Explorer trace model schematic, right-click a driver or receiver symbol, click
Constraints, and then click Create Template (Selected).
Alternatives:
• After you click a driver or receiver symbol, from the File menu, click Create Template
(All).
• Right-click any driver or receiver symbol, click Constraints, and then click Create
Template (All).
To Save a Constraint Template

1. From the Constraint Template Editor (CTE) Main toolbar, click .
Alternative: From the File menu, click Save Template.
2. From the Export Constraint Template dialog box, specify a location and filename (.ctm),
and then click Save.
Rule: By default, constraint templates are saved in your top-level design folder.

Result: All constraint templates ( ) currently displayed in the CTE are saved to the .ctm
file you specified.
Updating a Net Topology With CTE Changes

When you make changes to the constraint values available from the Constraint Template Editor,
you must update the net topology if you want to re-simulate it using the updated constraint
values.
To Update a Net Topology for Simulation

From the CTE, click the top-level row of a constraint template, or a sub-level differential net
row, and then from the Main toolbar, click .
Example: In the following illustration, the positive net of a differential pair is selected for
update.
Figure 14-3. Sub-Level Net Selected for Update

You can quickly copy all constraint values that you define in a spreadsheet row into the rows of
other design objects that will benefit from these values. When painting rules to copy constraint
values, it is important to remember that the design object from which you copy must be the
same as the design object to which you copy.
To Copy Constraint Values Between Rows

1. Click a CTE spreadsheet row, and then from the Main toolbar, click .
2. Click the CTE spreadsheet row for which you want to apply the copied constraint
values.
3. Continue clicking additional rows to paint these rules where appropriate.
4. To turn off the Rule Painter, from the Main toolbar, click .
Reducing the Display of CTE Constraints

When you want to work with just a subset of CTE constraints, you can select from pre-defined
and user-created constraint groups to limit the types of constraints that are displayed.

To Display Only Specific Constraint Types in the CTE

From the Main toolbar, click the Group dropdown, and then select a constraint type.
Example: To display only Overshoot/Ringback constraints, click the Group dropdown, and
then click Template Overshoot/Ringback.
To Display All Constraint Types

From the Group dropdown, click All.
Importing Constraint Templates

You can import constraint templates into your ICX Pro Explorer environment for the purpose of
applying them to trace model schematics, viewing/editing them to verify their constraint values,
or painting rules from one constraint template to another. When your goal is application, the
Template Name associated with an imported constraint template must match the net name to
which you want to apply it.
To Import a Constraint Template

1. From the Main toolbar, click .
Alternative: From the File menu, click Open Template.
2. From the Import Constraint Template dialog box, browse to the appropriate constraint
template file (.ctm), and then click Open.
Deleting Constraint-Template Objects

As you work with constraint templates, you may want to delete a design-object row (for
example, a specific from-to or pin pair), or an entire constraint template.
To Delete a Constraint-Template Object

From the CTE, click a unique design-object row, or a top-level constraint-template row, and
then from the Main toolbar, click .
Rule: When you select a row that you cannot delete, the delete icon will not become active.
Related Topics
• “Sending Nets to HyperLynx LineSim” on page 273
• “Sending Nets to ICX Pro Explorer” on page 275

Updating CES With Constraint Enhancements

After you create a constraint template to capture net topology enhancements, you can apply it
one or more nets in CES. By doing so, you will complete the signal integrity and enhancement
process by updating CES with the work that you performed in HyperLynx LineSim or ICX Pro
Explorer. When you are using HyperLynx LineSim, you can instead update CES on-the-fly with
your changes. For more information, please refer to “Updating CES Dynamically With
HyperLynx LineSim Changes” on page 274.
Note
You must make a constraint template file (.ctm) available to CES before you can apply a
constraint template stored within it to a net.
To Update a CES Net With Constraint Enhancements

1. From the CES File menu, click Import, and then click Constraint Template.
2. From the CES Import Constraint Template dialog box, select the path and filename of
the constraint template file (.ctm) that includes your net topology enhancements, and
then click Open.
3. From the CES Spreadsheet Nets page, select one or more electrical nets ( ) to update,
right-click, and then click Apply Constraint Template.
4. From the Select Constraint Template dialog box, click the constraint template of the net
you enhanced in HyperLynx LineSim or ICX Pro Explorer, and then click OK.
Result: Your net enhancements are applied to one or more CES nets.
Example of Updating Net DiffPairA

In this example, you have used ICX Pro Explorer to enhance the signal integrity of a CES net,
DiffPairA. After saving the ICX Pro Explorer version of this net to a constraint template
(DiffPairNets.ctm), you are ready to update CES with the changes stored in the template.
To Update Net DiffPairA

1. From the CES Import Constraint Template dialog box, select DiffPairNets.ctm, and then
click Open.
2. From the CES Spreadsheet Nets page, right-click net DiffPairA, and then click Apply
Constraint Template.
3. From the Select Constraint Template dialog box, click the DiffPairA template, and then
click OK.
Result: CES net DiffPairA is updated to include the constraint enhancements of the
DiffPairA template, which was stored in the DiffPairNets.ctm template file.

Related Topics
• “Sending Nets to HyperLynx LineSim” on page 273
• “Sending Nets to ICX Pro Explorer” on page 275
• “Creating Constraint Templates to Capture Enhancements” on page 276

Chapter 15
Design Tool Update
This section covers design tool update. Some of the topics included are management of design
changes between tools, synchronization of constraint data between schematics and CES, and
sending schematic data to layout. This section also provides information about synchronization
of constraint data between CES and layout, and sending layout data to schematics. Please refer
to the table of contents for the full listing of topics included in this section.
Managing Design Changes Between Tools

After you exit CES, constraint changes you make while working within CES are automatically
synchronized with the schematic entry or PCB layout tool from which you launched CES. For
example, after launching CES from DxDesigner, changes that you make to constraints that
correspond to schematic design properties are updated within DxDesigner after you exit CES.
From a back-end perspective, Expedition PCB, for example, is updated with changes from CES
in the same manner; however, you can explicitly send pending CES changes to layout during
the active CES session as well.
When you want to update changes between the front-end and back-end tools that comprise your
flow, you can perform forward annotation by sending schematic data to layout, or back
annotation by updating schematic designs with changes from layout. During these processes,
constraint synchronization occurs, resulting in full updates of both the front-end and back-end
constraint sets. For more information, please refer to “CES Synchronization of Constraint
Databases” on page 282.
Communicating Design Changes Between Schematic and

Layout
CES provides several constraint-driven design flows that bring together front-end design
systems (schematic) like Design Architect, Board Architect, Design Capture, DesignView, and
DxDesigner with back-end design systems (layout) like Expedition PCB, Board Station XE, and
Board Station RE. Depending on the design systems that make up your design flow, you
communicate design changes between schematic and layout using the forward and back-
annotation commands provided by your design systems.
Constraint-Driven Design-Flow Manuals

For proper usage of these design annotation commands within the CES constraint-driven design
flow that you use, please refer to the following design-flow manuals:

Design Tool Update
• Constraint Editor System (CES) User's Manual for Board Station XE and RE Flows
(da_bs.pdf)
• Constraint Editor System (CES) User's Manual for Expedition Enterprise Flow: Design
Capture (dc_exp.pdf)
• Constraint Editor System (CES) User's Manual for Expedition Enterprise Flow:
DxDesigner (dx_exp.pdf)
You can find these PDFs within InfoHubs, on SupportNet, or in your Mentor software
installation directory.
CES Synchronization of Constraint Databases

The most important thing to understand about constraint synchronization is that both the front-
end and back-end constraint databases are updated as a result of this process. Regardless of
whether you are forward annotating or back annotating, both CES databases will have the
latest/synchronized constraint data. For this reason, the synchronization process is unlike
standard design annotation, which usually results in the front-end communicating its changes to
the back-end, or vice versa, but not both at the same time. The following illustration provides an
overview of this process.
Figure 15-1. CES Synchronization Updates Both CES Databases During Design
Annotation
How you set the winner for design annotation depends on the flow you are using. Refer to the
CES flow manual for your design flow for more information. For the listing of flow manuals,
please refer to “Constraint-Driven Design-Flow Manuals” on page 281.

Design Tool Update
Caution
When back annotating, there is the possibility for some objects to be skipped as part of
the PIM process. To determine if any updated objects were skipped and not back
annotated to the front end, please review the latest PIM log file for back annotation,
stored at <design_folder>\database\cdbsvr\PIMlog. When forward annotating, no
objects are skipped, therefore full synchronization always occurs.
CES synchronization works in this manner to provide more opportunities for constraint
alignment in all of its flows. Because both forward annotation and back annotation result in
constraint synchronization, overall design state is less of an issue for update purposes. For
example, when your Design Architect/Board Architect data is changing less frequently as you
move toward manufacturing start, forward annotating to Board Station XE gives you more
opportunities to acquire constraint changes made in XE-CES. Due to the large volume of design
changes that can occur in Board Station XE at the end of the PCB creation cycle, forward
annotating to get back-end constraint changes saves time because there are few or no schematic
changes to communicate to your layout design.
XtremePCB
XtremePCB gives multiple designers the ability to simultaneously work on a single layout
project. Because of this, CES synchronization is also used as a back-end only process to manage
changes to layer and net constraints within your PCB design. The result is that all constraint
work performed by multiple designers is accurately stored in the back-end CES database.
During forward annotation and back annotation, the front-end and back-end CES databases are
synchronized as explained above.
Note
When you run XDS Save from XtremePCB, it back annotates when necessary. As
expected, this back-annotation process includes full CES synchronization between back-
end and front-end constraint databases.
TeamPCB
TeamPCB gives you the ability to partition your layout design, but it does not incorporate
constraint changes made to a partition. For this reason, you should use TeamPCB to perform
layout operations to partitions–not constraint modifications. After a partition is rejoined to the
main layout design, you can modify constraints in CES.

Design Tool Update
Resolving Schematic Constraint Conflicts Manually
Resolving Schematic Constraint Conflicts

Manually
You can use the Constraint Resolution Manager (CRM) mode of CES to manually resolve
constraint conflicts that arise between sheets that you copy from a source schematic design to a
target schematic design. Providing manual constraint resolution during this type of copy gives
you the ability to specify the aspects of net design reuse you want to apply, while keeping
important constraint values that are unique to your design. In some cases, you might want to use
most of the constraint values in the source sheet, and keep only a few of the values of the sheet
in the target design. In other cases, you might specify that more constraint values in the target
sheet be used than those in the source sheet.
Prerequisites
• Optional, but recommended, set up your schematic tool to launch CRM automatically
when needed. Please refer to your schematic documentation to determine how to set up
the application to launch the Constraint Resolution Manager automatically for conflict
resolution when copying a sheet between two designs.
• You must have copied a schematic sheet from a source design to a target design.
Procedure
1. When CRM is not automatically displayed, from CES, with the CRM toolbar enabled,
select the most recent item from the dropdown list.
2. CES is now in CRM mode. It has the appearance of CES, but provides a limited subset
of functions related to manual resolution of constraint conflicts. At any time, to switch
from CRM mode back to CES, from the CRM Tools menu, click Constraint Editor
System.
3. When there are conflicting constraint values between source and target objects, the CES
Spreadsheet Nets page and/or Trace & Via Properties page will highlight each net and/or
layer row that has conflicting constraint values. Cells that do not conflict will remain
white.
4. For each conflicting cell, you can do the following:
• To view the list of available values from which you can choose, click the dropdown
button. “S” refers to the source value, “T” refers to the target value, and “C” refers to
a concurrent value that is being entered in real time.
• To change the default conflict resolution by choosing a different constraint value,
right-click a cell, and then click the appropriate Restore to selection. For example,
to use the value already in a sheet which you are pasting, click Restore to Target.
5. Change appropriate constraint values as often as you like until the correct set of source,
target, and concurrent values are present.

Design Tool Update
Resolving Schematic Constraint Conflicts Manually
6. After you have finished, close the CRM, or switch to CES mode. To do so, from the
CRM Tools menu, click Constraint Editor System.
Results
The set of appropriate constraint values is chosen. There are no longer any conflicting
constraints in the target sheet.
Related Topics
“Viewing Constraint Resolution Statistics” on
page 285
Viewing Constraint Resolution Statistics

While you are using the Constraint Resolution Manager, you may find it helpful to get a top-
level view of the source wins, target wins, or all constraint selections that you have made to
resolve each set of conflicting values. Doing so is especially helpful when you want to quickly
verify that the selections you have made are correct. The alternative is to scroll through each
affected page of the CES Spreadsheet. In comparison, using that method can be error-prone and
time-consuming.
Prerequisites
• CES must be in CRM mode.
Procedure
1. From the CRM Data menu, click Constraint Resolution.
2. From the Constraint Resolution dialog box, review the table of Source and target wins,
and the summary of win statistics located at the top of the dialog box.
3. Optionally, you can do any of the following:
• To display just target wins, click to enable the Show only target wins check box.
• To display only source wins, click to enable the Show only source wins check box.
• To update the table to show the latest wins after you make changes within the CRM,
click Refresh.
• To cross probe to the CES Spreadsheet row to which a win refers, click a list row.
Alternative: To move up or down one row in the wins list while cross probing, click
or .
4. After you finish reviewing statistics, click Close.

Design Tool Update
Synchronizing Constraint Data Between Schematics and CES
Results
The dialog box is no longer displayed on screen, leaving the CRM at the forefront of the screen.
Related Topics
“Resolving Schematic Constraint Conflicts
Manually” on page 284
Synchronizing Constraint Data Between

Schematics and CES
You synchronize constraint data between schematics and CES whenever CES saves your
constraint modifications. During this process, the front-end tool from which you launched CES
is updated with any applicable constraint changes or assignments.
Sending Schematic Data to Layout

After you synchronize constraint data between schematics and CES, you can send schematic
data to layout to update layout with any applicable changes. The process of sending schematic
data to layout is called forward annotation.
To Send Schematic Data to Layout

From your front-end design tool, or in some cases your back-end design tool, forward annotate.
Note: For specific forward-annotation commands, please refer to the CES constraint-driven
design-flow manual for your flow, or your schematic-capture software documentation.
Sending DxDesigner Schematic Data to Expedition PCB

When sending constraint changes you made in DxDesigner to Expedition PCB, you must first
create a front-end CES database by launching CES from DxDesigner. You must only do this
once in order for the database to be created. For example, after using only the DxDesigner
Attributes add-in to enter or modify Expedition PCB style constraints, you do not yet have a
front-end CES database. To create it, from the DxDesigner Tools menu, click Setup
Constraints.
Synchronizing Constraint Data Between CES and

Layout
You synchronize constraint data between layout and CES whenever you exit CES or explicitly
update layout with pending CES changes. During either of these processes, the back-end tool

Design Tool Update
Sending Layout Data to Schematics
from which you launched CES is updated with any applicable constraint changes or
assignments.
Note
You must save your layout database after you exit CES. This is true regardless of whether
you have made design changes to your layout database prior to launching CES. The only
way for your layout design to incorporate your constraint changes is through a save in
your layout software.

After you synchronize constraint data between layout and CES, you can update schematic
designs with changes from layout to update your schematic design with any applicable changes.
The process of updating schematic designs with changes from layout is called back annotation.
To Send Layout Data to Schematics

From your back-end design tool, back annotate.
Note: For specific back-annotation commands, please refer to the CES constraint-driven
design-flow manual for your flow, or your layout/routing software documentation.
Related Topics
• “Synchronizing Constraint Data Between CES and Layout” on page 286

Design Tool Update

Appendix A
CES Constraint Reference
This section provides a full constraint reference for each constraint available in CES. This
reference is organized and ordered to reflect the display of constraints on each CES Spreadsheet
page.
Using This Constraint Reference

The CES Constraint Reference includes information about each design constraint that appears
on the Trace & Via Properties, Clearances, Nets, Parts, and Noise Rules pages of the CES
Spreadsheet. Constraints in each category are listed by their default arrangement on a
spreadsheet page. By default, each constraint is available from the CES session launched from
any design tool unless otherwise specified.
Click within section “CES Constraint Reference” of the table of contents to view the
reference topic associated with a constraint. In the illustration below, the graphic available in
the overshoot constraint topic Dynamic Low Overshoot Max is shown.
Figure A-1. CES Constraint Reference Example Illustration
Note
For illustrative purposes, components and other board elements may appear
disproportionately large relative to PCB size.
Supported Design Components

Some constraints within this reference indicate that they are supported by design components
that may be included in your constraint-driven design flow. Please refer to the following
definitions for an understanding of each design component:
• AutoActive® – Integrated place and route environment of Expedition PCB, Board

Station XE, and Board Station RE.

Using This Constraint Reference
• Hazards – Dynamically updated design rule checking for placement and routing
constraint information. This component is available in Expedition PCB, Board Station
XE, and Board Station RE.
• High-speed routing (HSR) – Routing using estimation to determine how to adjust
routing to meet high-speed constraints (for example, time of flight delay or length
delay). This component is available in Expedition PCB, Board Station XE, and Board
Station RE.
• ICX Pro Verify – Design verification through full-board simulation of nets.
Related Topics
• “Quick Reference - CES Constraint Spreadsheet” on page 28
• “Defining Constraints With CES Spreadsheets” on page 99
• “Creating Constraint Groups” on page 118

Trace and Via Properties

Please refer to the trace and via property constraint reference topics that follow. These
constraints are accessible from the CES Spreadsheet Trace & Via Properties page.

Index
Displays the layer number for a board layer. This constraint is also displayed on the Clearances
page and Z-Axis Clearances page.
Tip: In the event that the stackup layer sequence is shown out of order in the spreadsheet,
you can click to sort by the Index heading to return the layer listing to its sequential order.
Constraint Type
Reference
Example
1

Type
Displays the type of printed circuit board layer (for example, signal, power, or ground). This
constraint is also displayed on the Clearances page.
Note
When Type is Flooded Signal, the Typical Impedance constraint is calculated based on
the test width and the Trace to Plane constraint for that layer in the (Master) scheme's
(Default Rule).
Constraint Type
Reference
Example
Power
Related Constraints
• “Trace To Plane” on page 308
• “Typical Impedance” on page 299

Via Assignments
Defines the via assignment for a net class.
Default means that the net class is using the via assignment defaults defined in CES setup,
which are general via settings for a design. Custom indicates that the via assignment design
defaults are not being used for this net class.

This constraint is supported during high-speed routing (HSR) and by Hazards in the AutoActive
environment.
For a definition of each supported design component, please refer to “Supported Design
Components” on page 289.
Constraint Type
Modifiable
Example
(default)
Related Topics
• “Specifying Trace and Via Rules” on page 154

Route
Defines whether the board layer is routed during PCB fabrication. You can define Route
individually or for all board layers of a net class.

environment.
Constraint Type
Modifiable
Related Topics

Trace Width Minimum

Defines the minimum acceptable trace width. You can define Trace Width Minimum
individually or for all board layers of a net class.
Trace Width Minimum is used whenever the router can successfully route at this trace width.
Figure A-2. Trace Width Minimum

environment.
Constraint Type
Modifiable
Example
8 mil
Related Constraints
• “Trace Width Expansion” on page 298
• “Trace Width Typical” on page 297
Related Topics

Trace Width Typical

Defines the typical acceptable trace width. You can define Trace Width Typical individually or
for all board layers of a net class.
This trace width is used by the router whenever possible.
Figure A-3. Trace Width Typical

environment.
Constraint Type
Modifiable
Example
9 mil
Related Constraints
• “Trace Width Expansion” on page 298
• “Trace Width Minimum” on page 296
Related Topics

Trace Width Expansion

Defines the expansion, or maximum acceptable trace width.You can define Trace Width
Expansion individually or for all board layers of a net class.
When the router needs to increase trace width to satisfy routing requirements, this trace width is
used.
Figure A-4. Trace Width Expansion

environment.
Constraint Type
Modifiable
Example
10 mil
Related Constraints
Related Topics

Typical Impedance
Defines signal impedance for the Trace Width Typical constraint. When you enter a value into
the Trace Width Typical cell, impedance at this width is calculated and placed into the Typical
Impedance cell.
Note
Typical Impedance is not calculated or able to be entered for traces that are on plane
layers. To indicate this, CES grays out the cell and leaves it empty.
In order for this constraint to be calculated, your board stackup must include at least one
plane layer.
When you adjust this constraint, Trace Width Typical is always updated unless you do not have
a valid stackup or the trace is on a plane layer.
When calculating impedance, the following stackup properties are included as necessary:
• Layer thickness
• Dielectric constants
• Position of plane layers
• Copper thickness for metal layers

This constraint is supported during high-speed routing (HSR) and by Hazards.
Constraint Type
Modifiable
Related Constraints
Related Topics

Differential Typical Impedance

Defines signal impedance for trace segments that are part of a differential pair. This value is
calculated and updated automatically when you modify Trace Width Typical, Typical
Impedance, or Differential Spacing.
Note
Differential Typical Impedance is not calculated or able to be entered for traces that are
on plane layers. To indicate this, CES grays out the cell and leaves it empty.
In order for this constraint to be calculated, your board stackup must include at least one
plane layer.
When you modify Differential Typical Impedance manually, Differential Spacing is updated as
well.
When calculating impedance, the following stackup properties are included as necessary:
• Layer thickness
• Dielectric constants
• Position of plane layers
• Copper thickness for metal layers

Constraint Type
Modifiable
Related Constraints
• “Typical Impedance” on page 299
• “Differential Spacing” on page 301
Related Topics

Differential Spacing
Defines the required parallel distance between trace segments that comprise a differential pair.
You can define Differential Spacing individually or for all board layers of a net class.
Figure A-5. Differential Spacing
Tip: When applied in conjunction with Differential Spacing, Trace Width Minimum
gives you the ability to define a smaller Differential Spacing constraint. As trace width
decreases, potential aggressor net interference between differential pairs reduces as the
total conductive surface area decreases.

Constraint Type
Modifiable
Example
0.5 mm
Related Constraints
Related Topics

Clearances
Clearances
Please refer to the clearance constraint reference topics that follow. These constraints are
accessible from the CES Spreadsheet Clearances page.
Note
By default, the clearance constraints defined in the (Defaut Rule) are used between all net
classes unless you create additional clearance rule sets and then assign them between
specific net classes.

Clearances
Index
Displays the layer number for a board layer. This constraint is also displayed on the Trace &
Via Properties page and Z-Axis Clearances page.
Constraint Type
Reference
Example
1

Clearances
Type
Displays the type of printed circuit board layer (for example, signal, power, or ground). This
constraint is also displayed on the Trace & Via Properties page.
Constraint Type
Reference
Example
Signal

Clearances
Trace To Trace
Defines the minimum clearance distance between trace segments. You can define Trace to
Trace individually or for all board layers of a clearance rule.
Figure A-6. Trace To Trace

This constraint is supported by Hazards in the AutoActive environment.
Constraint Type
Modifiable
Example
10 mil
Related Topics
• “Assigning Class-To-Class Clearance Rules” on page 165

Clearances
Trace To Pad
Defines the minimum clearance distance between traces and pads. You can define Trace To Pad
Figure A-7. Trace To Pad

Constraint Type
Modifiable
Example
12 mil
Related Topics

Clearances
Trace To Via
Defines the minimum clearance distance between traces and vias. You can define Trace To Via
Figure A-8. Trace To Via

Constraint Type
Modifiable
Example
8 mil
Related Topics

Clearances
Trace To Plane
Defines the minimum clearance distance between traces and planes. You can define Trace To
Plane individually or for all board layers of a clearance rule.
Figure A-9. Trace To Plane

Constraint Type
Modifiable
Example
20 mil
Related Topics

Clearances
Trace To SMD Pad

Defines the minimum clearance distance between the pads of surface mount devices and traces.
You can define Trace To SMD Pad individually, or for all board layers of a clearance rule.
Figure A-10. Trace To SMD Pad

Constraint Type
Modifiable
Example
15 mil
Related Topics

Clearances
Pad To Pad
Defines the minimum clearance distance between pads. You can define Pad To Pad individually
or for all board layers of a clearance rule.
Figure A-11. Pad To Pad

Constraint Type
Modifiable
Example
10 mil
Related Topics

Clearances
Pad To Via
Defines the minimum clearance distance between pads and vias. You can define Pad To Via
Figure A-12. Pad To Via

Constraint Type
Modifiable
Example
8 mil
Related Topics

Clearances
Pad To Plane
Defines the minimum clearance distance between pads and planes. You can define Pad To
Plane individually or for all board layers of a clearance rule.
Figure A-13. Pad To Plane

Constraint Type
Modifiable
Example
20 mil
Related Topics

Clearances
Via To Via
Defines the minimum clearance distance between vias. You can define Via To Via individually
or for all board layers of a clearance rule.
Figure A-14. Via To Via

Constraint Type
Modifiable
Example
10 mil
Related Topics

Clearances
Via To Plane
Defines the minimum clearance distance between vias and planes. You can define Via To Plane
Figure A-15. Via To Plane

Constraint Type
Modifiable
Example
10 mil
Related Topics

Clearances
Via To SMD Pad

Defines the minimum clearance distance between the pads of surface mount devices and vias.
You can define Via To SMD Pad individually, or for all board layers of a clearance rule.
Figure A-16. Via To SMD Pad

Constraint Type
Modifiable
Example
15 mil
Related Topics

Clearances
Plane To Plane
Defines the minimum clearance distance between planes. You can define Plane To Plane
Figure A-17. Plane To Plane
Note
When working in an Expedition PCB flow, you can only define this constraint at the
(Master) scheme level.

Constraint Type
Modifiable
Example
20 mil
Related Topics

Clearances
Embedded Resistor To Trace

Defines the minimum clearance distance between the resistive material of embedded thick-film
resistors and traces. You can define Embedded Resistor To Trace individually or for all board
Figure A-18. Embedded Resistor To Trace

Constraint Type
Modifiable
Example
15 mil
Related Topics

Clearances
Embedded Resistor To Pad

resistors and pads. You can define Embedded Resistor To Pad individually or for all board
Figure A-19. Embedded Resistor To Pad

Constraint Type
Modifiable
Example
15 mil
Related Topics

Clearances
Embedded Resistor To Via

resistors and vias. You can define Embedded Resistor To Via individually or for all board layers
Figure A-20. Embedded Resistor To Via

Constraint Type
Modifiable
Example
15 mil
Related Topics

Clearances
Embedded Resistor To Resistor

resistors. You can define Embedded Resistor To Resistor individually or for all board layers of
a clearance rule.
Figure A-21. Embedded Resistor To Resistor

Constraint Type
Modifiable
Example
15 mil
Related Topics

Clearances
EP Mask To Trace
Defines the minimum clearance distance between the production mask of embedded thin-film
resistors and traces. You can define EP Mask To Trace individually or for all board layers of a
clearance rule.
Figure A-22. EP Mask To Trace

Constraint Type
Modifiable
Example
15 mil
Related Topics

Clearances
EP Mask To Pad
resistors and pads. You can define EP Mask To Pad individually or for all board layers of a
clearance rule.
Figure A-23. EP Mask To Pad

Constraint Type
Modifiable
Example
15 mil
Related Topics

Clearances
EP Mask To Via
resistors and vias. You can define EP Mask To Via individually or for all board layers of a
clearance rule.
Figure A-24. EP Mask To Via

Constraint Type
Modifiable
Example
15 mil
Related Topics

Clearances
EP Mask To Resistor
resistors and the resistive material of embedded thick-film resistors. You can define EP Mask
To Resistor individually or for all board layers of a clearance rule.
Figure A-25. EP Mask To Resistor

Constraint Type
Modifiable
Example
15 mil
Related Topics

Z-Axis Clearances
Z-Axis Clearances
Please refer to the z-axis clearance constraint reference topics that follow. These constraints are
accessible from the CES Spreadsheet Z-Axis Clearances page.
Note
By default, z-axis clearance constraints, even those defined in the (Defaut Z-Axis Rule),
are not used between any net classes. In order to use your values for these constraints, you
must assign z-axis clearance rule sets between specific net classes.

Z-Axis Clearances
Index
Displays the layer number for a board layer. This constraint is also displayed on the Trace &
Via Properties page and Clearances page.
Constraint Type
Reference
Example
1

Z-Axis Clearances
Trace To Trace
Defines the minimum clearance distance between trace segments located on different signal
layers. You can define Trace To Trace individually or for all board layers of a clearance rule.
Figure A-26. Trace To Trace

Constraint Type
Modifiable
Example
10 mil
Related Topics
• “Assigning Z-Axis Class-To-Class Clearance Rules” on page 168

Z-Axis Clearances
Trace To Pad
Defines the minimum clearance distance between traces and pads located on different signal
layers. You can define Trace To Pad individually or for all board layers of a clearance rule.
Figure A-27. Trace To Pad

Constraint Type
Modifiable
Example
12 mil
Related Topics

Z-Axis Clearances
Trace To Via
Defines the minimum clearance distance between traces and vias located on different signal
layers. You can define Trace To Via individually or for all board layers of a clearance rule.
Figure A-28. Trace To Via

Constraint Type
Modifiable
Example
8 mil
Related Topics

Z-Axis Clearances
Trace To Plane
Defines the minimum clearance distance between traces and planes located on different signal
layers. You can define Trace To Plane individually or for all board layers of a clearance rule.
Figure A-29. Trace To Plane

Constraint Type
Modifiable
Example
20 mil
Related Topics

Z-Axis Clearances
Trace To SMD Pad

Defines the minimum clearance distance between the pads of surface mount devices and traces
located on internal signal layers. You can define Trace To SMD Pad individually, or for all
Figure A-30. Trace To SMD Pad

Constraint Type
Modifiable
Example
15 mil
Related Topics

Nets
Nets
Please refer to the net constraint reference topics that follow. These constraints are accessible
from the CES Spreadsheet Nets page.

Nets
Hierarchical Path
Displays the hierarchical path to the object within the design.
Nets Spreadsheet Group

All
Constraint Type
Reference
Example
sheet1

Nets
# Pins
Displays the number of pins that comprise the net.

Net Properties and All
Constraint Type
Reference
Example
2

Nets
Analog
Defines the net as analog and prevents physical nets that comprise an electrical net from being
merged into an electrical net or differential pair. You cannot define differential pair nets as
Analog. You can define Analog individually or for all nets of a constraint class.
Note
To change a net from an electrical net to a physical net, you can enable Analog for the net
row. When electrical nets are automatically updated in CES, the net will now show as a
physical net. To reverse the process, disable the Analog cell.

Constraint Type
Modifiable
Related Topics
• “Understanding Electrical Nets and Physical Nets in CES” on page 53
• “Specifying General Net Constraints” on page 179

Nets
Bus
Defines the constraint class as a bus. Nets within the constraint class should be limited to those
nets that comprise the bus.
The Bus constraint is also used to indicate that Expedition PCB should enable bus planning and
routing capabilities for a specific constraint class.

Constraint Type
Modifiable
Related Topics

Nets
Net Class
Displays the name of the net class to which the net belongs.
When you create a constraint template, this constraint is included.

Net Properties, Differential Pair Properties, and Delays and Lengths, and All
Constraint Type
Reference

Nets
Template Name
Optionally, defines the constraint template to which the net is assigned. You can define
Template Name individually or for all nets of a constraint class.

Template and All
Constraint Type
Modifiable

Nets
Template Status
Displays the synchronization status of the net with regard to the current values stored in the
constraint template.
When one or more constraints values of a constraint template are modified after it was assigned
to one or more nets, the Template Status cell will indicate that the net no longer includes the
latest template values.

Template and All
Constraint Type
Reference
Related Topics
• “Updating a Net With Constraint Template Changes” on page 238

Nets
Topology Type
Defines the topology type used for routing, which can be an automatic routing pattern, or
custom routing pattern that you define. You can define Topology Type individually or for all
You can choose from the following automatic topology types, each of which has a
corresponding Topology toolbar button:
• – MST (Minimum Spanning Tree) tells the router to connect the pins in any way
possible.
• – Chained instructs the router to connect nets from pin to pin beginning with all
sources, all loads, and then all terminators.
• – TShape tells the router to connect pins based upon a T-shaped physical model.
• – Star instructs the router to connect pins based upon a star-shaped physical model.
• – HTree tells the router to connect pins based upon a hierarchical tree model.
• Custom/Complex – When creating a custom topology type, you can define Topology
Type as either Custom or Complex. Custom is used for netline ordering that does not
include pin sets. Complex is used for netline ordering that does include pin sets. When
you begin the process of netline ordering a Custom topology, if you add a pin set, its
type is changed to Complex.
When you define Topology Type for a differential pair, it is applied to both nets that comprise
the differential pair. The same is true when you define it for a net that comprises a differential
pair. After you do so, the other net and the differential pair level all show the updated selection.

environment.

Constraint Type
Modifiable

Nets
Related Constraints
• “Topology Ordered” on page 342
Related Topics
• “Specifying Topologies for Nets and Constraint Classes” on page 180

Nets
Topology Ordered
For Topology Type Custom or Complex, displays whether the custom topology type has
undergone netline ordering, which is required for each user-specific topology type.
When defining netline ordering for a Complex topology, the Topology Ordered cell will not
update to state “Yes” until the next time you launch CES from the PCB layout system. This is
because the PCB layout system needs to analyze your usage of pin sets and fromtos to ensure
that the Complex topology is in fact fully ordered.

Constraint Type
Reference
Related Constraints
• “Topology Type” on page 340

Nets
Stub Length Max

Defines the maximum stub length that can be created when routing this net as a custom,
complex, or chained Topology Type. You can define Stub Length Max individually or for all
When available, the actual value for this constraint is displayed in the Actual cell to its right.

environment.

Constraint Type
Modifiable
Related Topics
• “Specifying Topologies for Nets and Constraint Classes” on page 180

Nets
# Vias Max
Defines the maximum number of vias that can be created when routing a net. This constraint
value must be between 1 and 1000. You can define # Vias Max individually or for all nets of a
constraint class.


Constraint Type
Modifiable
Related Topics

Nets
Max Restricted Layer Length External

Defines the maximum trace length that can be routed on external restricted board layers. You
can define Max Restricted Layer Length External individually or for all nets of a constraint
class.
Restricted layers are those that do not have routing enabled through the Route constraint, which
is located on the Trace & Via Properties page of the CES Spreadsheet.
Figure A-31. Cross Section of a 6-Layer PCB (External)
An external layer is a surface layer, either the top or bottom layer of the board. In the above
example, the PCB has two external layers and four internal layers.


Constraint Type
Modifiable
Related Constraints
• “Max Restricted Layer Length Internal” on page 346
Related Topics

Nets
Max Restricted Layer Length Internal

Defines the maximum trace length that can be routed on internal restricted board layers. You
can define Max Restricted Layer Length Internal individually or for all nets of a constraint
class.
Restricted layers are those that do not have routing enabled through the Route constraint, which
is located on the Trace & Via Properties page of the CES Spreadsheet.
Figure A-32. Cross Section of a 6-Layer PCB (Internal)
An internal layer is a non-surface layer, sandwiched somewhere between the top and bottom
board layers. In the above example, the PCB has four internal layers.


Constraint Type
Modifiable
Related Constraints
• “Max Restricted Layer Length External” on page 345
Related Topics

Nets
From To Constraints Layer

Defines the board layer on which to route a from-to for a non-differential net that uses Topology
Type Custom. You can define From To Constraints Layer individually for each from-to that is
part of a non-differential net.
Note
In order to apply this constraint, you must enable from-to rows on the CES Spreadsheet.
To do so, from the Filters menu, click Levels, and then click to enable FromTos.

This constraint is supported during high-speed routing (HSR), and by Hazards in the
AutoActive environment.

Constraint Type
Modifiable
Related Constraints
• “From To Constraints Trace Width” on page 348
Related Topics

Nets
From To Constraints Trace Width

Optionally defines the trace width to which to route a from-to. You can only define this
constraint for non-differential nets that use a custom Topology Type. You also must define
From To Constraints Layer before you can enter a value for this constraint. You can define
From To Constraints Trace Width individually for each from-to.
From To Constraints Trace Width overrides any trace width constraints defined for a net on the
Trace & Via Properties page (for example, Trace Width Typical). When you define From To
Constraints Layer without defining an override width, the trace width constraints of the net class
are used.
Note
In order to apply this constraint, you must enable from-to rows on the CES Spreadsheet.


Constraint Type
Modifiable
Related Constraints
• “From To Constraints Z0” on page 349
Related Topics

Nets
From To Constraints Z0
Displays an impedance calculation based on the trace width override value defined in From To
Constraints Trace Width.
Note
In order to view this constraint, you must enable from-to rows on the CES Spreadsheet.


Constraint Type
Reference
Related Constraints
• “From To Constraints Trace Width” on page 348

Nets
Length or TOF Delay Type

Defines the delay type for a net, which can be controlled electrically (TOF) or physically
(Length). You can define Length or TOF Delay Type individually, for pin pairs, for differential
TOF Delay Type gives you the ability to specify time of flight based upon how long it takes the
signal to propagate through the net. Length Delay Type gives you the ability to set length
constraints that instruct the router to keep the net length within a specific range.


Delays and Lengths, Differential Pair Properties, and All
Constraint Type
Modifiable
Related Constraints
• “Length or TOF Delay Delta” on page 359
• “Length or TOF Delay Max” on page 353
• “Length or TOF Delay Min” on page 351
Related Topics
• “Specifying Delay Rules for Nets” on page 192

Nets
Length or TOF Delay Min

Defines the minimum acceptable physical routing length or signal propagation delay (for
example, time) between design connections. You can define Length or TOF Delay Min
individually, for pin pairs, for differential pairs, or for all nets of a constraint class.
Note
Length tuning in Expedition PCB and BoardStation XE/RE will not work when the
length value exceeds 55 inches. In board configurations with extremely long traces,
ensure that this constraint does not exceed 55 inches.
Figure A-33. Length or TOF Delay Min
Length or TOF Delay Actual Calculations

The actual value for length or TOF delay is displayed in the Actual cell to the right. This value
is taken from the PCB design and will additionally include pin package length actuals and via
delay actuals when they are available. To include via delay actuals, you do so through the Setup
Parameters dialog box of Expedition PCB or BoardStation XE. From the Via Definitions tab,
define via delays using the cells of the Delay row.


Constraint Type
Modifiable

Nets
Related Constraints
• “Length or TOF Delay Max” on page 353
• “Length or TOF Delay Type” on page 350
Related Topics

Nets
Length or TOF Delay Max

Defines the maximum acceptable physical routing length or signal propagation delay (for
example, time) between design connections. You can define Length or TOF Delay Max
individually, for pin pairs, for differential pairs, or for all nets of a constraint class.
Note
Length tuning in Expedition PCB and BoardStation XE/RE will not work when the
length value exceeds 55 inches. In board configurations with extremely long traces,
ensure that this constraint does not exceed 55 inches.
Figure A-34. Length or TOF Delay Max
Length or TOF Delay Actual Calculations

The actual value for length or TOF delay is displayed in the Actual cell to the right. This value
is taken from the PCB design and will additionally include pin package length actuals and via
delay actuals when they are available. To include via delay actuals, you do so through the Setup
Parameters dialog box of Expedition PCB or BoardStation XE. From the Via Definitions tab,
define via delays using the cells of the Delay row.
Manhattan Length
To derive maximum length from the Manhattan length computed during routing, enter a value
between 1 and 100, and follow it with a percentage sign (%). For example, to use 110% of
Manhattan length, enter 10%.


Nets

Constraint Type
Modifiable
Related Constraints
• “Length or TOF Delay Min” on page 351
• “Length or TOF Delay Type” on page 350
Related Topics

Nets
Length or TOF Delay Manhattan

Displays the Manhattan net length. This length is replaced with Length or TOF Delay Actual
when the net is routed.

Delays and Lengths and All
Constraint Type
Reference

Nets
Length or TOF Delay Min Length

Displays the straight line length between two pin pairs when both components are placed. This
length is replaced with Length or TOF Delay Actual when the net is routed.

Constraint Type
Reference
Related Topics

Nets
Length or TOF Delay Match

Defines a match character or string (for example, 1) you can use to group nets for similar length
or time of flight delay routing. You can apply Length or TOF Delay Match individually, for pin
pairs, or for differential pairs.
To duplicate the delay in a net row that has a defined match character, enter the match character
into the Length or TOF Delay Match cell of the net for which you have not defined delay.


Constraint Type
Modifiable
Related Constraints
• “Formulas Formula” on page 361
Related Topics

Nets
Length or TOF Delay Tol

Introduces a tolerance range around the net routing delay requirements for nets that duplicate a
Length or TOF Delay Match (for example, 1). You can also define this constraint at the
constraint class level without the pre-requirement of defining a match character or string.


Constraint Type
Modifiable
Example
5 ns
Related Topics
• “Matching Delay Tolerance at the Constraint Class Level” on page 197

Nets
Length or TOF Delay Delta

Displays estimates for routing results that can be achieved without constraint modification.

Constraint Type
Reference

Nets
Length or TOF Delay Range

Displays the range of length or time of flight actuals for all nets and/or constraint classes that are
part of the same match group.
For example, a value of 3000:5000 indicates that the smallest actual among matched design
objects is 3000; the largest actual is 5000.

Constraint Type
Reference
Related Constraints
• “Length or TOF Delay Match” on page 357

Nets
Formulas Formula
Defines a formula that can be used to create delay relationships between nets and pin pairs. You
can define Formulas Formula individually or for pin pairs.


Constraint Type
Modifiable
Related Constraints
• “Length or TOF Delay Match” on page 357
Related Topics
• “Defining Formulas to Create Net Relationships” on page 199

Nets
Formulas Violation
Displays formula violation information based on the Formulas Formula constraint.


Constraint Type
Reference

Nets
Static Low Overshoot Max

Defines the maximum low DC voltage (minimum) that a buffer can withstand without
permanent damage to the buffer. You can define Static Low Overshoot Max individually, for
differential pairs, or for all nets of a constraint class. This value is defined in an IBIS model
through the S_overshoot_low keyword.
You must enter rail-relative (rr) values, where:
• rr = VLmin – abs for low

• rr = abs – VHmax for high
By defining Dynamic Low Overshoot Max, you can specify an operating voltage limit below
this value. For more information, please refer to “Dynamic Low Overshoot Max” on page 367.
Figure A-35. Static Low Overshoot Max
Note
In order to use this constraint, you must have an Electrical CES license. In order to
calculate the actual value for this constraint, you must be using ICX Pro Verify within
your design flow.

This constraint is supported by Hazards and ICX Pro Verify.

Overshoot/Ringback and All
Constraint Type
Modifiable

Nets
Example
0.3 V
Related Constraints
• “Dynamic High Overshoot Max” on page 369
• “Dynamic Low Overshoot Max” on page 367
• “Static High Overshoot Max” on page 365
Related Topics
• “Defining Overshoot and Ringback Constraints” on page 209

Nets
Static High Overshoot Max

Defines the maximum high DC voltage that a buffer can withstand without permanent damage
to the buffer. You can define Static High Overshoot Max individually, for differential pairs, or
for all nets of a constraint class. This value is defined in an IBIS model through the
S_overshoot_high keyword.

By defining Dynamic High Overshoot Max, you can specify an operating voltage limit above
this value. For more information, please refer to “Dynamic High Overshoot Max” on page 369.
Figure A-36. Static High Overshoot Max
Note
your design flow.


Constraint Type
Modifiable

Nets
Example
0.2 V
Related Constraints
• “Static Low Overshoot Max” on page 363
Related Topics

Nets
Dynamic Low Overshoot Max

Defines an available, smaller low operating voltage (below minimum) limit for the signal that is
to not exceed a specific duration. This voltage limit should not be met or exceeded, but allow for
the signal to go lower than Static Low Overshoot Max, while never equaling Dynamic Low
Overshoot Max. You can define Dynamic Low Overshoot Max individually, or for all nets of a
constraint class. These values are defined in an IBIS model through the D_overshoot_low and

Static Low Overshoot Max defines the standard low operating voltage. Dynamic Low
Overshoot Max give you the ability to define an exception-based low overshoot. This constraint
requires both a time and voltage value, which you separate with a : character.
Figure A-37. Dynamic Low Overshoot Max
Note
your design flow.



Nets
Constraint Type
Modifiable
Example
0.6:5 (0.6 V for 5 ns)
Related Constraints
Related Topics

Nets
Dynamic High Overshoot Max

Defines an available, larger high operating voltage (above maximum) limit for the signal that is
to not exceed a specific duration. This voltage limit should not be met or exceeded, but allow for
the signal to go higher than Static High Overshoot Max, while never equaling Dynamic High
Overshoot Max. You can define Dynamic High Overshoot Max individually, for differential
pairs, or for all nets of a constraint class. These values are defined in an IBIS model through the
D_overshoot_high and D_overshoot_time keywords.

Static High Overshoot Max defines the standard high operating voltage. Dynamic High
Overshoot Max give you the ability to define an exception-based high overshoot. This
constraint requires both a time and voltage value, which you separate with a : character.
Figure A-38. Dynamic High Overshoot Max
Note
your design flow.



Nets
Constraint Type
Modifiable
Example
0.4:5 (0.4 V for 5 ns)
Related Constraints
Related Topics

Nets
Ringback Margin High Min

Defines the minimum allowed difference between the high switching threshold (Vinh) and a
ringback wave. You can define Ringback Margin High Min individually, for differential pairs,
Excessive ringback voltage can cause a device to momentarily switch out of the intended logic
state. When available, the actual value for this constraint is displayed in the Actual cell to its
right.
Note
your design flow.


Constraint Type
Modifiable
Related Topics

Nets
Ringback Margin Low Min

Defines the minimum allowed difference between the low switching threshold (Vinl) and a
ringback wave. You can define Ringback Margin Low Min individually, for differential pairs,
Excessive ringback voltage can cause a device to momentarily switch out of the intended logic
state. When available, the actual value for this constraint is displayed in the Actual cell to its
right.
Note
your design flow.


Constraint Type
Modifiable
Related Topics

Nets
Non-Monotonic Edge
Defines a non-monotonicity requirement for the rising edge, falling edge, or both signal edges.
You can define Non-Monotonic Edge individually, for differential pairs, or for all nets of a
constraint class. For example, when you set Non-Monotonic Edge to Rising, an error is reported
only if the rising signal edge is non-monotonic.
A monotonic signal edge progresses toward the opposite signal state without any digression
back to the original signal state.
Figure A-39. Non-Monotonic Edge
Note
your design flow.


Constraint Type
Modifiable
Related Topics

Nets
Single Ended Characteristic Impedance Value

Defines the single-ended characteristic impedance for net traces. You can define Single Ended
Characteristic Impedance Value individually, for differential pairs, or for all nets of a constraint
class.
When available, the minimum and maximum actual values for this constraint are displayed in
the Actual cells to its right.
When you define this constraint at the differential pair level, and the individual net level for nets
that comprise a differential pair, in the case of a conflict, the value at the differential pair level is
used.

Constraint Type
Modifiable
Related Topics

Nets
Single Ended Characteristic Impedance Tol

Introduces a tolerance range around Single Ended Characteristic Impedance Value. You can
define Single Ended Characteristic Impedance Tol individually, for differential pairs, or for all
For example, a tolerance of 5 ohms allows a Single Ended Characteristic Impedance Value of
40 ohms to tolerate a value between 35 ohms and 45 ohms.

Constraint Type
Modifiable
Related Topics

Nets
Simulation Settings
Defines the simulation settings to use when generating actual values for Nets Spreadsheet
Overshoot/Ringback and Simulated Delays groups. You can define Simulation Settings
individually, for differential pairs, or for all nets of a constraint class.
Both Simulation Stimulus and Simulation Settings affect the generation of actual values.
Note
In order to use this constraint, you must have an Electrical CES license.
Overshoot/Ringback
For Overshoot/Ringback, Simulation Settings and Simulation Stimulus generate actual values
for the following constraints:

• “Ringback Margin High Min” on page 371
• “Ringback Margin Low Min” on page 372
• “Non-Monotonic Edge” on page 373
Simulated Delays
For Simulated Delays, Simulation Settings and Simulation Stimulus generate actual values for
the following constraints:
• “Simulated Delay Min” on page 381

• “Simulated Delay Max” on page 382
• “Simulated Delay Max Range” on page 383
• “Simulated Delay Match” on page 385

This constraint is supported by ICX Pro Verify.

Nets

Overshoot/Ringback, Simulated Delays, and All
Constraint Type
Modifiable
Related Constraints
• “Simulation Stimulus” on page 378
Related Topics
• “Specifying Simulated Delay Rules for Nets” on page 205

Nets
Simulation Stimulus
Defines the simulation stimulus to use when generating actual values for Nets Spreadsheet
Overshoot/Ringback and Simulated Delays groups. You can define Simulation Stimulus
individually, for differential pairs, or for all nets of a constraint class.
Both Simulation Stimulus and Simulation Settings affect the generation of these actual values.
Note


Overshoot/Ringback, Simulated Delays, and All
Constraint Type
Modifiable
Related Constraints
• “Simulation Settings” on page 376
Related Topics

Nets
Simulated Delay Edge

Defines the simulated delay edge to constrain, which controls the switching time between signal
states. You can define Simulated Delay Edge individually, for differential pairs, for pin pairs, or
Figure A-40. Simulated Delay Edge
Note
Simulated Delay Edge can be one of the following signal-edge selections:
• Rise – Constrain the rising time between low and high signal states.
• Fall – Constrain the falling time between high and low signal states.
• Rise:Fall – Constrain both rising and falling times between signal states with unique
minimum and maximum values.
Example: A value of 100:120 in the Simulated Delay Min field constrains the minimum
rising delay to 100, and the minimum falling delay to 120.
• Both – Constrain both rising and falling times, between signal states, with the same
minimum and maximum values.


Simulated Delays and All
Constraint Type
Modifiable

Nets
Related Topics

Nets
Simulated Delay Min

Defines the minimum acceptable simulated delay for the Simulated Delay Edge value (for
example, Rise or Fall). You can define Simulated Delay Min individually, for differential pairs,
for pin pairs, or for all nets of a constraint class.
When Simulated Delay Edge is set to Rise:Fall, separate the rising and falling minimums with a
: character. To use the same minimum value for each switching delay, enter a single value. After
you press Enter, CES completes the constraint value by duplicating the value you entered and
inserting a colon between them.
Note
your design flow.


Constraint Type
Modifiable
Related Constraints
• “Simulated Delay Edge” on page 379
Related Topics

Nets
Simulated Delay Max

Defines the maximum acceptable simulated delay for the Simulated Delay Edge value (for
example, Rise:Fall or Both). You can define Simulated Delay Max individually, for differential
pairs, for pin pairs, or for all nets of a constraint class.
When Simulated Delay Edge is set to Rise:Fall, separate the rising and falling maximums with a
: character. To use the same maximum value for each switching delay, enter a single value.
After you press Enter, CES completes the constraint value by duplicating the value you entered
and inserting a colon between them.
Note
your design flow.


Constraint Type
Modifiable
Related Constraints
Related Topics

Nets
Simulated Delay Max Range

Defines a maximum acceptable range of difference between Simulated Delay Actual Min and
Simulated Delay Actual Max for the Simulated Delay Edge value (for example, Fall or Both).
You can define Simulated Delay Max Range individually, for differential pairs, for pin pairs, or
You can define this constraint with or without defined Simulated Delay Min and Simulated
Delay Max constraints. When Simulated Delay Edge is set to Rise:Fall, separate the rising and
falling maximum ranges with a : character.
Note
your design flow.


Constraint Type
Modifiable
Related Constraints
Related Topics

Nets
Simulated Delay Match To

Defines the hierarchical level of matching for the Simulated Delay Match constraint. You can
match to the constraint class, net, or pin-pair level. You can define Simulated Delay Match To
individually, for differential pairs, for pin pairs, or for all nets of a constraint class.
Note
your design flow.


Constraint Type
Modifiable
Related Constraints
Related Topics

Nets
Simulated Delay Match

Defines the electrical net, pin pair, or constraint class to which to match the Simulated Delay
constraints (for example, Simulated Delay Edge, Simulated Delay Min, and Simulated Delay
Max). You can define Simulated Delay Match individually, for differential pairs, for pin pairs,
When available, the minimum, maximum, and range actual values for this constraint are
displayed in the Actual cells to its right.
When matching a net to a constraint class that has unique Simulated Delay constraints for each
net, the mean of the delay range for nets in the constraint class is used as the matching simulated
delay. For example, a constraint class contains three nets with unique Simulated Delay Min
constraints of 100, 115, and 145. When assigning this constraint class to a net, the average value
of 120 is used for minimum delay.
Note
your design flow.


Constraint Type
Modifiable
Related Constraints
• “Simulated Delay Match To” on page 384
• “Simulated Delay Offset” on page 387
• “Simulated Delay Tol” on page 388

Nets
Related Topics

Nets
Simulated Delay Offset

Introduces a positive or negative offset (for example, 50 ns or -50 ns) from Simulated Delay
Min and Simulated Delay Max when matching the simulated delay of an electrical net or
constraint class (Simulated Delay Match). You can define Simulated Delay Offset individually,
for differential pairs, for pin pairs, or for all nets of a constraint class.
This offset is used for all edge rates constrained through Simulated Delay Edge of the matched
net or constraint class.
Note


Constraint Type
Modifiable
Related Constraints
• “Simulated Delay Tol” on page 388
Related Topics

Nets
Simulated Delay Tol

Introduces a tolerance range (for example, 5 ns) around Simulated Delay Min and Simulated
Delay Max when matching the simulated delay of an electrical net or constraint class
(Simulated Delay Match). You can define Simulated Delay Tol individually, for differential
pairs, for pin pairs, or for all nets of a constraint class.
This tolerance is used for all edge rates constrained through Simulated Delay Edge of the
matched net or constraint class.
Note


Constraint Type
Modifiable
Related Constraints
• “Simulated Delay Offset” on page 387
Related Topics

Nets
Differential Pair Tol Max

Defines the tolerance of the time of flight or length delay between differential pairs. You can
define Differential Pair Tol Max individually for each differential pair.

This constraint is supported during high-speed routing and by Hazards in the AutoActive
environment.

Differential Pair Properties and All
Constraint Type
Modifiable
Example
5 ns
Related Topics

Nets
Convergence Tolerance Max

Defines the maximum allowed difference in trace length from pads to the point where traces
start routing differentially at the Differential Spacing constraint. You can define Convergence
Tolerance Max individually for each differential pair.
Figure A-41. Convergence Tolerance Max

environment.

Constraint Type
Modifiable
Example
500 mil
Related Topics

Nets
Distance to Convergence Max

Defines the maximum distance that differential traces are allowed to route before they converge
as a differential pair. The distance value is the combination of segment lengths. Convergence is
met when traces start routing at the Differential Spacing constraint.You can define Distance to
Convergence Max individually for each differential pair.
Figure A-42. Distance to Convergence Max

environment.

Constraint Type
Modifiable
Example
5000 mil
Related Topics

Nets
Separation Distance Max

Defines the maximum allowed distance that differential traces are allowed to route at a spacing
greater or less than the Differential Spacing constraint. You can define Separation Distance
Max individually for each differential pair.
Figure A-43. Separation Distance Max

environment.

Constraint Type
Modifiable
Example
200 mil
Related Topics

Nets
Differential Spacing
Displays the required parallel distance between trace segments that comprise a differential pair.
When separate spacing values are defined for each board layer, CES displays the values as a
colon-separated list (for example, 5:8).
Figure A-44. Differential Spacing

environment.

Constraint Type
Reference
Example
30 mil
Related Constraints
Related Topics

Nets
Differential Impedance Target

Defines the target differential impedance. You can define this constraint for differential pairs.
When available, the minimum and maximum actual values for this constraint are displayed in
the Actual cells to its right.
When this constraint cannot be met, Differential Spacing is used. Currently, routers do not obey
Differential Impedance Target, but Hazards displays violations.


Constraint Type
Modifiable
Related Constraints
• “Differential Impedance Tolerance” on page 395
Related Topics

Nets
Differential Impedance Tolerance

Introduces a tolerance range around Differential Impedance Target. You can define this
constraint for differential pairs.
When this constraint cannot be met, Differential Spacing is used. For example, to allow a 5 ohm
tolerance range against a Differential Impedance Target value of 25 ohms, enter 5. This
tolerance value specifies an acceptable impedance range of 20 to 30 ohms.


Constraint Type
Modifiable
Related Constraints
• “Differential Impedance Target” on page 394
Related Topics

Nets
I/O Standard
Defines the technology standard for an FPGA signal net. You can define I/O Standard
individually, or for all nets of a constraint class.
In I/O Designer, you can set this constraint through the Signals List or Pins List by modifying
the I/O Standard attribute.
Note
For this version, only I/O Standard is accessible and modifiable through CES. All other

I/O and All
Constraint Type
Modifiable
Example
PCI
Related Topics
• “Modifying I/O Designer FPGA Constraints” on page 211

Parts
Parts
Please refer to the part constraint reference topics that follow. These constraints are accessible
from the CES Spreadsheet Parts page.

Parts
Hierarchical Path
Displays the hierarchical component path, when applicable.
Constraint Type
Reference

Parts
Part Number
Displays the part number for a design component.
Constraint Type
Reference

Parts
Qty
Displays the number of times a part is used throughout your design.
Constraint Type
Reference

Parts
Part Type
Displays the part-type value associated with a design component.
Constraint Type
Reference

Parts
Series
Defines whether a series-class component (for example, resistor) should actually be considered
a series element, and therefore not used for electrical net generation. You can define Series for
parts and part instances.
Tip: You can also modify the series specification for a part instance from the Nets tab of
the CES Spreadsheet. To do so, expand a physical net, right-click a pin instance (for
example, R1-1), and then click Make series or Make non-series. This change affects
only the part instance.
When an extensive electrical net includes other electrical nets that should not stay grouped into
the top-level, extensive electrical net, you can disable the Series checkbox of any
connecting/shared components to separate the electrical nets of interest. A common reason to do
this is when you need to define two electrical nets as a differential pair for the purpose of
constraint definition, but they do not show up as independent electrical nets (or a pre-defined
diff pair) because of their association with the comprehensive electrical net (for example, power
net).
In the following example of a missing differential pair, CES did not recognize a differential pair
that shares a series discrete component. Instead, CES interprets the design methodology of the
net as an electrical net ("^^^"). To change this recognition, you would uncheck the Series
checkbox, and then automatically or manually define the differential pair.
Constraint Type
Modifiable

Parts
IBIS Component Name

Defines the IBIS model used for a part. You can define IBIS Component Name individually, or
for all instances of a part.
IBIS models contain the greatest amount of part detail, including package information for each
pin, and represent parts most accurately. CES uses your design information to assign a default
value to this cell. In most cases it will be correct, though, it is important to understand the
process that CES uses to make the assignment. For more information, please refer to
“Hierarchical Assignment Process” on page 264.
Note
In order to use this constraint, you must have an Electrical CES license. When both IBIS
Component Name and Technology constraints are defined for a part, IBIS Component
Name is used.
Constraint Type
Modifiable
Related Constraints
• “Technology” on page 404
Related Topics
• “Overriding IBIS Values” on page 268

Parts
Technology
Defines the technology model used for a part. You can define Technology individually, or for
all instances of a part.
Because they model parts broadly by technological classification, technology models do not
provide as much detail as IBIS models. A common difference between technology models and
IBIS models is that technology models include information for each pin type, while IBIS
models include information for each pin.
Note
In order to use this constraint, you must have an Electrical CES license. When both IBIS
Component Name and Technology constraints are defined for a part, IBIS Component
Name is used.
Constraint Type
Modifiable
Related Constraints
• “IBIS Component Name” on page 403
Related Topics

Parts
Value
Defines the electrical value associated with a discrete part, which can be resistance, inductance,
or capacitance. You can define Value individually or for all instances of a part.
The Value constraint can be used for two-pin resistors, capacitors, inductors, Thevenin and AC
terminators, and passive modules that contain multiple two-pin slots/gates.
Note
When assigning a Value constraint to a discrete part row, its reference designator (for
example, R, L, or C), must be defined. For more information, please refer to “To Specify
Discrete Component Prefixes” on page 61.
Constraint Type
Modifiable
Related Topics
• “Overriding IBIS Values” on page 268

Parts
IBIS Pin Type

Displays the IBIS pin type for a pin instance.
IBIS Pin Type comes from library information in IBIS Component Name.
Constraint Type
Reference
Related Constraints
• “IBIS Component Name” on page 403

Parts
Schematic Pin Type

Displays the schematic pin type for a pin instance.
Constraint Type
Reference

Parts
Topology Pin Type

Defines the chaining pin type for a pin instance. Chaining pin types are source, load, or
terminator (S, L, or T).

This constraint is supported during high-speed routing and in the AutoActive environment.
Constraint Type
Modifiable

Parts
Pin Package Length

Defines a pin's internal package length between the substrate and dielectric layers of the
component. This constraint is commonly used to define wire bonding length.

Constraint Type
Modifiable
Related Constraints
• “Pin Package Delay” on page 410
Related Topics
• “Importing Pin Package Length Values” on page 269

Parts
Pin Package Delay

Defines a pin's internal package delay between the substrate and dielectric layers of the
component. This constraint is commonly used to define the delay for wire bonding.
Automatically Calculating Pin Package Delay

When used in conjunction with Pin Package Length, you can have CES automatically calculate
Pin Package Delay based on the pin package propagation delay that is defined in your CES
settings. To do so, after you have defined Pin Package Length, right-click within the Pin
Package Delay cell, and then click Calculate Delay. The alternative approach is to define Pin
Package Delay manually.

Constraint Type
Modifiable
Related Constraints
• “Pin Package Length” on page 409
Related Topics
• “To Set Design Configuration Preferences” on page 59

Parts
Thermal Power Dissipation

Defines a part’s power dissipation as a subset of the total amount of power needed to run the
component.
Constraint Type
Modifiable
Example
1W
Related Topics
“Defining Thermal Constraints for Parts” on page 268

Parts
Thermal Power Scaling Factor

Defines a part instance’s scaling factor with regard to power dissipation.
Constraint Type
Modifiable
Example
1
Related Topics

Parts
Thermal Theta-jc
Defines a part’s junction-to-casing thermal resistance. This is also commonly referred to as die-
to-package heat resistance.
Constraint Type
Modifiable
Example
7 degC/watt
Related Topics

Parts
Thermal Casing Temperature Limit

Defines a part’s maximum allowable temperature for the component casing or package.
Constraint Type
Modifiable
Example
60 degC
Related Topics

Parts
Thermal Junction Temperature Limit

Defines a part’s maximum allowable temperature for component junctions. A component
junction is also commonly referred to as a die.
Constraint Type
Modifiable
Example
70 degC
Related Topics

Parts
I/O Standard
Displays the defined technology standard for an FPGA signal net. When on the CES
Spreadsheet Nets page, you can define I/O Standard individually, or for all nets of a constraint
class.
In I/O Designer, you can set this constraint through the Signals List or Pins List by modifying
the I/O Standard attribute.
Note
For this version, only I/O Standard is accessible and modifiable through CES. All other
Constraint Type
Reference
Example
PCI
Related Topics
• “Modifying I/O Designer FPGA Constraints” on page 211

Noise Rules
Noise Rules
Please refer to the noise rule constraint reference topics that follow. These constraints are
accessible from the CES Spreadsheet Noise Rules page.

Noise Rules
Noise Type
Defines the noise type for a specific parallelism rule and/or Crosstalk Max constraint and
Crosstalk Level.
Noise Type can be either net-to-net or class-to-class.

environment.
Constraint Type
Modifiable
Related Constraints
Related Topics
• “Assigning Parallelism Rules to Nets and Constraint Classes” on page 218
• “Defining Crosstalk Rules for Nets and Constraint Classes” on page 221

Noise Rules
Constraint Class or Electrical Net Name Victim

Defines the victim constraint class or electrical net of the aggressor-victim relationship.
You can use these relationships to define both crosstalk and parallelism rules.

environment.
Constraint Type
Modifiable
Related Constraints
• “Crosstalk Level” on page 425
• “Crosstalk Max” on page 422
• “Parallelism Rule” on page 421
Related Topics

Noise Rules
Constraint Class or Electrical Net Name Aggressor

Defines the aggressor constraint class or electrical net of the aggressor-victim relationship.
You can use these relationships to define both crosstalk and parallelism rules.

environment.
Constraint Type
Modifiable
Related Constraints
• “Parallelism Rule” on page 421
Related Topics

Noise Rules
Parallelism Rule
Defines the parallelism rule for a class-to-class or net-to-net parallelism relationship.
The Parallelism Rule constraint can be one of the parallelism rules you defined previously. You
can also create a new parallelism rule by selecting New in the cell for this constraint.

environment.
Constraint Type
Modifiable
Related Topics

Noise Rules
Crosstalk Max
Defines the maximum acceptable crosstalk that a net or all nets within a constraint class can be
subjected to as victim nets. You can define Crosstalk Max individually or for all nets of a
constraint class.
Crosstalk results when another net (aggressor) causes electromagnetic interference on a victim
net. In the following illustration, the electromagnetic field produced by net A is strong enough
to interfere with net B.
Figure A-45. Crosstalk Max
In the CES Spreadsheet, you define aggressor nets using Constraint Class or Electrical Net
Name Aggressor. You define victim nets using Constraint Class or Electrical Net Name Victim.
Note
In order to calculate the simulation actual for this constraint, you must be using ICX Pro
Verify within your design flow.

environment.
Constraint Type
Modifiable
Related Constraints
• “Constraint Class or Electrical Net Name Aggressor” on page 420
• “Constraint Class or Electrical Net Name Victim” on page 419

Noise Rules
Related Topics

Noise Rules
Crosstalk Sim Actual

Displays the actual value for Crosstalk Max based on ICX Pro Verify calculations.
Note
In order to calculate this actual value, you must be using ICX Pro Verify within your
design flow.
Constraint Type
Reference
Related Constraints

Noise Rules
Crosstalk Level
Defines the signal state of the victim net in a crosstalk relationship.
You can define Crosstalk Level using one of the following choices:
• High & Low – Require Crosstalk Max to be met for both high and low signal states.
• High – The victim net is on (in its high state). The voltage level is at or above the high
• Low – The victim net is off (in its low state). The voltage level is at or below the low
• Tristate – Require Crosstalk Max to be met for just tristate signal states. During tristate,
the victim net is off, but a small voltage still flows from the receiver to ground (for
example, 0.5 V).
• High & Tristate – Require Crosstalk Max to be met for both high and tristate signal
states. During tristate, the victim net is off, but a small voltage still flows from the
receiver to ground (for example, 0.5 V).
• Low & Tristate – Require Crosstalk Max to be met for both low and tristate signal states.
During tristate, the victim net is off, but a small voltage still flows from the receiver to
ground (for example, 0.5 V).
• All – Require Crosstalk Max to be met for all signal states.
Constraint Type
Modifiable
Related Constraints
• “Constraint Class or Electrical Net Name Aggressor” on page 420
• “Constraint Class or Electrical Net Name Victim” on page 419
Related Topics

Noise Rules

Appendix B
CES Command-Line Tools Reference
This section provides you with reference documentation for command-line tools that are
available with CES. Please refer to the table of contents for the full listing of documented
commands.

cons2ascii
cons2ascii
Used to export CES data in the encrypted ASCII format (.cs_).
Usage
cons2ascii -export -outputdir <path> -cns <.cns file> -prj <.prj file> -snapshot <name> -
topblock <name>
Arguments
• -export
Export switch.
• -outputdir <path>
Directory in which to place the exported constraint file.
• -cns <.cns file>
.cns file to use.
• -prj <.prj file>
.prj file for the design.
• -snapshot <name>
Snapshot name.
• -topblock <name>
Topblock name.
Description
This command exports the entire constraint set in encrypted ASCII format (.cs_). All arguments
for this command are required.
Tip: To determine the path to the iCDB database, snapshot name, topblock name, and
other similar information, you can use iCDB Server Manager. To access it, from the
Tools menu, click iCDB Server Manager.
Example
cons2ascii -export -outputdir c:\OutDir -cns
c:\ee7.9.4\7.9.4EE\SDD_HOME\standard\ce_ee.cn
-prj c:\design\design.prj -snapshot DxD -topblock top
Related Topics
“Exporting Constraints in Encrypted ASCII “Decrypting and Encrypting Exported
Format” on page 244 Constraint Data” on page 244

cons2csv
cons2csv
Used to export and import CES data in the encrypted CSV format (.ecsv).
Note
Encrypted CSV import is controlled release functionality. You must have a special
license to use this functionality. Import is only supported in the EE flow.
Export Usage
cons2csv -export -pages -output <file> -prj <prj file> -snapshot <name>
-topblock <name> -noverify
Import Usage
cons2csv -import -input <file> -prj <prj file> -snapshot <name> -topblock <name>
Arguments
• -export
Export switch.
• -import
Import switch.
• -output <file>
Used only with the export switch. Directory and filename of exported constraint file(s).
When using the pages switch, this argument defines the suffix to be used for each file. When
you do not use the pages switch, you should enter this argument as the full filename (for
example, c:\output\alltables.ecsv).
• -input <file>
Used only with the import switch. Directory and filename of the .ecsv file to import or
process.
• -prj <prj file>
Directory and filename of .prj file.
• -snapshot <name>
Snapshot name.
• -topblock <name>
Top block name.
• -pages
Used with the export switch to create a separate .ecsv file for each table.

cons2csv
• -noverify
Used with the export switch to skip the CES Diagnostics run that happens automatically
before export.
Description
This command exports and imports constraint data in the encrypted CSV file format (.ecsv).
When exporting, you can choose to export all constraint data to a single file, or multiple files.
Tip: To determine the path to the .prj file, snapshot name, topblock name, and other
similar information, you can use iCDB Server Manager. To access it, from the Tools
menu, click iCDB Server Manager.
Export Example
cons2csv -export -pages -output c:\data\tables -prj .\design.prj
-snapshot DXD -topblock Schematic1
Import Example
cons2csv -import -input c:\data\tables_Class2ClassClear.ecsv
-prj .\design.prj -snapshot DXD -topblock Schematic1
Related Topics
“Exporting Constraints in Encrypted CSV “Importing Constraints in Encrypted CSV
Format” on page 243 Format” on page 246
“Decrypting and Encrypting Exported “Example CSV Files” on page 250
“Guidelines for CSV Files” on page 253

cons2xml
cons2xml
Used to export and import CES data in the proprietary encrypted XML format (.cts). You can
also list detailed information about an iCDB database using this command.
Export Usage
cons2xml -export -output <path> -icdb <path> -sn <snapshot> -tb <topblock> -log <path>
-constempl | -pages <list>
Import Usage
cons2xml -import -input <path> -icdb <path> -sn <snapshot> -tb <topblock> -log <path>
List Usage
cons2xml -list -icdb <path>
Arguments
• -export
Export switch.
• -import
Import switch.
• -list
List switch. Provides detailed information about the iCDB database (for example, snapshot
names and block names).
• -output <path>
Used only with the export switch. Directory in which to place the exported constraint file.
• -input <path>
Used only with the import switch. Directory and filename of the .cts file to import.
• -icdb <path>
Path to the iCDB database.
• -sn <snapshot>
Snapshot name.
• -tb <topblock>
Top block name.
• -log <path>
Path to optional log file that can be created during import or export.
• -constempl | -pages <list>
Used with the export switch. Optionally, output just constraint template information or just
certain constraint information based on the following list of all available pages/constraint

cons2xml
data: CLASS_CLASS_RULE, CLASS_CLASS_ZAXIS_RULE, CLEARRULES,

CONSTANTS, CUSTOM_TAB, DESIGN, ENET, GENCLEARANCES,
GEN_OBJ_TYPE, LAYER, MATCHGROUPS, NETCLASSES, PARALLEL_RULE,
PARRULEDEFS, PART, PKGTYPERULES, PKGTYPE_PKGTYPE_RULE, PNET,
SCHEMES, SCHEME_CLASS_LAYER, SCHEME_RULE_LAYER,
SHARED_RESOURCES, TESTPOINT_SCHEME, TOPOTMPL, VARIABLES, VIAS,
VIASPANS, ZAXIS_CLEARRULE
Description
This command exports and imports constraint data in the proprietary encrypted XML (.cts)
format. You can also use it to list detailed information about an iCDB database (that you could
then use with the import or export functions of this command). When exporting, you can choose
which constraints/pages to include in the output file. When importing, all constraint data that
you exported to the file is imported back into CES.
Export Example
cons2xml -export -output c:\output\file.cts -icdb c:\mydesign\database
-sn Snapshot1 -tb Microtop -log c:\output\file_log.txt -pages ENET,PART
Import Example
cons2xml -import -input c:\files\file.cts -icdb c:\mydesign\database
-sn Snapshot1 -tb Microtop -log c:\files\file_log.txt
List Example
cons2xml -list -icdb c:\mydesign\database
Related Topics
“Exporting Constraints in Encrypted XML “Importing CES Constraints” on page 245

csv2dat
csv2dat
Used to decrypt and encrypt data files exported from CES in the encrypted ASCII (.cs_) format
and encrypted CSV (.ecsv) format. You also use this command to encrypt CSV files that you
create from scratch.
Prerequisites
• You must have a CES Encryption license. You can request this license free of charge
from the PCB Community: http://communities.mentor.com/mgcx/docs/DOC-2533
Usage
csv2dat -decrypt | encrypt -input <path> -output <path>
Arguments
• -decrypt | encrypt
Specifies whether you are decrypting or encrypting data.
• -input <path>
The path and filename of the file you want to process.
• -output <path>
The path and filename of the output file you want to produce.
Description
This command encrypts or decrypts a single file at a time by reading and writing the encrypted
ASCII format or encrypted CSV format.
Examples
csv2dat -decrypt -input C:\Files\design1_nets.cs_
-output C:\Files\design1_nets.txt
csv2dat -encrypt -input C:\Files\data.csv -output C:\Files\data.ecsv
csv2dat -encrypt -input C:\Files\design1_nets.txt

-output C:\Files\design1_nets.cs_
Related Topics
“Decrypting and Encrypting Exported

ImportPinPackageLength
Used to import values from a PinPkgLengths.txt side file.
Usage
ImportPinPackageLength -icdb <path> -sn <name> -tb <name> -ppl <path> -offline
-zero_ppl -log <path>
Arguments
• -icdb <path>
Path to the iCDB database.
• -sn <name>
Snapshot name.
• -tb <name>
Topblock name.
• -ppl <path>
Path to a PinPkgLengths.txt side file
• -offline
Run import without an iCDB server.
• -zero_ppl
Sets values to 0 for any pin package lengths that are not specified in the side file. This only
applies to pins of part numbers defined in the side file. Otherwise, the existing values in
CES are kept, when defined.
• -log <path>
Creates a log file at the specified path.
Description
This command imports CES Parts page Pin Package Length constraint values from a side file
that you previously created or acquired. When a part number included in a side file is missing
definitions for one or more pins, you can use the zero_ppl switch to set Pin Package Length to
zero for those pins.
Example
ImportPinPackageLength -icdb c:\micro_design\database -sn micro -tb top -
ppl c:\data\PinPkgLengths.txt

Related Topics
“Importing Pin Package Length Values” on “Example PinPkgLengths.txt File” on
page 269 page 271
“Pin Package Length” on page 409


A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Index
Templates, 231
Index
— Symbols — Constraint class

(Minimum) scheme, 153 Add nets, 147
# Pins, 334 Auto bus, 148
# Vias Max, 344 Copy, 151
— Numerics — Create, 145
2-pin, 62 Delete, 151
Hierarchy, 145
—A— Rename, 147
Analog, 335 Constraint Class or Electrical Net Name
Assigning, 168 Aggressor, 420
Auto bus, 148 Constraint Class or Electrical Net Name
Victim, 419
—B— Constraint Editor System (CES), 47
Back-end, 281
Constraint quick-reference, 28
Before you begin, 49
Constraint Reference, 289
Board Architect, 48
Constraint template
Board Station RE, 48
Apply, 233
Board Station XE, 48
Convergence Tolerance Max, 390
Board Station XE Design Flow
Cross probing, 58
CES synchronization, 282
Cross select, 58
Bus, 336
Crosstalk Level, 425
Bus constraint classes, 148
Crosstalk Max, 422
—C— Crosstalk rules, 221
Capture net constraints, 231 Crosstalk Sim Actual, 424
CES, 47 Customization, 79
Clearance rule sets
—D—
Assign, 165 Default
Create, 158 Rules, 177
Clearances, 302 Tolerances, 59
Colors, 65 Delay
Command quick-reference, 14 Calculations, 194
Commands, 14 Default value, 194
Component pin pairs, 188 Rules, 192
Concurrent design, 48 Delete
Constraint Constraint class, 151
Classes, 145 Net class, 143
Data, 99 Rule-area scheme, 177
Groups, 118 Design

Preferences, 59 Export
Reuse, 239 Constraint Templates, 239
Setup, 59 Constraints, 241, 244
Design Architect, 48
Design Capture, 48 —F—
Design-flow manuals, 281 Filters, 115, 118
DesignView, 48 Find, 113
Diff Pair Spacing, 301 Fonts, 65
Differential Impedance Target, 394 Formulas, 199
Differential Impedance Tolerance, 395 Formulas Formula, 361
Differential pair Formulas Violation, 362
Assign rules, 227 FPGA constraints, 211
Define automatically, 224 From To Constraints Layer, 347
Define manually, 223 From To Constraints Trace Width, 348
Delete, 224 From To Constraints Z0, 349
Diff_Pin, 227 From-tos, 180
Differential Spacing, 393 Front-end, 47
Discrete component prefixes, 61 —G—
Discrete pin pairs, 188 General
Display Clearance rules, 174
Settings, 59 Options, 59
Units, 66 Preferences, 59
Distance to Convergence Max, 391 Global rules, 153
DxDesigner, 47 Ground nets, 62
Dynamic High Overshoot Max, 369 GUI quick-reference, 20
Dynamic Low Overshoot Max, 367
Dynamic overshoot, 211 —I—
I/O Designer I/O Standard, 396, 416
—E— IBIS Component Name, 403
EBD pin pairs, 190 IBIS Pin Type, 406
Electrical Icons, 106
Preferences, 60 ICX Pro Explorer, 275
Rules, 145 Import constraints, 245
Units, 68 Improve design accuracy, 47
Embedded Resistor to Pad, 318 Index (Clearances), 303
Embedded Resistor to Resistor, 320 Index (Trace and Via Properties), 292
Embedded Resistor to Trace, 317 Index (Z-Axis Clearances), 326
Embedded Resistor to Via, 319 Intellectual property, 47
Embedded resistors, 163 Interdigitated capacitors, 164
Engineering format, 69 Interface quick-reference, 20
EP Mask to Pad, 322
EP Mask to Resistor, 324 —K—
EP Mask to Trace, 321 Keyin netlist, 48
EP Mask to Via, 323
Exit, 57 —L—
Layout, 281
Expedition PCB, 47

Length or TOF Delay Delta, 359 Parallelism, 215

Length or TOF Delay Manhattan, 355 Parallelism mode, 59
Length or TOF Delay Match, 357 Parallelism Rule, 421
Length or TOF Delay Max, 353 Parallelism rules, 216
Length or TOF Delay Min, 351 Assign, 218
Length or TOF Delay Min Length, 356 Parallelism rules hierarchy, 215
Length or TOF Delay Range, 360 Part Number, 399
Length or TOF Delay Tol, 358 Part Type, 401
Length or TOF Delay Type, 350 Parts, 397
Libraries, 232 PCB, 47
Pin Package Length, 409
—M— Pin pairs, 180
Manhattan length, 193 Plane to Plane, 316
Mask, 165 Power nets, 62, 142
Matching delay, 195 Precision, 67
Max Restricted Layer Length External, 345 Production mask, 165
Max Restricted Layer Length Internal, 346
Mezzanine capacitors, 164 —Q—
Monotonic Edge, 373 Qty, 400
Multiple loads, 180
—R—
—N— Reuse, 239
Navigator, 80 Ringback, 209
Net Class, 337, 338, 339 Ringback Margin High Min, 371
Net class Ringback Margin Low Min, 372
Add nets, 141 Roll back, 135
Copy, 142 Route, 295
Create, 139 Rule-area schemes, 153
Delete, 143 Rules, 215
Hierarchy, 139
Power nets, 142 —S—
Rename, 141 Same constraints
Net line ordering, 180 Electrical rules, 151
Nets, 332 Physical rules, 142
Noise Rules, 417 Save, 137
Noise Type, 418 Schematic, 281
Notation, 68 Schematic Pin Type, 407
Screen-printed capacitors, 164
—O— Search, 113
Options, 59 Separation Distance Max, 392
Output, 80 Series, 402
Overshoot, 209 Settings, 59
Signal edge rates, 205
—P— Signal integrity exploration, 275
Pad to Plane, 312 Simulated Delay Edge, 379
Pad to Via, 311 Simulated Delay Match, 385
Pair Tol Max, 389

Simulated Delay Match To, 384 Trace Width Minimum, 296

Simulated Delay Max, 382 Trace Width Typical, 297
Simulated Delay Max Range, 383 Type, 293, 304
Simulated Delay Min, 381 Typical Impedance, 299
Simulated Delay Offset, 387
Simulated delay rules, 205 —U—
Simulated Delay Tol, 388 Units, 66
Simulation options, 71 User interface quick reference, 20
Simulation Settings, 376 —V—
Simulation Stimulus, 378 Validate constraints, 128
Single Ended Characteristic Impedance Tol, Value, 405
375 Via Assignments, 294
Single Ended Characteristic Impedance Value, Via rules, 154
374 Via to Plane, 314
SMD Pad to Trace, 309, 331 Via to Via, 313
SMD Pad to Via, 315
Spreadsheet icons, 106 —W—
Spreadsheet pages, 104 Window customization, 79
Stackup, 259
Stackup layers, 216 —Z—
Z-axis clearance rule sets
Start CES, 56
Assign, 168
Static High Overshoot Max, 365
Create, 158
Static Low Overshoot Max, 363
Z-Axis Clearances, 325
Static overshoot, 209
Status Bar, 80
Stub Length Max, 343
—T—
Technology, 404
Thermal Casing Temperature Limit, 414
Thermal Junction Temperature Limit, 415
Thermal Power Dissipation, 411
Thermal Power Scaling Factor, 412
Thermal Theta-jc, 413
Thick-film resistors, 163
Thin-film resistors, 163
Toolbars, 80
Topology Ordered, 342
Topology Pin Type, 408
Topology Type, 340
Trace and Via Properties, 291
Trace and via rules, 154
Trace to Plane, 308, 330
Trace to Trace, 305, 327
Trace to Via, 307, 329
Trace Width Expansion, 298

End-User License Agreement
The latest version of the End-User License Agreement is available on-line at:
www.mentor.com/eula
IMPORTANT INFORMATION
USE OF ALL SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS. CAREFULLY READ THIS LICENSE
AGREEMENT BEFORE USING THE PRODUCTS. USE OF SOFTWARE INDICATES CUSTOMER’S
COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN
THIS AGREEMENT. ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS AND CONDITIONS
SHALL NOT APPLY.
END-USER LICENSE AGREEMENT (“Agreement”)
This is a legal agreement concerning the use of Software (as defined in Section 2) and hardware (collectively “Products”)
between the company acquiring the Products (“Customer”), and the Mentor Graphics entity that issued the
corresponding quotation or, if no quotation was issued, the applicable local Mentor Graphics entity (“Mentor
Graphics”). Except for license agreements related to the subject matter of this license agreement which are physically
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Rev. 100615, Part No. 246066

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Constraint Editor System™ (CES) User’s

Software Version EE 7.9.4

© 2004-2012 Mentor Graphics Corporation

RESTRICTED RIGHTS LEGEND 03/97

Constraint Editor System (CES) Users Manual, EE 7.9.4 3

Automatically Recognized Topologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4 Constraint Editor System (CES) Users Manual, EE 7.9.4

Filtering Spreadsheet Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Constraint Editor System (CES) Users Manual, EE 7.9.4 5

Specifying Trace and Via Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

6 Constraint Editor System (CES) Users Manual, EE 7.9.4

Constraint Editor System (CES) Users Manual, EE 7.9.4 7

8 Constraint Editor System (CES) Users Manual, EE 7.9.4

Trace Width Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Constraint Editor System (CES) Users Manual, EE 7.9.4 9

Max Restricted Layer Length Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

10 Constraint Editor System (CES) Users Manual, EE 7.9.4

Constraint Editor System (CES) Users Manual, EE 7.9.4 11

12 Constraint Editor System (CES) Users Manual, EE 7.9.4

Figure 1-1. Constraint Editor System (CES) Quick Help

Constraint Editor System (CES) Users Manual, EE 7.9.4 13

Quick Reference - CES Commands

Table 1-1. CES Commands

14 Constraint Editor System (CES) Users Manual, EE 7.9.4

Table 1-1. CES Commands (cont.)

Constraint Editor System (CES) Users Manual, EE 7.9.4 15

Table 1-1. CES Commands (cont.)

16 Constraint Editor System (CES) Users Manual, EE 7.9.4

Table 1-1. CES Commands (cont.)

Constraint Editor System (CES) Users Manual, EE 7.9.4 17

Table 1-1. CES Commands (cont.)

18 Constraint Editor System (CES) Users Manual, EE 7.9.4

Table 1-1. CES Commands (cont.)

Constraint Editor System (CES) Users Manual, EE 7.9.4 19

Quick Reference - CES GUI

Table 1-2. File Menu Selections

20 Constraint Editor System (CES) Users Manual, EE 7.9.4

Table 1-2. File Menu Selections (cont.)

Table 1-3. Edit Menu Selections

Constraint Editor System (CES) Users Manual, EE 7.9.4 21

Table 1-3. Edit Menu Selections (cont.)

22 Constraint Editor System (CES) Users Manual, EE 7.9.4

Table 1-3. Edit Menu Selections (cont.)

Table 1-4. View Menu Selections

Constraint Editor System (CES) Users Manual, EE 7.9.4 23

Table 1-4. View Menu Selections (cont.)

Table 1-6. Filters Menu Selections

24 Constraint Editor System (CES) Users Manual, EE 7.9.4

Table 1-7. Tools Menu Selections

Table 1-8. Data Menu Selections

Constraint Editor System (CES) Users Manual, EE 7.9.4 25

Table 1-8. Data Menu Selections (cont.)

Table 1-9. Output Menu Selections

26 Constraint Editor System (CES) Users Manual, EE 7.9.4

Table 1-9. Output Menu Selections (cont.)

Constraint Editor System (CES) Users Manual, EE 7.9.4 27

Quick Reference - CES Constraint Spreadsheet

CES Constraint Spreadsheet Pages

• “Trace and Via Properties Summary” on page 28