Datasheet IC 4051B

CD4051B, CD4052B, CD4053B
Data sheet acquired from Harris Semiconductor August 1998 - Revised October 2003
SCHS047G
Features The CD4051B is a single 8-Channel multiplexer having three

binary control inputs, A, B, and C, and an inhibit input. The
• Wide Range of Digital and Analog Signal Levels three binary signals select 1 of 8 channels to be turned on,
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V and connect one of the 8 inputs to the output.
- Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20VP-P
The CD4052B is a differential 4-Channel multiplexer having
[ /Title • Low ON Resistance, 125Ω (Typ) Over 15VP-P Signal Input two binary control inputs, A and B, and an inhibit input. The
Range for VDD -VEE = 18V
(CD405 two binary input signals select 1 of 4 pairs of channels to be
1B, • High OFF Resistance, Channel Leakage of ±100pA (Typ) turned on and connect the analog inputs to the outputs.
CD4052 at VDD -VEE = 18V The CD4053B is a triple 2-Channel multiplexer having three
B, • Logic-Level Conversion for Digital Addressing Signals of separate digital control inputs, A, B, and C, and an inhibit
CD4053 3V to 20V (VDD -VSS = 3V to 20V) to Switch Analog
Signals to 20VP-P (VDD -VEE = 20V)
input. Each control input selects one of a pair of channels
which are connected in a single-pole, double-throw
B)
• Matched Switch Characteristics, rON = 5Ω (Typ) for configuration.
/Sub- VDD -VEE = 15V
ject When these devices are used as demultiplexers, the
(CMOS • Very Low Quiescent Power Dissipation Under All Digital-
Control Input and Supply Conditions, 0.2µW (Typ) at
“CHANNEL IN/OUT” terminals are the outputs and the
“COMMON OUT/IN” terminals are the inputs.
Analog VDD -VSS = VDD -VEE = 10V
Multi- Ordering Information
• Binary Address Decoding on Chip
plex- TEMP. RANGE
ers/Dem • 5V, 10V, and 15V Parametric Ratings PART NUMBER (oC) PACKAGE
ultiplex- • 100% Tested for Quiescent Current at 20V CD4051BF3A, CD4052BF3A, -55 to 125 16 Ld CERAMIC
ers with • Maximum Input Current of 1µA at 18V Over Full Package CD4053BF3A DIP
Logic Temperature Range, 100nA at 18V and 25oC CD4051BE, CD4052BE, -55 to 125 16 Ld PDIP
CD4053BE
Level • Break-Before-Make Switching Eliminates Channel
Overlap CD4051BM, CD4051BMT, -55 to 125 16 Ld SOIC
Conver- CD4051BM96
sion) CD4052BM, CD4052BMT,
/Author Applications CD4052BM96
CD4053BM, CD4053BMT,
() • Analog and Digital Multiplexing and Demultiplexing CD4053BM96
/Key- • A/D and D/A Conversion CD4051BNSR, CD4052BNSR, -55 to 125 16 Ld SOP
words • Signal Gating
CD4053BNSR
(Harris CD4051BPW, CD4051BPWR, -55 to 125 16 Ld TSSOP

Semi- CMOS Analog Multiplexers/Demultiplexers CD4052BPW, CD4052BPWR
CD4053BPW, CD4053BPWR
conduc- with Logic Level Conversion
tor, The CD4051B, CD4052B, and CD4053B analog multiplexers NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
CD4000 are digitally-controlled analog switches having low ON reel of 250.
impedance and very low OFF leakage current. Control of
analog signals up to 20VP-P can be achieved by digital
signal amplitudes of 4.5V to 20V (if VDD -VSS = 3V, a
VDD -VEE of up to 13V can be controlled; for VDD -VEE level
differences above 13V, a VDD -VSS of at least 4.5V is
required). For example, if VDD = +4.5V, VSS = 0V, and
VEE = -13.5V, analog signals from -13.5V to +4.5V can be
controlled by digital inputs of 0V to 5V. These multiplexer
circuits dissipate extremely low quiescent power over the
full VDD -VSS and VDD -VEE supply-voltage ranges,
independent of the logic state of the control signals. When
a logic “1” is present at the inhibit input terminal, all
channels are off.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD4051B, CD4052B, CD4053B
Pinouts
CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP) CD4052B (PDIP, CDIP, SOP, TSSOP)
TOP VIEW TOP VIEW
CHANNELS 4 1 16 VDD Y CHANNELS 0 1 16 VDD

IN/OUT IN/OUT
6 2 15 2 2 2 15 2 X CHANNELS
COM OUT/IN 3 14 1 COMMON “Y” OUT/IN 3 14 1 IN/OUT
CHANNELS IN/OUT
CHANNELS 7 4 13 0 Y CHANNELS 3 4 13 COMMON “X” OUT/IN
IN/OUT IN/OUT
5 5 12 3 1 5 12 0 X CHANNELS
INH 6 11 A INH 6 11 3 IN/OUT
VEE 7 10 B VEE 7 10 A
VSS 8 9 C VSS 8 9 B
CD4053B (PDIP, CDIP, SOP, TSSOP)

TOP VIEW
by 1 16 VDD
IN/OUT bx 2 15 OUT/IN bx OR by
cy 3 14 OUT/IN ax OR ay
OUT/IN CX OR CY 4 13 ay
IN/OUT
IN/OUT CX 5 12 ax
INH 6 11 A
VEE 7 10 B
VSS 8 9 C
Functional Block Diagrams

CD4051B
CHANNEL IN/OUT
7 6 5 4 3 2 1 0
16 VDD 4 2 5 1 12 15 14 13
TG
TG
A † 11
TG
COMMON
TG OUT/IN
B † 10 BINARY
LOGIC TO 3
1 OF 8
LEVEL TG
DECODER
CONVERSION WITH
C † 9 INHIBIT TG
TG
INH † 6
TG
8 VSS 7 VEE
† All inputs are protected by standard CMOS protection network.
2
CD4051B, CD4052B, CD4053B
Functional Block Diagrams (Continued)

CD4052B
X CHANNELS IN/OUT
3 2 1 0
11 15 14 12
TG
16 VDD
TG
TG COMMON X
OUT/IN
TG 13
A † 10
BINARY
TG 3
LOGIC TO
B † 9 1 OF 4 COMMON Y
LEVEL
DECODER OUT/IN
CONVERSION TG
WITH
INH † 6 INHIBIT
TG
TG
1 5 2 4
0 1 2 3
8 VSS 7 VEE
Y CHANNELS IN/OUT
CD4053B
BINARY TO
1 OF 2 IN/OUT
LOGIC DECODERS
LEVEL 16 VDD WITH
CONVERSION INHIBIT cy cx by bx ay ax
3 5 1 2 13 12
COMMON
OUT/IN
TG ax OR ay
14
A † 11 TG
COMMON
OUT/IN
TG bx OR by
15
B † 10
TG
COMMON
OUT/IN
TG cx OR cy
C † 9
4
TG
INH † 6
VDD
8 VSS 7 VEE
† All inputs are protected by standard CMOS protection network.
3
CD4051B, CD4052B, CD4053B
TRUTH TABLES
INPUT STATES
INHIBIT C B A “ON” CHANNEL(S)
CD4051B
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 X X X None
CD4052B
INHIBIT B A
0 0 0 0x, 0y
0 0 1 1x, 1y
0 1 0 2x, 2y
0 1 1 3x, 3y
1 X X None
CD4053B
INHIBIT A OR B OR C
0 0 ax or bx or cx
0 1 ay or by or cy
1 X None
X = Don’t Care
4
CD4051B, CD4052B, CD4053B
Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to V-) Package Thermal Impedance, θJA (see Note 1):
Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V E (PDIP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V M (SOIC) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA NS (SOP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) package . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Operating Conditions Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1,
RL = 100Ω, Unless Otherwise Specified (Note 3)
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)

25
PARAMETER VIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125 MIN TYP MAX UNITS
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
Quiescent Device - - - 5 5 5 150 150 - 0.04 5 µA

Current, IDD Max
- - - 10 10 10 300 300 - 0.04 10 µA
- - - 15 20 20 600 600 - 0.04 20 µA
- - - 20 100 100 3000 3000 - 0.08 100 µA
Drain to Source ON - 0 0 5 800 850 1200 1300 - 470 1050 Ω

Resistance rON Max
- 0 0 10 310 330 520 550 - 180 400 Ω
0 ≤ VIS ≤ VDD
- 0 0 15 200 210 300 320 - 125 240 Ω
Change in ON - 0 0 5 - - - - - 15 - Ω
Resistance (Between
- 0 0 10 - - - - - 10 - Ω
Any Two Channels),
∆rON - 0 0 15 - - - - - 5 - Ω
OFF Channel Leakage - 0 0 18 ±100 (Note 2) ±1000 (Note 2) - ±0.01 ±100 nA

Current: Any Channel (Note 2)
OFF (Max) or ALL
Channels OFF (Common
OUT/IN) (Max)
Capacitance: - -5 5- 5
Input, CIS - - - - - 5 - pF
Output, COS
CD4051 - - - - - 30 - pF
CD4052 - - - - - 18 - pF
CD4053 - - - - - 9 - pF
Feedthrough
CIOS - - - - - 0.2 - pF
Propagation Delay Time VDD RL = 200kΩ, 5 - - - - - 30 60 ns

(Signal Input to Output CL = 50pF,
10 - - - - - 15 30 ns
tr , tf = 20ns
15 - - - - - 10 20 ns
5
CD4051B, CD4052B, CD4053B
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1,
RL = 100Ω, Unless Otherwise Specified (Continued) (Note 3)
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)

25
PARAMETER VIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125 MIN TYP MAX UNITS
CONTROL (ADDRESS OR INHIBIT), VC
Input Low Voltage, VIL , VIL = VDD VEE = VSS , 5 1.5 1.5 1.5 1.5 - - 1.5 V
Max through RL = 1kΩ to VSS ,
10 3 3 3 3 - - 3 V
1kΩ; IIS < 2µA on All
VIH = VDD OFF Channels 15 4 4 4 4 - - 4 V
through
Input High Voltage, VIH , 1kΩ 5 3.5 3.5 3.5 3.5 3.5 - - V
Min
10 7 7 7 7 7 - - V
15 11 11 11 11 11 - - V
Input Current, IIN (Max) VIN = 0, 18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 µA
Propagation Delay Time:

Address-to-Signal tr , tf = 20ns, 0 0 5 - - - - - 450 720 ns
OUT (Channels ON or CL = 50pF,
OFF) See Figures 10, RL = 10kΩ 0 0 10 - - - - - 160 320 ns
11, 14 0 0 15 - - - - - 120 240 ns
-5 0 5 - - - - - 225 450 ns

Inhibit-to-Signal OUT tr , tf = 20ns, 0 0 5 - - - - - 400 720 ns
(Channel Turning ON) CL = 50pF,
0 0 10 - - - - - 160 320 ns
See Figure 11 RL = 1kΩ
0 0 15 - - - - - 120 240 ns
-10 0 5 - - - - - 200 400 ns

Inhibit-to-Signal OUT tr , tf = 20ns, 0 0 5 - - - - - 200 450 ns
(Channel Turning CL = 50pF,
0 0 10 - - - - - 90 210 ns
OFF) See Figure 15 RL = 10kΩ
0 0 15 - - - - - 70 160 ns
-10 0 5 - - - - - 130 300 ns
Input Capacitance, CIN - - - - - 5 7.5 pF

(Any Address or Inhibit
Input)
NOTE:
2. Determined by minimum feasible leakage measurement for automatic testing.
Electrical Specifications
TEST CONDITIONS LIMITS
PARAMETER VIS (V) VDD (V) RL (kΩ) TYP UNITS
Cutoff (-3dB) Frequency Chan- 5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 30 MHz
nel ON (Sine Wave Input)
VEE = VSS , CD4052 25 MHz
V OS CD4051 20 MHz
20Log ------------ = – 3dB
V IS
VOS at Any Channel 60 MHz
6
CD4051B, CD4052B, CD4053B
Electrical Specifications
TEST CONDITIONS LIMITS
PARAMETER VIS (V) VDD (V) RL (kΩ) TYP UNITS
Total Harmonic Distortion, THD 2 (Note 3) 5 10 0.3 %
3 (Note 3) 10 0.2 %
5 (Note 3) 15 0.12 %
VEE = VSS, fIS = 1kHz Sine Wave %
-40dB Feedthrough Frequency 5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 8 MHz

(All Channels OFF)
VEE = VSS , CD4052 10 MHz
V OS
20Log ------------ = – 40dB CD4051 12 MHz
V IS
VOS at Any Channel 8 MHz
-40dB Signal Crosstalk 5 (Note 3) 10 1 Between Any 2 Channels 3 MHz

Frequency
VEE = VSS , Between Sections, Measured on Common 6 MHz
V OS CD4052 Only
20Log ------------ = – 40dB Measured on Any Chan- 10 MHz
V IS nel
Between Any Two In Pin 2, Out Pin 14 2.5 MHz

Sections, CD4053
In Pin 15, Out Pin 14 6 MHz
Only
Address-or-Inhibit-to-Signal - 10 10 65 mVPEAK
Crosstalk (Note 4)
VEE = 0, VSS = 0, tr , tf = 20ns, VCC 65 mVPEAK

= VDD - VSS (Square Wave)
NOTES:
3. Peak-to-Peak voltage symmetrical about V DD – V EE
-----------------------------
2
4. Both ends of channel.
Typical Performance Curves

600 300
VDD - VEE = 5V VDD - VEE = 10V
rON , CHANNEL ON RESISTANCE (Ω)
500 250
200 TA = 125oC
400
300 TA = 125oC 150

TA = 25oC
TA = 25oC
200 100
TA = -55oC
TA = -55oC
100 50
0 0
-4 -3 -2 -1 0 1 2 3 4 5 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10
VIS , INPUT SIGNAL VOLTAGE (V) VIS , INPUT SIGNAL VOLTAGE (V)
FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) VOLTAGE (ALL TYPES)
7
CD4051B, CD4052B, CD4053B
Typical Performance Curves (Continued)
600 250
TA = 25oC VDD - VEE = 15V

VDD - VEE = 5V
500
200
TA = 125oC
400
150
300
100 TA = 25oC
200
TA = -55oC
10V
50
100 15V
0 0
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10
VIS , INPUT SIGNAL VOLTAGE (V) VIS , INPUT SIGNAL VOLTAGE (V)
FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) VOLTAGE (ALL TYPES)
6 105
VDD = 5V TA = 25oC TEST CIRCUIT
PD , POWER DISSIPATION PACKAGE (µW)

VOS , OUTPUT SIGNAL VOLTAGE (V)
VSS = 0V RL = 100kΩ, RL = 10kΩ VDD

1kΩ ALTERNATING “O”
4 VEE = -5V AND “I” PATTERN B/D
500Ω f
TA = 25oC CL = 50pF CD4029
100Ω 104 A B C
VDD
2 VDD = 15V 100Ω 11 10 9
13
14
0 103 15
12 CD4051
1
-2 VDD = 10V 5
2 3
102 48 7 6 C
VDD = 5V L
-4
100Ω Ι
CL = 15pF
-6 10
-6 -4 -2 0 2 4 6 1 10 102 103 104 105
VIS , INPUT SIGNAL VOLTAGE (V) SWITCHING FREQUENCY (kHz)
FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING

(CD4051B) FREQUENCY (CD4051B)
105 105 TA = 25oC VDD = 15V

TA = 25oC
ALTERNATING “O” ALTERNATING “O” VDD = 10V

AND “I” PATTERN TEST CIRCUIT AND “I” PATTERN
CL = 50pF VDD CL = 50pF
104
f 104
CD4029 TEST CIRCUIT
VDD = 15V VDD B/D VDD f
A B 9
100Ω 4 CL
10 9 100Ω 3
1 3 CL 12
103 103 5
5 13 13
2 12 100Ω CD4053 2
VDD = 10V 4 CD4052 14 10 1
15
100Ω
6 VDD = 5V 11 15
11
102 6 14
102 VDD = 5V 7 7
CL = 15pF 8 8
Ι
CL = 15pF Ι
10
10
1 10 102 103 104 105 1 10 102 103 104 105
SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz)
FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4052B) FREQUENCY (CD4053B)
8
CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms
VDD = 15V VDD = 7.5V VDD = 5V VDD = 5V
7.5V 5V 5V
16 16 16 16
VSS = 0V VSS = 0V
VSS = 0V
VEE = 0V
7 7 7 7
8 VEE = -7.5V 8 VEE = -10V 8 VEE = -5V 8
VSS = 0V
(A) (B) (C) (D)
NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels

are: “0” = VSS and “1” = VDD. The analog signal (through the TG) may
swing from VEE to VDD.
FIGURE 9. TYPICAL BIAS VOLTAGES
tr = 20ns tf = 20ns tr = 20ns tf = 20ns
90% 90% 90% 90%

50% 50% 50% 50%
10% 10% 10% 10%
TURN-ON TIME
90% 90%
50%
10% 10%
10%
TURN-OFF TIME TURN-ON
TURN-OFF TIME tPHZ TIME
FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF
(RL = 1kΩ) (RL = 1kΩ)
VDD VDD VDD
1 16 1 16 1 16
2 15 2 15 2 15
3 14 IDD 3 14 IDD 3 14
4 13 4 13 4 13 IDD
5 12 5 12 5 12
6 11 6 11 6 11
7 10 7 10 7 10
8 9 8 9 8 9
CD4051 CD4052 CD4053
FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF
9
CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms (Continued)

VDD VDD VDD
1 16 1 16 1 16
2 15 2 15 2 15 IDD
IDD 3 14 IDD 3 14 3 14
4 13 4 13 4 13
5 12 5 12 5 12
6 11 6 11 6 11
7 10 7 10 7 10
8 9 8 9 8 9
CD4051 CD4052 CD4053
FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF
VDD VDD
OUTPUT
OUTPUT OUTPUT
1 16 1 16 VDD 1 16
VDD 2 15 RL CL 2 15 2 15 RL CL
CL RL
3 14 3 14 3 14
4 13 VEE VDD 4 13
4 13
5 12 VDD 5 12 VEE
5 12 VDD
VEE 6 11 VEE 6 11 VEE 6 11
VSS CLOCK VEE VDD VSS CLOCK
7 10 7 10 7 10
IN VSS CLOCK IN
8 9 8 9 8 9
VSS VSS IN VSS
CD4051 VSS CD4052 VSS CD4053 VSS
FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
VDD VDD
OUTPUT OUTPUT
OUTPUT
1 16 1 16 1 16 VDD
RL 50pF 2 15 RL 50pF 2 15 RL 2 15
50pF
3 14 3 14 3 14
VEE 4 13 VEE 4 13 4 13
VEE
VDD VDD 5 12 VDD 5 12 VDD 5 12
6 11 VDD 6 11 VDD 6 11
VSS VSS
CLOCK VEE 7 10 CLOCK VEE 7 10 VSS CLOCK VEE 7 10
IN VSS 8 9 IN VSS 8 9 IN VSS 8 9
tPHL AND tPLH VSS V

tPHL AND tPLH SS
V
tPHL AND tPLH SS
CD4051 CD4052 CD4053
FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
VDD
VDD VDD
µA VIH
1K 1 16
1 16 1 16 1K 1K 2 15 µA
2 15 2 15 µA 1K
3 14
3 14 3 14 4 13
1K 4 13 VIH 4 13 VIH
VIH 5 12
5 12 5 12 1K
VIL 6 11 VIH
6 11 6 11 7 10
VIL 7 10 VIL 7 10 VIL
VIH 8 9
8 9 8 9
CD4053B
CD4051B CD4052B
VIL VIL
MEASURE < 2µA ON ALL MEASURE < 2µA ON ALL MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6) “OFF” CHANNELS (e.g., CHANNEL 2x) “OFF” CHANNELS (e.g., CHANNEL by)
FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
10
CD4051B, CD4052B, CD4053B

VDD VDD KEITHLEY
VDD
160 DIGITAL
1 16 MULTIMETER
1 16 2 15
2 15 3 14 TG
3 14 10kΩ “ON”
4 13 1kΩ Y
4 13 5 12 RANGE
5 12 6 11
6 11 VSS X-Y
7 10
7 10 PLOTTER
8 9
8 9
H.P. X
Ι CD4051 Ι CD4052 MOSELEY
CD4053 7030A
FIGURE 17. QUIESCENT DEVICE CURRENT FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT
CIRCUIT
VDD VDD
1 16 1 16
2 15 2 15
3 14 3 14
4 13 4 13
5 12 VDD 5 12 VDD
6 11 6 11
7 10 Ι 7 10 Ι
8 9 8 9
VSS VSS
VSS CD4051 VSS CD4052
CD4053 NOTE: Measure inputs sequentially, NOTE: Measure inputs sequentially,
to both VDD and VSS connect all to both VDD and VSS connect all
unused inputs to either VDD or VSS . unused inputs to either VDD or VSS .
FIGURE 19. INPUT CURRENT
5VP-P
CHANNEL CHANNEL
ON OFF
RF
VM
5VP-P RF COMMON RL
OFF VM
CHANNEL
1K
VDD RL
CHANNEL RF CHANNEL
6 OFF VM ON
7 RL
RL
8
FIGURE 20. FEEDTHROUGH (ALL TYPES) FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS
(ALL TYPES)
5VP-P
CHANNEL IN X CHANNEL IN Y RF
ON OR OFF ON OR OFF VM
RL RL
FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)
11
CD4051B, CD4052B, CD4053B
DIFFERENTIAL CD4052 CD4052

SIGNALS
COMMUNICATIONS
LINK
DIFF. DIFF.
AMPLIFIER/ RECEIVER
LINE DRIVER
DIFF. DEMULTIPLEXING
MULTIPLEXING
FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B
Special Considerations
In applications where separate power sources are used to
drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load). This
provision avoids permanent current flow or clamp action on
the VDD supply when power is applied or removed from the
CD4051B, CD4052B or CD4053B.
A A
B B
CD4051B
C C
INH
Q0 COMMON
D A A
Q1 B OUTPUT
1/2
E B CD4051B
CD4556 Q2 C
E INH
A
B
CD4051B
C
INH
FIGURE 24. 24-TO-1 MUX ADDRESSING
12
PACKAGE OPTION ADDENDUM
www.ti.com 14-May-2010
PACKAGING INFORMATION
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
7901502EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
8101801EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD4051BE ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4051BEE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4051BF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD4051BF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD4051BF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI
CD4051BM ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BM96 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BM96G3 PREVIEW SOIC D 16 2500 TBD Call TI Call TI
CD4051BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BME4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BMG4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BMT ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BMTE4 ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BMTG4 ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BNSR ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPW ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(RoHS)
Addendum-Page 1
Type Drawing Qty
(RoHS)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
CD4052BPWRG3 PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI
no Sb/Br)
(RoHS)
(RoHS)
CD4053BF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI
Addendum-Page 2
Type Drawing Qty
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
CD4053BPWRG3 PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
Addendum-Page 3
compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4051B, CD4051B-MIL, CD4052B, CD4052B-MIL, CD4053B, CD4053B-MIL :

• Automotive: CD4051B-Q1, CD4053B-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4051BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4052BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4052BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4052BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4053BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4053BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4053BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jul-2010
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4051BM96 SOIC D 16 2500 346.0 346.0 33.0
CD4051BM96 SOIC D 16 2500 333.2 345.9 28.6
CD4051BNSR SO NS 16 2000 346.0 346.0 33.0
CD4051BPWR TSSOP PW 16 2000 346.0 346.0 29.0
CD4052BM96 SOIC D 16 2500 333.2 345.9 28.6
CD4052BNSR SO NS 16 2000 346.0 346.0 33.0
CD4052BPWR TSSOP PW 16 2000 346.0 346.0 29.0
CD4053BM96 SOIC D 16 2500 333.2 345.9 28.6
CD4053BNSR SO NS 16 2000 346.0 346.0 33.0
CD4053BPWR TSSOP PW 16 2000 346.0 346.0 29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN
0,30
0,65 0,10 M
0,19
14 8
0,15 NOM
4,50 6,60
4,30 6,20
Gage Plane
0,25
1 7
0°– 8°
A 0,75
0,50
Seating Plane
1,20 MAX 0,15 0,10

0,05
PINS **
8 14 16 20 24 28
DIM
A MAX 3,10 5,10 5,10 6,60 7,90 9,80
A MIN 2,90 4,90 4,90 6,40 7,70 9,60
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
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CD4051B, CD4052B, CD4053B

Features The CD4051B is a single 8-Channel multiplexer having three

(Harris CD4051BPW, CD4051BPWR, -55 to 125 16 Ld TSSOP

CHANNELS 4 1 16 VDD Y CHANNELS 0 1 16 VDD

CD4053B (PDIP, CDIP, SOP, TSSOP)

Functional Block Diagrams

† All inputs are protected by standard CMOS protection network.

Functional Block Diagrams (Continued)

† All inputs are protected by standard CMOS protection network.

INHIBIT C B A “ON” CHANNEL(S)

Absolute Maximum Ratings Thermal Information

CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)

SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)

Quiescent Device - - - 5 5 5 150 150 - 0.04 5 µA

- - - 15 20 20 600 600 - 0.04 20 µA

- - - 20 100 100 3000 3000 - 0.08 100 µA

Drain to Source ON - 0 0 5 800 850 1200 1300 - 470 1050 Ω

OFF Channel Leakage - 0 0 18 ±100 (Note 2) ±1000 (Note 2) - ±0.01 ±100 nA

Propagation Delay Time VDD RL = 200kΩ, 5 - - - - - 30 60 ns

CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)

CONTROL (ADDRESS OR INHIBIT), VC

Input Current, IIN (Max) VIN = 0, 18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 µA

Propagation Delay Time:

Propagation Delay Time:

-10 0 5 - - - - - 200 400 ns

Propagation Delay Time:

-10 0 5 - - - - - 130 300 ns

Input Capacitance, CIN - - - - - 5 7.5 pF

PARAMETER VIS (V) VDD (V) RL (kΩ) TYP UNITS

PARAMETER VIS (V) VDD (V) RL (kΩ) TYP UNITS

Total Harmonic Distortion, THD 2 (Note 3) 5 10 0.3 %

VEE = VSS, fIS = 1kHz Sine Wave %

-40dB Feedthrough Frequency 5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 8 MHz

-40dB Signal Crosstalk 5 (Note 3) 10 1 Between Any 2 Channels 3 MHz

Between Any Two In Pin 2, Out Pin 14 2.5 MHz

VEE = 0, VSS = 0, tr , tf = 20ns, VCC 65 mVPEAK

Typical Performance Curves

rON , CHANNEL ON RESISTANCE (Ω)

300 TA = 125oC 150

Typical Performance Curves (Continued)

rON , CHANNEL ON RESISTANCE (Ω)

PD , POWER DISSIPATION PACKAGE (µW)

VSS = 0V RL = 100kΩ, RL = 10kΩ VDD

FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING

105 105 TA = 25oC VDD = 15V

ALTERNATING “O” ALTERNATING “O” VDD = 10V

Test Circuits and Waveforms

VDD = 15V VDD = 7.5V VDD = 5V VDD = 5V

NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels

FIGURE 9. TYPICAL BIAS VOLTAGES

tr = 20ns tf = 20ns tr = 20ns tf = 20ns

90% 90% 90% 90%

VDD VDD VDD

CD4051 CD4052 CD4053

FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF

Test Circuits and Waveforms (Continued)

CD4051 CD4052 CD4053