SDM Vol 4
SDM Vol 4
SDM Vol 4
NOTE: The Intel® 64 and IA-32 Architectures Software Developer's Manual consists of ten volumes:
Basic Architecture, Order Number 253665; Instruction Set Reference A-L, Order Number 253666;
Instruction Set Reference M-U, Order Number 253667; Instruction Set Reference V-Z, Order Number
326018; Instruction Set Reference, Order Number 334569; System Programming Guide, Part 1, Order
Number 253668; System Programming Guide, Part 2, Order Number 253669; System Programming
Guide, Part 3, Order Number 326019; System Programming Guide, Part 4, Order Number 332831;
Model-Specific Registers, Order Number 335592. Refer to all ten volumes when evaluating your design
needs.
CHAPTER 1
ABOUT THIS MANUAL
1.1 INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.1 Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.2 Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.3 Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.4 Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.5 Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.6 Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.7 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
CHAPTER 2
MODEL-SPECIFIC REGISTERS (MSRS)
2.1 ARCHITECTURAL MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
2.3 MSRS IN THE 45 NM AND 32 NM INTEL ATOM® PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
2.4 MSRS IN INTEL PROCESSORS BASED ON SILVERMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
2.4.1 MSRs with Model-Specific Behavior in the Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93
2.4.2 MSRs In Intel Atom® Processors Based on Airmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
2.5 MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99
2.6 MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT PLUS MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-123
2.7 MSRS IN INTEL ATOM® PROCESSORS BASED ON TREMONT MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-127
2.8 MSRS IN THE INTEL® MICROARCHITECTURE CODE NAME NEHALEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-129
2.8.1 Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-147
2.8.2 Additional MSRs in the Intel® Xeon® Processor 7500 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-149
2.9 MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES (BASED ON INTEL® MICROARCHITECTURE CODE NAME
WESTMERE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-163
2.10 MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY (BASED ON INTEL® MICROARCHITECTURE CODE NAME
WESTMERE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-164
2.11 MSRS IN INTEL® PROCESSOR FAMILY BASED ON INTEL® MICROARCHITECTURE CODE NAME SANDY BRIDGE. . . . . . . 2-166
2.11.1 MSRs In 2nd Generation Intel® Core™ Processor Family (Based on Intel® Microarchitecture Code Name Sandy
Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-186
2.11.2 MSRs In Intel® Xeon® Processor E5 Family (Based on Intel® Microarchitecture Code Name Sandy Bridge) . . . . . . .2-190
2.11.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-194
2.12 MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY (BASED ON INTEL® MICROARCHITECTURE CODE
NAME IVY BRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-198
2.12.1 MSRs In Intel® Xeon® Processor E5 v2 Product Family (Based on Ivy Bridge-E Microarchitecture) . . . . . . . . . . . . . . .2-201
2.12.2 Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-209
2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families. . . . . . . . . . . . . . . . . . . . . . . . . .2-211
2.13 MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS (BASED ON HASWELL MICROARCHITECTURE) . . . . . . . 2-215
2.13.1 MSRs in 4th Generation Intel® Core™ Processor Family (based on Haswell Microarchitecture) . . . . . . . . . . . . . . . . . . . .2-220
2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-232
2.14 MSRS IN INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-234
2.14.1 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-244
2.15 MSRS IN INTEL® CORE™ M PROCESSORS AND 5TH GENERATION INTEL CORE PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . 2-254
2.16 MSRS IN INTEL® XEON® PROCESSORS E5 V4 FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-258
2.16.1 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-269
2.16.2 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-270
2.17 MSRS IN THE 6TH GENERATION, 7TH GENERATION, 8TH GENERATION, 9TH GENERATION, 10TH GENERATION, AND 11TH
GENERATION INTEL® CORE™ PROCESSORS, INTEL® XEON® PROCESSOR SCALABLE FAMILY, 2ND AND 3RD GENERATION INTEL®
XEON® PROCESSOR SCALABLE FAMILY, 8TH GENERATION INTEL® CORE™ I3 PROCESSORS, AND INTEL® XEON® E
PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-274
2.17.1 MSRs Specific to 7th Generation and 8th Generation Intel® Core™ Processors based on Kaby Lake Microarchitecture
and Coffee Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-297
2.17.2 MSRs Specific to 8th Generation Intel® Core™ i3 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-299
2.17.3 MSRs Specific to 10th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-305
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2.17.4 MSRs Specific to 11th Generation Intel® Core™ Processors based on Tiger Lake Microarchitecture . . . . . . . . . . . . . . . . .2-308
2.17.5 MSRs Specific to Intel® Xeon® Processor Scalable Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-311
2.17.6 MSRs Specific to 3rd Generation Intel® Xeon® Processor Scalable Family based on Ice Lake Microarchitecture . . . . . .2-323
2.18 MSRS IN INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES AND INTEL® XEON PHI™ PROCESSOR 7215/7285/7295
SERIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-325
2.19 MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-341
2.19.1 MSRs Unique to Intel® Xeon® Processor MP with L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-367
2.20 MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-368
2.21 MSRS IN THE PENTIUM M PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-377
2.22 MSRS IN THE P6 FAMILY PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-384
2.23 MSRS IN PENTIUM PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-393
2.24 MSR INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-394
iv Vol. 4
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PAGE
FIGURES
Figure 1-1. Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Vol. 4 v
CONTENTS
PAGE
TABLES
Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table 2-2. IA-32 Architectural MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
Table 2-4. MSRs in 45 nm and 32 nm Intel Atom® Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
Table 2-5. MSRs Supported by Intel Atom® Processors with CPUID Signature 06_27H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom® Processors . . 2-80
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
Table 2-8. Specific MSRs Supported by Intel Atom® Processors with CPUID Signatures 06_37H, 06_4AH, 06_5AH, 06_5DH 2-94
Table 2-9. Specific MSRs Supported by Intel Atom® Processor E3000 Series with CPUID Signature 06_37H . . . . . . . . . . . . . . . . 2-95
Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series with CPUID Signature 06_4DH. . . . . . . . . . . . . . . . 2-95
Table 2-11. MSRs in Intel Atom® Processors Based on the Airmont Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99
Table 2-13. MSRs in Intel Atom® Processors Based on the Goldmont Plus Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-123
Table 2-14. MSRs in Intel Atom® Processors Based on the Tremont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-128
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-129
Table 2-16. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-147
Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-149
Table 2-18. Additional MSRs Supported by Intel Processors (Based on Intel® Microarchitecture Code Name Westmere). . . . . .2-164
Table 2-19. Additional MSRs Supported by Intel® Xeon® Processor E7 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-165
Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge . . . . . . . . . . . . . .2-166
Table 2-21. MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy Bridge) 2-187
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-188
Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) . . . .2-190
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-194
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel® microarchitecture code
name Ivy Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-198
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) . . .2-201
Table 2-27. Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel Signature
06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-209
Table 2-28. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-212
Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures . . . . . . . . . . . . . .2-215
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture). . . . . . . . . . . . . . . . . . . . . . .2-220
Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with DisplayFamily_DisplayModel
Signature 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-233
Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-234
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-244
Table 2-34. Additional MSRs Common to Processors Based the Broadwell Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-254
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors . . . . . . . . . .2-256
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the
Broadwell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-258
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H . . . . . . . . . . . .2-269
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH . . . . . . . . . . . . .2-271
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th Generation, and
11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd Generation Intel® Xeon®
Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E Processors . . . . . . . . . . .2-274
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™ Processors, and
Future Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-295
Table 2-41. Additional MSRs Supported by 7th Generation and 8th Generation Intel® Core™ Processors Based on Kaby Lake
Microarchitecture and Coffee Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-297
Table 2-42. Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake
Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-299
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture. . . . . . . . . . . . .2-303
Table 2-44. MSRs Supported by 10th Generation Intel® Core™ Processors Based on Ice Lake Microarchitecture . . . . . . . . . . . . .2-305
Table 2-45. Additional MSRs Supported by 11th Generation Intel® Core™ Processors Based on Tiger Lake Microarchitecture 2-308
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H . . . . . . . . .2-311
Table 2-47. MSRs Supported by 3rd Generation Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel
Signatures of 06_6AH and 06_6CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-323
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H
and 06_85H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-325
Table 2-49. Additional MSRs Supported by Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series with DisplayFamily_DisplayModel
Signature 06_85H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-340
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-342
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Table 2-51. MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-367
Table 2-52. MSRs Unique to Intel® Xeon® Processor 7100 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-367
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV. . . . . . . . . . . . . . . 2-368
Table 2-54. MSRs in Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-377
Table 2-55. MSRs in the P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-384
Table 2-56. MSRs in the Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-394
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viii Vol. 4
CHAPTER 1
ABOUT THIS MANUAL
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4: Model-Specific Registers (order
number 335592) is part of a set that describes the architecture and programming environment of Intel® 64 and IA-
32 architecture processors. Other volumes in this set are:
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (order number
253665).
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D: Instruction Set
Reference (order numbers 253666, 253667, 326018 and 334569).
• The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D: System
Programming Guide (order numbers 253668, 253669, 326019 and 332831).
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture
and programming environment of Intel 64 and IA-32 processors. The Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volumes 2A, 2B, 2C & 2D, describe the instruction set of the processor and the opcode struc-
ture. These volumes apply to application programmers and to programmers who write operating systems or exec-
utives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D, describe
the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operating-
system and BIOS designers. In addition, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
3B, and Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C address the programming
environment for classes of software that host operating systems. The Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 4, describes the model-specific registers of Intel 64 and IA-32 processors.
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ABOUT THIS MANUAL
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Vol. 4 1-3
ABOUT THIS MANUAL
The 7th generation Intel® Core™ processors are based on the Kaby Lake microarchitecture and support Intel 64
architecture.
The Intel® Atom™ processor C series, the Intel® Atom™ processor X series, the Intel® Pentium® processor J
series, the Intel® Celeron® processor J series, and the Intel® Celeron® processor N series are based on the Gold-
mont microarchitecture.
The Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series is based on the Knights Landing microarchitecture and
supports Intel 64 architecture.
The Intel® Pentium® Silver processor series, the Intel® Celeron® processor J series, and the Intel® Celeron®
processor N series are based on the Goldmont Plus microarchitecture.
The 8th generation Intel® Core™ processors, 9th generation Intel® Core™ processors, and Intel® Xeon® E proces-
sors are based on the Coffee Lake microarchitecture and support Intel 64 architecture.
The Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series is based on the Knights Mill microarchitecture and
supports Intel 64 architecture.
The 2nd generation Intel® Xeon® Processor Scalable Family is based on the Cascade Lake product and supports
Intel 64 architecture.
Some 10th generation Intel® Core™ processors are based on the Ice Lake microarchitecture, and some are based
on the Comet Lake microarchitecture; both support Intel 64 architecture.
Some 11th generation Intel® Core™ processors are based on the Tiger Lake microarchitecture, and some are
based on the Rocket Lake microarchitecture; both support Intel 64 architecture.
Some 3rd generation Intel® Xeon® Processor Scalable Family processors are based on the Cooper Lake product,
and some are based on the Ice Lake microarchitecture; both support Intel 64 architecture.
IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microproces-
sors. Intel® 64 architecture is the instruction set architecture and programming environment which is the superset
of Intel’s 32-bit and 64-bit architectures. It is compatible with the IA-32 architecture.
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ABOUT THIS MANUAL
NOTE
Avoid any software dependence upon the state of reserved bits in Intel 64 and IA-32 registers.
Depending upon the values of reserved register bits will make software dependent upon the
unspecified manner in which the processor handles these bits. Programs that depend upon
reserved values risk incompatibility with future processors.
Data Structure
Highest 24 23 8 7 Bit offset
31 16 15 0
Address
28
24
20
16
12
8
4
Lowest
Byte 3 Byte 2 Byte 1 Byte 0 0 Address
Byte Offset
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In this example LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand,
and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.
DS:FF79H
The following segment address identifies an instruction address in the code segment. The CS register points to the
code segment and the EIP register contains the address of the instruction.
CS:EIP
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CPUID.01H:EDX.SSE[bit 25] = 1
CR4.OSFXSR[bit 9] = 1
Example CR name
IA32_MISC_ENABLE.ENABLEFOPCODE[bit 2] = 1
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation
1.3.7 Exceptions
An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to
divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other condi-
tions. Some types of exceptions may provide error codes. An error code reports additional information about the
error. An example of the notation used to show an exception and error code is shown below:
#PF(fault code)
This example refers to a page-fault exception under conditions where an error code naming a type of fault is
reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate
code. In this case, the error code is zero, as shown below for a general-protection exception:
#GP(0)
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CHAPTER 2
MODEL-SPECIFIC REGISTERS (MSRS)
This chapter lists MSRs across Intel processor families. All MSRs listed can be read with the RDMSR and written with
the WRMSR instructions. The scope of an MSR defines the set of processors that access the same MSR with RDMSR
and WRMSR. Thread-scope MSRs are unique to every logical processor. Core-scope MSRs are shared by the threads
in the same core; similarly for module-scope, die-scope, and package-scope.
When a processor package contains a single die, die-scope and package-scope are synonymous. When a package
contains multiple die, they are distinct.
NOTE
For information on hierarchical level types supported, refer to the CPUID Leaf 1FH definition for the
actual level type numbers: “V2 Extended Topology Enumeration Leaf” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2A. Also see Section 8.9.1, “Hierarchical
Mapping of Shared Resources” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
Register addresses are given in both hexadecimal and decimal. The register name is the mnemonic register name
and the bit description describes individual bits in registers.
Model specific registers and its bit-fields may be supported for a finite range of processor families/models. To distin-
guish between different processor family and/or models, software must use CPUID.01H leaf function to query the
combination of DisplayFamily and DisplayModel to determine model-specific availability of MSRs (see CPUID
instruction in Chapter 3, “Instruction Set Reference, A-L” in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 2A). Table 2-1 lists the signature values of DisplayFamily and DisplayModel for various
processor families or processor number series.
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C2H 194 IA32_PMC1 General Performance Counter 1 (R/W) If CPUID.0AH: EAX[15:8] >
(PERFCTR1) 1
C3H 195 IA32_PMC2 General Performance Counter 2 (R/W) If CPUID.0AH: EAX[15:8] >
2
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188H 392 IA32_PERFEVTSEL2 Performance Event Select Register 2 (R/W) If CPUID.0AH: EAX[15:8] >
2
189H 393 IA32_PERFEVTSEL3 Performance Event Select Register 3 (R/W) If CPUID.0AH: EAX[15:8] >
3
18AH- 394- Reserved 06_0EH2
197H 407
198H 408 IA32_PERF_STATUS Current Performance Status (RO) 0F_03H
See Section 14.1.1, “Software Interface For
Initiating Performance State Transitions”.
15:0 Current performance State Value.
63:16 Reserved
199H 409 IA32_PERF_CTL Performance Control MSR (R/W) 0F_03H
Software makes a request for a new
Performance state (P-State) by writing this
MSR. See Section 14.1.1, “Software
Interface For Initiating Performance State
Transitions”.
15:0 Target performance State Value.
31:16 Reserved
32 IDA Engage (R/W) 06_0FH (Mobile only)
When set to 1: disengages IDA.
63:33 Reserved
19AH 410 IA32_CLOCK_MODULATION Clock Modulation Control (R/W) If CPUID.01H:EDX[22] = 1
See Section 14.8.3, “Software Controlled
Clock Modulation.”
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10:0 Reserved
11 Valid
Enable range mask.
31:12 PhysMask
SMRR address range mask.
63:32 Reserved
1F8H 504 IA32_PLATFORM_DCA_CAP DCA Capability (R) If CPUID.01H: ECX[18] = 1
1F9H 505 IA32_CPU_DCA_CAP If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1
1FAH 506 IA32_DCA_0_CAP DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1
0 DCA_ACTIVE: Set by HW when DCA is fuse-
enabled and no defeatures are set.
2:1 TRANSACTION
6:3 DCA_TYPE
10:7 DCA_QUEUE_SIZE
12:11 Reserved
16:13 DCA_DELAY: Writes will update the register
but have no HW side-effect.
23:17 Reserved
24 SW_BLOCK: SW can request DCA block by
setting this bit.
25 Reserved
26 HW_BLOCK: Set when DCA is blocked by HW
(e.g. CR0.CD = 1).
31:27 Reserved
200H 512 IA32_MTRR_PHYSBASE0 See Section 11.11.2.3, “Variable Range If IA32_MTRRCAP[7:0] > 0
(MTRRphysBase0) MTRRs.”
201H 513 IA32_MTRR_PHYSMASK0 MTRRphysMask0 If IA32_MTRRCAP[7:0] > 0
202H 514 IA32_MTRR_PHYSBASE1 MTRRphysBase1 If IA32_MTRRCAP[7:0] > 1
203H 515 IA32_MTRR_PHYSMASK1 MTRRphysMask1 If IA32_MTRRCAP[7:0] > 1
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4C1H 1217 IA32_A_PMC0 Full Width Writable IA32_PMC0 Alias (R/W) (If CPUID.0AH: EAX[15:8] >
0) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C2H 1218 IA32_A_PMC1 Full Width Writable IA32_PMC1 Alias (R/W) (If CPUID.0AH: EAX[15:8] >
1) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C3H 1219 IA32_A_PMC2 Full Width Writable IA32_PMC2 Alias (R/W) (If CPUID.0AH: EAX[15:8] >
2) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C4H 1220 IA32_A_PMC3 Full Width Writable IA32_PMC3 Alias (R/W) (If CPUID.0AH: EAX[15:8] >
3) &&
IA32_PERF_CAPABILITIES[
13] = 1
4C5H 1221 IA32_A_PMC4 Full Width Writable IA32_PMC4 Alias (R/W) (If CPUID.0AH: EAX[15:8] >
4) &&
IA32_PERF_CAPABILITIES[
13] = 1
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42 Package_Control If CPUID.06H:EAX.[7] = 1
See Section 14.4.4, “Managing HWP”. && CPUID.06H:EAX.[11] =
1
63:43 Reserved
775H 1909 IA32_PECI_HWP_REQUEST_INFO IA32_PECI_HWP_REQUEST_INFO
7:0 Minimum Performance
(MINIMUM_PERFORMANCE): Used by OS to
read the latest value of PECI minimum
performance input. Default value is 0.
15:8 Maximum Performance
(MAXIMUM_PERFORMANCE): Used by OS to
read the latest value of PECI maximum
performance input. Default value is 0.
23:16 Reserved.
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63:N+32 Reserved
C8EH 3214 IA32_QM_CTR Monitoring Counter Register (R/O) If ( CPUID.(EAX=07H,
ECX=0):EBX.[12] = 1 )
61:0 Resource Monitored Data
62 Unavailable: If 1, indicates data for this
RMID is not available or not monitored for
this resource or RMID.
63 Error: If 1, indicates an unsupported RMID
or event type was written to
IA32_PQR_QM_EVTSEL.
C8FH 3215 IA32_PQR_ASSOC Resource Association Register (R/W) If ( (CPUID.(EAX=07H,
ECX=0):EBX[12] =1) or
(CPUID.(EAX=07H,
ECX=0):EBX[15] =1 ) )
N-1:0 Resource Monitoring ID (R/W): ID for N = Ceil (Log2 (
monitoring hardware to track internal CPUID.(EAX= 0FH,
operation, e.g., memory access. ECX=0H).EBX[31:0] +1))
31:N Reserved
63:32 COS (R/W): The class of service (COS) to If ( CPUID.(EAX=07H,
enforce (on writes); returns the current COS ECX=0):EBX.[15] = 1 )
when read.
C90H - 3216 - Reserved MSR Address Space for CAT See Section 17.19.4.1, “Enumeration and
D8FH 3471 Mask Registers Detection Support of Cache Allocation
Technology”.
C90H 3216 IA32_L3_MASK_0 L3 CAT Mask for COS0 (R/W) If (CPUID.(EAX=10H,
ECX=0H):EBX[1] != 0)
63:32 Reserved
C90H+ 3216+n IA32_L3_MASK_n L3 CAT Mask for COSn (R/W) n = CPUID.(EAX=10H,
n ECX=1H):EDX[15:0]
31:0 Capacity Bit Mask (R/W)
63:32 Reserved
D10H - 3344 - Reserved MSR Address Space for L2 See Section 17.19.4.1, “Enumeration and
D4FH 3407 CAT Mask Registers Detection Support of Cache Allocation
Technology”.
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63:32 Reserved
D10H+ 3344+n IA32_L2_MASK_n L2 CAT Mask for COSn (R/W) n = CPUID.(EAX=10H,
n ECX=2H):EDX[15:0]
31:0 Capacity Bit Mask (R/W)
63:32 Reserved
D90H 3472 IA32_BNDCFGS Supervisor State of MPX Configuration If (CPUID.(EAX=07H,
(R/W) ECX=0H):EBX[14] = 1)
0 EN: Enable Intel MPX in supervisor mode.
1 BNDPRESERVE: Preserve the bounds
registers for near branch instructions in the
absence of the BND prefix.
11:2 Reserved, must be zero.
63:12 Base Address of Bound Directory.
D91H 3473 IA32_COPY_LOCAL_TO_PLATFORM4 Copy Local State to Platform State (W) IF ((CPUID.19H:EBX[4] = 1)
&& (CPUID.(EAX=07H,
ECX=0H).ECX[23] = 1))
0 IWKeyBackup IF ((CPUID.19H:EBX[4] = 1)
Copy IWKey to IWKeyBackup && (CPUID.(EAX=07H,
ECX=0H).ECX[23] = 1))
63:1 Reserved
4
D92H 3474 IA32_COPY_PLATFORM_TO_LOCAL Copy Platform State to Local State (W) IF ((CPUID.19H:EBX[4] = 1)
&& (CPUID.(EAX=07H,
ECX=0H).ECX[23] = 1))
0 IWKeyBackup IF ((CPUID.19H:EBX[4] = 1)
Copy IWKeyBackup to IWKey && (CPUID.(EAX=07H,
ECX=0H).ECX[23] = 1))
63:1 Reserved
DA0H 3488 IA32_XSS Extended Supervisor State Mask (R/W) If( CPUID.(0DH, 1):EAX.[3] =
1
7:0 Reserved.
8 Trace Packet Configuration State (R/W)
10:9 Reserved.
11 CET_U State (R/W)
12 CET_S State (R/W)
13 HDC State (R/W)
63:14 Reserved.
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2. The *_ADDR MSRs may or may not be present; this depends on flag settings in IA32_MCi_STATUS. See Section 15.3.2.3 and Section
15.3.2.4 for more information.
3. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].
4. Further details on Key Locker and usage of this MSR can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
7:0 Reserved
12:8 Maximum Qualified Ratio (R)
The maximum allowed bus ratio.
49:13 Reserved
52:50 See Table 2-2.
63:53 Reserved
1BH 27 IA32_APIC_BASE Unique See Section 10.4.4, “Local APIC Status and Location” and
Table 2-2.
2AH 42 MSR_EBL_CR_POWERON Shared Processor Hard Power-On Configuration (R/W)
Enables and disables processor features; (R) indicates
current processor configuration.
0 Reserved
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7:0 Reserved
12:8 Maximum Qualified Ratio (R)
The maximum allowed bus ratio.
63:13 Reserved
1BH 27 IA32_APIC_BASE Unique See Section 10.4.4, “Local APIC Status and Location” and
Table 2-2.
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Table 2-5 lists model-specific registers (MSRs) that are specific to Intel Atom® processor with the CPUID signature
with DisplayFamily_DisplayModel of 06_27H.
Table 2-5. MSRs Supported by Intel Atom® Processors with CPUID Signature 06_27H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3F8H 1016 MSR_PKG_C2_RESIDENCY Package Package C2 Residency
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state parameters
or ACPI C-States.
63:0 Package Package C2 Residency Counter (R/O)
Time that this package is in processor-specific C2 states
since last reset. Counts at 1 Mhz frequency.
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Table 2-5. MSRs Supported by Intel Atom® Processors (Contd.)with CPUID Signature 06_27H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3F9H 1017 MSR_PKG_C4_RESIDENCY Package Package C4 Residency
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state parameters
or ACPI C-States.
63:0 Package Package C4 Residency Counter. (R/O)
Time that this package is in processor-specific C4 states
since last reset. Counts at 1 Mhz frequency.
3FAH 1018 MSR_PKG_C6_RESIDENCY Package Package C6 Residency
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state parameters
or ACPI C-States.
63:0 Package Package C6 Residency Counter. (R/O)
Time that this package is in processor-specific C6 states
since last reset. Counts at 1 Mhz frequency.
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Table 2-7 lists model-specific registers (MSRs) that are common to Intel® Atom™ processors based on the Silver-
mont and Airmont microarchitectures but not newer microarchitectures.
7:0 Reserved
13:8 Maximum Qualified Ratio (R)
The maximum allowed bus ratio.
49:13 Reserved
52:50 See Table 2-2.
63:33 Reserved
3AH 58 IA32_FEATURE_CONTROL Core Control Features in Intel 64Processor (R/W)
See Table 2-2.
0 Lock (R/WL)
1 Reserved
2 Enable VMX outside SMX operation (R/WL)
40H 64 MSR_LASTBRANCH_0_FROM_IP Core Last Branch Record 0 From IP (R/W)
One of eight pairs of last branch record registers on the
last branch record stack. The From_IP part of the stack
contains pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 17.5 and record format in Section 17.4.8.1.
41H 65 MSR_LASTBRANCH_1_FROM_IP Core Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
42H 66 MSR_LASTBRANCH_2_FROM_IP Core Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
43H 67 MSR_LASTBRANCH_3_FROM_IP Core Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
44H 68 MSR_LASTBRANCH_4_FROM_IP Core Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
45H 69 MSR_LASTBRANCH_5_FROM_IP Core Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
46H 70 MSR_LASTBRANCH_6_FROM_IP Core Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
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Table 2-8. Specific MSRs Supported by Intel Atom® Processors with CPUID Signatures
06_37H, 06_4AH, 06_5AH, 06_5DH
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
CDH 205 MSR_FSB_FREQ Module Scaleable Bus Speed(RO)
This field indicates the intended scaleable bus clock
speed for processors based on Silvermont
microarchitecture.
2:0 • 100B: 080.0 MHz
• 000B: 083.3 MHz
• 001B: 100.0 MHz
• 010B: 133.3 MHz
• 011B: 116.7 MHz
63:3 Reserved
606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers used in RAPL Interfaces (R/O)
See Section 14.10.1, “RAPL Interfaces.”
3:0 Power Units
Power related information (in milliWatts) is based on the
multiplier, 2^PU; where PU is an unsigned integer
represented by bits 3:0. Default value is 0101b,
indicating power unit is in 32 milliWatts increment.
7:4 Reserved
12:8 Energy Status Units
Energy related information (in microJoules) is based on
the multiplier, 2^ESU; where ESU is an unsigned integer
represented by bits 12:8. Default value is 00101b,
indicating energy unit is in 32 microJoules increment.
15:13 Reserved
19:16 Time Unit
The value is 0000b, indicating time unit is in one second.
63:20 Reserved
610H 1552 MSR_PKG_POWER_LIMIT Package PKG RAPL Power Limit Control (R/W)
14:0 Package Power Limit #1 (R/W)
See Section 14.10.3, “Package RAPL Domain.” and
MSR_RAPL_POWER_UNIT in Table 2-8.
15 Enable Power Limit #1 (R/W)
See Section 14.10.3, “Package RAPL Domain.”
16 Package Clamping Limitation #1 (R/W)
See Section 14.10.3, “Package RAPL Domain.”
23:17 Time Window for Power Limit #1 (R/W)
In unit of second. If 0 is specified in bits [23:17], defaults
to 1 second window.
63:24 Reserved
611H 1553 MSR_PKG_ENERGY_STATUS Package PKG Energy Status (R/O)
See Section 14.10.3, “Package RAPL Domain.” and
MSR_RAPL_POWER_UNIT in Table 2-8.
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Table 2-8. Specific MSRs Supported by Intel Atom® Processors with CPUID Signatures
06_37H, 06_4AH, 06_5AH, 06_5DH
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.” and
MSR_RAPL_POWER_UNIT in Table 2-8.
Table 2-9 lists model-specific registers (MSRs) that are specific to Intel Atom® processor E3000 Series (CPUID
signature with DisplayFamily_DisplayModel of 06_37H).
Table 2-9. Specific MSRs Supported by Intel Atom® Processor E3000 Series with CPUID Signature 06_37H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
668H 1640 MSR_CC6_DEMOTION_POLICY_CONFIG Package Core C6 Demotion Policy Config MSR
63:0 Controls per-core C6 demotion policy. Writing a value of
0 disables core level HW demotion policy.
669H 1641 MSR_MC6_DEMOTION_POLICY_CONFIG Package Module C6 Demotion Policy Config MSR
63:0 Controls module (i.e., two cores sharing the second-level
cache) C6 demotion policy. Writing a value of 0 disables
module level HW demotion policy.
664H 1636 MSR_MC6_RESIDENCY_COUNTER Module Module C6 Residency Counter (R/0)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0 Time that this module is in module-specific C6 states
since last reset. Counts at 1 Mhz frequency.
Table 2-10 lists model-specific registers (MSRs) that are specific to Intel Atom® processor C2000 Series (CPUID
signature with DisplayFamily_DisplayModel of 06_4DH).
Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series with CPUID Signature 06_4DH
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1A4H 420 MSR_MISC_FEATURE_CONTROL Miscellaneous Feature Control (R/W)
0 Core L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which
fetches additional lines of code or data into the L2
cache.
1 Reserved
2 Core DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which
fetches the next cache line into L1 data cache.
63:3 Reserved
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Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series (Contd.)with CPUID Signature
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode (RW)
7:0 Package Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8 Package Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16 Package Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24 Package Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
39:32 Package Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
47:40 Package Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
55:48 Package Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 core active.
63:56 Package Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 core active.
606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers used in RAPL Interfaces (R/O)
See Section 14.10.1, “RAPL Interfaces.”
3:0 Power Units
Power related information (in milliWatts) is based on
the multiplier, 2^PU; where PU is an unsigned integer
represented by bits 3:0. Default value is 0101b,
indicating power unit is in 32 milliWatts increment.
7:4 Reserved
12:8 Energy Status Units.
Energy related information (in microJoules) is based on
the multiplier, 2^ESU; where ESU is an unsigned
integer represented by bits 12:8. Default value is
00101b, indicating energy unit is in 32 microJoules
increment.
15:13 Reserved
19:16 Time Unit
The value is 0000b, indicating time unit is in one
second.
63:20 Reserved
610H 1552 MSR_PKG_POWER_LIMIT Package PKG RAPL Power Limit Control (R/W)
See Section 14.10.3, “Package RAPL Domain.”
66EH 1646 MSR_PKG_POWER_INFO Package PKG RAPL Parameter (R/0)
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Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series (Contd.)with CPUID Signature
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
14:0 Thermal Spec Power (R/0)
The unsigned integer value is the equivalent of the
thermal specification power of the package domain.
The unit of this field is specified by the “Power Units”
field of MSR_RAPL_POWER_UNIT.
63:15 Reserved
Table 2-11. MSRs in Intel Atom® Processors Based on the Airmont Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
CDH 205 MSR_FSB_FREQ Module Scaleable Bus Speed(RO)
This field indicates the intended scaleable bus clock
speed for processors based on Airmont
microarchitecture.
3:0 • 0000B: 083.3 MHz
• 0001B: 100.0 MHz
• 0010B: 133.3 MHz
• 0011B: 116.7 MHz
• 0100B: 080.0 MHz
• 0101B: 093.3 MHz
• 0110B: 090.0 MHz
• 0111B: 088.9 MHz
• 1000B: 087.5 MHz
63:5 Reserved
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Module C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
See http://biosbits.org.
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Table 2-11. MSRs in Intel Atom® Processors Based on the Airmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
000b: No limit
001b: C1
010b: C2
110b: C6
111b: C7
9:3 Reserved
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE to
MWAIT instructions.
14:11 Reserved
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
63:16 Reserved
E4H 228 MSR_PMG_IO_CAPTURE_BASE Module Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
15:0 LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO
redirection. If IO MWAIT Redirection is enabled, reads to
this address will be consumed by the power
management logic and decoded to MWAIT instructions.
When IO port address redirection is enabled, this is the
IO port address reported to the OS/software.
18:16 C-state Range (R/W)
Specifies the encoding value of the maximum C-State
code name to be included when IO read to MWAIT
redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include.
001b - Deep Power Down Technology is the max C-
State.
010b - C7 is the max C-State to include.
63:19 Reserved
638H 1592 MSR_PP0_POWER_LIMIT Package PP0 RAPL Power Limit Control (R/W)
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Table 2-11. MSRs in Intel Atom® Processors Based on the Airmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
14:0 PP0 Power Limit #1 (R/W)
See Section 14.10.4, “PP0/PP1 RAPL Domains” and
MSR_RAPL_POWER_UNIT in Table 2-8.
15 Enable Power Limit #1 (R/W)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
16 Reserved
23:17 Time Window for Power Limit #1 (R/W)
Specifies the time duration over which the average
power must remain below PP0_POWER_LIMIT
#1(14:0). Supported Encodings:
0x0: 1 second time duration.
0x1: 5 second time duration (Default).
0x2: 10 second time duration.
0x3: 15 second time duration.
0x4: 20 second time duration.
0x5: 25 second time duration.
0x6: 30 second time duration.
0x7: 35 second time duration.
0x8: 40 second time duration.
0x9: 45 second time duration.
0xA: 50 second time duration.
0xB-0x7F - reserved.
63:24 Reserved
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
17H 23 MSR_PLATFORM_ID Module Model Specific Platform ID (R)
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Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
49:0 Reserved
52:50 See Table 2-2.
63:33 Reserved
3AH 58 IA32_FEATURE_CONTROL Core Control Features in Intel 64 Processor (R/W)
See Table 2-2.
0 Lock (R/WL)
1 Enable VMX inside SMX operation (R/WL)
2 Enable VMX outside SMX operation (R/WL)
14:8 SENTER local functions enables (R/WL)
15 SENTER global functions enable (R/WL)
18 SGX global functions enable (R/WL)
63:19 Reserved
3BH 59 IA32_TSC_ADJUST Core Per-Core TSC ADJUST (R/W)
See Table 2-2.
C3H 195 IA32_PMC2 Core Performance Counter Register
See Table 2-2.
C4H 196 IA32_PMC3 Core Performance Counter Register
See Table 2-2.
CEH 206 MSR_PLATFORM_INFO Package Platform Information
Contains power management and other model specific
features enumeration. See http://biosbits.org.
7:0 Reserved
15:8 Package Maximum Non-Turbo Ratio (R/O)
This is the ratio of the maximum frequency that does
not require turbo. Frequency = ratio * 100 MHz.
27:16 Reserved
28 Package Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio
Limit for Turbo mode is enabled. When set to 0,
indicates Programmable Ratio Limit for Turbo mode is
disabled.
29 Package Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo
mode is programmable. When set to 0, indicates TDP
Limit for Turbo mode is not programmable.
30 Package Programmable TJ OFFSET (R/O)
When set to 1, indicates that
MSR_TEMPERATURE_TARGET.[27:24] is valid and
writable to specify a temperature offset.
39:31 Reserved
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Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
47:40 Package Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that
the processor can operate, in units of 100MHz.
63:48 Reserved
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Core C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
See http://biosbits.org.
3:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
0000b: No limit
0001b: C1
0010b: C3
0011b: C6
0100b: C7
0101b: C7S
0110b: C8
0111b: C9
1000b: C10
9:3 Reserved
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE to
MWAIT instructions.
14:11 Reserved
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
63:16 Reserved
17DH 381 MSR_SMM_MCA_CAP Core Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability enhancement. Accessible only
while in SMM.
57:0 Reserved
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access
restriction is supported and the
MSR_SMM_FEATURE_CONTROL is supported.
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Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
59 Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is
supported and the MSR_SMM_DELAYED is supported.
63:60 Reserved
188H 392 IA32_PERFEVTSEL2 Core See Table 2-2.
189H 393 IA32_PERFEVTSEL3 Core See Table 2-2.
1A0H 416 IA32_MISC_ENABLE Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled
and disabled.
0 Core Fast-Strings Enable
See Table 2-2.
2:1 Reserved
3 Package Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 1.
6:4 Reserved
7 Core Performance Monitoring Available (R)
See Table 2-2.
10:8 Reserved
11 Core Branch Trace Storage Unavailable (RO)
See Table 2-2.
12 Core Processor Event Based Sampling Unavailable (RO)
See Table 2-2.
15:13 Reserved
16 Package Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
18 Core ENABLE MONITOR FSM (R/W)
See Table 2-2.
21:19 Reserved
22 Core Limit CPUID Maxval (R/W)
See Table 2-2.
23 Package xTPR Message Disable (R/W)
See Table 2-2.
33:24 Reserved
34 Core XD Bit Disable (R/W)
See Table 2-2.
37:35 Reserved
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Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
38 Package Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo
Boost Technology, the turbo mode feature is disabled
and the IDA_Enable feature flag will be clear
(CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA,
CPUID.06H: EAX[1] reports the processor’s support of
turbo mode is enabled.
Note: The power-on default value is used by BIOS to
detect hardware support of turbo mode. If the power-
on default value is 1, turbo mode is available in the
processor. If the power-on default value is 0, turbo
mode is not available.
63:39 Reserved
1A4H 420 MSR_MISC_FEATURE_CONTROL Miscellaneous Feature Control (R/W)
0 Core L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which
fetches additional lines of code or data into the L2
cache.
1 Reserved
2 Core DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which
fetches the next cache line into L1 data cache.
63:3 Reserved
1AAH 426 MSR_MISC_PWR_MGMT Package Miscellaneous Power Management Control
Various model specific features enumeration. See
http://biosbits.org.
0 EIST Hardware Coordination Disable (R/W)
When 0, enables hardware coordination of Enhanced
Intel Speedstep Technology request from processor
cores. When 1, disables hardware coordination of
Enhanced Intel Speedstep Technology requests.
21:1 Reserved
22 Thermal Interrupt Coordination Enable (R/W)
If set, then thermal interrupt on one core is routed to
all cores.
63:23 Reserved
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Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode by Core Groups
(RW)
Specifies Maximum Ratio Limit for each Core Group.
Max ratio for groups with more cores must decrease
monotonically.
For groups with less than 4 cores, the max ratio must
be 32 or less. For groups with 4-5 cores, the max ratio
must be 22 or less. For groups with more than 5 cores,
the max ratio must be 16 or less.
7:0 Package Maximum Ratio Limit for Active Cores in Group 0
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 0 threshold.
15:8 Package Maximum Ratio Limit for Active Cores in Group 1
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 1 threshold,
and greater than the Group 0 threshold.
23:16 Package Maximum Ratio Limit for Active Cores in Group 2
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 2 threshold,
and greater than the Group 1 threshold.
31:24 Package Maximum Ratio Limit for Active Cores in Group 3
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 3 threshold,
and greater than the Group 2 threshold.
39:32 Package Maximum Ratio Limit for Active Cores in Group 4
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 4 threshold,
and greater than the Group 3 threshold.
47:40 Package Maximum Ratio Limit for Active Cores in Group 5
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 5 threshold,
and greater than the Group 4 threshold.
55:48 Package Maximum Ratio Limit for Active Cores in Group 6
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 6 threshold,
and greater than the Group 5 threshold.
63:56 Package Maximum Ratio Limit for Active Cores in Group 7
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 7 threshold,
and greater than the Group 6 threshold.
1AEH 430 MSR_TURBO_GROUP_CORECNT Package Group Size of Active Cores for Turbo Mode Operation
(RW)
Writes of 0 threshold is ignored.
2-104 Vol. 4
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Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
7:0 Package Group 0 Core Count Threshold
Maximum number of active cores to operate under the
Group 0 Max Turbo Ratio limit.
15:8 Package Group 1 Core Count Threshold
Maximum number of active cores to operate under the
Group 1 Max Turbo Ratio limit. Must be greater than
the Group 0 Core Count.
23:16 Package Group 2 Core Count Threshold
Maximum number of active cores to operate under the
Group 2 Max Turbo Ratio limit. Must be greater than
the Group 1 Core Count.
31:24 Package Group 3 Core Count Threshold
Maximum number of active cores to operate under the
Group 3 Max Turbo Ratio limit. Must be greater than
the Group 2 Core Count.
39:32 Package Group 4 Core Count Threshold
Maximum number of active cores to operate under the
Group 4 Max Turbo Ratio limit. Must be greater than
the Group 3 Core Count.
47:40 Package Group 5 Core Count Threshold
Maximum number of active cores to operate under the
Group 5 Max Turbo Ratio limit. Must be greater than
the Group 4 Core Count.
55:48 Package Group 6 Core Count Threshold
Maximum number of active cores to operate under the
Group 6 Max Turbo Ratio limit. Must be greater than
the Group 5 Core Count.
63:56 Package Group 7 Core Count Threshold
Maximum number of active cores to operate under the
Group 7 Max Turbo Ratio limit. Must be greater than
the Group 6 Core Count, and not less than the total
number of processor cores in the package. E.g., specify
255.
1C8H 456 MSR_LBR_SELECT Core Last Branch Record Filtering Select Register (R/W)
See Section 17.9.2, “Filtering of Last Branch Records.”
0 CPL_EQ_0
1 CPL_NEQ_0
2 JCC
3 NEAR_REL_CALL
4 NEAR_IND_CALL
5 NEAR_RET
6 NEAR_IND_JMP
7 NEAR_REL_JMP
Vol. 4 2-105
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
8 FAR_BRANCH
9 EN_CALL_STACK
63:10 Reserved
1C9H 457 MSR_LASTBRANCH_TOS Core Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-4) that points to the MSR
containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
1FCH 508 MSR_POWER_CTL Core Power Control Register. See http://biosbits.org.
0 Reserved
1 Package C1E Enable (R/W)
When set to ‘1’, will enable the CPU to switch to the
Minimum Enhanced Intel SpeedStep Technology
operating point when all execution cores enter MWAIT
(C1).
63:2 Reserved
210H 528 IA32_MTRR_PHYSBASE8 Core See Table 2-2.
211H 529 IA32_MTRR_PHYSMASK8 Core See Table 2-2.
212H 530 IA32_MTRR_PHYSBASE9 Core See Table 2-2.
213H 531 IA32_MTRR_PHYSMASK9 Core See Table 2-2.
280H 640 IA32_MC0_CTL2 Module See Table 2-2.
281H 641 IA32_MC1_CTL2 Module See Table 2-2.
282H 642 IA32_MC2_CTL2 Core See Table 2-2.
283H 643 IA32_MC3_CTL2 Module See Table 2-2.
284H 644 IA32_MC4_CTL2 Package See Table 2-2.
285H 645 IA32_MC5_CTL2 Package See Table 2-2.
286H 646 IA32_MC6_CTL2 Package See Table 2-2.
300H 768 MSR_SGXOWNEREPOCH0 Package Lower 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if
CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any
thread in the package.
63:0 Lower 64 bits of an 128-bit external entropy value for
key derivation of an enclave.
301H 769 MSR_SGXOWNEREPOCH1 Package Upper 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if
CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any
thread in the package.
63:0 Upper 64 bits of an 128-bit external entropy value for
key derivation of an enclave.
38EH 910 IA32_PERF_GLOBAL_STATUS Core See Table 2-2. See Section 18.2.4, “Architectural
Performance Monitoring Version 4.”
0 Ovf_PMC0
2-106 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1 Ovf_PMC1
2 Ovf_PMC2
3 Ovf_PMC3
31:4 Reserved
32 Ovf_FixedCtr0
33 Ovf_FixedCtr1
34 Ovf_FixedCtr2
54:35 Reserved
55 Trace_ToPA_PMI
57:56 Reserved
58 LBR_Frz.
59 CTR_Frz.
60 ASCI
61 Ovf_Uncore
62 Ovf_BufDSSAVE
63 CondChgd
390H 912 IA32_PERF_GLOBAL_STATUS_RESET Core See Table 2-2. See Section 18.2.4, “Architectural
Performance Monitoring Version 4.”
0 Set 1 to clear Ovf_PMC0.
1 Set 1 to clear Ovf_PMC1.
2 Set 1 to clear Ovf_PMC2.
3 Set 1 to clear Ovf_PMC3.
31:4 Reserved
32 Set 1 to clear Ovf_FixedCtr0.
33 Set 1 to clear Ovf_FixedCtr1.
34 Set 1 to clear Ovf_FixedCtr2.
54:35 Reserved
55 Set 1 to clear Trace_ToPA_PMI.
57:56 Reserved
58 Set 1 to clear LBR_Frz.
59 Set 1 to clear CTR_Frz.
60 Set 1 to clear ASCI.
61 Set 1 to clear Ovf_Uncore.
62 Set 1 to clear Ovf_BufDSSAVE.
63 Set 1 to clear CondChgd.
391H 913 IA32_PERF_GLOBAL_STATUS_SET Core See Table 2-2. See Section 18.2.4, “Architectural
Performance Monitoring Version 4.”
Vol. 4 2-107
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
0 Set 1 to cause Ovf_PMC0 = 1.
1 Set 1 to cause Ovf_PMC1 = 1.
2 Set 1 to cause Ovf_PMC2 = 1.
3 Set 1 to cause Ovf_PMC3 = 1.
31:4 Reserved
32 Set 1 to cause Ovf_FixedCtr0 = 1.
33 Set 1 to cause Ovf_FixedCtr1 = 1.
34 Set 1 to cause Ovf_FixedCtr2 = 1.
54:35 Reserved
55 Set 1 to cause Trace_ToPA_PMI = 1.
57:56 Reserved
58 Set 1 to cause LBR_Frz = 1.
59 Set 1 to cause CTR_Frz = 1.
60 Set 1 to cause ASCI = 1.
61 Set 1 to cause Ovf_Uncore.
62 Set 1 to cause Ovf_BufDSSAVE.
63 Reserved
392H 914 IA32_PERF_GLOBAL_INUSE Core See Table 2-2.
3F1H 1009 MSR_PEBS_ENABLE Core See Table 2-2. See Section 18.6.2.4, “Processor Event
Based Sampling (PEBS).”
0 Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC0. (R/W)
3F8H 1016 MSR_PKG_C3_RESIDENCY Package Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0 Package C3 Residency Counter (R/O)
Value since last reset that this package is in
processor-specific C3 states. Count at the same
frequency as the TSC.
3F9H 1017 MSR_PKG_C6_RESIDENCY Package Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0 Package C6 Residency Counter (R/O)
Value since last reset that this package is in
processor-specific C6 states. Count at the same
frequency as the TSC.
3FCH 1020 MSR_CORE_C3_RESIDENCY Core Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
2-108 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:0 CORE C3 Residency Counter (R/O)
Value since last reset that this core is in processor-
specific C3 states. Count at the same frequency as the
TSC.
406H 1030 IA32_MC1_ADDR Module See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
418H 1048 IA32_MC6_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
419H 1049 IA32_MC6_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
41AH 1050 IA32_MC6_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
4C3H 1219 IA32_A_PMC2 Core See Table 2-2.
4C4H 1220 IA32_A_PMC3 Core See Table 2-2.
4E0H 1248 MSR_SMM_FEATURE_CONTROL Package Enhanced SMM Feature Control (SMM-RW)
Reports SMM capability Enhancement. Accessible only
while in SMM.
0 Lock (SMM-RWO)
When set to ‘1’ locks this register from further
changes.
1 Reserved
2 SMM_Code_Chk_En (SMM-RW)
This control bit is available only if
MSR_SMM_MCA_CAP[58] == 1. When set to ‘0’
(default) none of the logical processors are prevented
from executing SMM code outside the ranges defined
by the SMRR.
When set to ‘1’ any logical processor in the package
that attempts to execute SMM code not within the
ranges defined by the SMRR will assert an
unrecoverable MCE.
63:3 Reserved
4E2H 1250 MSR_SMM_DELAYED Package SMM Delayed (SMM-RO)
Reports the interruptible state of all logical processors
in the package. Available only while in SMM and
MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
Vol. 4 2-109
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
N-1:0 LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its state in a
long flow of internal operation which delays servicing
an interrupt. The corresponding bit will be set at the
start of long events such as: Microcode Update Load,
C6, WBINVD, Ratio Change, Throttle.
The bit is automatically cleared at the end of each long
event. The reset value of this field is 0.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N Reserved
4E3H 1251 MSR_SMM_BLOCKED Package SMM Blocked (SMM-RO)
Reports the blocked state of all logical processors in
the package. Available only while in SMM.
N-1:0 LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its blocked
state to service an SMI. The corresponding bit will be
set if the logical processor is in one of the following
states: Wait For SIPI or SENTER Sleep.
The reset value of this field is 0FFFH.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N Reserved
500H 1280 IA32_SGX_SVN_STATUS Core Status and SVN Threshold of SGX Support for ACM
(RO)
0 Lock
See Section 37.11.3, “Interactions with Authenticated
Code Modules (ACMs)”.
15:1 Reserved
23:16 SGX_SVN_SINIT
See Section 37.11.3, “Interactions with Authenticated
Code Modules (ACMs)”.
63:24 Reserved
560H 1376 IA32_RTIT_OUTPUT_BASE Core Trace Output Base Register (R/W)
See Table 2-2.
561H 1377 IA32_RTIT_OUTPUT_MASK_PTRS Core Trace Output Mask Pointers Register (R/W)
See Table 2-2.
570H 1392 IA32_RTIT_CTL Core Trace Control Register (R/W)
0 TraceEn
1 CYCEn
2 OS
3 User
6:4 Reserved, must be zero.
2-110 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
7 CR3 filter
8 ToPA
Writing 0 will #GP if also setting TraceEn.
9 MTCEn
10 TSCEn
11 DisRETC
12 Reserved, must be zero.
13 BranchEn
17:14 MTCFreq
18 Reserved, must be zero.
22:19 CYCThresh
23 Reserved, must be zero.
27:24 PSBFreq
31:28 Reserved, must be zero.
35:32 ADDR0_CFG
39:36 ADDR1_CFG
63:40 Reserved, must be zero.
571H 1393 IA32_RTIT_STATUS Core Tracing Status Register (R/W)
0 FilterEn
Writes ignored.
1 ContexEn
Writes ignored.
2 TriggerEn
Writes ignored.
3 Reserved
4 Error (R/W)
5 Stopped
31:6 Reserved, must be zero.
48:32 PacketByteCnt
63:49 Reserved, must be zero.
572H 1394 IA32_RTIT_CR3_MATCH Core Trace Filter CR3 Match Register (R/W)
4:0 Reserved
63:5 CR3[63:5] value to match.
580H 1408 IA32_RTIT_ADDR0_A Core Region 0 Start Address (R/W)
63:0 See Table 2-2.
581H 1409 IA32_RTIT_ADDR0_B Core Region 0 End Address (R/W)
63:0 See Table 2-2.
Vol. 4 2-111
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
582H 1410 IA32_RTIT_ADDR1_A Core Region 1 Start Address (R/W)
63:0 See Table 2-2.
583H 1411 IA32_RTIT_ADDR1_B Core Region 1 End Address (R/W)
63:0 See Table 2-2.
606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers used in RAPL Interfaces (R/O)
See Section 14.10.1, “RAPL Interfaces.”
3:0 Power Units
Power related information (in Watts) is in unit of
1W/2^PU; where PU is an unsigned integer
represented by bits 3:0. Default value is 1000b,
indicating power unit is in 3.9 milliWatts increment.
7:4 Reserved
12:8 Energy Status Units
Energy related information (in Joules) is in unit of
1Joule/ (2^ESU); where ESU is an unsigned integer
represented by bits 12:8. Default value is 01110b,
indicating energy unit is in 61 microJoules.
15:13 Reserved
19:16 Time Unit
Time related information (in seconds) is in unit of
1S/2^TU; where TU is an unsigned integer
represented by bits 19:16. Default value is 1010b,
indicating power unit is in 0.977 millisecond.
63:20 Reserved
60AH 1546 MSR_PKGC3_IRTL Package Package C3 Interrupt Response Limit (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the
package should be put into a package C3 state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. See Table 2-20 for
supported time unit encodings.
14:13 Reserved
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and
can be used by the processor for package C-sate
management.
63:16 Reserved
2-112 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
60BH 1547 MSR_PKGC_IRTL1 Package Package C6/C7S Interrupt Response Limit 1 (R/W)
This MSR defines the interrupt response time limit
used by the processor to manage a transition to a
package C6 or C7S state.
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the
package should be put into a package C6 or C7S state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. See Table 2-20 for
supported time unit encodings.
14:13 Reserved
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and
can be used by the processor for package C-sate
management.
63:16 Reserved
60CH 1548 MSR_PKGC_IRTL2 Package Package C7 Interrupt Response Limit 2 (R/W)
This MSR defines the interrupt response time limit
used by the processor to manage a transition to a
package C7 state.
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the
package should be put into a package C7 state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. See Table 2-20 for
supported time unit encodings.
14:13 Reserved
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and
can be used by the processor for package C-sate
management.
63:16 Reserved
60DH 1549 MSR_PKG_C2_RESIDENCY Package Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
Vol. 4 2-113
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:0 Package C2 Residency Counter (R/O)
Value since last reset that this package is in
processor-specific C2 states. Count at the same
frequency as the TSC.
610H 1552 MSR_PKG_POWER_LIMIT Package PKG RAPL Power Limit Control (R/W)
See Section 14.10.3, “Package RAPL Domain.”
611H 1553 MSR_PKG_ENERGY_STATUS Package PKG Energy Status (R/O)
See Section 14.10.3, “Package RAPL Domain.”
613H 1555 MSR_PKG_PERF_STATUS Package PKG Perf Status (R/O)
See Section 14.10.3, “Package RAPL Domain.”
614H 1556 MSR_PKG_POWER_INFO Package PKG RAPL Parameters (R/W)
14:0 Thermal Spec Power (R/W)
See Section 14.10.3, “Package RAPL Domain.”
15 Reserved
30:16 Minimum Power (R/W)
See Section 14.10.3, “Package RAPL Domain.”
31 Reserved
46:32 Maximum Power (R/W)
See Section 14.10.3, “Package RAPL Domain.”
47 Reserved
54:48 Maximum Time Window (R/W)
Specified by 2^Y * (1.0 + Z/4.0) * Time_Unit, where
“Y” is the unsigned integer value represented by bits
52:48, “Z” is an unsigned integer represented by bits
54:53. “Time_Unit” is specified by the “Time Units”
field of MSR_RAPL_POWER_UNIT.
63:55 Reserved
618H 1560 MSR_DRAM_POWER_LIMIT Package DRAM RAPL Power Limit Control (R/W)
See Section 14.10.5, “DRAM RAPL Domain.”
619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W)
See Section 14.10.5, “DRAM RAPL Domain.”
632H 1586 MSR_PKG_C10_RESIDENCY Package Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
63:0 Package C10 Residency Counter (R/O)
Value since last reset that the entire SOC is in an S0i3
state. Count at the same frequency as the TSC.
2-114 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
641H 1601 MSR_PP1_ENERGY_STATUS Package PP1 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
64CH 1612 MSR_TURBO_ACTIVATION_RATIO Package ConfigTDP Control (R/W)
Vol. 4 2-115
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
12 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating
system request due to electrical design point
constraints (e.g., maximum electrical current
consumption).
13 Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating
system request due to Turbo transition attenuation.
This prevents performance degradation due to
frequent operating ratio changes.
14 Maximum Efficiency Frequency Status (R0)
When set, frequency is reduced below the maximum
efficiency frequency.
15 Reserved
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
18 Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power
Limiting Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software
writing 0.
19 Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power
Limiting Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software
writing 0.
24:20 Reserved
25 Core Power Limiting Log
When set, indicates that the Core Power Limiting
Status bit has asserted since the log bit was last
cleared.
This log bit will remain set until cleared by software
writing 0.
2-116 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
26 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
27 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
28 Electrical Design Point Log
When set, indicates that the EDP Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition
Attenuation Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software
writing 0.
30 Maximum Efficiency Frequency Log
When set, indicates that the Maximum Efficiency
Frequency Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software
writing 0.
63:31 Reserved
680H 1664 MSR_LASTBRANCH_0_FROM_IP Core Last Branch Record 0 From IP (R/W)
One of 32 pairs of last branch record registers on the
last branch record stack. The From_IP part of the stack
contains pointers to the source instruction . See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 17.6 and record format in Section 17.4.8.1.
0:47 From Linear Address (R/W)
62:48 Signed extension of bits 47:0.
63 Mispred
681H 1665 MSR_LASTBRANCH_1_FROM_IP Core Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
682H 1666 MSR_LASTBRANCH_2_FROM_IP Core Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
683H 1667 MSR_LASTBRANCH_3_FROM_IP Core Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Vol. 4 2-117
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
684H 1668 MSR_LASTBRANCH_4_FROM_IP Core Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
685H 1669 MSR_LASTBRANCH_5_FROM_IP Core Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
686H 1670 MSR_LASTBRANCH_6_FROM_IP Core Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
687H 1671 MSR_LASTBRANCH_7_FROM_IP Core Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
688H 1672 MSR_LASTBRANCH_8_FROM_IP Core Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
689H 1673 MSR_LASTBRANCH_9_FROM_IP Core Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68AH 1674 MSR_LASTBRANCH_10_FROM_IP Core Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68BH 1675 MSR_LASTBRANCH_11_FROM_IP Core Last Branch Record 11 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68CH 1676 MSR_LASTBRANCH_12_FROM_IP Core Last Branch Record 12 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68DH 1677 MSR_LASTBRANCH_13_FROM_IP Core Last Branch Record 13 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68EH 1678 MSR_LASTBRANCH_14_FROM_IP Core Last Branch Record 14 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68FH 1679 MSR_LASTBRANCH_15_FROM_IP Core Last Branch Record 15 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
690H 1680 MSR_LASTBRANCH_16_FROM_IP Core Last Branch Record 16 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
691H 1681 MSR_LASTBRANCH_17_FROM_IP Core Last Branch Record 17 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
692H 1682 MSR_LASTBRANCH_18_FROM_IP Core Last Branch Record 18 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
693H 1683 MSR_LASTBRANCH_19_FROM_IP Core Last Branch Record 19From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
694H 1684 MSR_LASTBRANCH_20_FROM_IP Core Last Branch Record 20 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
695H 1685 MSR_LASTBRANCH_21_FROM_IP Core Last Branch Record 21 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
696H 1686 MSR_LASTBRANCH_22_FROM_IP Core Last Branch Record 22 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
2-118 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
697H 1687 MSR_LASTBRANCH_23_FROM_IP Core Last Branch Record 23 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
698H 1688 MSR_LASTBRANCH_24_FROM_IP Core Last Branch Record 24 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
699H 1689 MSR_LASTBRANCH_25_FROM_IP Core Last Branch Record 25 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69AH 1690 MSR_LASTBRANCH_26_FROM_IP Core Last Branch Record 26 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69BH 1691 MSR_LASTBRANCH_27_FROM_IP Core Last Branch Record 27 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69CH 1692 MSR_LASTBRANCH_28_FROM_IP Core Last Branch Record 28 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69DH 1693 MSR_LASTBRANCH_29_FROM_IP Core Last Branch Record 29 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69EH 1694 MSR_LASTBRANCH_30_FROM_IP Core Last Branch Record 30 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69FH 1695 MSR_LASTBRANCH_31_FROM_IP Core Last Branch Record 31 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
6C0H 1728 MSR_LASTBRANCH_0_TO_IP Core Last Branch Record 0 To IP (R/W)
One of 32 pairs of last branch record registers on the
last branch record stack. The To_IP part of the stack
contains pointers to the Destination instruction and
elapsed cycles from last LBR update. See Section 17.6.
0:47 Target Linear Address (R/W)
63:48 Elapsed cycles from last update to the LBR.
6C1H 1729 MSR_LASTBRANCH_1_TO_IP Core Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C2H 1730 MSR_LASTBRANCH_2_TO_IP Core Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C3H 1731 MSR_LASTBRANCH_3_TO_IP Core Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C4H 1732 MSR_LASTBRANCH_4_TO_IP Core Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C5H 1733 MSR_LASTBRANCH_5_TO_IP Core Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C6H 1734 MSR_LASTBRANCH_6_TO_IP Core Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C7H 1735 MSR_LASTBRANCH_7_TO_IP Core Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Vol. 4 2-119
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
6C8H 1736 MSR_LASTBRANCH_8_TO_IP Core Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C9H 1737 MSR_LASTBRANCH_9_TO_IP Core Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CAH 1738 MSR_LASTBRANCH_10_TO_IP Core Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CBH 1739 MSR_LASTBRANCH_11_TO_IP Core Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CCH 1740 MSR_LASTBRANCH_12_TO_IP Core Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CDH 1741 MSR_LASTBRANCH_13_TO_IP Core Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CEH 1742 MSR_LASTBRANCH_14_TO_IP Core Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CFH 1743 MSR_LASTBRANCH_15_TO_IP Core Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D0H 1744 MSR_LASTBRANCH_16_TO_IP Core Last Branch Record 16 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D1H 1745 MSR_LASTBRANCH_17_TO_IP Core Last Branch Record 17 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D2H 1746 MSR_LASTBRANCH_18_TO_IP Core Last Branch Record 18 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D3H 1747 MSR_LASTBRANCH_19_TO_IP Core Last Branch Record 19To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D4H 1748 MSR_LASTBRANCH_20_TO_IP Core Last Branch Record 20 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D5H 1749 MSR_LASTBRANCH_21_TO_IP Core Last Branch Record 21 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D6H 1750 MSR_LASTBRANCH_22_TO_IP Core Last Branch Record 22 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D7H 1751 MSR_LASTBRANCH_23_TO_IP Core Last Branch Record 23 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D8H 1752 MSR_LASTBRANCH_24_TO_IP Core Last Branch Record 24 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D9H 1753 MSR_LASTBRANCH_25_TO_IP Core Last Branch Record 25 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DAH 1754 MSR_LASTBRANCH_26_TO_IP Core Last Branch Record 26 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
2-120 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
6DBH 1755 MSR_LASTBRANCH_27_TO_IP Core Last Branch Record 27 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DCH 1756 MSR_LASTBRANCH_28_TO_IP Core Last Branch Record 28 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DDH 1757 MSR_LASTBRANCH_29_TO_IP Core Last Branch Record 29 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DEH 1758 MSR_LASTBRANCH_30_TO_IP Core Last Branch Record 30 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DFH 1759 MSR_LASTBRANCH_31_TO_IP Core Last Branch Record 31 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
802H 2050 IA32_X2APIC_APICID Core x2APIC ID register (R/O)
803H 2051 IA32_X2APIC_VERSION Core x2APIC Version register (R/O)
808H 2056 IA32_X2APIC_TPR Core x2APIC Task Priority register (R/W)
80AH 2058 IA32_X2APIC_PPR Core x2APIC Processor Priority register (R/O)
80BH 2059 IA32_X2APIC_EOI Core x2APIC EOI register (W/O)
80DH 2061 IA32_X2APIC_LDR Core x2APIC Logical Destination register (R/O)
80FH 2063 IA32_X2APIC_SIVR Core x2APIC Spurious Interrupt Vector register (R/W)
810H 2064 IA32_X2APIC_ISR0 Core x2APIC In-Service register bits [31:0] (R/O)
811H 2065 IA32_X2APIC_ISR1 Core x2APIC In-Service register bits [63:32] (R/O)
812H 2066 IA32_X2APIC_ISR2 Core x2APIC In-Service register bits [95:64] (R/O)
813H 2067 IA32_X2APIC_ISR3 Core x2APIC In-Service register bits [127:96] (R/O)
814H 2068 IA32_X2APIC_ISR4 Core x2APIC In-Service register bits [159:128] (R/O)
815H 2069 IA32_X2APIC_ISR5 Core x2APIC In-Service register bits [191:160] (R/O)
816H 2070 IA32_X2APIC_ISR6 Core x2APIC In-Service register bits [223:192] (R/O)
817H 2071 IA32_X2APIC_ISR7 Core x2APIC In-Service register bits [255:224] (R/O)
818H 2072 IA32_X2APIC_TMR0 Core x2APIC Trigger Mode register bits [31:0] (R/O)
819H 2073 IA32_X2APIC_TMR1 Core x2APIC Trigger Mode register bits [63:32] (R/O)
81AH 2074 IA32_X2APIC_TMR2 Core x2APIC Trigger Mode register bits [95:64] (R/O)
81BH 2075 IA32_X2APIC_TMR3 Core x2APIC Trigger Mode register bits [127:96] (R/O)
81CH 2076 IA32_X2APIC_TMR4 Core x2APIC Trigger Mode register bits [159:128] (R/O)
81DH 2077 IA32_X2APIC_TMR5 Core x2APIC Trigger Mode register bits [191:160] (R/O)
81EH 2078 IA32_X2APIC_TMR6 Core x2APIC Trigger Mode register bits [223:192] (R/O)
81FH 2079 IA32_X2APIC_TMR7 Core x2APIC Trigger Mode register bits [255:224] (R/O)
820H 2080 IA32_X2APIC_IRR0 Core x2APIC Interrupt Request register bits [31:0] (R/O)
821H 2081 IA32_X2APIC_IRR1 Core x2APIC Interrupt Request register bits [63:32] (R/O)
822H 2082 IA32_X2APIC_IRR2 Core x2APIC Interrupt Request register bits [95:64] (R/O)
823H 2083 IA32_X2APIC_IRR3 Core x2APIC Interrupt Request register bits [127:96] (R/O)
Vol. 4 2-121
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
824H 2084 IA32_X2APIC_IRR4 Core x2APIC Interrupt Request register bits [159:128]
(R/O)
825H 2085 IA32_X2APIC_IRR5 Core x2APIC Interrupt Request register bits [191:160]
(R/O)
826H 2086 IA32_X2APIC_IRR6 Core x2APIC Interrupt Request register bits [223:192]
(R/O)
827H 2087 IA32_X2APIC_IRR7 Core x2APIC Interrupt Request register bits [255:224]
(R/O)
828H 2088 IA32_X2APIC_ESR Core x2APIC Error Status register (R/W)
82FH 2095 IA32_X2APIC_LVT_CMCI Core x2APIC LVT Corrected Machine Check Interrupt
register (R/W)
830H 2096 IA32_X2APIC_ICR Core x2APIC Interrupt Command register (R/W)
832H 2098 IA32_X2APIC_LVT_TIMER Core x2APIC LVT Timer Interrupt register (R/W)
833H 2099 IA32_X2APIC_LVT_THERMAL Core x2APIC LVT Thermal Sensor Interrupt register (R/W)
834H 2100 IA32_X2APIC_LVT_PMI Core x2APIC LVT Performance Monitor register (R/W)
835H 2101 IA32_X2APIC_LVT_LINT0 Core x2APIC LVT LINT0 register (R/W)
836H 2102 IA32_X2APIC_LVT_LINT1 Core x2APIC LVT LINT1 register (R/W)
837H 2103 IA32_X2APIC_LVT_ERROR Core x2APIC LVT Error register (R/W)
838H 2104 IA32_X2APIC_INIT_COUNT Core x2APIC Initial Count register (R/W)
839H 2105 IA32_X2APIC_CUR_COUNT Core x2APIC Current Count register (R/O)
83EH 2110 IA32_X2APIC_DIV_CONF Core x2APIC Divide Configuration register (R/W)
83FH 2111 IA32_X2APIC_SELF_IPI Core x2APIC Self IPI register (W/O)
C8FH 3215 IA32_PQR_ASSOC Core Resource Association Register (R/W)
31:0 Reserved
33:32 COS (R/W)
63: 34 Reserved
D10H 3344 IA32_L2_QOS_MASK_0 Module L2 Class Of Service Mask - COS 0 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
0:7 CBM: Bit vector of available L2 ways for COS 0
enforcement.
63:8 Reserved
D11H 3345 IA32_L2_QOS_MASK_1 Module L2 Class Of Service Mask - COS 1 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.
0:7 CBM: Bit vector of available L2 ways for COS 0
enforcement.
63:8 Reserved
D12H 3346 IA32_L2_QOS_MASK_2 Module L2 Class Of Service Mask - COS 2 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.
0:7 CBM: Bit vector of available L2 ways for COS 0
enforcement.
2-122 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on the Goldmont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:8 Reserved
D13H 3347 IA32_L2_QOS_MASK_3 Package L2 Class Of Service Mask - COS 3 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
0:19 CBM: Bit vector of available L2 ways for COS 3
enforcement.
63:20 Reserved
D90H 3472 IA32_BNDCFGS Core See Table 2-2.
DA0H 3488 IA32_XSS Core See Table 2-2.
See Table 2-6, and Table 2-12 for MSR definitions applicable to processors with CPUID signature 06_5CH.
Table 2-13. MSRs in Intel Atom® Processors Based on the Goldmont Plus Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3AH 58 IA32_FEATURE_CONTROL Core Control Features in Intel 64Processor (R/W)
See Table 2-2.
0 Lock (R/WL)
1 Enable VMX inside SMX operation (R/WL)
2 Enable VMX outside SMX operation (R/WL)
14:8 SENTER local functions enables (R/WL)
15 SENTER global functions enable (R/WL)
17 SGX Launch Control Enable (R/WL)
This bit must be set to enable runtime reconfiguration
of SGX Launch Control via IA32_SGXLEPUBKEYHASHn
MSR.
Valid if CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
18 SGX global functions enable (R/WL)
Vol. 4 2-123
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-13. MSRs in Intel Atom® Processors Based on the Goldmont Plus Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:19 Reserved
8CH 140 IA32_SGXLEPUBKEYHASH0 Core See Table 2-2.
8DH 141 IA32_SGXLEPUBKEYHASH1 Core See Table 2-2.
8EH 142 IA32_SGXLEPUBKEYHASH2 Core See Table 2-2.
8FH 143 IA32_SGXLEPUBKEYHASH3 Core See Table 2-2.
3F1H 1009 MSR_PEBS_ENABLE Core (R/W) See Table 2-2. See Section 18.6.2.4, “Processor
Event Based Sampling (PEBS).”
0 Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC0.
1 Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC1.
2 Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC2.
3 Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC3.
31:4 Reserved
32 Enable PEBS trigger and recording for
IA32_FIXED_CTR0.
33 Enable PEBS trigger and recording for
IA32_FIXED_CTR1.
34 Enable PEBS trigger and recording for
IA32_FIXED_CTR2.
63:35 Reserved
570H 1392 IA32_RTIT_CTL Core Trace Control Register (R/W)
0 TraceEn
1 CYCEn
2 OS
3 User
4 PwrEvtEn
5 FUPonPTW
6 FabricEn
7 CR3 filter
8 ToPA
Writing 0 will #GP if also setting TraceEn.
9 MTCEn
10 TSCEn
11 DisRETC
2-124 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-13. MSRs in Intel Atom® Processors Based on the Goldmont Plus Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
12 PTWEn
13 BranchEn
17:14 MTCFreq
18 Reserved, must be zero.
22:19 CYCThresh
23 Reserved, must be zero.
27:24 PSBFreq
31:28 Reserved, must be zero.
35:32 ADDR0_CFG
39:36 ADDR1_CFG
63:40 Reserved, must be zero.
680H 1664 MSR_LASTBRANCH_0_FROM_IP Core Last Branch Record 0 From IP (R/W)
One of the three MSRs that make up the first entry of
the 32-entry LBR stack. The From_IP part of the stack
contains pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 17.7, “Last Branch, Call Stack, Interrupt, and
Exception Recording for Processors based on
Goldmont Plus Microarchitecture.”
681H 1665 MSR_LASTBRANCH_i_FROM_IP Core Last Branch Record i From IP (R/W)
- - See description of MSR_LASTBRANCH_0_FROM_IP; i
69FH 1695 = 1-31.
6C0H 1728 MSR_LASTBRANCH_0_TO_IP Core Last Branch Record 0 To IP (R/W)
One of the three MSRs that make up the first entry of
the 32-entry LBR stack. The To_IP part of the stack
contains pointers to the Destination instruction. See
also:
• Section 17.7, “Last Branch, Call Stack, Interrupt, and
Exception Recording for Processors based on
Goldmont Plus Microarchitecture.”
6C1H 1729 MSR_LASTBRANCH_i_TO_IP Core Last Branch Record i To IP (R/W)
- - See description of MSR_LASTBRANCH_0_TO_IP; i = 1-
6DFH 1759 31.
DC0H 3520 MSR_LASTBRANCH_INFO_0 Core Last Branch Record 0 Additional Information (R/W)
One of the three MSRs that make up the first entry of
the 32-entry LBR stack. This part of the stack
contains flag and elapsed cycle information. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 17.9.1, “LBR Stack.”
DC1H 3521 MSR_LASTBRANCH_INFO_1 Core Last Branch Record 1 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC2H 3522 MSR_LASTBRANCH_INFO_2 Core Last Branch Record 2 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Vol. 4 2-125
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-13. MSRs in Intel Atom® Processors Based on the Goldmont Plus Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
DC3H 3523 MSR_LASTBRANCH_INFO_3 Core Last Branch Record 3 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC4H 3524 MSR_LASTBRANCH_INFO_4 Core Last Branch Record 4 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC5H 3525 MSR_LASTBRANCH_INFO_5 Core Last Branch Record 5 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC6H 3526 MSR_LASTBRANCH_INFO_6 Core Last Branch Record 6 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC7H 3527 MSR_LASTBRANCH_INFO_7 Core Last Branch Record 7 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC8H 3528 MSR_LASTBRANCH_INFO_8 Core Last Branch Record 8 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC9H 3529 MSR_LASTBRANCH_INFO_9 Core Last Branch Record 9 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCAH 3530 MSR_LASTBRANCH_INFO_10 Core Last Branch Record 10 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCBH 3531 MSR_LASTBRANCH_INFO_11 Core Last Branch Record 11 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCCH 3532 MSR_LASTBRANCH_INFO_12 Core Last Branch Record 12 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCDH 3533 MSR_LASTBRANCH_INFO_13 Core Last Branch Record 13 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCEH 3534 MSR_LASTBRANCH_INFO_14 Core Last Branch Record 14 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCFH 3535 MSR_LASTBRANCH_INFO_15 Core Last Branch Record 15 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD0H 3536 MSR_LASTBRANCH_INFO_16 Core Last Branch Record 16 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD1H 3537 MSR_LASTBRANCH_INFO_17 Core Last Branch Record 17 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD2H 3538 MSR_LASTBRANCH_INFO_18 Core Last Branch Record 18 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD3H 3539 MSR_LASTBRANCH_INFO_19 Core Last Branch Record 19 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD4H 3520 MSR_LASTBRANCH_INFO_20 Core Last Branch Record 20 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD5H 3521 MSR_LASTBRANCH_INFO_21 Core Last Branch Record 21 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
2-126 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-13. MSRs in Intel Atom® Processors Based on the Goldmont Plus Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
DD6H 3522 MSR_LASTBRANCH_INFO_22 Core Last Branch Record 22 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD7H 3523 MSR_LASTBRANCH_INFO_23 Core Last Branch Record 23 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD8H 3524 MSR_LASTBRANCH_INFO_24 Core Last Branch Record 24 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD9H 3525 MSR_LASTBRANCH_INFO_25 Core Last Branch Record 25 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDAH 3526 MSR_LASTBRANCH_INFO_26 Core Last Branch Record 26 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDBH 3527 MSR_LASTBRANCH_INFO_27 Core Last Branch Record 27 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDCH 3528 MSR_LASTBRANCH_INFO_28 Core Last Branch Record 28 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDDH 3529 MSR_LASTBRANCH_INFO_29 Core Last Branch Record 29 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDEH 3530 MSR_LASTBRANCH_INFO_30 Core Last Branch Record 30 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDFH 3531 MSR_LASTBRANCH_INFO_31 Core Last Branch Record 31 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
See Table 2-6, Table 2-12 and Table 2-13 for MSR definitions applicable to processors with CPUID signature 06_7AH.
Vol. 4 2-127
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-14. MSRs in Intel Atom® Processors Based on the Tremont Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
33H 51 MSR_TEST_CTRL Core Test Control Register
28:0 Reserved.
29 Enable #AC(0) exception for split locked accesses:
Cause #AC(0) exception for split locked access at all
CPL irrespective of CR0.AM or EFLAGS.AC. If bits 29
and 31 are both set, bit 29 takes precedence.
30 Reserved.
31 Reserved.
CFH 207 IA32_CORE_CAPABILITIES Core IA32 Core Capabilities Register
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
4:0 Reserved.
5 Bit 29 of MSR_TEST_CTRL (address 33H) supported.
63:6 Reserved.
3F1H 1009 MSR_PEBS_ENABLE Core (R/W) See Table 2-2. See Section 18.6.2.4, “Processor
Event Based Sampling (PEBS)”.
n:0 Enable PEBS trigger and recording for the programmed
event (precise or otherwise) on IA32_PMCx. The
maximum value n can be determined from
CPUID.0AH:EAX[15:8].
31:n+1 Reserved.
32+m:32 Enable PEBS trigger and recording for
IA32_FIXED_CTRx. The maximum value m can be
determined from CPUID.0AH:EDX[4:0].
59:33+m Reserved.
60 Pend a PerfMon Interrupt (PMI) after each PEBS event.
62:61 Specifies PEBS output destination. Encodings:
00B: DS Save Area
01B: Intel PT trace output. Supported if
IA32_PERF_CAPABILITIES.PEBS_OUTPUT_PT_AVAIL[
16] and CPUID.07H.0.EBX[25] are set.
10B: Reserved
11B: Reserved
63 Reserved.
1309H 4873 MSR_RELOAD_FIXED_CTRx Reload value for IA32_FIXED_CTRx (R/W)
- -
47:0 Value loaded into IA32_FIXED_CTRx when a PEBS
130BH 4875
record is generated while PEBS_EN_FIXEDx = 1 and
PEBS_OUTPUT = 01B in IA32_PEBS_ENABLE, and
FIXED_CTRx is overflowed.
63:48 Reserved.
2-128 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-14. MSRs in Intel Atom® Processors Based on the Tremont Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
14C1H 5313 MSR_RELOAD_PMCx Reload value for IA32_PMCx (R/W)
- -
47:0 Value loaded into IA32_PMCx when a PEBS record is
14C8H 5320
generated while PEBS_EN_PMCx = 1 and
PEBS_OUTPUT = 01B in IA32_PEBS_ENABLE, and
PMCx is overflowed.
63:48 Reserved.
See Table 2-6, Table 2-12, Table 2-13 and Table 2-14 for MSR definitions applicable to processors with CPUID signature 06_86H.
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
0H 0 IA32_P5_MC_ADDR Thread See Section 2.23, “MSRs in Pentium Processors.”
1H 1 IA32_P5_MC_TYPE Thread See Section 2.23, “MSRs in Pentium Processors.”
6H 6 IA32_MONITOR_FILTER_SIZE Thread See Section 8.10.5, “Monitor/Mwait Address Range
Determination” and Table 2-2.
10H 16 IA32_TIME_STAMP_COUNTER Thread See Section 17.17, “Time-Stamp Counter,” and see
Table 2-2.
17H 23 IA32_PLATFORM_ID Package Platform ID (R)
See Table 2-2.
17H 23 MSR_PLATFORM_ID Package Model Specific Platform ID (R)
49:0 Reserved
52:50 See Table 2-2.
63:53 Reserved
1BH 27 IA32_APIC_BASE Thread See Section 10.4.4, “Local APIC Status and Location,”
and Table 2-2.
Vol. 4 2-129
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
34H 52 MSR_SMI_COUNT Thread SMI Counter (R/O)
2-130 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
47:40 Package Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the
processor can operate, in units of 133.33MHz.
63:48 Reserved
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Core C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States. See http://biosbits.org.
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package. The
default is set as factory-configured package C-state
limit.
The following C-state code name encodings are
supported:
000b: C0 (no package C-sate support)
001b: C1 (Behavior is the same as 000b)
010b: C3
011b: C6
100b: C7
101b and 110b: Reserved
111: No package C-state limit.
Note: This field cannot be used to limit package C-state
to C3.
9:3 Reserved
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE to
MWAIT instructions.
14:11 Reserved
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
23:16 Reserved
24 Interrupt filtering enable (R/W)
When set, processor cores in a deep C-State will wake
only when the event message is destined for that core.
When 0, all processor cores in a deep C-State will wake
for an event message.
25 C3 state auto demotion enable (R/W)
When set, the processor will conditionally demote
C6/C7 requests to C3 based on uncore auto-demote
information.
Vol. 4 2-131
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
26 C1 state auto demotion enable (R/W)
When set, the processor will conditionally demote
C3/C6/C7 requests to C1 based on uncore auto-demote
information.
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Package C State Demotion Enable (R/W)
30 Package C State UnDemotion Enable (R/W)
63:31 Reserved
E4H 228 MSR_PMG_IO_CAPTURE_BASE Core Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
15:0 LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO
redirection. If IO MWAIT Redirection is enabled, reads to
this address will be consumed by the power
management logic and decoded to MWAIT instructions.
When IO port address redirection is enabled, this is the
IO port address reported to the OS/software.
18:16 C-state Range (R/W)
Specifies the encoding value of the maximum C-State
code name to be included when IO read to MWAIT
redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include.
001b - C6 is the max C-State to include.
010b - C7 is the max C-State to include.
63:19 Reserved
E7H 231 IA32_MPERF Thread Maximum Performance Frequency Clock Count (RW)
See Table 2-2.
E8H 232 IA32_APERF Thread Actual Performance Frequency Clock Count (RW)
See Table 2-2.
FEH 254 IA32_MTRRCAP Thread See Table 2-2.
174H 372 IA32_SYSENTER_CS Thread See Table 2-2.
175H 373 IA32_SYSENTER_ESP Thread See Table 2-2.
176H 374 IA32_SYSENTER_EIP Thread See Table 2-2.
179H 377 IA32_MCG_CAP Thread See Table 2-2.
17AH 378 IA32_MCG_STATUS Thread Global Machine Check Status
2-132 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
0 RIPV
When set, bit indicates that the instruction addressed
by the instruction pointer pushed on the stack (when
the machine check was generated) can be used to
restart the program. If cleared, the program cannot be
reliably restarted.
1 EIPV
When set, bit indicates that the instruction addressed
by the instruction pointer pushed on the stack (when
the machine check was generated) is directly
associated with the error.
2 MCIP
When set, bit indicates that a machine check has been
generated. If a second machine check is detected while
this bit is still set, the processor enters a shutdown
state. Software should write this bit to 0 after
processing a machine check exception.
63:3 Reserved
186H 390 IA32_PERFEVTSEL0 Thread See Table 2-2.
7:0 Event Select
15:8 UMask
16 USR
17 OS
18 Edge
19 PC
20 INT
21 AnyThread
22 EN
23 INV
31:24 CMASK
63:32 Reserved
187H 391 IA32_PERFEVTSEL1 Thread See Table 2-2.
188H 392 IA32_PERFEVTSEL2 Thread See Table 2-2.
189H 393 IA32_PERFEVTSEL3 Thread See Table 2-2.
198H 408 IA32_PERF_STATUS Core See Table 2-2.
15:0 Current Performance State Value.
63:16 Reserved
199H 409 IA32_PERF_CTL Thread See Table 2-2.
Vol. 4 2-133
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
19AH 410 IA32_CLOCK_MODULATION Thread Clock Modulation (R/W)
See Table 2-2.
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
0 Reserved
3:1 On demand Clock Modulation Duty Cycle (R/W)
4 On demand Clock Modulation Enable (R/W)
63:5 Reserved
19BH 411 IA32_THERM_INTERRUPT Core Thermal Interrupt Control (R/W)
See Table 2-2.
19CH 412 IA32_THERM_STATUS Core Thermal Monitor Status (R/W)
See Table 2-2.
1A0H 416 IA32_MISC_ENABLE Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled
and disabled.
0 Thread Fast-Strings Enable
See Table 2-2.
2:1 Reserved
3 Thread Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 1.
6:4 Reserved
7 Thread Performance Monitoring Available (R)
See Table 2-2.
10:8 Reserved
11 Thread Branch Trace Storage Unavailable (RO)
See Table 2-2.
12 Thread Processor Event Based Sampling Unavailable (RO)
See Table 2-2.
15:13 Reserved
16 Package Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
18 Thread ENABLE MONITOR FSM. (R/W) See Table 2-2.
21:19 Reserved
22 Thread Limit CPUID Maxval (R/W)
See Table 2-2.
23 Thread xTPR Message Disable (R/W)
See Table 2-2.
33:24 Reserved
2-134 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
34 Thread XD Bit Disable (R/W)
See Table 2-2.
37:35 Reserved
38 Package Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo
Boost Technology, the turbo mode feature is disabled
and the IDA_Enable feature flag will be clear
(CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA,
CPUID.06H: EAX[1] reports the processor’s support of
turbo mode is enabled.
Note: The power-on default value is used by BIOS to
detect hardware support of turbo mode. If the power-
on default value is 1, turbo mode is available in the
processor. If the power-on default value is 0, turbo
mode is not available.
63:39 Reserved
1A2H 418 MSR_TEMPERATURE_TARGET Thread Temperature Target
15:0 Reserved
23:16 Temperature Target (R)
The minimum temperature at which PROCHOT# will be
asserted. The value is degrees C.
63:24 Reserved
1A4H 420 MSR_MISC_FEATURE_CONTROL Miscellaneous Feature Control (R/W)
0 Core L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches
additional lines of code or data into the L2 cache.
1 Core L2 Adjacent Cache Line Prefetcher Disable (R/W)
If 1, disables the adjacent cache line prefetcher, which
fetches the cache line that comprises a cache line pair
(128 bytes).
2 Core DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which
fetches the next cache line into L1 data cache.
3 Core DCU IP Prefetcher Disable (R/W)
If 1, disables the L1 data cache IP prefetcher, which
uses sequential load history (based on instruction
pointer of previous loads) to determine whether to
prefetch additional lines.
63:4 Reserved
1A6H 422 MSR_OFFCORE_RSP_0 Thread Offcore Response Event Select Register (R/W)
Vol. 4 2-135
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1AAH 426 MSR_MISC_PWR_MGMT Miscellaneous Power Management Control
Various model specific features enumeration. See
http://biosbits.org.
0 Package EIST Hardware Coordination Disable (R/W)
When 0, enables hardware coordination of Enhanced
Intel Speedstep Technology request from processor
cores. When 1, disables hardware coordination of
Enhanced Intel Speedstep Technology requests.
1 Thread Energy/Performance Bias Enable (R/W)
This bit makes the IA32_ENERGY_PERF_BIAS register
(MSR 1B0h) visible to software with Ring 0 privileges.
This bit’s status (1 or 0) is also reflected by
CPUID.(EAX=06h):ECX[3].
63:2 Reserved
1ACH 428 MSR_TURBO_POWER_CURRENT_LIMIT See http://biosbits.org.
14:0 Package TDP Limit (R/W)
TDP limit in 1/8 Watt granularity.
15 Package TDP Limit Override Enable (R/W)
A value = 0 indicates override is not active; a value = 1
indicates override is active.
30:16 Package TDC Limit (R/W)
TDC limit in 1/8 Amp granularity.
31 Package TDC Limit Override Enable (R/W)
A value = 0 indicates override is not active; a value = 1
indicates override is active.
63:32 Reserved
1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0.
RW if MSR_PLATFORM_INFO.[28] = 1.
7:0 Package Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8 Package Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16 Package Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24 Package Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
63:32 Reserved
1C8H 456 MSR_LBR_SELECT Core Last Branch Record Filtering Select Register (R/W)
See Section 17.9.2, “Filtering of Last Branch Records.”
2-136 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
0 CPL_EQ_0
1 CPL_NEQ_0
2 JCC
3 NEAR_REL_CALL
4 NEAR_IND_CALL
5 NEAR_RET
6 NEAR_IND_JMP
7 NEAR_REL_JMP
8 FAR_BRANCH
63:9 Reserved
1C9H 457 MSR_LASTBRANCH_TOS Thread Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR
containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 680H).
1D9H 473 IA32_DEBUGCTL Thread Debug Control (R/W)
See Table 2-2.
1DDH 477 MSR_LER_FROM_LIP Thread Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that
the processor executed prior to the last exception that
was generated or the last interrupt that was handled.
1DEH 478 MSR_LER_TO_LIP Thread Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last
branch instruction that the processor executed prior to
the last exception that was generated or the last
interrupt that was handled.
1F2H 498 IA32_SMRR_PHYSBASE Core See Table 2-2.
Vol. 4 2-137
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
202H 514 IA32_MTRR_PHYSBASE1 Thread See Table 2-2.
203H 515 IA32_MTRR_PHYSMASK1 Thread See Table 2-2.
204H 516 IA32_MTRR_PHYSBASE2 Thread See Table 2-2.
205H 517 IA32_MTRR_PHYSMASK2 Thread See Table 2-2.
206H 518 IA32_MTRR_PHYSBASE3 Thread See Table 2-2.
207H 519 IA32_MTRR_PHYSMASK3 Thread See Table 2-2.
208H 520 IA32_MTRR_PHYSBASE4 Thread See Table 2-2.
209H 521 IA32_MTRR_PHYSMASK4 Thread See Table 2-2.
20AH 522 IA32_MTRR_PHYSBASE5 Thread See Table 2-2.
20BH 523 IA32_MTRR_PHYSMASK5 Thread See Table 2-2.
20CH 524 IA32_MTRR_PHYSBASE6 Thread See Table 2-2.
20DH 525 IA32_MTRR_PHYSMASK6 Thread See Table 2-2.
20EH 526 IA32_MTRR_PHYSBASE7 Thread See Table 2-2.
20FH 527 IA32_MTRR_PHYSMASK7 Thread See Table 2-2.
210H 528 IA32_MTRR_PHYSBASE8 Thread See Table 2-2.
211H 529 IA32_MTRR_PHYSMASK8 Thread See Table 2-2.
212H 530 IA32_MTRR_PHYSBASE9 Thread See Table 2-2.
213H 531 IA32_MTRR_PHYSMASK9 Thread See Table 2-2.
250H 592 IA32_MTRR_FIX64K_00000 Thread See Table 2-2.
258H 600 IA32_MTRR_FIX16K_80000 Thread See Table 2-2.
259H 601 IA32_MTRR_FIX16K_A0000 Thread See Table 2-2.
268H 616 IA32_MTRR_FIX4K_C0000 Thread See Table 2-2.
269H 617 IA32_MTRR_FIX4K_C8000 Thread See Table 2-2.
26AH 618 IA32_MTRR_FIX4K_D0000 Thread See Table 2-2.
26BH 619 IA32_MTRR_FIX4K_D8000 Thread See Table 2-2.
26CH 620 IA32_MTRR_FIX4K_E0000 Thread See Table 2-2.
26DH 621 IA32_MTRR_FIX4K_E8000 Thread See Table 2-2.
26EH 622 IA32_MTRR_FIX4K_F0000 Thread See Table 2-2.
26FH 623 IA32_MTRR_FIX4K_F8000 Thread See Table 2-2.
277H 631 IA32_PAT Thread See Table 2-2.
280H 640 IA32_MC0_CTL2 Package See Table 2-2.
281H 641 IA32_MC1_CTL2 Package See Table 2-2.
282H 642 IA32_MC2_CTL2 Core See Table 2-2.
283H 643 IA32_MC3_CTL2 Core See Table 2-2.
284H 644 IA32_MC4_CTL2 Core See Table 2-2.
285H 645 IA32_MC5_CTL2 Core See Table 2-2.
2-138 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
286H 646 IA32_MC6_CTL2 Package See Table 2-2.
287H 647 IA32_MC7_CTL2 Package See Table 2-2.
288H 648 IA32_MC8_CTL2 Package See Table 2-2.
2FFH 767 IA32_MTRR_DEF_TYPE Thread Default Memory Types (R/W)
See Table 2-2.
309H 777 IA32_FIXED_CTR0 Thread Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
30AH 778 IA32_FIXED_CTR1 Thread Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
30BH 779 IA32_FIXED_CTR2 Thread Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
345H 837 IA32_PERF_CAPABILITIES Thread See Table 2-2. See Section 17.4.1, “IA32_DEBUGCTL
MSR.”
5:0 LBR Format
See Table 2-2.
6 PEBS Record Format
7 PEBSSaveArchRegs
See Table 2-2.
11:8 PEBS_REC_FORMAT
See Table 2-2.
12 SMM_FREEZE
See Table 2-2.
63:13 Reserved
38DH 909 IA32_FIXED_CTR_CTRL Thread Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
38EH 910 IA32_PERF_GLOBAL_STATUS Thread See Table 2-2. See Section 18.6.2.2, “Global Counter
Control Facilities.”
38EH 910 MSR_PERF_GLOBAL_STATUS Thread Provides single-bit status used by software to query
the overflow condition of each performance counter.
(RO)
61 UNC_Ovf
Uncore overflowed if 1.
38FH 911 IA32_PERF_GLOBAL_CTRL Thread See Table 2-2. See Section 18.6.2.2, “Global Counter
Control Facilities.”
390H 912 IA32_PERF_GLOBAL_OVF_CTRL Thread See Table 2-2. See Section 18.6.2.2, “Global Counter
Control Facilities.” Allows software to clear counter
overflow conditions on any combination of fixed-
function PMCs (IA32_FIXED_CTRx) or general-purpose
PMCs via a single WRMSR.
390H 912 MSR_PERF_GLOBAL_OVF_CTRL Thread (R/W)
Vol. 4 2-139
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
61 CLR_UNC_Ovf
Set 1 to clear UNC_Ovf.
3F1H 1009 MSR_PEBS_ENABLE Thread See Section 18.3.1.1.1, “Processor Event Based
Sampling (PEBS).”
0 Enable PEBS on IA32_PMC0 (R/W)
1 Enable PEBS on IA32_PMC1 (R/W)
2 Enable PEBS on IA32_PMC2 (R/W)
3 Enable PEBS on IA32_PMC3 (R/W)
31:4 Reserved
32 Enable Load Latency on IA32_PMC0 (R/W)
33 Enable Load Latency on IA32_PMC1 (R/W)
34 Enable Load Latency on IA32_PMC2 (R/W)
35 Enable Load Latency on IA32_PMC3 (R/W)
63:36 Reserved
3F6H 1014 MSR_PEBS_LD_LAT Thread See Section 18.3.1.1.2, “Load Latency Performance
Monitoring Facility.”
15:0 Minimum threshold latency value of tagged load
operation that will be counted. (R/W)
63:36 Reserved
3F8H 1016 MSR_PKG_C3_RESIDENCY Package Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0 Package C3 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C3 states. Count at the same frequency as the
TSC.
3F9H 1017 MSR_PKG_C6_RESIDENCY Package Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0 Package C6 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C6 states. Count at the same frequency as the
TSC.
3FAH 1018 MSR_PKG_C7_RESIDENCY Package Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0 Package C7 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C7 states. Count at the same frequency as the
TSC.
2-140 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3FCH 1020 MSR_CORE_C3_RESIDENCY Core Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0 CORE C3 Residency Counter (R/O)
Value since last reset that this core is in processor-
specific C3 states. Count at the same frequency as the
TSC.
3FDH 1021 MSR_CORE_C6_RESIDENCY Core Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0 CORE C6 Residency Counter (R/O)
Value since last reset that this core is in processor-
specific C6 states. Count at the same frequency as the
TSC.
400H 1024 IA32_MC0_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H 1025 IA32_MC0_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H 1026 IA32_MC0_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
403H 1027 IA32_MC0_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
404H 1028 IA32_MC1_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H 1029 IA32_MC1_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
406H 1030 IA32_MC1_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
407H 1031 IA32_MC1_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
408H 1032 IA32_MC2_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H 1033 IA32_MC2_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH 1034 IA32_MC2_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
Vol. 4 2-141
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
40BH 1035 IA32_MC2_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
40CH 1036 IA32_MC3_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH 1037 IA32_MC3_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH 1038 IA32_MC3_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
40FH 1039 IA32_MC3_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
410H 1040 IA32_MC4_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H 1041 IA32_MC4_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H 1042 IA32_MC4_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the MSR_MC3_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
413H 1043 IA32_MC4_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
414H 1044 IA32_MC5_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
415H 1045 IA32_MC5_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
416H 1046 IA32_MC5_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
417H 1047 IA32_MC5_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
418H 1048 IA32_MC6_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
419H 1049 IA32_MC6_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
41AH 1050 IA32_MC6_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
41BH 1051 IA32_MC6_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
41CH 1052 IA32_MC7_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
41DH 1053 IA32_MC7_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
41EH 1054 IA32_MC7_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
41FH 1055 IA32_MC7_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
420H 1056 IA32_MC8_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
421H 1057 IA32_MC8_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
422H 1058 IA32_MC8_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
423H 1059 IA32_MC8_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
2-142 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
480H 1152 IA32_VMX_BASIC Thread Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2.
See Appendix A.1, “Basic VMX Information.”
481H 1153 IA32_VMX_PINBASED_CTLS Thread Capability Reporting Register of Pin-based
VM-execution Controls (R/O)
See Table 2-2.
See Appendix A.3, “VM-Execution Controls.”
482H 1154 IA32_VMX_PROCBASED_CTLS Thread Capability Reporting Register of Primary Processor-
Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
483H 1155 IA32_VMX_EXIT_CTLS Thread Capability Reporting Register of VM-Exit Controls (R/O)
See Table 2-2.
See Appendix A.4, “VM-Exit Controls.”
484H 1156 IA32_VMX_ENTRY_CTLS Thread Capability Reporting Register of VM-Entry Controls
(R/O)
See Table 2-2.
See Appendix A.5, “VM-Entry Controls.”
485H 1157 IA32_VMX_MISC Thread Reporting Register of Miscellaneous VMX Capabilities
(R/O)
See Table 2-2.
See Appendix A.6, “Miscellaneous Data.”
486H 1158 IA32_VMX_CR0_FIXED0 Thread Capability Reporting Register of CR0 Bits Fixed to 0
(R/O)
See Table 2-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
487H 1159 IA32_VMX_CR0_FIXED1 Thread Capability Reporting Register of CR0 Bits Fixed to 1
(R/O)
See Table 2-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
488H 1160 IA32_VMX_CR4_FIXED0 Thread Capability Reporting Register of CR4 Bits Fixed to 0
(R/O)
See Table 2-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
489H 1161 IA32_VMX_CR4_FIXED1 Thread Capability Reporting Register of CR4 Bits Fixed to 1
(R/O)
See Table 2-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
48AH 1162 IA32_VMX_VMCS_ENUM Thread Capability Reporting Register of VMCS Field
Enumeration (R/O)
See Table 2-2.
See Appendix A.9, “VMCS Enumeration.”
Vol. 4 2-143
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
48BH 1163 IA32_VMX_PROCBASED_CTLS2 Thread Capability Reporting Register of Secondary Processor-
Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
600H 1536 IA32_DS_AREA Thread DS Save Area (R/W)
See Table 2-2.
See Section 18.6.3.4, “Debug Store (DS) Mechanism.”
680H 1664 MSR_LASTBRANCH_0_FROM_IP Thread Last Branch Record 0 From IP (R/W)
One of sixteen pairs of last branch record registers on
the last branch record stack. The From_IP part of the
stack contains pointers to the source instruction. See
also:
• Last Branch Record Stack TOS at 1C9H.
• Section 17.9.1 and record format in Section 17.4.8.1.
681H 1665 MSR_LASTBRANCH_1_FROM_IP Thread Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
682H 1666 MSR_LASTBRANCH_2_FROM_IP Thread Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
683H 1667 MSR_LASTBRANCH_3_FROM_IP Thread Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
684H 1668 MSR_LASTBRANCH_4_FROM_IP Thread Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
685H 1669 MSR_LASTBRANCH_5_FROM_IP Thread Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
686H 1670 MSR_LASTBRANCH_6_FROM_IP Thread Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
687H 1671 MSR_LASTBRANCH_7_FROM_IP Thread Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
688H 1672 MSR_LASTBRANCH_8_FROM_IP Thread Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
689H 1673 MSR_LASTBRANCH_9_FROM_IP Thread Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68AH 1674 MSR_LASTBRANCH_10_FROM_IP Thread Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68BH 1675 MSR_LASTBRANCH_11_FROM_IP Thread Last Branch Record 11 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68CH 1676 MSR_LASTBRANCH_12_FROM_IP Thread Last Branch Record 12 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68DH 1677 MSR_LASTBRANCH_13_FROM_IP Thread Last Branch Record 13 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
2-144 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
68EH 1678 MSR_LASTBRANCH_14_FROM_IP Thread Last Branch Record 14 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68FH 1679 MSR_LASTBRANCH_15_FROM_IP Thread Last Branch Record 15 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
6C0H 1728 MSR_LASTBRANCH_0_TO_IP Thread Last Branch Record 0 To IP (R/W)
One of sixteen pairs of last branch record registers on
the last branch record stack. This part of the stack
contains pointers to the destination instruction.
6C1H 1729 MSR_LASTBRANCH_1_TO_IP Thread Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C2H 1730 MSR_LASTBRANCH_2_TO_IP Thread Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C3H 1731 MSR_LASTBRANCH_3_TO_IP Thread Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C4H 1732 MSR_LASTBRANCH_4_TO_IP Thread Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C5H 1733 MSR_LASTBRANCH_5_TO_IP Thread Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C6H 1734 MSR_LASTBRANCH_6_TO_IP Thread Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C7H 1735 MSR_LASTBRANCH_7_TO_IP Thread Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C8H 1736 MSR_LASTBRANCH_8_TO_IP Thread Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C9H 1737 MSR_LASTBRANCH_9_TO_IP Thread Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CAH 1738 MSR_LASTBRANCH_10_TO_IP Thread Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CBH 1739 MSR_LASTBRANCH_11_TO_IP Thread Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CCH 1740 MSR_LASTBRANCH_12_TO_IP Thread Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CDH 1741 MSR_LASTBRANCH_13_TO_IP Thread Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CEH 1742 MSR_LASTBRANCH_14_TO_IP Thread Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CFH 1743 MSR_LASTBRANCH_15_TO_IP Thread Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
802H 2050 IA32_X2APIC_APICID Thread x2APIC ID Register (R/O)
Vol. 4 2-145
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
803H 2051 IA32_X2APIC_VERSION Thread x2APIC Version Register (R/O)
808H 2056 IA32_X2APIC_TPR Thread x2APIC Task Priority Register (R/W)
80AH 2058 IA32_X2APIC_PPR Thread x2APIC Processor Priority Register (R/O)
80BH 2059 IA32_X2APIC_EOI Thread x2APIC EOI Register (W/O)
80DH 2061 IA32_X2APIC_LDR Thread x2APIC Logical Destination Register (R/O)
80FH 2063 IA32_X2APIC_SIVR Thread x2APIC Spurious Interrupt Vector Register (R/W)
810H 2064 IA32_X2APIC_ISR0 Thread x2APIC In-Service Register Bits [31:0] (R/O)
811H 2065 IA32_X2APIC_ISR1 Thread x2APIC In-Service Register Bits [63:32] (R/O)
812H 2066 IA32_X2APIC_ISR2 Thread x2APIC In-Service Register Bits [95:64] (R/O)
813H 2067 IA32_X2APIC_ISR3 Thread x2APIC In-Service Register Bits [127:96] (R/O)
814H 2068 IA32_X2APIC_ISR4 Thread x2APIC In-Service Register Bits [159:128] (R/O)
815H 2069 IA32_X2APIC_ISR5 Thread x2APIC In-Service Register Bits [191:160] (R/O)
816H 2070 IA32_X2APIC_ISR6 Thread x2APIC In-Service Register Bits [223:192] (R/O)
817H 2071 IA32_X2APIC_ISR7 Thread x2APIC In-Service Register Bits [255:224] (R/O)
818H 2072 IA32_X2APIC_TMR0 Thread x2APIC Trigger Mode Register Bits [31:0] (R/O)
819H 2073 IA32_X2APIC_TMR1 Thread x2APIC Trigger Mode Register Bits [63:32] (R/O)
81AH 2074 IA32_X2APIC_TMR2 Thread x2APIC Trigger Mode Register Bits [95:64] (R/O)
81BH 2075 IA32_X2APIC_TMR3 Thread x2APIC Trigger Mode Register Bits [127:96] (R/O)
81CH 2076 IA32_X2APIC_TMR4 Thread x2APIC Trigger Mode Register Bits [159:128] (R/O)
81DH 2077 IA32_X2APIC_TMR5 Thread x2APIC Trigger Mode Register Bits [191:160] (R/O)
81EH 2078 IA32_X2APIC_TMR6 Thread x2APIC Trigger Mode Register Bits [223:192] (R/O)
81FH 2079 IA32_X2APIC_TMR7 Thread x2APIC Trigger Mode Register Bits [255:224] (R/O)
820H 2080 IA32_X2APIC_IRR0 Thread x2APIC Interrupt Request Register Bits [31:0] (R/O)
821H 2081 IA32_X2APIC_IRR1 Thread x2APIC Interrupt Request Register Bits [63:32] (R/O)
822H 2082 IA32_X2APIC_IRR2 Thread x2APIC Interrupt Request Register Bits [95:64] (R/O)
823H 2083 IA32_X2APIC_IRR3 Thread x2APIC Interrupt Request Register Bits [127:96] (R/O)
824H 2084 IA32_X2APIC_IRR4 Thread x2APIC Interrupt Request Register Bits [159:128] (R/O)
825H 2085 IA32_X2APIC_IRR5 Thread x2APIC Interrupt Request Register Bits [191:160] (R/O)
826H 2086 IA32_X2APIC_IRR6 Thread x2APIC Interrupt Request Register Bits [223:192] (R/O)
827H 2087 IA32_X2APIC_IRR7 Thread x2APIC Interrupt Request Register Bits [255:224] (R/O)
828H 2088 IA32_X2APIC_ESR Thread x2APIC Error Status Register (R/W)
82FH 2095 IA32_X2APIC_LVT_CMCI Thread x2APIC LVT Corrected Machine Check Interrupt Register
(R/W)
830H 2096 IA32_X2APIC_ICR Thread x2APIC Interrupt Command Register (R/W)
832H 2098 IA32_X2APIC_LVT_TIMER Thread x2APIC LVT Timer Interrupt Register (R/W)
833H 2099 IA32_X2APIC_LVT_THERMAL Thread x2APIC LVT Thermal Sensor Interrupt Register (R/W)
2-146 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
834H 2100 IA32_X2APIC_LVT_PMI Thread x2APIC LVT Performance Monitor Register (R/W)
835H 2101 IA32_X2APIC_LVT_LINT0 Thread x2APIC LVT LINT0 Register (R/W)
836H 2102 IA32_X2APIC_LVT_LINT1 Thread x2APIC LVT LINT1 Register (R/W)
837H 2103 IA32_X2APIC_LVT_ERROR Thread x2APIC LVT Error Register (R/W)
838H 2104 IA32_X2APIC_INIT_COUNT Thread x2APIC Initial Count Register (R/W)
839H 2105 IA32_X2APIC_CUR_COUNT Thread x2APIC Current Count Register (R/O)
83EH 2110 IA32_X2APIC_DIV_CONF Thread x2APIC Divide Configuration Register (R/W)
83FH 2111 IA32_X2APIC_SELF_IPI Thread x2APIC Self IPI Register (W/O)
C000_ IA32_EFER Thread Extended Feature Enables
0080H See Table 2-2.
C000_ IA32_STAR Thread System Call Target Address (R/W)
0081H See Table 2-2.
C000_ IA32_LSTAR Thread IA-32e Mode System Call Target Address (R/W)
0082H See Table 2-2.
C000_ IA32_FMASK Thread System Call Flag Mask (R/W)
0084H See Table 2-2.
C000_ IA32_FS_BASE Thread Map of BASE Address of FS (R/W)
0100H See Table 2-2.
C000_ IA32_GS_BASE Thread Map of BASE Address of GS (R/W)
0101H See Table 2-2.
C000_ IA32_KERNEL_GS_BASE Thread Swap Target of BASE Address of GS (R/W)
0102H See Table 2-2.
C000_ IA32_TSC_AUX Thread AUXILIARY TSC Signature (R/W)
0103H See Table 2-2 and Section 17.17.2, “IA32_TSC_AUX
Register and RDTSCP Support.”
2.8.1 Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series
Intel Xeon Processor 5500 and 3400 series support additional model-specific registers listed in Table 2-16. These
MSRs also apply to Intel Core i7 and i5 processor family CPUID signature with DisplayFamily_DisplayModel of
06_1AH, 06_1EH and 06_1FH, see Table 2-1.
Table 2-16. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1ADH 429 MSR_TURBO_RATIO_LIMIT Package Actual maximum turbo frequency is multiplied by
133.33MHz.
(Not available in model 06_2EH.)
Vol. 4 2-147
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-16. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
7:0 Maximum Turbo Ratio Limit 1C (R/O)
Maximum Turbo mode ratio limit with 1 core active.
15:8 Maximum Turbo Ratio Limit 2C (R/O)
Maximum Turbo mode ratio limit with 2 cores active.
23:16 Maximum Turbo Ratio Limit 3C (R/O)
Maximum Turbo mode ratio limit with 3 cores active.
31:24 Maximum Turbo Ratio Limit 4C (R/O)
Maximum Turbo mode ratio limit with 4 cores active.
63:32 Reserved
301H 769 MSR_GQ_SNOOP_MESF Package
0 From M to S (R/W)
1 From E to S (R/W)
2 From S to S (R/W)
3 From F to S (R/W)
4 From M to I (R/W)
5 From E to I (R/W)
6 From S to I (R/W)
7 From F to I (R/W)
63:8 Reserved
391H 913 MSR_UNCORE_PERF_GLOBAL_CTRL Package See Section 18.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
392H 914 MSR_UNCORE_PERF_GLOBAL_STATUS Package See Section 18.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
393H 915 MSR_UNCORE_PERF_GLOBAL_OVF_CTRL Package See Section 18.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
394H 916 MSR_UNCORE_FIXED_CTR0 Package See Section 18.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
395H 917 MSR_UNCORE_FIXED_CTR_CTRL Package See Section 18.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
396H 918 MSR_UNCORE_ADDR_OPCODE_MATCH Package See Section 18.3.1.2.3, “Uncore Address/Opcode
Match MSR.”
3B0H 960 MSR_UNCORE_PMC0 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B1H 961 MSR_UNCORE_PMC1 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B2H 962 MSR_UNCORE_PMC2 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B3H 963 MSR_UNCORE_PMC3 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B4H 964 MSR_UNCORE_PMC4 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
2-148 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-16. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3B5H 965 MSR_UNCORE_PMC5 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B6H 966 MSR_UNCORE_PMC6 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B7H 967 MSR_UNCORE_PMC7 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C0H 944 MSR_UNCORE_PERFEVTSEL0 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C1H 945 MSR_UNCORE_PERFEVTSEL1 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C2H 946 MSR_UNCORE_PERFEVTSEL2 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C3H 947 MSR_UNCORE_PERFEVTSEL3 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C4H 948 MSR_UNCORE_PERFEVTSEL4 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C5H 949 MSR_UNCORE_PERFEVTSEL5 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C6H 950 MSR_UNCORE_PERFEVTSEL6 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C7H 951 MSR_UNCORE_PERFEVTSEL7 Package See Section 18.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
Vol. 4 2-149
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
290H 656 IA32_MC16_CTL2 Package See Table 2-2.
291H 657 IA32_MC17_CTL2 Package See Table 2-2.
292H 658 IA32_MC18_CTL2 Package See Table 2-2.
293H 659 IA32_MC19_CTL2 Package See Table 2-2.
294H 660 IA32_MC20_CTL2 Package See Table 2-2.
295H 661 IA32_MC21_CTL2 Package See Table 2-2.
394H 816 MSR_W_PMON_FIXED_CTR Package Uncore W-box perfmon fixed counter.
395H 817 MSR_W_PMON_FIXED_CTR_CTL Package Uncore U-box perfmon fixed counter control MSR.
424H 1060 IA32_MC9_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
425H 1061 IA32_MC9_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
426H 1062 IA32_MC9_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
427H 1063 IA32_MC9_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
428H 1064 IA32_MC10_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
429H 1065 IA32_MC10_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
42AH 1066 IA32_MC10_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
42BH 1067 IA32_MC10_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
42CH 1068 IA32_MC11_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
42DH 1069 IA32_MC11_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
42EH 1070 IA32_MC11_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
42FH 1071 IA32_MC11_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
430H 1072 IA32_MC12_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
431H 1073 IA32_MC12_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
432H 1074 IA32_MC12_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
433H 1075 IA32_MC12_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
434H 1076 IA32_MC13_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
435H 1077 IA32_MC13_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
436H 1078 IA32_MC13_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
437H 1079 IA32_MC13_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
438H 1080 IA32_MC14_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
439H 1081 IA32_MC14_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
43AH 1082 IA32_MC14_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
43BH 1083 IA32_MC14_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
43CH 1084 IA32_MC15_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
2-150 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
43DH 1085 IA32_MC15_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
43EH 1086 IA32_MC15_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
43FH 1087 IA32_MC15_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
440H 1088 IA32_MC16_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
441H 1089 IA32_MC16_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
442H 1090 IA32_MC16_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
443H 1091 IA32_MC16_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
444H 1092 IA32_MC17_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
445H 1093 IA32_MC17_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
446H 1094 IA32_MC17_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
447H 1095 IA32_MC17_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
448H 1096 IA32_MC18_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
449H 1097 IA32_MC18_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
44AH 1098 IA32_MC18_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
44BH 1099 IA32_MC18_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
44CH 1100 IA32_MC19_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
44DH 1101 IA32_MC19_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
44EH 1102 IA32_MC19_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
44FH 1103 IA32_MC19_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
450H 1104 IA32_MC20_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
451H 1105 IA32_MC20_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
452H 1106 IA32_MC20_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
453H 1107 IA32_MC20_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
454H 1108 IA32_MC21_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
455H 1109 IA32_MC21_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and
Chapter 16.
456H 1110 IA32_MC21_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
457H 1111 IA32_MC21_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
C00H 3072 MSR_U_PMON_GLOBAL_CTRL Package Uncore U-box perfmon global control MSR.
C01H 3073 MSR_U_PMON_GLOBAL_STATUS Package Uncore U-box perfmon global status MSR.
C02H 3074 MSR_U_PMON_GLOBAL_OVF_CTRL Package Uncore U-box perfmon global overflow control MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
C10H 3088 MSR_U_PMON_EVNT_SEL Package Uncore U-box perfmon event select MSR.
C21H 3105 MSR_B0_PMON_BOX_STATUS Package Uncore B-box 0 perfmon local box status MSR.
C22H 3106 MSR_B0_PMON_BOX_OVF_CTRL Package Uncore B-box 0 perfmon local box overflow control
MSR.
C30H 3120 MSR_B0_PMON_EVNT_SEL0 Package Uncore B-box 0 perfmon event select MSR.
C41H 3137 MSR_S0_PMON_BOX_STATUS Package Uncore S-box 0 perfmon local box status MSR.
C42H 3138 MSR_S0_PMON_BOX_OVF_CTRL Package Uncore S-box 0 perfmon local box overflow control
MSR.
C50H 3152 MSR_S0_PMON_EVNT_SEL0 Package Uncore S-box 0 perfmon event select MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
C61H 3169 MSR_B1_PMON_BOX_STATUS Package Uncore B-box 1 perfmon local box status MSR.
C62H 3170 MSR_B1_PMON_BOX_OVF_CTRL Package Uncore B-box 1 perfmon local box overflow control
MSR.
C70H 3184 MSR_B1_PMON_EVNT_SEL0 Package Uncore B-box 1 perfmon event select MSR.
CA1H 3233 MSR_M0_PMON_BOX_STATUS Package Uncore M-box 0 perfmon local box status MSR.
CA2H 3234 MSR_M0_PMON_BOX_OVF_CTRL Package Uncore M-box 0 perfmon local box overflow control
MSR.
CA4H 3236 MSR_M0_PMON_TIMESTAMP Package Uncore M-box 0 perfmon time stamp unit select
MSR.
CA5H 3237 MSR_M0_PMON_DSP Package Uncore M-box 0 perfmon DSP unit select MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
CA6H 3238 MSR_M0_PMON_ISS Package Uncore M-box 0 perfmon ISS unit select MSR.
CA7H 3239 MSR_M0_PMON_MAP Package Uncore M-box 0 perfmon MAP unit select MSR.
CA8H 3240 MSR_M0_PMON_MSC_THR Package Uncore M-box 0 perfmon MIC THR select MSR.
CA9H 3241 MSR_M0_PMON_PGT Package Uncore M-box 0 perfmon PGT unit select MSR.
CAAH 3242 MSR_M0_PMON_PLD Package Uncore M-box 0 perfmon PLD unit select MSR.
CABH 3243 MSR_M0_PMON_ZDP Package Uncore M-box 0 perfmon ZDP unit select MSR.
CB0H 3248 MSR_M0_PMON_EVNT_SEL0 Package Uncore M-box 0 perfmon event select MSR.
CC1H 3265 MSR_S1_PMON_BOX_STATUS Package Uncore S-box 1 perfmon local box status MSR.
CC2H 3266 MSR_S1_PMON_BOX_OVF_CTRL Package Uncore S-box 1 perfmon local box overflow control
MSR.
CD0H 3280 MSR_S1_PMON_EVNT_SEL0 Package Uncore S-box 1 perfmon event select MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
CD6H 3286 MSR_S1_PMON_EVNT_SEL3 Package Uncore S-box 1 perfmon event select MSR.
CE1H 3297 MSR_M1_PMON_BOX_STATUS Package Uncore M-box 1 perfmon local box status MSR.
CE2H 3298 MSR_M1_PMON_BOX_OVF_CTRL Package Uncore M-box 1 perfmon local box overflow control
MSR.
CE4H 3300 MSR_M1_PMON_TIMESTAMP Package Uncore M-box 1 perfmon time stamp unit select
MSR.
CE5H 3301 MSR_M1_PMON_DSP Package Uncore M-box 1 perfmon DSP unit select MSR.
CE6H 3302 MSR_M1_PMON_ISS Package Uncore M-box 1 perfmon ISS unit select MSR.
CE7H 3303 MSR_M1_PMON_MAP Package Uncore M-box 1 perfmon MAP unit select MSR.
CE8H 3304 MSR_M1_PMON_MSC_THR Package Uncore M-box 1 perfmon MIC THR select MSR.
CE9H 3305 MSR_M1_PMON_PGT Package Uncore M-box 1 perfmon PGT unit select MSR.
CEAH 3306 MSR_M1_PMON_PLD Package Uncore M-box 1 perfmon PLD unit select MSR.
CEBH 3307 MSR_M1_PMON_ZDP Package Uncore M-box 1 perfmon ZDP unit select MSR.
CF0H 3312 MSR_M1_PMON_EVNT_SEL0 Package Uncore M-box 1 perfmon event select MSR.
D01H 3329 MSR_C0_PMON_BOX_STATUS Package Uncore C-box 0 perfmon local box status MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
D02H 3330 MSR_C0_PMON_BOX_OVF_CTRL Package Uncore C-box 0 perfmon local box overflow control
MSR.
D10H 3344 MSR_C0_PMON_EVNT_SEL0 Package Uncore C-box 0 perfmon event select MSR.
D21H 3361 MSR_C4_PMON_BOX_STATUS Package Uncore C-box 4 perfmon local box status MSR.
D22H 3362 MSR_C4_PMON_BOX_OVF_CTRL Package Uncore C-box 4 perfmon local box overflow control
MSR.
D30H 3376 MSR_C4_PMON_EVNT_SEL0 Package Uncore C-box 4 perfmon event select MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
D3AH 3386 MSR_C4_PMON_EVNT_SEL5 Package Uncore C-box 4 perfmon event select MSR.
D41H 3393 MSR_C2_PMON_BOX_STATUS Package Uncore C-box 2 perfmon local box status MSR.
D42H 3394 MSR_C2_PMON_BOX_OVF_CTRL Package Uncore C-box 2 perfmon local box overflow control
MSR.
D50H 3408 MSR_C2_PMON_EVNT_SEL0 Package Uncore C-box 2 perfmon event select MSR.
D61H 3425 MSR_C6_PMON_BOX_STATUS Package Uncore C-box 6 perfmon local box status MSR.
D62H 3426 MSR_C6_PMON_BOX_OVF_CTRL Package Uncore C-box 6 perfmon local box overflow control
MSR.
D70H 3440 MSR_C6_PMON_EVNT_SEL0 Package Uncore C-box 6 perfmon event select MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
D75H 3445 MSR_C6_PMON_CTR2 Package Uncore C-box 6 perfmon counter MSR.
D76H 3446 MSR_C6_PMON_EVNT_SEL3 Package Uncore C-box 6 perfmon event select MSR.
D81H 3457 MSR_C1_PMON_BOX_STATUS Package Uncore C-box 1 perfmon local box status MSR.
D82H 3458 MSR_C1_PMON_BOX_OVF_CTRL Package Uncore C-box 1 perfmon local box overflow control
MSR.
D90H 3472 MSR_C1_PMON_EVNT_SEL0 Package Uncore C-box 1 perfmon event select MSR.
DA1H 3489 MSR_C5_PMON_BOX_STATUS Package Uncore C-box 5 perfmon local box status MSR.
DA2H 3490 MSR_C5_PMON_BOX_OVF_CTRL Package Uncore C-box 5 perfmon local box overflow control
MSR.
DB0H 3504 MSR_C5_PMON_EVNT_SEL0 Package Uncore C-box 5 perfmon event select MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
DB1H 3505 MSR_C5_PMON_CTR0 Package Uncore C-box 5 perfmon counter MSR.
DB2H 3506 MSR_C5_PMON_EVNT_SEL1 Package Uncore C-box 5 perfmon event select MSR.
DC1H 3521 MSR_C3_PMON_BOX_STATUS Package Uncore C-box 3 perfmon local box status MSR.
DC2H 3522 MSR_C3_PMON_BOX_OVF_CTRL Package Uncore C-box 3 perfmon local box overflow control
MSR.
DD0H 3536 MSR_C3_PMON_EVNT_SEL0 Package Uncore C-box 3 perfmon event select MSR.
Vol. 4 2-159
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
DE0H 3552 MSR_C7_PMON_BOX_CTRL Package Uncore C-box 7 perfmon local box control MSR.
DE1H 3553 MSR_C7_PMON_BOX_STATUS Package Uncore C-box 7 perfmon local box status MSR.
DE2H 3554 MSR_C7_PMON_BOX_OVF_CTRL Package Uncore C-box 7 perfmon local box overflow control
MSR.
DF0H 3568 MSR_C7_PMON_EVNT_SEL0 Package Uncore C-box 7 perfmon event select MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E0AH 3594 MSR_R0_PMON_IPERF0_P6 Package Uncore R-box 0 perfmon IPERF0 unit Port 6 select
MSR.
E0BH 3595 MSR_R0_PMON_IPERF0_P7 Package Uncore R-box 0 perfmon IPERF0 unit Port 7 select
MSR.
E0CH 3596 MSR_R0_PMON_QLX_P0 Package Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
E0DH 3597 MSR_R0_PMON_QLX_P1 Package Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
E0EH 3598 MSR_R0_PMON_QLX_P2 Package Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
E0FH 3599 MSR_R0_PMON_QLX_P3 Package Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
E10H 3600 MSR_R0_PMON_EVNT_SEL0 Package Uncore R-box 0 perfmon event select MSR.
Vol. 4 2-161
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E25H 3621 MSR_R1_PMON_IPERF1_P9 Package Uncore R-box 1 perfmon IPERF1 unit Port 9 select
MSR.
E26H 3622 MSR_R1_PMON_IPERF1_P10 Package Uncore R-box 1 perfmon IPERF1 unit Port 10 select
MSR.
E27H 3623 MSR_R1_PMON_IPERF1_P11 Package Uncore R-box 1 perfmon IPERF1 unit Port 11 select
MSR.
E28H 3624 MSR_R1_PMON_IPERF1_P12 Package Uncore R-box 1 perfmon IPERF1 unit Port 12 select
MSR.
E29H 3625 MSR_R1_PMON_IPERF1_P13 Package Uncore R-box 1 perfmon IPERF1 unit Port 13 select
MSR.
E2AH 3626 MSR_R1_PMON_IPERF1_P14 Package Uncore R-box 1 perfmon IPERF1 unit Port 14 select
MSR.
E2BH 3627 MSR_R1_PMON_IPERF1_P15 Package Uncore R-box 1 perfmon IPERF1 unit Port 15 select
MSR.
E2CH 3628 MSR_R1_PMON_QLX_P4 Package Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
E2DH 3629 MSR_R1_PMON_QLX_P5 Package Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
E2EH 3630 MSR_R1_PMON_QLX_P6 Package Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
E2FH 3631 MSR_R1_PMON_QLX_P7 Package Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
E30H 3632 MSR_R1_PMON_EVNT_SEL8 Package Uncore R-box 1 perfmon event select MSR.
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Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E3EH 3646 MSR_R1_PMON_EVNT_SEL15 Package Uncore R-box 1 perfmon event select MSR.
2.9 MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES (BASED ON INTEL®
MICROARCHITECTURE CODE NAME WESTMERE)
Intel® Xeon® Processor 5600 Series (based on Intel® microarchitecture code name Westmere) supports the MSR
interfaces listed in Table 2-15, Table 2-16, plus additional MSR listed in Table 2-18. These MSRs apply to Intel Core
i7, i5 and i3 processor family with CPUID signature DisplayFamily_DisplayModel of 06_25H and 06_2CH, see Table
2-1.
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F41H 3905 MSR_C8_PMON_BOX_STATUS Package Uncore C-box 8 perfmon local box status MSR.
F42H 3906 MSR_C8_PMON_BOX_OVF_CTRL Package Uncore C-box 8 perfmon local box overflow control MSR.
F50H 3920 MSR_C8_PMON_EVNT_SEL0 Package Uncore C-box 8 perfmon event select MSR.
Vol. 4 2-165
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-19. Additional MSRs Supported by Intel® Xeon® Processor E7 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
FC0H 4032 MSR_C9_PMON_BOX_CTRL Package Uncore C-box 9 perfmon local box control MSR.
FC1H 4033 MSR_C9_PMON_BOX_STATUS Package Uncore C-box 9 perfmon local box status MSR.
FC2H 4034 MSR_C9_PMON_BOX_OVF_CTRL Package Uncore C-box 9 perfmon local box overflow control MSR.
FD0H 4048 MSR_C9_PMON_EVNT_SEL0 Package Uncore C-box 9 perfmon event select MSR.
2-166 Vol. 4
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Vol. 4 2-167
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MODEL-SPECIFIC REGISTERS (MSRS)
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2.11.1 MSRs In 2nd Generation Intel® Core™ Processor Family (Based on Intel®
Microarchitecture Code Name Sandy Bridge)
Table 2-21 and Table 2-22 list model-specific registers (MSRs) that are specific to the 2nd generation Intel® Core™
processor family (based on Intel microarchitecture code name Sandy Bridge). These processors have a CPUID
signature with DisplayFamily_DisplayModel of 06_2AH; see Table 2-1.
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Vol. 4 2-187
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Table 2-22 lists the MSRs of uncore PMU for Intel processors with CPUID signature 06_2AH.
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
391H 913 MSR_UNC_PERF_GLOBAL_CTRL Package Uncore PMU Global Control
0 Slice 0 select.
1 Slice 1 select.
2 Slice 2 select.
3 Slice 3 select.
4 Slice 4 select.
18:5 Reserved
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved
392H 914 MSR_UNC_PERF_GLOBAL_STATUS Package Uncore PMU Main Status
0 Fixed counter overflowed.
1 An ARB counter overflowed.
2 Reserved
3 A CBox counter overflowed (on any slice).
63:4 Reserved
394H 916 MSR_UNC_PERF_FIXED_CTRL Package Uncore Fixed Counter Control (R/W)
19:0 Reserved
20 Enable overflow propagation.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
21 Reserved
22 Enable counting.
63:23 Reserved
395H 917 MSR_UNC_PERF_FIXED_CTR Package Uncore Fixed Counter
47:0 Current count.
63:48 Reserved
396H 918 MSR_UNC_CBO_CONFIG Package Uncore C-Box Configuration Information (R/O)
3B2H 944 MSR_UNC_ARB_PERFEVTSEL0 Package Uncore Arb Unit, Counter 0 Event Select MSR
3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb unit, Counter 1 Event Select MSR
700H 1792 MSR_UNC_CBO_0_PERFEVTSEL0 Package Uncore C-Box 0, Counter 0 Event Select MSR
701H 1793 MSR_UNC_CBO_0_PERFEVTSEL1 Package Uncore C-Box 0, Counter 1 Event Select MSR
702H 1794 MSR_UNC_CBO_0_PERFEVTSEL2 Package Uncore C-Box 0, Counter 2 Event Select MSR
703H 1795 MSR_UNC_CBO_0_PERFEVTSEL3 Package Uncore C-Box 0, Counter 3 Event Select MSR
705H 1797 MSR_UNC_CBO_0_UNIT_STATUS Package Uncore C-Box 0, Unit Status for Counter 0-3
706H 1798 MSR_UNC_CBO_0_PERFCTR0 Package Uncore C-Box 0, Performance Counter 0
707H 1799 MSR_UNC_CBO_0_PERFCTR1 Package Uncore C-Box 0, Performance Counter 1
708H 1800 MSR_UNC_CBO_0_PERFCTR2 Package Uncore C-Box 0, Performance Counter 2
709H 1801 MSR_UNC_CBO_0_PERFCTR3 Package Uncore C-Box 0, Performance Counter 3
710H 1808 MSR_UNC_CBO_1_PERFEVTSEL0 Package Uncore C-Box 1, Counter 0 Event Select MSR
711H 1809 MSR_UNC_CBO_1_PERFEVTSEL1 Package Uncore C-Box 1, Counter 1 Event Select MSR
712H 1810 MSR_UNC_CBO_1_PERFEVTSEL2 Package Uncore C-Box 1, Counter 2 Event Select MSR
713H 1811 MSR_UNC_CBO_1_PERFEVTSEL3 Package Uncore C-Box 1, Counter 3 Event Select MSR
715H 1813 MSR_UNC_CBO_1_UNIT_STATUS Package Uncore C-Box 1, Unit Status for Counter 0-3
716H 1814 MSR_UNC_CBO_1_PERFCTR0 Package Uncore C-Box 1, Performance Counter 0
717H 1815 MSR_UNC_CBO_1_PERFCTR1 Package Uncore C-Box 1, Performance Counter 1
718H 1816 MSR_UNC_CBO_1_PERFCTR2 Package Uncore C-Box 1, Performance Counter 2
719H 1817 MSR_UNC_CBO_1_PERFCTR3 Package Uncore C-Box 1, Performance Counter 3
720H 1824 MSR_UNC_CBO_2_PERFEVTSEL0 Package Uncore C-Box 2, Counter 0 Event Select MSR
721H 1825 MSR_UNC_CBO_2_PERFEVTSEL1 Package Uncore C-Box 2, Counter 1 Event Select MSR
722H 1826 MSR_UNC_CBO_2_PERFEVTSEL2 Package Uncore C-Box 2, Counter 2 Event Select MSR
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Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
723H 1827 MSR_UNC_CBO_2_PERFEVTSEL3 Package Uncore C-Box 2, Counter 3 Event Select MSR
725H 1829 MSR_UNC_CBO_2_UNIT_STATUS Package Uncore C-Box 2, Unit Status for Counter 0-3
726H 1830 MSR_UNC_CBO_2_PERFCTR0 Package Uncore C-Box 2, Performance Counter 0
727H 1831 MSR_UNC_CBO_2_PERFCTR1 Package Uncore C-Box 2, Performance Counter 1
728H 1832 MSR_UNC_CBO_3_PERFCTR2 Package Uncore C-Box 3, Performance Counter 2
729H 1833 MSR_UNC_CBO_3_PERFCTR3 Package Uncore C-Box 3, Performance Counter 3
730H 1840 MSR_UNC_CBO_3_PERFEVTSEL0 Package Uncore C-Box 3, Counter 0 Event Select MSR
731H 1841 MSR_UNC_CBO_3_PERFEVTSEL1 Package Uncore C-Box 3, Counter 1 Event Select MSR
732H 1842 MSR_UNC_CBO_3_PERFEVTSEL2 Package Uncore C-Box 3, Counter 2 Event Select MSR
733H 1843 MSR_UNC_CBO_3_PERFEVTSEL3 Package Uncore C-Box 3, counter 3 Event Select MSR
735H 1845 MSR_UNC_CBO_3_UNIT_STATUS Package Uncore C-Box 3, Unit Status for Counter 0-3
736H 1846 MSR_UNC_CBO_3_PERFCTR0 Package Uncore C-Box 3, Performance Counter 0
737H 1847 MSR_UNC_CBO_3_PERFCTR1 Package Uncore C-Box 3, Performance Counter 1
738H 1848 MSR_UNC_CBO_3_PERFCTR2 Package Uncore C-Box 3, Performance Counter 2
739H 1849 MSR_UNC_CBO_3_PERFCTR3 Package Uncore C-Box 3, Performance Counter 3
740H 1856 MSR_UNC_CBO_4_PERFEVTSEL0 Package Uncore C-Box 4, Counter 0 Event Select MSR
741H 1857 MSR_UNC_CBO_4_PERFEVTSEL1 Package Uncore C-Box 4, Counter 1 Event Select MSR
742H 1858 MSR_UNC_CBO_4_PERFEVTSEL2 Package Uncore C-Box 4, Counter 2 Event Select MSR
743H 1859 MSR_UNC_CBO_4_PERFEVTSEL3 Package Uncore C-Box 4, Counter 3 Event Select MSR
745H 1861 MSR_UNC_CBO_4_UNIT_STATUS Package Uncore C-Box 4, Unit status for Counter 0-3
746H 1862 MSR_UNC_CBO_4_PERFCTR0 Package Uncore C-Box 4, Performance Counter 0
747H 1863 MSR_UNC_CBO_4_PERFCTR1 Package Uncore C-Box 4, Performance Counter 1
748H 1864 MSR_UNC_CBO_4_PERFCTR2 Package Uncore C-Box 4, Performance Counter 2
749H 1865 MSR_UNC_CBO_4_PERFCTR3 Package Uncore C-Box 4, Performance Counter 3
2.11.2 MSRs In Intel® Xeon® Processor E5 Family (Based on Intel® Microarchitecture Code
Name Sandy Bridge)
Table 2-23 lists additional model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5 Family
(based on Intel® microarchitecture code name Sandy Bridge). These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_2DH, and also supports MSRs listed in Table 2-20 and Table 2-24.
2-190 Vol. 4
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Vol. 4 2-191
MODEL-SPECIFIC REGISTERS (MSRS)
2-192 Vol. 4
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Vol. 4 2-193
MODEL-SPECIFIC REGISTERS (MSRS)
2.11.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family
Intel Xeon Processor E5 family is based on the Sandy Bridge microarchitecture. The MSR-based uncore PMU inter-
faces are listed in Table 2-24. For complete detail of the uncore PMU, refer to Intel Xeon Processor E5 Product
Family Uncore Performance Monitoring Guide. These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_2DH
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
C33H 3123 MSR_PCU_PMON_EVNTSEL3 Package Uncore PCU Perfmon Event Select for PCU Counter 3
C34H 3124 MSR_PCU_PMON_BOX_FILTER Package Uncore PCU Perfmon box-wide Filter
C36H 3126 MSR_PCU_PMON_CTR0 Package Uncore PCU Perfmon Counter 0
C37H 3127 MSR_PCU_PMON_CTR1 Package Uncore PCU Perfmon Counter 1
C38H 3128 MSR_PCU_PMON_CTR2 Package Uncore PCU Perfmon Counter 2
C39H 3129 MSR_PCU_PMON_CTR3 Package Uncore PCU Perfmon Counter 3
D04H 3332 MSR_C0_PMON_BOX_CTL Package Uncore C-box 0 Perfmon Local Box Wide Control
D10H 3344 MSR_C0_PMON_EVNTSEL0 Package Uncore C-box 0 Perfmon Event Select for C-box 0
Counter 0
D11H 3345 MSR_C0_PMON_EVNTSEL1 Package Uncore C-box 0 Perfmon Event Select for C-box 0
Counter 1
D12H 3346 MSR_C0_PMON_EVNTSEL2 Package Uncore C-box 0 Perfmon Event Select for C-box 0
Counter 2
D13H 3347 MSR_C0_PMON_EVNTSEL3 Package Uncore C-box 0 Perfmon Event Select for C-box 0
Counter 3
D14H 3348 MSR_C0_PMON_BOX_FILTER Package Uncore C-box 0 Perfmon Box Wide Filter
D16H 3350 MSR_C0_PMON_CTR0 Package Uncore C-box 0 Perfmon Counter 0
D17H 3351 MSR_C0_PMON_CTR1 Package Uncore C-box 0 Perfmon Counter 1
D18H 3352 MSR_C0_PMON_CTR2 Package Uncore C-box 0 Perfmon Counter 2
D19H 3353 MSR_C0_PMON_CTR3 Package Uncore C-box 0 Perfmon Counter 3
D24H 3364 MSR_C1_PMON_BOX_CTL Package Uncore C-box 1 Perfmon Local Box Wide Control
D30H 3376 MSR_C1_PMON_EVNTSEL0 Package Uncore C-box 1 Perfmon Event Select for C-box 1
Counter 0
D31H 3377 MSR_C1_PMON_EVNTSEL1 Package Uncore C-box 1 Perfmon Event Select for C-box 1
Counter 1
D32H 3378 MSR_C1_PMON_EVNTSEL2 Package Uncore C-box 1 Perfmon Event Select for C-box 1
Counter 2
D33H 3379 MSR_C1_PMON_EVNTSEL3 Package Uncore C-box 1 Perfmon Event Select for C-box 1
Counter 3
D34H 3380 MSR_C1_PMON_BOX_FILTER Package Uncore C-box 1 Perfmon Box Wide Filter
D36H 3382 MSR_C1_PMON_CTR0 Package Uncore C-box 1 Perfmon Counter 0
D37H 3383 MSR_C1_PMON_CTR1 Package Uncore C-box 1 Perfmon Counter 1
D38H 3384 MSR_C1_PMON_CTR2 Package Uncore C-box 1 Perfmon Counter 2
D39H 3385 MSR_C1_PMON_CTR3 Package Uncore C-box 1 Perfmon Counter 3
D44H 3396 MSR_C2_PMON_BOX_CTL Package Uncore C-box 2 Perfmon Local Box Wide Control
D50H 3408 MSR_C2_PMON_EVNTSEL0 Package Uncore C-box 2 Perfmon Event Select for C-box 2
Counter 0
D51H 3409 MSR_C2_PMON_EVNTSEL1 Package Uncore C-box 2 Perfmon Event Select for C-box 2
Counter 1
Vol. 4 2-195
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
D52H 3410 MSR_C2_PMON_EVNTSEL2 Package Uncore C-box 2 Perfmon Event Select for C-box 2
Counter 2
D53H 3411 MSR_C2_PMON_EVNTSEL3 Package Uncore C-box 2 Perfmon Event Select for C-box 2
Counter 3
D54H 3412 MSR_C2_PMON_BOX_FILTER Package Uncore C-box 2 Perfmon Box Wide Filter
D56H 3414 MSR_C2_PMON_CTR0 Package Uncore C-box 2 Perfmon Counter 0
D57H 3415 MSR_C2_PMON_CTR1 Package Uncore C-box 2 Perfmon Counter 1
D58H 3416 MSR_C2_PMON_CTR2 Package Uncore C-box 2 Perfmon Counter 2
D59H 3417 MSR_C2_PMON_CTR3 Package Uncore C-box 2 Perfmon Counter 3
D64H 3428 MSR_C3_PMON_BOX_CTL Package Uncore C-box 3 Perfmon Local Box Wide Control
D70H 3440 MSR_C3_PMON_EVNTSEL0 Package Uncore C-box 3 Perfmon Event Select for C-box 3
Counter 0
D71H 3441 MSR_C3_PMON_EVNTSEL1 Package Uncore C-box 3 Perfmon Event Select for C-box 3
Counter 1
D72H 3442 MSR_C3_PMON_EVNTSEL2 Package Uncore C-box 3 Perfmon Event Select for C-box 3
Counter 2
D73H 3443 MSR_C3_PMON_EVNTSEL3 Package Uncore C-box 3 Perfmon Event Select for C-box 3
Counter 3
D74H 3444 MSR_C3_PMON_BOX_FILTER Package Uncore C-box 3 Perfmon Box Wide Filter
D76H 3446 MSR_C3_PMON_CTR0 Package Uncore C-box 3 Perfmon Counter 0
D77H 3447 MSR_C3_PMON_CTR1 Package Uncore C-box 3 Perfmon Counter 1
D78H 3448 MSR_C3_PMON_CTR2 Package Uncore C-box 3 Perfmon Counter 2
D79H 3449 MSR_C3_PMON_CTR3 Package Uncore C-box 3 Perfmon Counter 3
D84H 3460 MSR_C4_PMON_BOX_CTL Package Uncore C-box 4 Perfmon Local Box Wide Control
D90H 3472 MSR_C4_PMON_EVNTSEL0 Package Uncore C-box 4 Perfmon Event Select for C-box 4
Counter 0
D91H 3473 MSR_C4_PMON_EVNTSEL1 Package Uncore C-box 4 Perfmon Event Select for C-box 4
Counter 1
D92H 3474 MSR_C4_PMON_EVNTSEL2 Package Uncore C-box 4 Perfmon Event Select for C-box 4
Counter 2
D93H 3475 MSR_C4_PMON_EVNTSEL3 Package Uncore C-box 4 Perfmon Event Select for C-box 4
Counter 3
D94H 3476 MSR_C4_PMON_BOX_FILTER Package Uncore C-box 4 Perfmon Box Wide Filter
D96H 3478 MSR_C4_PMON_CTR0 Package Uncore C-box 4 Perfmon Counter 0
D97H 3479 MSR_C4_PMON_CTR1 Package Uncore C-box 4 Perfmon Counter 1
D98H 3480 MSR_C4_PMON_CTR2 Package Uncore C-box 4 Perfmon Counter 2
D99H 3481 MSR_C4_PMON_CTR3 Package Uncore C-box 4 Perfmon Counter 3
DA4H 3492 MSR_C5_PMON_BOX_CTL Package Uncore C-box 5 Perfmon Local Box Wide Control
DB0H 3504 MSR_C5_PMON_EVNTSEL0 Package Uncore C-box 5 Perfmon Event Select for C-box 5
Counter 0
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
DB1H 3505 MSR_C5_PMON_EVNTSEL1 Package Uncore C-box 5 Perfmon Event Select for C-box 5
Counter 1
DB2H 3506 MSR_C5_PMON_EVNTSEL2 Package Uncore C-box 5 Perfmon Event Select for C-box 5
Counter 2
DB3H 3507 MSR_C5_PMON_EVNTSEL3 Package Uncore C-box 5 Perfmon Event Select for C-box 5
Counter 3
DB4H 3508 MSR_C5_PMON_BOX_FILTER Package Uncore C-box 5 Perfmon Box Wide Filter
DB6H 3510 MSR_C5_PMON_CTR0 Package Uncore C-box 5 Perfmon Counter 0
DB7H 3511 MSR_C5_PMON_CTR1 Package Uncore C-box 5 Perfmon Counter 1
DB8H 3512 MSR_C5_PMON_CTR2 Package Uncore C-box 5 Perfmon Counter 2
DB9H 3513 MSR_C5_PMON_CTR3 Package Uncore C-box 5 Perfmon Counter 3
DC4H 3524 MSR_C6_PMON_BOX_CTL Package Uncore C-box 6 Perfmon Local Box Wide Control
DD0H 3536 MSR_C6_PMON_EVNTSEL0 Package Uncore C-box 6 Perfmon Event Select for C-box 6
Counter 0
DD1H 3537 MSR_C6_PMON_EVNTSEL1 Package Uncore C-box 6 Perfmon Event Select for C-box 6
Counter 1
DD2H 3538 MSR_C6_PMON_EVNTSEL2 Package Uncore C-box 6 Perfmon Event Select for C-box 6
Counter 2
DD3H 3539 MSR_C6_PMON_EVNTSEL3 Package Uncore C-box 6 Perfmon Event Select for C-box 6
Counter 3
DD4H 3540 MSR_C6_PMON_BOX_FILTER Package Uncore C-box 6 Perfmon Box Wide Filter
DD6H 3542 MSR_C6_PMON_CTR0 Package Uncore C-box 6 Perfmon Counter 0
DD7H 3543 MSR_C6_PMON_CTR1 Package Uncore C-box 6 Perfmon Counter 1
DD8H 3544 MSR_C6_PMON_CTR2 Package Uncore C-box 6 Perfmon Counter 2
DD9H 3545 MSR_C6_PMON_CTR3 Package Uncore C-box 6 Perfmon Counter 3
DE4H 3556 MSR_C7_PMON_BOX_CTL Package Uncore C-box 7 Perfmon Local Box Wide Control
DF0H 3568 MSR_C7_PMON_EVNTSEL0 Package Uncore C-box 7 Perfmon Event Select for C-box 7
Counter 0
DF1H 3569 MSR_C7_PMON_EVNTSEL1 Package Uncore C-box 7 Perfmon Event Select for C-box 7
Counter 1
DF2H 3570 MSR_C7_PMON_EVNTSEL2 Package Uncore C-box 7 Perfmon Event Select for C-box 7
Counter 2
DF3H 3571 MSR_C7_PMON_EVNTSEL3 Package Uncore C-box 7 Perfmon Event Select for C-box 7
Counter 3
DF4H 3572 MSR_C7_PMON_BOX_FILTER Package Uncore C-box 7 Perfmon Box Wide Filter
DF6H 3574 MSR_C7_PMON_CTR0 Package Uncore C-box 7 Perfmon Counter 0
DF7H 3575 MSR_C7_PMON_CTR1 Package Uncore C-box 7 Perfmon Counter 1
DF8H 3576 MSR_C7_PMON_CTR2 Package Uncore C-box 7 Perfmon Counter 2
DF9H 3577 MSR_C7_PMON_CTR3 Package Uncore C-box 7 Perfmon Counter 3
Vol. 4 2-197
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors
(based on Intel® microarchitecture code name Ivy Bridge)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
CEH 206 MSR_PLATFORM_INFO Package Platform Information
Contains power management and other model
specific features enumeration. See http://biosbits.org.
7:0 Reserved
15:8 Package Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC
runs at. Frequency = ratio * 100 MHz.
27:16 Reserved
28 Package Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio
Limit for Turbo mode is enabled. When set to 0,
indicates Programmable Ratio Limit for Turbo mode is
disabled.
29 Package Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo
mode is programmable. When set to 0, indicates that
TDP Limit for Turbo mode is not programmable.
31:30 Reserved
32 Package Low Power Mode Support (LPM) (R/O)
When set to 1, indicates that LPM is supported. When
set to 0, indicates LPM is not supported.
34:33 Package Number of ConfigTDP Levels (R/O)
00: Only Base TDP level available.
01: One additional TDP level available.
02: Two additional TDP level available.
03: Reserved
39:35 Reserved
47:40 Package Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that
the processor can operate, in units of 100MHz.
55:48 Package Minimum Operating Ratio (R/O)
Contains the minimum supported operating ratio in
units of 100 MHz.
63:56 Reserved
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors
(based on Intel® microarchitecture code name Ivy Bridge) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Core C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
See http://biosbits.org.
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-
state to C3.
9:3 Reserved
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE
to MWAIT instructions.
14:11 Reserved
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
24:16 Reserved
25 C3 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote
C6/C7 requests to C3 based on uncore auto-demote
information.
26 C1 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote
C3/C6/C7 requests to C1 based on uncore auto-
demote information.
27 Enable C3 Undemotion (R/W)
When set, enables undemotion from demoted C3.
28 Enable C1 Undemotion (R/W)
When set, enables undemotion from demoted C1.
Vol. 4 2-199
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors
(based on Intel® microarchitecture code name Ivy Bridge) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:29 Reserved
639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
648H 1608 MSR_CONFIG_TDP_NOMINAL Package Base TDP Ratio (R/O)
7:0 Config_TDP_Base
Base TDP level ratio to be used for this specific
processor (in units of 100 MHz).
63:8 Reserved
649H 1609 MSR_CONFIG_TDP_LEVEL1 Package ConfigTDP Level 1 ratio and power level (R/O)
14:0 PKG_TDP_LVL1
Power setting for ConfigTDP Level 1.
15 Reserved
23:16 Config_TDP_LVL1_Ratio
ConfigTDP level 1 ratio to be used for this specific
processor.
31:24 Reserved
46:32 PKG_MAX_PWR_LVL1
Max Power setting allowed for ConfigTDP Level 1.
47 Reserved
62:48 PKG_MIN_PWR_LVL1
MIN Power setting allowed for ConfigTDP Level 1.
63 Reserved
64AH 1610 MSR_CONFIG_TDP_LEVEL2 Package ConfigTDP Level 2 ratio and power level (R/O)
14:0 PKG_TDP_LVL2
Power setting for ConfigTDP Level 2.
15 Reserved
23:16 Config_TDP_LVL2_Ratio
ConfigTDP level 2 ratio to be used for this specific
processor.
31:24 Reserved
46:32 PKG_MAX_PWR_LVL2
Max Power setting allowed for ConfigTDP Level 2.
47 Reserved
62:48 PKG_MIN_PWR_LVL2
MIN Power setting allowed for ConfigTDP Level 2.
63 Reserved
64BH 1611 MSR_CONFIG_TDP_CONTROL Package ConfigTDP Control (R/W)
2-200 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors
(based on Intel® microarchitecture code name Ivy Bridge) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1:0 TDP_LEVEL (RW/L)
System BIOS can program this field.
30:2 Reserved.
31 Config_TDP_Lock (RW/L)
When this bit is set, the content of this register is
locked until a reset.
63:32 Reserved
64CH 1612 MSR_TURBO_ACTIVATION_RATIO Package ConfigTDP Control (R/W)
7:0 MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8 Reserved
31 TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is
locked until a reset.
63:32 Reserved
See Table 2-20, Table 2-21 and Table 2-22 for other MSR definitions applicable to processors with CPUID signature 06_3AH.
2.12.1 MSRs In Intel® Xeon® Processor E5 v2 Product Family (Based on Ivy Bridge-E
Microarchitecture)
Table 2-26 lists model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5 v2 Product
Family (based on Ivy Bridge-E microarchitecture). These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_3EH, see Table 2-1. These processors supports the MSR interfaces listed in
Table 2-20, and Table 2-26.
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
4EH 78 MSR_PPIN_CTL Package Protected Processor Inventory Number Enable Control
(R/W)
Vol. 4 2-201
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
0 LockOut (R/WO)
If 0, indicates that further writes to MSR_PPIN_CTL is
allowed.
If 1, indicates that further writes to MSR_PPIN_CTL is
disallowed. Writing 1 to this bit is only permitted if the
Enable_PPIN bit is clear.
The Privileged System Software Inventory Agent
should read MSR_PPIN_CTL[bit 1] to determine if
MSR_PPIN is accessible.
The Privileged System Software Inventory Agent is not
expected to write to this MSR.
1 Enable_PPIN (R/W)
If 1, indicates that MSR_PPIN is accessible using
RDMSR.
If 0, indicates that MSR_PPIN is inaccessible using
RDMSR. Any attempt to read MSR_PPIN will cause #GP.
63:2 Reserved
4FH 79 MSR_PPIN Package Protected Processor Inventory Number (R/O)
63:0 Protected Processor Inventory Number (R/O)
A unique value within a given CPUID
family/model/stepping signature that a privileged
inventory initialization agent can access to identify
each physical processor, when access to MSR_PPIN is
enabled. Access to MSR_PPIN is permitted only if
MSR_PPIN_CTL[bits 1:0] = ‘10b’.
CEH 206 MSR_PLATFORM_INFO Package Platform Information
Contains power management and other model specific
features enumeration. See http://biosbits.org.
7:0 Reserved
15:8 Package Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC
runs at. Frequency = ratio * 100 MHz.
22:16 Reserved
23 Package PPIN_CAP (R/O)
When set to 1, indicates that Protected Processor
Inventory Number (PPIN) capability can be enabled for
a privileged system inventory agent to read PPIN from
MSR_PPIN.
When set to 0, PPIN capability is not supported. An
attempt to access MSR_PPIN_CTL or MSR_PPIN will
cause #GP.
27:24 Reserved
2-202 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
28 Package Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit
for Turbo mode is enabled. When set to 0, indicates
Programmable Ratio Limit for Turbo mode is disabled.
29 Package Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode
is programmable. When set to 0, indicates TDP Limit for
Turbo mode is not programmable.
30 Package Programmable TJ OFFSET (R/O)
When set to 1, indicates that
MSR_TEMPERATURE_TARGET.[27:24] is valid and
writable to specify a temperature offset.
39:31 Reserved
47:40 Package Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that
the processor can operate, in units of 100MHz.
63:48 Reserved
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Core C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
See http://biosbits.org.
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-state
to C3.
9:3 Reserved
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE to
MWAIT instructions.
Vol. 4 2-203
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
14:11 Reserved
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
63:16 Reserved
179H 377 IA32_MCG_CAP Thread Global Machine Check Capability (R/O)
7:0 Count
8 MCG_CTL_P
9 MCG_EXT_P
10 MCP_CMCI_P
11 MCG_TES_P
15:12 Reserved
23:16 MCG_EXT_CNT
24 MCG_SER_P
25 Reserved
26 MCG_ELOG_P
63:27 Reserved
17FH 383 MSR_ERROR_CONTROL Package MC Bank Error Configuration (R/W)
0 Reserved
1 MemError Log Enable (R/W)
When set, enables IMC status bank to log additional info
in bits 36:32.
63:2 Reserved
1A2H 418 MSR_TEMPERATURE_TARGET Package Temperature Target
15:0 Reserved
23:16 Temperature Target (RO)
The minimum temperature at which PROCHOT# will be
asserted. The value is degrees C.
27:24 TCC Activation Offset (R/W)
Specifies a temperature offset in degrees C from the
temperature target (bits 23:16). PROCHOT# will assert
at the offset target temperature. Write is permitted
only if MSR_PLATFORM_INFO.[30] is set.
63:28 Reserved
1AEH 430 MSR_TURBO_RATIO_LIMIT1 Package Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0.
RW if MSR_PLATFORM_INFO.[28] = 1.
7:0 Package Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active.
2-204 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
15:8 Package Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10 core active.
23:16 Package Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.
31:24 Package Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.
63:32 Reserved
285H 645 IA32_MC5_CTL2 Package See Table 2-2.
286H 646 IA32_MC6_CTL2 Package See Table 2-2.
287H 647 IA32_MC7_CTL2 Package See Table 2-2.
288H 648 IA32_MC8_CTL2 Package See Table 2-2.
289H 649 IA32_MC9_CTL2 Package See Table 2-2.
28AH 650 IA32_MC10_CTL2 Package See Table 2-2.
28BH 651 IA32_MC11_CTL2 Package See Table 2-2.
28CH 652 IA32_MC12_CTL2 Package See Table 2-2.
28DH 653 IA32_MC13_CTL2 Package See Table 2-2.
28EH 654 IA32_MC14_CTL2 Package See Table 2-2.
28FH 655 IA32_MC15_CTL2 Package See Table 2-2.
290H 656 IA32_MC16_CTL2 Package See Table 2-2.
291H 657 IA32_MC17_CTL2 Package See Table 2-2.
292H 658 IA32_MC18_CTL2 Package See Table 2-2.
293H 659 IA32_MC19_CTL2 Package See Table 2-2.
294H 660 IA32_MC20_CTL2 Package See Table 2-2.
295H 661 IA32_MC21_CTL2 Package See Table 2-2.
296H 662 IA32_MC22_CTL2 Package See Table 2-2.
297H 663 IA32_MC23_CTL2 Package See Table 2-2.
298H 664 IA32_MC24_CTL2 Package See Table 2-2.
299H 665 IA32_MC25_CTL2 Package See Table 2-2.
29AH 666 IA32_MC26_CTL2 Package See Table 2-2.
29BH 667 IA32_MC27_CTL2 Package See Table 2-2.
29CH 668 IA32_MC28_CTL2 Package See Table 2-2.
414H 1044 IA32_MC5_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
415H 1045 IA32_MC5_STATUS Package
Bank MC5 reports MC errors from the Intel QPI module.
416H 1046 IA32_MC5_ADDR Package
417H 1047 IA32_MC5_MISC Package
Vol. 4 2-205
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
418H 1048 IA32_MC6_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
419H 1049 IA32_MC6_STATUS Package
Bank MC6 reports MC errors from the integrated I/O
41AH 1050 IA32_MC6_ADDR Package module.
41BH 1051 IA32_MC6_MISC Package
41CH 1052 IA32_MC7_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
41DH 1053 IA32_MC7_STATUS Package
Banks MC7 and MC 8 report MC errors from the two
41EH 1054 IA32_MC7_ADDR Package home agents.
41FH 1055 IA32_MC7_MISC Package
420H 1056 IA32_MC8_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
421H 1057 IA32_MC8_STATUS Package
Banks MC7 and MC 8 report MC errors from the two
422H 1058 IA32_MC8_ADDR Package home agents.
423H 1059 IA32_MC8_MISC Package
424H 1060 IA32_MC9_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
425H 1061 IA32_MC9_STATUS Package
Banks MC9 through MC 16 report MC errors from each
426H 1062 IA32_MC9_ADDR Package channel of the integrated memory controllers.
427H 1063 IA32_MC9_MISC Package
428H 1064 IA32_MC10_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
429H 1065 IA32_MC10_STATUS Package
Banks MC9 through MC 16 report MC errors from each
42AH 1066 IA32_MC10_ADDR Package channel of the integrated memory controllers.
42BH 1067 IA32_MC10_MISC Package
434H 1076 IA32_MC13_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
435H 1077 IA32_MC13_STATUS Package
Banks MC9 through MC 16 report MC errors from each
436H 1078 IA32_MC13_ADDR Package channel of the integrated memory controllers.
437H 1079 IA32_MC13_MISC Package
2-206 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
438H 1080 IA32_MC14_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
439H 1081 IA32_MC14_STATUS Package
Banks MC9 through MC 16 report MC errors from each
43AH 1082 IA32_MC14_ADDR Package channel of the integrated memory controllers.
43BH 1083 IA32_MC14_MISC Package
43CH 1084 IA32_MC15_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
43DH 1085 IA32_MC15_STATUS Package
Banks MC9 through MC 16 report MC errors from each
43EH 1086 IA32_MC15_ADDR Package channel of the integrated memory controllers.
43FH 1087 IA32_MC15_MISC Package
440H 1088 IA32_MC16_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
441H 1089 IA32_MC16_STATUS Package
Banks MC9 through MC 16 report MC errors from each
442H 1090 IA32_MC16_ADDR Package channel of the integrated memory controllers.
443H 1091 IA32_MC16_MISC Package
444H 1092 IA32_MC17_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
445H 1093 IA32_MC17_STATUS Package
Bank MC17 reports MC errors from a specific CBo (core
446H 1094 IA32_MC17_ADDR Package broadcast) and its corresponding slice of L3.
447H 1095 IA32_MC17_MISC Package
448H 1096 IA32_MC18_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
449H 1097 IA32_MC18_STATUS Package
Bank MC18 reports MC errors from a specific CBo (core
44AH 1098 IA32_MC18_ADDR Package broadcast) and its corresponding slice of L3.
44BH 1099 IA32_MC18_MISC Package
44CH 1100 IA32_MC19_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
44DH 1101 IA32_MC19_STATUS Package
Bank MC19 reports MC errors from a specific CBo (core
44EH 1102 IA32_MC19_ADDR Package broadcast) and its corresponding slice of L3.
44FH 1103 IA32_MC19_MISC Package
Vol. 4 2-207
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
458H 1112 IA32_MC22_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
459H 1113 IA32_MC22_STATUS Package
Bank MC22 reports MC errors from a specific CBo (core
45AH 1114 IA32_MC22_ADDR Package broadcast) and its corresponding slice of L3.
45BH 1115 IA32_MC22_MISC Package
45CH 1116 IA32_MC23_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
45DH 1117 IA32_MC23_STATUS Package
Bank MC23 reports MC errors from a specific CBo (core
45EH 1118 IA32_MC23_ADDR Package broadcast) and its corresponding slice of L3.
45FH 1119 IA32_MC23_MISC Package
460H 1120 IA32_MC24_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
461H 1121 IA32_MC24_STATUS Package
Bank MC24 reports MC errors from a specific CBo (core
462H 1122 IA32_MC24_ADDR Package broadcast) and its corresponding slice of L3.
463H 1123 IA32_MC24_MISC Package
464H 1124 IA32_MC25_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
465H 1125 IA32_MC25_STATUS Package
Bank MC25 reports MC errors from a specific CBo (core
466H 1126 IA32_MC25_ADDR Package broadcast) and its corresponding slice of L3.
467H 1127 IA32_MC2MISC Package
468H 1128 IA32_MC26_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
469H 1129 IA32_MC26_STATUS Package
Bank MC26 reports MC errors from a specific CBo (core
46AH 1130 IA32_MC26_ADDR Package broadcast) and its corresponding slice of L3.
46BH 1131 IA32_MC26_MISC Package
46CH 1132 IA32_MC27_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
46DH 1133 IA32_MC27_STATUS Package
Bank MC27 reports MC errors from a specific CBo (core
46EH 1134 IA32_MC27_ADDR Package broadcast) and its corresponding slice of L3.
46FH 1135 IA32_MC27_MISC Package
470H 1136 IA32_MC28_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
471H 1137 IA32_MC28_STATUS Package
Bank MC28 reports MC errors from a specific CBo (core
472H 1138 IA32_MC28_ADDR Package broadcast) and its corresponding slice of L3.
473H 1139 IA32_MC28_MISC Package
2-208 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E
microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W)
See Section 14.10.5, “DRAM RAPL Domain.”
639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
See Table 2-20, for other MSR definitions applicable to Intel Xeon processor E5 v2 with CPUID signature 06_3EH.
Vol. 4 2-209
MODEL-SPECIFIC REGISTERS (MSRS)
2-210 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
478H 1144 IA32_MC30_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
479H 1145 IA32_MC30_STATUS Package
Bank MC30 reports MC errors from a specific CBo (core
47AH 1146 IA32_MC30_ADDR Package broadcast) and its corresponding slice of L3.
47BH 1147 IA32_MC30_MISC Package
47CH 1148 IA32_MC31_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
47DH 1149 IA32_MC31_STATUS Package
Bank MC31 reports MC errors from a specific CBo (core
47EH 1150 IA32_MC31_ADDR Package broadcast) and its corresponding slice of L3.
47FH 1147 IA32_MC31_MISC Package
See Table 2-20, Table 2-26 for other MSR definitions applicable to Intel Xeon processor E7 v2 with CPUID signature 06_3AH.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the
factory-set configuration is dependent on features specific to the processor and the platform.
2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families
Intel Xeon Processor E5 v2 and E7 v2 families are based on the Ivy Bridge-E microarchitecture. The MSR-based
uncore PMU interfaces are listed in Table 2-24 and Table 2-28. For complete detail of the uncore PMU, refer to Intel
Xeon Processor E5 v2 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID signa-
ture with DisplayFamily_DisplayModel of 06_3EH.
Vol. 4 2-211
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-28. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
C00H 3072 MSR_PMON_GLOBAL_CTL Package Uncore Perfmon Per-Socket Global Control
C01H 3073 MSR_PMON_GLOBAL_STATUS Package Uncore Perfmon Per-Socket Global Status
C06H 3078 MSR_PMON_GLOBAL_CONFIG Package Uncore Perfmon Per-Socket Global Configuration
C15H 3093 MSR_U_PMON_BOX_STATUS Package Uncore U-box Perfmon U-Box Wide Status
C35H 3125 MSR_PCU_PMON_BOX_STATUS Package Uncore PCU Perfmon Box Wide Status
D1AH 3354 MSR_C0_PMON_BOX_FILTER1 Package Uncore C-Box 0 Perfmon Box Wide Filter1
D3AH 3386 MSR_C1_PMON_BOX_FILTER1 Package Uncore C-Box 1 Perfmon Box Wide Filter1
D5AH 3418 MSR_C2_PMON_BOX_FILTER1 Package Uncore C-Box 2 Perfmon Box Wide Filter1
D7AH 3450 MSR_C3_PMON_BOX_FILTER1 Package Uncore C-Box 3 Perfmon Box Wide Filter1
D9AH 3482 MSR_C4_PMON_BOX_FILTER1 Package Uncore C-Box 4 Perfmon Box Wide Filter1
DBAH 3514 MSR_C5_PMON_BOX_FILTER1 Package Uncore C-Box 5 Perfmon Box Wide Filter1
DDAH 3546 MSR_C6_PMON_BOX_FILTER1 Package Uncore C-Box 6 Perfmon Box Wide Filter1
DFAH 3578 MSR_C7_PMON_BOX_FILTER1 Package Uncore C-Box 7 Perfmon Box Wide Filter1
E04H 3588 MSR_C8_PMON_BOX_CTL Package Uncore C-Box 8 Perfmon Local Box Wide Control
E10H 3600 MSR_C8_PMON_EVNTSEL0 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 0
E11H 3601 MSR_C8_PMON_EVNTSEL1 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 1
E12H 3602 MSR_C8_PMON_EVNTSEL2 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 2
E13H 3603 MSR_C8_PMON_EVNTSEL3 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 3
E14H 3604 MSR_C8_PMON_BOX_FILTER Package Uncore C-Box 8 Perfmon Box Wide Filter
E16H 3606 MSR_C8_PMON_CTR0 Package Uncore C-Box 8 Perfmon Counter 0
E17H 3607 MSR_C8_PMON_CTR1 Package Uncore C-Box 8 Perfmon Counter 1
E18H 3608 MSR_C8_PMON_CTR2 Package Uncore C-Box 8 Perfmon Counter 2
E19H 3609 MSR_C8_PMON_CTR3 Package Uncore C-Box 8 Perfmon Counter 3
E1AH 3610 MSR_C8_PMON_BOX_FILTER1 Package Uncore C-Box 8 Perfmon Box Wide Filter1
E24H 3620 MSR_C9_PMON_BOX_CTL Package Uncore C-Box 9 Perfmon Local Box Wide Control
E30H 3632 MSR_C9_PMON_EVNTSEL0 Package Uncore C-Box 9 Perfmon Event Select for C-box 9
Counter 0
E31H 3633 MSR_C9_PMON_EVNTSEL1 Package Uncore C-Box 9 Perfmon Event Select for C-box 9
Counter 1
E32H 3634 MSR_C9_PMON_EVNTSEL2 Package Uncore C-Box 9 Perfmon Event Select for C-box 9
Counter 2
E33H 3635 MSR_C9_PMON_EVNTSEL3 Package Uncore C-Box 9 Perfmon Event Select for C-box 9
Counter 3
E34H 3636 MSR_C9_PMON_BOX_FILTER Package Uncore C-Box 9 Perfmon Box Wide Filter
E36H 3638 MSR_C9_PMON_CTR0 Package Uncore C-Box 9 Perfmon Counter 0
2-212 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-28. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E37H 3639 MSR_C9_PMON_CTR1 Package Uncore C-Box 9 Perfmon Counter 1
E38H 3640 MSR_C9_PMON_CTR2 Package Uncore C-Box 9 Perfmon Counter 2
E39H 3641 MSR_C9_PMON_CTR3 Package Uncore C-Box 9 Perfmon Counter 3
E3AH 3642 MSR_C9_PMON_BOX_FILTER1 Package Uncore C-Box 9 Perfmon Box Wide Filter1
E44H 3652 MSR_C10_PMON_BOX_CTL Package Uncore C-Box 10 Perfmon Local Box Wide Control
E50H 3664 MSR_C10_PMON_EVNTSEL0 Package Uncore C-Box 10 Perfmon Event Select for C-Box
10 Counter 0
E51H 3665 MSR_C10_PMON_EVNTSEL1 Package Uncore C-Box 10 Perfmon Event Select for C-Box
10 Counter 1
E52H 3666 MSR_C10_PMON_EVNTSEL2 Package Uncore C-Box 10 Perfmon Event Select for C-Box
10 Counter 2
E53H 3667 MSR_C10_PMON_EVNTSEL3 Package Uncore C-Box 10 Perfmon Event Select for C-Box
10 Counter 3
E54H 3668 MSR_C10_PMON_BOX_FILTER Package Uncore C-Box 10 Perfmon Box Wide Filter
E56H 3670 MSR_C10_PMON_CTR0 Package Uncore C-Box 10 Perfmon Counter 0
E57H 3671 MSR_C10_PMON_CTR1 Package Uncore C-Box 10 Perfmon Counter 1
E58H 3672 MSR_C10_PMON_CTR2 Package Uncore C-Box 10 Perfmon Counter 2
E59H 3673 MSR_C10_PMON_CTR3 Package Uncore C-Box 10 Perfmon Counter 3
E5AH 3674 MSR_C10_PMON_BOX_FILTER1 Package Uncore C-Box 10 Perfmon Box Wide Filter1
E64H 3684 MSR_C11_PMON_BOX_CTL Package Uncore C-Box 11 Perfmon Local Box Wide Control
E70H 3696 MSR_C11_PMON_EVNTSEL0 Package Uncore C-Box 11 Perfmon Event Select for C-Box
11 Counter 0
E71H 3697 MSR_C11_PMON_EVNTSEL1 Package Uncore C-Box 11 Perfmon Event Select for C-Box
11 Counter 1
E72H 3698 MSR_C11_PMON_EVNTSEL2 Package Uncore C-Box 11 Perfmon Event Select for C-Box
11 Counter 2
E73H 3699 MSR_C11_PMON_EVNTSEL3 Package Uncore C-Box 11 Perfmon Event Select for C-Box
11 Counter 3
E74H 3700 MSR_C11_PMON_BOX_FILTER Package Uncore C-Box 11 Perfmon Box Wide Filter
E76H 3702 MSR_C11_PMON_CTR0 Package Uncore C-Box 11 Perfmon Counter 0
E77H 3703 MSR_C11_PMON_CTR1 Package Uncore C-Box 11 Perfmon Counter 1
E78H 3704 MSR_C11_PMON_CTR2 Package Uncore C-Box 11 Perfmon Counter 2
E79H 3705 MSR_C11_PMON_CTR3 Package Uncore C-Box 11 Perfmon Counter 3
E7AH 3706 MSR_C11_PMON_BOX_FILTER1 Package Uncore C-Box 11 Perfmon Box Wide Filter1
E84H 3716 MSR_C12_PMON_BOX_CTL Package Uncore C-Box 12 Perfmon Local Box Wide Control
E90H 3728 MSR_C12_PMON_EVNTSEL0 Package Uncore C-Box 12 Perfmon Event Select for C-Box
12 Counter 0
E91H 3729 MSR_C12_PMON_EVNTSEL1 Package Uncore C-Box 12 Perfmon Event Select for C-Box
12 Counter 1
Vol. 4 2-213
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-28. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E92H 3730 MSR_C12_PMON_EVNTSEL2 Package Uncore C-Box 12 Perfmon Event Select for C-Box
12 Counter 2
E93H 3731 MSR_C12_PMON_EVNTSEL3 Package Uncore C-Box 12 Perfmon Event Select for C-Box
12 Counter 3
E94H 3732 MSR_C12_PMON_BOX_FILTER Package Uncore C-Box 12 Perfmon Box Wide Filter
E96H 3734 MSR_C12_PMON_CTR0 Package Uncore C-Box 12 Perfmon Counter 0
E97H 3735 MSR_C12_PMON_CTR1 Package Uncore C-Box 12 Perfmon Counter 1
E98H 3736 MSR_C12_PMON_CTR2 Package Uncore C-Box 12 Perfmon Counter 2
E99H 3737 MSR_C12_PMON_CTR3 Package Uncore C-Box 12 Perfmon Counter 3
E9AH 3738 MSR_C12_PMON_BOX_FILTER1 Package Uncore C-Box 12 Perfmon Box Wide Filter1
EA4H 3748 MSR_C13_PMON_BOX_CTL Package Uncore C-Box 13 Perfmon Local Box Wide Control
EB0H 3760 MSR_C13_PMON_EVNTSEL0 Package Uncore C-Box 13 Perfmon Event Select for C-Box
13 Counter 0
EB1H 3761 MSR_C13_PMON_EVNTSEL1 Package Uncore C-Box 13 Perfmon Event Select for C-Box
13 Counter 1
EB2H 3762 MSR_C13_PMON_EVNTSEL2 Package Uncore C-Box 13 Perfmon Event Select for C-Box
13 Counter 2
EB3H 3763 MSR_C13_PMON_EVNTSEL3 Package Uncore C-Box 13 Perfmon Event Select for C-Box
13 Counter 3
EB4H 3764 MSR_C13_PMON_BOX_FILTER Package Uncore C-Box 13 Perfmon Box Wide Filter
EB6H 3766 MSR_C13_PMON_CTR0 Package Uncore C-Box 13 Perfmon Counter 0
EB7H 3767 MSR_C13_PMON_CTR1 Package Uncore C-Box 13 Perfmon Counter 1
EB8H 3768 MSR_C13_PMON_CTR2 Package Uncore C-Box 13 Perfmon Counter 2
EB9H 3769 MSR_C13_PMON_CTR3 Package Uncore C-Box 13 Perfmon Counter 3
EBAH 3770 MSR_C13_PMON_BOX_FILTER1 Package Uncore C-Box 13 Perfmon Box Wide Filter1
EC4H 3780 MSR_C14_PMON_BOX_CTL Package Uncore C-Box 14 Perfmon Local Box Wide Control
ED0H 3792 MSR_C14_PMON_EVNTSEL0 Package Uncore C-Box 14 Perfmon Event Select for C-Box
14 Counter 0
ED1H 3793 MSR_C14_PMON_EVNTSEL1 Package Uncore C-Box 14 Perfmon Event Select for C-Box
14 Counter 1
ED2H 3794 MSR_C14_PMON_EVNTSEL2 Package Uncore C-Box 14 Perfmon Event Select for C-Box
14 Counter 2
ED3H 3795 MSR_C14_PMON_EVNTSEL3 Package Uncore C-Box 14 Perfmon Event Select for C-Box
14 Counter 3
ED4H 3796 MSR_C14_PMON_BOX_FILTER Package Uncore C-Box 14 Perfmon Box Wide Filter
ED6H 3798 MSR_C14_PMON_CTR0 Package Uncore C-Box 14 Perfmon Counter 0
ED7H 3799 MSR_C14_PMON_CTR1 Package Uncore C-Box 14 Perfmon Counter 1
ED8H 3800 MSR_C14_PMON_CTR2 Package Uncore C-Box 14 Perfmon Counter 2
ED9H 3801 MSR_C14_PMON_CTR3 Package Uncore C-Box 14 Perfmon Counter 3
EDAH 3802 MSR_C14_PMON_BOX_FILTER1 Package Uncore C-Box 14 Perfmon Box Wide Filter1
2-214 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3BH 59 IA32_TSC_ADJUST Thread Per-Logical-Processor TSC ADJUST (R/W)
See Table 2-2.
CEH 206 MSR_PLATFORM_INFO Package Platform Information
Contains power management and other model
specific features enumeration. See
http://biosbits.org.
7:0 Reserved
15:8 Package Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC
runs at. Frequency = ratio * 100 MHz.
27:16 Reserved
28 Package Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio
Limit for Turbo mode is enabled. When set to 0,
indicates Programmable Ratio Limit for Turbo mode
is disabled.
29 Package Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo
mode is programmable. When set to 0, indicates TDP
Limit for Turbo mode is not programmable.
31:30 Reserved
32 Package Low Power Mode Support (LPM) (R/O)
When set to 1, indicates that LPM is supported.
When set to 0, indicates LPM is not supported.
34:33 Package Number of ConfigTDP Levels (R/O)
00: Only Base TDP level available.
01: One additional TDP level available.
02: Two additional TDP level available.
03: Reserved
39:35 Reserved
47:40 Package Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that
the processor can operate, in units of 100MHz.
Vol. 4 2-215
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
55:48 Package Minimum Operating Ratio (R/O)
Contains the minimum supported operating ratio in
units of 100 MHz.
63:56 Reserved
186H 390 IA32_PERFEVTSEL0 Thread Performance Event Select for Counter 0 (R/W)
Supports all fields described inTable 2-2 and the
fields below.
32 IN_TX: See Section 18.3.6.5.1.
When IN_TX (bit 32) is set, AnyThread (bit 21)
should be cleared to prevent incorrect results.
187H 391 IA32_PERFEVTSEL1 Thread Performance Event Select for Counter 1 (R/W)
Supports all fields described inTable 2-2 and the
fields below.
32 IN_TX: See Section 18.3.6.5.1.
When IN_TX (bit 32) is set, AnyThread (bit 21)
should be cleared to prevent incorrect results.
188H 392 IA32_PERFEVTSEL2 Thread Performance Event Select for Counter 2 (R/W)
Supports all fields described inTable 2-2 and the
fields below.
32 IN_TX: See Section 18.3.6.5.1.
When IN_TX (bit 32) is set, AnyThread (bit 21)
should be cleared to prevent incorrect results.
33 IN_TXCP: See Section 18.3.6.5.1.
When IN_TXCP=1 & IN_TX=1 and in sampling, a
spurious PMI may occur and transactions may
continuously abort near overflow conditions.
Software should favor using IN_TXCP for counting
over sampling. If sampling, software should use large
“sample-after” value after clearing the counter
configured to use IN_TXCP and also always reset the
counter even when no overflow condition was
reported.
189H 393 IA32_PERFEVTSEL3 Thread Performance Event Select for Counter 3 (R/W)
Supports all fields described inTable 2-2 and the
fields below.
32 IN_TX: See Section 18.3.6.5.1
When IN_TX (bit 32) is set, AnyThread (bit 21)
should be cleared to prevent incorrect results.
1C8H 456 MSR_LBR_SELECT Thread Last Branch Record Filtering Select Register (R/W)
0 CPL_EQ_0
1 CPL_NEQ_0
2 JCC
3 NEAR_REL_CALL
2-216 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
4 NEAR_IND_CALL
5 NEAR_RET
6 NEAR_IND_JMP
7 NEAR_REL_JMP
8 FAR_BRANCH
9 EN_CALL_STACK
63:9 Reserved
1D9H 473 IA32_DEBUGCTL Thread Debug Control (R/W)
See Table 2-2.
0 LBR: Last Branch Record
1 BTF
5:2 Reserved
6 TR: Branch Trace
7 BTS: Log Branch Trace Message to BTS Buffer
8 BTINT
9 BTS_OFF_OS
10 BTS_OFF_USER
11 FREEZE_LBR_ON_PMI
12 FREEZE_PERFMON_ON_PMI
13 ENABLE_UNCORE_PMI
14 FREEZE_WHILE_SMM
15 RTM_DEBUG
63:15 Reserved
491H 1169 IA32_VMX_VMFUNC Thread Capability Reporting Register of VM-Function
Controls (R/O)
See Table 2-2.
60BH 1548 MSR_PKGC_IRTL1 Package Package C6/C7 Interrupt Response Limit 1 (R/W)
This MSR defines the interrupt response time limit
used by the processor to manage a transition to a
package C6 or C7 state. The latency programmed in
this register is for the shorter-latency sub C-states
used by an MWAIT hint to a C6 or C7 state.
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if
the package should be put into a package C6 or C7
state.
Vol. 4 2-217
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. See Table 2-20 for
supported time unit encodings.
14:13 Reserved
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid
and can be used by the processor for package C-sate
management.
63:16 Reserved
60CH 1548 MSR_PKGC_IRTL2 Package Package C6/C7 Interrupt Response Limit 2 (R/W)
This MSR defines the interrupt response time limit
used by the processor to manage a transition to a
package C6 or C7 state. The latency programmed in
this register is for the longer-latency sub C-states
used by an MWAIT hint to a C6 or C7 state.
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
9:0 Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if
the package should be put into a package C6 or C7
state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. See Table 2-20 for
supported time unit encodings.
14:13 Reserved
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid
and can be used by the processor for package C-sate
management.
63:16 Reserved
613H 1555 MSR_PKG_PERF_STATUS Package PKG Perf Status (R/O)
See Section 14.10.3, “Package RAPL Domain.”
619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
648H 1608 MSR_CONFIG_TDP_NOMINAL Package Base TDP Ratio (R/O)
7:0 Config_TDP_Base
Base TDP level ratio to be used for this specific
processor (in units of 100 MHz).
2-218 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:8 Reserved
649H 1609 MSR_CONFIG_TDP_LEVEL1 Package ConfigTDP Level 1 Ratio and Power Level (R/O)
14:0 PKG_TDP_LVL1
Power setting for ConfigTDP Level 1.
15 Reserved
23:16 Config_TDP_LVL1_Ratio
ConfigTDP level 1 ratio to be used for this specific
processor.
31:24 Reserved
46:32 PKG_MAX_PWR_LVL1
Max Power setting allowed for ConfigTDP Level 1.
62:47 PKG_MIN_PWR_LVL1
MIN Power setting allowed for ConfigTDP Level 1.
63 Reserved
64AH 1610 MSR_CONFIG_TDP_LEVEL2 Package ConfigTDP Level 2 Ratio and Power Level (R/O)
14:0 PKG_TDP_LVL2
Power setting for ConfigTDP Level 2.
15 Reserved
23:16 Config_TDP_LVL2_Ratio
ConfigTDP level 2 ratio to be used for this specific
processor.
31:24 Reserved
46:32 PKG_MAX_PWR_LVL2
Max Power setting allowed for ConfigTDP Level 2.
62:47 PKG_MIN_PWR_LVL2
MIN Power setting allowed for ConfigTDP Level 2.
63 Reserved
64BH 1611 MSR_CONFIG_TDP_CONTROL Package ConfigTDP Control (R/W)
Vol. 4 2-219
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
7:0 MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8 Reserved
31 TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is
locked until a reset.
63:32 Reserved
C80H 3200 IA32_DEBUG_INTERFACE Package Silicon Debug Feature Control (R/W)
See Table 2-2.
2.13.1 MSRs in 4th Generation Intel® Core™ Processor Family (based on Haswell
Microarchitecture)
Table 2-30 lists model-specific registers (MSRs) that are specific to 4th generation Intel® Core™ processor family
and Intel® Xeon® processor E3-1200 v3 product family (based on Haswell microarchitecture). These processors
have a CPUID signature with DisplayFamily_DisplayModel of 06_3CH/06_45H/06_46H, see Table 2-1.
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Core C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
See http://biosbits.org.
3:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
Package C states C7 are not available to processors
with a signature of 06_3CH.
9:4 Reserved
10 I/O MWAIT Redirection Enable (R/W)
2-220 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
14:11 Reserved
15 CFG Lock (R/WO)
24:16 Reserved
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
63:29 Reserved
17DH 381 MSR_SMM_MCA_CAP THREAD Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible
only while in SMM.
57:0 Reserved
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1, indicates that the SMM code access
restriction is supported and the
MSR_SMM_FEATURE_CONTROL is supported.
59 Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator
is supported and the MSR_SMM_DELAYED is
supported.
63:60 Reserved
1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0.
RW if MSR_PLATFORM_INFO.[28] = 1.
7:0 Package Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8 Package Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16 Package Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24 Package Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
63:32 Reserved
391H 913 MSR_UNC_PERF_GLOBAL_CTRL Package Uncore PMU Global Control
0 Core 0 select.
1 Core 1 select.
2 Core 2 select.
3 Core 3 select.
18:4 Reserved
Vol. 4 2-221
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved
392H 914 MSR_UNC_PERF_GLOBAL_STATUS Package Uncore PMU Main Status
0 Fixed counter overflowed.
1 An ARB counter overflowed.
2 Reserved
3 A CBox counter overflowed (on any slice).
63:4 Reserved
394H 916 MSR_UNC_PERF_FIXED_CTRL Package Uncore Fixed Counter Control (R/W)
19:0 Reserved
20 Enable overflow propagation.
21 Reserved
22 Enable counting.
63:23 Reserved
395H 917 MSR_UNC_PERF_FIXED_CTR Package Uncore Fixed Counter
47:0 Current count.
63:48 Reserved
396H 918 MSR_UNC_CBO_CONFIG Package Uncore C-Box Configuration Information (R/O)
3:0 Encoded number of C-Box, derive value by “-1“.
63:4 Reserved
3B0H 946 MSR_UNC_ARB_PERFCTR0 Package Uncore Arb Unit, Performance Counter 0
3B1H 947 MSR_UNC_ARB_PERFCTR1 Package Uncore Arb Unit, Performance Counter 1
3B2H 944 MSR_UNC_ARB_PERFEVTSEL0 Package Uncore Arb Unit, Counter 0 Event Select MSR
3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb Unit, Counter 1 Event Select MSR
391H 913 MSR_UNC_PERF_GLOBAL_CTRL Package Uncore PMU Global Control
0 Core 0 select.
1 Core 1 select.
2 Core 2 select.
3 Core 3 select.
18:4 Reserved
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved
2-222 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
395H 917 MSR_UNC_PERF_FIXED_CTR Package Uncore Fixed Counter
47:0 Current count.
63:48 Reserved
3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb Unit, Counter 1 Event Select MSR
4E0H 1248 MSR_SMM_FEATURE_CONTROL Package Enhanced SMM Feature Control (SMM-RW)
Reports SMM capability Enhancement. Accessible
only while in SMM.
0 Lock (SMM-RWO)
When set to ‘1’ locks this register from further
changes.
1 Reserved
2 SMM_Code_Chk_En (SMM-RW)
This control bit is available only if
MSR_SMM_MCA_CAP[58] == 1. When set to ‘0’
(default) none of the logical processors are
prevented from executing SMM code outside the
ranges defined by the SMRR.
When set to ‘1’ any logical processor in the package
that attempts to execute SMM code not within the
ranges defined by the SMRR will assert an
unrecoverable MCE.
63:3 Reserved
4E2H 1250 MSR_SMM_DELAYED Package SMM Delayed (SMM-RO)
Reports the interruptible state of all logical
processors in the package. Available only while in
SMM and
MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] ==
1.
N-1:0 LOG_PROC_STATE (SMM-RO)
Each bit represents a logical processor of its state in
a long flow of internal operation which delays
servicing an interrupt. The corresponding bit will be
set at the start of long events such as: Microcode
Update Load, C6, WBINVD, Ratio Change, Throttle.
The bit is automatically cleared at the end of each
long event. The reset value of this field is 0.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N Reserved
4E3H 1251 MSR_SMM_BLOCKED Package SMM Blocked (SMM-RO)
Reports the blocked state of all logical processors in
the package. Available only while in SMM.
Vol. 4 2-223
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
N-1:0 LOG_PROC_STATE (SMM-RO)
Each bit represents a logical processor of its blocked
state to service an SMI. The corresponding bit will be
set if the logical processor is in one of the following
states: Wait For SIPI or SENTER Sleep.
The reset value of this field is 0FFFH.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N Reserved
606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers Used in RAPL Interfaces (R/O)
3:0 Package Power Units
See Section 14.10.1, “RAPL Interfaces.”
7:4 Package Reserved
12:8 Package Energy Status Units
Energy related information (in Joules) is based on the
multiplier, 1/2^ESU; where ESU is an unsigned
integer represented by bits 12:8. Default value is
0EH (or 61 micro-joules).
15:13 Package Reserved
19:16 Package Time Units
See Section 14.10.1, “RAPL Interfaces.”
63:20 Reserved
639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
640H 1600 MSR_PP1_POWER_LIMIT Package PP1 RAPL Power Limit Control (R/W)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
641H 1601 MSR_PP1_ENERGY_STATUS Package PP1 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
642H 1602 MSR_PP1_POLICY Package PP1 Balance Policy (R/W)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
690H 1680 MSR_CORE_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in Processor Cores
(R/W)
(Frequency refers to processor core frequency.)
0 PROCHOT Status (R0)
When set, processor core frequency is reduced below
the operating system request due to assertion of
external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal event.
3:2 Reserved
2-224 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
4 Graphics Driver Status (R0)
When set, frequency is reduced below the operating
system request due to Processor Graphics driver
override.
5 Autonomous Utilization-Based Frequency Control
Status (R0)
When set, frequency is reduced below the operating
system request because the processor has detected
that utilization is low.
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal alert from the
Voltage Regulator.
7 Reserved
8 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating
system request due to electrical design point
constraints (e.g., maximum electrical current
consumption).
9 Core Power Limiting Status (R0)
When set, frequency is reduced below the operating
system request due to domain-level power limiting.
10 Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating
system request due to package-level power limiting
PL1.
11 Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating
system request due to package-level power limiting
PL2.
12 Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating
system request due to multi-core turbo limits.
13 Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating
system request due to Turbo transition attenuation.
This prevents performance degradation due to
frequent operating ratio changes.
15:14 Reserved
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
Vol. 4 2-225
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
17 Thermal Log
When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
19:18 Reserved
20 Graphics Driver Log
When set, indicates that the Graphics Driver Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
21 Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-
Based Frequency Control Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
23 Reserved
24 Electrical Design Point Log
When set, indicates that the EDP Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
25 Core Power Limiting Log
When set, indicates that the Core Power Limiting
Status bit has asserted since the log bit was last
cleared.
This log bit will remain set until cleared by software
writing 0.
26 Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1
Power Limiting Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
2-226 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
27 Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2
Power Limiting Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
28 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition
Attenuation Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software
writing 0.
63:30 Reserved
6B0H 1712 MSR_GRAPHICS_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in the Processor
Graphics (R/W)
(Frequency refers to processor graphics frequency.)
0 PROCHOT Status (R0)
When set, frequency is reduced below the operating
system request due to assertion of external
PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal event.
3:2 Reserved
4 Graphics Driver Status (R0)
When set, frequency is reduced below the operating
system request due to Processor Graphics driver
override.
5 Autonomous Utilization-Based Frequency Control
Status (R0)
When set, frequency is reduced below the operating
system request because the processor has detected
that utilization is low.
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal alert from the
Voltage Regulator.
7 Reserved
Vol. 4 2-227
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
8 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating
system request due to electrical design point
constraints (e.g., maximum electrical current
consumption).
9 Graphics Power Limiting Status (R0)
When set, frequency is reduced below the operating
system request due to domain-level power limiting.
10 Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating
system request due to package-level power limiting
PL1.
11 Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating
system request due to package-level power limiting
PL2.
15:12 Reserved
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
19:18 Reserved
20 Graphics Driver Log
When set, indicates that the Graphics Driver Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
21 Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-
Based Frequency Control Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
2-228 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
23 Reserved
24 Electrical Design Point Log
When set, indicates that the EDP Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
25 Core Power Limiting Log
When set, indicates that the Core Power Limiting
Status bit has asserted since the log bit was last
cleared.
This log bit will remain set until cleared by software
writing 0.
26 Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1
Power Limiting Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
27 Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2
Power Limiting Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
28 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition
Attenuation Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software
writing 0.
63:30 Reserved
6B1H 1713 MSR_RING_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in the Ring
Interconnect (R/W)
(Frequency refers to ring interconnect in the uncore.)
0 PROCHOT Status (R0)
When set, frequency is reduced below the operating
system request due to assertion of external
PROCHOT.
Vol. 4 2-229
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1 Thermal Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal event.
5:2 Reserved
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal alert from the
Voltage Regulator.
7 Reserved
8 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating
system request due to electrical design point
constraints (e.g., maximum electrical current
consumption).
9 Reserved
10 Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating
system request due to package-level power limiting
PL1.
11 Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating
system request due to package-level power limiting
PL2.
15:12 Reserved
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
19:18 Reserved.
20 Graphics Driver Log
When set, indicates that the Graphics Driver Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
2-230 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
21 Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-
Based Frequency Control Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
23 Reserved
24 Electrical Design Point Log
When set, indicates that the EDP Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
25 Core Power Limiting Log
When set, indicates that the Core Power Limiting
Status bit has asserted since the log bit was last
cleared.
This log bit will remain set until cleared by software
writing 0.
26 Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1
Power Limiting Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
27 Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2
Power Limiting Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
28 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
Vol. 4 2-231
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition
Attenuation Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software
writing 0.
63:30 Reserved
700H 1792 MSR_UNC_CBO_0_PERFEVTSEL0 Package Uncore C-Box 0, Counter 0 Event Select MSR
701H 1793 MSR_UNC_CBO_0_PERFEVTSEL1 Package Uncore C-Box 0, Counter 1 Event Select MSR
706H 1798 MSR_UNC_CBO_0_PERFCTR0 Package Uncore C-Box 0, Performance Counter 0
707H 1799 MSR_UNC_CBO_0_PERFCTR1 Package Uncore C-Box 0, Performance Counter 1
710H 1808 MSR_UNC_CBO_1_PERFEVTSEL0 Package Uncore C-Box 1, Counter 0 Event Select MSR
711H 1809 MSR_UNC_CBO_1_PERFEVTSEL1 Package Uncore C-Box 1, Counter 1 Event Select MSR
716H 1814 MSR_UNC_CBO_1_PERFCTR0 Package Uncore C-Box 1, Performance Counter 0
717H 1815 MSR_UNC_CBO_1_PERFCTR1 Package Uncore C-Box 1, Performance Counter 1
720H 1824 MSR_UNC_CBO_2_PERFEVTSEL0 Package Uncore C-Box 2, Counter 0 Event Select MSR
721H 1824 MSR_UNC_CBO_2_PERFEVTSEL1 Package Uncore C-Box 2, Counter 1 Event Select MSR
726H 1830 MSR_UNC_CBO_2_PERFCTR0 Package Uncore C-Box 2, Performance Counter 0
727H 1831 MSR_UNC_CBO_2_PERFCTR1 Package Uncore C-Box 2, Performance Counter 1
730H 1840 MSR_UNC_CBO_3_PERFEVTSEL0 Package Uncore C-Box 3, Counter 0 Event Select MSR
731H 1841 MSR_UNC_CBO_3_PERFEVTSEL1 Package Uncore C-Box 3, Counter 1 Event Select MSR
736H 1846 MSR_UNC_CBO_3_PERFCTR0 Package Uncore C-Box 3, Performance Counter 0
737H 1847 MSR_UNC_CBO_3_PERFCTR1 Package Uncore C-Box 3, Performance Counter 1
See Table 2-20, Table 2-21, Table 2-22, Table 2-25, Table 2-29 for other MSR definitions applicable to processors with CPUID
signatures 063CH, 06_46H.
2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors
The 4th generation Intel® Core™ processor family (based on Haswell microarchitecture) with CPUID
DisplayFamily_DisplayModel signature 06_45H supports the MSR interfaces listed in Table 2-20, Table 2-21, Table
2-29, Table 2-30, and Table 2-31.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors
with DisplayFamily_DisplayModel Signature 06_45H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Core C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
See http://biosbits.org.
3:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package. The
default is set as factory-configured package C-state
limit.
The following C-state code name encodings are
supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
9:4 Reserved
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved
15 CFG Lock (R/WO)
24:16 Reserved
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
63:29 Reserved
630H 1584 MSR_PKG_C8_RESIDENCY Package Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
59:0 Package C8 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C8 states. Count at the same frequency as the
TSC.
63:60 Reserved
Vol. 4 2-233
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors
with DisplayFamily_DisplayModel Signature 06_45H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
631H 1585 MSR_PKG_C9_RESIDENCY Package Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
59:0 Package C9 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C9 states. Count at the same frequency as the
TSC.
63:60 Reserved
632H 1586 MSR_PKG_C10_RESIDENCY Package Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
59:0 Package C10 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C10 states. Count at the same frequency as the
TSC.
63:60 Reserved
See Table 2-20, Table 2-21, Table 2-22, Table 2-29, Table 2-30 for other MSR definitions applicable to processors with CPUID
signature 06_45H.
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Vol. 4 2-235
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2-236 Vol. 4
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Vol. 4 2-237
MODEL-SPECIFIC REGISTERS (MSRS)
41CH 1052 IA32_MC7_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
41DH 1053 IA32_MC7_STATUS Package
Bank MC7 reports MC errors from the home agent HA 0.
41EH 1054 IA32_MC7_ADDR Package
41FH 1055 IA32_MC7_MISC Package
420H 1056 IA32_MC8_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
421H 1057 IA32_MC8_STATUS Package
Bank MC8 reports MC errors from the home agent HA 1.
422H 1058 IA32_MC8_ADDR Package
423H 1059 IA32_MC8_MISC Package
424H 1060 IA32_MC9_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
425H 1061 IA32_MC9_STATUS Package
Banks MC9 through MC 16 report MC errors from each
426H 1062 IA32_MC9_ADDR Package channel of the integrated memory controllers.
427H 1063 IA32_MC9_MISC Package
428H 1064 IA32_MC10_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
429H 1065 IA32_MC10_STATUS Package
Banks MC9 through MC 16 report MC errors from each
42AH 1066 IA32_MC10_ADDR Package channel of the integrated memory controllers.
42BH 1067 IA32_MC10_MISC Package
42CH 1068 IA32_MC11_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
42DH 1069 IA32_MC11_STATUS Package
Banks MC9 through MC 16 report MC errors from each
42EH 1070 IA32_MC11_ADDR Package channel of the integrated memory controllers.
42FH 1071 IA32_MC11_MISC Package
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MODEL-SPECIFIC REGISTERS (MSRS)
434H 1076 IA32_MC13_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
435H 1077 IA32_MC13_STATUS Package
Banks MC9 through MC 16 report MC errors from each
436H 1078 IA32_MC13_ADDR Package channel of the integrated memory controllers.
437H 1079 IA32_MC13_MISC Package
438H 1080 IA32_MC14_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
439H 1081 IA32_MC14_STATUS Package
Banks MC9 through MC 16 report MC errors from each
43AH 1082 IA32_MC14_ADDR Package channel of the integrated memory controllers.
43BH 1083 IA32_MC14_MISC Package
43CH 1084 IA32_MC15_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
43DH 1085 IA32_MC15_STATUS Package
Banks MC9 through MC 16 report MC errors from each
43EH 1086 IA32_MC15_ADDR Package channel of the integrated memory controllers.
43FH 1087 IA32_MC15_MISC Package
440H 1088 IA32_MC16_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
441H 1089 IA32_MC16_STATUS Package
Banks MC9 through MC 16 report MC errors from each
442H 1090 IA32_MC16_ADDR Package channel of the integrated memory controllers.
443H 1091 IA32_MC16_MISC Package
444H 1092 IA32_MC17_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
445H 1093 IA32_MC17_STATUS Package
Bank MC17 reports MC errors from the following pair of
446H 1094 IA32_MC17_ADDR Package CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6,
447H 1095 IA32_MC17_MISC Package CBo9, CBo12, CBo15.
448H 1096 IA32_MC18_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
449H 1097 IA32_MC18_STATUS Package
Bank MC18 reports MC errors from the following pair of
44AH 1098 IA32_MC18_ADDR Package CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
44BH 1099 IA32_MC18_MISC Package CBo10, CBo13, CBo16.
44CH 1100 IA32_MC19_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
44DH 1101 IA32_MC19_STATUS Package
Bank MC19 reports MC errors from the following pair of
44EH 1102 IA32_MC19_ADDR Package CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
44FH 1103 IA32_MC19_MISC Package CBo11, CBo14, CBo17.
450H 1104 IA32_MC20_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
451H 1105 IA32_MC20_STATUS Package
Bank MC20 reports MC errors from the Intel QPI 1
452H 1106 IA32_MC20_ADDR Package module.
453H 1107 IA32_MC20_MISC Package
Vol. 4 2-239
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2-240 Vol. 4
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Vol. 4 2-241
MODEL-SPECIFIC REGISTERS (MSRS)
2-242 Vol. 4
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Vol. 4 2-243
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2.14.1 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family
Intel Xeon Processor E5 v3 and E7 v3 family are based on the Haswell-E microarchitecture. The MSR-based uncore
PMU interfaces are listed in Table 2-33. For complete detail of the uncore PMU, refer to Intel Xeon Processor E5 v3
Product Family Uncore Performance Monitoring Guide. These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_3FH.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
706H 1798 MSR_U_PMON_EVNTSEL1 Package Uncore U-Box Perfmon Event Select for U-Box
Counter 1
708H 1800 MSR_U_PMON_BOX_STATUS Package Uncore U-Box Perfmon U-Box Wide Status
709H 1801 MSR_U_PMON_CTR0 Package Uncore U-Box Perfmon Counter 0
70AH 1802 MSR_U_PMON_CTR1 Package Uncore U-Box Perfmon Counter 1
710H 1808 MSR_PCU_PMON_BOX_CTL Package Uncore PCU Perfmon for PCU-Box-Wide Control
711H 1809 MSR_PCU_PMON_EVNTSEL0 Package Uncore PCU Perfmon Event Select for PCU Counter 0
712H 1810 MSR_PCU_PMON_EVNTSEL1 Package Uncore PCU Perfmon Event Select for PCU Counter 1
713H 1811 MSR_PCU_PMON_EVNTSEL2 Package Uncore PCU Perfmon Event Select for PCU Counter 2
714H 1812 MSR_PCU_PMON_EVNTSEL3 Package Uncore PCU Perfmon Event Select for PCU Counter 3
715H 1813 MSR_PCU_PMON_BOX_FILTER Package Uncore PCU Perfmon Box-Wide Filter
716H 1814 MSR_PCU_PMON_BOX_STATUS Package Uncore PCU Perfmon Box Wide Status
717H 1815 MSR_PCU_PMON_CTR0 Package Uncore PCU Perfmon Counter 0
718H 1816 MSR_PCU_PMON_CTR1 Package Uncore PCU Perfmon Counter 1
719H 1817 MSR_PCU_PMON_CTR2 Package Uncore PCU Perfmon Counter 2
71AH 1818 MSR_PCU_PMON_CTR3 Package Uncore PCU Perfmon Counter 3
720H 1824 MSR_S0_PMON_BOX_CTL Package Uncore SBo 0 Perfmon for SBo 0 Box-Wide Control
721H 1825 MSR_S0_PMON_EVNTSEL0 Package Uncore SBo 0 Perfmon Event Select for SBo 0
Counter 0
722H 1826 MSR_S0_PMON_EVNTSEL1 Package Uncore SBo 0 Perfmon Event Select for SBo 0
Counter 1
723H 1827 MSR_S0_PMON_EVNTSEL2 Package Uncore SBo 0 Perfmon Event Select for SBo 0
Counter 2
724H 1828 MSR_S0_PMON_EVNTSEL3 Package Uncore SBo 0 Perfmon Event Select for SBo 0
Counter 3
725H 1829 MSR_S0_PMON_BOX_FILTER Package Uncore SBo 0 Perfmon Box-Wide Filter
726H 1830 MSR_S0_PMON_CTR0 Package Uncore SBo 0 Perfmon Counter 0
727H 1831 MSR_S0_PMON_CTR1 Package Uncore SBo 0 Perfmon Counter 1
728H 1832 MSR_S0_PMON_CTR2 Package Uncore SBo 0 Perfmon Counter 2
729H 1833 MSR_S0_PMON_CTR3 Package Uncore SBo 0 Perfmon Counter 3
72AH 1834 MSR_S1_PMON_BOX_CTL Package Uncore SBo 1 Perfmon for SBo 1 Box-Wide Control
72BH 1835 MSR_S1_PMON_EVNTSEL0 Package Uncore SBo 1 Perfmon Event Select for SBo 1
Counter 0
72CH 1836 MSR_S1_PMON_EVNTSEL1 Package Uncore SBo 1 Perfmon Event Select for SBo 1
Counter 1
72DH 1837 MSR_S1_PMON_EVNTSEL2 Package Uncore SBo 1 Perfmon Event Select for SBo 1
Counter 2
72EH 1838 MSR_S1_PMON_EVNTSEL3 Package Uncore SBo 1 Perfmon Event Select for SBo 1
Counter 3
72FH 1839 MSR_S1_PMON_BOX_FILTER Package Uncore SBo 1 Perfmon Box-Wide Filter
Vol. 4 2-245
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
730H 1840 MSR_S1_PMON_CTR0 Package Uncore SBo 1 Perfmon Counter 0
731H 1841 MSR_S1_PMON_CTR1 Package Uncore SBo 1 Perfmon Counter 1
732H 1842 MSR_S1_PMON_CTR2 Package Uncore SBo 1 Perfmon Counter 2
733H 1843 MSR_S1_PMON_CTR3 Package Uncore SBo 1 Perfmon Counter 3
734H 1844 MSR_S2_PMON_BOX_CTL Package Uncore SBo 2 Perfmon for SBo 2 Box-Wide Control
735H 1845 MSR_S2_PMON_EVNTSEL0 Package Uncore SBo 2 Perfmon Event Select for SBo 2
Counter 0
736H 1846 MSR_S2_PMON_EVNTSEL1 Package Uncore SBo 2 Perfmon Event Select for SBo 2
Counter 1
737H 1847 MSR_S2_PMON_EVNTSEL2 Package Uncore SBo 2 Perfmon Event Select for SBo 2
Counter 2
738H 1848 MSR_S2_PMON_EVNTSEL3 Package Uncore SBo 2 Perfmon Event Select for SBo 2
Counter 3
739H 1849 MSR_S2_PMON_BOX_FILTER Package Uncore SBo 2 Perfmon Box-Wide Filter
73AH 1850 MSR_S2_PMON_CTR0 Package Uncore SBo 2 Perfmon Counter 0
73BH 1851 MSR_S2_PMON_CTR1 Package Uncore SBo 2 Perfmon Counter 1
73CH 1852 MSR_S2_PMON_CTR2 Package Uncore SBo 2 Perfmon Counter 2
73DH 1853 MSR_S2_PMON_CTR3 Package Uncore SBo 2 Perfmon Counter 3
73EH 1854 MSR_S3_PMON_BOX_CTL Package Uncore SBo 3 Perfmon for SBo 3 Box-Wide Control
73FH 1855 MSR_S3_PMON_EVNTSEL0 Package Uncore SBo 3 Perfmon Event Select for SBo 3
Counter 0
740H 1856 MSR_S3_PMON_EVNTSEL1 Package Uncore SBo 3 Perfmon Event Select for SBo 3
Counter 1
741H 1857 MSR_S3_PMON_EVNTSEL2 Package Uncore SBo 3 Perfmon Event Select for SBo 3
Counter 2
742H 1858 MSR_S3_PMON_EVNTSEL3 Package Uncore SBo 3 Perfmon Event Select for SBo 3
Counter 3
743H 1859 MSR_S3_PMON_BOX_FILTER Package Uncore SBo 3 Perfmon Box-Wide Filter
744H 1860 MSR_S3_PMON_CTR0 Package Uncore SBo 3 Perfmon Counter 0
745H 1861 MSR_S3_PMON_CTR1 Package Uncore SBo 3 Perfmon Counter 1
746H 1862 MSR_S3_PMON_CTR2 Package Uncore SBo 3 Perfmon Counter 2
747H 1863 MSR_S3_PMON_CTR3 Package Uncore SBo 3 Perfmon Counter 3
E00H 3584 MSR_C0_PMON_BOX_CTL Package Uncore C-Box 0 Perfmon for Box-Wide Control
E01H 3585 MSR_C0_PMON_EVNTSEL0 Package Uncore C-Box 0 Perfmon Event Select for C-Box 0
Counter 0
E02H 3586 MSR_C0_PMON_EVNTSEL1 Package Uncore C-Box 0 Perfmon Event Select for C-Box 0
Counter 1
E03H 3587 MSR_C0_PMON_EVNTSEL2 Package Uncore C-Box 0 Perfmon Event Select for C-Box 0
Counter 2
E04H 3588 MSR_C0_PMON_EVNTSEL3 Package Uncore C-Box 0 Perfmon Event Select for C-Box 0
Counter 3
2-246 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E05H 3589 MSR_C0_PMON_BOX_FILTER0 Package Uncore C-Box 0 Perfmon Box Wide Filter 0
E06H 3590 MSR_C0_PMON_BOX_FILTER1 Package Uncore C-Box 0 Perfmon Box Wide Filter 1
E07H 3591 MSR_C0_PMON_BOX_STATUS Package Uncore C-Box 0 Perfmon Box Wide Status
E08H 3592 MSR_C0_PMON_CTR0 Package Uncore C-Box 0 Perfmon Counter 0
E09H 3593 MSR_C0_PMON_CTR1 Package Uncore C-Box 0 Perfmon Counter 1
E0AH 3594 MSR_C0_PMON_CTR2 Package Uncore C-Box 0 Perfmon Counter 2
E0BH 3595 MSR_C0_PMON_CTR3 Package Uncore C-Box 0 Perfmon Counter 3
E10H 3600 MSR_C1_PMON_BOX_CTL Package Uncore C-Box 1 Perfmon for Box-Wide Control
E11H 3601 MSR_C1_PMON_EVNTSEL0 Package Uncore C-Box 1 Perfmon Event Select for C-Box 1
Counter 0
E12H 3602 MSR_C1_PMON_EVNTSEL1 Package Uncore C-Box 1 Perfmon Event Select for C-Box 1
Counter 1
E13H 3603 MSR_C1_PMON_EVNTSEL2 Package Uncore C-Box 1 Perfmon Event Select for C-Box 1
Counter 2
E14H 3604 MSR_C1_PMON_EVNTSEL3 Package Uncore C-Box 1 Perfmon Event Select for C-Box 1
Counter 3
E15H 3605 MSR_C1_PMON_BOX_FILTER0 Package Uncore C-Box 1 Perfmon Box Wide Filter 0
E16H 3606 MSR_C1_PMON_BOX_FILTER1 Package Uncore C-Box 1 Perfmon Box Wide Filter1
E17H 3607 MSR_C1_PMON_BOX_STATUS Package Uncore C-Box 1 Perfmon Box Wide Status
E18H 3608 MSR_C1_PMON_CTR0 Package Uncore C-Box 1 Perfmon Counter 0
E19H 3609 MSR_C1_PMON_CTR1 Package Uncore C-Box 1 Perfmon Counter 1
E1AH 3610 MSR_C1_PMON_CTR2 Package Uncore C-Box 1 Perfmon Counter 2
E1BH 3611 MSR_C1_PMON_CTR3 Package Uncore C-Box 1 Perfmon Counter 3
E20H 3616 MSR_C2_PMON_BOX_CTL Package Uncore C-Box 2 Perfmon for Box-Wide Control
E21H 3617 MSR_C2_PMON_EVNTSEL0 Package Uncore C-Box 2 Perfmon Event Select for C-Box 2
Counter 0
E22H 3618 MSR_C2_PMON_EVNTSEL1 Package Uncore C-Box 2 Perfmon Event Select for C-Box 2
Counter 1
E23H 3619 MSR_C2_PMON_EVNTSEL2 Package Uncore C-Box 2 Perfmon Event Select for C-Box 2
Counter 2
E24H 3620 MSR_C2_PMON_EVNTSEL3 Package Uncore C-Box 2 Perfmon Event select for C-Box 2
Counter 3
E25H 3621 MSR_C2_PMON_BOX_FILTER0 Package Uncore C-Box 2 Perfmon Box Wide Filter 0
E26H 3622 MSR_C2_PMON_BOX_FILTER1 Package Uncore C-Box 2 Perfmon Box Wide Filter1
E27H 3623 MSR_C2_PMON_BOX_STATUS Package Uncore C-Box 2 Perfmon Box Wide Status
E28H 3624 MSR_C2_PMON_CTR0 Package Uncore C-Box 2 Perfmon Counter 0
E29H 3625 MSR_C2_PMON_CTR1 Package Uncore C-Box 2 Perfmon Counter 1
E2AH 3626 MSR_C2_PMON_CTR2 Package Uncore C-Box 2 Perfmon Counter 2
E2BH 3627 MSR_C2_PMON_CTR3 Package Uncore C-Box 2 Perfmon Counter 3
Vol. 4 2-247
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E30H 3632 MSR_C3_PMON_BOX_CTL Package Uncore C-Box 3 Perfmon for Box-Wide Control
E31H 3633 MSR_C3_PMON_EVNTSEL0 Package Uncore C-Box 3 Perfmon Event Select for C-Box 3
Counter 0
E32H 3634 MSR_C3_PMON_EVNTSEL1 Package Uncore C-Box 3 Perfmon Event Select for C-Box 3
Counter 1
E33H 3635 MSR_C3_PMON_EVNTSEL2 Package Uncore C-Box 3 Perfmon Event Select for C-Box 3
Counter 2
E34H 3636 MSR_C3_PMON_EVNTSEL3 Package Uncore C-Box 3 Perfmon Event Select for C-Box 3
Counter 3
E35H 3637 MSR_C3_PMON_BOX_FILTER0 Package Uncore C-Box 3 Perfmon Box Wide Filter 0
E36H 3638 MSR_C3_PMON_BOX_FILTER1 Package Uncore C-Box 3 Perfmon Box Wide Filter1
E37H 3639 MSR_C3_PMON_BOX_STATUS Package Uncore C-Box 3 Perfmon Box Wide Status
E38H 3640 MSR_C3_PMON_CTR0 Package Uncore C-Box 3 Perfmon Counter 0
E39H 3641 MSR_C3_PMON_CTR1 Package Uncore C-Box 3 Perfmon Counter 1
E3AH 3642 MSR_C3_PMON_CTR2 Package Uncore C-Box 3 Perfmon Counter 2
E3BH 3643 MSR_C3_PMON_CTR3 Package Uncore C-Box 3 Perfmon Counter 3
E40H 3648 MSR_C4_PMON_BOX_CTL Package Uncore C-Box 4 Perfmon for Box-Wide Control
E41H 3649 MSR_C4_PMON_EVNTSEL0 Package Uncore C-Box 4 Perfmon Event Select for C-Box 4
Counter 0
E42H 3650 MSR_C4_PMON_EVNTSEL1 Package Uncore C-Box 4 Perfmon Event Select for C-Box 4
Counter 1
E43H 3651 MSR_C4_PMON_EVNTSEL2 Package Uncore C-Box 4 Perfmon Event Select for C-Box 4
Counter 2
E44H 3652 MSR_C4_PMON_EVNTSEL3 Package Uncore C-Box 4 Perfmon Event Select for C-Box 4
Counter 3
E45H 3653 MSR_C4_PMON_BOX_FILTER0 Package Uncore C-Box 4 Perfmon Box Wide Filter 0
E46H 3654 MSR_C4_PMON_BOX_FILTER1 Package Uncore C-Box 4 Perfmon Box Wide Filter1
E47H 3655 MSR_C4_PMON_BOX_STATUS Package Uncore C-Box 4 Perfmon Box Wide Status
E48H 3656 MSR_C4_PMON_CTR0 Package Uncore C-Box 4 Perfmon Counter 0
E49H 3657 MSR_C4_PMON_CTR1 Package Uncore C-Box 4 Perfmon Counter 1
E4AH 3658 MSR_C4_PMON_CTR2 Package Uncore C-Box 4 Perfmon Counter 2
E4BH 3659 MSR_C4_PMON_CTR3 Package Uncore C-Box 4 Perfmon Counter 3
E50H 3664 MSR_C5_PMON_BOX_CTL Package Uncore C-Box 5 Perfmon for Box-Wide Control
E51H 3665 MSR_C5_PMON_EVNTSEL0 Package Uncore C-Box 5 Perfmon Event Select for C-Box 5
Counter 0
E52H 3666 MSR_C5_PMON_EVNTSEL1 Package Uncore C-Box 5 Perfmon Event Select for C-Box 5
Counter 1
E53H 3667 MSR_C5_PMON_EVNTSEL2 Package Uncore C-Box 5 Perfmon Event Select for C-Box 5
Counter 2
E54H 3668 MSR_C5_PMON_EVNTSEL3 Package Uncore C-Box 5 Perfmon Event Select for C-Box 5
Counter 3
2-248 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E55H 3669 MSR_C5_PMON_BOX_FILTER0 Package Uncore C-Box 5 Perfmon Box Wide Filter 0
E56H 3670 MSR_C5_PMON_BOX_FILTER1 Package Uncore C-Box 5 Perfmon Box Wide Filter 1
E57H 3671 MSR_C5_PMON_BOX_STATUS Package Uncore C-Box 5 Perfmon Box Wide Status
E58H 3672 MSR_C5_PMON_CTR0 Package Uncore C-Box 5 Perfmon Counter 0
E59H 3673 MSR_C5_PMON_CTR1 Package Uncore C-Box 5 Perfmon Counter 1
E5AH 3674 MSR_C5_PMON_CTR2 Package Uncore C-Box 5 Perfmon Counter 2
E5BH 3675 MSR_C5_PMON_CTR3 Package Uncore C-Box 5 Perfmon Counter 3
E60H 3680 MSR_C6_PMON_BOX_CTL Package Uncore C-Box 6 Perfmon for Box-Wide Control
E61H 3681 MSR_C6_PMON_EVNTSEL0 Package Uncore C-Box 6 Perfmon Event Select for C-Box 6
Counter 0
E62H 3682 MSR_C6_PMON_EVNTSEL1 Package Uncore C-Box 6 Perfmon Event Select for C-Box 6
Counter 1
E63H 3683 MSR_C6_PMON_EVNTSEL2 Package Uncore C-Box 6 Perfmon Event Select for C-Box 6
Counter 2
E64H 3684 MSR_C6_PMON_EVNTSEL3 Package Uncore C-Box 6 Perfmon Event Select for C-Box 6
Counter 3
E65H 3685 MSR_C6_PMON_BOX_FILTER0 Package Uncore C-Box 6 Perfmon Box Wide Filter 0
E66H 3686 MSR_C6_PMON_BOX_FILTER1 Package Uncore C-Box 6 Perfmon Box Wide Filter 1
E67H 3687 MSR_C6_PMON_BOX_STATUS Package Uncore C-Box 6 Perfmon Box Wide Status
E68H 3688 MSR_C6_PMON_CTR0 Package Uncore C-Box 6 Perfmon Counter 0
E69H 3689 MSR_C6_PMON_CTR1 Package Uncore C-Box 6 Perfmon Counter 1
E6AH 3690 MSR_C6_PMON_CTR2 Package Uncore C-Box 6 Perfmon Counter 2
E6BH 3691 MSR_C6_PMON_CTR3 Package Uncore C-Box 6 Perfmon Counter 3
E70H 3696 MSR_C7_PMON_BOX_CTL Package Uncore C-Box 7 Perfmon for Box-Wide Control
E71H 3697 MSR_C7_PMON_EVNTSEL0 Package Uncore C-Box 7 Perfmon Event Select for C-Box 7
Counter 0
E72H 3698 MSR_C7_PMON_EVNTSEL1 Package Uncore C-Box 7 Perfmon Event Select for C-Box 7
Counter 1
E73H 3699 MSR_C7_PMON_EVNTSEL2 Package Uncore C-Box 7 Perfmon Event Select for C-Box 7
Counter 2
E74H 3700 MSR_C7_PMON_EVNTSEL3 Package Uncore C-Box 7 Perfmon Event Select for C-Box 7
Counter 3
E75H 3701 MSR_C7_PMON_BOX_FILTER0 Package Uncore C-Box 7 Perfmon Box Wide Filter 0
E76H 3702 MSR_C7_PMON_BOX_FILTER1 Package Uncore C-Box 7 Perfmon Box Wide Filter 1
E77H 3703 MSR_C7_PMON_BOX_STATUS Package Uncore C-Box 7 Perfmon Box Wide Status
E78H 3704 MSR_C7_PMON_CTR0 Package Uncore C-Box 7 Perfmon Counter 0
E79H 3705 MSR_C7_PMON_CTR1 Package Uncore C-Box 7 Perfmon Counter 1
E7AH 3706 MSR_C7_PMON_CTR2 Package Uncore C-Box 7 Perfmon Counter 2
E7BH 3707 MSR_C7_PMON_CTR3 Package Uncore C-Box 7 Perfmon Counter 3
Vol. 4 2-249
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
E80H 3712 MSR_C8_PMON_BOX_CTL Package Uncore C-Box 8 Perfmon Local Box Wide Control
E81H 3713 MSR_C8_PMON_EVNTSEL0 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 0
E82H 3714 MSR_C8_PMON_EVNTSEL1 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 1
E83H 3715 MSR_C8_PMON_EVNTSEL2 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 2
E84H 3716 MSR_C8_PMON_EVNTSEL3 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 3
E85H 3717 MSR_C8_PMON_BOX_FILTER0 Package Uncore C-Box 8 Perfmon Box Wide Filter 0
E86H 3718 MSR_C8_PMON_BOX_FILTER1 Package Uncore C-Box 8 Perfmon Box Wide Filter 1
E87H 3719 MSR_C8_PMON_BOX_STATUS Package Uncore C-Box 8 Perfmon Box Wide Status
E88H 3720 MSR_C8_PMON_CTR0 Package Uncore C-Box 8 Perfmon Counter 0
E89H 3721 MSR_C8_PMON_CTR1 Package Uncore C-Box 8 Perfmon Counter 1
E8AH 3722 MSR_C8_PMON_CTR2 Package Uncore C-Box 8 Perfmon Counter 2
E8BH 3723 MSR_C8_PMON_CTR3 Package Uncore C-Box 8 Perfmon Counter 3
E90H 3728 MSR_C9_PMON_BOX_CTL Package Uncore C-Box 9 Perfmon Local Box Wide Control
E91H 3729 MSR_C9_PMON_EVNTSEL0 Package Uncore C-Box 9 Perfmon Event Select for C-Box 9
Counter 0
E92H 3730 MSR_C9_PMON_EVNTSEL1 Package Uncore C-Box 9 Perfmon Event Select for C-Box 9
Counter 1
E93H 3731 MSR_C9_PMON_EVNTSEL2 Package Uncore C-Box 9 Perfmon Event Select for C-Box 9
Counter 2
E94H 3732 MSR_C9_PMON_EVNTSEL3 Package Uncore C-Box 9 Perfmon Event Select for C-Box 9
Counter 3
E95H 3733 MSR_C9_PMON_BOX_FILTER0 Package Uncore C-Box 9 Perfmon Box Wide Filter 0
E96H 3734 MSR_C9_PMON_BOX_FILTER1 Package Uncore C-Box 9 Perfmon Box Wide Filter 1
E97H 3735 MSR_C9_PMON_BOX_STATUS Package Uncore C-Box 9 Perfmon Box Wide Status
E98H 3736 MSR_C9_PMON_CTR0 Package Uncore C-Box 9 Perfmon Counter 0
E99H 3737 MSR_C9_PMON_CTR1 Package Uncore C-Box 9 Perfmon Counter 1
E9AH 3738 MSR_C9_PMON_CTR2 Package Uncore C-Box 9 Perfmon Counter 2
E9BH 3739 MSR_C9_PMON_CTR3 Package Uncore C-Box 9 Perfmon Counter 3
EA0H 3744 MSR_C10_PMON_BOX_CTL Package Uncore C-Box 10 Perfmon Local Box Wide Control
EA1H 3745 MSR_C10_PMON_EVNTSEL0 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10
Counter 0
EA2H 3746 MSR_C10_PMON_EVNTSEL1 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10
Counter 1
EA3H 3747 MSR_C10_PMON_EVNTSEL2 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10
Counter 2
EA4H 3748 MSR_C10_PMON_EVNTSEL3 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10
Counter 3
2-250 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
EA5H 3749 MSR_C10_PMON_BOX_FILTER0 Package Uncore C-Box 10 Perfmon Box Wide Filter 0
EA6H 3750 MSR_C10_PMON_BOX_FILTER1 Package Uncore C-Box 10 Perfmon Box Wide Filter 1
EA7H 3751 MSR_C10_PMON_BOX_STATUS Package Uncore C-Box 10 Perfmon Box Wide Status
EA8H 3752 MSR_C10_PMON_CTR0 Package Uncore C-Box 10 Perfmon Counter 0
EA9H 3753 MSR_C10_PMON_CTR1 Package Uncore C-Box 10 perfmon Counter 1
EAAH 3754 MSR_C10_PMON_CTR2 Package Uncore C-Box 10 Perfmon Counter 2
EABH 3755 MSR_C10_PMON_CTR3 Package Uncore C-Box 10 Perfmon Counter 3
EB0H 3760 MSR_C11_PMON_BOX_CTL Package Uncore C-Box 11 Perfmon Local Box Wide Control
EB1H 3761 MSR_C11_PMON_EVNTSEL0 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11
Counter 0
EB2H 3762 MSR_C11_PMON_EVNTSEL1 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11
Counter 1
EB3H 3763 MSR_C11_PMON_EVNTSEL2 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11
Counter 2
EB4H 3764 MSR_C11_PMON_EVNTSEL3 Package Uncore C-box 11 Perfmon Event Select for C-Box 11
Counter 3
EB5H 3765 MSR_C11_PMON_BOX_FILTER0 Package Uncore C-Box 11 Perfmon Box Wide Filter 0
EB6H 3766 MSR_C11_PMON_BOX_FILTER1 Package Uncore C-Box 11 Perfmon Box Wide Filter 1
EB7H 3767 MSR_C11_PMON_BOX_STATUS Package Uncore C-Box 11 Perfmon Box Wide Status
EB8H 3768 MSR_C11_PMON_CTR0 Package Uncore C-Box 11 Perfmon Counter 0
EB9H 3769 MSR_C11_PMON_CTR1 Package Uncore C-Box 11 Perfmon Counter 1
EBAH 3770 MSR_C11_PMON_CTR2 Package Uncore C-Box 11 Perfmon Counter 2
EBBH 3771 MSR_C11_PMON_CTR3 Package Uncore C-Box 11 Perfmon Counter 3
EC0H 3776 MSR_C12_PMON_BOX_CTL Package Uncore C-Box 12 Perfmon Local Box Wide Control
EC1H 3777 MSR_C12_PMON_EVNTSEL0 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12
Counter 0
EC2H 3778 MSR_C12_PMON_EVNTSEL1 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12
Counter 1
EC3H 3779 MSR_C12_PMON_EVNTSEL2 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12
Counter 2
EC4H 3780 MSR_C12_PMON_EVNTSEL3 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12
Counter 3
EC5H 3781 MSR_C12_PMON_BOX_FILTER0 Package Uncore C-Box 12 Perfmon Box Wide Filter 0
EC6H 3782 MSR_C12_PMON_BOX_FILTER1 Package Uncore C-Box 12 Perfmon Box Wide Filter 1
EC7H 3783 MSR_C12_PMON_BOX_STATUS Package Uncore C-Box 12 Perfmon Box Wide Status
EC8H 3784 MSR_C12_PMON_CTR0 Package Uncore C-Box 12 Perfmon Counter 0
EC9H 3785 MSR_C12_PMON_CTR1 Package Uncore C-Box 12 Perfmon Counter 1
ECAH 3786 MSR_C12_PMON_CTR2 Package Uncore C-Box 12 Perfmon Counter 2
ECBH 3787 MSR_C12_PMON_CTR3 Package Uncore C-Box 12 Perfmon Counter 3
Vol. 4 2-251
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
ED0H 3792 MSR_C13_PMON_BOX_CTL Package Uncore C-Box 13 Perfmon local box wide control.
ED1H 3793 MSR_C13_PMON_EVNTSEL0 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13
Counter 0
ED2H 3794 MSR_C13_PMON_EVNTSEL1 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13
Counter 1
ED3H 3795 MSR_C13_PMON_EVNTSEL2 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13
Counter 2
ED4H 3796 MSR_C13_PMON_EVNTSEL3 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13
Counter 3
ED5H 3797 MSR_C13_PMON_BOX_FILTER0 Package Uncore C-Box 13 Perfmon Box Wide Filter 0
ED6H 3798 MSR_C13_PMON_BOX_FILTER1 Package Uncore C-Box 13 Perfmon Box Wide Filter 1
ED7H 3799 MSR_C13_PMON_BOX_STATUS Package Uncore C-Box 13 Perfmon Box Wide Status
ED8H 3800 MSR_C13_PMON_CTR0 Package Uncore C-Box 13 Perfmon Counter 0
ED9H 3801 MSR_C13_PMON_CTR1 Package Uncore C-Box 13 Perfmon Counter 1
EDAH 3802 MSR_C13_PMON_CTR2 Package Uncore C-Box 13 Perfmon Counter 2
EDBH 3803 MSR_C13_PMON_CTR3 Package Uncore C-Box 13 Perfmon Counter 3
EE0H 3808 MSR_C14_PMON_BOX_CTL Package Uncore C-Box 14 Perfmon Local Box Wide Control
EE1H 3809 MSR_C14_PMON_EVNTSEL0 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14
Counter 0
EE2H 3810 MSR_C14_PMON_EVNTSEL1 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14
Counter 1
EE3H 3811 MSR_C14_PMON_EVNTSEL2 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14
Counter 2
EE4H 3812 MSR_C14_PMON_EVNTSEL3 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14
Counter 3
EE5H 3813 MSR_C14_PMON_BOX_FILTER Package Uncore C-Box 14 Perfmon Box Wide Filter 0
EE6H 3814 MSR_C14_PMON_BOX_FILTER1 Package Uncore C-Box 14 Perfmon Box Wide Filter 1
EE7H 3815 MSR_C14_PMON_BOX_STATUS Package Uncore C-Box 14 Perfmon Box Wide Status
EE8H 3816 MSR_C14_PMON_CTR0 Package Uncore C-Box 14 Perfmon Counter 0
EE9H 3817 MSR_C14_PMON_CTR1 Package Uncore C-Box 14 Perfmon Counter 1
EEAH 3818 MSR_C14_PMON_CTR2 Package Uncore C-Box 14 Perfmon Counter 2
EEBH 3819 MSR_C14_PMON_CTR3 Package Uncore C-Box 14 Perfmon Counter 3
EF0H 3824 MSR_C15_PMON_BOX_CTL Package Uncore C-Box 15 Perfmon Local Box Wide Control
EF1H 3825 MSR_C15_PMON_EVNTSEL0 Package Uncore C-Box 15 Perfmon Event Select for C-Box 15
Counter 0
EF2H 3826 MSR_C15_PMON_EVNTSEL1 Package Uncore C-Box 15 Perfmon Event Select for C-Box 15
Counter 1
EF3H 3827 MSR_C15_PMON_EVNTSEL2 Package Uncore C-Box 15 Perfmon Event Select for C-Box 15
Counter 2
EF4H 3828 MSR_C15_PMON_EVNTSEL3 Package Uncore C-Box 15 Perfmon Event Select for C-Box 15
Counter 3
2-252 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
EF5H 3829 MSR_C15_PMON_BOX_FILTER0 Package Uncore C-Box 15 Perfmon Box Wide Filter 0
EF6H 3830 MSR_C15_PMON_BOX_FILTER1 Package Uncore C-Box 15 Perfmon Box Wide Filter 1
EF7H 3831 MSR_C15_PMON_BOX_STATUS Package Uncore C-Box 15 Perfmon Box Wide Status
EF8H 3832 MSR_C15_PMON_CTR0 Package Uncore C-Box 15 Perfmon Counter 0
EF9H 3833 MSR_C15_PMON_CTR1 Package Uncore C-Box 15 Perfmon Counter 1
EFAH 3834 MSR_C15_PMON_CTR2 Package Uncore C-Box 15 Perfmon Counter 2
EFBH 3835 MSR_C15_PMON_CTR3 Package Uncore C-Box 15 Perfmon Counter 3
F00H 3840 MSR_C16_PMON_BOX_CTL Package Uncore C-Box 16 Perfmon for Box-Wide Control
F01H 3841 MSR_C16_PMON_EVNTSEL0 Package Uncore C-Box 16 Perfmon Event Select for C-Box 16
Counter 0
F02H 3842 MSR_C16_PMON_EVNTSEL1 Package Uncore C-Box 16 Perfmon Event Select for C-Box 16
Counter 1
F03H 3843 MSR_C16_PMON_EVNTSEL2 Package Uncore C-Box 16 Perfmon Event Select for C-Box 16
Counter 2
F04H 3844 MSR_C16_PMON_EVNTSEL3 Package Uncore C-Box 16 Perfmon Event Select for C-Box 16
Counter 3
F05H 3845 MSR_C16_PMON_BOX_FILTER0 Package Uncore C-Box 16 Perfmon Box Wide Filter 0
F06H 3846 MSR_C16_PMON_BOX_FILTER1 Package Uncore C-Box 16 Perfmon Box Wide Filter 1
F07H 3847 MSR_C16_PMON_BOX_STATUS Package Uncore C-Box 16 Perfmon Box Wide Status
F08H 3848 MSR_C16_PMON_CTR0 Package Uncore C-Box 16 Perfmon Counter 0
F09H 3849 MSR_C16_PMON_CTR1 Package Uncore C-Box 16 Perfmon Counter 1
F0AH 3850 MSR_C16_PMON_CTR2 Package Uncore C-Box 16 Perfmon Counter 2
F0BH 3851 MSR_C16_PMON_CTR3 Package Uncore C-Box 16 Perfmon Counter 3
F10H 3856 MSR_C17_PMON_BOX_CTL Package Uncore C-Box 17 Perfmon for Box-Wide Control
F11H 3857 MSR_C17_PMON_EVNTSEL0 Package Uncore C-Box 17 Perfmon Event Select for C-Box 17
Counter 0
F12H 3858 MSR_C17_PMON_EVNTSEL1 Package Uncore C-Box 17 Perfmon Event Select for C-Box 17
Counter 1
F13H 3859 MSR_C17_PMON_EVNTSEL2 Package Uncore C-Box 17 Perfmon Event Select for C-Box 17
Counter 2
F14H 3860 MSR_C17_PMON_EVNTSEL3 Package Uncore C-Box 17 Perfmon Event Select for C-Box 17
Counter 3
F15H 3861 MSR_C17_PMON_BOX_FILTER0 Package Uncore C-Box 17 Perfmon Box Wide Filter 0
F16H 3862 MSR_C17_PMON_BOX_FILTER1 Package Uncore C-Box 17 Perfmon Box Wide Filter1
F17H 3863 MSR_C17_PMON_BOX_STATUS Package Uncore C-Box 17 Perfmon Box Wide Status
F18H 3864 MSR_C17_PMON_CTR0 Package Uncore C-Box 17 Perfmon Counter 0
F19H 3865 MSR_C17_PMON_CTR1 Package Uncore C-Box 17 Perfmon Counter 1
F1AH 3866 MSR_C17_PMON_CTR2 Package Uncore C-Box 17 Perfmon Counter 2
F1BH 3867 MSR_C17_PMON_CTR3 Package Uncore C-Box 17 Perfmon Counter 3
Vol. 4 2-253
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-34. Additional MSRs Common to Processors Based the Broadwell Microarchitectures
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
38EH 910 IA32_PERF_GLOBAL_STATUS Thread See Table 2-2. See Section 18.6.2.2, “Global Counter
Control Facilities.”
0 Ovf_PMC0
1 Ovf_PMC1
2 Ovf_PMC2
3 Ovf_PMC3
31:4 Reserved
32 Ovf_FixedCtr0
33 Ovf_FixedCtr1
34 Ovf_FixedCtr2
54:35 Reserved
55 Trace_ToPA_PMI
See Section 31.2.6.2, “Table of Physical Addresses
(ToPA).”
60:56 Reserved
61 Ovf_Uncore
62 Ovf_BufDSSAVE
63 CondChgd
390H 912 IA32_PERF_GLOBAL_OVF_CTRL Thread See Table 2-2. See Section 18.6.2.2, “Global Counter
Control Facilities.”
0 Set 1 to clear Ovf_PMC0
1 Set 1 to clear Ovf_PMC1
2 Set 1 to clear Ovf_PMC2
3 Set 1 to clear Ovf_PMC3
31:4 Reserved
32 Set 1 to clear Ovf_FixedCtr0
33 Set 1 to clear Ovf_FixedCtr1
2-254 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-34. Additional MSRs Common to Processors Based the Broadwell Microarchitectures
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
34 Set 1 to clear Ovf_FixedCtr2
54:35 Reserved.
55 Set 1 to clear Trace_ToPA_PMI.
See Section 31.2.6.2, “Table of Physical Addresses
(ToPA).”
60:56 Reserved
61 Set 1 to clear Ovf_Uncore
62 Set 1 to clear Ovf_BufDSSAVE
63 Set 1 to clear CondChgd
560H 1376 IA32_RTIT_OUTPUT_BASE THREAD Trace Output Base Register (R/W)
6:0 Reserved
MAXPHYADDR1-1:7 Base physical address.
63:MAXPHYADDR Reserved
561H 1377 IA32_RTIT_OUTPUT_MASK_PTRS THREAD Trace Output Mask Pointers Register (R/W)
6:0 Reserved
31:7 MaskOrTableOffset
63:32 Output Offset.
570H 1392 IA32_RTIT_CTL Thread Trace Control Register (R/W)
0 TraceEn
1 Reserved, must be zero.
2 OS
3 User
6:4 Reserved, must be zero.
7 CR3 filter
8 ToPA
Writing 0 will #GP if also setting TraceEn.
9 Reserved, must be zero.
10 TSCEn
11 DisRETC
12 Reserved, must be zero.
13 Reserved; writing 0 will #GP if also setting TraceEn.
63:14 Reserved, must be zero.
571H 1393 IA32_RTIT_STATUS Thread Tracing Status Register (R/W)
0 Reserved, writes ignored.
1 ContexEn, writes ignored.
2 TriggerEn, writes ignored.
3 Reserved
Vol. 4 2-255
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-34. Additional MSRs Common to Processors Based the Broadwell Microarchitectures
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
4 Error (R/W)
5 Stopped
63:6 Reserved, must be zero.
572H 1394 IA32_RTIT_CR3_MATCH THREAD Trace Filter CR3 Match Register (R/W)
4:0 Reserved
63:5 CR3[63:5] value to match.
620H 1568 MSR UNCORE_RATIO_LIMIT Package Uncore Ratio Limit (R/W)
Out of reset, the min_ratio and max_ratio fields
represent the widest possible range of uncore
frequencies. Writing to these fields allows software to
control the minimum and the maximum frequency that
hardware will select.
63:15 Reserved
14:8 MIN_RATIO
Writing to this field controls the minimum possible
ratio of the LLC/Ring.
7 Reserved
6:0 MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
NOTES:
1. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].
Table 2-35 lists MSRs that are specific to Intel Core M processors and 5th Generation Intel Core Processors.
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Scope
Address Register Name Bit Description
Hex Dec
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Core C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
See http://biosbits.org.
2-256 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Scope
Address Register Name Bit Description
Hex Dec
3:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
9:4 Reserved
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved
15 CFG Lock (R/WO)
24:16 Reserved
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Enable Package C-State Auto-Demotion (R/W)
30 Enable Package C-State Undemotion (R/W)
63:31 Reserved
1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0.
RW if MSR_PLATFORM_INFO.[28] = 1.
7:0 Package Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8 Package Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16 Package Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24 Package Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
Vol. 4 2-257
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Scope
Address Register Name Bit Description
Hex Dec
39:32 Package Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5core active.
47:40 Package Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6core active.
63:48 Reserved
639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
See Table 2-20, Table 2-21, Table 2-22, Table 2-25, Table 2-29, Table 2-30, Table 2-34 for other MSR definitions applicable to
processors with CPUID signature 06_3DH.
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
4EH 78 MSR_PPIN_CTL Package Protected Processor Inventory Number Enable Control
(R/W)
0 LockOut (R/WO)
See Table 2-26.
1 Enable_PPIN (R/W)
See Table 2-26.
63:2 Reserved
4FH 79 MSR_PPIN Package Protected Processor Inventory Number (R/O)
63:0 Protected Processor Inventory Number (R/O)
See Table 2-26.
CEH 206 MSR_PLATFORM_INFO Package Platform Information
Contains power management and other model specific
features enumeration. See http://biosbits.org.
7:0 Reserved
15:8 Package Maximum Non-Turbo Ratio (R/O)
See Table 2-26.
22:16 Reserved.
2-258 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
23 Package PPIN_CAP (R/O)
See Table 2-26.
27:24 Reserved
28 Package Programmable Ratio Limit for Turbo Mode (R/O)
See Table 2-26.
29 Package Programmable TDP Limit for Turbo Mode (R/O)
See Table 2-26.
30 Package Programmable TJ OFFSET (R/O)
See Table 2-26.
39:31 Reserved
47:40 Package Maximum Efficiency Ratio (R/O)
See Table 2-26.
63:48 Reserved
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Core C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
See http://biosbits.org.
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package. The
default is set as factory-configured package C-state
limit.
The following C-state code name encodings are
supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported
by the processor are available.
9:3 Reserved
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved
15 CFG Lock (R/WO)
16 Automatic C-State Conversion Enable (R/W)
If 1, the processor will convert HALT or MWAT(C1) to
MWAIT(C6).
24:17 Reserved
25 C3 State Auto Demotion Enable (R/W)
Vol. 4 2-259
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Package C State Demotion Enable (R/W)
30 Package C State UnDemotion Enable (R/W)
63:31 Reserved
179H 377 IA32_MCG_CAP Thread Global Machine Check Capability (R/O)
7:0 Count
8 MCG_CTL_P
9 MCG_EXT_P
10 MCP_CMCI_P
11 MCG_TES_P
15:12 Reserved
23:16 MCG_EXT_CNT
24 MCG_SER_P
25 MCG_EM_P
26 MCG_ELOG_P
63:27 Reserved
17DH 381 MSR_SMM_MCA_CAP Thread Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only
while in SMM.
57:0 Reserved
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1, indicates that the SMM code access
restriction is supported and a host-space interface
available to SMM handler.
59 Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator is
supported and a host-space interface available to SMM
handler.
63:60 Reserved
19CH 412 IA32_THERM_STATUS Core Thermal Monitor Status (R/W)
See Table 2-2.
0 Thermal Status (RO)
See Table 2-2.
1 Thermal Status Log (R/WC0)
See Table 2-2.
2-260 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
2 PROTCHOT # or FORCEPR# Status (RO)
See Table 2-2.
3 PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4 Critical Temperature Status (RO)
See Table 2-2.
5 Critical Temperature Status Log (R/WC0)
See Table 2-2.
6 Thermal Threshold #1 Status (RO)
See Table 2-2.
7 Thermal Threshold #1 Log (R/WC0)
See Table 2-2.
8 Thermal Threshold #2 Status (RO)
See Table 2-2.
9 Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10 Power Limitation Status (RO)
See Table 2-2.
11 Power Limitation Log (R/WC0)
See Table 2-2.
12 Current Limit Status (RO)
See Table 2-2.
13 Current Limit Log (R/WC0)
See Table 2-2.
14 Cross Domain Limit Status (RO)
See Table 2-2.
15 Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16 Digital Readout (RO)
See Table 2-2.
26:23 Reserved
30:27 Resolution in Degrees Celsius (RO)
See Table 2-2.
31 Reading Valid (RO)
See Table 2-2.
63:32 Reserved
1A2H 418 MSR_TEMPERATURE_TARGET Package Temperature Target
15:0 Reserved
Vol. 4 2-261
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
23:16 Temperature Target (RO)
See Table 2-26.
27:24 TCC Activation Offset (R/W)
See Table 2-26.
63:28 Reserved.
1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0.
RW if MSR_PLATFORM_INFO.[28] = 1.
7:0 Package Maximum Ratio Limit for 1C
15:8 Package Maximum Ratio Limit for 2C
23:16 Package Maximum Ratio Limit for 3C
31:24 Package Maximum Ratio Limit for 4C
39:32 Package Maximum Ratio Limit for 5C
47:40 Package Maximum Ratio Limit for 6C
55:48 Package Maximum Ratio Limit for 7C
63:56 Package Maximum Ratio Limit for 8C
1AEH 430 MSR_TURBO_RATIO_LIMIT1 Package Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0.
RW if MSR_PLATFORM_INFO.[28] = 1.
7:0 Package Maximum Ratio Limit for 9C
15:8 Package Maximum Ratio Limit for 10C
23:16 Package Maximum Ratio Limit for 11C
31:24 Package Maximum Ratio Limit for 12C
39:32 Package Maximum Ratio Limit for 13C
47:40 Package Maximum Ratio Limit for 14C
55:48 Package Maximum Ratio Limit for 15C
63:56 Package Maximum Ratio Limit for 16C
606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers Used in RAPL Interfaces (R/O)
3:0 Package Power Units
See Section 14.10.1, “RAPL Interfaces.”
7:4 Package Reserved
12:8 Package Energy Status Units
Energy related information (in Joules) is based on the
multiplier, 1/2^ESU; where ESU is an unsigned integer
represented by bits 12:8. Default value is 0EH (or 61
micro-joules).
15:13 Package Reserved
2-262 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
19:16 Package Time Units
See Section 14.10.1, “RAPL Interfaces.”
63:20 Reserved
618H 1560 MSR_DRAM_POWER_LIMIT Package DRAM RAPL Power Limit Control (R/W)
See Section 14.10.5, “DRAM RAPL Domain.”
619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O)
Energy consumed by DRAM devices.
31:0 Energy in 15.3 micro-joules. Requires BIOS
configuration to enable DRAM RAPL mode 0 (Direct VR).
63:32 Reserved
61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W)
See Section 14.10.5, “DRAM RAPL Domain.”
620H 1568 MSR UNCORE_RATIO_LIMIT Package Uncore Ratio Limit (R/W)
Out of reset, the min_ratio and max_ratio fields
represent the widest possible range of uncore
frequencies. Writing to these fields allows software to
control the minimum and the maximum frequency that
hardware will select.
63:15 Reserved
14:8 MIN_RATIO
Writing to this field controls the minimum possible ratio
of the LLC/Ring.
7 Reserved
6:0 MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
639H 1593 MSR_PP0_ENERGY_STATUS Package Reserved (R/O)
Reads return 0.
690H 1680 MSR_CORE_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in Processor Cores
(R/W)
(Frequency refers to processor core frequency.)
0 PROCHOT Status (R0)
When set, processor core frequency is reduced below
the operating system request due to assertion of
external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal event.
Vol. 4 2-263
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
2 Power Budget Management Status (R0)
When set, frequency is reduced below the operating
system request due to PBM limit.
3 Platform Configuration Services Status (R0)
When set, frequency is reduced below the operating
system request due to PCS limit.
4 Reserved
5 Autonomous Utilization-Based Frequency Control
Status (R0)
When set, frequency is reduced below the operating
system request because the processor has detected
that utilization is low.
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal alert from the Voltage
Regulator.
7 Reserved
8 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating
system request due to electrical design point
constraints (e.g., maximum electrical current
consumption).
9 Reserved
10 Multi-Core Turbo Status (R0)
When set, frequency is reduced below the operating
system request due to Multi-Core Turbo limits.
12:11 Reserved
13 Core Frequency P1 Status (R0)
When set, frequency is reduced below max non-turbo
P1.
14 Core Max N-Core Turbo Frequency Limiting Status (R0)
When set, frequency is reduced below max n-core
turbo frequency.
15 Core Frequency Limiting Status (R0)
When set, frequency is reduced below the operating
system request.
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
2-264 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
17 Thermal Log
When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
18 Power Budget Management Log
When set, indicates that the PBM Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
19 Platform Configuration Services Log
When set, indicates that the PCS Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
20 Reserved
21 Autonomous Utilization-Based Frequency Control Log
When set, indicates that the AUBFC Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
23 Reserved
24 Electrical Design Point Log
When set, indicates that the EDP Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
25 Reserved
26 Multi-Core Turbo Log
When set, indicates that the Multi-Core Turbo Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
28:27 Reserved
Vol. 4 2-265
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
29 Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
30 Core Max N-Core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo
Frequency Limiting Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
31 Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting
Status bit has asserted since the log bit was last
cleared.
This log bit will remain set until cleared by software
writing 0.
63:32 Reserved
770H 1904 IA32_PM_ENABLE Package See Section 14.4.2, “Enabling HWP”.
771H 1905 IA32_HWP_CAPABILITIES Thread See Section 14.4.3, “HWP Performance Range and
Dynamic Capabilities”.
774H 1908 IA32_HWP_REQUEST Thread See Section 14.4.4, “Managing HWP”.
7:0 Minimum Performance (R/W)
15:8 Maximum Performance (R/W)
23:16 Desired Performance (R/W)
63:24 Reserved
777H 1911 IA32_HWP_STATUS Thread See Section 14.4.5, “HWP Feedback”.
1:0 Reserved
2 Excursion to Minimum (RO)
63:3 Reserved
C8DH 3213 IA32_QM_EVTSEL THREAD Monitoring Event Select Register (R/W)
If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.
7:0 EventID (RW)
Event encoding:
0x00: No monitoring.
0x01: L3 occupancy monitoring.
0x02: Total memory bandwidth monitoring.
0x03: Local memory bandwidth monitoring.
All other encoding reserved.
31:8 Reserved
2-266 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
41:32 RMID (RW)
63:42 Reserved
C8FH 3215 IA32_PQR_ASSOC THREAD Resource Association Register (R/W)
9:0 RMID
31:10 Reserved
51:32 COS (R/W)
63: 52 Reserved
C90H 3216 IA32_L3_QOS_MASK_0 Package L3 Class Of Service Mask - COS 0 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
0:19 CBM: Bit vector of available L3 ways for COS 0
enforcement.
63:20 Reserved
C91H 3217 IA32_L3_QOS_MASK_1 Package L3 Class Of Service Mask - COS 1 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.
0:19 CBM: Bit vector of available L3 ways for COS 1
enforcement.
63:20 Reserved
C92H 3218 IA32_L3_QOS_MASK_2 Package L3 Class Of Service Mask - COS 2 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.
0:19 CBM: Bit vector of available L3 ways for COS 2
enforcement.
63:20 Reserved
C93H 3219 IA32_L3_QOS_MASK_3 Package L3 Class Of Service Mask - COS 3 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
0:19 CBM: Bit vector of available L3 ways for COS 3
enforcement.
63:20 Reserved
C94H 3220 IA32_L3_QOS_MASK_4 Package L3 Class Of Service Mask - COS 4 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4.
0:19 CBM: Bit vector of available L3 ways for COS 4
enforcement.
63:20 Reserved
C95H 3221 IA32_L3_QOS_MASK_5 Package L3 Class Of Service Mask - COS 5 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5.
0:19 CBM: Bit vector of available L3 ways for COS 5
enforcement.
63:20 Reserved
C96H 3222 IA32_L3_QOS_MASK_6 Package L3 Class Of Service Mask - COS 6 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6.
Vol. 4 2-267
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
0:19 CBM: Bit vector of available L3 ways for COS 6
enforcement.
63:20 Reserved
C97H 3223 IA32_L3_QOS_MASK_7 Package L3 Class Of Service Mask - COS 7 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7.
0:19 CBM: Bit vector of available L3 ways for COS 7
enforcement.
63:20 Reserved
C98H 3224 IA32_L3_QOS_MASK_8 Package L3 Class Of Service Mask - COS 8 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8.
0:19 CBM: Bit vector of available L3 ways for COS 8
enforcement.
63:20 Reserved
C99H 3225 IA32_L3_QOS_MASK_9 Package L3 Class Of Service Mask - COS 9 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9.
0:19 CBM: Bit vector of available L3 ways for COS 9
enforcement.
63:20 Reserved
C9AH 3226 IA32_L3_QOS_MASK_10 Package L3 Class Of Service Mask - COS 10 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=10.
0:19 CBM: Bit vector of available L3 ways for COS 10
enforcement.
63:20 Reserved
C9BH 3227 IA32_L3_QOS_MASK_11 Package L3 Class Of Service Mask - COS 11 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=11.
0:19 CBM: Bit vector of available L3 ways for COS 11
enforcement.
63:20 Reserved
C9CH 3228 IA32_L3_QOS_MASK_12 Package L3 Class Of Service Mask - COS 12 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=12.
0:19 CBM: Bit vector of available L3 ways for COS 12
enforcement.
63:20 Reserved
C9DH 3229 IA32_L3_QOS_MASK_13 Package L3 Class Of Service Mask - COS 13 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=13.
0:19 CBM: Bit vector of available L3 ways for COS 13
enforcement.
63:20 Reserved
C9EH 3230 IA32_L3_QOS_MASK_14 Package L3 Class Of Service Mask - COS 14 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=14.
2-268 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family
Based on the Broadwell Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
0:19 CBM: Bit vector of available L3 ways for COS 14
enforcement.
63:20 Reserved
C9FH 3231 IA32_L3_QOS_MASK_15 Package L3 Class Of Service Mask - COS 15 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=15.
0:19 CBM: Bit vector of available L3 ways for COS 15
enforcement.
63:20 Reserved
2.16.1 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family
The MSRs listed in Table 2-37 are available to Intel® Xeon® Processor D Product Family (CPUID
DisplayFamily_DisplayModel = 06_56H). The Intel® Xeon® processor D product family is based on the Broadwell
microarchitecture and supports the MSR interfaces listed in Table 2-20, Table 2-29, Table 2-34, Table 2-36, and
Table 2-37.
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1ACH 428 MSR_TURBO_RATIO_LIMIT3 Package Config Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0.
RW if MSR_PLATFORM_INFO.[28] = 1.
62:0 Package Reserved
63 Package Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration1
specified in MSR_TURBO_RATIO_LIMIT,
MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration
(Default).
286H 646 IA32_MC6_CTL2 Package See Table 2-2.
287H 647 IA32_MC7_CTL2 Package See Table 2-2.
289H 649 IA32_MC9_CTL2 Package See Table 2-2.
28AH 650 IA32_MC10_CTL2 Package See Table 2-2.
291H 657 IA32_MC17_CTL2 Package See Table 2-2.
292H 658 IA32_MC18_CTL2 Package See Table 2-2.
293H 659 IA32_MC19_CTL2 Package See Table 2-2.
Vol. 4 2-269
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
418H 1048 IA32_MC6_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
419H 1049 IA32_MC6_STATUS Package
Bank MC6 reports MC errors from the integrated I/O
41AH 1050 IA32_MC6_ADDR Package module.
41BH 1051 IA32_MC6_MISC Package
41CH 1052 IA32_MC7_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
41DH 1053 IA32_MC7_STATUS Package
Bank MC7 reports MC errors from the home agent HA 0.
41EH 1054 IA32_MC7_ADDR Package
41FH 1055 IA32_MC7_MISC Package
424H 1060 IA32_MC9_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
425H 1061 IA32_MC9_STATUS Package
Banks MC9 through MC 10 report MC errors from each
426H 1062 IA32_MC9_ADDR Package channel of the integrated memory controllers.
427H 1063 IA32_MC9_MISC Package
428H 1064 IA32_MC10_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
429H 1065 IA32_MC10_STATUS Package
Banks MC9 through MC 10 report MC errors from each
42AH 1066 IA32_MC10_ADDR Package channel of the integrated memory controllers.
42BH 1067 IA32_MC10_MISC Package
444H 1092 IA32_MC17_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
445H 1093 IA32_MC17_STATUS Package
Bank MC17 reports MC errors from the following pair of
446H 1094 IA32_MC17_ADDR Package CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6,
447H 1095 IA32_MC17_MISC Package CBo9, CBo12, CBo15.
448H 1096 IA32_MC18_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
449H 1097 IA32_MC18_STATUS Package
Bank MC18 reports MC errors from the following pair of
44AH 1098 IA32_MC18_ADDR Package CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
44BH 1099 IA32_MC18_MISC Package CBo10, CBo13, CBo16.
44CH 1100 IA32_MC19_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
44DH 1101 IA32_MC19_STATUS Package
Bank MC19 reports MC errors from the following pair of
44EH 1102 IA32_MC19_ADDR Package CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
44FH 1103 IA32_MC19_MISC Package CBo11, CBo14, CBo17.
See Table 2-20, Table 2-29, Table 2-34, and Table 2-36 for other MSR definitions applicable to processors with CPUID signature
06_56H.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the
factory-set configuration is dependent on features specific to the processor and the platform.
2-270 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
architecture and supports the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-29, Table 2-34, Table 2-36,
and Table 2-38.
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1ACH 428 MSR_TURBO_RATIO_LIMIT3 Package Config Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0.
RW if MSR_PLATFORM_INFO.[28] = 1.
62:0 Package Reserved
63 Package Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration1
specified in MSR_TURBO_RATIO_LIMIT,
MSR_TURBO_RATIO_LIMIT1 and
MSR_TURBO_RATIO_LIMIT2.
If 0, the processor uses factory-set configuration
(Default).
285H 645 IA32_MC5_CTL2 Package See Table 2-2.
286H 646 IA32_MC6_CTL2 Package See Table 2-2.
287H 647 IA32_MC7_CTL2 Package See Table 2-2.
288H 648 IA32_MC8_CTL2 Package See Table 2-2.
289H 649 IA32_MC9_CTL2 Package See Table 2-2.
28AH 650 IA32_MC10_CTL2 Package See Table 2-2.
28BH 651 IA32_MC11_CTL2 Package See Table 2-2.
28CH 652 IA32_MC12_CTL2 Package See Table 2-2.
28DH 653 IA32_MC13_CTL2 Package See Table 2-2.
28EH 654 IA32_MC14_CTL2 Package See Table 2-2.
28FH 655 IA32_MC15_CTL2 Package See Table 2-2.
290H 656 IA32_MC16_CTL2 Package See Table 2-2.
291H 657 IA32_MC17_CTL2 Package See Table 2-2.
292H 658 IA32_MC18_CTL2 Package See Table 2-2.
293H 659 IA32_MC19_CTL2 Package See Table 2-2.
294H 660 IA32_MC20_CTL2 Package See Table 2-2.
295H 661 IA32_MC21_CTL2 Package See Table 2-2.
414H 1044 IA32_MC5_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
415H 1045 IA32_MC5_STATUS Package
Bank MC5 reports MC errors from the Intel QPI 0
416H 1046 IA32_MC5_ADDR Package module.
417H 1047 IA32_MC5_MISC Package
418H 1048 IA32_MC6_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
419H 1049 IA32_MC6_STATUS Package
Bank MC6 reports MC errors from the integrated I/O
41AH 1050 IA32_MC6_ADDR Package module.
41BH 1051 IA32_MC6_MISC Package
Vol. 4 2-271
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
41CH 1052 IA32_MC7_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
41DH 1053 IA32_MC7_STATUS Package
Bank MC7 reports MC errors from the home agent HA
41EH 1054 IA32_MC7_ADDR Package 0.
41FH 1055 IA32_MC7_MISC Package
420H 1056 IA32_MC8_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
421H 1057 IA32_MC8_STATUS Package
Bank MC8 reports MC errors from the home agent HA
422H 1058 IA32_MC8_ADDR Package 1.
423H 1059 IA32_MC8_MISC Package
424H 1060 IA32_MC9_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
425H 1061 IA32_MC9_STATUS Package
Banks MC9 through MC 16 report MC errors from each
426H 1062 IA32_MC9_ADDR Package channel of the integrated memory controllers.
427H 1063 IA32_MC9_MISC Package
428H 1064 IA32_MC10_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
429H 1065 IA32_MC10_STATUS Package
Banks MC9 through MC 16 report MC errors from each
42AH 1066 IA32_MC10_ADDR Package channel of the integrated memory controllers.
42BH 1067 IA32_MC10_MISC Package
42CH 1068 IA32_MC11_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
42DH 1069 IA32_MC11_STATUS Package
Banks MC9 through MC 16 report MC errors from each
42EH 1070 IA32_MC11_ADDR Package channel of the integrated memory controllers.
42FH 1071 IA32_MC11_MISC Package
430H 1072 IA32_MC12_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
431H 1073 IA32_MC12_STATUS Package
Banks MC9 through MC 16 report MC errors from each
432H 1074 IA32_MC12_ADDR Package channel of the integrated memory controllers.
433H 1075 IA32_MC12_MISC Package
434H 1076 IA32_MC13_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
435H 1077 IA32_MC13_STATUS Package
Banks MC9 through MC 16 report MC errors from each
436H 1078 IA32_MC13_ADDR Package channel of the integrated memory controllers.
437H 1079 IA32_MC13_MISC Package
438H 1080 IA32_MC14_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
439H 1081 IA32_MC14_STATUS Package
Banks MC9 through MC 16 report MC errors from each
43AH 1082 IA32_MC14_ADDR Package channel of the integrated memory controllers.
43BH 1083 IA32_MC14_MISC Package
43CH 1084 IA32_MC15_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
43DH 1085 IA32_MC15_STATUS Package
Banks MC9 through MC 16 report MC errors from each
43EH 1086 IA32_MC15_ADDR Package channel of the integrated memory controllers.
43FH 1087 IA32_MC15_MISC Package
2-272 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
440H 1088 IA32_MC16_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
441H 1089 IA32_MC16_STATUS Package
Banks MC9 through MC 16 report MC errors from each
442H 1090 IA32_MC16_ADDR Package channel of the integrated memory controllers.
443H 1091 IA32_MC16_MISC Package
444H 1092 IA32_MC17_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
445H 1093 IA32_MC17_STATUS Package
Bank MC17 reports MC errors from the following pair of
446H 1094 IA32_MC17_ADDR Package CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6,
447H 1095 IA32_MC17_MISC Package CBo9, CBo12, CBo15.
448H 1096 IA32_MC18_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
449H 1097 IA32_MC18_STATUS Package
Bank MC18 reports MC errors from the following pair of
44AH 1098 IA32_MC18_ADDR Package CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
44BH 1099 IA32_MC18_MISC Package CBo10, CBo13, CBo16.
44CH 1100 IA32_MC19_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
44DH 1101 IA32_MC19_STATUS Package
Bank MC19 reports MC errors from the following pair of
44EH 1102 IA32_MC19_ADDR Package CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
44FH 1103 IA32_MC19_MISC Package CBo11, CBo14, CBo17.
450H 1104 IA32_MC20_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
451H 1105 IA32_MC20_STATUS Package
Bank MC20 reports MC errors from the Intel QPI 1
452H 1106 IA32_MC20_ADDR Package module.
453H 1107 IA32_MC20_MISC Package
454H 1108 IA32_MC21_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
455H 1109 IA32_MC21_STATUS Package
Bank MC21 reports MC errors from the Intel QPI 2
456H 1110 IA32_MC21_ADDR Package module.
457H 1111 IA32_MC21_MISC Package
C81H 3201 IA32_L3_QOS_CFG Package Cache Allocation Technology Configuration (R/W)
0 CAT Enable. Set 1 to enable Cache Allocation
Technology.
63:1 Reserved
See Table 2-20, Table 2-21, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with CPUID signature
06_45H.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the
factory-set configuration is dependent on features specific to the processor and the platform.
Vol. 4 2-273
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3AH 58 IA32_FEATURE_CONTROL Thread Control Features in Intel 64 Processor (R/W)
See Table 2-2.
FEH 254 IA32_MTRRCAP Thread MTRR Capability (RO, Architectural)
See Table 2-2
19CH 412 IA32_THERM_STATUS Core Thermal Monitor Status (R/W)
See Table 2-2.
0 Thermal Status (RO)
See Table 2-2.
2-274 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1 Thermal Status Log (R/WC0)
See Table 2-2.
2 PROTCHOT # or FORCEPR# Status (RO)
See Table 2-2.
3 PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4 Critical Temperature Status (RO)
See Table 2-2.
5 Critical Temperature Status Log (R/WC0)
See Table 2-2.
6 Thermal threshold #1 Status (RO)
See Table 2-2.
7 Thermal threshold #1 Log (R/WC0)
See Table 2-2.
8 Thermal Threshold #2 Status (RO)
See Table 2-2.
9 Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10 Power Limitation Status (RO)
See Table 2-2.
11 Power Limitation Log (R/WC0)
See Table 2-2.
12 Current Limit Status (RO)
See Table 2-2.
13 Current Limit Log (R/WC0)
See Table 2-2.
14 Cross Domain Limit Status (RO)
See Table 2-2.
15 Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16 Digital Readout (RO)
See Table 2-2.
26:23 Reserved
30:27 Resolution in Degrees Celsius (RO)
See Table 2-2.
31 Reading Valid (RO)
See Table 2-2.
Vol. 4 2-275
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:32 Reserved
1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1
7:0 Package Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8 Package Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16 Package Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24 Package Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
63:32 Reserved
1C9H 457 MSR_LASTBRANCH_TOS Thread Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-4) that points to the MSR
containing the most recent branch record.
1FCH 508 MSR_POWER_CTL Core Power Control Register
See http://biosbits.org.
0 Reserved
1 Package C1E Enable (R/W)
When set to ‘1’, will enable the CPU to switch to the
Minimum Enhanced Intel SpeedStep Technology
operating point when all execution cores enter MWAIT
(C1).
18:2 Reserved
19 Disable Energy Efficiency Optimization (R/W)
Setting this bit disables the P-States energy efficiency
optimization. Default value is 0. Disable/enable the
energy efficiency optimization in P-State legacy mode
(when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an
effect only in the turbo range or into PERF_MIN_CTL
value if it is not zero set. In HWP mode
(IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect
between the OS desired or OS maximize to the OS
minimize performance setting.
20 Disable Race to Halt Optimization (R/W)
Setting this bit disables the Race to Halt optimization
and avoids this optimization limitation to execute
below the most efficient frequency ratio. Default value
is 0 for processors that support Race to Halt
optimization.
2-276 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:21 Reserved
300H 768 MSR_SGXOWNEREPOCH0 Package Lower 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if
CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread
in the package.
63:0 Lower 64 bits of an 128-bit external entropy value for
key derivation of an enclave.
301H 768 MSR_SGXOWNEREPOCH1 Package Upper 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if
CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread
in the package.
63:0 Upper 64 bits of an 128-bit external entropy value for
key derivation of an enclave.
38EH 910 IA32_PERF_GLOBAL_STATUS See Table 2-2. See Section 18.2.4, “Architectural
Performance Monitoring Version 4.”
0 Thread Ovf_PMC0
1 Thread Ovf_PMC1
2 Thread Ovf_PMC2
3 Thread Ovf_PMC3
4 Thread Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
5 Thread Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
6 Thread Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
7 Thread Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
31:8 Reserved
32 Thread Ovf_FixedCtr0
33 Thread Ovf_FixedCtr1
34 Thread Ovf_FixedCtr2
54:35 Reserved
55 Thread Trace_ToPA_PMI
57:56 Reserved
58 Thread LBR_Frz
59 Thread CTR_Frz
60 Thread ASCI
61 Thread Ovf_Uncore
62 Thread Ovf_BufDSSAVE
63 Thread CondChgd
Vol. 4 2-277
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
390H 912 IA32_PERF_GLOBAL_STATUS_RESET See Table 2-2. See Section 18.2.4, “Architectural
Performance Monitoring Version 4.”
0 Thread Set 1 to clear Ovf_PMC0.
1 Thread Set 1 to clear Ovf_PMC1.
2 Thread Set 1 to clear Ovf_PMC2.
3 Thread Set 1 to clear Ovf_PMC3.
4 Thread Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
5 Thread Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
6 Thread Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
7 Thread Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
31:8 Reserved
32 Thread Set 1 to clear Ovf_FixedCtr0.
33 Thread Set 1 to clear Ovf_FixedCtr1.
34 Thread Set 1 to clear Ovf_FixedCtr2.
54:35 Reserved
55 Thread Set 1 to clear Trace_ToPA_PMI.
57:56 Reserved
58 Thread Set 1 to clear LBR_Frz.
59 Thread Set 1 to clear CTR_Frz.
60 Thread Set 1 to clear ASCI.
61 Thread Set 1 to clear Ovf_Uncore.
62 Thread Set 1 to clear Ovf_BufDSSAVE.
63 Thread Set 1 to clear CondChgd.
391H 913 IA32_PERF_GLOBAL_STATUS_SET See Table 2-2. See Section 18.2.4, “Architectural
Performance Monitoring Version 4.”
0 Thread Set 1 to cause Ovf_PMC0 = 1.
1 Thread Set 1 to cause Ovf_PMC1 = 1.
2 Thread Set 1 to cause Ovf_PMC2 = 1.
3 Thread Set 1 to cause Ovf_PMC3 = 1.
4 Thread Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] >
4).
5 Thread Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] >
5).
6 Thread Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] >
6).
2-278 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
7 Thread Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] >
7).
31:8 Reserved
32 Thread Set 1 to cause Ovf_FixedCtr0 = 1.
33 Thread Set 1 to cause Ovf_FixedCtr1 = 1.
34 Thread Set 1 to cause Ovf_FixedCtr2 = 1.
54:35 Reserved
55 Thread Set 1 to cause Trace_ToPA_PMI = 1.
57:56 Reserved
58 Thread Set 1 to cause LBR_Frz = 1.
59 Thread Set 1 to cause CTR_Frz = 1.
60 Thread Set 1 to cause ASCI = 1.
61 Thread Set 1 to cause Ovf_Uncore.
62 Thread Set 1 to cause Ovf_BufDSSAVE.
63 Reserved
392H 913 IA32_PERF_GLOBAL_INUSE Thread See Table 2-2.
3F7H 1015 MSR_PEBS_FRONTEND Thread FrontEnd Precise Event Condition Select (R/W)
2:0 Event Code Select
3 Reserved
4 Event Code Select High
7:5 Reserved
19:8 IDQ_Bubble_Length Specifier
22:20 IDQ_Bubble_Width Specifier
63:23 Reserved
500H 1280 IA32_SGX_SVN_STATUS Thread Status and SVN Threshold of SGX Support for ACM (RO)
0 Lock
See Section 37.11.3, “Interactions with Authenticated
Code Modules (ACMs)”.
15:1 Reserved
23:16 SGX_SVN_SINIT
See Section 37.11.3, “Interactions with Authenticated
Code Modules (ACMs)”.
63:24 Reserved
560H 1376 IA32_RTIT_OUTPUT_BASE Thread Trace Output Base Register (R/W)
See Table 2-2.
Vol. 4 2-279
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
561H 1377 IA32_RTIT_OUTPUT_MASK_PTRS Thread Trace Output Mask Pointers Register (R/W)
See Table 2-2.
570H 1392 IA32_RTIT_CTL Thread Trace Control Register (R/W)
0 TraceEn
1 CYCEn
2 OS
3 User
6:4 Reserved, must be zero.
7 CR3 filter
8 ToPA
Writing 0 will #GP if also setting TraceEn.
9 MTCEn
10 TSCEn
11 DisRETC
12 Reserved, must be zero.
13 BranchEn
17:14 MTCFreq
18 Reserved, must be zero.
22:19 CYCThresh
23 Reserved, must be zero.
27:24 PSBFreq
31:28 Reserved, must be zero.
35:32 ADDR0_CFG
39:36 ADDR1_CFG
63:40 Reserved, must be zero.
571H 1393 IA32_RTIT_STATUS Thread Tracing Status Register (R/W)
0 FilterEn, writes ignored.
1 ContexEn, writes ignored.
2 TriggerEn, writes ignored.
3 Reserved
4 Error (R/W)
5 Stopped
31:6 Reserved, must be zero.
48:32 PacketByteCnt
63:49 Reserved, must be zero.
2-280 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
572H 1394 IA32_RTIT_CR3_MATCH Thread Trace Filter CR3 Match Register (R/W)
4:0 Reserved
63:5 CR3[63:5] value to match
580H 1408 IA32_RTIT_ADDR0_A Thread Region 0 Start Address (R/W)
63:0 See Table 2-2.
581H 1409 IA32_RTIT_ADDR0_B Thread Region 0 End Address (R/W)
63:0 See Table 2-2.
582H 1410 IA32_RTIT_ADDR1_A Thread Region 1 Start Address (R/W)
63:0 See Table 2-2.
583H 1411 IA32_RTIT_ADDR1_B Thread Region 1 End Address (R/W)
63:0 See Table 2-2.
639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
64DH 1613 MSR_PLATFORM_ENERGY_COUNTER Platform* Platform Energy Counter (R/O)
This MSR is valid only if both platform vendor hardware
implementation and BIOS enablement support it. This
MSR will read 0 if not valid.
31:0 Total energy consumed by all devices in the platform
that receive power from integrated power delivery
mechanism, included platform devices are processor
cores, SOC, memory, add-on or peripheral devices that
get powered directly from the platform power delivery
means. The energy units are specified in the
MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
63:32 Reserved
64EH 1614 MSR_PPERF Thread Productive Performance Count (R/O)
63:0 Hardware’s view of workload scalability. See Section
14.4.5.1.
64FH 1615 MSR_CORE_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in Processor Cores
(R/W)
(Frequency refers to processor core frequency.)
0 PROCHOT Status (R0)
When set, frequency is reduced below the operating
system request due to assertion of external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal event.
3:2 Reserved
Vol. 4 2-281
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
4 Residency State Regulation Status (R0)
When set, frequency is reduced below the operating
system request due to residency state regulation limit.
5 Running Average Thermal Limit Status (R0)
When set, frequency is reduced below the operating
system request due to Running Average Thermal Limit
(RATL).
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal alert from a processor
Voltage Regulator (VR).
7 VR Therm Design Current Status (R0)
When set, frequency is reduced below the operating
system request due to VR thermal design current limit.
8 Other Status (R0)
When set, frequency is reduced below the operating
system request due to electrical or other constraints.
9 Reserved
10 Package/Platform-Level Power Limiting PL1 Status
(R0)
When set, frequency is reduced below the operating
system request due to package/platform-level power
limiting PL1.
11 Package/Platform-Level PL2 Power Limiting Status
(R0)
When set, frequency is reduced below the operating
system request due to package/platform-level power
limiting PL2/PL3.
12 Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating
system request due to multi-core turbo limits.
13 Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating
system request due to Turbo transition attenuation.
This prevents performance degradation due to
frequent operating ratio changes.
15:14 Reserved
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
2-282 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
17 Thermal Log
When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
19:18 Reserved.
20 Residency State Regulation Log
When set, indicates that the Residency State
Regulation Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software
writing 0.
21 Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
23 VR Thermal Design Current Log
When set, indicates that the VR TDC Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
24 Other Log
When set, indicates that the Other Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
25 Reserved
Vol. 4 2-283
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
27 Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package or Platform Level
PL2/PL3 Power Limiting Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
28 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition
Attenuation Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software
writing 0.
63:30 Reserved
652H 1618 MSR_PKG_HDC_CONFIG Package HDC Configuration (R/W)
2:0 PKG_Cx_Monitor
Configures Package Cx state threshold for
MSR_PKG_HDC_DEEP_RESIDENCY.
63: 3 Reserved
653H 1619 MSR_CORE_HDC_RESIDENCY Core Core HDC Idle Residency (R/O)
63:0 Core_Cx_Duty_Cycle_Cnt
655H 1621 MSR_PKG_HDC_SHALLOW_RESIDENCY Package Accumulate the cycles the package was in C2 state and
at least one logical processor was in forced idle (R/O)
63:0 Pkg_C2_Duty_Cycle_Cnt
656H 1622 MSR_PKG_HDC_DEEP_RESIDENCY Package Package Cx HDC Idle Residency (R/O)
63:0 Pkg_Cx_Duty_Cycle_Cnt
658H 1624 MSR_WEIGHTED_CORE_C0 Package Core-count Weighted C0 Residency (R/O)
63:0 Increment at the same rate as the TSC. The increment
each cycle is weighted by the number of processor
cores in the package that reside in C0. If N cores are
simultaneously in C0, then each cycle the counter
increments by N.
659H 1625 MSR_ANY_CORE_C0 Package Any Core C0 Residency (R/O)
63:0 Increment at the same rate as the TSC. The increment
each cycle is one if any processor core in the package is
in C0.
2-284 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
65AH 1626 MSR_ANY_GFXE_C0 Package Any Graphics Engine C0 Residency (R/O)
63:0 Increment at the same rate as the TSC. The increment
each cycle is one if any processor graphic device’s
compute engines are in C0.
65BH 1627 MSR_CORE_GFXE_OVERLAP_C0 Package Core and Graphics Engine Overlapped C0 Residency
(R/O)
63:0 Increment at the same rate as the TSC. The increment
each cycle is one if at least one compute engine of the
processor graphics is in C0 and at least one processor
core in the package is also in C0.
65CH 1628 MSR_PLATFORM_POWER_LIMIT Platform* Platform Power Limit Control (R/W-L)
Allows platform BIOS to limit power consumption of the
platform devices to the specified values. The Long
Duration power consumption is specified via
Platform_Power_Limit_1 and
Platform_Power_Limit_1_Time. The Short Duration
power consumption limit is specified via the
Platform_Power_Limit_2 with duration chosen by the
processor.
The processor implements an exponential-weighted
algorithm in the placement of the time windows.
14:0 Platform Power Limit #1
Average Power limit value which the platform must not
exceed over a time window as specified by
Power_Limit_1_TIME field.
The default value is the Thermal Design Power (TDP)
and varies with product skus. The unit is specified in
MSR_RAPLPOWER_UNIT.
15 Enable Platform Power Limit #1
When set, enables the processor to apply control policy
such that the platform power does not exceed
Platform Power limit #1 over the time window
specified by Power Limit #1 Time Window.
16 Platform Clamping Limitation #1
When set, allows the processor to go below the OS
requested P states in order to maintain the power
below specified Platform Power Limit #1 value.
This bit is writeable only when CPUID (EAX=6):EAX[4]
is set.
Vol. 4 2-285
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
23:17 Time Window for Platform Power Limit #1
Specifies the duration of the time window over which
Platform Power Limit 1 value should be maintained for
sustained long duration. This field is made up of two
numbers from the following equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17]
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, The unit is specified in
MSR_RAPLPOWER_UNIT[Time Unit].
31:24 Reserved
46:32 Platform Power Limit #2
Average Power limit value which the platform must not
exceed over the Short Duration time window chosen
by the processor.
The recommended default value is 1.25 times the Long
Duration Power Limit (i.e., Platform Power Limit # 1).
47 Enable Platform Power Limit #2
When set, enables the processor to apply control policy
such that the platform power does not exceed
Platform Power limit #2 over the Short Duration time
window.
48 Platform Clamping Limitation #2
When set, allows the processor to go below the OS
requested P states in order to maintain the power
below specified Platform Power Limit #2 value.
62:49 Reserved
63 Lock. Setting this bit will lock all other bits of this MSR
until system RESET.
690H 1680 MSR_LASTBRANCH_16_FROM_IP Thread Last Branch Record 16 From IP (R/W)
One of 32 triplets of last branch record registers on the
last branch record stack. This part of the stack contains
pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 17.12.
691H 1681 MSR_LASTBRANCH_17_FROM_IP Thread Last Branch Record 17 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
692H 1682 MSR_LASTBRANCH_18_FROM_IP Thread Last Branch Record 18 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
2-286 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
693H 1683 MSR_LASTBRANCH_19_FROM_IP Thread Last Branch Record 19From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
694H 1684 MSR_LASTBRANCH_20_FROM_IP Thread Last Branch Record 20 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
695H 1685 MSR_LASTBRANCH_21_FROM_IP Thread Last Branch Record 21 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
696H 1686 MSR_LASTBRANCH_22_FROM_IP Thread Last Branch Record 22 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
697H 1687 MSR_LASTBRANCH_23_FROM_IP Thread Last Branch Record 23 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
698H 1688 MSR_LASTBRANCH_24_FROM_IP Thread Last Branch Record 24 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
699H 1689 MSR_LASTBRANCH_25_FROM_IP Thread Last Branch Record 25 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69AH 1690 MSR_LASTBRANCH_26_FROM_IP Thread Last Branch Record 26 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69BH 1691 MSR_LASTBRANCH_27_FROM_IP Thread Last Branch Record 27 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69CH 1692 MSR_LASTBRANCH_28_FROM_IP Thread Last Branch Record 28 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69DH 1693 MSR_LASTBRANCH_29_FROM_IP Thread Last Branch Record 29 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69EH 1694 MSR_LASTBRANCH_30_FROM_IP Thread Last Branch Record 30 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69FH 1695 MSR_LASTBRANCH_31_FROM_IP Thread Last Branch Record 31 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
6B0H 1712 MSR_GRAPHICS_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in the Processor
Graphics (R/W)
(Frequency refers to processor graphics frequency.)
0 PROCHOT Status (R0)
When set, frequency is reduced due to assertion of
external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced due to a thermal event.
4:2 Reserved.
5 Running Average Thermal Limit Status (R0)
When set, frequency is reduced due to running average
thermal limit.
Vol. 4 2-287
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
6 VR Therm Alert Status (R0)
When set, frequency is reduced due to a thermal alert
from a processor Voltage Regulator.
7 VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
8 Other Status (R0)
When set, frequency is reduced due to electrical or
other constraints.
9 Reserved
10 Package/Platform-Level Power Limiting PL1 Status
(R0)
When set, frequency is reduced due to
package/platform-level power limiting PL1.
11 Package/Platform-Level PL2 Power Limiting Status
(R0)
When set, frequency is reduced due to
package/platform-level power limiting PL2/PL3.
12 Inefficient Operation Status (R0)
When set, processor graphics frequency is operating
below target frequency.
15:13 Reserved
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
20:18 Reserved.
21 Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
2-288 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
23 VR Thermal Design Current Log
When set, indicates that the VR Therm Alert Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
24 Other Log
When set, indicates that the OTHER Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
25 Reserved
26 Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package/Platform Level
PL1 Power Limiting Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
27 Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package/Platform Level
PL2 Power Limiting Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
28 Inefficient Operation Log
When set, indicates that the Inefficient Operation
Status bit has asserted since the log bit was last
cleared.
This log bit will remain set until cleared by software
writing 0.
63:29 Reserved
6B1H 1713 MSR_RING_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in the Ring Interconnect
(R/W)
(Frequency refers to ring interconnect in the uncore.)
0 PROCHOT Status (R0)
When set, frequency is reduced due to assertion of
external PROCHOT.
Vol. 4 2-289
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1 Thermal Status (R0)
When set, frequency is reduced due to a thermal event.
4:2 Reserved
5 Running Average Thermal Limit Status (R0)
When set, frequency is reduced due to running average
thermal limit.
6 VR Therm Alert Status (R0)
When set, frequency is reduced due to a thermal alert
from a processor Voltage Regulator.
7 VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
8 Other Status (R0)
When set, frequency is reduced due to electrical or
other constraints.
9 Reserved
10 Package/Platform-Level Power Limiting PL1 Status
(R0)
When set, frequency is reduced due to
package/Platform-level power limiting PL1.
11 Package/Platform-Level PL2 Power Limiting Status
(R0)
When set, frequency is reduced due to
package/Platform-level power limiting PL2/PL3.
15:12 Reserved
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
20:18 Reserved
21 Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
2-290 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
23 VR Thermal Design Current Log
When set, indicates that the VR Therm Alert Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
24 Other Log
When set, indicates that the OTHER Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
25 Reserved
26 Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package/Platform Level
PL1 Power Limiting Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
27 Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package/Platform Level
PL2 Power Limiting Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
63:28 Reserved
6D0H 1744 MSR_LASTBRANCH_16_TO_IP Thread Last Branch Record 16 To IP (R/W)
One of 32 triplets of last branch record registers on the
last branch record stack. This part of the stack contains
pointers to the destination instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 17.12.
6D1H 1745 MSR_LASTBRANCH_17_TO_IP Thread Last Branch Record 17 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D2H 1746 MSR_LASTBRANCH_18_TO_IP Thread Last Branch Record 18 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D3H 1747 MSR_LASTBRANCH_19_TO_IP Thread Last Branch Record 19To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Vol. 4 2-291
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
6D4H 1748 MSR_LASTBRANCH_20_TO_IP Thread Last Branch Record 20 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D5H 1749 MSR_LASTBRANCH_21_TO_IP Thread Last Branch Record 21 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D6H 1750 MSR_LASTBRANCH_22_TO_IP Thread Last Branch Record 22 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D7H 1751 MSR_LASTBRANCH_23_TO_IP Thread Last Branch Record 23 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D8H 1752 MSR_LASTBRANCH_24_TO_IP Thread Last Branch Record 24 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D9H 1753 MSR_LASTBRANCH_25_TO_IP Thread Last Branch Record 25 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DAH 1754 MSR_LASTBRANCH_26_TO_IP Thread Last Branch Record 26 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DBH 1755 MSR_LASTBRANCH_27_TO_IP Thread Last Branch Record 27 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DCH 1756 MSR_LASTBRANCH_28_TO_IP Thread Last Branch Record 28 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DDH 1757 MSR_LASTBRANCH_29_TO_IP Thread Last Branch Record 29 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DEH 1758 MSR_LASTBRANCH_30_TO_IP Thread Last Branch Record 30 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DFH 1759 MSR_LASTBRANCH_31_TO_IP Thread Last Branch Record 31 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
770H 1904 IA32_PM_ENABLE Package See Section 14.4.2, “Enabling HWP”.
771H 1905 IA32_HWP_CAPABILITIES Thread See Section 14.4.3, “HWP Performance Range and
Dynamic Capabilities”.
772H 1906 IA32_HWP_REQUEST_PKG Package See Section 14.4.4, “Managing HWP”.
773H 1907 IA32_HWP_INTERRUPT Thread See Section 14.4.6, “HWP Notifications”.
774H 1908 IA32_HWP_REQUEST Thread See Section 14.4.4, “Managing HWP”.
7:0 Minimum Performance (R/W)
15:8 Maximum Performance (R/W)
23:16 Desired Performance (R/W)
31:24 Energy/Performance Preference (R/W)
41:32 Activity Window (R/W)
42 Package Control (R/W)
2-292 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:43 Reserved
777H 1911 IA32_HWP_STATUS Thread See Section 14.4.5, “HWP Feedback”.
D90H 3472 IA32_BNDCFGS Thread See Table 2-2.
DA0H 3488 IA32_XSS Thread See Table 2-2.
DB0H 3504 IA32_PKG_HDC_CTL Package See Section 14.5.2, “Package level Enabling HDC”.
DB1H 3505 IA32_PM_CTL1 Thread See Section 14.5.3, “Logical-Processor Level HDC
Control”.
DB2H 3506 IA32_THREAD_STALL Thread See Section 14.5.4.1, “IA32_THREAD_STALL”.
DC0H 3520 MSR_LBR_INFO_0 Thread Last Branch Record 0 Additional Information (R/W)
One of 32 triplet of last branch record registers on the
last branch record stack. This part of the stack contains
flag, TSX-related and elapsed cycle information. See
also:
• Last Branch Record Stack TOS at 1C9H.
• Section 17.9.1, “LBR Stack.”
DC1H 3521 MSR_LBR_INFO_1 Thread Last Branch Record 1 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC2H 3522 MSR_LBR_INFO_2 Thread Last Branch Record 2 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC3H 3523 MSR_LBR_INFO_3 Thread Last Branch Record 3 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC4H 3524 MSR_LBR_INFO_4 Thread Last Branch Record 4 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC5H 3525 MSR_LBR_INFO_5 Thread Last Branch Record 5 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC6H 3526 MSR_LBR_INFO_6 Thread Last Branch Record 6 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC7H 3527 MSR_LBR_INFO_7 Thread Last Branch Record 7 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC8H 3528 MSR_LBR_INFO_8 Thread Last Branch Record 8 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DC9H 3529 MSR_LBR_INFO_9 Thread Last Branch Record 9 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCAH 3530 MSR_LBR_INFO_10 Thread Last Branch Record 10 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCBH 3531 MSR_LBR_INFO_11 Thread Last Branch Record 11 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Vol. 4 2-293
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
DCCH 3532 MSR_LBR_INFO_12 Thread Last Branch Record 12 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCDH 3533 MSR_LBR_INFO_13 Thread Last Branch Record 13 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCEH 3534 MSR_LBR_INFO_14 Thread Last Branch Record 14 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DCFH 3535 MSR_LBR_INFO_15 Thread Last Branch Record 15 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD0H 3536 MSR_LBR_INFO_16 Thread Last Branch Record 16 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD1H 3537 MSR_LBR_INFO_17 Thread Last Branch Record 17 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD2H 3538 MSR_LBR_INFO_18 Thread Last Branch Record 18 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD3H 3539 MSR_LBR_INFO_19 Thread Last Branch Record 19 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD4H 3520 MSR_LBR_INFO_20 Thread Last Branch Record 20 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD5H 3521 MSR_LBR_INFO_21 Thread Last Branch Record 21 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD6H 3522 MSR_LBR_INFO_22 Thread Last Branch Record 22 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD7H 3523 MSR_LBR_INFO_23 Thread Last Branch Record 23 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD8H 3524 MSR_LBR_INFO_24 Thread Last Branch Record 24 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DD9H 3525 MSR_LBR_INFO_25 Thread Last Branch Record 25 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDAH 3526 MSR_LBR_INFO_26 Thread Last Branch Record 26 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDBH 3527 MSR_LBR_INFO_27 Thread Last Branch Record 27 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDCH 3528 MSR_LBR_INFO_28 Thread Last Branch Record 28 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDDH 3529 MSR_LBR_INFO_29 Thread Last Branch Record 29 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
2-294 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th
Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 2nd and 3rd
Generation Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E
Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
DDEH 3530 MSR_LBR_INFO_30 Thread Last Branch Record 30 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
DDFH 3531 MSR_LBR_INFO_31 Thread Last Branch Record 31 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Table 2-40 lists the MSRs of uncore PMU for Intel processors with CPUID DisplayFamily_DisplayModel signatures of
06_4EH, 06_5EH, 06_8EH, 06_9EH, and 06_66H.
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™
Processors, and Future Intel® Core™ Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
394H 916 MSR_UNC_PERF_FIXED_CTRL Package Uncore Fixed Counter Control (R/W)
19:0 Reserved
20 Enable overflow propagation.
21 Reserved
22 Enable counting.
63:23 Reserved
395H 917 MSR_UNC_PERF_FIXED_CTR Package Uncore Fixed Counter
43:0 Current count.
63:44 Reserved
396H 918 MSR_UNC_CBO_CONFIG Package Uncore C-Box Configuration Information (R/O)
3:0 Specifies the number of C-Box units with
programmable counters (including processor cores
and processor graphics).
63:4 Reserved
3B0H 946 MSR_UNC_ARB_PERFCTR0 Package Uncore Arb Unit, Performance Counter 0
3B1H 947 MSR_UNC_ARB_PERFCTR1 Package Uncore Arb Unit, Performance Counter 1
3B2H 944 MSR_UNC_ARB_PERFEVTSEL0 Package Uncore Arb Unit, Counter 0 Event Select MSR
3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb Unit, Counter 1 Event Select MSR
700H 1792 MSR_UNC_CBO_0_PERFEVTSEL0 Package Uncore C-Box 0, Counter 0 Event Select MSR
701H 1793 MSR_UNC_CBO_0_PERFEVTSEL1 Package Uncore C-Box 0, Counter 1 Event Select MSR
706H 1798 MSR_UNC_CBO_0_PERFCTR0 Package Uncore C-Box 0, Performance Counter 0
707H 1799 MSR_UNC_CBO_0_PERFCTR1 Package Uncore C-Box 0, Performance Counter 1
710H 1808 MSR_UNC_CBO_1_PERFEVTSEL0 Package Uncore C-Box 1, Counter 0 Event Select MSR
711H 1809 MSR_UNC_CBO_1_PERFEVTSEL1 Package Uncore C-Box 1, Counter 1 Event Select MSR
Vol. 4 2-295
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™
Processors, and Future Intel® Core™ Processors
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
716H 1814 MSR_UNC_CBO_1_PERFCTR0 Package Uncore C-Box 1, Performance Counter 0
717H 1815 MSR_UNC_CBO_1_PERFCTR1 Package Uncore C-Box 1, Performance Counter 1
720H 1824 MSR_UNC_CBO_2_PERFEVTSEL0 Package Uncore C-Box 2, Counter 0 Event Select MSR
721H 1825 MSR_UNC_CBO_2_PERFEVTSEL1 Package Uncore C-Box 2, Counter 1 Event Select MSR
726H 1830 MSR_UNC_CBO_2_PERFCTR0 Package Uncore C-Box 2, Performance Counter 0
727H 1831 MSR_UNC_CBO_2_PERFCTR1 Package Uncore C-Box 2, Performance Counter 1
730H 1840 MSR_UNC_CBO_3_PERFEVTSEL0 Package Uncore C-Box 3, Counter 0 Event Select MSR
731H 1841 MSR_UNC_CBO_3_PERFEVTSEL1 Package Uncore C-Box 3, Counter 1 Event Select MSR
736H 1846 MSR_UNC_CBO_3_PERFCTR0 Package Uncore C-Box 3, Performance Counter 0
737H 1847 MSR_UNC_CBO_3_PERFCTR1 Package Uncore C-Box 3, Performance Counter 1
E01H 3585 MSR_UNC_PERF_GLOBAL_CTRL Package Uncore PMU Global Control
0 Slice 0 select.
1 Slice 1 select.
2 Slice 2 select.
3 Slice 3 select.
4 Slice 4select.
18:5 Reserved
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved
E02H 3586 MSR_UNC_PERF_GLOBAL_STATUS Package Uncore PMU Main Status
0 Fixed counter overflowed.
1 An ARB counter overflowed.
2 Reserved
3 A CBox counter overflowed (on any slice).
63:4 Reserved
2-296 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.1 MSRs Specific to 7th Generation and 8th Generation Intel® Core™ Processors based on
Kaby Lake Microarchitecture and Coffee Lake Microarchitecture
Table 2-42 lists additional MSRs for 7th generation and 8th generation Intel Core processors with a CPUID
DisplayFamily_DisplayModel signatures of 06_8EH and 06_9EH. For an MSR listed in Table 2-42 that also appears
in the model-specific tables of prior generations, Table 2-42 supersedes prior generation tables.
Table 2-41. Additional MSRs Supported by 7th Generation and 8th Generation Intel® Core™ Processors
Based on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
80H 128 MSR_TRACE_HUB_STH_ACPIBAR_BASE Package NPK Address Used by AET Messages (R/W)
0 Lock Bit
If set, this MSR cannot be re-written anymore. Lock bit
has to be set in order for the AET packets to be
directed to NPK MMIO.
17:1 Reserved
63:18 ACPIBAR_BASE_ADDRESS
AET target address in NPK MMIO space.
1F4H 500 MSR_PRMRR_PHYS_BASE Core Processor Reserved Memory Range Register -
Physical Base Control Register (R/W)
2:0 MemType
PRMRR BASE MemType.
11:3 Reserved
45:12 Base
PRMRR Base Address.
63:46 Reserved
1F5H 501 MSR_PRMRR_PHYS_MASK Core Processor Reserved Memory Range Register -
Physical Mask Control Register (R/W)
9:0 Reserved
10 Lock
Lock bit for the PRMRR.
11 VLD
Enable bit for the PRMRR.
45:12 Mask
PRMRR MASK bits.
63:46 Reserved
1FBH 507 MSR_PRMRR_VALID_CONFIG Core Valid PRMRR Configurations (R/W)
0 1M supported MEE size.
4:1 Reserved
5 32M supported MEE size.
6 64M supported MEE size.
7 128M supported MEE size.
31:8 Reserved
Vol. 4 2-297
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-41. Additional MSRs Supported by 7th Generation and 8th Generation Intel® Core™ Processors
Based on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
2F4H 756 MSR_UNCORE_PRMRR_PHYS_BASE Package (R/W)
The PRMRR range is used to protect the processor
reserved memory from unauthorized reads and
writes. Any IO access to this range is aborted. This
register controls the location of the PRMRR range by
indicating its starting address. It functions in tandem
with the PRMRR mask register.
11:0 Reserved
PAWIDTH-1:12 Range Base
This field corresponds to bits PAWIDTH-1:12 of the
base address memory range which is allocated to
PRMRR memory.
63:PAWIDTH Reserved
2F5H 757 MSR_UNCORE_PRMRR_PHYS_MASK Package (R/W)
This register controls the size of the PRMRR range by
indicating which address bits must match the PRMRR
base register value.
9:0 Reserved
10 Lock
Setting this bit locks all writeable settings in this
register, including itself.
11 Range_En
Indicates whether the PRMRR range is enabled and
valid.
38:12 Range_Mask
This field indicates which address bits must match
PRMRR base in order to qualify as an PRMRR access.
63:39 Reserved
620H 1568 MSR_RING_RATIO_LIMIT Package Ring Ratio Limit (R/W)
This register provides Min/Max Ratio Limits for the
LLC and Ring.
6:0 MAX_Ratio
This field is used to limit the max ratio of the
LLC/Ring.
7 Reserved
14:8 MIN_Ratio
Writing to this field controls the minimum possible
ratio of the LLC/Ring.
63:15 Reserved
2-298 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-42. Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3AH 58 IA32_FEATURE_CONTROL Thread Control Features in Intel 64 Processor (R/W)
See Table 2-2.
0 Lock (R/WL)
1 Enable VMX Inside SMX Operation (R/WL)
2 Enable VMX Outside SMX Operation (R/WL)
14:8 SENTER Local Functions Enables (R/WL)
15 SENTER Global Functions Enable (R/WL)
17 SGX Launch Control Enable (R/WL)
This bit must be set to enable runtime reconfiguration
of SGX Launch Control via IA32_SGXLEPUBKEYHASHn
MSR.
Available only if CPUID.(EAX=07H, ECX=0H): ECX[30]
= 1.
18 SGX Global Functions Enable (R/WL)
63:21 Reserved
350H 848 MSR_BR_DETECT_CTRL Branch Monitoring Global Control (R/W)
0 EnMonitoring
Global enable for branch monitoring.
1 EnExcept
Enable branch monitoring event signaling on threshold
trip.
The branch monitoring event handler is signaled via
the existing PMI signaling mechanism as programmed
from the corresponding local APIC LVT entry.
2 EnLBRFrz
Enable LBR freeze on threshold trip. This will cause
the LBR frozen bit 58 to be set in
IA32_PERF_GLOBAL_STATUS when a triggering
condition occurs and this bit is enabled.
3 DisableInGuest
When set to ‘1’, branch monitoring, event triggering
and LBR freeze actions are disabled when operating
at VMX non-root operation.
7:4 Reserved
Vol. 4 2-299
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-42. Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
17:8 WindowSize
Window size defined by WindowCntSel. Values 0 –
1023 are supported.
Once the Window counter reaches the WindowSize
count both the Window Counter and all Branch
Monitoring Counters are cleared.
23:18 Reserved
25:24 WindowCntSel
Window event count select:
‘00 = Instructions retired.
‘01 = Branch instructions retired
‘10 = Return instructions retired.
‘11 = Indirect branch instructions retired.
26 CntAndMode
When set to ‘1’, the overall branch monitoring event
triggering condition is true only if all enabled counters’
threshold conditions are true.
When ‘0’, the threshold tripping condition is true if any
enabled counters’ threshold is true.
63:27 Reserved
351H 849 MSR_BR_DETECT_STATUS Branch Monitoring Global Status (R/W)
0 Branch Monitoring Event Signaled
When set to '1', Branch Monitoring event signaling is
blocked until this bit is cleared by software.
1 LBRsValid
This status bit is set to ‘1’ if the LBR state is
considered valid for sampling by branch monitoring
software.
7:2 Reserved
8 CntrHit0
Branch monitoring counter #0 threshold hit. This
status bit is sticky and once set requires clearing by
software. Counter operation continues independent
of the state of the bit.
9 CntrHit1
Branch monitoring counter #1 threshold hit. This
status bit is sticky and once set requires clearing by
software. Counter operation continues independent
of the state of the bit.
15:10 Reserved
Reserved for additional branch monitoring counters
threshold hit status.
2-300 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-42. Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
25:16 CountWindow
The current value of the window counter. The count
value is frozen on a valid branch monitoring triggering
condition. This is a 10-bit unsigned value.
31:26 Reserved
Reserved for future extension of CountWindow.
39:32 Count0
The current value of counter 0 updated after each
occurrence of the event being counted. The count
value is frozen on a valid branch monitoring triggering
condition (in which case CntrHit0 will also be set). This
is an 8-bit signed value (2’s complement).
Heuristic events which only increment will saturate
and freeze at maximum value 0xFF (256).
RET-CALL event counter saturate at maximum value
0x7F (+127) and minimum value 0x80 (-128).
47:40 Count1
The current value of counter 1 updated after each
occurrence of the event being counted. The count
value is frozen on a valid branch monitoring triggering
condition (in which case CntrHit1 will also be set). This
is an 8-bit signed value (2’s complement).
Heuristic events which only increment will saturate
and freeze at maximum value 0xFF (256).
RET-CALL event counter saturate at maximum value
0x7F (+127) and minimum value 0x80 (-128).
63:48 Reserved
354H 852 MSR_BR_DETECT_COUNTER_CONFIG_i Branch Monitoring Detect Counter Configuration (R/W)
- -
355H 853
0 CntrEn
Enable counter.
7:1 CntrEvSel
Event select (other values #GP)
‘0000000 = RETs.
‘0000001 = RET-CALL bias.
‘0000010 = RET mispredicts.
‘0000011 = Branch (all) mispredicts.
‘0000100 = Indirect branch mispredicts.
‘0000101 = Far branch instructions.
Vol. 4 2-301
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-42. Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
14:8 CntrThreshold
Threshold (an unsigned value of 0 to 127 supported).
The value 0 of counter threshold will result in event
signaled after every instruction. #GP if threshold is <
2.
15 MispredEventCnt
Mispredict events counting behavior:
‘0 = Mispredict events are counted in a window.
‘1 = Mispredict events are counted based on a
consecutive occurrence. CntrThreshold is treated as #
of consecutive mispredicts. This control bit only
applies to events specified by CntrEvSel that involve a
prediction (0000010, 0000011, 0000100). Setting
this bit for other events is ignored.
63:16 Reserved
3F8H 1016 MSR_PKG_C3_RESIDENCY Package Package C3 Residency Counter (R/O)
63:0 Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
620H 1568 MSR_RING_RATIO_LIMIT Package Ring Ratio Limit (R/W)
This register provides Min/Max Ratio Limits for the
LLC and Ring.
6:0 MAX_Ratio
This field is used to limit the max ratio of the
LLC/Ring.
7 Reserved
14:8 MIN_Ratio
Writing to this field controls the minimum possible
ratio of the LLC/Ring.
63:15 Reserved
660H 1632 MSR_CORE_C1_RESIDENCY Core Core C1 Residency Counter (R/O)
63:0 Value since last reset for the Core C1 residency.
Counter rate is the Max Non-Turbo frequency (same
as TSC). This counter counts in case both of the core's
threads are in an idle state and at least one of the
core's thread residency is in a C1 state or in one of its
sub states. The counter is updated only after a core C
state exit. Note: Always reads 0 if core C1 is
unsupported. A value of zero indicates that this
processor does not support core C1 or never entered
core C1 level state.
662H 1634 MSR_CORE_C3_RESIDENCY Core Core C3 Residency Counter (R/O)
63:0 Will always return 0.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-43 lists the MSRs of uncore PMU for Intel processors with CPUID signature 06_66H.
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
394H 916 MSR_UNC_PERF_FIXED_CTRL Package Uncore Fixed Counter Control (R/W)
19:0 Reserved
20 Enable overflow propagation.
21 Reserved
22 Enable counting.
63:23 Reserved
395H 917 MSR_UNC_PERF_FIXED_CTR Package Uncore Fixed Counter
47:0 Current count.
63:48 Reserved
396H 918 MSR_UNC_CBO_CONFIG Package Uncore C-Box Configuration Information (R/O)
3B2H 944 MSR_UNC_ARB_PERFEVTSEL0 Package Uncore Arb Unit, Counter 0 Event Select MSR
3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb unit, Counter 1 Event Select MSR
700H 1792 MSR_UNC_CBO_0_PERFEVTSEL0 Package Uncore C-Box 0, Counter 0 Event Select MSR
701H 1793 MSR_UNC_CBO_0_PERFEVTSEL1 Package Uncore C-Box 0, Counter 1 Event Select MSR
702H 1794 MSR_UNC_CBO_0_PERFCTR0 Package Uncore C-Box 0, Performance Counter 0
703H 1795 MSR_UNC_CBO_0_PERFCTR1 Package Uncore C-Box 0, Performance Counter 1
708H 1800 MSR_UNC_CBO_1_PERFEVTSEL0 Package Uncore C-Box 1, Counter 0 Event Select MSR
709H 1801 MSR_UNC_CBO_1_PERFEVTSEL1 Package Uncore C-Box 1, Counter 1 Event Select MSR
70AH 1802 MSR_UNC_CBO_1_PERFCTR0 Package Uncore C-Box 1, Performance Counter 0
70BH 1803 MSR_UNC_CBO_1_PERFCTR1 Package Uncore C-Box 1, Performance Counter 1
710H 1808 MSR_UNC_CBO_2_PERFEVTSEL0 Package Uncore C-Box 2, Counter 0 Event Select MSR
711H 1809 MSR_UNC_CBO_2_PERFEVTSEL1 Package Uncore C-Box 2, Counter 1 Event Select MSR
712H 1810 MSR_UNC_CBO_2_PERFCTR0 Package Uncore C-Box 2, Performance Counter 0
713H 1811 MSR_UNC_CBO_2_PERFCTR1 Package Uncore C-Box 2, Performance Counter 1
718H 1816 MSR_UNC_CBO_3_PERFEVTSEL0 Package Uncore C-Box 3, Counter 0 Event Select MSR
719H 1817 MSR_UNC_CBO_3_PERFEVTSEL1 Package Uncore C-Box 3, Counter 1 Event Select MSR
71AH 1818 MSR_UNC_CBO_3_PERFCTR0 Package Uncore C-Box 3, Performance Counter 0
71BH 1819 MSR_UNC_CBO_3_PERFCTR1 Package Uncore C-Box 3, Performance Counter 1
Vol. 4 2-303
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
720H 1824 MSR_UNC_CBO_4_PERFEVTSEL0 Package Uncore C-Box 4, Counter 0 Event Select MSR
721H 1825 MSR_UNC_CBO_4_PERFEVTSEL1 Package Uncore C-Box 4, Counter 1 Event Select MSR
722H 1826 MSR_UNC_CBO_4_PERFCTR0 Package Uncore C-Box 4, Performance Counter 0
723H 1827 MSR_UNC_CBO_4_PERFCTR1 Package Uncore C-Box 4, Performance Counter 1
728H 1832 MSR_UNC_CBO_5_PERFEVTSEL0 Package Uncore C-Box 5, Counter 0 Event Select MSR
729H 1833 MSR_UNC_CBO_5_PERFEVTSEL1 Package Uncore C-Box 5, Counter 1 Event Select MSR
72AH 1834 MSR_UNC_CBO_5_PERFCTR0 Package Uncore C-Box 5, Performance Counter 0
72BH 1835 MSR_UNC_CBO_5_PERFCTR1 Package Uncore C-Box 5, Performance Counter 1
730H 1840 MSR_UNC_CBO_6_PERFEVTSEL0 Package Uncore C-Box 6, Counter 0 Event Select MSR
731H 1841 MSR_UNC_CBO_6_PERFEVTSEL1 Package Uncore C-Box 6, Counter 1 Event Select MSR
732H 1842 MSR_UNC_CBO_6_PERFCTR0 Package Uncore C-Box 6, Performance Counter 0
733H 1843 MSR_UNC_CBO_6_PERFCTR1 Package Uncore C-Box 6, Performance Counter 1
738H 1848 MSR_UNC_CBO_7_PERFEVTSEL0 Package Uncore C-Box 7, Counter 0 Event Select MSR
739H 1849 MSR_UNC_CBO_7_PERFEVTSEL1 Package Uncore C-Box 7, Counter 1 Event Select MSR
73AH 1850 MSR_UNC_CBO_7_PERFCTR0 Package Uncore C-Box 7, Performance Counter 0
73BH 1851 MSR_UNC_CBO_7_PERFCTR1 Package Uncore C-Box 7, Performance Counter 1
E01H 3585 MSR_UNC_PERF_GLOBAL_CTRL Package Uncore PMU Global Control
0 Slice 0 select.
1 Slice 1 select.
2 Slice 2 select.
3 Slice 3 select.
4 Slice 4select.
18:5 Reserved
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved
E02H 3586 MSR_UNC_PERF_GLOBAL_STATUS Package Uncore PMU Main Status
0 Fixed counter overflowed.
1 An ARB counter overflowed.
2 Reserved
3 A CBox counter overflowed (on any slice).
63:4 Reserved
2-304 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44. MSRs Supported by 10th Generation Intel® Core™ Processors Based on Ice Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
33H 51 MSR_TEST_CTRL Core Test Control Register
28:0 Reserved.
29 Enable #AC(0) exception for split locked accesses:
Cause #AC(0) exception for split locked access at all
CPL irrespective of CR0.AM or EFLAGS.AC. If bits 29
and 31 are both set, bit 29 takes precedence.
30 Reserved.
31 Reserved.
48H 72 IA32_SPEC_CTRL Core See Table 2-2.
49H 73 IA32_PREDICT_CMD Thread See Table 2-2.
8CH 140 IA32_SGXLEPUBKEYHASH0 Thread See Table 2-2.
8DH 141 IA32_SGXLEPUBKEYHASH1 Thread See Table 2-2.
8EH 142 IA32_SGXLEPUBKEYHASH2 Thread See Table 2-2.
8FH 143 IA32_SGXLEPUBKEYHASH3 Thread See Table 2-2.
A0H 160 MSR_BIOS_MCU_ERRORCODE Package BIOS MCU ERRORCODE (R/O)
This MSR indicates if WRMSR 0x79 failed to configure
PRM memory and gives a hint to debug BIOS.
15:0 Package Error Codes (R/O)
30:16 Reserved.
31 Thread MCU Partial Success (R/O)
When set to 1, WRMSR 0x79 skipped part of the
functionality during BIOS.
A5H 165 MSR_FIT_BIOS_ERROR Thread FIT BIOS ERROR (R/W)
Report error codes for debug in case the processor
failed to parse the Firmware Table in BIOS.
Can also be used to log BIOS information.
7:0 Error Codes (R/W)
Error codes for debug.
15:8 Entry Type (R/W)
Failed FIT entry type.
16 FIT MCU Entry (R/W)
FIT contains MCU entry.
62:17 Reserved.
63 LOCK (R/W)
When set to 1, writes to this MSR will be skipped.
Vol. 4 2-305
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44. MSRs Supported by 10th Generation Intel® Core™ Processors Based on Ice Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
10BH 267 IA32_FLUSH_CMD Thread See Table 2-2.
151H 337 MSR_BIOS_DONE Thread BIOS Done (R/WO)
0 Thread BIOS Done Indication (R/WO)
Set by BIOS when it finishes programming the
processor and wants to lock the memory
configuration from changes by software that is
running on this thread.
Writes to the bit will be ignored if EAX[0] is 0.
1 Package Package BIOS Done Indication (R/O)
When set to 1, all threads in the package have bit 0 of
this MSR set.
31:2 Reserved.
1F1H 497 MSR_CRASHLOG_CONTROL Thread Write Data to a Crash Log Configuration
0 CDDIS: CrashDump_Disable
If set, indicates that Crash Dump is disabled.
63:1 Reserved.
2A0H 672 MSR_PRMRR_BASE_0 Core Processor Reserved Memory Range Register -
Physical Base Control Register (R/W)
2:0 MEMTYPE: PRMRR BASE Memory Type.
3 CONFIGURED: PRMRR BASE Configured.
11:4 Reserved.
51:12 BASE: PRMRR Base Address.
63:52 Reserved.
30CH 780 IA32_FIXED_CTR3 Thread Fixed-Function Performance Counter Register 3 (R/W)
Bit definitions are the same as found in
IA32_FIXED_CTR0, offset 309H. See Table 2-2.
329H 809 MSR_PERF_METRICS Thread Performance Metrics (R/W)
Reports metrics directly. Software can check (and/or
expose to its guests) the availability of
PERF_METRICS feature using
IA32_PERF_CAPABILITIES.PERF_METRICS_AVAILABL
E (bit 15).
7:0 Retiring. Percent of utilized slots by uops that
eventually retire (commit).
15:8 Bad Speculation. Percent of wasted slots due to
incorrect speculation, covering utilized by uops that do
not retire, or recovery bubbles (unutilized slots).
23:16 Frontend Bound. Percent of unutilized slots where
front-end did not deliver a uop while back-end is
ready.
31:24 Backend Bound. Percent of unutilized slots where a
uop was not delivered to back-end due to lack of back-
end resources.
2-306 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44. MSRs Supported by 10th Generation Intel® Core™ Processors Based on Ice Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:25 Reserved.
3F2H 1010 MSR_PEBS_DATA_CFG Thread PEBS Data Configuration (R/W)
Provides software the capability to select data groups
of interest and thus reduce the record size in memory
and record generation latency. Hence, a PEBS record's
size and layout vary based on the selected groups.
The MSR also allows software to select LBR depth for
branch data records.
0 Memory Info.
Setting this bit will capture memory information such
as the linear address, data source and latency of the
memory access in the PEBS record.
1 GPRs.
Setting this bit will capture the contents of the
General Purpose registers in the PEBS record.
2 XMMs.
Setting this bit will capture the contents of the XMM
registers in the PEBS record.
3 LBRs.
Setting this bit will capture LBR TO, FROM and INFO in
the PEBS record.
23:4 Reserved.
31:24 LBR Entries.
Set the field to the desired number of entries - 1. For
example, if the LBR_entries field is 0, a single entry
will be included in the record. To include 32 LBR
entries, set the LBR_entries field to 31 (0x1F). To
ensure all PEBS records are 16-byte aligned, software
can use LBR_entries that is multiple of 3.
541H 1345 MSR_CORE_UARCH_CTL Core Core Microarchitecture Control MSR (R/W)
0 L1 Scrubbing Enable
When set to 1, enable L1 scrubbing.
31:1 Reserved.
657H 1623 MSR_FAST_UNCORE_MSRS_CTL Thread Fast WRMSR/RDMSR Control MSR (R/W)
3:0 FAST_ACCESS_ENABLE:
Bit 0: When set to '1', provides a hint for the hardware
to enable fast access mode for the
IA32_HWP_REQUEST MSR.
This bit is sticky and is cleaned by the hardware only
during reset time.
This bit is valid only if
FAST_UNCORE_MSRS_CAPABILITY[0] is set. Setting
this bit will cause CPUID[6].EAX[18] to be set.
31:4 Reserved.
Vol. 4 2-307
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44. MSRs Supported by 10th Generation Intel® Core™ Processors Based on Ice Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
65EH 1630 MSR_FAST_UNCORE_MSRS_STATUS Thread Indication of Uncore MSRs, Post Write Activates
0 Indicates whether the CPU is still in the middle of
writing IA32_HWP_REQUEST MSR, even after the
WRMSR instruction has retired.
A value of 1 indicates the last write of
IA32_HWP_REQUEST is still ongoing.
A value of 0 indicates the last write of
IA32_HWP_REQUEST is visible outside the logical
processor.
Software can use the status of this bit to avoid
overwriting IA32_HWP_REQUEST.
31:1 Reserved.
65FH 1631 MSR_FAST_UNCORE_MSRS_CAPABILITY Thread Fast WRMSR/RDMSR Enumeration MSR (RO)
3:0 MSRS_CAPABILITY:
Bit 0: If set to ‘1’, hardware supports the fast access
mode for the IA32_HWP_REQUEST MSR.
31:4 Reserved.
772H 1906 IA32_HWP_REQUEST_PKG Package See Table 2-2.
775H 1909 IA32_PECI_HWP_REQUEST_INFO Thread See Table 2-2.
777H 1911 IA32_HWP_STATUS Thread See Table 2-2.
2.17.4 MSRs Specific to 11th Generation Intel® Core™ Processors based on Tiger Lake
Microarchitecture
Table 2-45 lists additional MSRs for 11th generation Intel Core processors with CPUID DisplayFamily_DisplayModel
signatures of 06_8CH and 06_8DH. For an MSR listed in Table 2-45 that also appears in the model-specific tables
of prior generations, Table 2-45 supersedes prior generation tables.
Table 2-45. Additional MSRs Supported by 11th Generation Intel® Core™ Processors
Based on Tiger Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
A0H 160 MSR_BIOS_MCU_ERRORCODE Package BIOS MCU ERRORCODE (R/O)
15:0 Error Codes
31:16 Reserved
A7H 167 MSR_BIOS_DEBUG Thread BIOS DEBUG (R/O)
This MSR indicates if WRMSR 79H failed to configure
PRM memory and gives a hint to debug BIOS.
30:0 Reserved
31 MCU Partial Success
When set to 1, WRMSR 79H skipped part of the
functionality during BIOS.
2-308 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-45. Additional MSRs Supported by 11th Generation Intel® Core™ Processors
Based on Tiger Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:32 Reserved
CFH 207 IA32_CORE_CAPABILITIES Package IA32_CR_CORE_CAPABILITIES (R/O)
This MSR provides an architectural enumeration
function for model-specific behavior.
0 STLB_QOS_SUPPORTED
When set to 1, the STLB QoS feature is supported and
the STLB QoS MSRs (1A8FH -1A97H) are accessible.
When set to 0, access to these MSRs will #GP.
1 Reserved
2 FUSA_SUPPORTED
3 RSM_IN_CPL0_ONLY
When set to 1, the RSM instruction is only allowed in
CPL0 (#GP triggered in any CPL != 0).
When set to 0, then any CPL may execute the RSM
instruction.
4 Reserved
5 SPLIT_LOCK_DISABLE_SUPPORTED
When set to 1, the ability to set MEMORY_CONTROL
(MSR 33H) bit 29 enables an #AC to be created when
a split lock is detected.
6 SNOOP_FILTER_QOS_SUPPORTED
When set to 1, the Snoop Filter Qos Mask MSRs are
supported.
When set to 0, access to these MSRs will #GP.
31:7 Reserved
492H 1170 IA32_VMX_PROCBASED_CTLS3 Core IA32_VMX_PROCBASED_CTLS3
This MSR enumerates the allowed 1-settings of the
third set of processor-based controls. Specifically, VM
entry allows bit X of the tertiary processor-based VM-
execution controls to be 1 if and only if bit X of the
MSR is set to 1.
If bit X of the MSR is cleared to 0, VM entry fails if
control X and the “activate tertiary controls” primary
processor-based VM-execution control are both 1.
0 LOADIWKEY
This control determines whether executions of
LOADIWKEY cause VM exits.
63:1 Reserved
601H 1537 MSR_VR_CURRENT_CONFIG Package Power Limit 4 (PL4)
Package-level maximum power limit (in Watts).
It is a proactive, instantaneous limit.
Vol. 4 2-309
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-45. Additional MSRs Supported by 11th Generation Intel® Core™ Processors
Based on Tiger Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
12:0 PL4 Value
PL4 value in 0.125 A increments. This field is locked
by VR_CURRENT_CONFIG[LOCK]. When the LOCK bit is
set to 1b, this field becomes Read Only.
30:13 Reserved
31 Lock Indication (LOCK)
This bit will lock the CURRENT_LIMIT settings in this
register and will also lock this setting. This means that
once set to 1b, the CURRENT_LIMIT setting and this
bit become Read Only until the next Warm Reset.
62:32 Not in use.
63 Reserved
981H 2433 IA32_TME_CAPABILITY See Table 2-2.
982H 2434 IA32_TME_ACTIVATE See Table 2-2.
983H 2435 IA32_TME_EXCLUDE_MASK See Table 2-2.
984H 2436 IA32_TME_EXCLUDE_BASE See Table 2-2.
990H 2448 IA32_COPY_STATUS1 Thread See Table 2-2.
991H 2449 IA32_IWKEYBACKUP_STATUS1 Platform See Table 2-2.
C82H 3202 IA32_L2_QOS_CFG Core IA32_CR_L2_QOS_CFG
This MSR provides software an enumeration of the
parameters that L2 QoS (Intel RDT) support in any
particular implementation.
0 CDP_ENABLE
When set to 1, it will enable the code and data
prioritization for the L2 CAT/Intel RDT feature.
When set to 0, code and data prioritization is disabled
for L2 CAT/Intel RDT. See Chapter 17, “Debug, Branch
Profile, TSC, and Intel® Resource Director Technology
(Intel® RDT) Features” for further details on CDP.
31:1 Reserved
D10H 3220 IA32_L2_QOS_MASK_[0-7] Package IA32_CR_L2_QOS_MASK_[0-7]
- - Controls MLC (L2) Intel RDT allocation. For more
D17H 3351 details on CAT/RDT, see Chapter 17, “Debug, Branch
Profile, TSC, and Intel® Resource Director Technology
(Intel® RDT) Features”.
2-310 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-45. Additional MSRs Supported by 11th Generation Intel® Core™ Processors
Based on Tiger Lake Microarchitecture
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
19:0 WAYS_MASK
Setting a 1 in this bit X allows threads with CLOS <n>
(where N is [0-7]) to allocate to way X in the MLC.
Ones are only allowed to be written to ways that
physically exist in the MLC (CPUID.4.2:EBX[31:22] will
indicate this).
Writing a 1 to a value beyond the highest way or a
non-contiguous set of 1s will cause a #GP on the
WRMSR to this MSR.
31:20 Reserved
D91H 3473 IA32_COPY_LOCAL_TO_PLATFORM1 Thread See Table 2-2.
D92H 3474 IA32_COPY_PLATFORM_TO_LOCAL1 Thread See Table 2-2.
NOTES:
1. Further details on Key Locker and usage of this MSR can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3AH 58 IA32_FEATURE_CONTROL Thread Control Features in Intel 64 Processor (R/W)
See Table 2-2.
0 Lock (R/WL)
1 Enable VMX Inside SMX Operation (R/WL)
2 Enable VMX Outside SMX Operation (R/WL)
14:8 SENTER Local Functions Enables (R/WL)
15 SENTER Global Functions Enable (R/WL)
18 SGX Global Functions Enable (R/WL)
20 LMCE_ENABLED (R/WL)
63:21 Reserved
4EH 78 MSR_PPIN_CTL Package Protected Processor Inventory Number Enable Control
(R/W)
0 LockOut (R/WO)
See Table 2-26.
Vol. 4 2-311
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1 Enable_PPIN (R/W)
See Table 2-26.
63:2 Reserved
4FH 79 MSR_PPIN Package Protected Processor Inventory Number (R/O)
63:0 Protected Processor Inventory Number (R/O)
See Table 2-26.
CEH 206 MSR_PLATFORM_INFO Package Platform Information
Contains power management and other model specific
features enumeration. See http://biosbits.org.
7:0 Reserved
15:8 Package Maximum Non-Turbo Ratio (R/O)
See Table 2-26.
22:16 Reserved.
23 Package PPIN_CAP (R/O)
See Table 2-26.
27:24 Reserved
28 Package Programmable Ratio Limit for Turbo Mode (R/O)
See Table 2-26.
29 Package Programmable TDP Limit for Turbo Mode (R/O)
See Table 2-26.
30 Package Programmable TJ OFFSET (R/O)
See Table 2-26.
39:31 Reserved
47:40 Package Maximum Efficiency Ratio (R/O)
See Table 2-26.
63:48 Reserved
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Core C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
See http://biosbits.org.
2-312 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported
by the processor are available.
9:3 Reserved
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved
15 CFG Lock (R/WO)
16 Automatic C-State Conversion Enable (R/W)
If 1, the processor will convert HALT or MWAT(C1) to
MWAIT(C6).
24:17 Reserved
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Package C State Demotion Enable (R/W)
30 Package C State UnDemotion Enable (R/W)
63:31 Reserved
179H 377 IA32_MCG_CAP Thread Global Machine Check Capability (R/O)
7:0 Count
8 MCG_CTL_P
9 MCG_EXT_P
10 MCP_CMCI_P
11 MCG_TES_P
15:12 Reserved
23:16 MCG_EXT_CNT
24 MCG_SER_P
25 MCG_EM_P
26 MCG_ELOG_P
63:27 Reserved
Vol. 4 2-313
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
17DH 381 MSR_SMM_MCA_CAP THREAD Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only
while in SMM.
57:0 Reserved
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access
restriction is supported and a host-space interface is
available to SMM handler.
59 Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is
supported and a host-space interface is available to
SMM handler.
63:60 Reserved
19CH 412 IA32_THERM_STATUS Core Thermal Monitor Status (R/W)
See Table 2-2.
0 Thermal Status (RO)
See Table 2-2.
1 Thermal Status Log (R/WC0)
See Table 2-2.
2 PROTCHOT # or FORCEPR# Status (RO)
See Table 2-2.
3 PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4 Critical Temperature Status (RO)
See Table 2-2.
5 Critical Temperature Status Log (R/WC0)
See Table 2-2.
6 Thermal Threshold #1 Status (RO)
See Table 2-2.
7 Thermal Threshold #1 Log (R/WC0)
See Table 2-2.
8 Thermal Threshold #2 Status (RO)
See Table 2-2.
9 Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10 Power Limitation Status (RO)
See Table 2-2.
11 Power Limitation Log (R/WC0)
See Table 2-2.
2-314 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
12 Current Limit Status (RO)
See Table 2-2.
13 Current Limit Log (R/WC0)
See Table 2-2.
14 Cross Domain Limit Status (RO)
See Table 2-2.
15 Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16 Digital Readout (RO)
See Table 2-2.
26:23 Reserved
30:27 Resolution in Degrees Celsius (RO)
See Table 2-2.
31 Reading Valid (RO)
See Table 2-2.
63:32 Reserved
1A2H 418 MSR_TEMPERATURE_TARGET Package Temperature Target
15:0 Reserved
23:16 Temperature Target (RO)
See Table 2-26.
27:24 TCC Activation Offset (R/W)
See Table 2-26.
63:28 Reserved
1ADH 429 MSR_TURBO_RATIO_LIMIT Package This register defines the ratio limits. RATIO[0:7] must
be populated in ascending order. RATIO[i+1] must be
less than or equal to RATIO[i]. Entries with RATIO[i] will
be ignored. If any of the rules above are broken, the
configuration is silently rejected. If the programmed
ratio is:
• Above the fused ratio for that core count, it will be
clipped to the fuse limits (assuming !OC).
• Below the min supported ratio, it will be clipped.
7:0 RATIO_0
Defines ratio limits.
15:8 RATIO_1
Defines ratio limits.
23:16 RATIO_2
Defines ratio limits.
31:24 RATIO_3
Defines ratio limits.
Vol. 4 2-315
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
39:32 RATIO_4
Defines ratio limits.
47:40 RATIO_5
Defines ratio limits.
55:48 RATIO_6
Defines ratio limits.
63:56 RATIO_7
Defines ratio limits.
1AEH 430 MSR_TURBO_RATIO_LIMIT_CORES Package This register defines the active core ranges for each
frequency point. NUMCORE[0:7] must be populated in
ascending order. NUMCORE[i+1] must be greater than
NUMCORE[i]. Entries with NUMCORE[i] == 0 will be
ignored. The last valid entry must have NUMCORE >=
the number of cores in the SKU. If any of the rules
above are broken, the configuration is silently rejected.
7:0 NUMCORE_0
Defines the active core ranges for each frequency
point.
15:8 NUMCORE_1
Defines the active core ranges for each frequency
point.
23:16 NUMCORE_2
Defines the active core ranges for each frequency
point.
31:24 NUMCORE_3
Defines the active core ranges for each frequency
point.
39:32 NUMCORE_4
Defines the active core ranges for each frequency
point.
47:40 NUMCORE_5
Defines the active core ranges for each frequency
point.
55:48 NUMCORE_6
Defines the active core ranges for each frequency
point.
63:56 NUMCORE_7
Defines the active core ranges for each frequency
point.
280H 640 IA32_MC0_CTL2 Core See Table 2-2.
281H 641 IA32_MC1_CTL2 Core See Table 2-2.
282H 642 IA32_MC2_CTL2 Core See Table 2-2.
283H 643 IA32_MC3_CTL2 Core See Table 2-2.
2-316 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
284H 644 IA32_MC4_CTL2 Package See Table 2-2.
285H 645 IA32_MC5_CTL2 Package See Table 2-2.
286H 646 IA32_MC6_CTL2 Package See Table 2-2.
287H 647 IA32_MC7_CTL2 Package See Table 2-2.
288H 648 IA32_MC8_CTL2 Package See Table 2-2.
289H 649 IA32_MC9_CTL2 Package See Table 2-2.
28AH 650 IA32_MC10_CTL2 Package See Table 2-2.
28BH 651 IA32_MC11_CTL2 Package See Table 2-2.
28CH 652 IA32_MC12_CTL2 Package See Table 2-2.
28DH 653 IA32_MC13_CTL2 Package See Table 2-2.
28EH 654 IA32_MC14_CTL2 Package See Table 2-2.
28FH 655 IA32_MC15_CTL2 Package See Table 2-2.
290H 656 IA32_MC16_CTL2 Package See Table 2-2.
291H 657 IA32_MC17_CTL2 Package See Table 2-2.
292H 658 IA32_MC18_CTL2 Package See Table 2-2.
293H 659 IA32_MC19_CTL2 Package See Table 2-2.
400H 1024 IA32_MC0_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
401H 1025 IA32_MC0_STATUS Core
Bank MC0 reports MC errors from the IFU module.
402H 1026 IA32_MC0_ADDR Core
403H 1027 IA32_MC0_MISC Core
404H 1028 IA32_MC1_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
405H 1029 IA32_MC1_STATUS Core
Bank MC1 reports MC errors from the DCU module.
406H 1030 IA32_MC1_ADDR Core
407H 1031 IA32_MC1_MISC Core
408H 1032 IA32_MC2_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
409H 1033 IA32_MC2_STATUS Core
Bank MC2 reports MC errors from the DTLB module.
40AH 1034 IA32_MC2_ADDR Core
40BH 1035 IA32_MC2_MISC Core
40CH 1036 IA32_MC3_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
40DH 1037 IA32_MC3_STATUS Core
Bank MC3 reports MC errors from the MLC module.
40EH 1038 IA32_MC3_ADDR Core
40FH 1039 IA32_MC3_MISC Core
410H 1040 IA32_MC4_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
411H 1041 IA32_MC4_STATUS Package
Bank MC4 reports MC errors from the PCU module.
412H 1042 IA32_MC4_ADDR Package
413H 1043 IA32_MC4_MISC Package
Vol. 4 2-317
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
414H 1044 IA32_MC5_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
415H 1045 IA32_MC5_STATUS Package
Bank MC5 reports MC errors from a link interconnect
416H 1046 IA32_MC5_ADDR Package module.
417H 1047 IA32_MC5_MISC Package
418H 1048 IA32_MC6_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
419H 1049 IA32_MC6_STATUS Package
Bank MC6 reports MC errors from the integrated I/O
41AH 1050 IA32_MC6_ADDR Package module.
41BH 1051 IA32_MC6_MISC Package
41CH 1052 IA32_MC7_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
41DH 1053 IA32_MC7_STATUS Package
Bank MC7 reports MC errors from the M2M 0.
41EH 1054 IA32_MC7_ADDR Package
41FH 1055 IA32_MC7_MISC Package
420H 1056 IA32_MC8_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
421H 1057 IA32_MC8_STATUS Package
Bank MC8 reports MC errors from the M2M 1.
422H 1058 IA32_MC8_ADDR Package
423H 1059 IA32_MC8_MISC Package
424H 1060 IA32_MC9_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
425H 1061 IA32_MC9_STATUS Package
Banks MC9 - MC11 report MC errors from the CHA
426H 1062 IA32_MC9_ADDR Package
427H 1063 IA32_MC9_MISC Package
428H 1064 IA32_MC10_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
429H 1065 IA32_MC10_STATUS Package
Banks MC9 - MC11 report MC errors from the CHA.
42AH 1066 IA32_MC10_ADDR Package
42BH 1067 IA32_MC10_MISC Package
42CH 1068 IA32_MC11_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
42DH 1069 IA32_MC11_STATUS Package
Banks MC9 - MC11 report MC errors from the CHA.
42EH 1070 IA32_MC11_ADDR Package
42FH 1071 IA32_MC11_MISC Package
430H 1072 IA32_MC12_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
431H 1073 IA32_MC12_STATUS Package
Banks MC12 report MC errors from each channel of a
432H 1074 IA32_MC12_ADDR Package link interconnect module.
433H 1075 IA32_MC12_MISC Package
434H 1076 IA32_MC13_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
435H 1077 IA32_MC13_STATUS Package
Banks MC13 through MC 18 report MC errors from the
436H 1078 IA32_MC13_ADDR Package integrated memory controllers.
437H 1079 IA32_MC13_MISC Package
2-318 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
438H 1080 IA32_MC14_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
439H 1081 IA32_MC14_STATUS Package
Banks MC13 through MC 18 report MC errors from the
43AH 1082 IA32_MC14_ADDR Package integrated memory controllers.
43BH 1083 IA32_MC14_MISC Package
43CH 1084 IA32_MC15_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
43DH 1085 IA32_MC15_STATUS Package
Banks MC13 through MC 18 report MC errors from the
43EH 1086 IA32_MC15_ADDR Package integrated memory controllers.
43FH 1087 IA32_MC15_MISC Package
440H 1088 IA32_MC16_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
441H 1089 IA32_MC16_STATUS Package
Banks MC13 through MC 18 report MC errors from the
442H 1090 IA32_MC16_ADDR Package integrated memory controllers
443H 1091 IA32_MC16_MISC Package
444H 1092 IA32_MC17_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
445H 1093 IA32_MC17_STATUS Package
Banks MC13 through MC 18 report MC errors from the
446H 1094 IA32_MC17_ADDR Package integrated memory controllers.
447H 1095 IA32_MC17_MISC Package
448H 1096 IA32_MC18_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
449H 1097 IA32_MC18_STATUS Package
Banks MC13 through MC 18 report MC errors from the
44AH 1098 IA32_MC18_ADDR Package integrated memory controllers.
44BH 1099 IA32_MC18_MISC Package
44CH 1100 IA32_MC19_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through
Section 15.3.2.4, “IA32_MCi_MISC MSRs.”.
44DH 1101 IA32_MC19_STATUS Package
Bank MC19 reports MC errors from a link interconnect
44EH 1102 IA32_MC19_ADDR Package module.
44FH 1103 IA32_MC19_MISC Package
606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers Used in RAPL Interfaces (R/O)
3:0 Package Power Units
See Section 14.10.1, “RAPL Interfaces.”
7:4 Package Reserved
12:8 Package Energy Status Units
Energy related information (in Joules) is based on the
multiplier, 1/2^ESU; where ESU is an unsigned integer
represented by bits 12:8. Default value is 0EH (or 61
micro-joules).
15:13 Package Reserved
19:16 Package Time Units
See Section 14.10.1, “RAPL Interfaces.”
63:20 Reserved
Vol. 4 2-319
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
618H 1560 MSR_DRAM_POWER_LIMIT Package DRAM RAPL Power Limit Control (R/W)
See Section 14.10.5, “DRAM RAPL Domain.”
619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O)
Energy consumed by DRAM devices.
31:0 Energy in 15.3 micro-joules. Requires BIOS
configuration to enable DRAM RAPL mode 0 (Direct
VR).
63:32 Reserved
61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W)
See Section 14.10.5, “DRAM RAPL Domain.”
620H 1568 MSR UNCORE_RATIO_LIMIT Package Uncore Ratio Limit (R/W)
Out of reset, the min_ratio and max_ratio fields
represent the widest possible range of uncore
frequencies. Writing to these fields allows software to
control the minimum and the maximum frequency that
hardware will select.
63:15 Reserved
14:8 MIN_RATIO
Writing to this field controls the minimum possible ratio
of the LLC/Ring.
7 Reserved
6:0 MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
639H 1593 MSR_PP0_ENERGY_STATUS Package Reserved (R/O)
Reads return 0.
C8DH 3213 IA32_QM_EVTSEL THREAD Monitoring Event Select Register (R/W)
If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.
7:0 EventID (RW)
Event encoding:
0x00: No monitoring.
0x01: L3 occupancy monitoring.
0x02: Total memory bandwidth monitoring.
0x03: Local memory bandwidth monitoring.
All other encoding reserved.
31:8 Reserved
41:32 RMID (RW)
63:42 Reserved
C8FH 3215 IA32_PQR_ASSOC THREAD Resource Association Register (R/W)
9:0 RMID
2-320 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
31:10 Reserved
51:32 COS (R/W)
63: 52 Reserved
C90H 3216 IA32_L3_QOS_MASK_0 Package L3 Class Of Service Mask - COS 0 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
0:19 CBM: Bit vector of available L3 ways for COS 0
enforcement.
63:20 Reserved
C91H 3217 IA32_L3_QOS_MASK_1 Package L3 Class Of Service Mask - COS 1 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.
0:19 CBM: Bit vector of available L3 ways for COS 1
enforcement.
63:20 Reserved
C92H 3218 IA32_L3_QOS_MASK_2 Package L3 Class Of Service Mask - COS 2 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.
0:19 CBM: Bit vector of available L3 ways for COS 2
enforcement.
63:20 Reserved
C93H 3219 IA32_L3_QOS_MASK_3 Package L3 Class Of Service Mask - COS 3 (R/W).
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
0:19 CBM: Bit vector of available L3 ways for COS 3
enforcement.
63:20 Reserved
C94H 3220 IA32_L3_QOS_MASK_4 Package L3 Class Of Service Mask - COS 4 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4.
0:19 CBM: Bit vector of available L3 ways for COS 4
enforcement.
63:20 Reserved
C95H 3221 IA32_L3_QOS_MASK_5 Package L3 Class Of Service Mask - COS 5 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5.
0:19 CBM: Bit vector of available L3 ways for COS 5
enforcement.
63:20 Reserved
C96H 3222 IA32_L3_QOS_MASK_6 Package L3 Class Of Service Mask - COS 6 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6.
0:19 CBM: Bit vector of available L3 ways for COS 6
enforcement.
63:20 Reserved
C97H 3223 IA32_L3_QOS_MASK_7 Package L3 Class Of Service Mask - COS 7 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7.
Vol. 4 2-321
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
0:19 CBM: Bit vector of available L3 ways for COS 7
enforcement.
63:20 Reserved
C98H 3224 IA32_L3_QOS_MASK_8 Package L3 Class Of Service Mask - COS 8 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8.
0:19 CBM: Bit vector of available L3 ways for COS 8
enforcement.
63:20 Reserved
C99H 3225 IA32_L3_QOS_MASK_9 Package L3 Class Of Service Mask - COS 9 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9.
0:19 CBM: Bit vector of available L3 ways for COS 9
enforcement.
63:20 Reserved
C9AH 3226 IA32_L3_QOS_MASK_10 Package L3 Class Of Service Mask - COS 10 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=10.
0:19 CBM: Bit vector of available L3 ways for COS 10
enforcement.
63:20 Reserved
C9BH 3227 IA32_L3_QOS_MASK_11 Package L3 Class Of Service Mask - COS 11 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=11.
0:19 CBM: Bit vector of available L3 ways for COS 11
enforcement.
63:20 Reserved
C9CH 3228 IA32_L3_QOS_MASK_12 Package L3 Class Of Service Mask - COS 12 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=12.
0:19 CBM: Bit vector of available L3 ways for COS 12
enforcement.
63:20 Reserved
C9DH 3229 IA32_L3_QOS_MASK_13 Package L3 Class Of Service Mask - COS 13 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=13.
0:19 CBM: Bit vector of available L3 ways for COS 13
enforcement.
63:20 Reserved
C9EH 3230 IA32_L3_QOS_MASK_14 Package L3 Class Of Service Mask - COS 14 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=14.
0:19 CBM: Bit vector of available L3 ways for COS 14
enforcement.
2-322 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:20 Reserved
C9FH 3231 IA32_L3_QOS_MASK_15 Package L3 Class Of Service Mask - COS 15 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
>=15.
0:19 CBM: Bit vector of available L3 ways for COS 15
enforcement.
63:20 Reserved
2.17.6 MSRs Specific to 3rd Generation Intel® Xeon® Processor Scalable Family based on Ice
Lake Microarchitecture
The 3rd generation Intel® Xeon® Processor Scalable Family based on Ice Lake microarchitecture (CPUID
DisplayFamily_DisplayModel signatures of 06_6AH and 06_6CH) support the MSRs listed in Table 2-47.
Table 2-47. MSRs Supported by 3rd Generation Intel® Xeon® Processor Scalable Family with
DisplayFamily_DisplayModel Signatures of 06_6AH and 06_6CH
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
612H 1554 MSR_PACKAGE_ENERGY_TIME_STATUS Package Package energy consumed by the entire CPU (R/W)
31:0 Total amount of energy consumed since last reset.
63:32 Total time elapsed when the energy was last updated.
This is a monotonic increment counter with auto wrap
back to zero after overflow. Unit is 10ns.
618H 1560 MSR_DRAM_POWER_LIMIT Package Allows software to set power limits for the DRAM
domain and measurement attributes associated with
each limit.
14:0 DRAM_PP_PWR_LIM:
Power Limit[0] for DDR domain. Units = Watts, Format
= 11.3, Resolution = 0.125W, Range = 0-2047.875W.
15 PWR_LIM_CTRL_EN:
Power Limit[0] enable bit for DDR domain.
16 Reserved
23:17 CTRL_TIME_WIN:
Power Limit[0] time window Y value, for DDR domain.
Actual time_window for RAPL is:
(1/1024 seconds) * (1+(x/4)) * (2^y)
62:24 Reserved
63 PP_PWR_LIM_LOCK:
When set, this entire register becomes read-only. This
bit will typically be set by BIOS during boot.
Vol. 4 2-323
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-47. MSRs Supported by 3rd Generation Intel® Xeon® Processor Scalable Family with
DisplayFamily_DisplayModel Signatures of 06_6AH and 06_6CH
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
31:0 Energy in 15.3 micro-joules. Requires BIOS
configuration to enable DRAM RAPL mode 0 (Direct
VR).
63:32 Reserved
61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
61CH 1564 MSR_DRAM_POWER_INFO Package DRAM Power Parameters (R/W)
14:0 Spec DRAM Power (DRAM_TDP):
The Spec power allowed for DRAM. The TDP setting is
typical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
15 Reserved
30:16 Minimal DRAM Power (DRAM_MIN_PWR):
The minimal power setting allowed for DRAM. Lower
values will be clamped to this value. The minimum
setting is typical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
31 Reserved
46:32 Maximal Package Power (DRAM_MAX_PWR):
The maximal power setting allowed for DRAM. Higher
values will be clamped to this value. The maximum
setting is typical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
47 Reserved
54:48 Maximal Time Window (DRAM_MAX_WIN):
The maximal time window allowed for the DRAM.
Higher values will be clamped to this value.
x = PKG_MAX_WIN[54:53]
y = PKG_MAX_WIN[52:48]
The timing interval window is Floating Point number
given by 1.x *power(2,y).
The unit of measurement is defined in
MSR_DRAM_POWER_INFO_UNIT[TIME_UNIT].
62:55 Reserved
2-324 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-47. MSRs Supported by 3rd Generation Intel® Xeon® Processor Scalable Family with
DisplayFamily_DisplayModel Signatures of 06_6AH and 06_6CH
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63 LOCK:
Lock bit to lock the register.
981H 2433 IA32_TME_CAPABILITY See Table 2-2.
982H 2434 IA32_TME_ACTIVATE See Table 2-2.
983H 2435 IA32_TME_EXCLUDE_MASK See Table 2-2.
984H 2436 IA32_TME_EXCLUDE_BASE See Table 2-2.
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
0H 0 IA32_P5_MC_ADDR Module See Section 2.23, “MSRs in Pentium Processors.”
1H 1 IA32_P5_MC_TYPE Module See Section 2.23, “MSRs in Pentium Processors.”
6H 6 IA32_MONITOR_FILTER_SIZE Thread See Section 8.10.5, “Monitor/Mwait Address Range
Determination.” See Table 2-2.
10H 16 IA32_TIME_STAMP_COUNTER Thread See Section 17.17, “Time-Stamp Counter,” and see
Table 2-2.
17H 23 IA32_PLATFORM_ID Package Platform ID (R)
See Table 2-2.
1BH 27 IA32_APIC_BASE Thread See Section 10.4.4, “Local APIC Status and Location,”
and Table 2-2.
34H 52 MSR_SMI_COUNT Thread SMI Counter (R/O)
31:0 SMI Count (R/O)
63:32 Reserved
3AH 58 IA32_FEATURE_CONTROL Thread Control Features in Intel 64Processor (R/W)
See Table 2-2.
0 Lock (R/WL)
1 Reserved
2 Enable VMX outside SMX operation (R/WL)
Vol. 4 2-325
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3BH 59 IA32_TSC_ADJUST THREAD Per-Logical-Processor TSC ADJUST (R/W)
See Table 2-2.
4EH 78 MSR_PPIN_CTL Package Protected Processor Inventory Number Enable Control
(R/W)
0 LockOut (R/WO)
See Table 2-26.
1 Enable_PPIN (R/W)
See Table 2-26.
63:2 Reserved
4FH 79 MSR_PPIN Package Protected Processor Inventory Number (R/O)
63:0 Protected Processor Inventory Number (R/O)
A unique value within a given CPUID
family/model/stepping signature that a privileged
inventory initialization agent can access to identify each
physical processor, when access to MSR_PPIN is
enabled. Access to MSR_PPIN is permitted only if
MSR_PPIN_CTL[bits 1:0] = ‘10b’.
79H 121 IA32_BIOS_UPDT_TRIG Core BIOS Update Trigger Register (W)
See Table 2-2.
8BH 139 IA32_BIOS_SIGN_ID THREAD BIOS Update Signature ID (RO)
See Table 2-2.
C1H 193 IA32_PMC0 THREAD Performance Counter Register
See Table 2-2.
C2H 194 IA32_PMC1 THREAD Performance Counter Register
See Table 2-2.
CEH 206 MSR_PLATFORM_INFO Package Platform Information
Contains power management and other model specific
features enumeration. See http://biosbits.org.
7:0 Reserved
15:8 Package Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC runs
at. Frequency = ratio * 100 MHz.
27:16 Reserved
28 Package Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit
for Turbo mode is enabled. When set to 0, indicates
Programmable Ratio Limit for Turbo mode is disabled.
29 Package Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode
is programmable. When set to 0, indicates TDP Limit for
Turbo mode is not programmable.
2-326 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
39:30 Reserved
47:40 Package Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the
processor can operate, in units of 100MHz.
63:48 Reserved
E2H 226 MSR_PKG_CST_CONFIG_CONTROL Package C-State Configuration Control (R/W)
2:0 Package C-State Limit (R/W)
Specifies the lowest C-state for the package. This
feature does not limit the processor core C-state. The
power-on default value from bit[2:0] of this register
reports the deepest package C-state the processor is
capable to support when manufactured. It is
recommended that BIOS always read the power-on
default value reported from this bit field to determine
the supported deepest C-state on the processor and
leave it as default without changing it.
000b - C0/C1 (No package C-state support)
001b - C2
010b - C6 (non retention)*
011b - C6 (Retention)*
100b - Reserved
101b - Reserved
110b - Reserved
111b - No package C-state limit. All C-States supported
by the processor are available.
Note: C6 retention mode provides more power saving
than C6 non-retention mode. Limiting the package to C6
non retention mode does prevent the
MSR_PKG_C6_RESIDENCY counter (MSR 3F9h) from
being incremented.
9:3 Reserved
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
registers at MSR_PMG_IO_CAPTURE_BASE[15:0] to
MWAIT instructions.
14:11 Reserved
15 CFG Lock (RO)
When set, locks bits [15:0] of this register for further
writes until the next reset occurs.
25 Reserved
26 C1 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote
C3/C6/C7 requests to C1 based on uncore auto-demote
information.
Vol. 4 2-327
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
27 Reserved
28 C1 State Auto Undemotion Enable (R/W)
When set, enables Undemotion from Demoted C1.
29 PKG C-State Auto Demotion Enable (R/W)
When set, enables Package C state demotion.
63:30 Reserved
E4H 228 MSR_PMG_IO_CAPTURE_BASE Tile Power Management IO Capture Base (R/W)
15:0 LVL_2 Base Address (R/W)
Microcode will compare IO-read zone to this base
address to determine if an MWAIT(C2/3/4) needs to be
issued instead of the IO-read. Should be programmed to
the chipset Plevel_2 IO address.
22:16 C-State Range (R/W)
The IO-port block size in which IO-redirection will be
executed (0-127). Should be programmed based on the
number of LVLx registers existing in the chipset.
63:23 Reserved
E7H 231 IA32_MPERF Thread Maximum Performance Frequency Clock Count (RW)
See Table 2-2.
E8H 232 IA32_APERF Thread Actual Performance Frequency Clock Count (RW)
See Table 2-2.
FEH 254 IA32_MTRRCAP Core Memory Type Range Register (R)
See Table 2-2.
13CH 52 MSR_FEATURE_CONFIG Core AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler
to handle unsuccessful read of this MSR.
1:0 AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of
AES instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
Otherwise, AES instructions are available.
Note, the AES instruction set is not available if read is
unsuccessful. If the configuration is not 01b, AES
instructions can be mis-configured if a privileged agent
unintentionally writes 11b.
63:2 Reserved
140H 320 MISC_FEATURE_ENABLES Thread MISC_FEATURE_ENABLES
0 Reserved
2-328 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
1 User Mode MONITOR and MWAIT (R/W)
If set to 1, the MONITOR and MWAIT instructions do not
cause invalid-opcode exceptions when executed with
CPL > 0 or in virtual-8086 mode. If MWAIT is executed
when CPL > 0 or in virtual-8086 mode, and if EAX
indicates a C-state other than C0 or C1, the instruction
operates as if EAX indicated the C-state C1.
63:2 Reserved
174H 372 IA32_SYSENTER_CS Thread See Table 2-2.
175H 373 IA32_SYSENTER_ESP Thread See Table 2-2.
176H 374 IA32_SYSENTER_EIP Thread See Table 2-2.
179H 377 IA32_MCG_CAP Thread See Table 2-2.
17AH 378 IA32_MCG_STATUS Thread See Table 2-2.
17DH 381 MSR_SMM_MCA_CAP Thread Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only
while in SMM.
31:0 Bank Support (SMM-RO)
One bit per MCA bank. If the bit is set, that bank
supports Enhanced MCA (Default all 0; does not support
EMCA).
55:32 Reserved
56 Targeted SMI (SMM-RO)
Set if targeted SMI is supported.
57 SMM_CPU_SVRSTR (SMM-RO)
Set if SMM SRAM save/restore feature is supported.
58 SMM_CODE_ACCESS_CHK (SMM-RO)
Set if SMM code access check feature is supported.
59 Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator is
supported and a host-space interface available to SMM
handler.
63:60 Reserved
186H 390 IA32_PERFEVTSEL0 Thread Performance Monitoring Event Select Register (R/W)
See Table 2-2.
7:0 Event Select
15:8 UMask
16 USR
17 OS
18 Edge
19 PC
Vol. 4 2-329
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
20 INT
21 AnyThread
22 EN
23 INV
31:24 CMASK
63:32 Reserved
187H 391 IA32_PERFEVTSEL1 Thread See Table 2-2.
198H 408 IA32_PERF_STATUS Package See Table 2-2.
199H 409 IA32_PERF_CTL Thread See Table 2-2.
19AH 410 IA32_CLOCK_MODULATION Thread Clock Modulation (R/W)
See Table 2-2.
19BH 411 IA32_THERM_INTERRUPT Module Thermal Interrupt Control (R/W)
See Table 2-2.
19CH 412 IA32_THERM_STATUS Module Thermal Monitor Status (R/W)
See Table 2-2.
0 Thermal Status (RO)
1 Thermal Status Log (R/WC0)
2 PROTCHOT # or FORCEPR# Status (RO)
3 PROTCHOT # or FORCEPR# Log (R/WC0)
4 Critical Temperature Status (RO)
5 Critical Temperature Status Log (R/WC0)
6 Thermal Threshold #1 Status (RO)
7 Thermal Threshold #1 Log (R/WC0)
8 Thermal Threshold #2 Status (RO)
9 Thermal Threshold #2 Log (R/WC0)
10 Power Limitation Status (RO)
11 Power Limitation Log (RWC0)
15:12 Reserved
22:16 Digital Readout (RO)
26:23 Reserved
30:27 Resolution in Degrees Celsius (RO)
31 Reading Valid (RO)
63:32 Reserved
1A0H 416 IA32_MISC_ENABLE Thread Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled
and disabled.
0 Fast-Strings Enable
2-330 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
2:1 Reserved
3 Automatic Thermal Control Circuit Enable (R/W)
6:4 Reserved
7 Performance Monitoring Available (R)
10:8 Reserved
11 Branch Trace Storage Unavailable (RO)
12 Processor Event Based Sampling Unavailable (RO)
15:13 Reserved
16 Enhanced Intel SpeedStep Technology Enable (R/W)
18 ENABLE MONITOR FSM (R/W)
21:19 Reserved
22 Limit CPUID Maxval (R/W)
23 xTPR Message Disable (R/W)
33:24 Reserved
34 XD Bit Disable (R/W)
37:35 Reserved
38 Turbo Mode Disable (R/W)
63:39 Reserved
1A2H 418 MSR_TEMPERATURE_TARGET Package Temperature Target
15:0 Reserved
23:16 Temperature Target (R)
29:24 Target Offset (R/W)
63:30 Reserved
1A4H 420 MSR_MISC_FEATURE_CONTROL Miscellaneous Feature Control (R/W)
0 Core DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher.
1 Core L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher.
63:2 Reserved
1A6H 422 MSR_OFFCORE_RSP_0 Shared Offcore Response Event Select Register (R/W)
1A7H 423 MSR_OFFCORE_RSP_1 Shared Offcore Response Event Select Register (R/W)
1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode for Groups of Cores
(RW)
0 Reserved
7:1 Package Maximum Number of Cores in Group 0
Number active processor cores which operates under
the maximum ratio limit for group 0.
Vol. 4 2-331
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
15:8 Package Maximum Ratio Limit for Group 0
Maximum turbo ratio limit when the number of active
cores are not more than the group 0 maximum core
count.
20:16 Package Number of Incremental Cores Added to Group 1
Group 1, which includes the specified number of
additional cores plus the cores in group 0, operates
under the group 1 turbo max ratio limit = “group 0 Max
ratio limit” - “group ratio delta for group 1”.
23:21 Package Group Ratio Delta for Group 1
An unsigned integer specifying the ratio decrement
relative to the Max ratio limit to Group 0.
28:24 Package Number of Incremental Cores Added to Group 2
Group 2, which includes the specified number of
additional cores plus all the cores in group 1, operates
under the group 2 turbo max ratio limit = “group 1 Max
ratio limit” - “group ratio delta for group 2”.
31:29 Package Group Ratio Delta for Group 2
An unsigned integer specifying the ratio decrement
relative to the Max ratio limit for Group 1.
36:32 Package Number of Incremental Cores Added to Group 3
Group 3, which includes the specified number of
additional cores plus all the cores in group 2, operates
under the group 3 turbo max ratio limit = “group 2 Max
ratio limit” - “group ratio delta for group 3”.
39:37 Package Group Ratio Delta for Group 3
An unsigned integer specifying the ratio decrement
relative to the Max ratio limit for Group 2.
44:40 Package Number of Incremental Cores Added to Group 4
Group 4, which includes the specified number of
additional cores plus all the cores in group 3, operates
under the group 4 turbo max ratio limit = “group 3 Max
ratio limit” - “group ratio delta for group 4”.
47:45 Package Group Ratio Delta for Group 4
An unsigned integer specifying the ratio decrement
relative to the Max ratio limit for Group 3.
52:48 Package Number of Incremental Cores Added to Group 5
Group 5, which includes the specified number of
additional cores plus all the cores in group 4, operates
under the group 5 turbo max ratio limit = “group 4 Max
ratio limit” - “group ratio delta for group 5”.
55:53 Package Group Ratio Delta for Group 5
An unsigned integer specifying the ratio decrement
relative to the Max ratio limit for Group 4.
2-332 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
60:56 Package Number of Incremental Cores Added to Group 6
Group 6, which includes the specified number of
additional cores plus all the cores in group 5, operates
under the group 6 turbo max ratio limit = “group 5 Max
ratio limit” - “group ratio delta for group 6”.
63:61 Package Group Ratio Delta for Group 6
An unsigned integer specifying the ratio decrement
relative to the Max ratio limit for Group 5.
1B0H 432 IA32_ENERGY_PERF_BIAS Thread See Table 2-2.
1B1H 433 IA32_PACKAGE_THERM_STATUS Package See Table 2-2.
1B2H 434 IA32_PACKAGE_THERM_INTERRUPT Package See Table 2-2.
1C8H 456 MSR_LBR_SELECT Thread Last Branch Record Filtering Select Register (R/W)
See Section 17.9.2, “Filtering of Last Branch Records.”
0 CPL_EQ_0
1 CPL_NEQ_0
2 JCC
3 NEAR_REL_CALL
4 NEAR_IND_CALL
5 NEAR_RET
6 NEAR_IND_JMP
7 NEAR_REL_JMP
8 FAR_BRANCH
63:9 Reserved
1C9H 457 MSR_LASTBRANCH_TOS Thread Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-2) that points to the MSR
containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
1D9H 473 IA32_DEBUGCTL Thread Debug Control (R/W)
0 LBR
Setting this bit to 1 enables the processor to record a
running trace of the most recent branches taken by the
processor in the LBR stack.
1 BTF
Setting this bit to 1 enables the processor to treat
EFLAGS.TF as single-step on branches instead of single-
step on instructions.
5:2 Reserved
6 TR
Setting this bit to 1 enables branch trace messages to
be sent.
Vol. 4 2-333
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
7 BTS
Setting this bit enables branch trace messages (BTMs)
to be logged in a BTS buffer.
8 BTINT
When clear, BTMs are logged in a BTS buffer in circular
fashion. When this bit is set, an interrupt is generated
by the BTS facility when the BTS buffer is full.
9 BTS_OFF_OS
When set, BTS or BTM is skipped if CPL = 0.
10 BTS_OFF_USR
When set, BTS or BTM is skipped if CPL > 0.
11 FREEZE_LBRS_ON_PMI
When set, the LBR stack is frozen on a PMI request.
12 FREEZE_PERFMON_ON_PMI
When set, each ENABLE bit of the global counter control
MSR are frozen (address 3BFH) on a PMI request.
13 Reserved
14 FREEZE_WHILE_SMM
When set, freezes perfmon and trace messages while in
SMM.
31:15 Reserved
1DDH 477 MSR_LER_FROM_LIP Thread Last Exception Record from Linear IP (R)
1DEH 478 MSR_LER_TO_LIP Thread Last Exception Record to Linear IP (R)
1F2H 498 IA32_SMRR_PHYSBASE Core See Table 2-2.
1F3H 499 IA32_SMRR_PHYSMASK Core See Table 2-2.
200H 512 IA32_MTRR_PHYSBASE0 Core See Table 2-2.
201H 513 IA32_MTRR_PHYSMASK0 Core See Table 2-2.
202H 514 IA32_MTRR_PHYSBASE1 Core See Table 2-2.
203H 515 IA32_MTRR_PHYSMASK1 Core See Table 2-2.
204H 516 IA32_MTRR_PHYSBASE2 Core See Table 2-2.
205H 517 IA32_MTRR_PHYSMASK2 Core See Table 2-2.
206H 518 IA32_MTRR_PHYSBASE3 Core See Table 2-2.
207H 519 IA32_MTRR_PHYSMASK3 Core See Table 2-2.
208H 520 IA32_MTRR_PHYSBASE4 Core See Table 2-2.
209H 521 IA32_MTRR_PHYSMASK4 Core See Table 2-2.
20AH 522 IA32_MTRR_PHYSBASE5 Core See Table 2-2.
20BH 523 IA32_MTRR_PHYSMASK5 Core See Table 2-2.
20CH 524 IA32_MTRR_PHYSBASE6 Core See Table 2-2.
2-334 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
20DH 525 IA32_MTRR_PHYSMASK6 Core See Table 2-2.
20EH 526 IA32_MTRR_PHYSBASE7 Core See Table 2-2.
20FH 527 IA32_MTRR_PHYSMASK7 Core See Table 2-2.
250H 592 IA32_MTRR_FIX64K_00000 Core See Table 2-2.
258H 600 IA32_MTRR_FIX16K_80000 Core See Table 2-2.
259H 601 IA32_MTRR_FIX16K_A0000 Core See Table 2-2.
268H 616 IA32_MTRR_FIX4K_C0000 Core See Table 2-2.
269H 617 IA32_MTRR_FIX4K_C8000 Core See Table 2-2.
26AH 618 IA32_MTRR_FIX4K_D0000 Core See Table 2-2.
26BH 619 IA32_MTRR_FIX4K_D8000 Core See Table 2-2.
26CH 620 IA32_MTRR_FIX4K_E0000 Core See Table 2-2.
26DH 621 IA32_MTRR_FIX4K_E8000 Core See Table 2-2.
26EH 622 IA32_MTRR_FIX4K_F0000 Core See Table 2-2.
26FH 623 IA32_MTRR_FIX4K_F8000 Core See Table 2-2.
277H 631 IA32_PAT Core See Table 2-2.
2FFH 767 IA32_MTRR_DEF_TYPE Core Default Memory Types (R/W)
See Table 2-2.
309H 777 IA32_FIXED_CTR0 Thread Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
30AH 778 IA32_FIXED_CTR1 Thread Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
30BH 779 IA32_FIXED_CTR2 Thread Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
345H 837 IA32_PERF_CAPABILITIES Package See Table 2-2. See Section 17.4.1, “IA32_DEBUGCTL
MSR.”
38DH 909 IA32_FIXED_CTR_CTRL Thread Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
38EH 910 IA32_PERF_GLOBAL_STATUS Thread See Table 2-2.
38FH 911 IA32_PERF_GLOBAL_CTRL Thread See Table 2-2.
390H 912 IA32_PERF_GLOBAL_OVF_CTRL Thread See Table 2-2.
3F1H 1009 MSR_PEBS_ENABLE Thread See Table 2-2.
3F8H 1016 MSR_PKG_C3_RESIDENCY Package Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
63:0 Package C3 Residency Counter (R/O)
3F9H 1017 MSR_PKG_C6_RESIDENCY Package
63:0 Package C6 Residency Counter (R/O)
3FAH 1018 MSR_PKG_C7_RESIDENCY Package
Vol. 4 2-335
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
63:0 Package C7 Residency Counter (R/O)
3FCH 1020 MSR_MC0_RESIDENCY Module Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
63:0 Module C0 Residency Counter (R/O)
3FDH 1021 MSR_MC6_RESIDENCY Module
63:0 Module C6 Residency Counter (R/O)
3FFH 1023 MSR_CORE_C6_RESIDENCY Core Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
63:0 CORE C6 Residency Counter (R/O)
400H 1024 IA32_MC0_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H 1025 IA32_MC0_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H 1026 IA32_MC0_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
404H 1028 IA32_MC1_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H 1029 IA32_MC1_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
408H 1032 IA32_MC2_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H 1033 IA32_MC2_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH 1034 IA32_MC2_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
40CH 1036 IA32_MC3_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH 1037 IA32_MC3_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH 1038 IA32_MC3_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
410H 1040 IA32_MC4_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H 1041 IA32_MC4_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H 1042 IA32_MC4_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented
or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
414H 1044 IA32_MC5_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
415H 1045 IA32_MC5_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
416H 1046 IA32_MC5_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
4C1H 1217 IA32_A_PMC0 Thread See Table 2-2.
4C2H 1218 IA32_A_PMC1 Thread See Table 2-2.
600H 1536 IA32_DS_AREA Thread DS Save Area (R/W)
See Table 2-2.
606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers Used in RAPL Interfaces (R/O)
2-336 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
3:0 Package Power Units
See Section 14.10.1, “RAPL Interfaces.”
7:4 Package Reserved
12:8 Package Energy Status Units
Energy related information (in Joules) is based on the
multiplier, 1/2^ESU; where ESU is an unsigned integer
represented by bits 12:8. Default value is 0EH (or 61
micro-joules).
15:13 Package Reserved
19:16 Package Time Units
See Section 14.10.1, “RAPL Interfaces.”
63:20 Reserved
60DH 1549 MSR_PKG_C2_RESIDENCY Package Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
63:0 Package C2 Residency Counter (R/O)
610H 1552 MSR_PKG_POWER_LIMIT Package PKG RAPL Power Limit Control (R/W)
See Section 14.10.3, “Package RAPL Domain.”
611H 1553 MSR_PKG_ENERGY_STATUS Package PKG Energy Status (R/O)
See Section 14.10.3, “Package RAPL Domain.”
613H 1555 MSR_PKG_PERF_STATUS Package PKG Perf Status (R/O)
See Section 14.10.3, “Package RAPL Domain.”
614H 1556 MSR_PKG_POWER_INFO Package PKG RAPL Parameters (R/W)
See Section 14.10.3, “Package RAPL Domain.”
618H 1560 MSR_DRAM_POWER_LIMIT Package DRAM RAPL Power Limit Control (R/W)
See Section 14.10.5, “DRAM RAPL Domain.”
619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O)
See Section 14.10.5, “DRAM RAPL Domain.”
61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W)
See Section 14.10.5, “DRAM RAPL Domain.”
638H 1592 MSR_PP0_POWER_LIMIT Package PP0 RAPL Power Limit Control (R/W)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O)
See Section 14.10.4, “PP0/PP1 RAPL Domains.”
648H 1608 MSR_CONFIG_TDP_NOMINAL Package Base TDP Ratio (R/O)
See Table 2-25.
Vol. 4 2-337
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
649H 1609 MSR_CONFIG_TDP_LEVEL1 Package ConfigTDP Level 1 ratio and power level (R/O)
See Table 2-25.
64AH 1610 MSR_CONFIG_TDP_LEVEL2 Package ConfigTDP Level 2 ratio and power level (R/O)
See Table 2-25.
64BH 1611 MSR_CONFIG_TDP_CONTROL Package ConfigTDP Control (R/W)
See Table 2-25.
64CH 1612 MSR_TURBO_ACTIVATION_RATIO Package ConfigTDP Control (R/W)
See Table 2-25.
690H 1680 MSR_CORE_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in Processor Cores (R/W)
(Frequency refers to processor core frequency.)
0 PROCHOT Status (R0)
1 Thermal Status (R0)
5:2 Reserved
6 VR Therm Alert Status (R0)
7 Reserved
8 Electrical Design Point Status (R0)
63:9 Reserved
6E0H 1760 IA32_TSC_DEADLINE Core TSC Target of Local APIC’s TSC Deadline Mode (R/W)
See Table 2-2.
802H 2050 IA32_X2APIC_APICID Thread x2APIC ID Register (R/O)
803H 2051 IA32_X2APIC_VERSION Thread x2APIC Version Register (R/O)
808H 2056 IA32_X2APIC_TPR Thread x2APIC Task Priority Register (R/W)
80AH 2058 IA32_X2APIC_PPR Thread x2APIC Processor Priority Register (R/O)
80BH 2059 IA32_X2APIC_EOI Thread x2APIC EOI Register (W/O)
80DH 2061 IA32_X2APIC_LDR Thread x2APIC Logical Destination Register (R/O)
80FH 2063 IA32_X2APIC_SIVR Thread x2APIC Spurious Interrupt Vector Register (R/W)
810H 2064 IA32_X2APIC_ISR0 Thread x2APIC In-Service Register Bits [31:0] (R/O)
811H 2065 IA32_X2APIC_ISR1 Thread x2APIC In-Service Register Bits [63:32] (R/O)
812H 2066 IA32_X2APIC_ISR2 Thread x2APIC In-Service Register Bits [95:64] (R/O)
813H 2067 IA32_X2APIC_ISR3 Thread x2APIC In-Service Register Bits [127:96] (R/O)
814H 2068 IA32_X2APIC_ISR4 Thread x2APIC In-Service Register Bits [159:128] (R/O)
815H 2069 IA32_X2APIC_ISR5 Thread x2APIC In-Service Register Bits [191:160] (R/O)
816H 2070 IA32_X2APIC_ISR6 Thread x2APIC In-Service Register Bits [223:192] (R/O)
817H 2071 IA32_X2APIC_ISR7 Thread x2APIC In-Service Register Bits [255:224] (R/O)
818H 2072 IA32_X2APIC_TMR0 Thread x2APIC Trigger Mode Register Bits [31:0] (R/O)
819H 2073 IA32_X2APIC_TMR1 Thread x2APIC Trigger Mode Register Bits [63:32] (R/O)
81AH 2074 IA32_X2APIC_TMR2 Thread x2APIC Trigger Mode Register Bits [95:64] (R/O)
2-338 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
81BH 2075 IA32_X2APIC_TMR3 Thread x2APIC Trigger Mode Register Bits [127:96] (R/O)
81CH 2076 IA32_X2APIC_TMR4 Thread x2APIC Trigger Mode Register Bits [159:128] (R/O)
81DH 2077 IA32_X2APIC_TMR5 Thread x2APIC Trigger Mode Register Bits [191:160] (R/O)
81EH 2078 IA32_X2APIC_TMR6 Thread x2APIC Trigger Mode Register Bits [223:192] (R/O)
81FH 2079 IA32_X2APIC_TMR7 Thread x2APIC Trigger Mode Register Bits [255:224] (R/O)
820H 2080 IA32_X2APIC_IRR0 Thread x2APIC Interrupt Request Register Bits [31:0] (R/O)
821H 2081 IA32_X2APIC_IRR1 Thread x2APIC Interrupt Request Register Bits [63:32] (R/O)
822H 2082 IA32_X2APIC_IRR2 Thread x2APIC Interrupt Request Register Bits [95:64] (R/O)
823H 2083 IA32_X2APIC_IRR3 Thread x2APIC Interrupt Request Register Bits [127:96] (R/O)
824H 2084 IA32_X2APIC_IRR4 Thread x2APIC Interrupt Request Register Bits [159:128] (R/O)
825H 2085 IA32_X2APIC_IRR5 Thread x2APIC Interrupt Request Register Bits [191:160] (R/O)
826H 2086 IA32_X2APIC_IRR6 Thread x2APIC Interrupt Request Register Bits [223:192] (R/O)
827H 2087 IA32_X2APIC_IRR7 Thread x2APIC Interrupt Request Register Bits [255:224] (R/O)
828H 2088 IA32_X2APIC_ESR Thread x2APIC Error Status Register (R/W)
82FH 2095 IA32_X2APIC_LVT_CMCI Thread x2APIC LVT Corrected Machine Check Interrupt Register
(R/W)
830H 2096 IA32_X2APIC_ICR Thread x2APIC Interrupt Command Register (R/W)
832H 2098 IA32_X2APIC_LVT_TIMER Thread x2APIC LVT Timer Interrupt Register (R/W)
833H 2099 IA32_X2APIC_LVT_THERMAL Thread x2APIC LVT Thermal Sensor Interrupt Register (R/W)
834H 2100 IA32_X2APIC_LVT_PMI Thread x2APIC LVT Performance Monitor Register (R/W)
835H 2101 IA32_X2APIC_LVT_LINT0 Thread x2APIC LVT LINT0 Register (R/W)
836H 2102 IA32_X2APIC_LVT_LINT1 Thread x2APIC LVT LINT1 Register (R/W)
837H 2103 IA32_X2APIC_LVT_ERROR Thread x2APIC LVT Error Register (R/W)
838H 2104 IA32_X2APIC_INIT_COUNT Thread x2APIC Initial Count Register (R/W)
839H 2105 IA32_X2APIC_CUR_COUNT Thread x2APIC Current Count Register (R/O)
83EH 2110 IA32_X2APIC_DIV_CONF Thread x2APIC Divide Configuration Register (R/W)
83FH 2111 IA32_X2APIC_SELF_IPI Thread x2APIC Self IPI Register (W/O)
C000_ IA32_EFER Thread Extended Feature Enables
0080H See Table 2-2.
C000_ IA32_STAR Thread System Call Target Address (R/W)
0081H See Table 2-2.
C000_ IA32_LSTAR Thread IA-32e Mode System Call Target Address (R/W)
0082H See Table 2-2.
C000_ IA32_FMASK Thread System Call Flag Mask (R/W)
0084H See Table 2-2.
C000_ IA32_FS_BASE Thread Map of BASE Address of FS (R/W)
0100H See Table 2-2.
Vol. 4 2-339
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-48. Selected MSRs Supported by Intel® Xeon Phi™ Processors with
DisplayFamily_DisplayModel Signatures 06_57H and 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
C000_ IA32_GS_BASE Thread Map of BASE Address of GS (R/W)
0101H See Table 2-2.
C000_ IA32_KERNEL_GS_BASE Thread Swap Target of BASE Address of GS (R/W)
0102H See Table 2-2.
C000_ IA32_TSC_AUX Thread AUXILIARY TSC Signature (R/W)
0103H See Table 2-2
Table 2-49 lists model-specific registers that are supported by Intel® Xeon Phi™ processor 7215, 7285, 7295 series
based on the Knights Mill microarchitecture.
Table 2-49. Additional MSRs Supported by Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
with DisplayFamily_DisplayModel Signature 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
9BH 155 IA32_SMM_MONITOR_CTL Core SMM Monitor Configuration (R/W)
This MSR is readable only if VMX is enabled, and
writeable only if VMX is enabled and in SMM mode, and is
used to configure the VMX MSEG base address. See
Table 2-2.
480H 1152 IA32_VMX_BASIC Core Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2.
481H 1153 IA32_VMX_PINBASED_ CTLS Core Capability Reporting Register of Pin-based VM-execution
Controls (R/O)
See Table 2-2.
482H 1154 IA32_VMX_PROCBASED_ CTLS Core Capability Reporting Register of Primary Processor-
based VM-execution Controls (R/O)
483H 1155 IA32_VMX_EXIT_CTLS Core Capability Reporting Register of VM-exit Controls (R/O)
See Table 2-2.
484H 1156 IA32_VMX_ENTRY_CTLS Core Capability Reporting Register of VM-entry Controls (R/O)
See Table 2-2.
485H 1157 IA32_VMX_MISC Core Reporting Register of Miscellaneous VMX Capabilities
(R/O)
See Table 2-2.
486H 1158 IA32_VMX_CR0_FIXED0 Core Capability Reporting Register of CR0 Bits Fixed to 0
(R/O)
See Table 2-2.
487H 1159 IA32_VMX_CR0_FIXED1 Core Capability Reporting Register of CR0 Bits Fixed to 1
(R/O)
See Table 2-2.
2-340 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-49. Additional MSRs Supported by Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
with DisplayFamily_DisplayModel Signature 06_85H
Register
Address Register Name / Bit Fields Scope Bit Description
Hex Dec
488H 1160 IA32_VMX_CR4_FIXED0 Core Capability Reporting Register of CR4 Bits Fixed to 0
(R/O)
See Table 2-2.
489H 1161 IA32_VMX_CR4_FIXED1 Core Capability Reporting Register of CR4 Bits Fixed to 1
(R/O)
See Table 2-2.
48AH 1162 IA32_VMX_VMCS_ENUM Core Capability Reporting Register of VMCS Field Enumeration
(R/O)
See Table 2-2.
48BH 1163 IA32_VMX_PROCBASED_ CTLS2 Core Capability Reporting Register of Secondary Processor-
Based VM-Execution Controls (R/O)
See Table 2-2.
48CH 1164 IA32_VMX_EPT_VPID_ENUM Core Capability Reporting Register of EPT and VPID (R/O)
See Table 2-2.
48DH 1165 IA32_VMX_TRUE_PINBASE D_CTLS Core Capability Reporting Register of Pin-Based VM-Execution
Flex Controls (R/O)
See Table 2-2.
48EH 1166 IA32_VMX_TRUE_PROCBASED_CTLS Core Capability Reporting Register of Primary Processor-
Based VM-Execution Flex Controls (R/O)
See Table 2-2.
48FH 1167 IA32_VMX_TRUE_EXIT_CTLS Core Capability Reporting Register of VM-Exit Flex Controls
(R/O)
See Table 2-2.
490H 1168 IA32_VMX_TRUE_ENTRY_CTLS Core Capability Reporting Register of VM-Entry Flex Controls
(R/O)
See Table 2-2.
491H 1169 IA32_VMX_FMFUNC Core Capability Reporting Register of VM-Function Controls
(R/O)
See Table 2-2.
Vol. 4 2-341
MODEL-SPECIFIC REGISTERS (MSRS)
2-342 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
3 MCERR# Observation Disabled (R)
Indicates whether MCERR# observation is
enabled (0) or disabled (1) as determined by the
strapping of A9#. The value in this bit is written
on the deassertion of RESET#; the bit is set to 1
when the address bus signal is asserted.
4 BINIT# Observation Enabled (R)
Indicates whether BINIT# observation is
enabled (0) or disabled (1) as determined by the
strapping of A10#. The value in this bit is
written on the deassertion of RESET#; the bit is
set to 1 when the address bus signal is
asserted.
6:5 APIC Cluster ID (R)
Contains the logical APIC cluster ID value as set
by the strapping of A12# and A11#. The logical
cluster ID value is written into the field on the
deassertion of RESET#; the field is set to 1
when the address bus signal is asserted.
7 Bus Park Disable (R)
Indicates whether bus park is enabled (0) or
disabled (1) as set by the strapping of A15#.
The value in this bit is written on the
deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
11:8 Reserved
13:12 Agent ID (R)
Contains the logical agent ID value as set by the
strapping of BR[3:0]. The logical ID value is
written into the field on the deassertion of
RESET#; the field is set to 1 when the address
bus signal is asserted.
63:14 Reserved
2BH 43 MSR_EBC_SOFT_POWERON 0, 1, 2, 3, Shared Processor Soft Power-On Configuration (R/W)
4, 6 Enables and disables processor features.
0 RCNT/SCNT On Request Encoding Enable (R/W)
Controls the driving of RCNT/SCNT on the
request encoding. Set to enable (1); clear to
disabled (0, default).
1 Data Error Checking Disable (R/W)
Set to disable system data bus parity checking;
clear to enable parity checking.
2 Response Error Checking Disable (R/W)
Set to disable (default); clear to enable.
3 Address/Request Error Checking Disable (R/W)
Set to disable (default); clear to enable.
Vol. 4 2-343
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
4 Initiator MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator bus
requests (default); clear to enable.
5 Internal MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator
internal errors (default); clear to enable.
6 BINIT# Driver Disable (R/W)
Set to disable BINIT# driver (default); clear to
enable driver.
63:7 Reserved
2CH 44 MSR_EBC_FREQUENCY_ID 2,3, 4, 6 Shared Processor Frequency Configuration
The bit field layout of this MSR varies according
to the MODEL value in the CPUID version
information. The following bit field layout
applies to Pentium 4 and Xeon Processors with
MODEL encoding equal or greater than 2.
(R) The field Indicates the current processor
frequency configuration.
15:0 Reserved
18:16 Scalable Bus Speed (R/W)
Indicates the intended scalable bus speed:
Encoding Scalable Bus Speed
000B 100 MHz (Model 2)
000B 266 MHz (Model 3 or 4)
001B 133 MHz
010B 200 MHz
011B 166 MHz
100B 333 MHz (Model 6)
2-344 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
31:24 Core Clock Frequency to System Bus Frequency
Ratio (R)
The processor core clock frequency to system
bus frequency ratio observed at the de-
assertion of the reset pin.
63:25 Reserved
2CH 44 MSR_EBC_FREQUENCY_ID 0, 1 Shared Processor Frequency Configuration (R)
The bit field layout of this MSR varies according
to the MODEL value of the CPUID version
information. This bit field layout applies to
Pentium 4 and Xeon Processors with MODEL
encoding less than 2.
Indicates current processor frequency
configuration.
20:0 Reserved
23:21 Scalable Bus Speed (R/W)
Indicates the intended scalable bus speed:
Encoding Scalable Bus Speed
000B 100 MHz
Vol. 4 2-345
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
176H 374 IA32_SYSENTER_EIP 0, 1, 2, 3, Unique CPL 0 Code Entry Point (R/W)
4, 6 See Table 2-2. See Section 5.8.7, “Performing
Fast Calls to System Procedures with the
SYSENTER and SYSEXIT Instructions.”
179H 377 IA32_MCG_CAP 0, 1, 2, 3, Unique Machine Check Capabilities (R)
4, 6 See Table 2-2. See Section 15.3.1.1,
“IA32_MCG_CAP MSR.”
17AH 378 IA32_MCG_STATUS 0, 1, 2, 3, Unique Machine Check Status (R)
4, 6 See Table 2-2. See Section 15.3.1.2,
“IA32_MCG_STATUS MSR.”
17BH 379 IA32_MCG_CTL Machine Check Feature Enable (R/W)
See Table 2-2.
See Section 15.3.1.3, “IA32_MCG_CTL MSR.”
180H 384 MSR_MCG_RAX 0, 1, 2, 3, Unique Machine Check EAX/RAX Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
181H 385 MSR_MCG_RBX 0, 1, 2, 3, Unique Machine Check EBX/RBX Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
182H 386 MSR_MCG_RCX 0, 1, 2, 3, Unique Machine Check ECX/RCX Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
183H 387 MSR_MCG_RDX 0, 1, 2, 3, Unique Machine Check EDX/RDX Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
184H 388 MSR_MCG_RSI 0, 1, 2, 3, Unique Machine Check ESI/RSI Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
2-346 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
185H 389 MSR_MCG_RDI 0, 1, 2, 3, Unique Machine Check EDI/RDI Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
186H 390 MSR_MCG_RBP 0, 1, 2, 3, Unique Machine Check EBP/RBP Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
187H 391 MSR_MCG_RSP 0, 1, 2, 3, Unique Machine Check ESP/RSP Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
188H 392 MSR_MCG_RFLAGS 0, 1, 2, 3, Unique Machine Check EFLAGS/RFLAG Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
189H 393 MSR_MCG_RIP 0, 1, 2, 3, Unique Machine Check EIP/RIP Save State
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Contains register state at time of machine check
error. When in non-64-bit modes at the time of
the error, bits 63-32 do not contain valid data.
18AH 394 MSR_MCG_MISC 0, 1, 2, 3, Unique Machine Check Miscellaneous
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
0 DS
When set, the bit indicates that a page assist or
page fault occurred during DS normal operation.
The processors response is to shut down.
The bit is used as an aid for debugging DS
handling code. It is the responsibility of the user
(BIOS or operating system) to clear this bit for
normal operation.
63:1 Reserved
18BH - 395- MSR_MCG_RESERVED1 - Reserved
18FH 399 MSR_MCG_RESERVED5
Vol. 4 2-347
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
190H 400 MSR_MCG_R8 0, 1, 2, 3, Unique Machine Check R8
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when
the processor is operating in 64-bit mode at the
time of the error.
191H 401 MSR_MCG_R9 0, 1, 2, 3, Unique Machine Check R9D/R9
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when
the processor is operating in 64-bit mode at the
time of the error.
192H 402 MSR_MCG_R10 0, 1, 2, 3, Unique Machine Check R10
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when
the processor is operating in 64-bit mode at the
time of the error.
193H 403 MSR_MCG_R11 0, 1, 2, 3, Unique Machine Check R11
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when
the processor is operating in 64-bit mode at the
time of the error.
194H 404 MSR_MCG_R12 0, 1, 2, 3, Unique Machine Check R12
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when
the processor is operating in 64-bit mode at the
time of the error.
195H 405 MSR_MCG_R13 0, 1, 2, 3, Unique Machine Check R13
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
2-348 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
63:0 Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when
the processor is operating in 64-bit mode at the
time of the error.
196H 406 MSR_MCG_R14 0, 1, 2, 3, Unique Machine Check R14
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when
the processor is operating in 64-bit mode at the
time of the error.
197H 407 MSR_MCG_R15 0, 1, 2, 3, Unique Machine Check R15
4, 6 See Section 15.3.2.6, “IA32_MCG Extended
Machine Check State MSRs.”
63:0 Registers R8-15 (and the associated state-save
MSRs) exist only in Intel 64 processors. These
registers contain valid information only when
the processor is operating in 64-bit mode at the
time of the error.
198H 408 IA32_PERF_STATUS 3, 4, 6 Unique See Table 2-2. See Section 14.1, “Enhanced
Intel Speedstep® Technology.”
199H 409 IA32_PERF_CTL 3, 4, 6 Unique See Table 2-2. See Section 14.1, “Enhanced
Intel Speedstep® Technology.”
19AH 410 IA32_CLOCK_MODULATION 0, 1, 2, 3, Unique Thermal Monitor Control (R/W)
4, 6 See Table 2-2.
See Section 14.8.3, “Software Controlled Clock
Modulation.”
19BH 411 IA32_THERM_INTERRUPT 0, 1, 2, 3, Unique Thermal Interrupt Control (R/W)
4, 6 See Section 14.8.2, “Thermal Monitor,” and see
Table 2-2.
19CH 412 IA32_THERM_STATUS 0, 1, 2, 3, Shared Thermal Monitor Status (R/W)
4, 6 See Section 14.8.2, “Thermal Monitor,” and see
Table 2-2.
19DH 413 MSR_THERM2_CTL Thermal Monitor 2 Control
3, Shared For Family F, Model 3 processors: When read,
specifies the value of the target TM2 transition
last written. When set, it sets the next target
value for TM2 transition.
4, 6 Shared For Family F, Model 4 and Model 6 processors:
When read, specifies the value of the target
TM2 transition last written. Writes may cause
#GP exceptions.
1A0H 416 IA32_MISC_ENABLE 0, 1, 2, 3, Shared Enable Miscellaneous Processor Features (R/W)
4, 6
Vol. 4 2-349
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
0 Fast-Strings Enable. See Table 2-2.
1 Reserved
2 x87 FPU Fopcode Compatibility Mode Enable
3 Thermal Monitor 1 Enable
See Section 14.8.2, “Thermal Monitor,” and see
Table 2-2.
4 Split-Lock Disable
When set, the bit causes an #AC exception to be
issued instead of a split-lock cycle. Operating
systems that set this bit must align system
structures to avoid split-lock scenarios.
When the bit is clear (default), normal split-locks
are issued to the bus.
This debug feature is specific to the Pentium 4
processor.
5 Reserved
6 Third-Level Cache Disable (R/W)
When set, the third-level cache is disabled;
when clear (default) the third-level cache is
enabled. This flag is reserved for processors
that do not have a third-level cache.
Note that the bit controls only the third-level
cache; and only if overall caching is enabled
through the CD flag of control register CR0, the
page-level cache controls, and/or the MTRRs.
See Section 11.5.4, “Disabling and Enabling the
L3 Cache.”
7 Performance Monitoring Available (R)
See Table 2-2.
8 Suppress Lock Enable
When set, assertion of LOCK on the bus is
suppressed during a Split Lock access. When
clear (default), LOCK is not suppressed.
9 Prefetch Queue Disable
When set, disables the prefetch queue. When
clear (default), enables the prefetch queue.
10 FERR# Interrupt Reporting Enable (R/W)
When set, interrupt reporting through the
FERR# pin is enabled; when clear, this interrupt
reporting function is disabled.
2-350 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
When this flag is set and the processor is in the
stop-clock state (STPCLK# is asserted),
asserting the FERR# pin signals to the
processor that an interrupt (such as, INIT#,
BINIT#, INTR, NMI, SMI#, or RESET#) is pending
and that the processor should return to normal
operation to handle the interrupt.
This flag does not affect the normal operation
of the FERR# pin (to indicate an unmasked
floating-point error) when the STPCLK# pin is
not asserted.
11 Branch Trace Storage Unavailable
(BTS_UNAVILABLE) (R)
See Table 2-2.
When set, the processor does not support
branch trace storage (BTS); when clear, BTS is
supported.
12 PEBS_UNAVILABLE: Processor Event Based
Sampling Unavailable (R)
See Table 2-2.
When set, the processor does not support
processor event-based sampling (PEBS); when
clear, PEBS is supported.
13 3 TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor
indicates that the die temperature is at the pre-
determined threshold, the Thermal Monitor 2
mechanism is engaged. TM2 will reduce the bus
to core ratio and voltage according to the value
last written to MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor
does not change the VID signals or the bus to
core ratio when the processor enters a thermal
managed state.
If the TM2 feature flag (ECX[8]) is not set to 1
after executing CPUID with EAX = 1, then this
feature is not supported and BIOS must not
alter the contents of this bit location. The
processor is operating out of spec if both this
bit and the TM1 bit are set to disabled states.
17:14 Reserved
18 3, 4, 6 ENABLE MONITOR FSM (R/W)
See Table 2-2.
Vol. 4 2-351
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
19 Adjacent Cache Line Prefetch Disable (R/W)
When set to 1, the processor fetches the cache
line of the 128-byte sector containing currently
required data. When set to 0, the processor
fetches both cache lines in the sector.
Single processor platforms should not set this
bit. Server platforms should set or clear this bit
based on platform performance observed in
validation and testing.
BIOS may contain a setup option that controls
the setting of this bit.
21:20 Reserved
22 3, 4, 6 Limit CPUID MAXVAL (R/W)
See Table 2-2.
Setting this can cause unexpected behavior to
software that depends on the availability of
CPUID leaves greater than 3.
23 Shared xTPR Message Disable (R/W)
See Table 2-2.
24 L1 Data Cache Context Mode (R/W)
When set, the L1 data cache is placed in shared
mode; when clear (default), the cache is placed
in adaptive mode. This bit is only enabled for IA-
32 processors that support Intel Hyper-
Threading Technology. See Section 11.5.6, “L1
Data Cache Context Mode.”
When L1 is running in adaptive mode and CR3s
are identical, data in L1 is shared across logical
processors. Otherwise, L1 is not shared and
cache use is competitive.
If the Context ID feature flag (ECX[10]) is set to
0 after executing CPUID with EAX = 1, the
ability to switch modes is not supported. BIOS
must not alter the contents of
IA32_MISC_ENABLE[24].
33:25 Reserved
34 Unique XD Bit Disable (R/W)
See Table 2-2.
63:35 Reserved
1A1H 417 MSR_PLATFORM_BRV 3, 4, 6 Shared Platform Feature Requirements (R)
17:0 Reserved
2-352 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
18 PLATFORM Requirements
When set to 1, indicates the processor has
specific platform requirements. The details of
the platform requirements are listed in the
respective data sheets of the processor.
63:19 Reserved
1D7H 471 MSR_LER_FROM_LIP 0, 1, 2, 3, Unique Last Exception Record From Linear IP (R)
4, 6 Contains a pointer to the last branch instruction
that the processor executed prior to the last
exception that was generated or the last
interrupt that was handled.
See Section 17.13.3, “Last Exception Records.”
31:0 From Linear IP
Linear address of the last branch instruction.
63:32 Reserved
1D7H 471 63:0 Unique From Linear IP
Linear address of the last branch instruction (If
IA-32e mode is active).
1D8H 472 MSR_LER_TO_LIP 0, 1, 2, 3, Unique Last Exception Record To Linear IP (R)
4, 6 This area contains a pointer to the target of the
last branch instruction that the processor
executed prior to the last exception that was
generated or the last interrupt that was
handled.
See Section 17.13.3, “Last Exception Records.”
31:0 From Linear IP
Linear address of the target of the last branch
instruction.
63:32 Reserved
1D8H 472 63:0 Unique From Linear IP
Linear address of the target of the last branch
instruction (If IA-32e mode is active).
1D9H 473 MSR_DEBUGCTLA 0, 1, 2, 3, Unique Debug Control (R/W)
4, 6 Controls how several debug features are used.
Bit definitions are discussed in the referenced
section.
See Section 17.13.1, “MSR_DEBUGCTLA MSR.”
1DAH 474 MSR_LASTBRANCH_TOS 0, 1, 2, 3, Unique Last Branch Record Stack TOS (R/O)
4, 6 Contains an index (0-3 or 0-15) that points to
the top of the last branch record stack (that is,
that points the index of the MSR containing the
most recent branch record).
See Section 17.13.2, “LBR Stack for Processors
Based on Intel NetBurst® Microarchitecture”;
and addresses 1DBH-1DEH and 680H-68FH.
Vol. 4 2-353
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
1DBH 475 MSR_LASTBRANCH_0 0, 1, 2 Unique Last Branch Record 0 (R/O)
One of four last branch record registers on the
last branch record stack. It contains pointers to
the source and destination instruction for one
of the last four branches, exceptions, or
interrupts that the processor took.
MSR_LASTBRANCH_0 through
MSR_LASTBRANCH_3 at 1DBH-1DEH are
available only on family 0FH, models 0H-02H.
They have been replaced by the MSRs at 680H-
68FH and 6C0H-6CFH.
See Section 17.12, “Last Branch, Call Stack,
Interrupt, and Exception Recording for
Processors based on Skylake Microarchitecture.”
1DCH 477 MSR_LASTBRANCH_1 0, 1, 2 Unique Last Branch Record 1
See description of the MSR_LASTBRANCH_0
MSR at 1DBH.
1DDH 477 MSR_LASTBRANCH_2 0, 1, 2 Unique Last Branch Record 2
See description of the MSR_LASTBRANCH_0
MSR at 1DBH.
1DEH 478 MSR_LASTBRANCH_3 0, 1, 2 Unique Last Branch Record 3
See description of the MSR_LASTBRANCH_0
MSR at 1DBH.
200H 512 IA32_MTRR_PHYSBASE0 0, 1, 2, 3, Shared Variable Range Base MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
201H 513 IA32_MTRR_PHYSMASK0 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
202H 514 IA32_MTRR_PHYSBASE1 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
203H 515 IA32_MTRR_PHYSMASK1 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
204H 516 IA32_MTRR_PHYSBASE2 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
205H 517 IA32_MTRR_PHYSMASK2 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs”.
206H 518 IA32_MTRR_PHYSBASE3 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
207H 519 IA32_MTRR_PHYSMASK3 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
208H 520 IA32_MTRR_PHYSBASE4 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
209H 521 IA32_MTRR_PHYSMASK4 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
2-354 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
20AH 522 IA32_MTRR_PHYSBASE5 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
20BH 523 IA32_MTRR_PHYSMASK5 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
20CH 524 IA32_MTRR_PHYSBASE6 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
20DH 525 IA32_MTRR_PHYSMASK6 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
20EH 526 IA32_MTRR_PHYSBASE7 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
20FH 527 IA32_MTRR_PHYSMASK7 0, 1, 2, 3, Shared Variable Range Mask MTRR
4, 6 See Section 11.11.2.3, “Variable Range MTRRs.”
250H 592 IA32_MTRR_FIX64K_00000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
258H 600 IA32_MTRR_FIX16K_80000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
259H 601 IA32_MTRR_FIX16K_A0000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
268H 616 IA32_MTRR_FIX4K_C0000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
269H 617 IA32_MTRR_FIX4K_C8000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs”.
26AH 618 IA32_MTRR_FIX4K_D0000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs”.
26BH 619 IA32_MTRR_FIX4K_D8000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
26CH 620 IA32_MTRR_FIX4K_E0000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
26DH 621 IA32_MTRR_FIX4K_E8000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
26EH 622 IA32_MTRR_FIX4K_F0000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
26FH 623 IA32_MTRR_FIX4K_F8000 0, 1, 2, 3, Shared Fixed Range MTRR
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
277H 631 IA32_PAT 0, 1, 2, 3, Unique Page Attribute Table
4, 6 See Section 11.11.2.2, “Fixed Range MTRRs.”
2FFH 767 IA32_MTRR_DEF_TYPE 0, 1, 2, 3, Shared Default Memory Types (R/W)
4, 6 See Table 2-2.
See Section 11.11.2.1, “IA32_MTRR_DEF_TYPE
MSR.”
Vol. 4 2-355
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
300H 768 MSR_BPU_COUNTER0 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
301H 769 MSR_BPU_COUNTER1 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
302H 770 MSR_BPU_COUNTER2 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
303H 771 MSR_BPU_COUNTER3 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
304H 772 MSR_MS_COUNTER0 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
305H 773 MSR_MS_COUNTER1 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
306H 774 MSR_MS_COUNTER2 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
307H 775 MSR_MS_COUNTER3 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
308H 776 MSR_FLAME_COUNTER0 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
309H 777 MSR_FLAME_COUNTER1 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
30AH 778 MSR_FLAME_COUNTER2 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
30BH 779 MSR_FLAME_COUNTER3 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
30CH 780 MSR_IQ_COUNTER0 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
30DH 781 MSR_IQ_COUNTER1 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
30EH 782 MSR_IQ_COUNTER2 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
30FH 783 MSR_IQ_COUNTER3 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
310H 784 MSR_IQ_COUNTER4 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
311H 785 MSR_IQ_COUNTER5 0, 1, 2, 3, Shared See Section 18.6.3.2, “Performance Counters.”
4, 6
360H 864 MSR_BPU_CCCR0 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
361H 865 MSR_BPU_CCCR1 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
362H 866 MSR_BPU_CCCR2 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
363H 867 MSR_BPU_CCCR3 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
2-356 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
364H 868 MSR_MS_CCCR0 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
365H 869 MSR_MS_CCCR1 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
366H 870 MSR_MS_CCCR2 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
367H 871 MSR_MS_CCCR3 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
368H 872 MSR_FLAME_CCCR0 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
369H 873 MSR_FLAME_CCCR1 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
36AH 874 MSR_FLAME_CCCR2 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
36BH 875 MSR_FLAME_CCCR3 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
36CH 876 MSR_IQ_CCCR0 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
36DH 877 MSR_IQ_CCCR1 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
36EH 878 MSR_IQ_CCCR2 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
36FH 879 MSR_IQ_CCCR3 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
370H 880 MSR_IQ_CCCR4 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
371H 881 MSR_IQ_CCCR5 0, 1, 2, 3, Shared See Section 18.6.3.3, “CCCR MSRs.”
4, 6
3A0H 928 MSR_BSU_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3A1H 929 MSR_BSU_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3A2H 930 MSR_FSB_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3A3H 931 MSR_FSB_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3A4H 932 MSR_FIRM_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3A5H 933 MSR_FIRM_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3A6H 934 MSR_FLAME_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3A7H 935 MSR_FLAME_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
Vol. 4 2-357
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
3A8H 936 MSR_DAC_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3A9H 937 MSR_DAC_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3AAH 938 MSR_MOB_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3ABH 939 MSR_MOB_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3ACH 940 MSR_PMH_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3ADH 941 MSR_PMH_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3AEH 942 MSR_SAAT_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3AFH 943 MSR_SAAT_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B0H 944 MSR_U2L_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B1H 945 MSR_U2L_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B2H 946 MSR_BPU_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B3H 947 MSR_BPU_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B4H 948 MSR_IS_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B5H 949 MSR_IS_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B6H 950 MSR_ITLB_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B7H 951 MSR_ITLB_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B8H 952 MSR_CRU_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3B9H 953 MSR_CRU_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3BAH 954 MSR_IQ_ESCR0 0, 1, 2 Shared See Section 18.6.3.1, “ESCR MSRs.”
This MSR is not available on later processors. It
is only available on processor family 0FH,
models 01H-02H.
3BBH 955 MSR_IQ_ESCR1 0, 1, 2 Shared See Section 18.6.3.1, “ESCR MSRs.”
This MSR is not available on later processors. It
is only available on processor family 0FH,
models 01H-02H.
2-358 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
3BCH 956 MSR_RAT_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3BDH 957 MSR_RAT_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3BEH 958 MSR_SSU_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3C0H 960 MSR_MS_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3C1H 961 MSR_MS_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3C2H 962 MSR_TBPU_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3C3H 963 MSR_TBPU_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3C4H 964 MSR_TC_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3C5H 965 MSR_TC_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3C8H 968 MSR_IX_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3C9H 969 MSR_IX_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3CAH 970 MSR_ALF_ESCR0 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3CBH 971 MSR_ALF_ESCR1 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3CCH 972 MSR_CRU_ESCR2 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3CDH 973 MSR_CRU_ESCR3 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3E0H 992 MSR_CRU_ESCR4 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3E1H 993 MSR_CRU_ESCR5 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3F0H 1008 MSR_TC_PRECISE_EVENT 0, 1, 2, 3, Shared See Section 18.6.3.1, “ESCR MSRs.”
4, 6
3F1H 1009 MSR_PEBS_ENABLE 0, 1, 2, 3, Shared Processor Event Based Sampling (PEBS) (R/W)
4, 6 Controls the enabling of processor event
sampling and replay tagging.
12:0 See https://perfmon-events.intel.com/.
23:13 Reserved
24 UOP Tag
Enables replay tagging when set.
Vol. 4 2-359
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
25 ENABLE_PEBS_MY_THR (R/W)
Enables PEBS for the target logical processor
when set; disables PEBS when clear (default).
See Section 18.6.4.3, “IA32_PEBS_ENABLE
MSR,” for an explanation of the target logical
processor.
This bit is called ENABLE_PEBS in IA-32
processors that do not support Intel Hyper-
Threading Technology.
26 ENABLE_PEBS_OTH_THR (R/W)
Enables PEBS for the target logical processor
when set; disables PEBS when clear (default).
See Section 18.6.4.3, “IA32_PEBS_ENABLE
MSR,” for an explanation of the target logical
processor.
This bit is reserved for IA-32 processors that do
not support Intel Hyper-Threading Technology.
63:27 Reserved
3F2H 1010 MSR_PEBS_MATRIX_VERT 0, 1, 2, 3, Shared See https://perfmon-events.intel.com/.
4, 6
400H 1024 IA32_MC0_CTL 0, 1, 2, 3, Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
4, 6
401H 1025 IA32_MC0_STATUS 0, 1, 2, 3, Shared See Section 15.3.2.2, “IA32_MCi_STATUS
4, 6 MSRS.”
402H 1026 IA32_MC0_ADDR 0, 1, 2, 3, Shared See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
4, 6 The IA32_MC0_ADDR register is either not
implemented or contains no address if the
ADDRV flag in the IA32_MC0_STATUS register
is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
403H 1027 IA32_MC0_MISC 0, 1, 2, 3, Shared See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
4, 6 The IA32_MC0_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC0_STATUS register is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
404H 1028 IA32_MC1_CTL 0, 1, 2, 3, Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
4, 6
405H 1029 IA32_MC1_STATUS 0, 1, 2, 3, Shared See Section 15.3.2.2, “IA32_MCi_STATUS
4, 6 MSRS.”
2-360 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
406H 1030 IA32_MC1_ADDR 0, 1, 2, 3, Shared See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
4, 6 The IA32_MC1_ADDR register is either not
implemented or contains no address if the
ADDRV flag in the IA32_MC1_STATUS register
is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
407H 1031 IA32_MC1_MISC Shared See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC1_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC1_STATUS register is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
408H 1032 IA32_MC2_CTL 0, 1, 2, 3, Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
4, 6
409H 1033 IA32_MC2_STATUS 0, 1, 2, 3, Shared See Section 15.3.2.2, “IA32_MCi_STATUS
4, 6 MSRS.”
40AH 1034 IA32_MC2_ADDR See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the
ADDRV flag in the IA32_MC2_STATUS register
is clear. When not implemented in the processor,
all reads and writes to this MSR will cause a
general-protection exception.
40BH 1035 IA32_MC2_MISC See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC2_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC2_STATUS register is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
40CH 1036 IA32_MC3_CTL 0, 1, 2, 3, Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
4, 6
40DH 1037 IA32_MC3_STATUS 0, 1, 2, 3, Shared See Section 15.3.2.2, “IA32_MCi_STATUS
4, 6 MSRS.”
40EH 1038 IA32_MC3_ADDR 0, 1, 2, 3, Shared See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
4, 6 The IA32_MC3_ADDR register is either not
implemented or contains no address if the
ADDRV flag in the IA32_MC3_STATUS register
is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
Vol. 4 2-361
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
40FH 1039 IA32_MC3_MISC 0, 1, 2, 3, Shared See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
4, 6 The IA32_MC3_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC3_STATUS register is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
410H 1040 IA32_MC4_CTL 0, 1, 2, 3, Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
4, 6
411H 1041 IA32_MC4_STATUS 0, 1, 2, 3, Shared See Section 15.3.2.2, “IA32_MCi_STATUS
4, 6 MSRS.”
412H 1042 IA32_MC4_ADDR See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the
ADDRV flag in the IA32_MC4_STATUS register
is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
413H 1043 IA32_MC4_MISC See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC2_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC4_STATUS register is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
480H 1152 IA32_VMX_BASIC 3, 4, 6 Unique Reporting Register of Basic VMX Capabilities
(R/O)
See Table 2-2.
See Appendix A.1, “Basic VMX Information.”
481H 1153 IA32_VMX_PINBASED_CTLS 3, 4, 6 Unique Capability Reporting Register of Pin-Based
VM-Execution Controls (R/O)
See Table 2-2.
See Appendix A.3, “VM-Execution Controls.”
482H 1154 IA32_VMX_PROCBASED_CTLS 3, 4, 6 Unique Capability Reporting Register of Primary
Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls,” and
see Table 2-2.
483H 1155 IA32_VMX_EXIT_CTLS 3, 4, 6 Unique Capability Reporting Register of VM-Exit
Controls (R/O)
See Appendix A.4, “VM-Exit Controls,” and see
Table 2-2.
2-362 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
484H 1156 IA32_VMX_ENTRY_CTLS 3, 4, 6 Unique Capability Reporting Register of VM-Entry
Controls (R/O)
See Appendix A.5, “VM-Entry Controls,” and see
Table 2-2.
485H 1157 IA32_VMX_MISC 3, 4, 6 Unique Reporting Register of Miscellaneous VMX
Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data,” and see
Table 2-2.
486H 1158 IA32_VMX_CR0_FIXED0 3, 4, 6 Unique Capability Reporting Register of CR0 Bits Fixed
to 0 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0,” and
see Table 2-2.
487H 1159 IA32_VMX_CR0_FIXED1 3, 4, 6 Unique Capability Reporting Register of CR0 Bits Fixed
to 1 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0,” and
see Table 2-2.
488H 1160 IA32_VMX_CR4_FIXED0 3, 4, 6 Unique Capability Reporting Register of CR4 Bits Fixed
to 0 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4,” and
see Table 2-2.
489H 1161 IA32_VMX_CR4_FIXED1 3, 4, 6 Unique Capability Reporting Register of CR4 Bits Fixed
to 1 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4,” and
see Table 2-2.
48AH 1162 IA32_VMX_VMCS_ENUM 3, 4, 6 Unique Capability Reporting Register of VMCS Field
Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration,” and see
Table 2-2.
48BH 1163 IA32_VMX_PROCBASED_CTLS2 3, 4, 6 Unique Capability Reporting Register of Secondary
Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls,” and
see Table 2-2.
600H 1536 IA32_DS_AREA 0, 1, 2, 3, Unique DS Save Area (R/W)
4, 6 See Table 2-2.
See Section 18.6.3.4, “Debug Store (DS)
Mechanism.”
680H 1664 MSR_LASTBRANCH_0_FROM_IP 3, 4, 6 Unique Last Branch Record 0 (R/W)
One of 16 pairs of last branch record registers
on the last branch record stack (680H-68FH).
This part of the stack contains pointers to the
source instruction for one of the last 16
branches, exceptions, or interrupts taken by the
processor.
Vol. 4 2-363
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
The MSRs at 680H-68FH, 6C0H-6CfH are not
available in processor releases before family
0FH, model 03H. These MSRs replace MSRs
previously located at 1DBH-1DEH.which
performed the same function for early releases.
See Section 17.12, “Last Branch, Call Stack,
Interrupt, and Exception Recording for
Processors based on Skylake Microarchitecture.”
681H 1665 MSR_LASTBRANCH_1_FROM_IP 3, 4, 6 Unique Last Branch Record 1
See description of MSR_LASTBRANCH_0 at
680H.
682H 1666 MSR_LASTBRANCH_2_FROM_IP 3, 4, 6 Unique Last Branch Record 2
See description of MSR_LASTBRANCH_0 at
680H.
683H 1667 MSR_LASTBRANCH_3_FROM_IP 3, 4, 6 Unique Last Branch Record 3
See description of MSR_LASTBRANCH_0 at
680H.
684H 1668 MSR_LASTBRANCH_4_FROM_IP 3, 4, 6 Unique Last Branch Record 4
See description of MSR_LASTBRANCH_0 at
680H.
685H 1669 MSR_LASTBRANCH_5_FROM_IP 3, 4, 6 Unique Last Branch Record 5
See description of MSR_LASTBRANCH_0 at
680H.
686H 1670 MSR_LASTBRANCH_6_FROM_IP 3, 4, 6 Unique Last Branch Record 6
See description of MSR_LASTBRANCH_0 at
680H.
687H 1671 MSR_LASTBRANCH_7_FROM_IP 3, 4, 6 Unique Last Branch Record 7
See description of MSR_LASTBRANCH_0 at
680H.
688H 1672 MSR_LASTBRANCH_8_FROM_IP 3, 4, 6 Unique Last Branch Record 8
See description of MSR_LASTBRANCH_0 at
680H.
689H 1673 MSR_LASTBRANCH_9_FROM_IP 3, 4, 6 Unique Last Branch Record 9
See description of MSR_LASTBRANCH_0 at
680H.
68AH 1674 MSR_LASTBRANCH_10_FROM_IP 3, 4, 6 Unique Last Branch Record 10
See description of MSR_LASTBRANCH_0 at
680H.
68BH 1675 MSR_LASTBRANCH_11_FROM_IP 3, 4, 6 Unique Last Branch Record 11
See description of MSR_LASTBRANCH_0 at
680H.
68CH 1676 MSR_LASTBRANCH_12_FROM_IP 3, 4, 6 Unique Last Branch Record 12
See description of MSR_LASTBRANCH_0 at
680H.
2-364 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
68DH 1677 MSR_LASTBRANCH_13_FROM_IP 3, 4, 6 Unique Last Branch Record 13
See description of MSR_LASTBRANCH_0 at
680H.
68EH 1678 MSR_LASTBRANCH_14_FROM_IP 3, 4, 6 Unique Last Branch Record 14
See description of MSR_LASTBRANCH_0 at
680H.
68FH 1679 MSR_LASTBRANCH_15_FROM_IP 3, 4, 6 Unique Last Branch Record 15
See description of MSR_LASTBRANCH_0 at
680H.
6C0H 1728 MSR_LASTBRANCH_0_TO_IP 3, 4, 6 Unique Last Branch Record 0 (R/W)
One of 16 pairs of last branch record registers
on the last branch record stack (6C0H-6CFH).
This part of the stack contains pointers to the
destination instruction for one of the last 16
branches, exceptions, or interrupts that the
processor took.
See Section 17.12, “Last Branch, Call Stack,
Interrupt, and Exception Recording for
Processors based on Skylake Microarchitecture.”
6C1H 1729 MSR_LASTBRANCH_1_TO_IP 3, 4, 6 Unique Last Branch Record 1
See description of MSR_LASTBRANCH_0 at
6C0H.
6C2H 1730 MSR_LASTBRANCH_2_TO_IP 3, 4, 6 Unique Last Branch Record 2
See description of MSR_LASTBRANCH_0 at
6C0H.
6C3H 1731 MSR_LASTBRANCH_3_TO_IP 3, 4, 6 Unique Last Branch Record 3
See description of MSR_LASTBRANCH_0 at
6C0H.
6C4H 1732 MSR_LASTBRANCH_4_TO_IP 3, 4, 6 Unique Last Branch Record 4
See description of MSR_LASTBRANCH_0 at
6C0H.
6C5H 1733 MSR_LASTBRANCH_5_TO_IP 3, 4, 6 Unique Last Branch Record 5
See description of MSR_LASTBRANCH_0 at
6C0H.
6C6H 1734 MSR_LASTBRANCH_6_TO_IP 3, 4, 6 Unique Last Branch Record 6
See description of MSR_LASTBRANCH_0 at
6C0H.
6C7H 1735 MSR_LASTBRANCH_7_TO_IP 3, 4, 6 Unique Last Branch Record 7
See description of MSR_LASTBRANCH_0 at
6C0H.
6C8H 1736 MSR_LASTBRANCH_8_TO_IP 3, 4, 6 Unique Last Branch Record 8
See description of MSR_LASTBRANCH_0 at
6C0H.
Vol. 4 2-365
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Register Name Model Shared/
Address Fields and Flags Avail- Unique1 Bit Description
ability
Hex Dec
6C9H 1737 MSR_LASTBRANCH_9_TO_IP 3, 4, 6 Unique Last Branch Record 9
See description of MSR_LASTBRANCH_0 at
6C0H.
6CAH 1738 MSR_LASTBRANCH_10_TO_IP 3, 4, 6 Unique Last Branch Record 10
See description of MSR_LASTBRANCH_0 at
6C0H.
6CBH 1739 MSR_LASTBRANCH_11_TO_IP 3, 4, 6 Unique Last Branch Record 11
See description of MSR_LASTBRANCH_0 at
6C0H.
6CCH 1740 MSR_LASTBRANCH_12_TO_IP 3, 4, 6 Unique Last Branch Record 12
See description of MSR_LASTBRANCH_0 at
6C0H.
6CDH 1741 MSR_LASTBRANCH_13_TO_IP 3, 4, 6 Unique Last Branch Record 13
See description of MSR_LASTBRANCH_0 at
6C0H.
6CEH 1742 MSR_LASTBRANCH_14_TO_IP 3, 4, 6 Unique Last Branch Record 14
See description of MSR_LASTBRANCH_0 at
6C0H.
6CFH 1743 MSR_LASTBRANCH_15_TO_IP 3, 4, 6 Unique Last Branch Record 15
See description of MSR_LASTBRANCH_0 at
6C0H.
C000_ IA32_EFER 3, 4, 6 Unique Extended Feature Enables
0080H See Table 2-2.
C000_ IA32_STAR 3, 4, 6 Unique System Call Target Address (R/W)
0081H See Table 2-2.
C000_ IA32_LSTAR 3, 4, 6 Unique IA-32e Mode System Call Target Address (R/W)
0082H See Table 2-2.
C000_ IA32_FMASK 3, 4, 6 Unique System Call Flag Mask (R/W)
0084H See Table 2-2.
C000_ IA32_FS_BASE 3, 4, 6 Unique Map of BASE Address of FS (R/W)
0100H See Table 2-2.
C000_ IA32_GS_BASE 3, 4, 6 Unique Map of BASE Address of GS (R/W)
0101H See Table 2-2.
C000_ IA32_KERNEL_GS_BASE 3, 4, 6 Unique Swap Target of BASE Address of GS (R/W)
0102H See Table 2-2.
NOTES
1. For HT-enabled processors, there may be more than one logical processors per physical unit. If an MSR is Shared, this means that
one MSR is shared between logical processors. If an MSR is unique, this means that each logical processor has its own MSR.
2-366 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
107CCH MSR_IFSB_BUSQ0 3, 4 Shared IFSB BUSQ Event Control and Counter Register (R/W)
See Section 18.6.6, “Performance Monitoring on 64-
bit Intel Xeon Processor MP with Up to 8-MByte L3
Cache.”
107CDH MSR_IFSB_BUSQ1 3, 4 Shared IFSB BUSQ Event Control and Counter Register (R/W)
107CEH MSR_IFSB_SNPQ0 3, 4 Shared IFSB SNPQ Event Control and Counter Register (R/W)
See Section 18.6.6, “Performance Monitoring on 64-
bit Intel Xeon Processor MP with Up to 8-MByte L3
Cache.”
107CFH MSR_IFSB_SNPQ1 3, 4 Shared IFSB SNPQ Event Control and Counter Register (R/W)
107D0H MSR_EFSB_DRDY0 3, 4 Shared EFSB DRDY Event Control and Counter Register (R/W)
See Section 18.6.6, “Performance Monitoring on 64-
bit Intel Xeon Processor MP with Up to 8-MByte L3
Cache.”
107D1H MSR_EFSB_DRDY1 3, 4 Shared EFSB DRDY Event Control and Counter Register (R/W)
107D2H MSR_IFSB_CTL6 3, 4 Shared IFSB Latency Event Control Register (R/W)
See Section 18.6.6, “Performance Monitoring on 64-
bit Intel Xeon Processor MP with Up to 8-MByte L3
Cache.”
107D3H MSR_IFSB_CNTR7 3, 4 Shared IFSB Latency Event Counter Register (R/W)
See Section 18.6.6, “Performance Monitoring on 64-
bit Intel Xeon Processor MP with Up to 8-MByte L3
Cache.”
The MSRs listed in Table 2-52 apply to Intel® Xeon® Processor 7100 series. These processors can be detected by
enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX = 4 as input) to detect the
presence of the third level cache, and with CPUID reporting family encoding 0FH, model encoding 6 (See CPUID
instruction for more details.). The performance monitoring MSRs listed in Table 2-52 are shared between logical
processors in the same core, but are replicated for each core.
Vol. 4 2-367
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. MSRs Unique to Intel® Xeon® Processor 7100 Series (Contd.)
Register Name Model Avail- Shared/
Fields and Flags ability Unique Bit Description
Register Address
107CDH MSR_EMON_L3_CTR_CTL1 6 Shared GBUSQ Event Control and Counter Register (R/W)
107CEH MSR_EMON_L3_CTR_CTL2 6 Shared GSNPQ Event Control and Counter Register (R/W)
See Section 18.6.6, “Performance Monitoring on
64-bit Intel Xeon Processor MP with Up to 8-
MByte L3 Cache.”
107CFH MSR_EMON_L3_CTR_CTL3 6 Shared GSNPQ Event Control and Counter Register (R/W)
107D0H MSR_EMON_L3_CTR_CTL4 6 Shared FSB Event Control and Counter Register (R/W)
See Section 18.6.6, “Performance Monitoring on
64-bit Intel Xeon Processor MP with Up to 8-
MByte L3 Cache.”
107D1H MSR_EMON_L3_CTR_CTL5 6 Shared FSB Event Control and Counter Register (R/W)
107D2H MSR_EMON_L3_CTR_CTL6 6 Shared FSB Event Control and Counter Register (R/W)
107D3H MSR_EMON_L3_CTR_CTL7 6 Shared FSB Event Control and Counter Register (R/W)
2.20 MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS
Model-specific registers (MSRs) for Intel Core Solo, Intel Core Duo processors, and Dual-core Intel Xeon processor
LV are listed in Table 2-53. The column “Shared/Unique” applies to Intel Core Duo processor. “Unique” means each
processor core has a separate MSR, or a bit field in an MSR governs only a core independently. “Shared” means the
MSR or the bit field in an MSR address governs the operation of both processor cores.
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
0H 0 P5_MC_ADDR Unique See Section 2.23, “MSRs in Pentium Processors,” and see
Table 2-2.
1H 1 P5_MC_TYPE Unique See Section 2.23, “MSRs in Pentium Processors,” and see
Table 2-2.
6H 6 IA32_MONITOR_FILTER_SIZE Unique See Section 8.10.5, “Monitor/Mwait Address Range
Determination,” and see Table 2-2.
10H 16 IA32_TIME_STAMP_COUNTER Unique See Section 17.17, “Time-Stamp Counter,” and see Table 2-2.
17H 23 IA32_PLATFORM_ID Shared Platform ID (R)
See Table 2-2.
The operating system can use this MSR to determine “slot”
information for the processor and the proper microcode
update to load.
1BH 27 IA32_APIC_BASE Unique See Section 10.4.4, “Local APIC Status and Location,” and see
Table 2-2.
2-368 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
2AH 42 MSR_EBL_CR_POWERON Shared Processor Hard Power-On Configuration (R/W)
Enables and disables processor features; (R) indicates current
processor configuration.
0 Reserved
1 Data Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
2 Response Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
3 MCERR# Drive Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
4 Address Parity Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
6: 5 Reserved
7 BINIT# Driver Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W.
8 Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled
9 Execute BIST (R/O)
1 = Enabled; 0 = Disabled
10 MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
11 Reserved
12 BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
13 Reserved
14 1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes
15 Reserved
17:16 APIC Cluster ID (R/O)
18 System Bus Frequency (R/O)
0 = 100 MHz
1 = Reserved
19 Reserved
21: 20 Symmetric Arbitration ID (R/O)
26:22 Clock Frequency Ratio (R/O)
Vol. 4 2-369
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
3AH 58 IA32_FEATURE_CONTROL Unique Control Features in IA-32 Processor (R/W)
See Table 2-2.
40H 64 MSR_LASTBRANCH_0 Unique Last Branch Record 0 (R/W)
One of 8 last branch record registers on the last branch record
stack: bits 31-0 hold the ‘from’ address and bits 63-32 hold
the ‘to’ address. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 17.15, “Last Branch, Interrupt, and Exception
Recording (Pentium M Processors).”
41H 65 MSR_LASTBRANCH_1 Unique Last Branch Record 1 (R/W)
See description of MSR_LASTBRANCH_0.
42H 66 MSR_LASTBRANCH_2 Unique Last Branch Record 2 (R/W)
See description of MSR_LASTBRANCH_0.
43H 67 MSR_LASTBRANCH_3 Unique Last Branch Record 3 (R/W)
See description of MSR_LASTBRANCH_0.
44H 68 MSR_LASTBRANCH_4 Unique Last Branch Record 4 (R/W)
See description of MSR_LASTBRANCH_0.
45H 69 MSR_LASTBRANCH_5 Unique Last Branch Record 5 (R/W)
See description of MSR_LASTBRANCH_0.
46H 70 MSR_LASTBRANCH_6 Unique Last Branch Record 6 (R/W)
See description of MSR_LASTBRANCH_0.
47H 71 MSR_LASTBRANCH_7 Unique Last Branch Record 7 (R/W)
See description of MSR_LASTBRANCH_0.
79H 121 IA32_BIOS_UPDT_TRIG Unique BIOS Update Trigger Register (W)
See Table 2-2.
8BH 139 IA32_BIOS_SIGN_ID Unique BIOS Update Signature ID (RO)
See Table 2-2.
C1H 193 IA32_PMC0 Unique Performance Counter Register
See Table 2-2.
C2H 194 IA32_PMC1 Unique Performance Counter Register
See Table 2-2.
CDH 205 MSR_FSB_FREQ Shared Scaleable Bus Speed (RO)
This field indicates the scaleable bus clock speed:
2:0 • 101B: 100 MHz (FSB 400)
• 001B: 133 MHz (FSB 533)
• 011B: 167 MHz (FSB 667)
2-370 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
E7H 231 IA32_MPERF Unique Maximum Performance Frequency Clock Count (RW)
See Table 2-2.
E8H 232 IA32_APERF Unique Actual Performance Frequency Clock Count (RW)
See Table 2-2.
FEH 254 IA32_MTRRCAP Unique See Table 2-2.
11EH 281 MSR_BBL_CR_CTL3 Shared Control Register 3
Used to configure the L2 Cache.
0 L2 Hardware Enabled (RO)
1= If the L2 is hardware-enabled
0= Indicates if the L2 is hardware-disabled
7:1 Reserved
8 L2 Enabled (R/W)
1 = L2 cache has been initialized
0 = Disabled (default)
Until this bit is set the processor will not respond to the
WBINVD instruction or the assertion of the FLUSH# input.
22:9 Reserved
23 L2 Not Present (RO)
0= L2 Present
1= L2 Not Present
63:24 Reserved
Vol. 4 2-371
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
2 MCIP
When set, this bit indicates that a machine check has been
generated. If a second machine check is detected while this bit
is still set, the processor enters a shutdown state. Software
should write this bit to 0 after processing a machine check
exception.
63:3 Reserved
186H 390 IA32_PERFEVTSEL0 Unique See Table 2-2.
187H 391 IA32_PERFEVTSEL1 Unique See Table 2-2.
198H 408 IA32_PERF_STATUS Shared See Table 2-2.
199H 409 IA32_PERF_CTL Unique See Table 2-2.
19AH 410 IA32_CLOCK_MODULATION Unique Clock Modulation (R/W)
See Table 2-2.
19BH 411 IA32_THERM_INTERRUPT Unique Thermal Interrupt Control (R/W)
See Table 2-2.
See Section 14.8.2, “Thermal Monitor.”
19CH 412 IA32_THERM_STATUS Unique Thermal Monitor Status (R/W)
See Table 2-2.
See Section 14.8.2, “Thermal Monitor”.
19DH 413 MSR_THERM2_CTL Unique Thermal Monitor 2 Control
15:0 Reserved
16 TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation
of the stop-clock duty cycle)
1 = Thermal Monitor 2 (thermally-initiated frequency
transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared,
TM_SELECT has no effect. Neither TM1 nor TM2 will be
enabled.
63:16 Reserved
1A0H 416 IA32_MISC_ENABLE Enable Miscellaneous Processor Features
(R/W)
Allows a variety of processor functions to be enabled and
disabled.
2:0 Reserved
3 Unique Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2.
6:4 Reserved
7 Shared Performance Monitoring Available (R)
See Table 2-2.
2-372 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
9:8 Reserved
10 Shared FERR# Multiplexing Enable (R/W)
1= FERR# asserted by the processor to indicate a pending
break event within the processor
0 = Indicates compatible FERR# signaling behavior
This bit must be set to 1 to support XAPIC interrupt model
usage.
11 Shared Branch Trace Storage Unavailable (RO)
See Table 2-2.
12 Reserved
13 Shared TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor indicates that
the die temperature is at the pre-determined threshold, the
Thermal Monitor 2 mechanism is engaged. TM2 will reduce the
bus to core ratio and voltage according to the value last
written to MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not
change the VID signals or the bus to core ratio when the
processor enters a thermal managed state.
If the TM2 feature flag (ECX[8]) is not set to 1 after executing
CPUID with EAX = 1, then this feature is not supported and
BIOS must not alter the contents of this bit location. The
processor is operating out of spec if both this bit and the TM1
bit are set to disabled states.
15:14 Reserved
16 Shared Enhanced Intel SpeedStep Technology Enable (R/W)
1= Enhanced Intel SpeedStep Technology enabled
18 Shared ENABLE MONITOR FSM (R/W)
See Table 2-2.
19 Reserved
22 Shared Limit CPUID Maxval (R/W)
See Table 2-2.
Setting this bit may cause behavior in software that depends
on the availability of CPUID leaves greater than 2.
33:23 Reserved
34 Shared XD Bit Disable (R/W)
See Table 2-2.
63:35 Reserved
1C9H 457 MSR_LASTBRANCH_TOS Unique Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing
the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).
Vol. 4 2-373
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
1D9H 473 IA32_DEBUGCTL Unique Debug Control (R/W)
Controls how several debug features are used. Bit definitions
are discussed in Table 2-2.
1DDH 477 MSR_LER_FROM_LIP Unique Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the
processor executed prior to the last exception that was
generated or the last interrupt that was handled.
1DEH 478 MSR_LER_TO_LIP Unique Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch
instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was
handled.
200H 512 MTRRphysBase0 Unique Memory Type Range Registers
201H 513 MTRRphysMask0 Unique Memory Type Range Registers
202H 514 MTRRphysBase1 Unique Memory Type Range Registers
203H 515 MTRRphysMask1 Unique Memory Type Range Registers
204H 516 MTRRphysBase2 Unique Memory Type Range Registers
205H 517 MTRRphysMask2 Unique Memory Type Range Registers
206H 518 MTRRphysBase3 Unique Memory Type Range Registers
207H 519 MTRRphysMask3 Unique Memory Type Range Registers
208H 520 MTRRphysBase4 Unique Memory Type Range Registers
209H 521 MTRRphysMask4 Unique Memory Type Range Registers
20AH 522 MTRRphysBase5 Unique Memory Type Range Registers
20BH 523 MTRRphysMask5 Unique Memory Type Range Registers
20CH 524 MTRRphysBase6 Unique Memory Type Range Registers
20DH 525 MTRRphysMask6 Unique Memory Type Range Registers
20EH 526 MTRRphysBase7 Unique Memory Type Range Registers
20FH 527 MTRRphysMask7 Unique Memory Type Range Registers
250H 592 MTRRfix64K_00000 Unique Memory Type Range Registers
258H 600 MTRRfix16K_80000 Unique Memory Type Range Registers
259H 601 MTRRfix16K_A0000 Unique Memory Type Range Registers
268H 616 MTRRfix4K_C0000 Unique Memory Type Range Registers
269H 617 MTRRfix4K_C8000 Unique Memory Type Range Registers
26AH 618 MTRRfix4K_D0000 Unique Memory Type Range Registers
26BH 619 MTRRfix4K_D8000 Unique Memory Type Range Registers
26CH 620 MTRRfix4K_E0000 Unique Memory Type Range Registers
26DH 621 MTRRfix4K_E8000 Unique Memory Type Range Registers
26EH 622 MTRRfix4K_F0000 Unique Memory Type Range Registers
26FH 623 MTRRfix4K_F8000 Unique Memory Type Range Registers
2-374 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
2FFH 767 IA32_MTRR_DEF_TYPE Unique Default Memory Types (R/W)
See Table 2-2.
See Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
400H 1024 IA32_MC0_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H 1025 IA32_MC0_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H 1026 IA32_MC0_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
IA32_MC0_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
404H 1028 IA32_MC1_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H 1029 IA32_MC1_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
406H 1030 IA32_MC1_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
IA32_MC1_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
408H 1032 IA32_MC2_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H 1033 IA32_MC2_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH 1034 IA32_MC2_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
IA32_MC2_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
40CH 1036 MSR_MC4_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH 1037 MSR_MC4_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH 1038 MSR_MC4_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
410H 1040 IA32_MC3_CTL See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H 1041 IA32_MC3_STATUS See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H 1042 MSR_MC3_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
Vol. 4 2-375
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
413H 1043 MSR_MC3_MISC Unique Machine Check Error Reporting Register - contains additional
information describing the machine-check error if the MISCV
flag in the IA32_MCi_STATUS register is set.
414H 1044 MSR_MC5_CTL Unique Machine Check Error Reporting Register - controls signaling of
#MC for errors produced by a particular hardware unit (or
group of hardware units).
415H 1045 MSR_MC5_STATUS Unique Machine Check Error Reporting Register - contains information
related to a machine-check error if its VAL (valid) flag is set.
Software is responsible for clearing IA32_MCi_STATUS MSRs
by explicitly writing 0s to them; writing 1s to them causes a
general-protection exception.
416H 1046 MSR_MC5_ADDR Unique Machine Check Error Reporting Register - contains the address
of the code or data memory location that produced the
machine-check error if the ADDRV flag in the
IA32_MCi_STATUS register is set.
417H 1047 MSR_MC5_MISC Unique Machine Check Error Reporting Register - contains additional
information describing the machine-check error if the MISCV
flag in the IA32_MCi_STATUS register is set.
480H 1152 IA32_VMX_BASIC Unique Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2.
See Appendix A.1, “Basic VMX Information”.
(If CPUID.01H:ECX.[bit 5])
481H 1153 IA32_VMX_PINBASED_CTLS Unique Capability Reporting Register of Pin-Based VM-Execution
Controls (R/O)
See Appendix A.3, “VM-Execution Controls”.
(If CPUID.01H:ECX.[bit 5])
482H 1154 IA32_VMX_PROCBASED_CTLS Unique Capability Reporting Register of Primary Processor-Based
VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls”.
(If CPUID.01H:ECX.[bit 5])
483H 1155 IA32_VMX_EXIT_CTLS Unique Capability Reporting Register of VM-Exit Controls (R/O)
See Appendix A.4, “VM-Exit Controls”.
(If CPUID.01H:ECX.[bit 5])
484H 1156 IA32_VMX_ENTRY_CTLS Unique Capability Reporting Register of VM-Entry Controls (R/O)
See Appendix A.5, “VM-Entry Controls”.
(If CPUID.01H:ECX.[bit 5])
485H 1157 IA32_VMX_MISC Unique Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data”.
(If CPUID.01H:ECX.[bit 5])
486H 1158 IA32_VMX_CR0_FIXED0 Unique Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0”.
(If CPUID.01H:ECX.[bit 5])
2-376 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Shared/
Address Register Name Unique Bit Description
Hex Dec
487H 1159 IA32_VMX_CR0_FIXED1 Unique Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0”.
(If CPUID.01H:ECX.[bit 5])
488H 1160 IA32_VMX_CR4_FIXED0 Unique Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4”.
(If CPUID.01H:ECX.[bit 5])
489H 1161 IA32_VMX_CR4_FIXED1 Unique Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4”.
(If CPUID.01H:ECX.[bit 5])
48AH 1162 IA32_VMX_VMCS_ENUM Unique Capability Reporting Register of VMCS Field Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration”.
(If CPUID.01H:ECX.[bit 5])
48BH 1163 IA32_VMX_PROCBASED_CTLS2 Unique Capability Reporting Register of Secondary Processor-Based
VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls”.
(If CPUID.01H:ECX.[bit 5] and
IA32_VMX_PROCBASED_CTLS[bit 63])
600H 1536 IA32_DS_AREA Unique DS Save Area (R/W)
See Table 2-2.
See Section 18.6.3.4, “Debug Store (DS) Mechanism.”
31:0 DS Buffer Management Area
Linear address of the first byte of the DS buffer management
area.
63:32 Reserved
C000_ IA32_EFER Unique See Table 2-2.
0080H
10:0 Reserved
11 Execute Disable Bit Enable
63:12 Reserved
Vol. 4 2-377
MODEL-SPECIFIC REGISTERS (MSRS)
2-378 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-379
MODEL-SPECIFIC REGISTERS (MSRS)
2-380 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-381
MODEL-SPECIFIC REGISTERS (MSRS)
2-382 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-383
MODEL-SPECIFIC REGISTERS (MSRS)
2-384 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-385
MODEL-SPECIFIC REGISTERS (MSRS)
2-386 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-387
MODEL-SPECIFIC REGISTERS (MSRS)
BBL_CR_CTL3[63:26] Reserved
BBL_CR_CTL3[25] Cache bus fraction (read only)
BBL_CR_CTL3[24] Reserved
BBL_CR_CTL3[23] L2 Hardware Disable (read only)
BBL_CR_CTL3[19] Reserved
BBL_CR_CTL3[18] Cache State error checking enable (read/write)
2-388 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-389
MODEL-SPECIFIC REGISTERS (MSRS)
187H 391 PerfEvtSel1 (EVNTSEL1) Performance Event Select for Counter 1 (R/W)
7:0 Event Select
Refer to Performance Counter section for a list of event encodings.
15:8 UMASK (Unit Mask)
Unit mask register set to 0 to enable all count options.
16 USER
Controls the counting of events at Privilege levels of 1, 2, and 3.
17 OS
Controls the counting of events at Privilege level of 0.
18 E
Occurrence/Duration Mode Select.
1 = Occurrence
0 = Duration
19 PC
Enabled the signaling of performance counter overflow via BP0 pin.
2-390 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-391
MODEL-SPECIFIC REGISTERS (MSRS)
2-392 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-393
MODEL-SPECIFIC REGISTERS (MSRS)
2-394 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-395
MODEL-SPECIFIC REGISTERS (MSRS)
2-396 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-397
MODEL-SPECIFIC REGISTERS (MSRS)
2-398 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-399
MODEL-SPECIFIC REGISTERS (MSRS)
2-400 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-401
MODEL-SPECIFIC REGISTERS (MSRS)
2-402 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-403
MODEL-SPECIFIC REGISTERS (MSRS)
2-404 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-405
MODEL-SPECIFIC REGISTERS (MSRS)
2-406 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-407
MODEL-SPECIFIC REGISTERS (MSRS)
2-408 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-409
MODEL-SPECIFIC REGISTERS (MSRS)
2-410 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-411
MODEL-SPECIFIC REGISTERS (MSRS)
2-412 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-413
MODEL-SPECIFIC REGISTERS (MSRS)
2-414 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-415
MODEL-SPECIFIC REGISTERS (MSRS)
2-416 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-417
MODEL-SPECIFIC REGISTERS (MSRS)
2-418 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-419
MODEL-SPECIFIC REGISTERS (MSRS)
2-420 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-421
MODEL-SPECIFIC REGISTERS (MSRS)
2-422 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-423
MODEL-SPECIFIC REGISTERS (MSRS)
2-424 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-425
MODEL-SPECIFIC REGISTERS (MSRS)
2-426 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-427
MODEL-SPECIFIC REGISTERS (MSRS)
2-428 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-429
MODEL-SPECIFIC REGISTERS (MSRS)
2-430 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-431
MODEL-SPECIFIC REGISTERS (MSRS)
2-432 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-433
MODEL-SPECIFIC REGISTERS (MSRS)
2-434 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-435
MODEL-SPECIFIC REGISTERS (MSRS)
2-436 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-437
MODEL-SPECIFIC REGISTERS (MSRS)
2-438 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-439
MODEL-SPECIFIC REGISTERS (MSRS)
2-440 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-441
MODEL-SPECIFIC REGISTERS (MSRS)
2-442 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-443
MODEL-SPECIFIC REGISTERS (MSRS)
2-444 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-445
MODEL-SPECIFIC REGISTERS (MSRS)
2-446 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-447
MODEL-SPECIFIC REGISTERS (MSRS)
2-448 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-449
MODEL-SPECIFIC REGISTERS (MSRS)
2-450 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-451
MODEL-SPECIFIC REGISTERS (MSRS)
2-452 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-453
MODEL-SPECIFIC REGISTERS (MSRS)
2-454 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-455
MODEL-SPECIFIC REGISTERS (MSRS)
2-456 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-457
MODEL-SPECIFIC REGISTERS (MSRS)
2-458 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-459
MODEL-SPECIFIC REGISTERS (MSRS)
2-460 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-461
MODEL-SPECIFIC REGISTERS (MSRS)
2-462 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-463
MODEL-SPECIFIC REGISTERS (MSRS)
2-464 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-465
MODEL-SPECIFIC REGISTERS (MSRS)
2-466 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-467
MODEL-SPECIFIC REGISTERS (MSRS)
2-468 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-469
MODEL-SPECIFIC REGISTERS (MSRS)
2-470 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Vol. 4 2-471
MODEL-SPECIFIC REGISTERS (MSRS)
2-472 Vol. 4
INDEX
Vol. 4 INDEX-1
INDEX
P
P5_MC_ADDR MSR, 2-55, 2-69, 2-80, 2-129, 2-166, 2-325, 2-368,
2-377, 2-384, 2-394
P5_MC_TYPE MSR, 2-55, 2-69, 2-80, 2-129, 2-166, 2-325, 2-368,
2-378, 2-384, 2-394
P6 family processors
description of, 1-1
MSR supported by, 2-384
Page frame (see Page)
PDBR (see CR3 control register)
PEBS_UNAVAILABLE flag
IA32_MISC_ENABLE MSR, 2-351
Pentium 4 processor, 1-1
MSRs supported, 2-55, 2-69, 2-80, 2-97, 2-99, 2-123, 2-127, 2-341,
2-342, 2-367
Pentium II processor, 1-3
Pentium III processor, 1-3
Pentium M processor
MSRs supported by, 2-377
Pentium Pro processor, 1-3
Pentium processor, 1-1
MSR supported by, 2-393
Precise event-based sampling (see PEBS)
R
Related literature, 1-8
Requested privilege level (see RPL)
Reserved bits, 1-5
INDEX-2 Vol. 4