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    EE290C - Spring 2011 RX FIR Equalizers: - Currently Not Very Popular - Why?

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    Fahmida Pervin Brishty
    This document summarizes a lecture on equalization techniques, including FIR equalizers and decision feedback equalizers (DFE). It discusses various DFE implementation challenges such as feedback latency constraints, summer design to meet settling time requirements, and maximum cancellation of intersymbol interference. It also covers DFE architectures like coefficient shuffling and loop unrolling.

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    EE290C - Spring 2011 RX FIR Equalizers: - Currently Not Very Popular - Why?

    Uploaded by

    Fahmida Pervin Brishty
    108 views4 pages
    This document summarizes a lecture on equalization techniques, including FIR equalizers and decision feedback equalizers (DFE). It discusses various DFE implementation challenges such as feedback latency constraints, summer design to meet settling time requirements, and maximum cancellation of intersymbol interference. It also covers DFE architectures like coefficient shuffling and loop unrolling.

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    Berkley 290

    Original Title

    Lecture08_Eq_FIR_II_DFE_6up

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    This document summarizes a lecture on equalization techniques, including FIR equalizers and decision feedback equalizers (DFE). It discusses various DFE implementation challenges such as feedback latency constraints, summer design to meet settling time requirements, and maximum cancellation of intersymbol interference. It also covers DFE architectures like coefficient shuffling and loop unrolling.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    108 views4 pages

    EE290C - Spring 2011 RX FIR Equalizers: - Currently Not Very Popular - Why?

    Uploaded by

    Fahmida Pervin Brishty
    This document summarizes a lecture on equalization techniques, including FIR equalizers and decision feedback equalizers (DFE). It discusses various DFE implementation challenges such as feedback latency constraints, summer design to meet settling time requirements, and maximum cancellation of intersymbol interference. It also covers DFE architectures like coefficient shuffling and loop unrolling.

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    RX FIR Equalizers

    EE290C – Spring 2011 • Currently not very popular – why?

    Lecture 8: Equalization: FIR II and DFE

    Elad Alon
    Dept. of EECS

    EE290C Lecture 8 4

    VM TX + Equalization Coefficient Shuffling Architecture


    • First implementation (K.-L. J. Wong, JSSC 2004): • Lee, Razavi, CICC 2001

    EE290C Lecture 8 2 EE290C Lecture 8 5

    Constant Current VM TX Design Shuffling Implementation


    • D. Dettloff, ISSCC 2010 • Can shuffle digital tap coefficients or analog
    inputs

    EE290C Lecture 8 3 EE290C Lecture 8 6


    Interleaving A Reminder
    • Often combined with tap shuffling
    • Ex: J. Jaussi, ISSCC 2004

    EE290C Lecture 8 7 EE290C Lecture 8 10

    DFE: Implementation Self-Loading

    • Creates bandwidth 0.6


    RX_in C = 20fF
    limit 0.5 L
    C = 40fF
    • No matter how 0.4 L
    C = 80fF
    much power you L

    m
    0.3

    G
    spend 0.2
    0.1

    • DFE has increased 0

    • Design driven by feedback latency constraint “self-loading” due 0 0.2 0.4 0.6
    GBW/(ω /γ )
    0.8 1
    T
    • New summer output needs to settle (at comparator to taps…
    input) within one bit time

    EE290C Lecture 8 8 EE290C Lecture 8 11

    DFE Summer Design DFE Summer Design


    • Key constraint:
    tdig_fb + tana_settle = Tbit

    • Need some Nτ of
    settling:
    τsum = (Tbit – tdig_fb)/Nτ

    • Typically want ~4τ for ~98% settling

    EE290C Lecture 8 9 EE290C Lecture 8 12


    Maximum Cancelled ISI Split Summation
    !0Gb/s DFE
    0.05 • B. Leibowitz, ISSCC 2007
    tdig = 30ps
    0.04 tdig = 40ps
    tdig = 50ps
    0.03
    m
    G

    0.02

    0.01

    0
    0 2 4 6 8 10
    M
    DFE

    • There is a maximum MDFE you can achieve


    • Don’t forget that every tap has to handle worst-
    case possible ISI
    • Implies max. number of taps (in given tech.)
    EE290C Lecture 8 13 EE290C Lecture 8 16

    TX FIR RX DFE Duality All CML Design


    • Can use same techniques we talked about in TX • H. Wang, VLSI 2009
    for RX DFE • Over 20Gb/s in 65nm CMOS
    • But still need to watch out for digital power…

    Vin
    d0

    clk

    0 – Imax/2
    z-1
    d0
    d1 d1
    0 – Imax/2 d2
    z-1
    d1
    d2
    0 – Imax/4 d2

    EE290C Lecture 8 14 EE290C Lecture 8 17

    Closing the First Tap Loop Unrolling


    • K. Parhi, ISCAS 1990

    +1+α +α d n | d n −1 = 1
    +1-α
    +α xn d n −1
    dClk D Q
    -α
    -1+α
    -α
    d n | d n −1 = 0

    -1-α dClk

    EE290C Lecture 8 15 EE290C Lecture 8 18


    Extended Loop Unrolling Practical DFE Design Issues

    EE290C Lecture 8 19 EE290C Lecture 8 22

    LE + DFE Practical DFE Design Issues

    EE290C Lecture 8 20 EE290C Lecture 8 23

    Practical DFE Design Issues

    EE290C Lecture 8 21

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