Advanced Multi-Bit 192Khz 24-Bit: General Description
Advanced Multi-Bit 192Khz 24-Bit: General Description
Advanced Multi-Bit 192Khz 24-Bit: General Description
AK4396
Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC
GENERAL DESCRIPTION
The AK4396 is a high performance stereo DAC for the 192kHz sampling mode of DVD-Audio including a
24bit digital filter. Using AKM's multi bit architecture for its modulator the AK4396 delivers a wide dynamic
range while preserving linearity for improved THD+N performance. The AK4396 has full differential SCF
outputs, removing the need for AC coupling capacitors and increasing performance for systems with
excessive clock jitter. The AK4396 accepts 192kHz PCM data and 1-bit DSD data, ideal for a wide range
of applications including DVD-Audio and SACD. The AK4396 has a fully functional compatibility with the
AK4393/4/5 and lower power dissipation.
FEATURES
• 128x Oversampling
• Sampling Rate: 30kHz ∼ 216kHz
• 24Bit 8x Digital Filter (Slow-roll-off option)
Ripple: ±0.005dB, Attenuation: 75dB
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• DSD data input available
• Digital de-emphasis for 32, 44.1, 48kHz sampling
• Soft Mute
• Digital Attenuator (Linear 256 steps)
• THD+N: −100dB
• DR, S/N: 120dB
• I/F format : MSB justified, 16/20/24bit LSB justified, I2S
• Master Clock: Normal Speed: 256fs, 384fs, 512fs, 768fs or 1152fs
Double Speed: 128fs, 192fs, 256fs or 384fs
Quad Speed: 128fs or 192fs
DSD: 512fs or 768fs
• Power Supply: 5V ± 5% (Analog), 3.0 ∼ 5.25V (Digital)
• CMOS or TTL Level Digital I/F
• Package: 28pin VSOP
• Pin Compatible with AK4393/4/5
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Block Diagram
ACKS DZFL
BICK/DCLK 8X ΔΣ AOUTL+
SCF
PCM Interpolator Modulator AOUTL-
LRCK/DSDR Data
Interface 8X ΔΣ AOUTR+
SCF
SDATA/DSDL Interpolator Modulator AOUTR-
DIF0/DCLK DZFR
DSD
DIF1/DSDL Data
DIF2/DSDR Interface
CAD0 De-emphasis
Control Register Clock Divider
CAD1 Control
Block Diagram
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Ordering Guide
Pin Layout
DVSS 1 28 ACKS/DZFR
DVDD 2 27 TST2/CAD1
MCLK 3 26 TST1/DZFL
PDN 4 25 P/S
BICK/DCLK 5 24 VCOM
SDATA/DSDL 6 23 AOUTL+
Top
View
LRCK/DSDR 7 22 AOUTL-
SMUTE/CSN 8 21 AOUTR+
DFS0/CAD0 9 20 AOUTR-
DEM0/CCLK 10 19 AVSS
DEM1/CDTI 11 18 AVDD
DIF0/DCLK 12 17 VREFH
DIF1/DSDL 13 16 VREFL
DIF2/DSDR 14 15 TTL
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2. Pin Configuration
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AK4393/4/5 AK4396
CKS2 CKS1 CKS0 DFS0=0 DFS0=1 ACKS DFS0=0 DFS0=1
0 0 0 256fs 128fs 0 256fs 128fs
0 0 1 256fs 256fs 0 256fs 256fs
0 1 0 384fs 192fs 0 384fs 192fs
0 1 1 384fs 384fs 0 384fs 384fs
1 0 0 512fs 256fs 1 512fs 256fs
1 0 1 512fs N/A 1 512fs N/A
1 1 0 768fs 384fs 1 768fs 384fs
1 1 1 768fs N/A 1 768fs N/A
: The setting of DFS0 is ignored.
4. Register map
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PIN/FUNCTION
Note: All input pins except internal pull-up/down pins should not be left floating.
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Note: All input pins except internal pull-up/down pins should not be left floating.
Note: TST1 pin outputs Hi-Z in parallel mode.
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1. PCM mode
2. DSD mode
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WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
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ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=5.0V; AVSS=DVSS=0V; VREFH=AVDD, VREFL=AVSS; Input data=24bit; RL ≥ 1kΩ;
BICK=64fs; Input Signal Frequency = 1kHz; Sampling frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz;
External Circuit: Figure 17; unless otherwise specified.)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 5)
THD+N fs=44.1kHz 0dBFS −100 −90 dB
BW=20kHz −60dBFS −57 - dB
fs=96kHz 0dBFS −97 - dB
BW=40kHz −60dBFS −54 - dB
fs=192kHz 0dBFS −97 - dB
BW=40kHz −60dBFS −54 - dB
BW=80kHz −60dBFS −51 - dB
Dynamic Range (−60dBFS with A-weighted) (Note 6) 114 120 dB
S/N (A-weighted) (Note 7) 114 120 dB
Interchannel Isolation (1kHz) 100 120 dB
DC Accuracy
Interchannel Gain Mismatch 0.15 0.3 dB
Gain Drift (Note 8) 20 - ppm/°C
Output Voltage (Note 9) ±2.65 ±2.8 ±2.95 Vpp
Load Capacitance 25 pF
Load Resistance (Note 10) 1 kΩ
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”) (Note 11)
AVDD 32 47 mA
DVDD (fs ≤ 96kHz) 8 - mA
DVDD (fs = 192kHz) 13 19 mA
Power down (PDN pin = “L”) (Note 12)
AVDD+DVDD 10 100 μA
Power Supply Rejection (Note 13) 50 dB
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 6. By Figure 17. External LPF Circuit Example 2.101dB at 16bit data and 118dB at 20bit data.
Note 7. By Figure 17. External LPF Circuit Example 2. S/N does not depend on input bit length.
Note 8. The voltage on (VREFH − VREFL) is held +5V externally.
Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFH − VREFL).
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH − VREFL)/5.
Note 10. For AC-load. 1.5kΩ for DC-Load
Note 11. typ. 5mA (@ DVDD=3.3V, fs ≤ 96kHz), typ. 8mA (@ DVDD=3.3V, fs = 192kHz)
Note 12. In the power-down mode. P/S pin = TTL pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held DVSS.
Note 13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.
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Note 14. The passband and stopband frequencies scale with fs. For example, PB = 0.4535×fs (@±0.01dB), SB =
0.546×fs.
Note 15. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of
both channels to input register to the output of analog signal.
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Note 16. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
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Note 17. DFS0, TTL, P/S and TST2 pins have internal pull-down or pull-up devices, nominally 100kΩ.
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SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V)
Parameter Symbol min typ max Units
Master Clock Timing
Frequency fCLK 7.7 41.472 MHz
Duty Cycle dCLK 40 60 %
LRCK Frequency (Note 18)
Normal Speed Mode fsn 30 54 kHz
Double Speed Mode fsd 54 108 kHz
Quad Speed Mode fsq 108 216 kHz
Duty Cycle Duty 45 55 %
PCM Audio Interface Timing
BICK Period
Normal Speed Mode tBCK 1/128fn ns
Double Speed Mode tBCK 1/64fd ns
Quad Speed Mode tBCK 1/64fq ns
BICK Pulse Width Low tBCKL 30 ns
BICK Pulse Width High tBCKH 30 ns
BICK “↑” to LRCK Edge (Note 19) tBLR 20 ns
LRCK Edge to BICK “↑” (Note 19) tLRB 20 ns
SDATA Hold Time tSDH 20 ns
SDATA Setup Time tSDS 20 ns
DSD Audio Interface Timing
DCLK Period tDCK 1/64fs ns
DCLK Pulse Width Low tDCKL 160 ns
DCLK Pulse Width High tDCKH 160 ns
DCLK Edge to DSDL/R (Note 20) tDDD −20 20 ns
Control Interface Timing
CCLK Period tCCK 200 ns
CCLK Pulse Width Low tCCKL 80 ns
Pulse Width High tCCKH 80 ns
CDTI Setup Time tCDS 50 ns
CDTI Hold Time tCDH 50 ns
CSN High Time tCSW 150 ns
CSN “↓” to CCLK “↑” tCSS 50 ns
CCLK “↑” to CSN “↑” tCSH 50 ns
Reset Timing
PDN Pulse Width (Note 21) tPD 150 ns
Note 18. When the normal/double/quad speed modes are switched, AK4396 should be reset by PDN pin or RSTN bit.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. DSD data transmitting device must meet this time.
Note 21. The AK4396 can be reset by bringing PDN pin “L” to “H”. When the states of or DFS1-0 bits change,
the AK4396 should be reset by RSTN bit.
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Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR tLRB
VIH
BICK
VIL
tSDS tSDH
VIH
SDATA
VIL
Audio Interface Timing (PCM Mode)
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tDCK
tDCKL tDCKH
VIH
DCLK
VIL
tDDD
DSDL VIH
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)
tDCK
tDCKL tDCKH
VIH
DCLK
VIL
tDDD tDDD
DSDL VIH
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
VIH
CSN
VIL
VIH
CCLK
VIL
tCDS tCDH
VIH
CDTI C1 C0 R/W A4
VIL
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tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI D3 D2 D1 D0
VIL
tPD
PDN
VIL
Power Down & Reset Timing
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OPERATION OVERVIEW
In serial mode, the AK4396 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,
PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode changes by D/P bit, the AK4396
should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4396 performs for
only PCM data.
System Clock
The external clocks, which are required to operate the AK4396, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. When external clocks are changed, the AK4396 should be reset by PDN pin or RSTN bit.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4396 is in normal operation
mode (PDN pin = “H”). If these clocks are not provided, the AK4396 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4396 should be in the power-down mode
(PDN pin = “L”) or in the reset mode (RSTN bit = “0”). After exiting reset (PDN pin = “L” → “H”) at power-up etc., the
AK4396 is in power-down mode until MCLK is supplied.
MCLK frequency is detected automatically and the sampling speed is set by DFS0 pin (Table 2). The MCLK frequency
corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to “0”. When DFS0 pin is changed,
the AK4396 should be reset by PDN pin. Quad speed mode is not supported in this mode.
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MCLK frequency and the sampling speed are detected automatically (Table 4) and DFS0 pin is ignored. DFS0 pin should
be fixed to DVSS or DVDD.
MCLK frequency is detected automatically and the sampling speed is set by DFS1-0 bits (Table 6). The MCLK frequency
corresponding to each sampling speed should be provided (Table 7). The AK4396 is set to Manual Setting Mode at
power-up (PDN pin = “L” → “H”). When DFS1-0 bits are changed, the AK4396 should be reset by RSTN bit.
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MCLK frequency and the sampling speed are detected automatically (Table 8) and DFS1-0 bits are ignored. The MCLK
frequency corresponding to each sampling speed should be provided (Table 9).
The external clocks, which are required to operate the AK4396, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
All external clocks (MCLK, DCLK) should always be present whenever the AK4396 is in the normal operation mode
(PDN pin = “H”). If these clocks are not provided, the AK4396 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4396 should be reset by PDN pin = “L” after threse clocks are provided. If the
external clocks are not present, the AK4396 should be in the power-down mode (PDN pin = “L”). After exiting
reset(PDN pin = “L” → “H”) at power-up etc., the AK4396 is in the power-down mode until MCLK is input.
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Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the
DIF2-0 pins (Parallel mode) or DIF2-0 bits (Serial mode) as shown in Table 11. In all formats the serial data is MSB-first,
2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats
by zeroing the unused LSBs.
LRCK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
BICK
(32fs)
SDATA 15 14 6 5 4 3 2 1 0 15 14 6 5 4 3 2 1 0 15 14
Mode 0
0 1 14 15 16 17 31 0 1 14 15 16 17 31 0 1
BICK
(64fs)
LRCK
0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1
BICK
(64fs)
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LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK
(64fs)
23:MSB, 0:LSB
LRCK
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1
BICK
(64fs)
23:MSB, 0:LSB
In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can
invert the polarity of DCLK.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR D0 D1 D2 D3
Normal
DSDL,DSDR
Phase Modulation D0 D1 D1 D2 D2 D3
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RSTN bit
≥4/fs
RSTN bit
Caution: In DSD mode, the signal level is ranging from 25% to 75%. Peak levels of DSD signal above this duty are not
recommended by SACD format book (Scarlet Book).
De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or
disabled with DEM1-0 pins or DEM1-0 bits. In case of double speed and quad speed mode, the digital de-emphasis filter
is always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode
are switched.
Output Volume
The AK4396 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 13.
Transition Time
Sampling Speed
1 Level 255 to 0
Normal Speed Mode 4LRCK 1020LRCK
Double Speed Mode 8LRCK 2040LRCK
Quad Speed Mode 16LRCK 4080LRCK
Table 13. ATT Transition Time
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Zero Detection
The AK4396 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF pin “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF
pins of both channels go to “L” at 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both
channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect
function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the
polarity of DZF pin.
Soft mute operation is performed at digital domain. When SMUTE pin goes to “H” or SMUTE bit goes to “1”, the output
signal is attenuated by −∞ during ATT_DATA × ATT transition time (Table 13) from the current ATT level. When
SMUTE pin is returned to “L” or SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually
changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before attenuating −∞
after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is
effective for changing the signal source without stopping the signal transmission.
SM U T E pin or
SM U T E bit
(1) (1)
AT T _Level
(3)
Attenuation
-∞
GD GD
(2) (2)
AO U T
(4)
8192/fs
D Z F pin
Notes:
(1) ATT_DATA × ATT transition time (Table 13). For example, this time is 1020LRCK cycles (1020/fs)
at ATT_DATA=255 in Normal Speed Mode.
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes
to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”.
System Reset
The AK4396 should be reset once by bringing PDN pin = “L” upon power-up. The analog section exits power-down
mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during
4/fs.
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Power-Down
The AK4396 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 9 shows an example of the system timing at the power-down and power-up.
PDN
DZFL/DZFR (6)
External
(5) Mute ON
MUTE
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge (“↑ ↓”) of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN pin = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN pin = “L”).
Other:
After exiting power-down mode (PDN pin: “L” Æ “H”), AOUT pins go to VCOM voltage (VA/2). This time is set
by a capacitor connected to VCOM pin and the internal resistor of VCOM pin.
E.g. C = 10μF
1 τ (typ) = 10μF x 0.75kΩ = 7.5ms, 5τ (typ) = 37.5ms
1 τ (max) = 10μF x 0.975kΩ = 9.75ms, 5τ (max) = 48.75ms
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Reset Function
When RSTN bit = “0”, the AK4396’s digital section is powered down but the internal register values are not initialized.
The analog outputs go to VCOM voltage and DZF pins of both channels go to “H”. Figure 10 shows the example of reset
by RSTN bit.
RSTN bit
3~4/fs (6) 2~3/fs (6)
Internal
RSTN Timing
2/fs(5)
DZFL/DZFR
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Click noise occurs at the edges (“↑ ↓”) of the internal timing of RSTN bit.
This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3 ~ 4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2 ~ 3/fs from RSTN bit “1”
to the internal RSTN bit “1”.
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Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4396. In parallel mode,
the register setting is ignored and the pin setting is ignored in serial mode. When the state of P/S pin is changed, the
AK4396 should be reset by PDN pin. The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting
must be all “L”. Internal registers may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this
interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits)
and Control data (MSB first, 8bits). The AK4396 latches the data on the rising edge of CCLK, so data should be clocked
in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).
PDN pin = “L” resets the registers to their default values. In serial mode, the internal timing circuit is reset by RSTN bit,
but the registers are not initialized.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
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Register Map
Notes:
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the only internal timing is reset and the registers are not initialized to their default values.
When the state of P/S pin is changed, the AK4396 should be reset by PDN pin.
Register Definitions
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
0 : Disable : Manual setting mode (Default)
1 : Enable : Auto setting mode
When ACKS bit = “1”, MCLK frequency and the sampling frequency are detected automatically.
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SYSTEM DESIGN
Figure 12, Figure 13 and Figure 14 show the system connection diagram. Figure 16 , Figure 17 and Figure 18 show the
analog output circuit examples. An evaluation board (AKD4396) is available which demonstrates the optimum layout,
power supply arrangements and measurement results.
Digital
Supply 3.3V
10u 0.1u
1 DVSS DZFR 28
+ DVDD CAD1
2 27
12 DIF0 VREFH 17
Analog
0.1u
+ Supply 5V
10u
13 DIF1 VREFL 16
14 DIF2 TTL 15
Notes:
- Chip Address = “00”. LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- AVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
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Digital
Supply 3.3V
10u 0.1u
1 DVSS ACKS 28
+
2 DVDD TST2 27
10 DEM0 AVSS 19
Mode 0.1u
+ 10u
11 DEM1 AVDD 18
setting Analog
12 DIF0 VREFH 17 Supply 5V
+
0.1u 10u
13 DIF1 VREFL 16
14 DIF2 TTL 15
Notes:
- BICK = 64fs, LRCK = fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- AVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
Figure 13. Typical Connection Diagram (AVDD = 5V, DVDD = 3.3V, Parallel mode, AK4393 compatible)
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ASAHI KASEI [AK4396]
Digital
Supply 5.0V
10u 0.1u
1 DVSS DZFR 28
+ DVDD CAD1
2 27
12 DIF0 VREFH 17
Analog
0.1u
+ Supply 5V
10u
13 DIF1 VREFL 16
14 DIF2 TTL 15
Notes:
- TTL pin (BVSS pin in case of AK4394/5) should be open.
- Chip Address = “00”, BICK = 64fs, LRCK = fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- AVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
Figure 14. Typical Connection Diagram (AVDD=5V, DVDD=5V, Serial mode, AK4394/5 compatible)
2 DVDD CAD1 27
3 MCLK DZFL 26
4 PDN P/S 25
8 CSN AOUTR+ 21
9 CAD0 AOUTR- 20
10 CCLK AVSS 19
11 CDTI AVDD 18
12 DIF0 VREFH 17
13 DIF1 VREFR 16
14 DIF2 TTL 15
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ASAHI KASEI [AK4396]
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.
AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. Power lines of
AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. The power up
sequence between AVDD and DVDD is not critical. AVSS and DVSS must be connected to analog ground
plane. Decoupling capacitors for high frequency should be placed as near as possible.
2. Voltage Reference
The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally connected to
AVDD and VREFL pin is normally connected to AVSS. VREFH and VREFL should be connected with a 0.1µF ceramic
capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor
attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All
signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted
coupling into the AK4396.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFH − VREFL = 5V) centered around VCOM. The
differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−. If the
summing gain is 1, the output range is 5.6Vpp (typ, VREFH − VREFL = 5V). The bias voltage of the external summing
circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive full scale
for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 16 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 17 shows an example of differential outputs and LPF circuit example by three op-amps.
AK4396
2.4k 2.4k
AOUT-
150 680p
+Vop
3.3n
2.4k 150 Analog
AOUT+ Out
Figure 16. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692)
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ASAHI KASEI [AK4396]
+15
3.3n
-15
+
10u
100u 180 0.1u
3 7
AOUTL- + 6
2 +
330 3.9n -
4
0.1u +10u
10k
NJM5534D +
10u 560
0.1u
680 1.0n
1.2k
100
620 2 - 4
6
+ Lch
3 7
620 1.0n NJM5534D
560
3.3n
+
10u
100u 180 0.1u
+ 3 7
AOUTL+ + 6
2 - +
330 3.9n 4 0.1u 10u
10k
NJM5534D +
10u
0.1u
680
1.2k
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ASAHI KASEI [AK4396]
It is recommended by SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass
filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4396 can achieve this filter
response by combination of the internal filter (Table 17) and an external filter (Figure 18).
Frequency Gain
20kHz −0.4dB
50kHz −2.8dB
100kHz −15.5dB
Table 17. Internal Filter Response at DSD mode
Figure 18. External 3rd order LPF Circuit Example for DSD
Frequency Gain
20kHz −0.05dB
50kHz −0.51dB
100kHz −16.8dB
DC gain = 1.07dB
Table 18. 3rd order LPF (Figure 18) Response
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ASAHI KASEI [AK4396]
PACKAGE
*5.6±0.2
7.6±0.2
1 14
+0.1
0.22±0.1 0.65 0.15-0.05
0.1±0.1
Detail A
0.5±0.2
Seating Plane | 0.10
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ASAHI KASEI [AK4396]
MARKING
AKM
AK4396VF
XXXBYYYYC
Revision History
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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