INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

HEF40192B
MSI
4-bit up/down decade counter
Product specification January 1995
File under Integrated Circuits, IC04
Philips Semiconductors Product specification

HEF40192B
4-bit up/down decade counter
MSI

DESCRIPTION counting, both clock inputs cannot be LOW

simultaneously. The outputs TCU and TCD are normally
The HEF40192B is a 4-bit synchronous up/down decade
HIGH. When the circuit has reached the maximum count
counter. The counter has a count-up clock input (CPU), a
state of ‘9’, the next HIGH to LOW transition of CPU will
count-down clock input (CPD), an asynchronous parallel
cause TCU to go LOW. TCU will stay LOW until CPU goes
load input (PL), four parallel data inputs (P0 to P3), an
HIGH again. Likewise, output TCD will go LOW when the
asynchronous master reset input (MR), four counter
circuit is in the zero state and CPD goes LOW. When PL is
outputs (O0 to O3), an active LOW terminal count-up
LOW, the information on P0 to P3 is asynchronously
(carry) output (TCU) and an active LOW terminal
loaded into the counter. A HIGH on MR resets the counter
count-down (borrow) output (TCD).
independent of all other input conditions. The counter
The counter outputs change state on the LOW to HIGH stages are of a static toggle type flip-flop.
transition of either clock input. However, for correct

Fig.2 Pinning diagram.

HEF40192BP(N): 16-lead DIL; plastic

(SOT38-1)
HEF40192BD(F): 16-lead DIL; ceramic (cerdip)
Fig.1 Functional diagram.
(SOT74)
HEF40192BT(D): 16-lead SO; plastic
(SOT109-1)
PINNING
( ): Package Designator North America
PL parallel load input (active LOW)
P0 to P3 parallel data inputs
CPU count-up clock pulse input (LOW to HIGH, FAMILY DATA, IDD LIMITS category MSI
edge-triggered)
See Family Specifications
CPD count-down clock pulse input (LOW to
HIGH, edge-triggered)
MR master reset input (asynchronous)
TCU buffered terminal count-up (carry) output
(active LOW)
TCD buffered terminal count-down
(borrow) output (active LOW)
O0 to O3 buffered counter outputs

January 1995 2
Philips Semiconductors Product specification

HEF40192B
4-bit up/down decade counter
MSI

Fig.3 Logic diagram (continued on next page).

January 1995 3
Philips Semiconductors Product specification

HEF40192B
4-bit up/down decade counter
MSI

Fig.4 Logic diagram (continued from Fig.3).

January 1995 4
Philips Semiconductors Product specification

HEF40192B
4-bit up/down decade counter
MSI

FUNCTION TABLE Notes

MR PL CPU CPD MODE 1. H = HIGH state (the more positive voltage)

L = LOW state (the less positive voltage)
H X X X reset (asyn.) X = state is immaterial
L L X X parallel load
= positive-going transition
L H H count-up

L H H count-down

Logic equations for terminal count:

TC D = O 0 ⋅ O 1 ⋅ O 2 ⋅ O 3 ⋅ CP D

TC U = O 0 ⋅ O 3 ⋅ CP U

Fig.5 State diagram.

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns

VDD
TYPICAL FORMULA FOR P (µW)
V
Dynamic power 5 550 fi + ∑(foCL) × VDD2 where
dissipation per 10 2400 fi + ∑(foCL) × VDD2 fi = input freq. (MHz)
package (P) 15 6500 fi + ∑(foCL) × VDD2 fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)

January 1995 5
Philips Semiconductors Product specification

HEF40192B
4-bit up/down decade counter
MSI

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

VDD TYPICAL EXTRAPOLATION

SYMBOL MIN. TYP. MAX.
V FORMULA
Propagation delays
CPU → On 5 210 415 ns 183 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 85 165 ns 74 ns + (0,23 ns/pF) CL
15 60 120 ns 52 ns + (0,16 ns/pF) CL
5 170 340 ns 143 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 70 140 ns 59 ns + (0,23 ns/pF) CL
15 50 100 ns 42 ns + (0,16 ns/pF) CL
CPD → On 5 210 420 ns 183 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 85 170 ns 74 ns + (0,23 ns/pF) CL
15 65 125 ns 57 ns + (0,16 ns/pF) CL
5 170 340 ns 143 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 70 140 ns 59 ns + (0,23 ns/pF) CL
15 50 100 ns 42 ns + (0,16 ns/pF) CL
CPU → TCU 5 125 250 ns 98 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 50 100 ns 39 ns + (0,23 ns/pF) CL
15 35 70 ns 27 ns + (0,16 ns/pF) CL
5 95 185 ns 68 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 40 80 ns 29 ns + (0,23 ns/pF) CL
15 30 60 ns 22 ns + (0,16 ns/pF) CL
CPD → TCD 5 140 280 ns 113 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 55 110 ns 44 ns + (0,23 ns/pF) CL
15 40 80 ns 32 ns + (0,16 ns/pF) CL
5 100 195 ns 73 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 40 85 ns 29 ns + (0,23 ns/pF) CL
15 30 65 ns 22 ns + (0,16 ns/pF) CL
MR → On 5 195 390 ns 168 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 80 160 ns 69 ns + (0,23 ns/pF) CL
15 60 120 ns 52 ns + (0,16 ns/pF) CL
MR → TCU 5 145 285 ns 118 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 60 115 ns 49 ns + (0,23 ns/pF) CL
15 45 90 ns 37 ns + (0,16 ns/pF) CL
MR → TCD 5 365 730 ns 338 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 130 265 ns 119 ns + (0,23 ns/pF) CL
15 100 205 ns 92 ns + (0,16 ns/pF) CL
PL → On 5 185 360 ns 158 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 75 150 ns 64 ns + (0,23 ns/pF) CL
15 55 110 ns 47 ns + (0,16 ns/pF) CL

January 1995 6
Philips Semiconductors Product specification

HEF40192B
4-bit up/down decade counter
MSI

VDD TYPICAL EXTRAPOLATION

SYMBOL MIN. TYP. MAX.
V FORMULA
5 145 290 ns 118 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 60 120 ns 49 ns + (0,23 ns/pF) CL
15 45 90 ns 37 ns + (0,16 ns/pF) CL

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

VDD TYPICAL EXTRAPOLATION

SYMBOL MIN. TYP. MAX.
V FORMULA
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
5 60 120 ns 10 ns + (1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
Set-up time 5 160 80 ns
Pn → PL 10 tsu 60 30 ns
15 50 25 ns
Hold time 5 10 −70 ns
Pn → PL 10 thold 5 −25 ns
15 5 −20 ns
Minimum CPU or CPD 5 150 75 ns
pulse width; LOW 10 tWCPL 50 25 ns
15 35 20 ns
Minimum MR 5 180 90 ns
pulse width; HIGH 10 tWMRH 70 35 ns
15 60 30 ns see also waveforms
Minimum PL 5 120 60 ns Fig.6
pulse width; LOW 10 tWPLL 45 20 ns
15 30 15 ns
Recovery time 5 125 65 ns
for MR 10 tRMR 70 35 ns
15 50 25 ns
Recovery time 5 90 45 ns
for PL 10 tRPL 35 15 ns
15 25 10 ns
Maximum clock 5 2,5 5 MHz
pulse frequency 10 fmax 7 14 MHz
15 9 18 MHz

January 1995 7
Philips Semiconductors Product specification

HEF40192B
4-bit up/down decade counter
MSI

Fig.6 Waveforms showing recovery times for PL and MR, minimum pulse widths for CPU, CPD, PL and MR,
and set-up and hold times for P to PL. Set-up times and hold times are shown as positive values but may
be specified as negative values.

January 1995 8
Philips Semiconductors Product specification

HEF40192B
4-bit up/down decade counter
MSI

Fig.7 Timing diagram.

APPLICATION INFORMATION
Some examples of applications for the HEF40192B are:
• Up/down difference counting
• Multistage ripple counting
• Multistage synchronous counting.

Fig.8 Example of cascaded HEF40192B ICs.

January 1995 9