Seqential Part-1 New

Unit-IV
Sequential Logic Circuits
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Unit Outcomes
 Use relevant triggering technique for the given digital

circuit.
 Use the given flip flop to construct the specific type of

counter.
 Use excitation table of the given flip flop to design

synchronous counter.
 Design the specified modulo-N counter using IC 7490.
 Construct ring/twisted ring counter using the given flip

flop.
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Combinational Circuits Vs Sequential Circuits
Logic circuits are classified into two groups:

Combinational logic circuits Logic gates make decisions
Basic building
blocks include Gates:
Sequential logic circuits

Flip Flops have memory
Basic building blocks

include FLIP-FLOPS:
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x1 z1
Combinational
xn logic zm
(a)
x1 z1
xn Combinational zm
logic
y1 yr Yr Y1
Memory
(b)
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Combinational Circuits Sequential Circuits
 In combinational circuits,  In sequential circuits, the

the output variables at any output variables at any
instant of time are instant of time are
dependent only on the dependent not only on the
present input variables. present input variables but
also past output variables.
 Memory unit is not required  Memory unit is required to

in combinational circuits. store the past history.
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Combinational Circuits Sequential Circuits
 Combinational circuits are  Sequential circuits are

faster because the delay slower than combinational
between the input and circuits.
output is due to
propagation delay of gates
only.
 Sequential circuits are

 Combinational circuits are
comparatively harder to
easy to design.
design.
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Unit IV – Sequential Logic Circuit
 Basic Memory Cell: RS Latch- using NAND & NOR.
 Triggering Methods: Edge Trigger & Level Trigger.
 SR Flip Flops: SR Flip Flop, Clocked SR FF with preset & clear,
Drawbacks of SR FF
 JK Flip Flops: Clocked JK FF with preset & clear, Race around
condition in JK FF, Master Slave JK FF, D and T type Flip Flop,
Excitation Tables of Flip Flops, Block schematic and function table
of IC 7474, IC 7475.
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What is exactly Memory?
A memory should support at least three
operations:
It should be able to hold a value
You should be able to read the value that is saved
You should be able to change that value
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Simple case - One bit memory
We will start with simplest case, a one bit

memory:
It should be able to hold a single bit, 0 or 1.
You should be able to read the bit that is saved.
You should be able to change the bit.

- You can set the bit to 1
- You can reset or clear the bit to 0.
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Basic Idea of Storage
 How can a circuit remember anything, when its just a
bunch of gates that produce outputs according to
inputs?
 The idea is to make a loop in a circuit, so outputs are
also inputs.
“1”
bistable cell
(Stored Value= state)
“0”
 Two inverters and a feedback loop form a “Static ”
storage cell
 The cell will hold value as long as it has power applied
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Basic Idea of Storage
How to get a new value into a storage cell?

Selectively break feedback path
Load new value into cell
“remember”
“load”
“data” “Stored Value”
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One Bit Memory Cell
 The output of each gate is connected to the input of the

other gate . This feedback connection is known as “Flip
Flop”.
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One Bit Memory Cell
 It has two stable states which are known as 1

(HIGH) state and 0 (LOW) state.
 Since flip flop has two stable states, it is called a
Binary or Bistable.
 Similarly it stores 1 bit information; either 1 or 0.
 it is a 1 bit memory unit or a 1 bit storage cell.
 Since information is locked or latched, 1 bit
memory cell is also known as LATCH.
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Latch
 Latch are the bi-stable devices which responds to the

change of input logic levels as they occur.
Q Q is the primary
output
Inputs Latch
Q is its
Q complementary
output
It is said to be in SET state if output Q is High
It is said to be in RESET state if output Q is Low
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RS Latch using NOR
R
Q
Q
S
Circuit Diagram
Outputs
R Q
Inputs
S Q
BRSREDDY
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RS Latch using NOR Logic Table
S R Qn Qn+1 State
0 0 0 0
No Change
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 X Indetermine
1 1 1 X
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RS Latch using NAND
R
Q
Circuit Diagram
Outputs
R Q
Inputs
S Q
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Symbol
RS Latch using NAND
Logic Table
S R Qn Qn+1 State
0 0 0 X
Indetermine
0 0 1 X
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 0 No Change
1 1 1 1
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RS Latch using NAND with additional circuitry
R S’
Q
S
R’
Circuit Diagram
R Q
Outputs
Inputs
S Q
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Symbol
RS Latch using NAND with additional circuitry Logic Table
S R Qn Qn+1 State
0 0 0 0
No Change
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 X Indetermine
1 1 1 X
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Drawbacks of SR FF
of IC 7474, IC 7475.
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Clock
 A clock is a special device that whose output

continuously alternates between 0 and 1.
 The time it takes the clock to change from 1 to 0 and

back to 1 is called the clock period, or clock cycle time.
 Clocks are often used to synchronize circuits.
clock period
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Triggering
 Sequential circuits are dependent on clock pulses applies to

their inputs.
 The result of flip-flop responding to a clock input is called
clock pulse triggering, of which there are four types. Each
type responds to a clock pulse in one of four ways:-
- High level triggering
- Low level triggering
- Positive edge triggering
- Negative edge triggering
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High Level Triggering
A flip flop who responds to a clock signal during

the time at which it is in the logic High state.
Triggers on High clock level
CLK
Symbol
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Low Level Triggering

the time at which it is in the logic Low state.
Triggers on Low clock level

Q
CLK
Symbol
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Positive Edge Triggering

Low to High transition of clock pulse.
Triggers on this edge of clock pulse
CLK
Symbol
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Negative Edge Triggering

High to Low transition of clock pulse.
Triggers on this edge of clock pulse
CLK
Q
Symbol
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Drawbacks of SR FF
of IC 7474, IC 7475.
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Gates Vs Flip Flops
 Gates are the building block of the logic circuits.

Their primary function is to perform decision
making operations.
 Flip-flops are the building blocks of the digital

circuits. Their primary function is to store the
binary bits.
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Flip Flops
 A flip-flop is a bi-stable device, with inputs, that remains

in a given state as long as power is applied and until input
signals are applied to cause its output to change.
 There are four basic different types of flip-flops:
- SR Flip Flop
- D Flip Flop
- JK Flip Flop
- T Flip Flop
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SR Flip Flop
R
Q R Q
SR-FF
S Q
Q
S
Symbol
Circuit Diagram
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SR Flip Flop
Logic Table
S R Qn Qn+1 State
0 0 0 X Indetermine
0 0 1 X
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 0 No Change
1 1 1 1
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Drawbacks of SR FF
of IC 7474, IC 7475.
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Clocked SR Flip Flop
S
R’
Q R Q
CLK
CLK SR-FF
S Q
Q
R
S’
Circuit Diagram Symbol
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Logic Table
CLK S R Q Q State
0 0 Q Q No Change
0 1 0 0 Reset
1 0 0 1 Set
1 1 X X Prohibited
X X Q Q No Change
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Synchronous Inputs
 The S and R (for SR FF), D (for D FF), J and K (JK FF),

and so on….,inputs are control inputs.
 These inputs are also called “Synchronous Inputs”

because the action of these inputs are
synchronized with the action of clock.
 The flip flop changes state only on the application

of clock signal.
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Asynchronous Inputs
 In addition to synchronous inputs the flip flops
have one or more asynchronous inputs .
 These asynchronous inputs operate independently
of control and clock input.
 Two asynchronous inputs are PRESET and CLEAR
 These are mostly active LOW inputs.

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Clocked SR Flip Flop with Clear and Preset Inputs
PR
S Q
CLK
Q
R
CR
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Asynchronous Inputs: PRESET and CLEAR
Sr. Action Function/Operation

No.
1 PRESET  1 Both these asynchronous inputs are inactive. The flip
flop responds to synchronous inputs.
CLEAR  1
2 PRESET  0 The PRESET is activated and Q is immediately set to
1 irrespective of synchronous inputs. The clock
CLEAR  1 input cannot affect the flip flop when PR=0.
3 The CLEAR is activated and Q is immediately cleared
PRESET  1
to 0 irrespective of synchronous inputs. The clock
CLEAR  0 input cannot affect the flip flop when CR=0.
4 This condition should not be used as it leads to race

PRESET  0
condition
CLEAR  0
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Clocked SR Flip Flop with Clear and Preset Inputs
PR
Inputs O/P
Comment
R Q
CLK CR PR S R Q Q
SR-FF 1 1 0 0 Q Q No Change
S Q 1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
CR
1 1 1 1 X X Invalid
X 0 1 X X 0 1 Clear
X 1 0 X X 1 0 Preset
X 0 0 X X X X Invalid
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Synchronous Sequential Circuits Vs Asynchronous
Sequential Circuits
Synchronous Seq Circuits Asynchronous Seq Circuits
 In Synchronous circuits,  In Asynchronous circuits,

memory elements are memory elements are
clocked FFs. either unclocked FFs or time
delay elements.
 In Synchronous circuits, the  In Asynchronous circuits,

change in input signals can the change in input signals
affect memory elements can affect memory
upon activation of clock elements at any instant of
signals. time.
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Synchronous Sequential Circuits Vs Asynchronous
Sequential Circuits
Synchronous Seq Circuits Asynchronous Seq Circuits
 The maximum operating  Because of the absence of

speed of the clock depends the clock, asynchronous
on time delays involved circuits can operate faster
than synchronous circuits.
 Easier to design  More difficult to design
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Drawbacks of SR FF
of IC 7474, IC 7475.
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Drawbacks of SR Flip Flop
If both inputs are pulled down to logic level 0,
both outputs will be at logic level 1. This state
should not be allowed to occur in flip-flops.
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Drawbacks of SR FF
of IC 7474, IC 7475.
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Level Triggered JK Flip Flop SR Flip Flop
Q
J R’
3
1 Q
CLK
S’ 2 Q
4
K
Q
J Q
Circuit Diagram of Level Triggered JK Flip Flop CLK JK-FF
K Q
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Level Triggered JK Flip Flop
Inputs Outputs
State
CLK J K Qn  1 Qn  1
0 X X Qn Qn Flip Flop is Disabled

Qn (No Change)
1 0 0 Qn
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Qn Qn Toggle
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Timing Diagram of Level Triggered JK Flip Flop
Race around
1 condition
CLK t
0
1
J 0
t
1
K t
0
1
Q t
0
J=1, J=0,
K=0, K=1,
CLK=1 CLK=1
J=1, J=1,
K=1, K=1,
CLK=0 CLK=1
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Race Around Condition in JK Flip Flop
 The “Race Around Condition” that we are going to explain
occurs J=K=1 i.e. when the flip flop is in the toggle mode.
 When J=1, K=1 and CLK=1, hence the JK flip flop is in the
toggle mode and Q becomes low and Q becomes high.
 These changed outputs get applied at the inputs of NAND
gates 3 and 4 of the JK FF. thus the new inputs to gates 3 and 4
are:
NAND – 3 : J=1, CLK=1, Q = 1
NAND – 4 : K=1, CLK=1, Q = 0
 Hence R’ will become 0 and S’ will become 1.
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Race Around Condition in JK Flip Flop
 Therefore after a time period corresponding to the

propagation delay, the Q and Q outputs will change to,
Q = 1 and Q =0
 These changed output again get applied to the inputs of

NAND-3 and 4 and the outputs will toggle again.
 Thus as long as J=K=1 and CLK=1, the outputs will keep

toggling indefinitely as shown in figure. This multiple,
toggling in the JK Flip flop is called as “Race Around
Condition”. It must be avoided
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How to Avoid Race Around Condition in JK Flip Flop
The race around condition in JK flip flop can be
avoided by
1. Using Edge Triggered JK Flip Flop
2. Using Master Slave JK Flip Flop
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Edge Triggered JK Flip Flop SR Flip Flop
Q
J R’
Q
C
CLK
R
S’ Q
K
Q
Circuit Diagram of Edge Triggered JK Flip Flop J Q
CLK JK-FF
K Q
Symbol
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Edge Triggered JK Flip Flop
Inputs Outputs
State
CLK J K Qn  1 Qn  1
0 or 1 X X Qn Qn
Flip Flop is Disabled
X X Qn Qn
(No Change)
0 0 Qn Qn
0 1 0 1 Reset
1 0 1 0 Set
1 1 Qn Qn Toggle
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using Edge Triggered JK Flip Flops?
 For the racing around to take place, it is necessary to have the
enable input high along with J=K=1.
 As the enable input remains high for a long time in a JK Flip
Flop, the problem of multiple toggling arises.
 But in edge triggered JK Flip Flop, the positive clock pulse is
present only for a very short time.
 Hence by the time changed outputs return back to the inputs
of NAND gates 3 and 4, the clock pulse has died down to zero.
Hence the multiple toggling can not take place.
 Thus the edge triggering avoids the race around condition.
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Master Slave JK Flip Flop
S
J Q1
Q
CLK
Q
K Q1
R
Master Slave
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Timing Diagram of Master Slave JK Flip Flop
CLK
K
Master Master Master
Active Master
Master Active Active Active
o/p Q1 or S
Master
o/p Q1or R
Slave
o/p Q or S
Slave Slave Slave
Active Active Active
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using MS JK Flip Flops?
 When Clock=1, J=1, K=1, Master Active and slave becomes
inactive. Outputs of master will toggle. So S and R also will be
inverted.
 When clock = 0: Master inactive, slave active. Outputs of the
slave will toggle.
 These changed output are returned back to the master inputs.
 But since clock=0, the master is still inactive. So it does not
respond to these changed outputs.
 This avoids the multiple toggling which leads to the race
around condition. Thus Master Slave JK Flip Flop will avoid the
race around condition.
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Clocked JK Flip Flop with Clear and Preset Inputs
PR
J Q
CLK
PR
K Q
J Q
JK-FF
CLK
K Q
CR
CR
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Clocked JK Flip Flop with Clear and Preset Inputs
Inputs
Outputs
Asynchronous Synchronous Comment
PR CR CLK J K Q Q
0 0 X X X 1 1 Prohibited
0 1 0 X X 1 0 Preset
1 0 0 X X 0 1 Clear
1 1 0 0 Q Q No Change
1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
1 1 1 1 Q Q Toggle
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Drawbacks of SR FF
condition in JK FF, Master Slave JK FF, D Flip Flop and T type Flip
Flop, Excitation Tables of Flip Flops, Block schematic and function
table of IC 7474, IC 7475.

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D Flip Flop
D S
CLK

D Q
D-FF
CLK Q
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D Flip Flop
Inputs Output
Comment
CLK D Qn  1 Qn  1
Last Value or No
0 X Qn Qn
Change
1 0 0 1 Reset
1 1 1 0 Set
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D Flip Flop with Preset and Clear Inputs
PR
D S
CLK
PR
Q
D Q
R
D-FF
CLK Q
CR
CR
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D Flip Flop with Preset and Clear Inputs
Inputs Output
Comment
PR CR CLK D Qn  1 Qn  1
0 0 X X Qn Qn Avoid
0 1 X X 1 0 Preset
1 0 X X 0 1 Clear
1 1 0 X Qn Qn No Change
1 1 1 0 0 1 Reset
1 1 1 1 1 0 Set
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Drawbacks of SR FF
of IC 7474, IC 7475.
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T Flip Flop
J R’
T
Q
CLK
K S’ Q
T Q
T-FF
CLK Q
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T Flip Flop
Inputs Output
Comment
CLK T Qn  1 Qn  1
0 X Qn Qn No Change
1 0 Qn Qn No Change
1 1 Qn Qn Toggle
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T Flip Flop with Preset and Clear Inputs
PR
J
T
Q
CLK
PR
K
Q
T Q
T-FF
CR CLK Q
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85
T Flip Flop with Preset and Clear Inputs
Inputs Output
Comment
PR CR CLK T Qn  1 Qn  1
0 0 X X Qn Qn Avoid
0 1 X X 1 0 Preset
1 0 X X 0 1 Clear
1 1 0 X Qn Qn No Change
1 1 1 0 Qn Qn No Change
1 1 1 1 Qn Qn Toggle
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Applications of Flip Flops
 Elimination of Keyboard Debounce

 As a memory element
 In various types of registers
 In counters
 As delay element
 Parallel Data storage
 Serial Data Storage
 Serial to Parallel Conversion
 Parallel to Serial Conversion
 Frequency Division
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Drawbacks of SR FF
of IC 7474, IC 7475.
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Excitation Tables of Flip Flops
Logic tables show the state of the output(s) of
a logic circuit as a function of its inputs at the
same time.
Since, clocked digital systems have memory,
their behavior depends on inputs in the past
as well as the present values of the inputs.

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Excitation Tables of Flip Flops
 Thus, flip-flops cannot be described by simple truth tables.
Instead, we use excitation or transition tables. These show:
 output before the clock transition — often labelled Qn

 inputs at the clock transition — such as S and R
 occasionally the type of clock transition – positive/negative
edge-triggered
 the resulting output after the clock transition — often
labelled Qn+1
 It is important to remember that Qn and Qn+1 describe the

same signal but at different times. The notation can vary, e.g.
Q0 and Q instead.
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Excitation Table of SR Flip Flop
S R Qn+1
0 0 Qn
0 1 0 Truth Table
1 0 1
1 1 ?
Present Next State Required Inputs
State O/P O/P
Qn Qn+1 S R
Excitation Table 0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
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 0  0 transition: If the present state of the FF is 0

and if it has to remain 0 when a clock pulse is applied,
the inputs can be either S=0, R=0 (no change condition)
or S=0, R=1 (Reset condition). Thus, S has to be 0 but R
can be either 0 or 1. So SR=0X for this transition.
and if it has to go 1 state when a clock pulse is applied,
the inputs have to be S=1 and R=0 (set condition). So
SR=10 for this transition.
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 1  0 transition: If the present state of the FF is 1 and

if it has to go to 0 state when a clock pulse is applied,
the inputs have to be S=0 and R=1 (Reset condition). So
SR=01 for this transition.
and if it has to remain 1 when a clock pulse is applied,
the inputs can be either S=0, R=0 (no change condition)
or S=1, R=0 (set condition). Thus, R has to be 0 but S
can be either 0 or 1. So SR=X0 for this transition.
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Excitation Table of JK Flip Flop
J K Qn+1
0 0 Qn
0 1 0 Truth Table
1 0 1
1 1 Qn
Present Next State Required Inputs
State O/P O/P
Qn Qn+1 J K
Excitation Table 0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
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 0  0 transition: The present state of the FF is 0 and

it has to remain 0 after the clock pulse. This can
happen with either J=0, K=0 (no change condition) or
J=0, K=1 (reset condition). Thus, J has to be 0 but K can
be either 0 or 1. So JK=0X for this transition.
it has to go 1 state after the clock pulse. This can
happen with either J=1, K=0 (set condition) or J=1, K=1
(toggle condition). Thus, J has to be 1 but K can be
either 0 or 1. So JK=1X for this transition.
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it has to go to 0 after the clock pulse. This can happen
with either J=0, K=1 (reset condition) or J=1, K=1
(toggle condition). Thus, K has to be 1 but J can be
either 0 or 1. So JK=X1 for this transition.
it has to remain in 1 state after the clock pulse. This can
happen with either J=0, K=0 (no change condition) or
J=1, K=0 (set condition). Thus, K has to be 0 but J can
be either 0 or 1. So JK=X0 for this transition.
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Excitation Table of D Flip Flop
D Qn+1
0 0 Truth Table
1 1
Present State Next State Required

O/P O/P Inputs
Qn Qn+1 D
Excitation Table 0 0 0
0 1 1
1 0 0
1 1 1
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Excitation Table of D Flip Flop
For a D Flip Flop, the next state is always equal
to the D input and it is independent of the
present state. Therefore, D must be 0 if Qn+1 has
to be 1 regardless of the value of Qn.
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Excitation Table of T Flip Flop
T Qn+1
Truth Table
0 Qn
1 Qn
Present State Next State Required

O/P O/P Inputs
Qn Qn+1 T
Excitation Table 0 0 0
0 1 1
1 0 1
1 1 1
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Excitation Table of T Flip Flop
For a T Flip Flop, when the input T=1, the state

of the Flip flop is complemented and when T=0,
the state of the Flip Flop remains unchanged.
Thus, for 0  0 and 1  1 transitions T must
be 0 and for 0  1 and 1  0 transitions T
must be 1.
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Conversion of Flip Flop
S R Flip to J K Flip Flop:
S Q
J
CLK SR-FF
K
R Q
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J K Flip to S R Flip Flop:
S J Q
CLK JK-FF
R K Q
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S R Flip to D Flip Flop:
D S Q
SR-FF
CLK
R Q
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D Flip to S R Flip Flop:
S
D Q
CLK D-FF
R
Q
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J K Flip to T Flip Flop:
T J Q
CLK JK-FF
K Q
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J K Flip to D Flip Flop:
D J Q
JK-FF
CLK
K Q
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D Flip to J K Flip Flop:
J D Q
CLK D-FF
Q
K
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Drawbacks of SR FF
of IC 7474, IC 7475.
9/11/2018 BRSREDDY 108
IC 7474 – Dual D Type Positive Edge triggered FF
 IC 7474 – Dual Positive Edge triggered D Flip Flop with

PRESET and CLEAR.
 These IC contain two independent D-type positive edge
triggered flip flops.
9/11/2018 BRSREDDY 109

PR PR
4 10
2 5 12 9
D Q D Q
D-FF D-FF
CLK Q CLK Q
3 6 11 8
1 13
CR CR
+Vcc = Pin 14
GND = Pin 7
9/11/2018 BRSREDDY 110

Inputs Outputs
Operating Mode
PR CR D Q Q
Preset L H X H L
Clear H L X L H
Undetermined L L X H H
Set H H H H L
Reset H H L L H
9/11/2018 BRSREDDY 111

IC 7476- Dual Master-Slave J-K Flip-Flops with Clear,
Preset, and Complementary Outputs
 This device contains two independent positive pulse triggered J-
K flip-flops with complementary outputs.
 The J and K data is processed by the flip-flop after a complete
clock pulse.
 While the clock is LOW the slave is isolated from the master. On
the positive transition of the clock, the data from the J and K
inputs is transferred to the master.
 While the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave.
 The logic state of J and K inputs must not be allowed to change
while the clock is HIGH. The data is transferred to the outputs on
the falling edge of the clock pulse.
 A LOW logic level on the preset or clear inputs will set or reset
the outputs regardless of theBRSREDDY
9/11/2018 other inputs. 112
IC 7476 – Dual JK Flip Flop with Set and Clear
Logic Diagram:
9/11/2018 BRSREDDY 113

PR PR
2 7
16 15 12 11
K Q K Q
CLK
1 D-FF CLK
6 D-FF
J Q J Q
4 14 9 10
3 8
CR CR
+Vcc = Pin 5
GND = Pin 13
9/11/2018 BRSREDDY 114

Inputs Outputs
Operating Mode
PR CR J K Q Q
Preset L H X X H L
Clear H L X X L H
Undetermined L L X X H H
Toggle H H H H Q Q
Reset H H L H L H
Set H H H L H L
Hold H H L L Q Q
9/11/2018 BRSREDDY 115
IC 7475 - Quad Latches
 These latches are ideally suited for use as temporary storage
for binary information between processing units and
input/output or indicator units.
 Information present at a data (D) input is transferred to the Q
input when the enable (G) is high, and the Q output will
follow the data input as long as the enable remains high.
 When the enable goes low, the information (that was present
at the data input at the time the transition occurred) is
retained at the Q output until the enable is permitted to go
high.
 These latches feature complementary Q and Q outputs from a
4-bit latch and are available in 16-pin packages.
9/11/2018 BRSREDDY 116

Logic Diagram:
9/11/2018 BRSREDDY 117

Function Table:
9/11/2018 BRSREDDY 118

IC 74373- Octal D-Type Transparent Latches and Edge-
Triggered Flip-Flops
 These 8-bit registers feature totem-pole TRI-STATE outputs
 designed specifically for driving highly-capacitive or relatively
low-impedance loads.
 The high-impedance state and increased high-logic level drive
provide these registers with the capability of being connected
directly to and driving the bus lines in a bus-organized system
without need for interface or pull-up components.
 They are particularly attractive for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working
registers.
9/11/2018 BRSREDDY 119

Features:
Choice of 8 latches or 8 D-type flip-flops in a

single package
TRI-STATE bus-driving outputs
Full parallel-access for loading
Buffered control inputs
P-N-P inputs reduce D-C loading on data lines

9/11/2018 BRSREDDY 120
Internal Diagram:
9/11/2018 BRSREDDY 121

Function Table:
9/11/2018 BRSREDDY 122

Logic Diagram:
9/11/2018 BRSREDDY 123

 Shift Register: Logic diagram of 4 bit shift registers - SISO, SIPO,
PIPO, PISO, 4 Bit Universal Shift Registers.
 Counters: Asynchronous Counter: 4 bit Ripple Counter, 4 Bit
Up/Down Counter, Modulus of counter, Synchronous Counter:
Design of 4 bit Synchronous up/down counter. Decade Counter:
Block schematic of IC 7490, IC 7490 as MOD-N Counter, Ring
Counter and Twisted Ring Counter
9/11/2018 BRSREDDY 124

Serial form of Data Vs Parallel Form of Data
 Data may be available in Parallel form or Serial form.
 Multi bit data is said to be in parallel form when all the

bits are available (accessible) simultaneously.
 The data is said to be in serial form when data bits

appear sequentially (one after another in time) at a
single terminal.
 Data may also be transferred in parallel form or in

serial form.
9/11/2018 BRSREDDY 125

Data Transmission Serial/Parallel
 Parallel data transfer is the simultaneous transmission

of all bits of data from one device to another.
 Serial data transfer is the transmission of one bit of

data at time from one device to another.
 Serial data must be transmitted under the

synchronization of a clock, since clock provides the
means to specify the time at which each new bit is
sampled
9/11/2018 BRSREDDY 126

Register
 As a flip flop can store only one bit of data, a 0 or a 1, it is
referred as a single bit register.
 When more bits of data are to be stored, a number of FFs
used.
 A register is a set of FFs used to store binary data.
 The storage capacity of a register is the number of bits (1s
and 0s) of digital data it can retain.
 A register may output data either in serial form or in
parallel form.
9/11/2018 BRSREDDY 127

Shift Register
 A shift register is a very important digital building blocks. It
has innumerable applications.
 Shift registers are a type of logic circuits closely related to

counters.
 They are used basically for storage and transfer of digital

data.
 The basic difference between a shift register and a counter

is that, a shift register has no specified sequence of states
whereas a counter has a specified sequence of states.
9/11/2018 BRSREDDY 128
Shift Registers
 Multi-bit register that moves stored data bits left/right
( 1 bit position per clock cycle)
 Shift Left is towards MSB

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 1 1 1 LSI 1 1 1 LSI
 Shift Right (or Shift Up) is towards MSB
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
RSI 0 1 1 1 RSI 0 1 1
9/11/2018 BRSREDDY 129

Flip Flop as Storage Element
Inputs Output
D Q
Comment
CLK D Qn  1 Qn  1
CLK D-FF Last Value
Qn Qn
0 X or No
Q
Change
0 0 1 Reset
1 1 0 Set
9/11/2018 BRSREDDY 130

Basic Data Movements in Shift Registers
9/11/2018 BRSREDDY 131

Types of Shift Registers
 SISO – Serial In Serial Out Shift Register
 SIPO – Serial In Parallel Out Shift Register
 PISO – Parallel In Serial Out Shift Register
 PIPO – Parallel In Parallel Out Shift Register
 Bi-directional Shift Register
 Universal Shift Register

9/11/2018 BRSREDDY 132
9/11/2018 BRSREDDY 133

SISO – Serial In Serial Out Shift Register (Shift Left)
Serial Data Serial Data
Input Output
DIN D0 Q0 D1 Q1 D2 Q2 D3 Q3
D-FF0 D-FF1 D-FF2 D-FF3
Q0 Q1 Q2 Q3
CLK
9/11/2018 BRSREDDY 134

Serial Input
CLK Q3 Q2 Q1 Q0
DIN = D0
Initially 0 0 0 0
1st 0 0 0 1 1
2nd 0 0 1 1 1
3rd 0 1 1 1 1
4th 1 1 1 1 1
9/11/2018 BRSREDDY 135

1111
136
FF-3 Sets
-------------------------------------------------------------------------------------
0111
FF-2 Sets
-------------------------------------------------------------------------------------
0011
BRSREDDY
FF-1 Sets
-------------------------------------------------------------------------------------
0001
FF-0 Sets
-------------------------------------------
0000
9/11/2018
Clock
DIN
Q0
Q3
Q1
Q2
SISO – Serial In Serial Out Shift Register (Shift Right)
Serial Data Serial Data
Input Output
Q3 Q2 Q1 Q0
CLK
9/11/2018 BRSREDDY 137

Serial Input
CLK DIN = D0 Q3 Q2 Q1 Q0
Initially 0 0 0 0
1st 1 1 0 0 0
2nd 1 1 1 0 0
3rd 1 1 1 1 0
4th 1 1 1 1 1
9/11/2018 BRSREDDY 138

1111
139
FF-0 Sets
-------------------------------------------------------------------------------------
1110
FF-1 Sets
-------------------------------------------------------------------------------------
1100
BRSREDDY
FF-2 Sets
-------------------------------------------------------------------------------------
1000
FF-3 Sets
-------------------------------------------
0000
9/11/2018
Clock
DIN
Q3
Q0
Q2
Q1
9/11/2018 BRSREDDY 140

SIPO – Serial In Parallel Out Shift Register
Serial Data
Input
Q0 Q1 Q2 Q3
CLK
Q0 Q1 Q2 Q3
Parallel Outputs
9/11/2018 BRSREDDY 141
9/11/2018 BRSREDDY 142

PIPO – Parallel In Parallel Out Shift Register
Parallel Data Input
D0 D1 D2 D3
D0 Q0 D1 Q1 D2 Q2 D3 Q3
Q0 Q1 Q2 Q3
CLK
Q0 Q1 Q2 Q3
Parallel Outputs
9/11/2018 BRSREDDY 143
9/11/2018 BRSREDDY 144

PISO – Parallel In Serial Out Shift Register
9/11/2018 BRSREDDY 145

Load Mode:
 When the Shift / Load line is Low, the AND gates G1, G2
and G3 become active. They will pass D1, D2, and D3
bits to the corresponding Flip Flops.
 On the low going edge of clock, the binary inputs D0,

D1, D2 and D3 will get loaded into corresponding flip
flops. Thus parallel loading takes place.
9/11/2018 BRSREDDY 146

Shift Mode:
 When the Shift / Load line is High, the AND gates G1, G2
and G3 become inactive. Hence parallel loading of
data becomes impossible.
 But AND gates G4, G5 and G6 become active.
Therefore the shifting of data from left to right bit by
bit on application of clock pulses
 Thus the parallel in serial out operation takes place
9/11/2018 BRSREDDY 147

9/11/2018 BRSREDDY 148

4 Bit Bi-directional Shift Register
 A bi directional shift register is one in which the data
bits can be shifted from left to right or from right to
left.
9/11/2018 BRSREDDY 149

Serial shift
Left input
Serial shift
right input
9/11/2018 BRSREDDY 150

With M = 1: Shift Right Operation
 If M=1, then the AND gates 1,3,5 and 7 are enabled

whereas the remaining AND gates 2,4,6 and 8 will be
disabled.
 Hence the data at shift right input is shifted to right bit

by bit from FF-3 to FF-0 on the application of clock
pulses.
 Thus with M=1 we get the serial right shift operation.

9/11/2018 BRSREDDY 151
With M = 0: Shift Left Operation
 If M=0, then the AND gates 2,4,6 and 8 are enabled

whereas the remaining AND gates 1,3,5 and 7 will be
disabled.
 Hence the data at shift left input is shifted to left bit by

bit from FF-0 to FF-3 on the application of clock pulses.
 Thus with M=0 we get the serial left shift operation.
9/11/2018 BRSREDDY 152

4 Bit Universal Shift Register
 A register capable of shifting in one direction only is a

unidirectional shift register.
 One that can shift in both directions is a bidirectional shift
register.
 If the register has both shifts and parallel load capabilities,
it is referred to as a “Universal Shift Register”.
 So universal shift register is a bidirectional shift register,
whose output can be either in serial form or in parallel
form and whose output also can be either in serial form or
parallel form.
9/11/2018 BRSREDDY 153
4 Bit Universal Shift Register
9/11/2018 BRSREDDY 154

Applications of Shift Registers
 For temporary data storage
 As a delay line
 Parallel to Serial Converter
 Serial to Parallel Converter
 Ring Counter
 Twisted Ring Counter (Johnson Counter)

9/11/2018 BRSREDDY 155
9/11/2018 BRSREDDY 156

Counter
 A digital counter is a set of flip flops whose states

changes in response to pulses applied at the input to
counter.
 The FFs are interconnected such that their combined

state at any time is the binary equivalent of the total
number of pulses that have occurred up to that time.
 Thus, as its name implies, a counter is used to count

pulses.
9/11/2018 BRSREDDY 157
Types of Counters
Counters
Asynchronous Counters Synchronous Counters
 Asynchronous or Ripple Counter: For these counters the

external clock signal is applied to one Flip Flop and then the
output of preceding flip flop is connected to the clock of the
next flip flop.
 Synchronous Counter: In synchronous counters all the flip flops

receive the external clock pulse simultaneously.
9/11/2018 BRSREDDY 158
9/11/2018 BRSREDDY 159

Asynchronous Vs Synchronous Counter
Asynchronous Counter Synchronous Counter
 Output of the preceding Flip  There is no connection

Flop is connected to clock of between output of preceding
the next Flip Flop. Flip Flop and Clock of next
one.
 All the Flip Flops are not  All the Flip Flops receive clock
clocked simultaneously. signal simultaneously.
 Logic circuit is simple.  With increase in number of

states, the logic circuit
becomes complicated.
9/11/2018 BRSREDDY 160
Asynchronous Vs Synchronous Counter
Asynchronous Counter Synchronous Counter
 P.D. = n X (td) where n is  P.D. = (td)FF + (td)Gate ,It is much

number of Flip Flops and td is shorter than that of
propagation delay of flip flop. asynchronous counter.
 Frequency of operation is low  Frequency of operation is

because of the long high due to shorter
propagation delay propagation delay.
9/11/2018 BRSREDDY 161

2 Bit Asynchronous or Ripple Up Counter
Logic 1
TA PR QA TB PR QB
CLK
FF-A FF-B
QA QB
CR CR
Logic 1
(LSB) QA QB (MSB)
Counter Outputs
9/11/2018 BRSREDDY 162
Counter Outputs Decimal

State Equivalent
Clock
QB QA Number of Counter
(MSB) (LSB) Output
Initially 0 0 - 0
1st 0 1 1 1
2nd 1 0 2 2
3rd 1 1 3 3
4th 0 0 4 0
9/11/2018 BRSREDDY 163
Clock
QA 0 1 0 1 0
QB 0 0 1 1 0
Counter O/P
QB QA
00 01 10 11 00
0 1 2 3 0
9/11/2018 BRSREDDY 164

 Number of States: 2 Bit ripple counter has four distinct

states of outputs namely 00,01,10 and 11.
- In general the number of states = 2n, where n is the
number of flip flops.
 Maximum Count is 3 (decimal) i.e. 11 binary
- In general the maximum count = (2n-1)
9/11/2018 BRSREDDY 165

State diagram of 2 bit Ripple Counter
 The state diagram of a counter represents the states of a

counter graphically.
 For example, for a 2 bit ripple counter the state diagram is

shown below.
Initial
State
0 1
3 2
Arrow indicates the

direction
9/11/2018 BRSREDDY 166
Logic 1
TA PR QA TB PR QB TC PR QC
CLK
FF-A FF-B FF-C
QA QB QC
CR CR CR
Logic 1
QA QB QC
(LSB) (MSB)
9/11/2018 BRSREDDY utputs 167

Flip Flop Outputs
Decimal
Clock QC QA State
QB Equivalent
(MSB) (LSB)
Initial 0 0 0 1 0
1st 0 0 1 2 1
2nd 0 1 0 3 2
3rd 0 1 1 4 3
4th 1 0 0 5 4
5th 1 0 1 6 5
6th 1 1 0 7 6
7th 1 1 1 8 7
8th 0 0 0 1 0
9/11/2018 BRSREDDY 168
Clock
QA 0 1 0 1 0 1 0 1 0
0 0 1 1 0 0 1 1 0
QB
QC 0 0 0 0 1 1 1 1 0
Counter O/P
QC QB QA
000 001 010 011 100 101 110 111 000
0 1 2 3 4 5 6 7 0
9/11/2018 BRSREDDY 169

State diagram of 3 bit Asynchronous Up Counter
000
111 001
110 010
101 011
100
9/11/2018 BRSREDDY 170

Logic 1
TA PR QA TB PR QB TC PR QC TD PR QD
CLK
FF-A FF-B FF-C FF-D
QA QB QC QD
CR CR CR CR
Logic 1
QA QB QC QD
(LSB) (MSB)
Counter Outputs
9/11/2018 BRSREDDY 171
Clock
QA
QB
QC
QD
Counter O/P
QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 00
9/11/2018 BRSREDDY 172
Design MOD-3 Asynchronous Counter
 Mod – 3 counter is a counter having three states i.e. 00, 01
and 10. After 10 it will return back to its original state 00.
Initial
CLR
State 0 Counter CLK
QA QB
2 1 Y
Reset Logic
State Diagram
Block Diagram
 We have to design the reset logic which is a combinational

circuit.
 The output of reset logic is applied to the clear inputs of

flip flops. This is an active Low input.
9/11/2018 BRSREDDY 173
Truth Table of Reset Logic
O/P of Reset
FF Outputs
Logic
QB QA Y
0 0 1
0 1 1
1 0 1
1 1 0
K-map & Simplification for Reset Logic
QA
QB
QA QA Y  QB  QA
0 1
QB 0 1 1  Y  QBQA
QB 1 1 0
9/11/2018 BRSREDDY 174
Logic 1 2 Bit Ripple
Counter
TA PR QA TB PR QB
CLK
FF-A FF-B
QA QB
CR CR
QA
QB
Reset Logic
9/11/2018 BRSREDDY 175

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Unit-IV

Sequential Logic Circuits

 Use relevant triggering technique for the given digital

 Use the given flip flop to construct the specific type of

 Use excitation table of the given flip flop to design

 Design the specified modulo-N counter using IC 7490.

 Construct ring/twisted ring counter using the given flip

Logic circuits are classified into two groups:

Sequential logic circuits

Basic building blocks

Combinational Circuits Sequential Circuits

 In combinational circuits,  In sequential circuits, the

 Memory unit is not required  Memory unit is required to

Combinational Circuits Sequential Circuits

 Combinational circuits are  Sequential circuits are

 Sequential circuits are

 Triggering Methods: Edge Trigger & Level Trigger.

 SR Flip Flops: SR Flip Flop, Clocked SR FF with preset & clear,

 JK Flip Flops: Clocked JK FF with preset & clear, Race around

condition in JK FF, Master Slave JK FF, D and T type Flip Flop,

Excitation Tables of Flip Flops, Block schematic and function table

A memory should support at least three

It should be able to hold a value

You should be able to read the value that is saved

You should be able to change that value

We will start with simplest case, a one bit

You should be able to read the bit that is saved.

You should be able to change the bit.

- You can reset or clear the bit to 0.

How to get a new value into a storage cell?

Load new value into cell

“data” “Stored Value”

 The output of each gate is connected to the input of the

 It has two stable states which are known as 1

 Latch are the bi-stable devices which responds to the

 Triggering Methods: Edge Trigger & Level Trigger.

 SR Flip Flops: SR Flip Flop, Clocked SR FF with preset & clear,

 JK Flip Flops: Clocked JK FF with preset & clear, Race around

condition in JK FF, Master Slave JK FF, D and T type Flip Flop,

Excitation Tables of Flip Flops, Block schematic and function table

 A clock is a special device that whose output

 The time it takes the clock to change from 1 to 0 and

 Clocks are often used to synchronize circuits.

 Sequential circuits are dependent on clock pulses applies to

A flip flop who responds to a clock signal during

Triggers on High clock level

A flip flop who responds to a clock signal during

Triggers on Low clock level

A flip flop who responds to a clock signal during

Triggers on this edge of clock pulse

A flip flop who responds to a clock signal during

Triggers on this edge of clock pulse

 Triggering Methods: Edge Trigger & Level Trigger.

 SR Flip Flops: SR Flip Flop, Clocked SR FF with preset & clear,

 JK Flip Flops: Clocked JK FF with preset & clear, Race around

condition in JK FF, Master Slave JK FF, D and T type Flip Flop,

Excitation Tables of Flip Flops, Block schematic and function table

 Gates are the building block of the logic circuits.