PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

MC-4R64CPE6C
Direct RambusTM DRAM RIMMTM Module
64M-BYTE (32M-WORD x 16-BIT)

Description
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The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for
use in a broad range of applications including computer memory, personal computers, workstations, and other
applications where high bandwidth and low latency are required.
MC-4R64CPE6C modules consists of four 128M Direct Rambus DRAM (Direct RDRAM™) devices (µPD488448).
These are extremely high-speed CMOS DRAMs organized as 8M words by 16 bits. The use of Rambus Signaling
Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using conventional system and
board design technologies.
Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes).
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The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous, randomly
addressed memory transactions. The separate control and data buses with independent row and column control yield
over 95 % bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions per device.

Features
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• 184 edge connector pads with 1mm pad spacing
• 64 MB Direct RDRAM storage
• Each RDRAM has 32 banks, for 128 banks total on module
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
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• Serial Presence Detect support
• Operates from a 2.5 V supply
• Low power and powerdown self refresh modes
• Separate Row and Column buses for higher efficiency
• Over Drive Factor (ODF) support
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The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.

Document No. E0051N11 (Ver. 1.1) This product became EOL in May, 2002.
(Previous No. M14805EJ2V0DS00)
Date Published February 2006 CP (K) Eipida Memory, Inc. 2001-2006
Printed in Japan Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
 MC-4R64CPE6C

Order information
Part number Organization I/O Freq. RAS access time Package Mounted devices
MHz ns

MC-4R64CPE6C - 845 32M x 16 800 45 184 edge connector pads RIMM 4 pieces of

MC-4R64CPE6C - 745 711 45 with heat spreader µPD488448FF

MC-4R64CPE6C - 653 600 53 Edge connector : Gold plated FBGA package
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2 Preliminary Data Sheet E0051N11

 MC-4R64CPE6C

Module Pad Configuration

B1 GND GND A1
B2 LDQA7 LDQA8 A2
B3 GND GND A3
B4 LDQA5 LDQA6 A4
B5 GND GND A5
B6 LDQA3 LDQA4 A6
B7 GND GND A7
B8 LDQA1 LDQA2 A8
B9 GND GND A9
B10 LCFM LDQA0 A10
B11 GND GND A11
B12 LCFMN LCTMN A12
B13 GND GND A13
B14 NC LCTM A14
B15 GND GND A15
B16 LROW2 NC A16
B17 GND GND A17
B18 LROW0 LROW1 A18
B19 GND GND A19
B20 LCOL3 LCOL4 A20
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B21 GND GND A21
B22 LCOL1 LCOL2 A22
B23 GND GND A23
B24 LDQB0 LCOL0 A24
B25 GND GND A25
B26 LDQB2 LDQB1 A26
B27 GND GND A27
B28 LDQB4 LDQB3 A28
B29 GND GND A29
B30 LDQB6 LDQB5 A30
B31 GND GND A31
B32 LDQB8 LDQB7 A32
B33 GND GND A33
B34 LCMD LSCK A34
B35 VCMOS VCMOS A35
B36 SIN SOUT A36
B37 VCMOS VCMOS A37
B38 NC NC A38
B39 GND GND A39
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B40 NC NC A40
B41 VDD VDD A41
B42 VDD VDD A42
B43 NC NC A43
B44 NC NC A44
B45 NC NC A45
B46 NC NC A46

LCFM, LCFMN,
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Side B Side A
RCFM, RCFMN : Clock from master
LCTM, LCTMN,
RCTM, RCTMN : Clock to master
LCMD, RCMD : Serial Command Pad
B47 NC NC A47
B48 NC NC A48
B49 NC NC A49 LROW2 - LROW0,
B50 NC NC A50
B51 VREF VREF A51 RROW2 - RROW0 : Row bus
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B52 GND GND A52
B53 SA0 SCL A53 LCOL4 - LCOL0,
B54 VDD VDD A54
B55 SA1 SDA A55
B56 SVDD SVDD A56 RCOL4 - RCOL0 : Column bus
B57 SA2 SWP A57
B58 VDD VDD A58 LDQA8 - LDQA0,
B59 RCMD RSCK A59
B60 GND GND A60 RDQA8 - RDQA0 : Data bus A
B61 RDQB8 RDQB7 A61
B62 GND GND A62
B63 RDQB6 RDQB5 A63 LDQB8 - LDQB0,
B64 GND GND A64
B65 RDQB4 RDQB3 A65 RDQB8 - RDQB0 : Data bus B
B66 GND GND A66
B67 RDQB2 RDQB1 A67 LSCK, RSCK : Clock input
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B68 GND GND A68
B69 RDQB0 RCOL0 A69
B70 GND GND A70
SA0 - SA2 : Serial Presence Detect Address
B71 RCOL1 RCOL2 A71
B72 GND GND A72 SCL, SDA : Serial Presence Detect Clock
B73 RCOL3 RCOL4 A73
B74 GND GND A74 SIN, SOUT : Serial I/O
B75 RROW0 RROW1 A75
B76 GND GND A76
B77 RROW2 NC A77
SVDD : SPD Voltage
B78 GND GND A78
B79 NC RCTM A79 SWP : Serial Presence Detect Write Protect
B80 GND GND A80
B81 RCFMN RCTMN A81 VCMOS : Supply voltage for serial pads
B82 GND GND A82
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B83 RCFM RDQA0 A83 VDD : Supply voltage
B84 GND GND A84
B85 RDQA1 RDQA2 A85
B86 GND GND A86 VREF : Logic threshold
B87 RDQA3 RDQA4 A87
B88 GND GND A88 GND : Ground reference
B89 RDQA5 RDQA6 A89
B90 GND GND A90 NC : These pads are not connected
B91 RDQA7 RDQA8 A91
B92 GND GND A92

Preliminary Data Sheet E0051N11 3

 MC-4R64CPE6C

Module Pad Names

Pad Signal Name Pad Signal Name Pad Signal Name Pad Signal Name
A1 GND B1 GND A47 NC B47 NC
A2 LDQA8 B2 LDQA7 A48 NC B48 NC
A3 GND B3 GND A49 NC B49 NC
A4 LDQA6 B4 LDQA5 A50 NC B50 NC
A5 GND B5 GND A51 VREF B51 VREF
A6 LDQA4 B6 LDQA3 A52 GND B52 GND
A7 GND B7 GND A53 SCL B53 SA0
A8 LDQA2 B8 LDQA1 A54 VDD B54 VDD
A9 GND B9 GND A55 SDA B55 SA1
A10 LDQA0 B10 LCFM A56 SVDD B56 SVDD
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A11 GND B11 GND A57 SWP B57 SA2
A12 LCTMN B12 LCFMN A58 VDD B58 VDD
A13 GND B13 GND A59 RSCK B59 RCMD
A14 LCTM B14 NC A60 GND B60 GND
A15 GND B15 GND A61 RDQB7 B61 RDQB8
A16 NC B16 LROW2 A62 GND B62 GND
A17 GND B17 GND A63 RDQB5 B63 RDQB6
A18 LROW1 B18 LROW0 A64 GND B64 GND
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A19 GND B19 GND A65 RDQB3 B65 RDQB4
A20 LCOL4 B20 LCOL3 A66 GND B66 GND
A21 GND B21 GND A67 RDQB1 B67 RDQB2
A22 LCOL2 B22 LCOL1 A68 GND B68 GND
A23 GND B23 GND A69 RCOL0 B69 RDQB0
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A24 LCOL0 B24 LDQB0 A70 GND B70 GND
A25 GND B25 GND A71 RCOL2 B71 RCOL1
A26 LDQB1 B26 LDQB2 A72 GND B72 GND
A27 GND B27 GND A73 RCOL4 B73 RCOL3
A28 LDQB3 B28 LDQB4 A74 GND B74 GND
A29 GND B29 GND A75 RROW1 B75 RROW0
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A30 LDQB5 B30 LDQB6 A76 GND B76 GND
A31 GND B31 GND A77 NC B77 RROW2
A32 LDQB7 B32 LDQB8 A78 GND B78 GND
A33 GND B33 GND A79 RCTM B79 NC
A34 LSCK B34 LCMD A80 GND B80 GND
A35 VCMOS B35 VCMOS A81 RCTMN B81 RCFMN
A36 SOUT B36 SIN A82 GND B82 GND
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A37 VCMOS B37 VCMOS A83 RDQA0 B83 RCFM
A38 NC B38 NC A84 GND B84 GND
A39 GND B39 GND A85 RDQA2 B85 RDQA1
A40 NC B40 NC A86 GND B86 GND
A41 VDD B41 VDD A87 RDQA4 B87 RDQA3
A42 VDD B42 VDD A88 GND B88 GND
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A43 NC B43 NC A89 RDQA6 B89 RDQA5
A44 NC B44 NC A90 GND B90 GND
A45 NC B45 NC A91 RDQA8 B91 RDQA7
A46 NC B46 NC A92 GND B92 GND

4 Preliminary Data Sheet E0051N11

 MC-4R64CPE6C

Module Connector Pad Description (1/2)

Signal I/O Type Description

GND – – Ground reference for RDRAM core and interface. 72 PCB connector pads.

LCFM I RSL Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
LCFMN I RSL Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
LCMD I VCMOS Serial Command used to read from and write to the control registers. Also used
for power management.
LCOL4..LCOL0 I RSL Column bus. 5-bit bus containing control and address information for column
accesses.
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LCTM I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
LCTMN I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
LDQA8..LDQA0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices.
LDQB8..LDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices.
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LROW2..LROW0 I RSL Row bus. 3-bit bus containing control and address information for row accesses.

LSCK I VCMOS Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
NC – – These pads are not connected. These 24 connector pads are reserved for future
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use.
RCFM I RSL Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
RCFMN I RSL Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
RCMD I VCMOS Serial Command Input used to read from and write to the control registers. Also
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used for power management.
RCOL4..RCOL0 I RSL Column bus. 5-bit bus containing control and address information for column
accesses.
RCTM I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
RCTMN I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
RDQA8..RDQA0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
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and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices.
RDQB8..RDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices.
RROW2..RROW0 I RSL Row bus. 3-bit bus containing control and address information for row accesses.
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Preliminary Data Sheet E0051N11 5

 MC-4R64CPE6C

(2/2)
Signal I/O Type Description

RSCK I VCMOS Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
SA0 I SVDD Serial Presence Detect Address 0.

SA1 I SVDD Serial Presence Detect Address 1.

SA2 I SVDD Serial Presence Detect Address 2.

SCL I SVDD Serial Presence Detect Clock.

SDA I/O SVDD Serial Presence Detect Data (Open Collector I/O).

SIN I/O VCMOS Serial I/O for reading from and writing to the control registers. Attaches to SIO0
of the first RDRAM on the module.
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SOUT I/O VCMOS Serial I/O for reading from and writing to the control registers. Attaches to SIO1
of the last RDRAM on the module.
SVDD — — SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2.

SWP I SVDD Serial Presence Detect Write Protect (active high). When low, the SPD can be
written as well as read.
VCMOS — — CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.

VDD — — Supply voltage for the RDRAM core and interface logic.
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VREF — — Logic threshold reference voltage for RSL signals.
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6 Preliminary Data Sheet E0051N11

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MC-4R64CPE6C

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Remarks 1. Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain.
2. See Serial Presence Detection Specification for information on the SPD device and its contents.
Near Connector
VDD

2 RDRAMs
VCMOS

Plus one

0.1 µF
1 per
LDQA 8 DQA 8 DQA 8 DQA 8 DQA 8 RDQA 8
LDQA 7 DQA 7 DQA 7 DQA 7 DQA 7 RDQA 7
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LDQA 6 DQA 6 DQA 6 DQA 6 DQA 6 RDQA 6

VREF
LDQA 5 DQA 5 DQA 5 DQA 5 DQA 5 RDQA 5
LDQA 4 DQA 4 DQA 4 DQA 4 DQA 4 RDQA 4
LDQA 3 DQA 3 DQA 3 DQA 3 DQA 3 RDQA 3

2 RDRAMs
LDQA 2 DQA 2 DQA 2 DQA 2 DQA 2 RDQA 2

RDRAM
LDQA 1 DQA 1 DQA 1 DQA 1 DQA 1 RDQA 1

0.1 µF
0.1 µF

1 per
2 per
LDQA 0 DQA 0 DQA 0 DQA 0 DQA 0 RDQA 0
LCFM CFM CFM CFM CFM RCFM
LCFMN CFMN CFMN CFMN CFMN RCFMN
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Preliminary Data Sheet E0051N11

LCTM CTM CTM CTM CTM RCTM
LCTMN CTMN CTMN CTMN CTMN RCTMN

VCMOS
VDD
LROW 2 ROW 2 ROW 2 ROW 2 ROW 2 RROW 2
LROW 1 ROW 1 ROW 1 ROW 1 ROW 1 RROW 1
U2

U3

U4
U1

LROW 0 ROW 0 ROW 0 ROW 0 ROW 0 RROW 0

LCOL 4 COL 4 COL 4 COL 4 COL 4 RCOL 4
LCOL 3 COL 3 COL 3 COL 3 COL 3 RCOL 3

0.1 µF
LCOL 2 COL 2 COL 2 COL 2 COL 2 RCOL 2
LCOL 1 COL 1 COL 1 COL 1 COL 1 RCOL 1
LCOL 0 COL 0 COL 0 COL 0 COL 0 RCOL 0
LDQB 0 DQB 0 DQB 0 DQB 0 DQB 0 RDQB 0
LDQB 1 DQB 1 DQB 1 DQB 1 DQB 1 RDQB 1

SVDD
LDQB 2 DQB 2 DQB 2 DQB 2 DQB 2 RDQB 2

SDA
LDQB 3 DQB 3 DQB 3 DQB 3 DQB 3 RDQB 3

SERIAL PD
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LDQB 4 DQB 4 DQB 4 DQB 4 DQB 4 RDQB 4
LDQB 5 DQB 5 DQB 5 DQB 5 DQB 5 RDQB 5
LDQB 6 DQB 6 DQB 6 DQB 6 DQB 6 RDQB 6
SIO 0
SIO 1

SIO 0
SIO 1
SIO 0
SIO 1

SIO 0
SIO 1
CMD

CMD
DQB 7

CMD

CMD
LDQB 7 DQB 7 DQB 7 DQB 7 RDQB 7

VREF

VREF
SCK

SCK
VREF

VREF
SCK

SCK

SDA

SA0 SA1 SA2

A2
LDQB 8 DQB 8 DQB 8 DQB 8 DQB 8 RDQB 8

SVDD

VCC

U0

A1
SIN SOUT
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LSCK RSCK

SCL

A0
WP
LCMD RCMD
VREF
Block Diagram

47 kΩ
SWP
SCL
 MC-4R64CPE6C

Electrical Specification
Absolute Maximum Ratings

Symbol Parameter MIN. MAX. Unit

VI,ABS Voltage applied to any RSL or CMOS signal pad with respect to GND −0.3 VDD + 0.3 V

VDD,ABS Voltage on VDD with respect to GND −0.5 VDD + 1.0 V

TSTORE Storage temperature −50 +100 °C

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
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DC Recommended Electrical Conditions

Symbol Parameter and conditions MIN. MAX. Unit

VDD Supply voltage 2.50 − 0.13 2.50 + 0.13 V

VCMOS CMOS I/O power supply at pad 2.5V controllers 2.5 − 0.13 2.5 + 0.25 V

1.8V controllers 1.8 − 0.1 1.8 + 0.2

VREF Reference voltage 1.4 − 0.2 1.4 + 0.2 V

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VIL RSL input low voltage VREF − 0.5 VREF − 0.2 V

VIH RSL input high voltage VREF + 0.2 VREF + 0.5 V

VIL,CMOS CMOS input low voltage −0.3 0.5VCMOS − 0.25 V

VIH,CMOS CMOS input high voltage 0.5VCMOS+0.25 VCMOS + 0.3 V

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VOL,CMOS CMOS output low voltage, IOL,CMOS = 1 mA — 0.3 V

VOH,CMOS CMOS output high voltage, IOH,CMOS = −0.25 mA VCMOS − 0.3 — V

IREF VREF current, VREF,MAX −40.0 +40.0 µA

ISCK,CMD CMOS input leakage current, (0 ≤ VCMOS ≤ VDD) −40.0 +40.0 µA
ISIN,SOUT CMOS input leakage current, (0 ≤ VCMOS ≤ VDD) −10.0 +10.0 µA
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8 Preliminary Data Sheet E0051N11

 MC-4R64CPE6C

AC Electrical Specifications

Symbol Parameter and Conditions MIN. TYP. MAX. Unit

Z Module Impedance 25.2 28 30.8 Ω

TPD Average clock delay from finger to finger of all RSL clock nets -845 1.25 ns

(CTM, CTMN,CFM, and CFMN) -745 1.25

-653 1.25

∆TPD −21
Note1,2
Propagation delay variation of RSL signals with respect to TPD +21 ps

∆TPD-CMOS Propagation delay variation of SCK and CMD signals with respect to −100 +100 ps
Note1
an average clock delay
Vα/VIN Attenuation Limit -845 12 %
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-745 12

-653 8

VXF/VIN Forward crosstalk coefficient -845 2 %

(300ps input rise time 20% - 80%) -745 2

-653 2

VXB/VIN Backward crosstalk coefficient -845 1.5 %

(300ps input rise time 20% - 80%) -745 1.5

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-653 1.5

RDC DC Resistance Limit -845 0.6 Ω

-745 0.6

-653 0.6
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Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted ∆TPD Specification” table.
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Adjusted ∆TPD Specification

Symbol Parameter and conditions Adjusted MIN./MAX. Absolute Unit

MIN. MAX.

∆TPD −30
Note
Propagation delay variation of RSL signals with respect to TPD +/− [17+(18*N*∆Z0)] +30 ps

Note N = Number of RDRAM devices installed on the RIMM module.

∆Z0 = delta Z0% = (MAX. Z0 − MIN. Z0) / (MIN. Z0)
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(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on
the module.)
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Preliminary Data Sheet E0051N11 9

 MC-4R64CPE6C

RIMM Module Current Profile

Note1
IDD RIMM module power conditions MAX. Unit
Note2
IDD1 One RDRAM in Read , balance in NAP mode -845 702.6 mA

-745 637.6

-653 552.6
Note2
IDD2 One RDRAM in Read , balance in Standby mode -845 1,020 mA

-745 940

-653 825
Note2
IDD3 One RDRAM in Read , balance in Active mode -845 1,230 mA

-745 1,120
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-653 975

IDD4 One RDRAM in Write, balance in NAP mode -845 662.6 mA

-745 607.6

-653 527.6

IDD5 One RDRAM in Write, balance in Standby mode -845 980 mA

-745 910

-653 800
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IDD6 One RDRAM in Write, balance in Active mode -845 1,190 mA

-745 1,090

-653 950

Notes 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage
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patterns. Power does not include Refresh Current.
2. I/O current is a function of the % of 1’s, to add I/O power for 50 % 1’s for a x16 need to add 257 mA for the
following : VDD = 2.5 V, VTERM = 1.8 V, VREF = 1.4 V and VDIL = VREF − 0.5 V.
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10 Preliminary Data Sheet E0051N11

 MC-4R64CPE6C

Timing Parameters
The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM data sheet
(µPD488448) for detailed timing diagrams.

Para- Description MIN. MAX. Units

meter -845 -745 -653

tRC Row Cycle time of RDRAM banks - the interval between ROWA packets with 28 28 28 — tCYCLE
ACT commands to the same bank.
Note 2
tRAS RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT 20 20 20 64µs tCYCLE
Note 1
command and next ROWR packet with PRER command to the same bank.
tRP Row Precharge time of RDRAM banks - the interval between ROWR packet with 8 8 8 — tCYCLE
Note 1
PRER command and next ROWA packet with ACT command to the same
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bank.
tPP Precharge-to-precharge time of RDRAM device - the interval between 8 8 8 — tCYCLE
Note 1
successive ROWR packets with PRER commands to any banks of the
same device.
tRR RAS-to-RAS time of RDRAM device - the interval between successive ROWA 8 8 8 — tCYCLE
packets with ACT commands to any banks of the same device.
tRCD RAS-to-CAS Delay - the interval from ROWA packet with ACT command to 9 7 7 — tCYCLE
COLC packet with RD or WR command. Note - the RAS-to-CAS delay seen
by the RDRAM core (tRCD-C) is equal to tRCD-C = 1 + tRCD because of differences in
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the row and column paths through the RDRAM interface.
tCAC CAS Access delay - the interval from RD command to Q read data. The 8 8 8 12 tCYCLE
equation for tCAC is given in the TPARM register.
tCWD CAS Write Delay - interval from WR command to D write data. 6 6 6 6 tCYCLE

tCC CAS-to-CAS time of RDRAM bank – the interval between successive COLC 4 4 4 — tCYCLE
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commands.
tPACKET Length of ROWA, ROWR, COLC, COLM or COLX packet. 4 4 4 4 tCYCLE

tRTR Interval from COLC packet with WR command to COLC packet which causes 8 8 8 — tCYCLE
retire, and to COLM packet with bytemask.
tOFFP The interval (offset) from COLC packet with RDA command, or from COLC 4 4 4 4 tCYCLE
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packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
the equivalent ROWR packet with PRER. The equation for tOFFP is given in the
TPARM register.
tRDP Interval from last COLC packet with RD command to ROWR packet with 4 4 4 — tCYCLE
PRER.
tRTP Interval from last COLC packet with automatic retire command to ROWR 4 4 4 — tCYCLE
packet with PRER.
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Notes 1. Or equivalent PREC or PREX command.
2. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE.
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Preliminary Data Sheet E0051N11 11

 MC-4R64CPE6C

Standard RIMM Module Marking

The RIMM modules are marked per Figure 1 below. This marking assists users to specify and verify if the correct
RIMM modules are installed in their systems. In the diagram, a label is shown attached to the RIMM module's heat
spreader. Information contained on the label is specific to the RIMM module and provides RDRAM information without
requiring removal of the RIMM module's heat spreader.

Figure 1. RIMM Module marking example

A B C D
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JAPAN 128MB/8d nonECC
MC-4R128CEE6C-845 800-45
0020B9001 G100 S100 1996 HCS, Inc. 800-748-0241 No. 6043B-ISO

G E H I F J

Label Field Description Marked Text Units

A Vendor logo Vendor logo area NEC −

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B Manufacturing Country Country of origin JAPAN, USA, FRANCE −

C Module Memory Capacity Number of 8-bit or 9-bit MBytes of RDRAM storage in 64MB, 96MB, 128MB, 192MB, MBytes
RIMM module 256MB
Number of RDRAMs Number of RDRAM devices contained in the RIMM /4d, /6d, /8d, /12d, /16d RDRAM
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module devices
D ECC Support Indicates whether the RIMM module supports 8-bit non ECC, ECC −
(non ECC) or 9-bit (ECC) Bytes
E Part No. NEC RIMM Part No. See table Order information −

F Memory Speed Data transfer speed for RIMM module 800, 711, 600 MHz
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tRAC Row Access Time -45, -53 ns

G Manufacturing Lot No. Manufactured Year code, Week code, In-house code YYWW∗∗∗∗∗ −

H Gerber Version PCB Gerber file revision used on RIMM Module G100 as Rev 1.00 −

I SPD Version SPD code version S100 as Rev 1.00 −

J Caution Logo − − −
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12 Preliminary Data Sheet E0051N11

 MC-4R64CPE6C

Package Drawings

184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (1/2)

EEPROM

A (AREA B)
R
128 M Direct RDRAM M1 (AREA B) V

P S

A
O N M Q
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L M2 (AREA A)
T
K B
H I J
G D E F
B
C
A1 (AREA A)
L
ITEM MILLIMETERS
A 133.35 TYP.
A1 133.35±0.13
B 55.175
B1 1.00±0.10
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C 11.50
detail of A part detail of B part C1 3.00±0.10
D 45.00
C1 E 32.00
W R1.00 R1.00
F 45.00
G 5.675
H 47.625
I 25.40
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Y B1
J 47.625
X Z K 6.35
L 1.00 TYP.
M 31.75±0.13
M1 11.97
M2 19.78
N 29.21
O 17.78
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P 4.00±0.10
Q R 2.00
R 3.00±0.10
S φ 2.44
T 1.27±0.10
V 2.43 MAX.
W 0.80±0.10
X 2.99
Y 0.15
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Z 2.00±0.10

Preliminary Data Sheet E0051N11 13

 MC-4R64CPE6C

;
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (2/2)

;;;;; ;
;;;;;;;;; A

;;;;;;;;;
;;;;;;;;; E
B
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F
Pad A1 C C Pad A92 G

D H

ITEM DESCRIPTION MIN. TYP. MAX. UNIT

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A PCB length 133.22 133.35 133.48 mm

B PCB height for 1.25" RIMM Module 31.62 31.75 31.88 mm

C Center-center pad width from pad A1 to A46, 44.95 45.00 45.05 mm

A47 to A92, B1 to B46 or B47 to B92
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D Spacing from PCB left edge to connector key notch - 55.175 - mm

E Spacing from contact pad PCB edge - 17.78 - mm

to side edge retainer notch
F PCB thickness 1.17 1.27 1.37 mm

G Heat spreader thickness from PCB surface (one side) to - - 3.09 mm

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heat spreader top surface
H RIMM thickness - - 4.46 mm
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14 Preliminary Data Sheet E0051N11

 MC-4R64CPE6C

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
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wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
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of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
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3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
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reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
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Preliminary Data Sheet E0051N11 15

 MC-4R64CPE6C

Rambus, RDRAM and the Rambus Logo are registered trademarks of Rambus Inc.
DirectRambus, DirectRDRAM, RIMM, RModule and RSocket are trademarks of Rambus Inc.

CAUTION FOR HANDLING MEMORY MODULES

When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.

When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
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• The information in this document is current as of August, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or
data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
• Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
L
patents, copyrights or other intellectual property rights of Elpida or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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• While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
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developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
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for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
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(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
M8E 00. 4