Toshiba

NTDPJTV04
SERVICE TRAINING
"Customer Satisfaction Through Knowledge"
SERVICING THE N5SS

COLOR TELEVISION
CHASSIS / DIGITAL
CONVERGENCE
TOSHIBA AMERICA CONSUMER PRODUCTS, INC.

NATIONAL SERVICE DIVISION
TRAINING DEPARTMENT
1420-B TOSHIBA DRIVE
LEBANON, TENNESSEE 37087
PHONE: (615) 449-2360
FAX: (615) 444-7520
FOREWORD
The material presented in this manual is provided for the technical training of TACP employees and
qualified service personnel only.
The specific circuit reference designations, pin numbers, etc., are taken from the TP48E50/60 Service
Manual, File Number 020-9508. The diagrams in this manual are simplified for training and should be used
as a reference guide only when servicing the N5SS CTV Chassis. Refer to the applicable service data for
detailed adjustment and servicing procedures.
NTDPJTV04
SERVICING TOSHIBA'S N5SS TELEVISION CHASSIS

©1996
TOSHIBA AMERICA CONSUMER PRODUCTS, INC.

National Service Division
National Training Department
1420 Toshiba Drive
Lebanon, TN 37087
(615) 449-2360
No part of this manual may be reproduced in whole or in part without prior written consent from
Toshiba America Consumer Products, Inc., Service Division.
CONTENTS
SECTION I 6. ON SCREEN FUNCTION ....................... 3-6

OVERALL UNIT CHARACTERISTICS, 7. SYSTEM BLOCK DIAGRAM ................ 3-7
BLOCK DIAGRAMS, LABS 1 & 2 8. LOCAL KEY DETECTION METHOD .. 3-8
1. MAIN FEATURES .................................. 1-2 9. ENTERING THE SERVICE MODE ....... 3-9
2. MERITS OF BUS SYSTEM.................... 1-2 10. TEST SIGNAL SELECTION .................. 3-9
2-1. Improved Servciceability ................. 1-2 11. SERVICE ADJUSTMENT ...................... 3-9
2-2. Reduction of Parts Count ................ 1-2 12. FAILURE DIAGNOSIS PROCEDURE 3-10
2-3. Quality Control ................................. 1-2 13. TROUBLE SHOOTING CHARTS ....... 3-13
3. COMPARISON/DIFFERENCES TG-1 ... 1-2
4. SPECIFICATIONS .................................. 1-3 SECTION IV
5. FRONT AND REAR CONTROL AUDIO OUTPUT CIRCUIT
VIEWS ..................................................... 1-4 1. OUTLINE ................................................. 4-2
5-1. Front View ........................................ 1-4 2. THEORY OF OPERATION .................... 4-2
5-2. Rear View ......................................... 1-5 2-1. Operation of TA8256H .................... 4-2
5-3. Remote Control View ....................... 1-6
6. '95 PJ-TV CHASSIS LAYOUT ............... 1-7
7. CONSTRUCTION OF CHASSIS............ 1-8 SECTION V
8. VIDEO SIGNAL FLOW. ....................... 1-9 DSP CIRCUIT
9. AUDIO SIGNAL FLOW. ...................... 1-11 1. ORIGINS OF DOLBY SURROUND ...... 5-2
10. POWER SUPPLY .................................. 1-12 2. THE DOLBY MP MATRIX .................... 5-2
11. H and V DEFLECTION. ........................ 1-13 3. THE DOLBY SURROUND
12. I2C COMMUNICATIONS. .................... 1-14 DECODER ............................................... 5-3
13. DIGITAL CONVERGENCE. ................ 1-15 4. DSP CIRCUIT .......................................... 5-3
14. LAB 1 ..................................................... 1-16 5. DSP (Digital Surround Processor) IC ...... 5-6
15. LAB 2 ..................................................... 1-20
SECTION VI
A/V SWITCHING CIRCUIT
SECTION II 1. OUTLINE ................................................. 6-2
TUNER, IF/MTS/S.PRO MODULE 2. IN/OUT TERMINALS ............................ 6-2
1. CIRCUIT BLOCK.................................... 2-2 3. CIRCUIT OPERATION .......................... 6-2
1-1. Outline .............................................. 2-2 3-1. Composite Video Signal ................... 6-2
1-2. Major Features .................................. 2-2 3-2. S-Video Signal ................................. 6-2
1-3. Audio Multiplex Demodulation
Circuit ............................................... 2-3 SECTION VII
1-4. A.PRO Section (Audio Processor) ... 2-4 VIDEO PROCESSING CIRCUIT
2. PIP TUNER .............................................. 2-6 1. OUTLINE ................................................. 7-2
2-1. Outline ............................................... 2-6 2. SIGNAL FLOW ....................................... 7-2
3. CIRCUIT OPERATION .......................... 7-2
SECTION III
CHANNEL SELECTION CIRCUIT SECTION VIII
1. OUTLINE OF CHANNEL V/C/D/IC
SELECTION CIRCUIT SYSTEM .......... 3-2 1. OUTLINE ................................................. 8-2
2. OPERATION OF CHANNEL 2. LARGE SCALE EMPLOYMENT OF
SELECTION CIRCUIT ........................... 3-2 BUS CONTROL OF PARAMETER FOR
3. MICROCOMPUTER ............................... 3-3 PICTURE CONTROLS ........................... 8-2
4. MICROCOMPUTER TERMINAL 3. EMPLOYMENT OF CONTAINING
FUNCTION .............................................. 3-4 EACH VIDEO BAND FILTER
5. EEPROM (QA02) .................................... 3-6 INSIDE ..................................................... 8-2
4. EMPLOYMENT OF CONTAINING 5. HIGH VOLTAGE GENERATION
EACH FILTER (FOR S/H) INSIDE ....... 8-2 CIRCUIT .............................................. 12-14
5. LOW COST OF IC .................................. 8-3 5-1. Theory of Operation ..................... 12-14
5-2. Operation Theory of the Harmonic
SECTION IX Non-Resonant System and Tuned
PIP MODULE Waveforms ................................... 12-16
1. BOARD LAYOUT ................................... 9-2 6. HIGH VOLTAGE CIRCUIT ............... 12-17
2. SIGNALS ................................................. 9-2 6-1. High Voltage Regulator................ 12-17
3. BLOCK DIAGRAM ................................ 9-3 7. X-RAY PROTECTION CIRCUIT ...... 12-20
7-1. Outline .......................................... 12-20
SECTION X 7-2. Operation ...................................... 12-20
SYNC SEPARATION, H-AFC, 8. OVER CURRENT PROTECTION
H-OSCILLATOR CIRCUITS CIRCUIT .............................................. 12-21
1. SYNC SEPARATION CIRCUIT .......... 10-2 8-1. Outline .......................................... 12-21
1-1. Theory of Operation ....................... 10-2 8-2. Operation ...................................... 12-21
2. H AFC (Automatic Frequency Control)
CIRCUIT ................................................ 10-3 SECTION XIII
3. H OSCILLATOR CIRCUIT .................. 10-4 DEFLECTION DISTORTION
3-1. Outline ............................................ 10-4 CORRECTION CIRCUIT (DPC Circuit)
3-2. Theory of Operation ....................... 10-4 1. DEFLECTION DISTORTION
CORRECTION IC (TA8859P) .............. 13-2
SECTION XI 1-1. Outline ............................................ 13-2
VERTICAL OUTPUT CIRCUIT 1-2. Functions and Features ................... 13-2
1. OUTLINE ............................................... 11-2 1-3. Block Diagram ............................... 13-2
1-1. Theory of Operation ....................... 11-2 2. DIODE MODULATOR CIRCUIT ........ 13-3
2. V OUTPUT CIRCUIT ........................... 11-3 3. ACTUAL CIRCUIT ............................... 13-4
2-1. Actual Circuit ................................. 11-3 3-1. Basic Operation and Current Path .. 13-5
2-2. Sawtooth Waveform Generation .... 11-3
2-3. V Output ......................................... 11-4 SECTION XIV
2-4. V Linearity Characteristic CLOSED CAPTION/EDS CIRCUIT
Correction ....................................... 11-6 1. OUTLINE ............................................... 14-2
3. PROTECTION CIRCUIT FOR 2. DATA TRANSMISSION FORMAT ..... 14-2
V DEFLECTION STOP ........................ 11-7 3. DISPLAY FORMAT ............................. 14-3
3-1. +35V Over Current 4. CIRCUIT OPERATION ........................ 14-4
Protection Circuit ........................... 11-8
SECTION XV
SECTION XII DIGITAL CONVERGENCE CIRCUIT
HORIZONTAL DEFLECTION CIRCUIT 1. OUTLINE ............................................... 15-2
1. OUTLINE ............................................... 12-2 2. CIRCUIT DESCRIPTION ..................... 15-2
2. HORIZONTAL DRIVE CIRCUIT ........ 12-2 2-1. Configuration.................................. 15-2
2-1. Theory of Operation ....................... 12-2 2-2. Circuit Operation ............................ 15-2
3. BASIC OPERATION OF HORIZONTAL 3. PICTURE ADJUSTMENT .................... 15-4
DRIVE .................................................... 12-3 3-1. Change of Memory (E2PROM) ...... 15-4
3-1. Theory of Operation ....................... 12-3 3-2. Service Mode .................................. 15-4
3-2. Drive System .................................. 12-4 4. ADJUSTING PICTURE
3-3. Circuit Description ......................... 12-5 DIMENSION (Green picture) ................ 15-6
4. HORIZONTAL OUTPUT CIRCUIT .... 12-6 5. KEY FUNCTION OF REMOTE CONTROL
4-1. Theory of Operation ....................... 12-7 UNIT ...................................................... 15-7
4-2. White Peak Bending 6. CONVERGENCE OUTPUT
Correction Circuit ......................... 12-11 CIRCUIT ................................................ 15-8
4-3. H Blanking ................................... 12-12 6-1. Outline ............................................ 15-8
4-4. 200V Low Voltage Protection ...... 12-13
6-2. Circuit Description ......................... 15-8
7. CONVERGENCE TROUBLESHOOTING 2. RECTIFYING CIRCUIT AND
CHART................................................. 15-10 STANDBY POWER SUPPLY .............. 17-4
8. LAB 3 ................................................... 15-11 3. MAIN SUPPLY CIRCUIT .................... 17-4
4. OUTLINE OF CURRENT RESONANT
SECTION XVI TYPE SUPPLY ...................................... 17-4
OPTICAL SECTION 5. FUNDAMENTAL THEORY ................ 17-5
1. NECK COMPONENTS ......................... 16-2 6. ACTUAL CIRCUIT ............................... 17-6
1-1. Outline of Components Around 7. SCAN DERIVED VOLTAGES............. 17-8
Neck of The Projection Tube ......... 16-2 8. PROTECTOR MODULE (Z801) .......... 17-9
1-2. Theory of Operation ........................ 16-2 9. SUB POWER SUPPLY ....................... 17-10
1-3. Projection Tube .............................. 16-3 10. PROTECT CIRCUITS ......................... 17-11
2. FUNCTION OF KEY 11. LAB 4 ................................................... 17-15
COMPONENTS ..................................... 16-4
2-1. Outline ............................................ 16-4 SECTION XVIII
2-2. Theory of Operation ....................... 16-4 DYNAMIC FOCUS CIRCUIT
2-4. Optical Coupling Effect ................. 16-8 1. OUTLINE ............................................... 18-2
2-5. Lens ................................................ 16-9 2. H DYNAMIC FOCUS CIRCUIT .......... 18-2
2-6. Focus Adjustment ......................... 16-10 2-1. Theory of Operation ....................... 18-2
2-2. Circuit Operation ............................ 18-3
SECTION XVII 3. V DYNAMIC FOCUS CIRCUIT .......... 18-4
POWER CIRCUIT 3-1. Theory of Operation ....................... 18-4
1. OVERVIEW ........................................... 17-3 3-2. Circuit Operation ............................ 18-5
SECTION I
OVERALL UNIT
CHARACTERISTICS
BLOCK DIAGRAMS
LABS 1 & 2
1-1
SECTION I
OVERALL UNIT
CHARACTERISTICS
1. MAIN FEATURES 3. COMPARISON/DIFFERENCES OF TG-1
CHASSIS
The main feature of Toshiba's projection television model
TP48E60, is the use of the N5SS (TG-1C) chassis. This Toshiba's concept for the TG-1 chassis was to create a sort
chassis utilizes a bus control system, developed by PHILIPS of universal chassis which, with minimal changes, could be
Corporation, called the I2C (or IIC) bus. IIC stands for Inter- used as a standard throughout the entire Toshiba color
Integrated Circuit control. This bus co-ordinates the transfer television lineup starting in 1995. TG-1 stands for "Toshiba
of data and control between ICs inside the Television. It is a Global 1". The TG-1 chassis can be found in several
bi-directional serial bus consisting of two lines, namely SDA different models and varies in both complexity and features.
(Serial DATA), and SCL (Serial CLOCK).
Digital data which is passed along the bus is received by

individual devices and can be either command or data. Root TG-1 Typical Picture and
Digital-to analog converters are also found within some of Chassis Chassis Sizes Features
the ICs, allowing them to be addressed and controlled by N5E A1 13, 19 Less
strings of digital instructions, replacing those functions N5ES A2 20, 32
which were previously implemented by external N5S A2 - LEM 20, 32
N5S B 27, 32
potentiometers.
N5SS C 27 thru 35 More
Typical Chassis Exam ples

2. MERITS OF THE BUS SYSTEM Model TG-1
CF13E22,23 A1
2-1. Improved Serviceability CF19E22 A1
Most of the adjustments previously made by resetting variable CF20E30 A1
resistors and/or capacitors can be made on the new chassis CF20E40 A1
by operating the remote control and seeing the results on the CN27E55 A2
television screen. This allows adjustments to be made without CF30E50 A2
removing covers on the unit thus increasing servicing speed CF32E50 A2
and efficiency. CF32E55 A2
CX32E60 B
2-2. Reduction of Parts Count CX32E60 B
The use of digital-to-analog converters built into the ICs, CN27E90 C
allowing them to be controlled by software, has eliminated CX32E70 C
or reduced the requirement for many discrete parts such as CN32E90 C
potentiometers and trimmers, etc. CN35E15 C
TP48E50,51 C
2-3. Quality Control TP48E60,61 C
The central control of adjustment data makes it easier to TP55E50,51 C
understand, analyze, and review the data, thus improving TP55E80.81 C
the quality of the product. TP61E80 C
TP48E90 C
1-2
4. SPECIFICATIONS
CHASSIS C C C C C C
MODEL Nbr TP48E50 TP48E60 TP48E90 TP55E50 TP55E80 TP61E80
TP48E51 TP48E61 TP55E51 TP55E81 STEP-UP
SPECIFICATION
1 Picture Size# 48"-D/S 48"-D/S 48"-D/S 55"-D/S 55"-D/S 61"-D/S
* 2 Channel Capacity 181ch 181ch 181ch 181ch 181ch 181ch
G 3 C. Caption ● ● ● ● ● ●
E 4 MTS with dbx ● ● ● ● ● ●
N 5 Bass, Tre/Balance ● ● ● ● ● ●
E 6 Sub-Audio-Program ● ● ● ● ● ●
R
7 Remote Control *A-Uni (42k A-Uni (42k *Intelig+EZ A-Univ (42k A-Univ (43k A-Univ (43k
A
L 8 Picture-in-Picture * ● (1TN) ● (2TN) ● (2TN) ● (1TN) ● (2TN) ● (2TN)
9 LED Indicator (RED) ● (P) ● (P) ● (P) ● (P) ● (P) ● (P)
10 Local Key 8key 8key 8key 8key 8key 8key
11 Dolby Surround — — ●(Prolo) — ● ●
12 Dig-Sound Processor — — ● (DSP4ch) — ● (DSP4ch) ● (DSP4ch)
* 13 Front Surround ● ● — ● — —
S 14 Cyclone ABX — — — — — —
O
15 Sub-Bass-System ● ● ● ● ● ●
U
N 16 Audio Output 14Wx2 14Wx2 14Wx2, 10Wx2 14Wx2 14Wx2 14Wx2
D & 10Wx2 & 10Wx2 & 10Wx2
17 Speaker Size & Nbr 160Rx2 160Rx2 160Rx2 160Rx2 160Rx2 160Rx2
& REAR SPK & REAR SPK & REAR SPK
18 Comb Filter ● (DIG) ● (DIG) ● (DIG) ● (DIG) ● (DIG) ● (3D-Y/C)
* 19 Dynamic Focus # ● ● ● ● ● ●
P 20 Scan Velocity Modu ● (RGB) ● (RGB) ● (RGB) ● (RGB) ● (RGB) ● (RGB)
I
C 21 Vert Contour Corre — — — — — —
T 22 Black Level Expand ● ● ● ● ● ●
U 23 Flesh Tone Correct ● ● ● ● ● ●
R 24 Dynamic Noise Reduc ● ● ● ● ● ●
E 25 Picture Preference ● ● ● ● ● ●
26 Digital-Convergence ● ● ● ● ● ●
27 Horiz Resolution 800 800 800 800 800 800
28 Parental-Ch Lock ● ● ● ● ● ●
* 29 Channel Label (32ch) ● ● ● ● ● ●
O
30 3-Language Display ● ● ● ● ● ●
T
H 31 Clock/Off-Timer ●/● ●/● ●/● ●/● ●/● ●/●
E 32 Favorite Channel ● ● ● ● ● ●
R 33 Extended-Data-Servi ● ● ● ● ● ●
34 Star-Sight-Decoder — — — — — —
35 S-Video In-Term ● (1+1) ● (1+1) ● (1+1) ● (1+1) ● (1+1) ● (1+1)
* 36 Audio, Video-In/Out 1+2/1 1+2/1 1+2/1 1+2/1 1+2/1 1+2/1
T 37 Front AV Jack ● ● ● ● ● ●
E 38 Variable Audio Out ● ● ● ● ● ●
R 39 2-RF Input *— ● ● — ● ●
M
40 Ext Speaker Term ● ● ● ● ●
S
41 PIP Audio Out Jack — — ● — — —
42 Center-Ch-Aud-Input — — — — ● ●
AC 43 Speaker-Box — — ● (SS-SR94 — ● (SS-SR94 ● (SS-SR94
*Cabinet NEW NEW NEW NEW NEW NEW
PARTS SUPPLY (ISO) — — — — — —
1-3
5. FRONT AND REAR CONTROL VIEWS
5-1. Front View
POWER indicator
POWER
Press to open the door. Remote sensor location
POWER button
Behind the door
Fig. 1-1
ANT/VIDEO button*
ADV button
IN-VIDEO 3 MENU-ADV
S-VIDEO VIDEO AUDIO
L/MONO R DEMO ANT/VIDEO VOLUME CHANNEL
VIDEO/AUDIO INPUT MENU buttom

jacks
CHANNEL
DEMO button butttons
S-VIDEO INPUT jack
VOLUME buttons*
−/+ buttons
* These buttons have dual functions.
Fig. 1-2
1-4
5-2. Rear View
S-VIDEO INPUT jack

TV rear
VARIABLE AUDIO
OUTPUT jacks
A
D O
O
R VAR
AUDIO
A O A
R VD
I EO
D O
OO
OO
A DO L/MONO DO
A P
R
P A R8
R R
PIP
D O1 D O2 AUDIO
O O
VIDEO 1 INPUT
jacks
EXTERNAL
SPEAKER
terminals VIDEO 2 INPUT
MAIN jacks
SPEAKER VIDEO/AUDIO
switch OUTPUT jacks
Fig. 1-3
1-5
5-3. Remote Control View
Transmit indicator
TIMER/Clock*
EDS* EDS TIMER POWER
TV
CAB
LE POWER
TV/CABLE/VCR switch TV/VIDEO RECALL MUTE
VCR
RECALL*
TV/VIDEO*
MUTE*
1 2 3
CH CHANNEL
4 5 6
Channel Number*
7 8 9
E N T
VOL RTN*
100 0 R T N
VOLUME
S T O P R E W P LA Y FF
PIP function* VCR function*
S W AS P O U R C E P IP
LO C A TE
P A U S E / S TSILLL O W
R E C T V /V C R
P IP
S T IL L C H
AUDio* SET UP*

P IC . A U D S
. E T U OP P T I O N
PICture* OPTION*
R E S E TE X I T F A V
RESET* −/+
C . C A PA N
T T 1 /2
C Y C /S B S D S P / S U R FAV −/+*
C. CAPT*
DSP/SUR*
ANT1/2*
EXIT* SYC/SBS*
To operate buttons inside the cover,

slide the cover down and toward you.
* These functions do not have

duplicate locations on the TV.
They can be controlled only by
the Remote Control.
Fig. 1-4
1-6
6. PJTV CHASSIS LAYOUT
3
REAR CENTER
AMP 2CH 4 -4:DYNAMIC FOCUS 1 :DEF/POWER 2 :MAIN
AMP 2CH
7A -1:FRONT SURROUND
8 :DIGITAL CONVER
7B -1:DSP 4CH
9 :DOLBY PRO
6A :DIGITAL COMB
3 −3:DPC 6B :3D Y/C
FRONT PIP(HOKURIKU)
AMP 2CH
7A -2:EDS.CC
7B -2:EDS.CC
to FOCUS
PACK to CRT
F.B.T
J-BOX
4 -2:SPEAKER 4 -1:A/V
Fig. 1-5
1-7
FEATURE
5 -4:FRONT 1. AUDIO
7A FRONT SURROUND
TP48E50/51/60/61
TP55E50/51
* SPK. TREM. 1pcs
* REAR.CENTER AMP W/O
7B :DSP4CH
TP55E80/81
TP61E80
* SPK TERM. 2pcs
* REAR. AMP W/
* CENTER. AMP W/O
* CENTER INPUT W/
5 -5:SVH FOCUS PACK 9 :DOLBY PRO
TP48E90
* SPK. TERM. 2pcs
* REAR. CENTER AMP W/
2. COMB FILTER
6A :DIGITAL COMB
TP48E50/51/60/61/90
TP55E50/51
6B :3D Y/C TP61E80
5 -1:CRT-D(R) 5 -4:CRT-D(G) 5 -4:CRT-D(B)
:CONV/POW2 3. TUNER
* TP48E50/51
* TP55E50/51ONLY
1 TUNER
OTHER 2 TUNER
7. CONSTRUCTION OF CHASSIS
1 WOOD CABINET
10
2 LIGHT BOX
3 SPEAKER GRILLE
4 FRONT COVER
8 5 CRT MOUNTING
6 SHIELD FRONT
7 SHIELD SIDE
8 SCREEN BEZEL
9 SCREEN BRACKET L
1
10 SCREEN BRACKET S
12 11 CONTROL PANEL
12 BACK BOARD
13 COUPLING R
14 COUPLING G
15 COUPLING B
11 7
16 CHASSIS FRAME MAIN
5 17 CHASSIS FRAME POWER
18 AV TERMINAL BOARD
2 18
13 14 15
6 16 17
Fig. 1-6
1-8
8. VIDEO SIGNAL FLOW BLOCK DIAGRAM
Basic Circuit Operation

The basic operation of the TG-1 chassis is illustrated in the into the video 1 input jack when the internal test signals are
block diagrams, figures 1-7 through 1-12. Although these used.
diagrams focus on the TP48E60, the video and audio signal
flow diagrams can be applied to any TG-1 chassis with The selected video signal is output as composite video and
minor modifications. applied to the video output jack, the EDS/CC/RGB SW.,
and the Digital Comb Filter or the 3D - Y/C circuit. After
Video Signal Flow processing the video signal is sent back to the AV Switcher
Figure 1-7 illustrates the video signal flow through the TG- as separate luminance (Y) and chrominance (C) signals.
1 chassis. The Antenna 1 (ANT 1) and Antenna 2 (ANT The Y and C signals are then sent to Q501 the Video
2) inputs allow two separate RF signals to be connected to Chroma Deflection Processing IC. A sync signal is tapped
the RF switcher. When the switch, which is controlled by off the Y signal and applied to Q501. Q501 processes the
the microcomputer, QA01, is in the up position the ANT 1 video signal and sends separate R, G, and B signals to the
signal is connected to the HY01 PIP Tuner/IF and the H001 CRT drives and the CRTs.
Main Tuner. Moving the switch down connects the ANT
2 signal to the H001 Tuner. Due to the RF Switch the ANT If the PIP feature is selected, composite video from AV
2 signal can’t be used as the PIP source, but when ANT 2 Switcher is sent to the PIP circuit, ZY01. After processing,
is selected the ANT 1 signal is available at RF OUT. The the PIP signal is sent to Q501 as R, G, B, and YS where it
PIP Tuner/IF produces a composite video (CV) signal and is mixed with the main video.
sends it to the AV Switcher, QV01. An IF signal produced
by the Main Tuner is sent to H002, which produces a
On screen display (OSD) R, G, and B signals produced by
composite video signal and sends it to the AV Switcher.
the Microcomputer, QA01, are mixed with the Extended
Data Service (EDS) and Closed Caption (CC) data in
Three video inputs, video 1 through 3, are applied to the AV UM01. These new signals are applied to an OR gate,
Switcher. The video 1 input can be composite video, Y/C QB91, and combined with the convergence signals from
video, or the test signal from QA01. Video 2 is composite the digital convergence circuit. The convergence signals
video only, and video 3 is either composite video or Y/C can be either the customer convergence cross hairs, or the
video. A mechanical switch on the video 1 input defaults service cross hatch pattern. All of these signals are sent to
to the test signal, so a video connector must not be plugged Q501 where they are mixed with the main video signal.
1-9
TEST E031Z
9
VIDEO 1 CV/Y 12
RED CRT RED CRT
C DRIVE
14
VIDEO 2 CV QV01 3
E032Z
AV GREEN CRT GRN CRT
CV/Y
VIDEO 3 16 DRIVE
C
18
SWITCHING
E033Z
RF HY01 PIP
9
BLUE CRT BLUE CRT
SWITCH TUNER/IF 15 R G B DRIVE
ANT 1 CV
Figure 1-7 Video Signal Flow Block Diagram
28
43 42 41
H001 C C
RF
Q503
OUT MAIN
TUNER
34 13
Q501
ANT 2
IF Y Y
2 MAIN VIDEO
Q202
H002 36 15 INPUT
CONTROL
IF/MTS
1-10
FROM
SYNC
QA01 A. PRO
7
Q204
17
VIDEO CHROMA
7 DEFLECTION
EQ CV
38 30 32 42 1 YS 32 PROCESSING
CV TO VIDEO
CV Y C 4 R 35
OUT JACK 6 2 4 CV 8 ZY01 PIP VIDEO
TEST SIGNAL G 34
DIGITAL PIP 5
INPUT
TO VIDEO 1 33
COMB 6 B
FILTER FROM
QA01 OR, 3D - Y/C
YS
R
DIGITAL
CONV.
MICRO G
9 CV B 10 4 13 1
COMPUTER YS
18 6
YS
2 3
YS
R UM01 R R
36
OSD, EDS, CC, &
22 1
OSD G
19 EDS/CC G
12 OR 11
G
39 CONVERGENCE
DATA 23 20 RGB SW. 5 5 6 38 VIDEO INPUT
B B QB91 B
24 21 2 9 8 37
9. AUDIO SIGNAL FLOW BLOCK DIAGRAM
Audio Signal Flow
Audio signals are applied to the AV Switcher from the jumper is removed so a center signal can be switched in to
three video jacks, H002, and the PIP Tuner, as shown in replace the main left and right signals. The amplified left
Figure 1-8. Like the video signal, there must not be a and right audio signals are applied to the internal/external
connector in the video 1 jack for the audio test signal to be speaker switch and routed to the desired speakers.
applied to the AV Switcher. In the TP48E90, PIP audio is
applied to the PIP output jack. The main audio signals are Sets equipped with Dolby or Dolby Pro Logic have a
applied to the audio output jacks and to the Front Surround surround audio signal that is sent to the audio processor in
circuit, the DSP/Dolby circuit, or the Dolby Pro Logic H002 from the Dolby circuit. The surround signal is then
circuit. Afterprocessing, the left and right audio signals sent to the rear amplifier, Q641, amplified, and applied to
are applied to the audio processor in H002 where the the rear speakers. In the TP48E90 the surround signal is
volume, balance, treble, and bass are controlled. Next, the routed through an amplifier in Q690 before it is applied to
audio signals are amplified by QS101 and applied to the Q641. Also, the TP48E90 is equipped with Dolby Pro
variable output jacks, and Q601. If the sub bass system Logic, and has a center channel. The center channel is
(SBS) is selected, a signal is mixed with the left and right amplified by the Center Amplifier, Q621, and applied to
signals just before Q601 to increase the signals bass the front speakers through the internal/external speaker
response. In TP55E80/81 and TP61E80 models, the switch.
8
L
VIDEO 2
VIDEO 1
L
TEST SIGNAL
FROM QA01
11
13
QV01 9
15
R
L
R AV 17
R
VIDEO 3
MONO AUDIO 29
SWITCHING 1
FROM HY01 31 L TO PIP OUT JACK
PIP TUNER 2 (TP48E90 ONLY)
L 5 R
R 6
37 35 QV14
IF H002 L TO AUDIO
FROM H001 OUT JACK
MAIN TUNER IF/MTS/A. PRO R
L 3 R 2 QS04
23 26 24 22 17 16 18 L
6 11 2 12
R L FRONT SURROUND,
SURROUND
R DSP/DOLBY, CENTER OUT
TP48E90 5 OR 4 7
TP55E80/81
SURROUND OUT DOLBY PRO LOGIC
TP61E80
10 Q621
SBS (SUB BASS SYSTEM) CENTER AMP
TP48E90 ONLY
TO &FROM CENTER
INPUT SWITCH & JACK
TP55E80/81 & TP61E80
ONLY
5 7 5 7
+ FRONT OR
L L INT/EXT CENTER
3 1 2 11 SWITCH SPEAKERS
+
R R L R
QS101 R TO VARIABLE AUDIO Q601
EXTERNAL
L OUT JACK
2 12
REAR
1 4 7 SPEAKERS
3
Q690 TP48E90 Q641
ONLY
REAR AMP
Figure 1-8 Audio Signal Flow Block Diagram
1-11
10. POWER SUPPLY AND PROTECTION BLOCK DIAGRAM
The E model PTVs actually have three separate power The Control/Protection circuit, Z801, has two functions.
supplies as shown in Figure 1-9. These supplies consist of The first is to regulate the Main Switch Mode Supply, and
the Standby Supply, the Main Switch Mode Supply, and the second is to monitor over current, over voltage, and
the Sub Switch Mode Supply. The Standby Supply provides under voltage sensors throughout the set. If any one of
the 5 VDC needed to run the microcomputer and the these sensors activates the protection circuit, Z801 turns
customer interface controls, such as the key pad and the IR off the switch powering the two switch mode supplies thus
receiver. When the set is turned on, the switch closes to turning off the set. If this occurs, a red LED on the front
activate the two switch mode supplies and provide the panel flashes at half second intervals, and the set must be
numerous DC voltages needed to operate the set. unplugged to reset Z801.
STANDBY +5VDC
TO MICROCOMPUTER
REGULATOR RESET
REG +5VDC
+30VDC
SWITCH REG +15VDC
120VAC SWITCH MODE +15VDC
(SUB) -15VDC
REG -9VDC
+12VDC
SWITCH
MODE +38VDC
(MAIN)
+125VDC
FEEDBACK
3
POWER
POWER Z801
OFF
ON/OFF FROM
16 CONTROL/PROTECTION 1
MICROCOMPUTER
13 14 OVERCURRENT,
OVERVOLTAGE, &
X-RAY SENSING
UNDER VOLTAGE
SENSING
Figure 1-9 Power Supply/Protection Block Diagram
1-12
11. HORIZONTAL AND VERTICAL DEFLECTION
Deflection circuitry in the E model PTV’s is rather straight Vertical drive (VD) is applied to the DPC circuit, U421, to
forward as show in Figure 1-10. The horizontal pulse from correct any distortions before it’s sent to the Vertical Drive
Q501 drives the horizontal drive circuitry, which in turn circuit, Q301. Then the vertical drive circuit supplies the
drives the Horizontal Yokes and the Flyback Transformer, signals required by the yokes for deflection.
T461. Numerous low voltage DC supplies are produced by
the Flyback, as well as the high voltages for the anode, To enhance horizontal transitions between dark and light
focus, and screen drives. To prevent excessive high areas of the picture, a Velocity Scan Modulation (VSM)
voltages, a sample X-Ray protection voltage is monitored signal is produced by Q501. This signal is sent to the SVM
by the over voltage protection circuits. circuit, E036Z, which in turn drives the SVM coils on the
CRTs.
HV HV R 30.7KV
AC TO HEATERS
+23VDC TO X-RAY
T461 DIST
BLOCK
G
B
TO CRT
ANODES
PROTECT 9
FLYBACK
+12VDC TRANSFORMER
7
2 R FOCUS &
+35VDC FOCUS
6 G SCREEN DRIVE
BLOCK
-27VDC B TO CRTs
5
+200VDC
3
+125VDC FROM 8 TO ABL
MAIN POWER 2 CIRCUIT
1
HORIZ
DRIVE
H-OUT HORIZ
Q501 23 DRIVE
TO HORIZ
YOKES
VIDEO
CHROMA
DEFLECTION
PROCESSING VD 4
U421 4
Q301 TO VERT
31 DPC 6 VERTICAL 2 YOKES
CIRCUIT DRIVE
48
VSM
EO36Z 1 TO SVM
2 SVM COILS
CIRCUIT
Figure 1-10 Horizontal and Vertical Deflection Block Diagram
1-13
12. I2C Communications
REG ADJUSTMENT PRESET
The TG-1 chassis uses I2C data communications to RCUT RED CUTOFF 40
control all customer features and most of the service GCUT GREEN CUTOFF 40
adjustments that where previously done with discrete BCUT BLUE CUTOFF 40
devices, refer to Figure 1-11. All communications RDRV RED DRIVE 40
BDRV BLUE DRIVE 40
are controlled by the Microcomputer, QA01 through
CNTX SUB-CONTRAST MAX 7F
serial data lines (SDA) and serial clock lines (SCL). BRTC SUB-BRIGHT CENTER 80
Memory settings for customer controls and service COLC SUB-COLOR CENTER 50
adjustments (except convergence data) are stored in TNTC SUB-TINT CENTER 40
the E2PROM Memory, QA02, and communicated SCOL SAP-COLOR 15
to QA01 by the SCL0 and SDA0 lines. Data and SCNT SUB-CONTRAST 15
clock lines SDA1 and SCL1 communicate with HPOS HORIZ. POSITION 16
VPOS VERTICAL POSITION 00
most of the circuits in the set. However, there are
HIT VERTICAL HEIGHT D1
three plug in circuits where the data and clock GMPS GMPS 00
signals are buffered by QB90 to provide isolation. VLIN VERTICAL LINEARITY 12
VSC A-S CORRECTION 08
All customer functions and most services VPS VERTICAL SHIFT 15
adjustments are implemented through the Key Pad VCP V-COMPENSATION 03
WID PICTURE WIDTH 25
and the Remote Sensor. The RMT OUT signal on TRAP TRAPEZIUM 10
the microcomputer drives the IR Transmitter on the HCP H-COMPENSATION 02
front panel, but it’s only used in the manufacturing VFC V-F CORRECTION 0F
process. Figure 1-12 shows the Service Registers STRH HORIZ. START POSITION 82
and their default values used for making adjustments
in the set. Figure 1-12 Service Register Default Values
KEY REMOTE
PAD SENSOR
18 KEY B 35 IC501 H001

H002 HY01
17
V/C/D IF/MTS/A.PRO TUNER TUNER/IF
PROCESSING
KEY A
SDA1
QA01 38 27 28 21 20 4 3
SCL1
MICRO- 37 9 10 25 24 1 2 44 43
COMPUTER
COMB FILTER QAV01 Q701
U421
OR AV CONV.
DPC CIRCUIT
3D-Y/C SWITCHING PROCESSOR
TO IR
LED RMT OUT
3
TRANS
11 12
F. SURR., ZY01 UM01
SCL0 SDA0 DSP/DOLBY, PIP EDS/CC
D. PRO LOGIC CIRCUIT RGB SW.
6 5
14 15 14 13 14 13
3 SDA2
QA02
EEPROM 5
MEMORY 2 SCL2
6
QB90
Figure 1-11 I2C Communication Block Diagram
1-14
13. Digital Convergence
The TG-1 model PTV’s are equipped with a new digital by the pre amps (Q715, Q717, & Q719) and power amps
convergence circuit shown in Figure 1-13. This circuit (Q751 & Q751) before being applied to the convergence
allows servicers to set the convergence with the remote yokes. The Power Amps Q752 and Q751 dissipate allot of
control. Q701, the Digital Convergence Processor aligns heat because of their current draw, so the supplies to these
the convergence from data received from the remote, and amps have a number of sensors for over current conditions.
saves the settings in the E2PROM, Q713. The digital Most of the convergence circuit is on a shielded board, but
convergence signals are converted to analog by the D/A the power amps are easily accessible for service.
Converters Q703, Q704, and Q705. Then they are amplified
Q713
EEPROM
Q752
6 5
DATA RH
CLK 45 46 15 18
RH 7 20 GH
Q703 14 11
86 D/A 3 1
RV 6 1 Q715
Q701 87 CONV. 5 7 BH
43 6 9
CLK GH 7 20
Q704 TO
FROM DIGITAL 89 3 1
GV 6 D/A 1 Q717 CONV.
QAO1 44 CONVERGENCE
DATA 90 CONV. 7 YOKES
PROCESSOR 5
BH 7 Q705 20 RV
15 18
96 D/A 5 7
BV 6 1 Q719
97
CONV. 1 GV
3
14 11
31 32
BV
6 9
HD VD Q751
FROM FROM
IC501 Q301
Figure 1-13 Convergence Block Diagram
1-15
LAB 1
BASIC OPERATION AND UNIT UNDERSTANDING
As a servicer, it is important now, more than ever, to fully understand the operation and functions of
a television set before proceeding with a repair. This is because many of the problems encountered by
a customer today can be caused by an incorrect menu selection or improper setup.
Therefore, the purpose of this lab is to familiarize you with menus and features of the television from
the customer’s point of view.
SECTION ONE
BASIC OPERATION
1. Verify that the unit is connected to an AC supply, and that a signal is connected to the ANT 1
input. While verifying signal connections, take time to examine all of the inputs on the rear and
front (behind door) of the unit.
2. Turn on the set with the remote control and tune to an active channel. Refer to page 9 of the
service manual provided and familiarize yourself with all of the keys on the remote paying,
particular attention to the following keys:
o EDS
o TIMER
o PIP Functions
Open the bottom door on the remote control by sliding it down. Try each key starting with the upper
row. Each of these buttons brings up another menu and/or sub-menus.
3. In the Picture Menu, What is Color Temperature?
____________________________________________________________________________
____________________________________________________________________________
4. In the Audio Menu, Where can the speakers be turned off by the user?
____________________________________________________________________________
____________________________________________________________________________
5. In the Setup Menu, What is Favorite Channel?, What is Channel Lock?
____________________________________________________________________________
____________________________________________________________________________
1-16
6. Refer to page 16 of the Service Manual and perform the User Convergence Adjustments. How
is this different from previous Toshiba PJTVs?
____________________________________________________________________________
____________________________________________________________________________
7. In the Option Menu, How many different languages are there? What are they used for? What is
Channel Label Used for?
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
NOTES:
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
SECTION TWO
DISASSEMBLY & SERVICE POSITION
Follow the procedure listed below to gain access to the tubes and circuit boards.
1. Remove the speaker grill by holding the sides and pulling straight out.
2. Take out the four screws holding the plastic shield in place. Then remove the shield.
3. Remove the control wires from the holder on the metal shield in front of the CRTs.
4. Remove the 4 screws holding the metal shield in place. The shield is notched, so slide it to the
right then down to remove it.
5. Remove the two screws holding the front control panel. Then release the tabs on either side and
let it hang down out of the way.
6. Remove the 4 screws holding the bottom of the screen. Then lift up on the top of the screen and
pull it away from the cabinet.
1-17
7. Remove the 5 screws holding the back panel. Then remove the back panel.
8. Reattach the control panel to the light box.
9. Remove the six screws on the front of the light box.
10. Remove the three screws on the back of the cabinet.
11. Remove the one screw holding the back of the light box to the cabinet.
12. From the front of the set, lift the light box up just a little, and pull it towards you.
13. Pull the light box all the way out of the cabinet and turn it on its side.
CAUTION: the light box weighs about 85 pounds, so get help if you need it.
SECTION THREE
IDENTIFICATION
1. Identify each of the board assemblies and note their locations. Use Figure 1-5 to help you
identify the various boards.
o Convergence/Output/Power Board
o Deflection/Power Board
o Main PCB
o Front Surround Board
o Digital Comb Filter Board
o PIP Board
o EDS/CC Board
2. Is there a convergence board in this unit?

If so, where?
____________________________________________________________________________
____________________________________________________________________________
3. How does this convergence setup differ from previous models?
____________________________________________________________________________
____________________________________________________________________________
4. Examine the Flyback and HV lead assemblies. What is different about this area from earlier
models?
____________________________________________________________________________
____________________________________________________________________________
1-18
5. Is it possible for one technician to perform a service call on this type of unit?
____________________________________________________________________________
____________________________________________________________________________
6. Put the lightbox in the cabinet, but don't screw it in. Then replace the screen and control panel.
Use a few screws to hold the screen and control panel in place.
SUMMARY
In this lab, the operation and function of the unit was determined, and the unit was set up for service
on the bench. Common user type problems in addition to overall serviceability was also discussed.
END OF LAB 1
1-19
LAB 2
TEST SIGNALS, SELF DIAGNOSTICS, & SERVICE REGISTERS
OBJECTIVES: After completing this lab you will be able to:
1. Enter and exit the set’s internal video and audio test signals.
2. Use the test signals for troubleshooting.
3. Use the set’s self diagnostic feature.
4. Make adjustments in the set with the service registers via the remote control.
SECTION ONE
VIDEO TEST SIGNALS
1. Verify that the unit is connected to an AC supply, and that a signal is connected to the ANT 1
input.
2. Enter the service mode by pressing mute on the remote. Press and hold mute a second time
while pressing menu on the control panel. An S appears in the upper right corner of the screen
indicating that the set is in the service mode. Press menu and the RCUT register appears in the
upper left corner of the screen.
3. Push the TV/VIDEO button on the remote once to enter the internal test pattern mode. The
screen should be red.
4. Slowly cycle through the test signals with the TV/VIDEO button until the white cross hairs on
a black background appear. (If the TV/VIDEO button is pushed in rapid succession, the set will
jump out of the test signal mode to one of the inputs - ANT 1, VIDEO 1, VIDEO 2, or VIDEO
3. The set is still in the service mode, so if this occurs, push the menu button then the TV/
VIDEO button to get back into the test signal mode.)
5. Plug a video cable into the VIDEO 1 input jack (make sure the other end of the cable is not
plugged into a video source)
6. What happened to the cross hairs?
____________________________________________________________________________
____________________________________________________________________________
7. If something did happen to the cross hairs, why did it happen?
____________________________________________________________________________
____________________________________________________________________________
1-20
8. Is there video on the screen?
____________________________________________________________________________
____________________________________________________________________________
9. If there is video on the screen, where does it come from?
____________________________________________________________________________
____________________________________________________________________________
10. Unplug the video cable.
SECTION TWO
AUDIO TEST SIGNALS
1. Push the 8 button on the remote to activate the audio test signal. (NOTE: The internal test
pattern mode must be activated for this feature to work.)
2. Push the mute button twice. Now you can control the volume of the signal.
3. Select AUD on the remote control.
4. Select BALANCE and adjust it from left to right with the + and - buttons.
5. Select SPEAKERS and turn them off then on. (NOTE: The speakers are turned off at Q601,
refer to Figure 1-8, while the volume, bass, treble, and balance are controlled in H002. This
means you can troubleshoot most of the audio system with the speakers off.)
6. Plug an audio cable into the left AUDIO 1 input jack (make sure the other end of the cable is
not plugged into an audio source)
7. What happened to audio?
____________________________________________________________________________
____________________________________________________________________________
8. If something did happen to the audio, why did it happen?
____________________________________________________________________________
____________________________________________________________________________
9. Push the 8 button to turn off the audio test signal.
10. Cycle the video test signals back to the ANT 1 signal with the TV/VIDEO button.
1-21
SECTION THREE
SELF DIAGNOSTICS
1. Push the 9 button to activate the self diagnostic feature.
2. What does POWER indicate?
____________________________________________________________________________
____________________________________________________________________________
3. What does BUS LINE indicate?
____________________________________________________________________________
____________________________________________________________________________
4. What does BUS CONT indicate?
____________________________________________________________________________
____________________________________________________________________________
5. What does BLOCK indicate?
____________________________________________________________________________
____________________________________________________________________________
6. Push the EXIT button to exit the self diagnostic feature.
7. Select the VIDEO 1 input with the TV/VIDEO button. (Make sure there is no signal applied to
VIDEO 1)
8. Push MENU on the control panel to display the registers.
9. Push 9 to activate the self diagnostic feature.
10. Is the display different from the previous display. ______
11. If it is, explain why.
____________________________________________________________________________
____________________________________________________________________________
12. Push the EXIT button to exit the self diagnostic feature.
13. Push MENU on the control panel to display the registers.
1-22
SECTION FOUR
SERVICE REGISTERS
NOTE: In each of the following exercises write down the register’s value before adjusting it. Then
restore the register to its original value before proceeding to the next exercise.
1. Enter the internal test pattern mode and select the test signal that has a white window in the
upper center of a black background as shown below.
2. Increase the RCUT register value and describe its effect on the picture.
RCUT______
____________________________________________________________________________
____________________________________________________________________________
3. Change the test signal to the white on black cross hatch pattern as shown below.
4. Select the HPOS register and vary its value between 00 and 1F. Describe its effect on the
picture. What happens if you increase the register to 20?
HPOS______
____________________________________________________________________________
____________________________________________________________________________
5. Select the VPOS register and vary its value between 00 and 07. Describe its effect on the
picture. What happens if you increase the register to 08?
VPOS______
____________________________________________________________________________
____________________________________________________________________________
1-23
6. Select the HIT register and vary its value 5 steps above and below the recorded value.
Describe its effect on the picture.
HIT______
___________________________________________________________________________
____________________________________________________________________________
7. Select the VLIN register and vary its value 8 steps above and below the recorded value.
VLIN______
___________________________________________________________________________
____________________________________________________________________________
8. Select the WID register and vary its value 8 steps above and below the recorded value.
WID______
___________________________________________________________________________
____________________________________________________________________________
9. Select the STRH register and vary its value 8 steps above and below the recorded value.
STRH______
___________________________________________________________________________
____________________________________________________________________________
SUMMARY
Now that you have completed Lab 2, you should be able to use the internal video and audio test
signals, the self diagnostic feature, and the service registers for making adjustments.
END OF LAB 2
1-24
SECTION II
TUNER, IF/MTS/S.PRO MODULE
2-1
1. CIRCUIT BLOCK
H002 - IF/MTS/A.PRO Module MVUS34S
EL466L SIF
VIF/SIF output Sound
H001 SAW
Multiplex A.PRO Circuit
Main Tuner Filter Circuit Circuit
RF AGC
C-IN
R-IN L-IN
TP12 TV TV
Video output R-OUT L-OUT
C-OUT
R-OUT
To A/V switch circuit L-OUT (L+R)
AFT output -OUT
Fig. 2-1 Block diagram
1-1. Outline
(1) RF signals sent from an antenna are converted into (5) VIF/SIF circuit uses PLL sync detection system to
intermediate frequency band signals (video: 45.75 MHz, improve performances shown below:
audio: 41.25 MHz) in the tuner. (Hereafter, these signals • Telop buzz in video over modulation
are called IF signals.) • DP, DG characteristics (video high-fidelity
(2) The IF signals are band-limited in passing through a reproduction)
SAW filter. • Cross color characteristic (coloring phenomenon at
(3) The IF signals band-limited are detected in the VIF color less high frequency signal objects)
circuit to develop video and AFT signals. (6) HIC SBX1637A-22 is used in the audio multiplexer
(4) The band-limited IF signals are detected in the SIF circuit to minimize the size with increased performance.
circuit and the detected output is demodulated by the (7) As a sound control processor, TA1217N is used. I2C-
audio multiplexer, developing R and L channel outputs. bus data control the DAC inside the IC to perform
These outputs are fed to the A/V switch circuit. switching of the audio multiplexer modes.
(5) A sound processor (S.PRO.) is provided.
1-2. Major Features

(1) The VIF/SIF circuit is fabricated into a small module
by using chip parts considerably.
(2) As the tuner, EL466L that which contains an integrated
PLL circuit is employed.
(3) Wide band double SAW filter F1802R used.
(4) FS (frequency synthesizer) type channel selection system
employed.
2-2
1-3. Audio Multiplex Demodulation Circuit Then, both are fed to the matrix circuit. At the same time,
The sound multiplex composite signal FM-detected in the each of the stereo pilot signal fH and the SAP pilot signal 5fH
PIF circuit enters pin 12 of HIC (hybrid IC) in passing is also demodulated to obtain an identification voltage. With
through the separation adjustment VR RV2 and amplified. the identification voltage thus obtained and the user control
After the amplification, the signal is split into two: one enters voltage are used to control the matrix.
a de-emphasis circuit, and only the main signal with the L-R The audio signals obtained by demodulating the sound
signal and a SAP signal removed enters the matrix circuit. At multiplex signal develop at pin 10 and 11 of HIC and develop
the same time, the other passes through various filters and the terminals of 12 and 14 of the module.
trap circuits, and the L-R signal is AM-demodulated, and the
SAP is FM-demodulated.
MVUS34S
MPX TV DAC-out1 TV DAC-out2

Out R-Out (SURR ON/OFF) L-Out (RFSW)
9 10 11 12 13 14 15
Monitor the input Stereo 0V SAP 0V OFF 0V RF1 0V

pin for multiplex
sound IC Other 5V Other 5V ON 9V RF2 9V
TV waveform detection TV waveform detection

output (R) output (L)
To AV select circuit
Fig. 2-2 Block diagram of MVUS34S
Table 2-1 Matrix for broadcasting conditions and Note:

reception mode Of the mode selection voltages, switching voltages for STE,
SAP, MONO do not output outside the module.
Output OSD display
Broad- Switching They are used inside the module to control the BUS.
12 pin 14 pin
casted mode Stereo SAP
(R) (L)
Stereo STE R L Y N
SAP R L Y N
MONO L+R L+R Y N
Mono STE L+R L+R N N
SAP L+R L+R N N
MONO L+R L+R N N
Stereo STE R L Y Y
+ SAP SAP SAP Y Y
SAP MONO L+R L+R Y Y
Mono STE L+R L+R N Y
+ SAP SAP SAP N Y
SAP MONO L+R L+R N Y
2-3
1-4. A.PRO Section (Audio Processor) All these processing are carried out according to the BUS
The S.PRO section has following functions. signals sent from a microcomputer.
(1) Woofer processing (L+R output)
(2) High band, low band, balance control Fig. 2-3 shows a block diagram of the A.PRO IC.
(3) Sound volume control, cyclone level control
(4) Cyclone ON/OFF
TA1217N
1 27 29 22 32 36 30 9 8 28
Lin 34 26 L out
BALANCE
TONE CONTROL
Rin 30 25 R out
2 Center
Cin LEVEL VOLUME
18 C out
10 W out
Win 3 Woofer 17
LPF
LEVEL
16
15
I/O
14
SDA 20 13
2
I C D/A
12 SAP Ident.
CONV
SCL 21 11 STE Ident.
4 5 6 7 31 24 23 22 19
16 17 18 19 20 21 22 23 24 25 26 27
R-in C-in L-in SCL1 SDA1 W-out C-out L-out R-out

9V
From From From to Q601 to Q641 to Q601 to Q601

A/V Dolby A/V SBS
Via QS101
Fig. 2-3 A.PRO block diagram
2-4
Configuration of the audio circuit and signal flow are given
in Fig. 2-4
A/V PCB
VIF+MTS+S.PRO
MODULE QV01 FOR PIP
IF MODULE
R 12 EQ 6 R From L 29
FromPIP
Main Tuner R 31 EN AUDIO
L 14 ER 5 L Tuner
L 2 L PIP OUT
R L PIP
TP48E90 ONLY
VIDEO1 11 L OUTPUT R 1 R (AUDIO)
VIDEO1
13 R
R L
VIDEO2 8 L VIDEO
VIDEO2
9 R OUTPUT Q601
TERMINAL VIF+MTS+A.PRO
R L MODULE
VIDEO3 AF 15 L R
(FRONTINPUT) VIDEO3 ROUT 26 + 2 11
AG 17 R R
R 35 AS
DSP 16 R L
L OUT 24 + 5 7
CIRCUIT
L 37 AR 18 L
L
WOUT 22
R L
VARIABLE
AI
AUDIOOUTPUT
TERMINAL AJ
Fig. 2-4
2-5
2. PIP TUNER
Lable
TUNER SAW VIF/SIF Name
SECTION FILTER CIRCUIT Lot No.
RF AGC
AFT VIDEO AUDIO

OUTPUT OUTPUT OUTPUT
1 15
Fig. 2-5 Terminal No. Name

1 NC
2-1. Outline 2 32V
The PIP tuner (EL922L) consists of a tuner and an IF block 3 S-CLOCK
integrated into one unit. The tuner receives RF signals 4 S-DATA
induced on an antenna and develops an AFT output, video 5 NC
output, and audio output. 6 ADDRESS
The tuner has receive channels of 181 as in the tuner for the
7 5V
main screen and it is also controlled through the I2C-bus.
As the IC for the IF, a PLL complete sync detection plus 8 RF AGC
audio inter carrier system are employed. 9 9V
10 AUDIO
11 GND
12 AFT
13 NC
14 GND
15 VIDEO
Fig. 2-6 Tuner terminal layout
2-6
SECTION III
CHANNEL SELECTION CIRCUIT
3-1
1. OUTLINE OF CHANNEL SELECTION • Setting of memory values for video parameters
CIRCUIT SYSTEM such as white balance (RGB cutoff, GB drive) and
gcorrection, etc.
The channel selection circuit in the N5SS chassis employs a • Setting of video parameters of video modes
bus system which performs central control by connecting (Standard, Movie, Memory)
a channel selection microcomputer to a control IC in each
circuit block through control lines called a bus. This bus (3) CONTROL OF A/V SWITCH IC (QV01 Toshiba
system herin referred to as the I2C bus system (two line bus) TA1218N)
is licensed from and was developed by Philips. • Preforms source switching for main screen and
sub screen
Integrated circuits controlled by the I2C bus system are : • Performs source switching for TV and up to three
QN06 for audio signal processing, Q501 for V/C/D signal video inputs
processing , QV01 for A/V switching, QA02 for non
volatile memory, main and sub U/V tuners (H001, HY01), (4) CONTROL OF NON-VOLATILE MEMORY IC
Q302 for deflection distortion correction, QY04 for PIP (QA02 Microchip 24LC08BI/P)
signal processing, QM01 for DSP, and Q701 for closed • Memorizes data for video and audio signal
caption control. adjustment values, volume and woofer adjustment
values, external input status, etc.
Differences from the previous N5SS chassis include; • Memorizes adjustment data for white balance
1. On-screen display generation now originates within (RGB cutoff, GB drive), sub-brightness, sub color,
ICA01. A separate IC is no longer used. sub tint, etc.
2. The microcomputer does not perform the closed • Memorizes deflection distortion correction value
caption function, but instead controls a separate IC data adjusted for each unit.
for this purpose.
3. The system uses two sperate channels of I2C bus. One (5) CONTROL OF U/V TUNER UNIT (H001 Matsushita
of these is dedicated for communication with the EL466L, HY01 Toshiba EL922L)
non-volatile memory. • A desired channel can be tuned by transferring a
channel selection frequency data (divided ratio
2. OPERATION OF CHANNEL data) to the I2C bus type frequency synthesizer
SELECTION CIRCUIT equipped in the tuner, and by setting a band
switch which selects the UHF or VHF band.
An 8 bit, Toshiba microcomputer (series TLCS-870) is
(6) CONTROL OF DEFLECTION DISTORTION
used within the television as ICA01. Part number
CORRECTION IC (Q302 Toshiba TA8859P)
TMP87CS38N-3152 or similar is employed.
• Sets adjustment memory value for vertical
With this microcomputer, each IC and circuit shown below
amplitude, linearity, horizontal amplitude,
are controlled.
parabola, corner, trapezoid distortion.
(1) CONTROL OF AUDIO SIGNAL PROCESS IC (QN06
(7) CONTROL OF PIP SIGNAL PROCESS IC (QY04
Toshiba TA1217N)
Toshiba TC9083F)
• Adjustments for volume, treble, bass and balance
• Controls ON/OFF and position shift of PIP.
• Selection between surround mode and DSP mode,
and level adjustment
(8) CONTROL OF DIGITAL SOUND PROCESSOR IC
• Level adjustment of BAZOOKA (Sub-Bass)
(QM04 Yamaha YSS238-D)
system
• Performs mode switching of DSP.
• Audio muting during channel selection or no signal
reception.
(9) CONTROL OF CLOSED CAPTION/EDS (QM01
Motorola XC144144P)
(2) CONTROL OF VIDEO/CHROMA/DEF SIGNAL
• Controls Closed Caption/EDS.
PROCESS IC (Q501 Toshiba TA1222N)
• Adjustments for uni-color, brightness, tint, color
gain, sharpness and PIP uni-color
• Setting of adjustment memory values for sub-
brightness, sub-color and sub-tint, etc.
3-2
3. MICROCOMPUTER
The main Microcomputer TMP87CS38N-3152 has 60k one chip.

byte of ROM capacity and is equipped with an internal OSD IIC device controls through I2C bus. (Timing chart : See fig.
function. 3-1)
The specification is as follow. • Pin 8, (LED) is used to source current and is an output
• Type name : TMP87CS38N-3152 only.
• ROM : 60k byte • For clock oscillation, an 8MHz ceramic oscillator is
• RAM : 2k byte used.
• Processing speed : 0.5m s (at 8MHz with Shortest • I2C has two channels. One is for EEPROM only.
command) • A Self diagnosis function which utilizes the ACK
• Package : 42 pin shrink DIP function of I2C is employed
• I2C-BUS : two channels • Function indication is added to service mode.
• PWM : 14 bit x 1, 7 bit x 9 • Operation by remote control is possible, and controls
• ADC : 8 bit x 6 (Successive comparison system, and adjustments can be made with no physical contact
Conversion time 20ms) is possible. (Bus connector in the conventional bus
• OSD chassis is deleted.)
Character kinds : 256 • Substantial self diagnosis function
Character display : 24 characters x 12 lines (1) B/W composite video signal generating function
Character dot : 14 x 18 dots (inside micon, green crossbar added)
Character size : 3 kinds (Selected by line) (2) Generating function of audio signal equivalent
Character color : 8 colors (Selected by character) to 1kHz (inside micon)
Display position : Horizontal 128 steps, Vertical (3) Detecting function of power protection circuit
256 steps operation
This microcomputer performs the functions of an Analog to (4) Detecting function of abnormality in I2C bus
Digital converter, reception of U/V TV and OSD display in line
(5) Functions of LED blink indication and OSD
indication
(6) Block diagnosis function which uses new VCD
and AV SW
SDA
SCL 1-7 9 1-7 1-7 8 9

8 8 9
Start Address R/W Ack Data Ack DATA Ack Stop

condition condition
Approx.180m S Some device may have no data,
or may have data with several
bytes continuing.
Fig. 3-1
3-3
4. MICROCOMPUTER TERMINAL FUNCTION
TMP87CS38N3152 (QA01)
GND 1 GND VDD 42 VDD
BAL 2 I P40 (PWM0) P57 I 41 ACP
REM OUT 3 O P41 (PWM1) P32 40 NC
MUTE 4 O P42 (PWM2) P57 39 GND
SP MUTE 5 O P43 (PWM3) SDA0 IO 38 SDA1

IIC-
BUS
NC 6 O P44 (PWM4) SCL0 O 37 SCL1
POWER 7 O P45 (PWM5) (TC3)P31 I 36 SYNC AV1
LED 8 O P46 (PWM6) (RXIN)P30 I 35 RMT IN
NC 9 O P47 (PWM7) P20 I 34 SW IN
NC 10 I P50 (PWM8/TC2) RESET I 33 RESET
SCL0 11 O P51 (SCL1) XOUT O 32 XOUT

IIC
-BUS
SDA0 12 IO P52 (SDA1) XIN I 31 XIN
SYNC VCD 13 I P53 (AINO/TC1) TEST I 30 TEST
NC 14 I P54 (AIN1) 0SC2 O 29 0SC1
AFT2 15 I P55 (AIN2) 0SC1 I 28 0SC2
AFT1 16 I P56 (AIN3) VD I 27 VSYNC
KEY-A 17 I P60 (AIN4) HD I 26 HSYNC
KEY-B 18 I P61 (AIN5) Y/BL O 25 Ys

SGV 19 O P62 B O 24 BOUT
SGA 20 O P63 G O 23 GOUT
GND 21 VSS R O 22 ROUT
Fig. 3-2
3-4
<< MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC >>
No. Terminal Name Function In/Out Logic Remarks

1 GND 0V
2 BAL INPUT BALANCE Out PWM out
3 REM OUT REMOTE CONTROL Out Remote control output
SIGNAL OUT
4 MUTE SOUND MUTE OUT Out Sound mute output
5 SP MUTE SPEAKER MUTE Out In muting = H
6 DEF POW Out
7 POWER POWER ON/OFF OUT Out Power control In ON=H
8 LED POWER LED OUTPUT Out Power LED on-control
LED lighting=L
9 POWER LNB Out 0V
10 LNB DET In 0V
11 SCL() IIC BUS CLOCK OUT Out IIC bus clock output 0
12 SDA() IIC BUS DATA IN/OUT In/Out IIC bus data input/output 0
13 SYNC VCD H SYNC INPUT In Main picture H. sync signal input
14
15 AFT2 IN In Sub tuner AFT S-curve input
16 AFT1 UV MAIN S-CURVE In Main tuner AFT S-curve
SIGNAL signal input
17 KEY A LOCAL KEY INPUT In Local key detection: 0 to 5V
18 KEY B LOCAL KEY INPUT In Local key detection: 0 to 5V
19 SGV TEST SIGNAL OUT Out Test signal output In normal=L 0V
20 SGA TEST AUDIO OUT Out Test audio output In normal=L 0V
21 VSS POWER GROUNDING — 0V: Gounding voltage 0V
22 R R Out At display on:Pulse
23 G G Out At dispaly on:Pulse
24 B B Out At dispaly on:Pulse
25 Y/BL BL Out At dispaly on:Pulse
26 HSYNC In HSYNC for OSD display Pulse
27 VSYNC In VSYNC for OSD display Pulse
28 OSC1 DISPLAY CLOCK Out 4.5MHz Pulse
29 OSC2 DISPLAY CLOCK In Pulse
30 TEST TEST MODE In GND fixed 0V
31 XIN SYSTEM CLOCK In System clock input 8MHz pulse
32 XOUT SYSTEM CLOCK Out System clock output 8MHz 8MHz pulse
33 RESET SYSTEM RESET In System reset input (In reset=L) 5V
34 SW IN
35 RMT IN REMOTE CONTROL IN In remote control pulse input=L In reception of
SIGNAL INPUT remote pulse
36 SYNC AV1 HSYNC INPUT In External H. sync signal input Pulse
37 SCL1 IIC BUS CLOCK OUT Out IIC bus clock output 1 Pulse
38 SDA1 IIC BUS DATA IN/OUT In/Out IIC bus data input/output 1 Pulse
39 GND 0V
40 NC
41 ACP NSYNC INPUT In AC pulse input
42 VDD POWER — 5V 5V
3-5
5. EEPROM (QA02)
EEPROM (Non volatile memory) has function which, in spite of power-off, memorizes the such condition as channel selecting
data, last memory status, user control and digital processor data. The capacity of EEPROM is 8k bits. Type name is 24LC08BI/
P or ST24C08CB6, and those are the same in pin allocation and function, and are exchangeable each other. This IC controls
through I2C bus. The power supply is common to the EEPROM and the main MICOM. Pin function of EEPROM is shown in
Fig. 3-3.
EEPROM(QA02)
A0 1 8 Vcc + 5V
Device address
A1 2 7 NC
GND
A2 3 6 SCL
I2C-BUS line
Vss 4 5 SDA
Fig. 3-3
6. ON SCREEN FUNCTION
ON SCREEN FUNCTION indicates data like channel, volume. Formerly, exclusive use of OSD IC was used, but in N5SS,
the OSD function is within the main microcomputer. Pin function concerning on-screen data generation is shown in Fig. 3-
4. Oscillation clock of OSD is approx. 4.5MHz. 9MHz which becomes multiplied by two to become the dot clock i slocated
within the microcomputer. For oscillation, a coil TRF1160D (LA02) is used.
QA01
OSC2 O 29 OSC2 OSC OUT
OSC1 I 28 OSC1 OSC IN
VD I 27 VSYNC H. SYNC SIGNAL
HD I 26 HSYNC V. SYNC SIGNAL
Y/BL O 25 Ys/Ym HALF TONE SIGNAL
B O 24 BOUT
G O 23 GOUT COLOR SIGNAL
R O 22 ROUT
VG
Fig. 3-4
3-6
7. SYSTEM BLOCK DIAGRAM
QA01
TMP87CS38N-3152
QA02 SDA 1 38
SCL 1 37 H001
MEMORY
24LC08B1/P
MAIN U/V TUNER
SDA SCL RMT 35 REMOTE
EL446L
SENSOR
5 6 UNIT SDA SCL
11 SCL 0
12 SDA 0 HY01
SUB U/V TUNER

KEY-A 17 EL922L
KEY SWITCH
H. SYNC PULSE 26 HSYNC KEY-B 18 SDA SCL
V. SYNC PULSE 27 VSYNC
RST 33
22 R VDD 42 POWER Q501
VIDEO SIGNAL
SUPPLY
PROCESS CIRCUIT 23 G GND 1 CIRCUIT VCD
24 B VSS 21 TA1222N
25 YS/TM POWER 7 SDA SCL
ACP 41 27 28
REMOTE CONTROL 3 RMT OUT
OUTPUT LED 8
H002
SOUND MUTE 4 MUTE XIN 31 8MHz
IF/MPX
SPEAKER MUTE 5 SP MUTE XOUT 32 CLOCK MVUS345
SDA SCL
Q701 OSCI 28 6.1MHz
21 20
OSCO 29 CLOCK
C/C, EDS
XC144144P SGV 19
DATA CLK SIGNAL
SGA 20 OUTPUT
MAIN SCREEN
SYNC-AV1 36 SYNC DET. QV01
AFT1 IN 16 AFT DET. AV SW

DPC UNIT TA1218N
SUB SCREEN SDA SCL
DATA CLK
SYCN-AV2 13 SYNC DET. 26 27
AFT2 IN 2 AFT DET.
QM01
QY04
DSP
SDA SCL
PIP CONTROL
DATA CLK
6 5
Fig. 3-5
3-7
8. LOCAL KEY DETECTION METHOD
Local key detection in the N5SS chassis is carried out by

using an analog voltage divider-like method which detects
a voltage appearing at the local key input terminals (pins 17,
15 16
18) of the microcomputer whenever a key is depressed.
Using this method, a maximum of 14 keys can be interpreted.
S15-1 S16-1
The circuit diagram shown at the left is a representation of
the local key circuit. As can be seen from the diagram, when
S15-2 S16-2 one of keys among SA-01 to SA-08 is pressed, each of two
input terminals (pins 17, 18) develops a voltage (Vin)
corresponding to the key pressed. (The voltage measurement
S15-3 S16-3 and key identification are carried out by an A/D converter
inside the microcomputer along with interpreting software.
S15-4 S16-4
S15-5 S16-5
S15-6 S16-6
S15-7 S16-7
Fig. 3-6. Local key assignment
Table 3-1 Local key assinment
Key No. Function Key No. Function

SA-02 POWER SA-01 DEMO START/STOP
SA-03 CH UP
SA-04 CH DN
SA-05 VOL UP
SA-06 VOL DN
SA-07 ANT/VIDEO, ADV
SA-08 MENU
3-8
9. ENTERING THE SERVICE MODE 11. SERVICE ADJUSTMENT
1. PROCEDURE 1. ADJUSTMENT MENU INDICATION ON/OFF,

(1) Press once MUTE key on the remote hand unit to MENU key ( on TV set)
indicate MUTE on screen of the television. 2. During display of the adjustment menu, the following
(2) Press the MUTE key of remote hand unit again and functions are possible:
keep depressed while depressing the MENU key on a) Selection of adjustment item :
the front of the unit. POS UP/DN key (on TV/remote unit)
b) Adjustment of each item :
2. During service mode, indication S is displayed at upper VOL UP/ DN key (on TV / remote unit)
right corner on screen. c) Direct selection of adjustment item
R CUTOFF : 1 POS (remote unit)
10. TEST SIGNAL SELECTION G CUTOFF : 2 POS (remote unit)
B CUTOFF : 3 POS (remote unit)
1. In OFF state of test signal, SGA terminal (Pin 20) and d) Data setting for PC unit adjustment
SGV terminal (Pin 21) are kept at a “L” condition. SUB CONTRAST : 4 POS (remote unit)
2. The function of VIDEO test signal selection is cyclically SUB COLOR : 5 POS (remote unit)
changed with each depression of the VIDEO key (on the SUB TINT : 6 POS (remote unit)
remote control unit). e) Horizontal line ON/OFF : VIDEO (TV)
(NOTE: applies only to direct view)
f) Test signal selection : VIDEO (remote unit)
* In service mode, serviceable items are limited.
Table 3-2 3. Test audio signal ON / OFF : 8 POS (remote unit)

* Test audio signal : 1kHz
Test Signal No. Name of Pattern
0 Signal OFF 4. Self check display : 9 POS (remote unit)

1 All black signal + R single color (OSD) * Cyclic display (including ON/OFF)
2 All black signal + G single color (OSD)

5. Initialization of memory :
3 All black signal + B single color (OSD) CALL (remote unit) + POS UP (TV)
6. Initialization of self check data :
4 All black signal
CALL (remote unit) + POS DN (TV)
5 All white signal 7. BUS OFF :
6 W/B CALL (remote unit) + VOL UP (TV)
7 Black cross bar
8 White cross bar
9 Black cross hatch
10 White cross hatch
11 White cross dot
12 Black cross dot
13 H signal (bright area)
14 H signal (dark area)
15 Black cross + G
(3) SGA (audio test signal) output should be square

wave of 1kHz.
3-9
12. FAILURE DIAGNOSIS PROCEDURE
The N5SS chassis is equipped with a self diagnosis function inside, used for troubleshooting.
1. CONTENTS TO BE CONFIRMED BY CUSTOMER BEFORE SERVICE CALL IS MADE
Table 3-3
Contents of self diagnosis Display items and actual operation
A. DISPLAY OF FAILURE INFORMATION Power indicator lamp blinks and picture does not come.
IN NO PICTURE (Condition of display)
1. When power protection circuit operates; 1. Power indicator red lamp blinks. (0.5 seconds interval)
2. When I2C-BUS line is shorted; 2. Power indicator red lamp blinks. (1 seconds interval)
If these indication appears, repairing work is required.
2. CONTENTS TO BE CONFIRMED BY SERVICER (Check in self diagnosis mode)
Table 3-4

<Countermeasure in case that phenomenon always arises.>
B. Detection of shortage in BUS line
C. Check of comunication status in BUS line (Example of screen display)
D. Check of signal line by sync signal detection
SELF CHECK
E. Indication of part code of microcom.(QA01)
NO. 239XXXX Part coce of QA01 E
F. Number of operation of power protection circuit F
POWER: 000000 Number of operation of
power protection circuit
BUS LINE: OK Short check of bus line B
BUS CONT: OK Communication check of C

busline
BLOCK: UV V1 V2 D
QV01, QV01S
3. EXECUTING SELF DIAGNOSIS FUNCTION [CAUTION]

(1) When executing block diagnosis, select first the desired input signal source (U/V BS VIDEO1,2,3) screen, and then enter
the self diagnosis mode.
(2) When diagnosing other input modes, repeat the diagnosis routines after source selection. The test signals and/or routines
apply only to the video source selected at the time of testing.
(PROCEDURE)
(1) Place the unit in the service mode.
(2) Press the “9” key on the remote control will display the self diagnosis results on screen.
With each key press the mode will change as shown below.
SERVICE mode SELF DIAGNOSIS mode
(3) To exit from the service mode, turn the power off via the front panel or remote control.
3-10
4. UNDERSTANDING THE RESULTS OF THE SELF DIAGNOSIS FUNCTION
See Fig. 3-7 .
(Example of screen display)

SELF CHECK
NO. 239XXXX Part coce of QA01 E
POWER: 000000 Number of operation of F
power protection circuit
BUS LINE: OK Short check of bus line B
BUS CONT: OK Communication check of C

busline
BLOCK: UV V1 V2 D
QV01, QV01S
Fig. 3-7
Table. 3-5
Item Contents Instruction of results
BUS LINE Detection of bus line short Indication of OK for normal result, NG for abnormal
Indication of OK for normal result

Indication of failure place in abnormality
(Failure place to be indicated)
QA02 NG, H001 NG, Q501 NG, H002 NG
QV01 NG, Q302 NG, QY02 NG, HY01 NG
QD04 NG, QM01 NG, Q701 NG
BUS CONT Communication state of bus line Note 1. The indication of failure place is only one
placet though failure places are plural. When
repair of a failure place finishes, the next
failure place is indicated. (The order of
priority of indication is left side.)
BLOCK: UV1 The sync signal part in each video signal *Indication by color
UV2 supplied from each block is detected. • Normal block :Green
V1 Then by checking the existence or non of • Non diagnosis block :Cyan
V2 sync part, the result of self diagnosis is
displayed on screen. Besides, when “9” key
on remote unit is pressed, diagnosis
operation is first executed once.
3-11
<Clearing the self diagnosis results>
While the error count state is displayed upon the screen, press the “CHANNEL DOWN” button on TV set
pressing “DISPLAY” button on remote unit.
[CAUTION] White
All ways observe the following caution, when in the Yellow
service mode screen. Cyan
Green
• Do not press the “CHANNEL UP” button. This will cause Magenta
initialization of the memory IC. (Replacement of memory Red
IC is required. Blue
• Do not initialize self diagnosis result. This will change user
( COLOR BAR SIGNAL)
adjusting contents to factory setting value. ( Adjustment is
Color elements are positioned in sequence of high brightness.
required.)
<Troubleshooting method utilizing internal test signal> (VIDEO INPUT 1 terminal should be open.)
(1) With service mode screen, press VIDEO button on remote unit. If inner video signal can be received, QV01 and after are
normal.
(2) With service mode screen, press “8” button on remote unit. If sound of 1kHz can be heard, QV01 and after are normal.
* By utilizing signal of VIDEO input terminal, each circuit can be checked. (Composite video signal, audio signal)
3-12
13. TROUBLE SHOOTING CHARTS
(1) TV DOES NOT TURNED ON
TV does not turned on.
YES
Relay sound
NO
NG
Check of voltage at pin 7 of QA01
(DC 5V).
OK
Check power circuit.
NG
8MHz oscillation waveform
at pin 32 of QA01.
OK
Check OSC circuit.
Replace QA01.
NG
Pulse output at pins 37 and 38 of QA01.
OK
NG
Voltage check at pin 32 of QA01
(DC 5V)
OK
Check reset circuit.
Check relay driving circuit. Replace QA01.
3-13
(2) NO ACCEPTION OF KEY-IN
Key on TV
Voltage change at pins 17, 18 of NG

QA01 (5V to 0V).
OK
Check key-in circuit.
Replace QA01.
Remote unit key
Pulse input at pin 35 of QA01, NG

When remote unit key is pressed.
OK
Replace QA01 Check tuner power circuit.
(3) NO PICTURE (SNOW NOISE)
No picture
NG
Voltage at pins of +5V, and 32V.
OK
Check H001. Check tuner power circuit.
3-14
(4) MEMORY CIRCUIT CHECK
Memory circuit check
NG
Voltage check at pin 8 of QA02 (5V).
OK Check power circuit.
NG
Pulse input at pins 5 and 6 of QA02
in memorizing operation.
OK
Check QA01.
Replace QA02.
Note: Use replacement parts for QA02.
Adjust items of TV set adjustment.
(5) NO INDICATION ON SCREEN
No indication on screen.
NG
Check of character signal at pin 23
of QA01. (5VP-P)
OK
Check V/C/D circuit.
Input of OSC waveform at pin 29 of QA01 NG

with indication key pressed.
OK
Check OSC circuit.
Check of sync signal at pins 26, 27 of QA01.
OK
Check sync circuit.
Replace QA01.
3-15
NOTES
3-16
SECTION IV
AUDIO OUTPUT CIRCUIT
4-1
1. OUTLINE
The main amplifiers and woofer output amplifiers use a

bipolar IC (TA8256H) and develop output powers of
10Wx2 + 13W.
2. THEORY OF OPERATION
2-1. Operation of TA8256H

The TA8256H is a modified version of the TA8128AH
which was used in the N4SS chassis as an audio ouput IC.
In the TA8256H, one channel has been added and up to 3
channels can be used. Performance for each channel is the
same as that of the TA8218H. Fig. 4-1 shows a block
diagram of the IC.
Vcc
25.5V
47m F 47m F
6 9
1m F RIPPLE FILTER Vcc
4k
L 4 OUTPUT-2 470m F
L AMP-2 8
30k
2.2W
RL (L)
350W 0.12m F
3 PRE POW 10
GND GND
0.12m F
350W RL (R)
2.2W
(R)
1m F AMP-3 12
OUTPUT-3 470m F
R 2
R 4k
30k 5 (mute)
MUTING
(mute Tc)
7
30k
1m F 4k
W 1 OUTPUT-3 1000m F
W AMP-1 11
350W
(S) or (W) 2.2W
RL (W)
0.12m F
20kW
Fig. 4-1
4-2
SECTION V
DSP CIRCUIT
5-1
1. ORIGINS OF DOLBY SURROUND into left, center equally into left and right, and right into right-
playing a Dolby Stereo soundtrack over two speakers
Dolby Stereo movies and Dolby Surround video and television reproduces the entire encoded soundtrack. There is but one
programs include an additional sonic dimension over exception: the surround signal, though audible, is not
conventional stereo productions. They are made using a Dolby reproduced in its proper spatial perspective. When the first
MP (Motion Picture) Matrix encoder, which combines four home decoder was developed in 1982, its goal was to restore
channels of audio into a standard two-channel format, suitable this lone missing dimension.
for recording or transmitting the same as regular stereo programs. Before we discuss decoders, it is necessary to see how the MP
To recapture the dimensional properties brought by the Matrix encoder works. Referring to the conceptual diagram
additional channels, a Dolby Surround decoder is used. In the in Fig. 5-1, the encoder accepts four separate input signals;
theatre, a professional decoder is part of the Dolby Stereo left, center, right, and surround (L, C, R, S), and creates two
cinema processor used to play 35 mm stereo optical prints. final outputs, left-total and right-total (Lt and Rt).
The decoder recovers the left, center, and right signals for
playback over three front speakers, and extracts the surround The L and R inputs go straight to the Lt and Rt outputs without
signal for distribution over an array of speakers wrapped modification, and the C input is divided equally to Lt and Rt
around the sides and back of the theater. (These same with a 3 dB level reduction (to maintain constant acoustic
speakers may also be driven from four of the six discrete power). The S input is also divided equally between Lt and Rt,
tracks on 70 mm Dolby Stereo magnetic prints, but in this but it first undergoes three additional processing steps:
case no decoder is needed.) a. Frequency bandlimiting from 100 Hz to 7 kHz.
Home viewing of movies on video has become extremely b. Encoding with a modified from of Dolby B-type noise
popular, and with the advent of stereo VCR's, stereo television reduction.
and digital video discs, the audio side of the video presentation c. Plus and minus 90-degree phase shifting is applied to
has improved considerably, inviting the use of full-range create a 180-degree phase differential between the
sound reproduction. The ability to deliver high quality audio components feeding Lt and Rt.
in these formats made it easy to bring MP Matrix-encoded It is clear there is no loss of separation between the left and right
soundtracks into the home as well, thus establishing the signals; they remain completely independent. Not so obvious
foundation for Dolby Surround. is that there is also no theoretical loss of separation between the
center and surround signals. Since the surround signal is
2. THE DOLBY MP MATRIX recovered by taking the difference between Lt and Rt, the
identical center channel components in Lt and Rt will exactly
One of the original goals of the MP Matrix was to enable cancel each other in the surround output. Likewise, since the
Dolby Stereo soundtracks to be successfully played in theaters center channel is derived from the sum of Lt and Rt, the equal
equiped for mono or two-channel stereo sound. This allows and opposite surround channel components will cancel each
movies to be distributed in a single optical format, and other in the center output.
furtheremore results in complete compativility with home The ability for this cancellation technique to maintain high
video media without requiring separate soundtrack mixes. separation between center and surround signals requires the
Since the three front channels of the MP Matrix are assembled amplitude and phase characteristics of the two transmission
in virtually the same way as a conventional stereo mix --- left channels to be as close as possible. For instance, if the center
Left + + Lt
+ +
DOLBY NR +90 DEG

Center -3dB Surround -3dB B.P.F
ENCORDER -90 DEG
+ +
Right + + Rt
Fig. 5-1 Conceptual Dolby Stereo/Dolby Surround encoder

5-2
channel components in Lt are not identical to the ones in Rt 4. DSP CIRCUIT
as a result of a channel balance error, center information will
come out of the surround channel in the form of unwanted A surround component (L-R) is extracted from L, R audio
crosstalk. signals coming through the AV SW in the matrix circuit as
shown in Fig. 5-3. The surround component enters the DSP
3. THE DOLBY SURROUND DECODER circuit through the LPF.
The signal is A/D converted, delayed by an arbitrary time of
This leads us to the original Dolby Surround decoder. The 0~100 msec (every 3.2 msec) by digital process and then D/
block diagram in Fig. 5-2 shows how the decoder works. A converted and outputs from the DSP IC. The DSP IC
Except for level and channel balance corrections, the Lt input develops two outputs; (LO) for FRONT (LO) and (RO) for
signal passes unmodified and becomes the left output. The Rt REAR and each output is controlled by the microcomputer
input signal likewise becomes the right output. Lt and Rt also for each surround mode. The output signal (LO) for FRONT
carry the center signal, so it will be heard as a "phantom" is added and subtracted with the input signal in a matrix
image between the left and right speakers, and sounds mixed circuit and output from the front speaker in passing through
anywhere across the stereo soundstage will be presented in the audio processor and main amplifiers.
their proper perspective. The center speaker is thus shown as At the same time, the output signal (RO) for REAR is fed to
optional since it is not needed to reproduce the center signal. the Dolby NR circuit, but switched to "Dolby surround"
mode, and then output from the rear speaker in passing
The L-R stage in the decoder will detect the surround signal through audio processors and rear main amplifiers.
by taking the difference of Lt and Rt, then passing it through In this case, the DSP stands for not only a simple digital
a 7 kHz low-pass filter, a delay line, and complementary surround processor but also a digital surround field processor.
Dolby noise reduction. The surround signal will also be That is, it works to give a simple surround effect but to give
reproduced by the left and right speakers, but it will be heard effect as if the listener can feel reality suitable for the
out-of-phase which will diffuse the image. programs. For example, it aims to give the listeners a reality
Since the heart of the decoding process is a simple L-R matching to each program they are enjoying in their home
difference amplifier, it is referred to generically as a "passive" listening room so that they can obtain reality of big concert
decoder. This is to distinguish it from decoders using active hall or feel as if they are watching a move at a reserved seat
processes to enhance separation which are known as "active" in a movie theater.
decoders.
INPUTS OUTPUTS
L L
Left
Lt R R MASTER
INPUT Right
LEVEL C LEVEL
BALANCE CONTROL Center
CONTROL CONTROL
C
Surround
Rt L+R
Optional passive center signal S
S ANTI- MODIFIED
L-R ALIAS B-TYPE NR
FILTER DECODER
7 kHz
AUDIO LOW PASS
DELAY SET
DELAY FILTER
Fig. 5-2 Passive surround decoder block diagram

5-3
QD02
From QD08 QD01 DSP Q670
A/V SW Input Balance Input Buffer Front Addition Circuit Front amp
12 14 L 5 7 L L+S
L L
IN 10 8 Speaker
R 8 R
R R
R L 10 R-S
9
6 5
1 3 1 L+R
MATRIX 7 3 Sycrone
LPF LPF (Super woofer)
(L-R CIRCUIT) (L-R)
QD01 QD01 QD02
Fig. 5-3 Block diagram of DSP circuit
4 QD03 DSP IC YM7128 B
VC
TO
A/D DIGITAL DELAY Audio

5-4
Processor
(H002)
Buffer
VL
CONT LO 3 1 5
D/A LPF 7 LO
BUS 7
QD04 QD05 QD05
CONVERT
From Micro
computer VR Buffer DQ06
RO 5 7 3
D/A LPF
8
QD06 1 Q640
Dolby NR
Rear Amp
6
9 14 L-R +S
L
12
Speaker
QD07 DQ02 R
As shown in Fig. 5-4, a sound emitted in a sound field can For more detail, this situation can be expressed with the
be classified as a direct sound which directly reaches ears of direct sound, initial reflection sound coming after one time of
a listener, and reflected sound which comes after collision reflection, and trains of reverberation sound in later period as
with a wall as shown by dotted line or comes after several shown in Fig. 5-5.
times of collision as shown by double dotted lines. The The DSP circuit develops these initial reflection sound and
listeners are determining that they are listing in what type of the reverberation sound artificially and add them to the
location by perceiving time difference and volume level original sounds, thereby creating rhe effect that allows the
difference between the direct sound and the reflected sound. listeners in the home listening room to feel as if they are
listening in an original location.
The DSP IC YM7128B has eight separate output taps and
their delay time and the output levels can be specified
separately, so, various sound fields can be selected by varying
the initial reflection sound. Moreover, the IC has an internal
feedback loop which controls the delay time and the output
level in considering the later time reverberation sound.
Direct Sound
Direct Sound
Sound Level Initial Reflection Sound
Initial Reflection
Sound
Reverberation Sound
Reverberation
Sound
Time
Fig. 5-4 Fig. 5-5
5-5
5. DSP (Digital Surround Processor) IC delay input after it is added to the doubler described above.
The output of eight taps T1 to T8 is added after performing
Input signal entered into analog input pin 4 of DSP IC QD03 reduction processing by GL1~GL8, GR1~GR8, and reduction
(YM7128B) is converted to 14 bit digital signal with the processing is performed by the digital attenuator VL or VR,
sampling frequency 23.6 kHz by A/D converter of 14 bit and an analog output is created by D/A converter after
floating system, and enters digital delay circuit through passing through digital filter, comes out from pin 7 or 8.
digital attenuator VM and doubler. The digital attenuated value, delay time and the coefficient of
The digital delay circuit has nine output taps, and the delay FIR type low pass filter are set by writing the data on the
time of each tap can be controlled independently, also each register.
tap position can be switched by T0 to T8 register. This process is performed by loading three data from sub
In a minute, the T0 output passes through the primary FIR microcomputer to microcomputer interface.
(Finite Impulse Response) type low pass filter, and reduction This unit has four modes as surround mode. The setting
processing is performed by VC, then it feed-backed to the values are described in Table 5-1.
Table 5-1 DSP control factor
Mode OFF DOLBY THEATER STADIUM NIGHT CLUB CONCERT UNIT

Control SURROUND HALL HALL
-VM (IN) -•¥ P-0 P0 ¥ P0 P0 P0 dB
VL (LO) -•¥ P0~ -• P0~ -¥• P0~ --¥• P0~ --¥•
VR (RO) P0 P0 P0 P0 P0
VC (Echo) -•¥ -•¥ M-6 M-10 M-8
GL1 P-4 M-2 M-2 P-2
2 M-6 -•¥ P-4 P-10
3 P-12 P-6 P-16
4 P-12 M-10 -•¥
5 -•¥ -•¥
6
7
8
GR1 P0
2 -•¥ P0
3 P-18
4 -•¥
5 P-2 P-6 P-4
6 M-2 M-6 P-8
7 P-8 M-10 P-8
8 P-10 P-12 P-14
T0 (Delay) 0 0 0 100.0 19.4 51.6 msec
1 19.4 12.9 93.6 12.9 71.0
2 0 38.7 100.0 19.4 83.9
3 71.0 100.0 22.6 100.0
4 87.1 0 29.0 0
5 29.0 6.5 64.5
6 45.2 9.7 80.7
7 83.9 25.3 90.4
8 100.0 35.5 100.0
C0 (Filter) 0 0.71875 0.59375 0.875 —
1 0.28125 0.40625 0.125 —
5-6
XD01
CD27 RD32 CD29

CD28
D01
QD03 RD33
11 12 16
XO XI /IC Vss
C1 1
CV REFERENCE VC TIMING GENERATION LD01

D
5 VOLTAGE AVDD
CD22 GENERATION 2 +B (5V)
C2
RD26
VM TO
CD21 CD20
From AIN A/D DIGITAL DELAY
Input LPF 4
CONVERTER T8 T7 T6 T5 T4 T3 T2 T1
CD15
GL1
CH GL2
3
GL3
CD23
Fig. 5-6
GL4 VL LO
D/A
5-7
/TI GL5 2fs 7 To LPF Output

CONVERTER (For FRONT ch)
6 GL6
DC26
GL7
GL8
GL1
GL2
GL3
GL4 VR RO
D/A To LPF Output
GL5 2fs 8
CONVERTER (For REAR ch)
MICROCOMPUTER GL6 DC25
INTERFACE
GL7
DIN AO SCI GL8

VSS AVSS
VDD
15 14 13 10 9
From Bus convert

(ICD04)
NOTES
5-8
SECTION VI
A/V SWITCHING CIRCUIT
6-1
1. OUTLINE
The A/V switching circuit selects the desired video and

audio signals from the various inputs. It is controlled by the
microcomputer through IIC bus.
2. IN/OUT TERMINALS
TUNER INPUT U/V Tuner (Main)
U/V Tuner (PIP)
EXTERNAL INPUT VIDEO 1 With S-terminal
VIDEO 2
VIDEO 3 (Front) With S-terminal
OUTPUT VIDEO OUTPUT (V, L, R)
AUDIO ON SUB-PICTURE
3. CIRCUIT OPERATION
This circuit consists of A/V SW IC; TA1218N (QV01), and

selects signals from U/V tuner (Main), U/V tuner (PIP),
E1, E2 and E3.
3-1. Composite Video Signal

The selected video signal is output to pin 38 of QV01, and
separated by comb filter into Y an C. The resulted signal
is input to pins 30 and 32 of QV01, and is output to pins 36
and 34 to be supplied to Q501 (V/C/D).
Video signal for PIP is output to pin 42 of QV01, and is
supplied to PIP unit (ZY01).
3-2. S-Video Signal

When a cable is connected to S-VIDEO terminal, inner
switch of S-VIDEO terminal is shorted to ground to turn off
the transistor (QV05 for VIDEO1 input) for S-VIDEO
terminal detection. Then chroma input terminal (Pin 14 for
VIDEO1 input) of QV01 turns on.
6-2
AV SW CIRCUIT
H002 HY01
IF/MTS/A. PRO PIP TUNER/IF
A V V A
EQ DSP
QV01 TA1218N
L/R in
18 C in
QA01
17 R in SYNC OUT 26 SYNC in
VIDEO 3
16 S in
15 L in PIP TV in 28
14 C in PIP L in 29 COMB
FILTER
13 R in Y in 30 Y out
VIDEO 1
12 S in PIP R in 31 V in
11 L in C in 32 C out
10 V in
9 R in C out 34 C in
VIDEO 2
R out 35 Q501
8 L in
7 V in Y out 36 Y in
6 R in L out 37
5 L in V out 38
2 PIP R out
PIP AUDIO PIP
OUT JACK
1 PIP L out PIP V out 42 V in
TP48E90 ONLY
A/V OUT
JACK
Fig. 6-1
6-3
NOTES
6-4
SECTION VII
VIDEO PROCESSING CIRCUIT
7-1
1. OUTLINE by RGB matrix. Next the signal is superimposed with
OSD signal to be output to pins 41, 42 and 43, and is
This circuit converts and amplifies video signal (Luminance supplied to CRT Drive circuit.
and chroma signals) separated into Y/C, to original color (4) The signal for Scan Modulation is processed with
signal, and is supplied to CRT Drive circuit. differential in Q501 to be output to pin 48 Besides, at
terminal for adjustment TP501, luminance and chroma
2. SIGNAL FLOW signals are automatically output according to the
selected items of service mode.
Signal flow chart is shown in figure 6-1 Block diagram.
(1) Luminance signal is input to pin 15 of Q501, and enters 3. CIRCUIT OPERATION
into delayline inside Q501 to be output to pin 4.
(2) Chroma signal is input to pin 13, and I/Q signal which All processing operation of video signal are done inside
is demodulated in color, is output to pins 5 and 6, and Q501. The outline of Q501 (TA1222N) is explained in the
next supplied to pins 51 and 52. next section. Here, major terminals excepting input/output
(3) The signal is processed on luminance and chroma terminals of Q501 are described.
signals, and is converted to original color signal (R,G,B)
Table 7-1
Pin No. Name Description
Pin 1 CW output 3.58MHz synchronized with burst is output. This is used for clock of comb filter.
Pin 10 Xtal 1 Terminal for 3.58MHz OSC crystal
Pin 11 APC filter Terminal for phase detection of color sync (OSC frequency control)
Pin 18 SYNC Sync-separated sync signal is output. It is used for detecting no signal in
microcomputer.
Pin 30 HD Terminal for output of HD pulse syncronized with horizontal sync., and for input
of black expading mask pulse. It is used for timing pulse of OSD, C.C (Closed
Caption) in microcomputer.
Pin 32 Ys OSD change-over pulse input: Ys of OSD is input.
Pin 45 ABL Terminal for ABL control input
Pin 47 Ym Input of pulse for half tone control: It is supplied from microcomputer.
Pin 49 APL DET Detecting average level of video signal for correction of DC transmission
Pin 50 BLACK DET Detecting black area of video signal for black expading circuit
Pin 54 COL Terminal for peak-hold of color limiter
Pin 55 DAC1 Test point (TP501): Functioning test point in service mode
7-2
NOTES
7-4
SECTION VIII
V/C/D/IC
8-1
1. OUTLINE
This IC enables more precise picture setting than that of former IC (TA8845N) by means of large scale employment
of IIC bus, and reduces many peripheral components by containing filters inside.
The main features (comparing TA8845) are as follows.
2. LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE

CONTROLS
Soft method of picture making

Table 8-1
Former/TA8845N TA1222N
* Black expanding start point External constant BUS control
* DC transmission correction quantity point External constant BUS control
* Black level correction quantity External constant BUS control
* Each ABCL characteristic External constant BUS control
3. EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE
Employment of automatic adjustment circuit by Fsc to absorb deviation / Employment of deviation aborbing method by high
S/N filter and mask triming using fixed CR
Table 8-2
* Y-DL Apa-con DL inside Inside
* Chroma TO/BPF External Inside
* Velocity modulation processing circuit External Inside
* Fsc trap for chroma demodulation output External Inside
4. EMPLOYMENT OF CONTAINING EACH FILTER (FOR S/H) INSIDE
Circuit operation by extremely low current / Employment of leak current cancel circuit Employment of detection circuit
which does not suffer from influence of stray capacity
Table 8-3
* Chroma ACC / killer filter External Inside
* Y / color difference clamp filter External Inside
* Filter for filter automatic adjustment External Inside
* AFC 2 filter External Inside
8-2
5. LOW COST OF IC
* Involving peripheral components inside ——> Down sizing of chip ——> Newly employment (NPN Tr area ratio to former
: -25%) of miniature process (PLAS-1 S process)
* Involving peripheral components inside——>Increasing of power consumption——>2 power supply system (5V / 9V
used)
* Involving peripheral components inside ——> Reducing of number of elements ——> Employment of new circuit
(1) Reducing of gate (change of preset method) of register for IIC decoder
(2) Reducing of DAC elements (employment of rudder type DAC + temperature compensation circuit)
(3) Deletion of chroma CW, ACC (employment of 90 degree shift phase circuit with automatic adjustment)
8-3
VCD BLOCK DIAGRAM (TA1222N)
CORRECTION
BLK/AFC IN
BENDING
SYNC IN
3'5" VCD
Daf vCC
AFC1
H. out
17 20 21 25 24 19 22 23
GND (DEF) VCC (DEF)
H. V. PHASE DET PHASE DET H. PHASE H. DUTY
32 FM VCO H. BLK H. DRIVE
SYNC SEP <APC-1> <APC-2> SHIFT SW
H. H. Y.
V. Sep 16 V. SEP Y.P OUT 31 VER OUT
COUNT DOWN PARABOLA COUNT DOWN
V. SYNC
18 SYNC OUT
SYNC SEP OUT
27 SDA
SYNC CHIP DELAY D/A I2C BUS
Y IN 15 FDC TRAP SW REGISTER 26 GND
CLAMP LINE CONVERTER DECODER
19 SCL
BPF DELAY LINE DELAY LINE SW 4 Y1 OUT
CHROMA IN 13 SW TOK
29 GND
GND
GAMMA BLACK BLACK
GND 34 ACC AMP TOF SW Y. CLAMP 53 Y2 OUT
CORRECTION LEVEL COR. STRETON
VCC
9V 12
(88) SUB B.C BLACK WHITE BLACK PEAK
ACC DET A.P.L DET 30
COLOR RESTORE PEAK DET PEAK DET HOLD
39 APL DET
P/N IDENT CHROMA SHARPNESS
APC FILTER 11 APC DET HPF TM AMP VM MUTE 28 VM OUT
BET BLK S DELAY LINE
R
T
X tal-1 CHROMA CW CHROMA SHARPNESS
10 T. NR AMP SUB CONT UNI COLOR
(3.58MHz) VCO MATRIX DEMOD. CONTROL
VCC
26
X tal-2 (PAL) 9 (98)
FILTER LPH 5 Q OUT
WPS HALF TONE CLAMP
AUTO ADJ FSC TRAP
X tal-3 (PAL) 8 6 Y OUT
I IN 51 33 B IN
IQ/UV FRESH IQ UV RGB

Q IN 52 SW CLAMP CONTRAST 34 G IN
CLAMP COLOR CONVERT BRIGHT
35 R IN
UNI COLOR DELAY YS SW
COLOR TINF 36 OSD Ys IN
TIME
37 OSD B IN
AXIS HALF
CLAMP CLAMP OSD AMP 38 OSD G IN
G-Y MATRIX TONE
39 OSD R IN
COLOR COLOR
COLOR LIMITER 54 CDE YS SW 22 Ys IN
PEAK DET GAMMA
DAC 2 55
HI BRIGHT RGB PEAK
SW ABCL AMP 25 ABL IN
COLOR MATRIX ACL DET
DAC 2 56
SECAM CONTROL SECAM COLOR

3 DAC 1/2 DRIVE CLAMP BLK
(FOR SECAM) CONTROL SYS IDENT
1H DL S.C.P HD OUT POWER OFF IN

CW OUT CUT OFF RGB OUT
CONTROL OUT EXT EFP IN YM SW
VCC (98) GND
1 7 2 30 47 46 44 41 42 43
YM IN
B OUT
G OUT
R OUT
EXPAND MATRIX
1H DL CONTROL
COLOR IDENT.
(SAND CASTLE)
HD OUT/BLACK
CW OUT/
(FOR PAL)
SCP OUT
8-4
SECTION IX
PIP MODULE
9-1
PMUS 02H (SN:23148232)
B-Y OFFSET
R-Y OFFSET
TINT
RY54 RY55 RY50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PIN I/O NAME PIN I/O NAME

4V
1 0 YS 9 I 5V
0V
2 - NC 10 I GND 350m S
4.2V
3 I GND 11 I VD 0V
4.8V
4 O R OUT 4.1V 12 I HD 1m S
10m S 4.2V
4.8V 3.0V 6V
5 O G OUT 4.1V 13 I/O SCL Or
-0.9V 0V
4.8V
6 O B OUT 14 I/O SDA
4.1V B CHASSIS C CHASSIS
7 I GND 15 - NC
4.8V
8 I PIP VIDEO 2.8V
9-2
PMUS02H
<BLOCK DIAGRAM OF PIP MODULE>
RY55 RY54
PIP VIDEO R OUT

8 36 VIDEO B-Y 14 51 BI BO 67 19 B-Y R OUT 23 4
IN OUT IN G OUT
R-Y 13 49 RI RO 65 18 R-Y G OUT 24 5
OUT IN B OUT
Y-OUT 12 SLICE 47 YI YO 64 16 YIN B OUT 25 6
9-3
WAVE FORM
HD 10 MODULATION 78 HDCN HDPN 18
76 VDCN VDPN 16
VD 11
QY03 QY01
QY01
TC9083F m PC1832GT
m PC 1832GT
(PIP PROCESSOR) (PIP V/C/D)
(PIP V/C/D)
VD
11
HD
12
NOTES
9-4
SECTION X
SYNC SEPARATION, H-AFC,
H-OSCILLATOR CIRCUITS
10-1
1. SYNC SEPARATION CIRCUIT
The sync separation circuit separates a sync signal from a

video signal and feeds it to an H and V deflection circuits.
The separation circuit consists of an amplitude separation (H
and V sync separation circuit) and a frequency separation
circuit (V sync separation circuit) which performs the
separation by using a frequency difference between H and V.
In the N5SS chassis, all these sync separation circuits are
contained in a V/C/D IC (TA1222N).
Fig. 10-1 shows a block diagram of the sync separation
circuit.
Sync H sync siganl

input
Q501
Composite H. V SYNC
video 17 SEPARATION
signal CIRCUIT
V SYNC WAVEFORM
V sync signal
SEPARATION SHAPEING
(Reset pulse)
CIRCUIT CIRCUIT
Fig. 10-1 Sync separation circuit block diagram
1-1. Theory of Operation

1-1-1. Auto slicer type synchronous separation circuit
When a synchronizing signal is separated, synchronous
separation is made from the beginning with constant voltage
in the conventional synchronous separation circuit. The auto
slider type circuit employed in this time makes synchronous
separation at a constant rate against the synchronizing signal
amplitude. (See Fig. 10-2)
In this method, even if an abnormal signal with small
amplitude is applied, stable synchronizing performance can
be obtained without separating pedestal.
Pedestal Level
D
B
B
A
Sync Separation Level A:B=C:D
b: Small Amplitude Sync. Signal
a: Corect Sync. Signal
Fig. 10-2 Synchronous separation by auto slider system
10-2
1-1-2. V Sync Separation Circuit First, phases of a 32 fH counted-down signal and a H sync
To separate a V sync signal from the composite sync signal signal contained in broadcasting signal are compared in the
consisting of V and H sync signals mixed, two stages of AFCI loop and the loop develops an H pulse signal for the
integration circuits are provided inside the IC. The circuit AFCII loop. That is, when a phase deference 01 exists in
consists of a differential circuit and a Miller integration comparison of the phase of fH signal developed by counting
circuit, and has following functions. down the 32 fH signal and the phase of H sync signal of the
(1) Removes H sync signal component. broadcasting signal, an error signal corresponding to the
(2) Maintain stable V sync performance for a tape recorded phase different is detected and a correction voltage V1
with a copy guard. corresponding to the error output is generated. With this
(3) Stabilized V sync performance under special field correction voltage, the 32 fH oscillator circuit is controlled.
conditions (poor field, ghost, sync depressed, adjacent The correction (control) voltage for the oscillator varies in
channel best). direction of positive or negative corresponding to phase
The V sync signal separated in this stage is processed in a lead or lag of the fH pulse (developed by counting down)
waveform shape circuit and then used as a reset pulse in the from the H sync signal. As the H oscillator (32 x fH), a
V division circuit as stated later. voltage controlled oscillator (VCO), oscillation frequency
and phase of which can be controlled with the control
2. H AFC (Automatic Frequency Control) voltage is used.
CIRCUIT Next, an H pulse signal is created from the fH signal counted
down, and the pulse is used instead of the H sync signal in
A sync system which performs synchronization with each the AFCII circuit. The AFCII circuit differs in the loop of
waveform of the sync signal as performed in a sync system the count down circuit and H output circuit.
in the V circuit is called a direct type sync system. However, The AFCII circuit compares phase of a H BLK pulse created
if the synchronization for the H oscillator is carried out with by waveform shaping a AFC pulse from the FBT and a phase
this method, the H oscillator synchronizes with external of the H pulse, and detects an error component corresponding
noises and the H synchronization will be disturbed. To to the phase difference 02 (if exist) and develops a
prevent this, an output of the H oscillator is compared with correction voltage V2 corresponding to the error, thereby
a reference H sync signal to detect deviations of frequency controlling the phase of Q501 H out.
and phase. The H oscillator is automatically controlled with The H output control voltage varies in a positive or negative
the detected output averaged. This circuit is called an AFC direction corresponding to the phase lead or lag of the H
circuit. BLK pulse from that of the H pulse. The phase of H out is
In the N4SS chassis, a conventional AFC circuit is not varied with the control voltage to make synchronization
employed but a new double AFC circuit built-in the TA1222N with the H pulse phase.
is used. Fig. 10-3 shows the AFC circuit and the block The purpose of the double AFC circuit employed this time
diagram of the circuit.
SYNC SEPARATION PHASE DETECTION 32 x fH

CIRCUIT CIRCUIT VCO
AFC II LOOP
H DRIVE
H COUNT DOWN PHASE DETECTION
H OUTPUT
(DIVIDING) CIRCUIT
CIRCUIT
AFC I LOOP
FBT PULSE
(AFC PULSE)
Fig. 10-3 H AFC circuit block diagram
10-3
is to improve horizontal jitter under signal reception in a
poor electrical field. The jitter in the poor field strength and
distortion due to phase difference are incompatible. That
is,to improve the jitter under poor field strength, response
speed must be slowed by lowering the AFC sensitivity. On H Vcc
the other hand, to improve distortion due to the phase
difference, the response must be increased by increasing the
AFC sensitivity.
In a conventional AFC circuit, setting of the sensitivity is
carried out at one part only, so an compromise point for both
2VP-P
characteristics must be found. However, with the double SYNC
AFC circuit employed this time, for the jitter the AFCI loop IN
17 20 21
works best with decreasing the sensitivity and for the phase
distortion the AFCII loop works with increasing the SYNC
H AFC I 32 x fH
SEPARATION
sensitivity. CIRCUIT
CIRCUIT VCO
3. H OSCILLATOR CIRCUIT
H COUNT
DOWN
3-1. Outline
A 503 kHz (32 x fH) voltage controlled type oscillator with
a ceramic oscillation element is used to generate a clock H AFC II
CIRCUIT
pulse and the clock is counted down, thereby obviating the
need of adjustments for both the H and V deflection process TA1222N
circuit.

(1) The H sync signal used as a reference signal enters
from the sync separation circuit to the AFCI circuit. At Fig. 10-4
the same time, the fH pulse created by counting down
the 32 x fH pulse generated in the ceramic oscillator
enters the H AFCI circuit. Phase difference between
these two signals enters an integration circuit (low pas
10-4
filter) connected to pin 4 and converted into a DC
voltage (AFC voltage).
(2) The AFC voltage controls frequency (32 x fH) of the
oscillator (VCO). High
OSC frequency (Hz)

Fig. 10-5 shows the control characteristics of the VCO.
(3) The H output is obtained by dividing the 32 x fH (503
kHz) of the oscillator with flip-flops. Fig. 10-6 shows
the block diagram of this count down circuit.
(4) The V output is created by dividing the 32 x fH
oscillator output into 1/8, and then by counting the 4 x Low
fH pulse with a vertical counter which is reset with a
V reset pulse (V sync output signal stated under sync
separation).
Low High
(5) That is, the V output is not created by simply counting AFC voltage (V)
down the H by performing V synchronization with a V
reset pulse entering within a window provided for V
synchronization --- called direct type sync system,
Fig. 10-5
thus, the circuit can work for non standard signals.
32fH 4fH fH
32 x fH VCO X 1/8 X 1/4 H OUTPUT
V sync Reset
signal V WAVEFORM pulse V
SHAPE V OUTPUT
COUNTER
CIRCUIT
Fig. 10-6 Block diagram of H, V count down circuits
10-5
NOTES
10-6
SECTION XI
VERTICAL OUTPUT CIRCUIT
11-1
1. OUTLINE
As can be seen from the block diagram, the sync circuit and
the V trigger circuit are contained in Q501 (TA1222N), and
the sawtooth generation circuit and amplifier (V drive circuit)
contained in Q302 (TA8859AP). The output circuit and
pump-up circuit circuits are included in Q301 (TA8427K).
DPS CIRCUIT
Q501 TA1222N Q302 TA8859AP Q301 TA8427K
SAM TOOTH
SYNC WAVE GAIN PUMP-UP
V. TRIGGER
CIRCUIT CIRCUIT CIRCUIT
AMP OUTPUT DEFLECTION

YOKE
LOGIC
Microcomputer
CIRCUIT
Fig. 11-1 Block diagram of V deflection circuit

The purpose of the V output circuit is to provide a sawtooth
wave signal with good linearity in V period to the deflection
yoke.
When a switch S is opened, an electric charge charged up to
a reference voltage VP discharges in an constant current
rate, and a reference sawtooth voltage generates at point a.
This voltage is applied to (+) input (non-inverted input) of
an differential amplifier, A. As the amplification factor of
A is sufficiently high, deflection current flows so that the
voltage V2 at point becomes equal to the voltage at point
.
Vp S: Switch
Differential
amplifier
L
a A
C2
c
R1 C2 R2 V2
V1
R3
Fig. 11-2
11-2
2. V OUTPUT CIRCUIT
2-1. Actual Circuit
D309
C322 +9V
R308 C308
D308
+35V D301
15 3 C313
R329 6
7
R303
3
FEEDBACK
4 Q301
Q501 14 Q302 6 L301 R336
C321 2
31 C307
1 5
R320 R307 L462+L463+L464
R301
13 8 R306
C309 C311
C314 C306
R313
R330
C305 +27V
C319 R304 R305
Fig. 11- 3
2-2. Sawtooth Waveform Generation

2-2-1. Circuit Operation
The sawtooth waveform generation circuit consists of as
shown in Fig. 11-4. When a trigger pulse enters pin 13, it is
differentiated in the waveform shape circuit and only the
falling part is detected by the trigger detection circuit, to the
waveform generation circuit is not susceptible to variations
of input pulse width.
The pulse generation circuit also works to fix the V ramp
voltage at a reference voltage when the trigger pulse enters,
so it can prevent the sawtooth wave start voltage from
variations by horizontal components, thus improving
interlacing characteristics.
WAVEFORM TRIGGER PULSE

13 V. RAMP AGC
5Vp SHAPE DET. GAIN
DC=0V Q302
14 15 16
+
R329 C321 C322 C323
Fig. 11-4
11-3
2-3. V Output
and supplies a sawtooth waveform current to a deflection
2-3-1. Circuit Operation yoke. Q3 turns on for first half of the scanning period
The V output circuit consists of a V driver circuit Q302, and allows a positive current to flow into the deflection
Pump-up circuit and output circuit Q301, and external yoke (Q3 DY C306 R305 GND), and Q4 turns
circuit components. on for last half of the scanning period and allows a
(1) Q2 amplifies its input fed from pin 4 of Q301, Q3, Q4 negative current to flow into the deflection yoke
output stage connected in a SEPP amplifies the current (R305 C306 DY Q4). These operations are
shown in Fig. 11-5.
+35V
D301 C308 50V
D308 V3
27V
Q301
6 3
GND
D309 R308 V7
Q3
7 27V
GND
BIAS V2
CIRCUIT
2 50V
Q2
4 Q4 DY
+
C306 GND
R305 Q3 ON
GND
1
Q4 ON
Fig. 11-5 V output circuit
(2) In Fig. 11-6 (a), the power Vcc is expressed as a fixed

level, and the positive and negative current flowing
into the deflection yoke is a current (d) = current (b) +
(c) in Fig. 11-6, and the emitter voltage of Q3 and Q4
is expressed as (e).
(3) Q3 collector loss is i1 x Vce1 and the value is equal to
multiplication of Fig. 11-6 (b) and slanted section of
Fig. 11-6 (e), and Q4 collector loss is equal to
multiplication of Fig. 11-6 (c) and dotted section of
Fig. 11-6 (e).
Power Vcc
GND (b) Q3 Collector current i1
Q3
GND (c) Q4 Collector current i2
i1 Vce 1
Q4
GND (d) Deflection yoke current i1+i2
Q2
i2
Vp
Vcc (e)
1/2 Vcc
GND
(a) Basic circuit
Fig. 11-6 Output stage operation waveform
11-4
basic operation is shown in Fig. 11-8.
(4) To decrease the collector loss of Q3, the power supply (6) Since pin 7 of a transistor switch inside Q301 is
voltage is decreased during scanning period as shown connected to the ground for the scanning period, the
in Fig. 11-7, and VCE1 decreases and the collector loss power supply (pin 3) of the output stage shows a
of Q3 also decreases. voltage of (VCC-VF), and C308 is charged up to a
Q3 Collector loss decreases voltage of (VCC-VF--VR) for this period.
by amount of this area (7) First half of flyback period
Power supply Current flows into L462 D1 C308 D308 VCC
for flyback period (Vp) (+35V) GND R305 C306 L462+L463+L464
Power supply in this order, and the voltage across these is:
for scanning period
(Vcc)
VP=VCC+VF+(VCC-VF-VR)+VF about 50V is
applied to pin 3. In this case, D301 is cut off.
(8) Last half of flyback period
Scanning period Current flows into VCC switch D309 C308
Q301(pin3) Q3 L462+L463+L464 C306 R305
in this order, and a voltage of VP=VCC-VCE (sat)-
Flyback period VF+(VCC-VF-VR)-VCE (sat), about 40V is applied
to pin 3.
(9) In this way, a power supply voltage of about 27V is
Fig. 11-7 Output stage power supply voltage applied to the output stage for the scanning period and
about 50V for flyback period.
(5) In this way, the circuit which switches power supply

circuit during scanning period and flyback period is
called a pump-up circuit. The purpose of the pump-up
circuit is to return the deflection yoke current rapidly
for a short period (within the flyback period) by
applying a high voltage for the flyback period. The
D301 C308 D301 C308
D308 D308
Q301 Q301
6 3 6 3
D309 R308 D309 R308
Switch Switch VR
Q3 7 Q3 7
D1 D1
First half
L462+L463+L464 L462+L463+L464
2 2
Q4 + Q4 +
C306 C306
R305 R305
Last half
(a) Scanning period (b) Flyback period
Fig. 11-8
11-5
2-4. V Linearity Characteristic Correction
2-4-1. S-character Correction

(Up-and Down-ward Extension Correction)
A parabola component developed across C306 is integrated
by R306 and C305, and the voltage is applied to pin 6 of
Q302 to perform S-character correction.
2-4-2. Up-and Down-ward Linearity Balance

A voltage developed at pin 2 of Q301 is divided with
resistors R307 and R303, and the voltage is applied to pin
6 of Q301 to improve the linearity balance characteristic.
Moreover, the S-character correction, up- and down-ward
balance correction, and M-character correction are also
performed through the bus control.
11-6
3. PROTECTION CIRCUIT FOR V
DEFLECTION STOP
Q301
2
DPC CIRCUIT 12V 9V
D350
L462+L463+L464
VERTICAL DEFLECTION COILS R352 R354
C306 Q350 BLANKING

C350 Q351 CIRCUIT
V-NF D354
R305 R350 Q353

0.82 D353
V-STOP
Fig. 11-9
When the deflection current is not supplied to the deflection

coils, one horizontal line appears on the screen. If this
Volttage Across
condition is not continued for a long time, no trouble will R305
occur in a conventional TV. But in the projection TV, all the
electron beams are directly concentrated at the fluorescent
screen because of no shadow mask used, and burns out the
screen instantly.
To prevent this, the stop of the V deflection is detected when Q350 BASE Q340 VBE
the horizontal one line occurs, and the video signals are
blanked out so that the electron beams are not emitted.
When the V deflection circuit is operating normally, a
12V-VBE (Q341)
sawtooth wave voltage is obtained across (R305), so Q350
repeats on-off operation in cycle of V sync. In this case, the
Q351 Collector
collector voltage of Q35 is set to develop less than (12V-VBE
(Q351)) with R352 and C350 as shown in Fig. 4-8.
Accordingly, Q351 and Q353 are continuously turned on. As
a result, diode D354 is turned off, giving no influence on the
blanking operation. Fig. 11-10
Next, when the V deflection stops, the voltage across (R305)
does not develop, so Q350 turns off, and both the Q351 and
Q353 are turned off. Then, the picture blanking terminal pin
13 of ICA05 is set to high through R354 and D354 connected
to 90V power line, BLANKING CIRCUIT ON thus cutting
off the projection tubes.
11-7
3-1. +35V Over Current Protection Circuit
The over current protection circuit cuts off the power supply
relay when it detects abnormal current increased in the +35V
power line due to failure of the vertical deflection circuit.
3-1-1. Theory of operation

Fig. 11-11 shows the circuit diagram of the over current
protection circuit. When the load current of the +35V line
increases, the voltage across a resistor of T370 will also
increase. When the voltage increases across R370. and the
voltage developed across R371 becomes higher than the Vbs
of Q370, Q370 turns on and a voltage develops across R374
due to the collector current flowing. When this voltage
increases to a value higher than about 13V, Z801 operates,
thus cutting off the power relay. When the circuit operates,
a power LED provided will turn on and off in red.
C303
R370 R327
+35V FBT
pin 6
D302
R372 C310
R371
C370
D421
UZ22BSD
Q370
2SA933SQ
R373 D370
UZ11BSB
To pin 14 (GATE)
R375 of Z801
C371
R374
Fig. 11-11
11-8
SECTION XII
HORIZONTAL DEFLECTION CIRCUIT
12-1
1. OUTLINE
The H deflection circuit works to deflect a beam from left to

right by flowing a sawtooth waveform of 15.734 kHz into the
DY H deflection coil.
2. HORIZONTAL DRIVE CIRCUIT
The H drive circuit works to start the H output circuit by

applying HVCC (Q501 DEF power source) to pin 22 of Q501
(TA1222N) and a bias to the H drive transistor Q402 at the
main power on.

(1) When the power switch is on, the main power supply of
125V starts to rise. At the same time, AF power supply
25V also rises.
(2) With 25V line risen, Q430 base voltage which is created
by dividing the audio power with R433 and D430 also
rises. Then, the transistor Q430 turns on and the HVCC
is applied from the audio power line through R432 and
D431 to pin 22 of Q501.
R432 Q430 D431
Q501
R433
D430 BB81
81 81 22 H Vcc
BB80 L400
SIGNAL C431 C430
Fig. 12-1 H drive circuit block diagram
12-2
3. BASIC OPERATION OF HORIZONTAL
DRIVE
A sufficient current must flow into base of the horizontal turn off the transistor, a sufficiently high, reverse voltage
output transistor to rapidly make it into a saturated (ON) must be applied to the base.
condition or a cut off (OFF) condition. For this purpose, a (3) When the transistor is on (collector current is maximum)
drive amplifier is provided between the oscillator circuit and condition with the sufficiently high forward voltage
the output circuit to amplify and to waveshape the pulse applied to the base, the transistor can not be turned off
voltage. immediately, if a reverse base bias is applied to the base
because minority carriers storaged in the base can not be
3-1. Theory of Operation reduced to zero instantly. That is, a reverse current
(1) The horizontal drive circuit works as a so called switching flows through an external circuit and gradually reduces
circuit which applies a pulse voltage to the output to zero. The time lag required for the base current to
transistor base and makes the transistor on when the disappear is called a storage time and falling time.
voltage swings in forward direction and off in reverse (4) To shorten the storage time and the falling time, a
direction. sufficiently high reverse bias voltage must be applied to
(2) To turn on the output transistor completely and to make allow a heavy reverse current to flow. This operation
the internal impedance low, a sufficiently high, forward also stabilizes operation of the horizontal output
drive voltage must be applied to the base and heavy base transistor.
current ib must be flown. On the contrary, to completely
On period OFF period
0 t Input waveform (b)
+
Forward
ib current
0 t Base current (c)
Reverse
current
V -
Falling
(a) time
Storage
time
Fig. 12-2
12-3
3-2. Drive System 3-2-2. OFF drive system
3-2-1. ON drive system When the drive transistor is on, the horizontal output transistor
When the drive transistor is on, the horizontal output transistor is off.
also turns on.
Merit:
Merit: • Energy balance between on and off periods of the drive
• The base current can be precisely controlled without circuit is better, and the circuit can be simplified.
being affected by variation of pulse width which is • Reverse base current of the horizontal output transistor
caused by the horizontal oscillator circuit and the drive can be controlled easily.
circuit.
Demerit:
Demerit: • Base-emitter forward current flowing into the horizontal
• It is difficult to flow a reverse bias current to the horizontal output transistor is susceptible to on-period variation of
output transistor to eliminate its storage carrier for transient the drive transistor.
period of on to off period for the horizontal output
transistor.
H output
H output
H driver
H driver
H OSC
H OSC
ON +B ON
(OFF) ON +B ON
(OFF)
(OFF) (OFF)
Fig. 12-3 Fig. 12-4
12-4
3-3. Circuit Description
In the N5SS chassis, the off drive system is employed.
(1) When Q1 inside Q501 is turned on, Q402 base is
forward biased through 9 V pin 22 of Q501 (H.
VCC) pin 23 of Q501 (H. Out) R411/R410 resistor
divider, and then, Q402 collector current flows through
125V R416 T401. In this case, the H output
transistor Q404 turns on with the base-emitter reverse
biased because of the off drive system employed.
(2) On the contrary, when Q1 inside IC501 is off (pin 8 is
0V), base-emitter bias of Q402 becomes 0V and Q402
turns off, and a collector pulse as shown in Fig. 12-5
develops at the collector.
The voltage is stepped down and Q404 is forward
biased with this voltage, thus turning on Q404.
(3) In this way, by stepping down the voltage developed at
primary winding of the drive transformer and by applying
it to Q404, a sufficient base current flows into Q404
base, thereby switching the Q404.
Q501
H. Vcc
22 T401
H drive
transistor
C431 C417 1 3
R415
Q1 Q404
R411
23 H output
2 4 transistor
R410
C413
Q402
H drive
transistor + V1
R416 V2
0V
C416
9V +125V
VCP
0V
Q402 Q402
OFF ON
Fig. 12-5
12-5
4. HORIZONTAL OUTPUT CIRCUIT
The horizontal output circuit applies a 15.734 kHz sawtooth

wave current to the deflection coil with mutual action of the
horizontal output transistor and the damper diode, and deflects
the electron beam from left to right in horizontal direction.
10 HV
5
2 T461
FBT
S-charactor
3 capacitor
Q404
H output 1 8 Deflection yoke
(With damper diode) (H coil)
IC501 T401
C440 L462 L463 L464
H drive C343
transformer D444
R415
H. out C444
C418
TP-33
Q402 D461 R441
H drive C423
BB81
C463 H
Q1 23 83 linearity
R411 C417 coil
C467
R410
D443 L441
L461
C413
To High Voltage
+ Regulator Circuit
C416 C464
R416
Resonat +
capacitor
To DPC output
SIGNAL DEF/POWER PCB

125V
PCB
Diode modulator circuit
Fig. 12-6
12-6
4-1. Theory of Operation Description of the basic circuit
4-1-1. Operation of Basic Circuit 1. t1~t2:
(1) To perform the horizontal scanning, a 15.734 kHz A positive pulse is applied to base of the output transistor
sawtooth wave current must be flown into the horizontal from the drive circuit, and a forward base current is flowing.
deflection coil. Theoretically speaking, this operation The output transistor is turned on in sufficient saturation
can be made with the circuit shown in Fig. 12-7 a and b. area. As a result, the collector voltage is almost equal to the
(2) As the switching operation of the circuit can be replaced ground voltage and the deflection current increases from
with switching operation of a transistor and a diode, the zero to a value in proportionally. (The current reaches
basic circuit of the horizontal output can be expressed maximum at t2, and a right half of picture is scanned up to this
by the circuit shown in Fig. 12-7 a. That is, the transistor period.)
can be turned on or off by applying a pulse across the
base emitter. A forward switching current flows for on- 2. t2:
period, and a reverse switching current flows through The base drive voltage rapidly changes to negative at t2 and
the diode for off-period. This switching is automatically the base current becomes zero. The output transistor turns
carried out. The diode used for this purpose is called a off, collector current reduces to zero, and the deflection
damper diode. current stops to increase.
3. t2~t3:
The drive voltage turns off at t2, but the deflection current
can not reduce to zero immediately because of inherent
nature of the coil and continues to flow, gradually decreasing
by charging the resonant capacitor C0. At the same time, the
capacitor voltage or the collector voltage is gradually
a H output basic circuit
increases, and reaches maximum voltage when the deflection
current reaches zero at t3. Under this condition, all electro-
H output
transistor magnetic energy in the deflection coil at t2 is transferred to
D Co L
the resonant capacitor in a form of electrostatic energy.
Deflection
Damper Resonant yoke 4. t3~t4:
diode capacitor
Since the charged energy in the resonant capacitor discharges
through the deflection coil, the deflection current increases
Vcc in reverse direction, and voltage at the capacitor gradually
reduces. That is, the electrostatic energy in the resonant
b H output equivalent circuit
capacitor is converted into a electromagnetic energy in this
process.
SW1 SW2 Co L 5. t4:

When the discharge is completed, the voltage reduces to
zero, and the deflection current reaches maximum value in
reverse direction. The t2~t4 is the horizontal flyback period,
and the electron beam is returned from right end to the left
Vcc
end on the screen by the deflection current stated above. The
operation for this period is equivalent to a half cycle of the
Fig. 12-7 resonant phenomenon with L and C0, and the flyback period
is determined by L and C0.
12-7
6. t4~t6: t1 t2 t3 t4 t5 t6
For this period. C0 is charged with the deflection current A TR 0
having opposite polarity to that of the deflection current base voltage
stated in "3.", and when the resonant capacitor voltage
exceeds VCC, the damper diode D conducts. The deflection
current decreases along to an exponential function B TR 0
base current
(approximately linear) curve and reaches zero at t6. Here,
operation returns to the state described under "1.", and the C TR
collector
one period of the horizontal scanning completes. For this current
0
period a left half of the screen is scanned.
D D 0
In this way, in the horizontal deflection scanning, a current
damper
flowing through the damper diode scans the left half of the current (SW2)
screen; the current developed by the horizontal output
E Switch
transistor scans the right half of the screen; and for the current 0
flyback period, both the damper diode and the output transistor (TR, SW1)
are cut off and the oscillation current of the circuit is used.
Using the oscillation current improves efficiency of the F Resonant
capacitor
circuit. That is, about a half of deflection current (one fourth current (Co) 0
in terms of power) is sufficient for the horizontal output
transistor.
G Deflection
current (Lo) 0
H TR
collector
voltage 0
Fig. 12-8
12-8
Amplitude Correction t2 t1 t2 t1
To vary horizontal amplitude, it is necessary to vary a
sawtooth wave current flowing into the deflection coil. q2 q1 t2 = t1 q2 q1 t2 > t1
These are two methods to vary the current; a method which q 2< q 1 q 2= q 1
varies LH by connecting a variable inductance L in series with
the deflection yoke, and a method which varies power supply
voltage (across S-character capacitor) for the deflection
yoke.
As the DPC circuits is used in the this chassis, the later
method which varies the deflection yoke power supply
voltage by modifying the bus data is used. (a) S-character correction (b)
4-1-2. Linearity Correction (LIN)

(1) S-curve Correction (S Capacitor)
Fig. 12-9
Pictures are expanded at left and right ends of the screen even
if a sawtooth current with good linearity flows in the deflection
coil when deflection angle of a picture tube increases. This is
because projected image sizes on the screen are different at
Cs
screen center area and the circumference area as shown in
Fig. 12-9. To suppress this expansion at the screen
circumference, it is necessary to set the deflection angle q1 TR
D Co
to a large value (rapidly deflecting the electron beam) at the LH
screen center area, and to set the deflection angle q2 to a
small value (scanning the electron beam slowly) at the Deflection coil
circumference area as shown in Fig. 12-9.
In the horizontal output circuit shown in Fig. 12-10, capacitor Vcc
CS connected in series with the deflection coil LH is to block (a) H output circuit
DC current. By properly selecting the value of CS and by
generating a parabolic voltage developed by integrating the
deflection coild current across the S capacitor, and by varying
the deflection yoke voltage with the voltage, the scanning
speed is decreased at beginning and end of the scanning, and
increased at center area of the screen. The S curve correction
(b) Sawtooth wave current
is carried out in this way, thereby obtaining pictures with
good linearity.
(c) Voltage across LH
Fast deflection
Slow deflection
(d) Synthesized current
Fig. 12-10
12-9
(2) Left-right Asymmetrical Correction (LIN coil)
In the circuit shown in Fig. 12-11 a, the deflection coil current
iH does not flow straight as shown by a dotted line in the
figure b if the linearity coil does not exist, by flows as shown
by the solid line because of effect of the diode for a first
scanning (screen left side) and effect of resistance of the
deflection coil for later half period of scanning (screen right
side). That is, the deflection current becomes a sawtooth
current with bad linearity, resulting in reproducing of
asymmetrical pictures at left and right sides of the screen (left
side expanded, right side compressed).
When a horizontal linearity oil L1 with a current characteristic
as shown in figure c is used, left side picture will be compressed
and right side picture will be expanded because the inductance
is high at the left side on the screen and low at the right side.
The left-right asymmetrical correction is carried out in this
way, and pictures with good linearity in total are obtained.
(a)
LH
FBT TR
TR LH D Co
D Co Deflection LI
coil
L
Cs
iH Li Vcc C
Cs
S-character
capacitor
(b) Deflection coil current
Deflection coil current
(iH)
(b) Sawtooth wave current
Resistance of LH
0 Characteristic of D
Fig. 12-12
(Left) (Right)
(c) Linearity coil characteristic
Linearity coil characteristic

Inductance
(m H)
(Left) (Right)
Current (A)
Fig. 12-11 Linearity coil
12-10
4-2. White Peak Bending Correction Circuit 4-2-2. Operation theory
4-2-1. Outline Fig. 12-13 shows circuit diagram. From R, G and B output
White peak area in screen picture may sometimes cause (pins 41, 42 and 43 of Q501), video signal is taken in the
bending in picture. See figure below. dividing ratio of resistor R375 and R378. After that, it suffers
In TP48E60 series, correction signal which consists of video DC cut by C360 and integration by R369 and C415, then is
signal and video ripple in video output circuit power supply input to pin 24 of Q501. On the other hand, video ripple in
200V is input to pin 24 (Bending correction terminal) of video output circuit power supply 200V suffers DC cut by
Q501. This corrects white peak bending. C475, and is inverted in Q470, then input to pin 24 of Q501
via C481. Pin 24 of Q501 is a bending correction terminal.
The voltage which is applied to this terminal, controls phase
of video signal to correct white peak bending.
9V
Q501
R375
Q361 Q362
R360 R367
R OUT 43
R364
G OUT 42 Q360
R365 R378
B OUT 41
R368
R366
C360 R369
EHT 24
Bending correction C415 Integration
terminal
Receiving Board BB91

93
Power, Def board 9V
R481 200V
R483
C481 Inversion R478 D406

3 T416
Q470 C475
D470
R484 D474 C466
R482
White peak
Bending by white peak
Fig. 12-13 White peak bending correction circuit
12-11
4-3. H Blanking 4-3-2. Theory of Operation
4-3-1. Outline The H blanking circuit determines the flyback period precisely
The H blanking circuit applies a blanking precisely for the from the AFC pulse in the FBT and applies the period to
horizontal flyback period so that undesirable pictures folding emitter of the video output stage transistor on the CRT-D PC
does not appear at screen ends. board.
This unit allows the users to adjust an horizontal amplitude
adjustment, so, picture quality at screen ends will be improved. 4-3-3. Circuit Operation
This is one of the purposes of the blanking circuit. As can be seen from Fig. 12-14, the flyback period of the
AFC pulse in the FBT starts at a negative side from 0V. To
detects this, the DC component is cut with C493. This is,
C493 is always charged through D487 with a negative side
(about -17V) of the AFC pulse. As a result, a voltage at point
A in the waveform rises from the ground level. This waveform
is sliced in a circuit (R410, C492, D486) to detect the flyback
period. Thus obtained voltage is applied to Q901, Q903, and
Q487 Q905 through D912 ~ D914 and cuts off them thereby
ON period blanking the resters.
D486
Slice level
0V
Approx.
-17V AFC Pulse Waveform at
point
Fig. 12-14
Q901
+27V Q903
D912
Q905
D913
Point A R906 D914

C492
T461 (FBT) Q487 P903
AFC C493 164
CRT-D DCB
7
164
R410 P405 Deflection/Power PCB
R409 D486
R405 R417 Q489
C449 D487
AFC Q488
R438
R445 V blanking
D441
Fig. 12-15
12-12
4-4. 200V Low Voltage Protection 4-4-2. Theory of Operation
4-4-1. Outline Fig. 12-16 shows a connection diagram.
CPT. To prevents this, a 200V low voltage protection circuit Under a normal condition Q340 is always on because of
is provided. about 210V supplied from the 200V line. Accordingly Q340
collector is kept at about 6.2V or the zener voltage of D341
and Q341 is turned off.
If some abnormality occurs and 200V line voltage lowers by
less than about 160V. Q340 turns off and its collector voltage
rises. So Q341 turns on. With Q341 turned on the voltage at
pin 14 of Z801 (expander) exceeds a threshold voltage and
pin 16 of Z80 is high level and makes the power relay turn off.
CRT-D Circuit Defletion circuit V circuit

-12V
R389 R390
P405 P310A P310B
200V 1 1 Q340
R347
2 2 VL VL
Q341
VQ VQ D340
R391
D341 R392 C340
Z801
14 GATE PROTECTOR
16
Fig. 12-16
12-13
5. HIGH VOLTAGE GENERATION
CIRCUIT
The high voltage generation circuit develops an anode voltage

for the picture tube, focus, screen, CRT heater, video output
(210V) and so on by stepping up the pulse voltage developed
for flyback period of the horizontal output circuit with the
FBT, and supplies the power to various circuit.
AFC CRT
10
blanking anode
Heater 9
+12V
C303 R448
4
Auxiliary +27V C447
winding D408
D302 7
C310
R327
6 Focus Pack
C460
D460 R469
-27.5V 5
D406 R443
+210V 3
C446
Primary +125V 2
winding R444
C448
1
Q404 ABL
T401
C463 H deflection coil

L462/L463/L464
L441 R441
1000VP-P
0
C423
1H
(15.75KHz)
Fig. 12-17
12-14
5-1-1. +210V
For the flyback period, pulses are stacked up to DC +125V
with FBT, and the voltage is rectified by D406 and filtered by
+125V
C446.
5-1-2. +35V, 12V

0
Pin 4 of the FBT is grounded and the shaded area of negative
pulse developed for opposite period of the flyback period is
rectified, thus developing better regulation power supply.
5-1-3. -27V Fig. 12-18

As a power for the DPC circuit, a negative pulse signal is
rectified by D460 and filtered with C460, thus developing the
-27V.
10 0
5-1-4. High voltage

4
Singular rectification system which uses a harmonics non-
resonant type FBT is employed and a better high voltage 7 +35V 0
regulation is obtained, so amplitude variation of pictures
becomes low. 6 For +12V
2
0
Fig. 12-19
F G
E Pulse
Picture
tube anode E
F
Primary Picture
tube capacitor
D EH
D Stacked
C C pulse of
4 block
EO
B B
Auxiliary A
A
1H
ABL 15.735KHz
Fig. 12-20
12-15
5-2. Operation Theory of the Harmonic Non-Resonant
System and Tuned Waveforms
The high voltage coil is of film multi-layer winding type and
the coils are isolated into seven blocks. Each block is connected
through a diode.
The basic operation is described in the case of 4 blocks
construction for simplification. Positive or negative pulse
determined by stray capacitance of each coil develops at
terminal points ( , , , , , F , G ) of each coil
as shown in Fig. 12-20, and these pulses are stacked as
shown, thus developing the high voltage.
Moreover, a capacitance between the internal and external
coatings of the picture tube works as a smoothing capacitor.
Focus voltage is obtained at point EO.
The FBT is turned to a harmonic of 15 times the fundamental
frequency, and the turned waveform is shown in Fig. 12-21.
Flyback
pulse 11m s
Reference 1 1
= = 45KHz
wave 22m s 22x10-5
20m s
45 KHz
Becomes 45 KHz x 15 = 675KHz

Harmonics this is determined by coil inductance capacitance and
63.5m s 15 times stray of FBT.
AC
675 KHz
0
AC
0 Tuned
waveform
(In case of 3X) (In case of 15X)
Hight
voltage E E
Focus Picture tube current

current
In case of 15 times the harmonics as compared with

3 times the harmonics, average conduction peiod of
the high voltage diode is wider.
As a result, high voltage variations are suppressed.
AC
0
Fig. 12-21 Tuned waveforms
12-16
6. HIGH VOLTAGE CIRCUIT
6-1. High Voltage Regulator In this unit, pulse transformer is eliminated and the regulator
6-1-1. Outline circuit using the method (3) is employed. The block diagram
Generally, four kinds of methods exist to stabilize a high is shown in Fig. 12-22.
voltage in high voltage output circuits using the FBT:
(1) Stabilization by varying the power supply voltage.
(2) Stabilization by varying L value with a saturable
reactance connected in series with the primary winding
of the FBT.
(3) Stabilization by varying equivalent capacitance of the
resonant capacitor C0.
(4) Stabilization by superimposing a DC or pulse (this
varies the high voltage) on a lower voltage side of the
high voltage winding of the FBT.
FBT ANODE
Hotizonal
output DY
125V
PW output
-27V
High voltage Reg.
V.
Ref.
Fig. 12-22 Basic circuit for high voltage regulator emplyed in the unit
12-17
6-1-2. Theory of Operation
Fig 12-23 shows a basic circuit of the high voltage regulator
used in the unit.
The high voltage regulator circuit splits a resonant capacitor
C0 to C1 and C2. thereby dividing the collector voltage (VCP)
of the H output transistor with C1 and C2.
Horizontal
Here, assume each voltage developed across C1 and C2 as FBT
output C1 LH
LP
VCP1 and VCP1, respectively,
CS +B
C2
VCP1 = VCP
C1+C2 D1
B
C2 D2
C2
VCP2 = VCP C3
C1+C2 Q1 High voltage
Reg.
C2 output amp
VCP = VCP2
C1+C2
each relation can be expressed by the above equations

~ . Fig. 12-23
The VCP2 developed across C2 is DC-clamped with a diode
D1 and the resultant voltage is smoothed with a diode D2 and
a capacitor C3. Thus processed voltage is obtained at the
point . This voltage is used to provide a base current for the
transistor Q1 or to flow the collector current. The voltage at
the point decreases with the circuit impedance and finally
lowers up to a VCE saturation voltage of Q1.
Then, VCP2 is not clamped by D2 with the voltage at the point
B. Since the VCP is expressed as a sum of VCP1 and VCP2 as
shown by equation , VCP decreases by amount the VCP2 is VCP = VCP1 + VCP2
decreased. This varies the high voltage.
Q1 collector current is controlled by Q1 base current which
is an output of the comparison inverted amplifier. That is, the
Q1 base current is controlled by a voltage obtained by
comparing a detection voltage of the top breeder of the FBT VCP 1
(9.1V) and a DC voltage of 9V.
VCP 2..
Fig. 12-24
12-18
6-1-3. Actual As a result, Q480 collector current increases and Q480
Fig 12-25 shows the actual circuit used in the unit. collector voltage (at the point ) decreases. Then, a peak
A resonant capacitor C0 is also split into two capacitors C443 value of VCP2 across C418 is clamped by the diode D443 at
and C444 in this circuit. The high voltage regulator cirucits the collector voltage lowered, and the collector voltage VCP
is structured by splitting the C443 to two capacitors of C443 of Q404 (H output transistor) obtained as a sum of the voltage
and C448. VCP1 across C443 and VCP2 across L418 decreases. Then, the
Here, assume a high voltage increases and the detection high voltage also decreases.
voltage ED´ obtained by dividing the high voltage also When the high voltage lowers, the corrective operation is
increases in proportional to the high voltage. This makes the carried out in reverse order.
voltage ED increase at pin 7. (The voltage is impedance * Resustors R451, R452, R453 and R455 are used to correct
transformed by a voltage follower circuit consisting of op undersirable influence (H amplitude increase at minimum
amplifier Q483 at pin 7.) IH) by the H amplidude regulator.
The voltage ED and a 9V reference voltage developed by a 3-
terminal regulator Q420 are compared. When the ED increases,
the voltage at pin 2 of Q483 differential amplifier also
increases, and the base current IB of the high voltage
transistor Q480 increases.
FBT EH
Horizontal C443
Q404
output L462 C440
-27V
CS
C444
R460
125V
R466
R435
C467
R455 ED'
D461 R461/R469 Q462
L461
R463
Q460
C482
Q483
C464 R454
ED
6
R453 8
D443 B R451 R452 7
D444 R489
C418
C419 Q480
R434 4 R450
2
3
R490
R431 R492 R488
Q420
C483 9V
R494 R439
R487
Fig. 12-25 Actual high voltage regulator circuit
12-19
7. X-RAY PROTECTION CIRCUIT
7-1. Outline
In case picture tube using high voltage, when high voltage
rises abnormally due to components failure and circuit
malfunction, there is possible danger that X-RAY leakage
increases to affect human body. To prevent it, X-RAY
protection circuit is equipped.
7-2. Operation
Figure 10-18 shows the circuit diagram. Supposing high
voltage rises abnormally due to some reason, pulse at pin 9
of T461 also rises, and detection voltage Eb rectified by
D471 and C471 in X-RAY protection circuit rises. When Eb
rises, emitter voltage of Tr10 divided by R25 and R26 in
protector module becomes higher than [zener voltage (6.2V)
of ZD6 + Tr10 VBE ]. This causes Tr10 turns on to supply
base current to Tr9. Then Tr9 turns on. By this Tr6 and Tr6
turn on to make ON/OFF pulse at pin 7of QA01 in low level,
QB30 and Q843 turns off, then relay SR81 turns off. Tr6 and
Tr7 are in thyristor-connection, and 5V of power holds
protection operation until main power switch is turned off.
During circuit operation, power LED near main power
switch blinks turn on and off in red.
Caution : To restart TV set, repair failure first.
5V Z801
15
12V
MICOM
R9
QA01#7
R10
R25 R472 T461
Tr10 ED
Tr7 Tr9 13 9
RB30 D471
R21 R26
RELAY R20
Tr6
SR81 R22 C471
D3
R12 ZD6
16 Tr5 C1
Q843 QB30
R11
12
+ C474
Fig. 12-26 X-RAY protection circuit
12-20
8. OVER CURRENT PROTECTION
CIRCUIT
8-1. Outline
If main power (125V) current increases abnormally due to
components failure, there is possible danger of the secondary
damage like failure getting involved in other part failure, and
abnormal heating. To prevent this, over current protection
circuit is equipped, which detects current of main B line to
turn off power relay in abnormal situation.
8-2. Operation
Fig. 12-27 shows over current protection circuit. When the
current of main B line increases abnormally due to the
shortage in load of main B line, voltage drop arises across
R470. By this voltage drop, when base-emitter voltage of Tr
8 in protector module (Z801) becomes appprox. 0.7V or
more, Tr 8 turns on, and the voltage by divided ratio of R15
and R16 is applied to cathode of ZD4. When this voltage
becomes higher than zener voltage of ZD4, ZD4 turns on to
supply base current to base of Tr 6 via R14. This causes Tr 5
ON and voltage at pin 16 of Z801 becomes Low. Therefore,
QB30 and Q843 turns off to set SR81 OFF. Tr 6 and Tr 7 in
Z801 are in thyristor- connection, and power 5V-1 supplied
at pin 15 keeps protection operation for standby power until
main power switch is turned off. During circuit operation,
power LED near main power switch blinks in red.
Caution : To restart TV set, repair failure first.
R470 F470
MAIN B To T461
R479 R471
5V
C472
15 2 1
MICON
R9
QA01#7
ZD4
RB30 R16
R10
Tr7
RELAY Tr8
SR81 D1
R14 R15
16 Tr6
Q843 QB30
R12 C1
Tr5
R11
Z801
PROTECTOR MODULE
17
Fig. 12-27 Over current protection circuit
12-21
NOTES
12-22
SECTION XIII
DEFLECTION DISTORTION
CORRECTION CIRCUIT
(DPC Circuit)
13-1
1. DEFLECTION DISTORTION
CORRECTION IC (TA8859P)
1-1. Outline (3) V S-character correction

The deflection distortion correction IC (TA8859AP), in (4) V picture position (neutral voltage setting)
combination with a V/C/D IC (TA1222N) which has a V (5) V M-character correction
pulse output, performs correction for various deflection (6) V EHT correction
distortions and V output under I2C bus control. All the I2C (7) H amplitude
bus controls are carried out by a microcomputer and can be (8) L and R pin-cushion distortion correction I (entire
controlled with the remote control. area)
(9) L and R pin-cushion distortion correction II (corner
1-2. Functions and Features portions at top and bottom)
The IC has functions of V RAMP voltage generation, V (10) H trapezoid distortion correction
amplitude automatic switching (50/60 Hz), V linearity (11) H EHT correction
correction, V amplification, EHT correction, side pincushion (12) V AGC time constant switching
correction, I2C bus interface, etc. and controls following
items through the I2C bus lines. 1-3. Block Diagram
(1) V amplitude Fig. 13-1 shows a block diagram of the basic circuit.
(2) V linearity
+12V
14 15 16 5 3
Waveform Trigger Puise V. AGC Time

V. Trigger-in 13 V. Rame AGC
Shape Det Gen. Constant SW
Control Through
H. Trapezoid Distortion Bus
Correction
V. M-Character V. Linearity V. S-Character
Correction Correction Correction
L-R Pincushion
Distortion Correction I
(Bus Control Signal)
SDA SCL
L-R Pincushion
Distortion Correction II
V. Amplitude
10 (Top & Bottom Comer Section)
Adj.
9 Logic
V. Screen V. EHT H.EHT H.EHT
12 Position Correction Input Corrction
H. Amplitude 2 EW-Drive
Adj.
8 6 1 4
V Drive V. Feedback EHT INPUT EW Feedback
Fig. 13-1
13-2
2. DIODE MODULATOR CIRCUIT
Cr, as shown in Fig. 13-3, are applied to the primary
Fig. 13-2 shows a basic circuit of the diode modulator used winding, the high voltage of the FBT is also constant.
in the N5SS chassis.
A key point in the modulation circuit shown in Fig. 13-2 is When the negative pulse developed at point B is integrated
the development of a negative pulse at point B. with Lm and Csm, the average value appears at Csm as a
In this circuit, a current loop of the resonant circuit for negative voltage.
flyback period is shown by an arrow, and the energy stored
in LDY is transferred to resonant capacitors Cr, Crm in By modulating this voltage to have a parabolic curve with
passing through Cr, Crm, Cs when the scanning completes. Q460, a waveform of Vm is obtained as shown in Fig. 13-
As a result, a positive, horizontal pulse as shown in Fig. 4. As a result, the voltage Vs which is the sum of the power
13-3 will appear at Cr, and the current flows into Crm supply voltage VB and Vm, is applied across the S-curve
with the direction as shown. Then a pulse as shown in Fig. capacitor Cs. Vs becomes a power source for the deflection
13-3 develops at the point B. yoke, and the modulated parabolic waveform, as shown in
On the other hand, since constant amplitude pulses across Fig. 13-3 , is applied to the horizontal deflection yoke
and corrects the left-right pin-cushion distortion.
A
FBT
LDY
DD Cr
H
OUT VB
Cs Vs
0
a) Waveform at point A
B Lm
0
DM Q460 Vm
Crm Csm
b) Waveform at point B
Fig. 13-2 Fig. 13-3
VB
VS
Fig. 13-4
13-3
3. ACTUAL CIRCUIT
In the actual circuit, the resonant capacitor is split into two

as shown in Fig. 13-7. One, C440, is inserted between the
collector of the H. OUT transistor and ground. The second
one, C444, is inserted between the collector and emitter. In
Fig. 13-5, C440 is expressed as C1 and C444 as C2, and the
resonant current path for the flyback period is shown by IP2 FBT
IP1
arrows.
C1
IH
In a conventional circuit, when the brightness of a picture H. LDY IP
tube varies, high voltage current and high voltage also vary. OUT
IY1
As a result, horizontal amplitude is affected. IY CS
VS
C2
However, in this circuit, the horizontal amplitude variation VB
can be suppressed to near zero if the high voltage current Lm
varies with variation of the high voltage. C3
IP2 Vm
IY1 Csm
When the scanning period completes, the energy stored in
the deflection yoke LDY is transferred to the resonant
capacitor in a form of current Iy. In this case, the current is
split into two; Iy1 passing through C1, C3 and Iy2 passing
through C2. In the same way, the energy stored in the
primary winding of the FBT is transferred to the resonant
capacitor in the form of Ip. In this case, the current (path) is Fig. 13-5
also split into two; Ip1 passing through C1 and Ip2 passing
through C2, C3. Concequently, the current differences
between Iy1 and Ip2 (Iy1-Ip2) passes through C3.
When the high voltage current IH reduces with a dark

picture, the current Ip in the primary circuit decreases, so VB
Ip1 and Ip2 also decrease. However, a current flowing into
(Iy1-Ip2) increases as Ip2 decreases. As a result, the pulse
developing at the point B increases and the voltage Vm at
Csm also increases as shown in Fig. 13-8. That is, when a VS
dark picture appears, the voltage across S-curve capacitor

Cs increases as shown in Fig. 13-8, the high voltage rises,
and the horizontal amplitude is going to decrease. But, as Vs
0
increases, the deflection yoke current increases and this
works to increase the horizontal amplitude. Accordingly, if
the brightness of a picture changes, the horizontal amplitude
is maintained at a constant value.
Fig. 13-6
13-4
3-1. Basic Operation and Current Path
3-1-1. Later Half Scanning Period 3-1-2. First Half Scanning Period
When the base drive current decreases and the H. OUT
When the power is turned on, the power supply voltage VB transistor is turned off, each of the energies stored in LDY,
is applied to Cs and Csm, and the Cs acts as a power source Lm, Lp of FTB is transferred to C1, C2 and C3, respectively,
for a later half of the scanning period for which the H. OUT and the resonant current becomes zero at a center of the
transistor is turned on, and the deflection current Iy flows in flyback period. Then, VA and VB pulses show a maximum
the path as shown below amplitude.
VA
FBT
LDY
VA
H.OUT IY lP FBT
+
Cs LDY lP
IP1 IY
C1 C2
VB
VB IY2
IP2 Cs
IM LM
DM IDC
CSM VB VB
+
IM LM
IDC
CSM
Fig. 13-7
Fig. 13-9
Voltage & current waveform in H period.
IY 0
IY 0
VA
0
VA 0
IM 0
IDC
IM 0
IDC
VB 0
VB 0
Fig. 13-8 C1: IY1+IP1

C1
C2: IY2+IP2
C2 0
C3: IP2-IY1-IM
C3 0
Fig. 13-10
13-5
3-1-3. Later Half of Flyback Period 3-1-4. First Half of Scanning Period
All energy in the coil has been transferred to the resonant When the flyback period completes, the damper diode DD
capacitors at the center of the flyback period, and the and the modulation diode DM turn on, and the Iy and Im
voltage shows the maximum value. However, during next proportionally decrease from the maximum value to zero.
half of the flyback period, the energy of the resonat capacitor The H. OUT transistor is turned on just preceding at the
is discharged as a reverse current through respective coil. center of the scanning period, and repeats the steps 3-1-1
When the discharge has been completed, VA and VB through 3-1-4 stated above.
becomes zero, and the deflection current in reverse direction
becomes the maximum.
VA VA
L.O.P.T FBT
LDY LDY
IP2 IY
IP1 IP
C1 C2 DD IY
CS CS
IY2
IY1
VB VB VB
VB
C3 LM
LM IM
IM DM
IDC IM
CSM CSM
Fig. 13-11 Fig. 13-13
Voltage & current waveform in H period.
Iy 0
IY 0
VA 0
VA
0
IM 0
IDC
IM 0
IDC
VB 0
VB 0
C1: IY1+IP1
C1
C2: IY2+IP2
C2 0
Fig. 13-14
C3: IP2-Iy1-IM.
C3 0
Fig. 13-12
13-6
SECTION XIV
CLOSED CAPTION/EDS CIRCUIT
14-1
1. OUTLINE
The CC (Closed Caption) and EDS (Extended Data

Services) circuits extract data from from the incoming
video signal and decode them to generate displayable text
information. Major features of the CC/EDS circuit found in
the TG1-C chassis are as follows:
(1) All decoding performed in 1 chip
(2) Capable of processing field 2 data ( CAPTION 3, 4

TEXT 1, 2 EDS) as well as field 1 data ( CAPTION 1,
2 TEXT 1, 2)
(3) Display of text mode extended from 8 rows to 15 rows.
(4) 64 extended characters to handle Spanish and the like.
(5) Background attribute capability (8 colors + transparent)
2. DATA TRANSMISSION FORMAT
The CC/EDS data is transmitted having been superimposed

on line 21, field 1 (21H) and field 2 (284H). Waveform of
line 21
is shown in Fig. 14-1. Line 21 signal is composed of data of
7 cycle clock-run-in, start bit and 16 bit (8bits x 2 bytes).
10_50±0.5m s 4.15±0.1m s 33.764m s

12_910m s
0.12m s
P P
b1 b3 b5 b7 A b1 b3 b5 b7 A
10.076m s b2 b4 b6 R b2 b4 b6 R
I I
T T 20m s
Y Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Fig. 14-1 Line 21 waveform
14-2
3. DISPLAY FORMAT
The character display area of caption mode and text mode

consists of 32 characters x 15 rows as shown in Fig. 14-2.
On the front and back of each row, 1 character blank area is
respectively added. In caption mode, up to 15 rows can be
displayed at the same time. Characters viewed while in text
mode are displayed in a black rectangular box of 34
characters x 15 rows. EDS display format is shown in Fig.
14-3. CC or EDS can be displayed only when data of that
type has been transmitted.
SCREEN
LINE 43
ROW1
LINE 237 ROW15
1 CHARACTER BLANK AREA 32 CHARACTERS 1 CHARACTER BLANK AREA
Fig. 14-2 Caption / Text display area
(Green) Network Name Call Letters (Green)

(White, Slant, Unerline) Program Name
(Cyan) Prog. Length Prog. Type Time In Show (Cyan)
(Cyan)
(Yellow)
Program Description (4rows)
(Character background:black)
Fig. 14-3 EDS display format
14-3
4. CIRCUIT OPERATION
A block diagram of the CC / EDS circuit is shown in Fig. 14-

4, and block diagram of QM01 is shown in Fig. 14-5.
The video signal which is input to pin 9 of UM01 is changed

to 1 Vp-p signal which is band-limited to 600kHz by the
input circuit, and it is supplied to pin 7 of QM01.
Inside QA01, line 21 signal information is extracted from

the input video signal, and is recovered on clock and data.
Recovered data is decoded by the command processor and
converted to a display signal of R, G, B, Ys in Output Logic
section.
The display signal is output at pins 18, 2, 3 and 17 in the

CMOS level of positive polarity. The display output and
OSD are switched by QR01 in UM01, and the selected
signal is sent to the V/C/D IC.
When CC/EDS and OSD are displayed concurrently, OSD

has the highest priority.
H. sync signal with negative CMOS level is input to pin 5

of QM01. This signal becomes the standard signal of a PLL
circuit in the IC. The loop filter for the PLL circuit is
connected to pin 9. QM01 is controlled by the I2C bus
connected to pins 14 and 15.
14-4
UM01 EDS/CC/RGB SW.
QM01 CC/EDS DECODER

XC144144P
UV01 A/V MODULE Q501 V/C/D
Video
in HD
V-AV EH 9 ATT LPF 7 VIDEO HIN 5 INVERTER 11
30 HD OUT
Fig. 14-4 CC /EDS circuit block diagram
VD
VIN 13 12 31 VP OUT
QA01 uCOM QR01 RGB SWITCH
Q89- I2C BUFFER

14-5
BOX 17 2 1A
SCK
SCL1 37 2 SCL1 SCL2 6 13 15 SCK R 18 5 2A
SDA
SDA1 38 3 SDA1 SDA2 5 14 14 SDA G 2 3 3A
Ys OUT
B 3 14 4A 1Y 4 6 36 OSD YS
R OUT
2Y 7 1 37 OSD R
G OUT
1 A/B 3Y 9 5 38 OSD G
B OUT
4Y 12 2 39 OSD B
OSD-YS 18 3 1B
OSD-R
R 22 19 6 2B
OSD-G
G 23 20 10 3B
OSD-B
B 24 21 13 4B
+5V
12
IC XC144144P
VDD
Sllced Data Data MOD

Data Sllcer Data Recovery &
XFR BUF
DLCK
COMP Video 7
V Clamp Data CLK
Recovery
Fig. 14-5 XC144144P QM01 block diagram
8 Display
Sllce Level SYNC Sllcer RAM
CSYNC
Command Processor
COMP SYNC Timing Logic
and CHAR
14-6
ROM
Vertical CTR Decoder Control
And Control
13
VIN
Horizontal R
Counter Output 18
G
Logic 2
DOT CLK B
3
Box
SMS
SDO
SCK
SDA
SEN
17
Phase/
Loop VCO
Freq
Filter
DET
PFD Loop 6 4 15 14 16
FIL Vss AVSS
+5V I2C NC
HIN 5 9 1 11
LPF
SECTION XV
DIGITAL CONVERGENCE CIRCUIT
15-1
1. OUTLINE
The Digital Convergence circuit developes the correction 2-2 Circuit Operation
signals to eliminate geometric distortions in the red, green, (1) When power is applied to the set, C711 resets the unit.
and blue CRTs. This new digital design is smaller than Vertical (VD) and horizontal (HD) sync signals are
previous convergence circuits, more accurate, and adjusted applied to Q701 and Q707. These signals lock the PLL
via the remote control. Once adjusted, the data is saved in (Q707) to 32 MHz, which is counter down in Q701 to
an E2PROM and retrieved every time the set is powered up. provided the clock.
Memory capacity for one full screen of data is 4k. (2) Q701 down loads the data in Q713 to RAM.
(3) Q701 processes the data, and sends it in serial form to
the D/A converters (Q703, Q704, & Q705).
2. CIRCUIT DESCRIPTION (4) Onced processed, the comvergence wave forms are
amplified by Q715, Q717, and Q719.
2-1 Configuration (5) Next, the waveforms are filtered before they are output
Figure 15-1 shows the circuit block diagram for the digital from the digital convergence board.
convergence board. The digital convergence circuit consists
of the convergence processor (Q701), the PLL circuit
(Q707), the E2PROM memory (Q713), D/A converters
(Q703, Q704, & Q705), and pre amplifiers (Q715, Q717, &
Q719).
Convergence waveforms from the D/A converters are
amplified and shaped by Q715, Q717 and Q719, filtered,
and output from unit. The PLL clock is adjusted by L719,
to a basic frequency of 32MHz with no sync signal. Q701
generates a customer convergence test pattern and a service
convergence test pattern, and outputs them as R, G, B and
YS signals.
15-2
R
BLOCK DIAGRAM
G
TEST PATTERN
Q713 B
Ys
E2PROM Load
MEMORY Q701 T7K64
Q703 Q715
FILTER RH
RAM (8x8x13bit)x3 D/A
Save
FILTER RV
C711 Q704 Q717

FILTER GH
RESET D/A
Fig. 15-1
FILTER GV
15-3
Q705 Q719
1/2048
FILTER BH
DATA
COUNTER D/A
CLK
FILTER BV
Q767 Q707
DIGITAL CONV. BOARD
VD
PLL
HD
QA01
32MHz±0.005MHz
µ-CON
MAIN
BUS LINE L719
Sub
BUS LINE
3. PICTURE ADJUSTMENT
The adjustment is done on 60Hz mode (NTSC). This mode is designed so that ordinary user cannot use this,
and special operation is required to use this.
3-1 Change of Memory (E2PROM) Data change is done by direct shift (cursor display) of
Memory of Q713 E2PROM is nonvolatile, and adjusted data adjusting points ; 60Hz mode (NTSC) 8x8 /1 color.
is stored. Since data in RAM of Q701 is eliminated with
power OFF, the RAM is set by soft command of 3-2-2 To enter and to exit
microcomputer QA01 at every power ON. The adjusted Press MUTE key on remote hand unit twice and keep
data which is obtained from screen-watching is once stored pressing the key, press MENU key of set console.
in RAM inside QA01. The whole data in RAM which is Then service data will be displayed on top left of screen.
corrected on each adjusting point and is changed, is saved Under the condition, Press “7” key on remote hand unit, and
into E2PROM (Q713) as a fixed data. The data capacity per the screen shows crosshatch picture (Later, the first picture).
one screen requires 4k for 60Hz mode (NTSC). Press again “7” key, and the screen changes to crosshatch +
data display (Later, second picture). This time changed
3-2 Service Mode data are automatically saved.
3-2-1 Outline Further, press “7” key on remote, the screen returns to
Service mode is controlled by software of microcomputer original picture.
QA01, and is one of function of set.
X + X + MENU
Service data display
The first picture The second picture
(original picture)
Remote Remote "7" key Remote
"7" key +automatic save "7" key
Fig. 15-2
15-4
3-2-3. Picture
60Hz mode (NTSC) ..................... Correcting point Horizontal 8 x Vertical 8 (Arrow marks denote correcting point)
The first picture The second picure
Data display
Cusor (red) Screen center

(Blinking)
Fig. 15-3
The first picture

Crosshatch pattern. Pattern colors are three color display.
Cursor is blinking in red. When changed, condition is last
memory state.
Cursor is ........... Data change mode in lighting,
Cursor shifting mode in blinking.
Display color shows the color that data change is possible.
The second picture

When entering from the first picture to the second picture,
correcting wave of convergence is muted for one second.
During this period, the changed data is transferred from
RAM Q701 to E2PROM Q713, and saved.
The second picture is indicated with data on top left of the
first picture, therefore, convergence cannot be adjusted by
this picture.
(CAUTION)
Receive suitable signal for adjustment. Decide the center
by cross pattern of static convergence in menu, and adjust
convergence from center to circumference.
15-5
4. ADJUSTING PICTURE DIMENSION
(Green picture)
60Hz mode (NTSC)

B
2
12xA
B
2
14xB
2mm
48 inches 4:3 Screen size: Horizontal 975mm Vertical 732mm

Dimension A: 80.9mm Dimension B: 48.8mm
Fig. 15-4
15-6
5. KEY FUNCTION OF REMOTE
CONTROL UNIT
EDS TIMER POWER

TV
E
CABL
VCR TV/VIDEO RECALL MUTE
MOVES CURSOR/LINE TOGGLES CURSOR

UP BETWEEN COLORS
1 2 3
CURSOR
LOCK/UNLOCK CH
MOVES CURSOR/LINE
LEFT
4 5 6
MOVES CURSOR/LINE
RIGHT
ENTER CONVERGENCE
MODE & SAVE
7 8 9
MOVES CURSOR/LINE ENT
DOWN
VOL
RED CRT
ON/OFF
100 0 RNT
GREEN CRT BLUE CRT

ON/OFF ON/OFF
Fig. 15-5
15-7
6. CONVERGENCE OUTPUT CIRCUIT
6-1 Outline 6-2-4. CONV-OUT mute

This circuit current-amplifies digital convergence correction In power-on operation, transistors Q765 and Q766 are made
signal at output circuit, and drives by convergence yoke to turned ON, and -15V is applied to pin 3 of CONV- OUT IC.
perform picture adjustment. These cause mute operation on CONV-OUT.
Digital convergence output signal 6ch adjustment is done.
(H-R/G/B) (V-R/G/B) 6-2-5. Operation of IC
1) Q764 (TC74HC4050AP)
6-2 Circuit Description Sync signal which is input from P711 1 VD, 2 HD, is,
6-2-1. Signal flow through buffer, supplied to digital convergence P708.
Signal which is corrected by digital convergence, is output
to P708 (V, H R/G/B); 2) 3-terminal source
is input to Q751 (V) R/G/B, and is output to P713, P714 and Q754 (+5V) Q755(+9V) Q756(-9V)
P715; Source for digital convergence
is input to Q752 (H) R/G/B, and is output to P713, P714 and
P715. 3) Q767 (TC4066BP)
P711 4 SDAM, 5 SCLM : microcomputer. Busline,
6-2-2. Over current protection circuit through Q767, is input to Digital Convergence P709, and is
All currents of Power supply, -15V, +15V and +30V are controlled.
detected to protect CONV-OUT IC from damage due to
output short of CONV-OUT. 4) To adjust from outside of digital convergence :
Current value: Normal ± 15V approx. 700mA Put adjusting jig into 6P socket of P720. Iscs turns from H
+30V approx. 200mA to L, switch of Q767 is changed over. Then busline from
Detecting curren ±15V approx. 1.8A or more microcomputer is cut off.
+30V approx. 700mA or more protecting operation P720 3 SCLU, 4 SDAU
Controlled by external adjusting jig.
6-2-3. Pump-up source
CONV-OUT IC Q752 (H)
Pin 10 (+15V/H,PV)
Pin 5 (+30V)
By HD input signal, pump-up is done only in horizontal
retracing time.
Pump-up
Pump-up source waveform

Horizontal correction wafeform
+30V +30V
+15V
+15V
0V
0V -15V
-15V
Horizontal correction waveform
Fig. 15-6
15-8
P712
PROTECT
5V-1
NC
+15V
(PROTECTOR)
1 2 3 4 R7782
(REGULATER) (+30V)
0.82Ω
Q754
5V-1
+5V D7701 Q757
DIGITAL CONVER R7750
(+15V)
Q755
0.33Ω
P708 +9V
RV
GV Q756 D7702
Q771 R7765
BV (-15V)
-9V
CONVERGENCE (BLOCK DIAGRAM)
RH 0.39Ω
GH
BH
Q770
C7771
+9V Q764 (PUMP UP)
-9V
+5V TC74HC4050 (HD) Q769 +15V
CONVER
HD YOKE
VD V
15-9
CONV-OUT Q751 P713
(HD) STK392-110 RED
5 H
10
B-V 9 G-V 11 R-V 18
R 8
G Q767 4 V
3 12 17
B MUTE
TC4066BP P714
Q765 BLUE
I2CS H
SCLV +
SDAU C7765
CONV-OUT Q752
+30V (+1501 (H) STK392-110
5
SCLM 10 H.PU)
SDAM V
B-H 9 G-H 11 R-H 18
8 P715
4 12 17 GREEN
P720 P711 3
6 5 4 3 2 1 7 6 5 4 3 2 1 H
MUTE
VD
HD
-15V
CNT
GND
DFAI
I2CS
GND
GND
INCS
SLLU
+
SCLM
SDAU
SDAM
C7766
Q766
7. CONVERGENCE TROUBLESHOOTING CHART
Relay turns on Reray OFF Relay operation sound Reray ON No Convergence

once but immediately at power on. correction wave.
turns off.
OK
Check screen modes

of picture.
Convergence PCB,
pull out of P712. Protect 1
Reray ON
Reray ON
Check power Check Q751, Q752

supply circuit. and repair.
Reray OFF Reray OFF Reray OFF
Check P708 R/G/B

correction wave.
Proceed to "protection
OK
circuit diagnosis procedures".
Check voltage at NG
Check power supply
±15V+30V pump up. circuit.
OK
Convergence output signals correction wave
Are output signals NG
Pump-up Check DEF PC13.
applied to H, Vblk of P711.
OK
+30V
Check voltage across NG Check Q754, Q755,

±9V+5V Q754, Q755, Q756. Q756 and repair.
0V
OK
-15V
Vertical Horizontal
Check signals of all IC
Q751 Q752
and associated cirduits.
(R/G/B) (R/G/B)
15-10
LAB 3
DIGITAL CONVERGENCE
GREEN GEOMETRY
1. Put the set in the service mode and bring up the convergence cross hatch.
2. Push the 100 button to turn off the red tube, and RTN to turn off the blue tube.
3. Place the convergence template on the screen and align the center cross hairs with the tabs in the
bezel.
4. Use low tack masking tape to attach the template to the bezel. Try to get the template flat against
the screen to reduce parallax errors.
5. Push the 3 button on the remote until the blinking cursor in the upper left corner of the screen
turns green.
6. Move the blinking cursor to the right with the 6 button, then down with the 8 button until it’s one
line to the right of center. The 4 button moves the cursor to the left, and the 2 button moves it up.
7. Push the 5 button to lock the cursor in place.
8. Use the 2, 6, 8, and 4 buttons to align the intersection of the cross hairs with those on the
template.
9. Push the 5 button to unlock the cursor.
10. Move the cursor to another location and repeat steps 7 and 8. Moving the cursor in a counter
clockwise spiral to the various locations works best. Normally, you need to repeat the procedure
a second time to make fine adjustments.
RED CONVERGENCE
1. Remove the template and press the 100 button to turn on the red tube.
2. Press the 3 button until the red cursor appears.
3. Align the red cross hatch pattern to the green cross hatch pattern the same way you aligned the
green with the cross hatch pattern on the template.
BLUE CONVERGENCE
1. Push the 100 button to turn off the red tube, and RTN to turn on the blue tube.
2. Push the 3 button until the blue cursor appears.
3. Align the blue cross hatch pattern to the green cross hatch pattern in the same manner.
4. Push the 100 button to turn on the red tube and check the convergence with all three tubes on.
The cross hatch pattern should be white with no red, green, or blue present. However, depending
on how much the blue tube is defocused, a slight blue halo may show.
15-11
5.Push the 7 button then the power button to save the settings and exit the service mode.
ELECTRICAL CENTERING
1. Disconnect all video cables in the video 1 input.
2. Put the set in the service mode.
3. Push the TV/VIDEO button on the remote until the white cross hair pattern on a black
background is displayed.
4. Check the centering of the cross hair pattern with the centering tabs in the bezel.
5. If the horizontal position is off, push the channel up button until the HPOS register appears. Use
the volume button to center the pattern.
6. If the vertical position is off, push the channel up button until the VPOS register appears. Use
the volume button to center the pattern.
7. Push the TV/VIDEO button until the TV picture is displayed, then turn the power off.
8. Turn the set on and check the picture quality with a live video signal.
END OF LAB 3
15-12
SECTION XVI
OPTICAL SECTION
16-1
1. NECK COMPONENTS
NOTES:
1-1. Outline of Components Around Neck of The
Projection Tube
Fig. 16-1 shows names and mounting locations of neck

components around the projection tube.
Deflection yoke Velocity modulation coil

Projection tube
Fig. 16-1
The neck components consist of, a deflection yoke assembly

(which consists of a main yoke, a sub-yoke, and a
centering magnet), and a velocity modulation coil .
The main yoke of the deflection yoke assembly consists of

a horizontal and vertical deflection coil, and deflects electron
beams in horizontal and vertical directions.
The sub-yoke is called a convergence yoke and also consists

of a horizontal and vertical coils. The sub-yoke performs
distortion correction and color registration according to
correction currents supplied from the convergence output
circuits.
Moreover, a centering magnet consisting of two 2-pole

magnets is provided at end of the deflection yoke to adjust
the raster position.
16-2
1-3. Projection Tube
TP4688J, TP4880A TP48E60/61 TW56D90

• Fluorescent screen: flat • Fluorescent screen: inverted R 350mm
Fig 16-2
Electrons around the peripheral of the CRT screen come Light beams around the peripheral of the CRT screen are
into collision with the A/B lenses and are not used, thus focused towards the center, thus increasing the amount of
lowering contrast, etc. light emitted towards the screens.
• Electromagnetic Focus
Electromagnetic focusing with magnets mounted around • Electrostatic Focus
the CRT neck. High unipotential focus
Eb G2 Screen
G5 G4 G3 K
Focus
Fig 16-3
Since the deflection is carried out by using a magnetic field The best beam pattern is obtained at screen center and
applied from the outside of the neck, high deflection power screen edges by applying parabolic voltages for H and V
is obtained and focusing quality is high. Moreover, since periods to the focus terminals.
the coils are mounted on the outside of the neck, the
configuration of the deflection fields created inside the neck This also assures a flat focusing characteristic across the
has less distortion, thus the best beam pattern will be entire screen.
obtained.
To obtain clearer pictures, a velocity modulation circuit is
also provided.
16-3
2. FUNCTION OF KEY COMPONENTS
2-1. Outline 2-2. Theory of Operation

The optical system of the TP48C60/61 consists of a screen,
mirror and lens assembly. A description will be given for
each block.
Screen
Mirror FRESNEL LENTICULAR

Sheet Sheet
Projection tube
Screen
Lens
Lens
Projection tube
Lens Refracting light beams running to screen

peripheral area to the G-axis direction
Projection (screen center direction) with effect of
tube convex lenses.
Optical coupling
system Widening directional
characteristic in horizontal
direction.
Fig. 16-4 Fig. 16-5
16-4
2-3-1. Effect of Fresnel Sheet 2-3-2. Appearance of LENTICULAR Sheet
The shape of the lens has been changed to reduce focal
length.
(This allows the product size to be reduced, specifically in
the distance from front to rear.)
FRESNEL
sheet
Effect of
FRENSNEL sheet
Lens
Without FRESNEL sheet
Fig. 16-6
LENTICULAR lens
Black stripe
n
tio
irec
ed
n sid
ree
Sc
Viewer side
Fig. 16-7
16-5
LENTICULAR sheet 2-3-3. Effect by LENTICULAR Sheet
If the light enters the front lenticular screen on the diagonal,
the light will be diffused in the same way as parallel light
incidence when viewed from the front of the TV.
Projection Viewer side

TP4688J TP48C50/51 tube side
TP4880A TW56D90
F1 F2
(Body diffusion) (Surface layer diffusion)
Diffuser Incident Outgoing

light light
When light beams enter LENTICULAR

sheet in parallel.
F1 F2
Fig. 16-8
Incident Outgoing
light light
Light beams will be effectively used by collecting the

diffuser at surface of the layer, thus increasing the brightness Black stripe
by about 10%. When light beams enter LENTICULAR

sheet diagonally.
SCREEN GAIN
LENTICULAR lens
TP48C60/61 5.6
TW56D90 6.2
Fig. 16-9
16-6
2-4. Optical Coupling Effect 2-4-1. Optical Coupling Effect
An liquid with a refraction index near that of glass is filled (1) Light beams , emitted from the fluorescent
between the projection tube and lens to suppress: surface A advance up to the lens, but light beam
returns to the fluorescent surface due to the total
(1) total reflection from the tube, thereby improving the reflection.
contrast
(2) This extremely lowers the contrast at the fluorescent
(2) interfacial reflection to reduce loss of light. Moreover, surface.
with the cooling effect of the liquid, the power output of the
projection tube can be safely increased. Assuming that the reflection index of air is 1.0 and that of
glass 1.5, the angle which causes the total reflection is 41.8°
That is, the light beams with an angle of q higher than 41.8°
can not exit from the projection tube. The light beams
returned to the fluorescent surface reaches 56% of the total
beams coming out from A.
Projection tube
Lens Liquid (ethylene glycol + glycerine) Projection tube

Index of refraction 1.4~1.45 fluorescene plane
Fig. 16-10
Lens
1 2
Air
Projection tube
face glass
3
q Fluorenscene plane
A
Projection tube
Fig. 16-11
16-7
2-5. Lens 2-5-1. Optical Coupling Effect
The lens system consists of a main lens (3 pieces of lens),
C lens, and the face plate of inverted gCRT (used as a lens), Note: When making adjustments on the neck components,
and realizes a short focus optical lens system with less it is always best to use dedicated drivers made of non
quantity of lens. magnetic material to avoid any distortion while
With the short focus optical system employed, the depth of making adjuctments.
the unit is reduced by about 30%, thus making the unit slim
and compact. Optical focus will be made according to the procedures
shown below. After completion of the electrical and optical
focus adjustments, convergence adjustments should be
made.
Liquid coolant
Plastic lens
Negative radius phospher
Loosen screws and adj ust the lens focus at

the best position by moving lenses left and right.
7" High bright
electrostatic focus CRT
Fig. 16-13 Lens focus adjustment
Glass lens
Black coating
Fig. 16-12 Projection

tube
LENSES
TP48C60/61 USPL DELTA 77 Deflection yoke Velocity modulation coil
(Mounted projection tube) V.M.Coil
TW56D90 USPL DELTA 79
Fig. 16-14 Mounting position of

deflection yoke and V.M coil
16-8
2-6. Focus Adjustment
(1) Turn on the static convergence switch and receives a
cross character signal.
(2) For easy adjustment, project one color to be adjusted
at a time on the screen. (Other colors can be interrupted
by putting caps on the lens.)
(3) Turn the electrical focus volume for the color to be
adjusted clockwise or counterclockwise so that the
focus at center of the cross character shows the best.
(4) Loosen screws securing the lens and move the lens
toward left and right until the best focus is obtained at
center of the cross character.
(5) repeat steps 3 and 4 to obtain the best focus. Finally,
secure the screws.
(6) Perform the convergence adjustment according to the
convergence adjustment method.
Focus pack
SCREEN
R G B
FOCUS
Electrical focus and gun drive

controls.
Remove 4 screws and

take off the cover which is in front
of the focus block.
Fig. 16-15
16-9
NOTES
16-10
Chapter XVII
Power Supply
17-1
Notes:
17-2
1. Power Supply Overview
A block diagram of the power circuit is shown in fig. 17-1. The power circuit consists of the following:
1) Standby Supply, which supplies the +5V-1 Standby to the microcomputer and +12V Standby to the On/Off Relay
(SR81).
2) Main Supply which supplies HORIZONTAL OUTPUT B+ (+125V) and AUDIO OUTPUT Vcc (+38V). The signal
process circuits are supplied by +5V-3, +5V-2, and +9V-2 via regulators from the 12V source of the Main Supply.
3) Sub Supply which supplies +30V, +15V and -15V for the convergence output board.
F801 T801 T802 T840

+12V Q840
Standby Supply
POWER
TRANS. REG. +5V-1 (MICROCOMPUTER)
TPW
1549AZ D840 Q830
REG. +5V-2 (for TUNER, COMB, V/C/D etc.)
Q831
T862 +12V
REG. +5V-3 (for PIP, ESD/C.C/RGB. SW) Main Supply
Q832
CONVERTER
F860 REG. +9V-2 (for COMB, DSP, CRT-D etc.)

SR81
+38V
TRANS.
R861
AUDIO OUT Vcc
D801
+9V
Defl. Vcc (to V/C/D IC)
Q801 Q430 F470 B+ (+125V)
VOLTAGE CONTROL TPW F.B.T. V.M
STR-Z3201 3332AS R470
R479 R471 +32V (TUNER)
R101
Q843 1 2
X-RAY
SW Z801 13 F.B.T.(HEATER)
R883
+
Q862 PROTECTOR C471 D471 R472
Q830 PHOTO COUPLER H1C1019 14 200V L.V.P. 35V O.C.P
SW 3 16
D802~D805
F850 +30V R7782
T888
F851 +30V
CONVERTER
O.C.P
Q768
Q802 +15V R7750 CONVERGENCE
TRANS.
VOLTAGE CONTROL
STR57041 +15V CIRCUIT
LOW VOLTAGE PROTECTOR O.C.P
Q853 Q854 Q759
-15V R7765 -15V
TPW
3330AM
O.C.P
Sub Supply Q762
Figure 17-1 Power Supply Block Diagram
17-3
2. Rectifying circuit and standby power supply
The rectifying circuit generates dc voltage sources from former. D840 along with C840 output a rectified and
the 117 Vac input. D899 is a metal oxide varistor used to smoothed 12V signal for driving relay SR81 and for sup-
absorb surges due to line spikes, lightning, etc. The arrow plying the +5V regulator, Q840. Q840 supplies the standby
in fig. 17-2 indicates the path in which the surge is by- +5V-1 and the reset signals for the microcomputer as well
passed. C801, T801 and T802 are filters for abnormal ra- as other circuits. When the power is switched on, QA01
diation or line noise. For direct view sets the degaussing (ICA01), the Main Microcomputer, sends a high signal from
circuit, using a thermistor, is supplied after SR81 (not pin 7 to the base of QB30, turning it on. This causes the
shown). R810 is used to suppress surge current during base of Q843 to go high and thereby turn it on. When Q843
switch-on. D801, along with C810, output a rectified and turns on, current flows through the coil of SR81, activat-
smoothed DC voltage. T840 is the standby power trans- ing the relay and thereby switching the main power on.
160 Vdc
+ Rectified
F801 D899 C801 Output
D801
117Vac C810
_ R810
Surge T801
+5V-1
Q843 QB30
.12Vdc MICOM
All voltages shown are POWER
during ON condition. 4.2Vdc On=5V
Off=0V
SR81 10.9Vdc
Q840
1 5 +5V (to MICOM)
3.9Vdc
2 4 Reset 5Vdc
3
0V C842
T840 D840 C840 C843
Figure 17-2 Standby Supply
3. Main Supply Circuit

The circuit in fig. 17-3 is a current resonant switching type and very little noise. In the case of a short on the load side
power supply that incorporates a hybrid IC, Q801 (STR- of T862, the AUDIO OUTPUT, Low B, and B+ circuits are
Z3201). The current resonant power circuit is highly effi- protected with F899, F890 and F470 respectively. F860 is
cient in that it operates with very low power consumption used to protect the primary side of T862.
4. Outline of Current Resonant Type Supply

Fig. 17-3 shows the configuration for the Current Reso- The automatic voltage control operation is performed by
nant type power supply. A start-up voltage is sent to Pin 10 the detection of the B+ voltage (125V) fed into the error
to begin operation. VIN source voltage of 160V is applied amp, Pin 5, of IC Z801, then output through Pin 3 to the
to Pin 1. Pin 14 is tied to ground for the negative phase of photo coupler. Next this signal is fed into the primary Os-
the MOS-FET configuration. The Primary winding of T862 cillating (OSC) circuit, located inside IC Q801 (Pin 6) which
and C870 are connected in series to form an LC Series controls the frequency of the ON/OFF time, via an internal
Resonant Circuit. The converter transformer, which is logic IC, for the MOS FET configuration.
driven by a push-pull MOSFET configuration located in-
side Q801, operates in forward mode.
17-4
R861
D862 D864
C876 D876 L863
R862 F860
IC Q801 STR-Z3201 17.4Vdc 89Vdc 78Vdc 78Vdc R871
10 16 3 2
Vcc VB HO G(H)
VIN
TSD OVP START 1
150-160Vdc
1.3Vdc CD R1
9 DELAY LATCH REF Logic F890
C869 OUT F899
15 F470
D801 +
72.6Vdc +12Vdc
R872 OC +38Vdc
OSC R2
12
B+ 125Vdc
OC CONTROL OSC
C867 COM C870 T862
R870 R865 .O1Vdc 14
ERROR
R4 R3 0V
AMP
C874
Z801
Css CONT CT RT GND LO G (L)
8 6 5 7 4 11 13
4.7Vdc R863 4.7Vdc 3.5Vdc 5.3Vdc 0V 7Vdc 7Vdc PHOTO
COUPLER
C866 D879 L864 Q862
R864 C862 R867
Figure 17-3 Current Resonant Supply (Main)
5. Fundamental Theory of LC Series Resonant Circuit

The LC series resonant switch mode power supply is a fre- increases. Conversely, when the load decreases, the fre-
quency regulated power supply operating above resonance quency increases and the current decreases. Table 17-1
(see figures 17-3 and 17-4). The LC series resonant circuit shows the voltages developed on T862 secondaries.
is composed of the primary winding of T862 and C870. A
Table 17-1 T862 Voltage Chart
negative feedback circuit is used to control the output of
the transformer. The feedback circuit, which monitors the T862 Pin # Voltage
125Vdc source, is composed of the error amp inside Z801
and the photo coupler (Q862). This feedback is applied to
Pin 2* 47 Vp-p
the CONT input (Pin 6) of IC801 to control the frequency Pin 3 Hot Side*
of the internal oscillator (OSC). When the load increases Ground
on the secondary side of the transformer, the frequency
decreases (operates closer to resonance) and the current Pins 4, 5* 148 Vp-p
Pins 6, 7* 127 Vp-p
VL (v)
Pin 9 27 Vp-p
increased Pin 10 27 Vp-p
load
decreased Pin 11, 12, Ground,
load
15 Signal Side
e
Pin 13 256 Vp-p
Pin 14 256 Vp-p
Pin 16 81 Vp-p
Frequency
Resonant point Nominal Pin 17 81 Vp-p
1 Operating
f= frequency
2π LC
* Reference Hot Side Ground (T862, Pin 3) when
measuring Pins 2, 4, 5, 6, and 7. CAUTION, USE
Fig. 17-4 Resonance Curve ISOLATION TRANSFORMER.
17-5
6. Main Supply Actual operation
Refer to Figure 17-5 diagram and waveforms.
1. Start-up 5. Css terminal (Pin 8) - soft start
When power is applied to the set, a start-up voltage of When power is first applied, the switching frequency is
16V is applied to pin 10 of IC Q801. At the same time, set high by capacitor C866 and resistor R863, resulting
charging of C869 (pin 9) induces a delay to the internal in soft start of the switching supply. Thus, current (surge)
latch circuit to prevent the Over Voltage Protect (OVP) in the POWER MOSFET output is limited to provide
circuit from shutting the set down. stable starting of the supply sources. After initial start-
2. Output switching element up, the circuit operates at its nominal frequency (70-80
kHz).
Two power MOSFETs operating in push-pull mode are
used for switching. The on-off timing of each is con- 6. CD terminal (Pin 9) - Latch Delay
trolled by the logic inside Q801. To avoid a short circuit The Latch circuit shuts the power supply off (shut-down)
from occuring a delay is used between the turn off of one when a fault is detected. Shut-down occurs by detecting
MOSFET to the turn on of the next. errors from the following:
3. CT terminal (Pin 5) - basic oscillation • Over voltage protection (OVP) circuit
The frequency of the internal oscillator is controlled by • Thermal shock detection (TSD) circuit
the Oscillator Control block. The frequency is deter- • Over current protection (OCP) circuit
mined by the charge and discharge of capacitor C862
connected to CT terminal. The oscillator generates a ramp • Loss of and no recovery of Main B+
waveform at Pin 5. The ramp waveform charges up to 4 The charging time of capacitor C869 connected to the
V (typical) and discharges to about 2.5 V. The charging CD terminal (Pin 9) is used to delay the operation of the
time is the output-on period, and discharging time is the Latch circuit when power is initially applied. If the unit
off period (see OSC OUT SIGNAL waveform of Figure goes into shut-down, temporarily remove ac power to
17-5). The lowest oscillation frequency is determined by reset the latch circuit.
capacitor C862 and resistor R867. 7. OC terminal (Pin 12) - Over Current Detect
4. CONT (Pin 6) - frequency control This is to detect over-current in the LC series resonant
Current flowing out of the CONT terminal (Pin 6) varies circuit.
the charging current of oscillator capacitor C862, which 8. Over voltage protection (OVP) circuit
in turn controls the frequency of the Output (Pin 15) sig-
If the Vcc terminal (Pin 10) exceeds 22V (typical), the
nal. The control current is determined by the
Latch circuit is engaged (shutdown) .
Photocoupler. The Photocoupler phototransister side cur-
rent is determined by the feedback current of the photo- 9. Thermal shock detection (TSD) circuit
diode side. The photodiode current is determined by the This is to make the Latch circuit operate when the IC's
Error Amp inside of Z801, which is monitoring the internal temperature exceeds 150°C.
+125V source. Thus, the terminal current (CONT) cor-
responds to the feedback from the +125V output.
17-6
R861
D862 D864
C876 D876 L863
R862 F860
IC Q801 STR-Z3201 17.4Vdc 89Vdc 78Vdc 78Vdc R871
10 16 3 2
Vcc VB HO G(H)
VIN
TSD OVP START 1
150-160Vdc
1.3Vdc CD R1
9 DELAY LATCH REF Logic F890
C869 OUT F899
15 F470
D801 +
72.6Vdc +12Vdc
R872 OC R2
+38Vdc
OSC
12
B+ 125Vdc
OC CONTROL OSC
C867 COM C870 T862
R870 R865 .O1Vdc 14
ERROR
R4 R3 0V
AMP
C874
Z801
Css CONT CT RT GND LO G (L)
8 6 5 7 4 11 13
4.7Vdc R863 4.7Vdc 3.5Vdc 5.3Vdc 0V 7Vdc 7Vdc PHOTO
COUPLER
C866 D879 L864 Q862
R864 C862 R867
DELAY TIME
=4V
(PIN 5)
CT PIN VOLTAGE
=2.5V
OSC OUT SIGNAL

(Internal)
(PIN11) ON OFF
LOW SIDE
GATE VOLTAGE
(PIN2)
HIGH SIDE OFF ON
GATE VOLTAGE
(PIN 15) =VIN

PUSH-PULL PIN VOLTAGE
OUT VOLTAGE (PIN 1)
OV
(PIN 15)
PUSH-PULL
OUT CURRENT
OA
Figure 17-5 Current Resonant Supply with Wavefoms

17-7
7. Scan-Derived Voltages (FBT)
Figure 17-6 shows the voltages derived from the FBT of (ABL) signal from pin 8. A 12Vdc source is also derived,
the Horizontal Deflection circuit. The FBT derives 200V via pin 7 and D408, to supply the SVM and DPC circuit
for the Video Output circuit from pin 3, +35V for the Fail boards. In addition, the 12Vdc source is used to develop
Safe, H.V. Regulator, Blanking, Dynamic Pin Cushion the +9V-1 source via a 9 Volt regulator made up of Q420,
(DPC), and Vertical Deflection (V.D.) circuits from pin 6, Q421, and D427. High voltage is supplied from the sec-
and -27V for the side DPC circuit from pin 5, Heater volt- ondary along with Focus and Screen voltage sources devel-
age from pin 9, Automatic Frequency Control (AFC) and oped from a tap on the high voltage secondary of T461.
blanking signal from pin 10, and the Automatic Black Level
AFC
BLANKING 10
+9V-1 Reg.
+9V-1 (Q420, 421,
D427) HEATER 9
FBT
29-30kV
4 to 2nd ANODE
R448 D408
+12V 7
C447 C307
R327
+35V 6 Z410
C310 D307 FOCUS X 3
D460
FOCUS
-27V 5 X3
C460 R469
SCREEN
X3 G2
R444 X3
B+
2
125Vdc C448
D406 R443
200V DF In
3
(Dynamic Focus)
C446
Q404 1 8 ABL
Collector
T461
Figure 17-6 Scan Derived Sources
17-8
8. Protector Module (Z801)
Figure 17-7 shows the standardized protector module In the B+ Over Current Protect (OCP) circuit, the cur-
(Z801). The following are the four different sections within rent is being compared across R470, which is applied
the Protector Module: Error Amp, Switch/Latch, B+ OCP, through Pins 1 and 2. The resistance of R470 is so small
and X-Ray Protect. In addition the Over Current Protect that changes in voltage equate to larger changes in current.
(OCP), Over Voltage Protect (OVP), and Under Voltage When a large enough change in voltage occurs the internal
Protect (UVP) circuits are routed through the internal latch circuit outputs a low on Pin 16, which shuts the unit
Switch/Latch circuit to trigger the unit off through the Pro- down.
tect output (Pin 16).
In the X-Ray Protect circuit, Pin 11 provides a reference
The Error Amp circuit monitors the B+, 125V line, via voltage of +25V. If the High Voltage increases abnormally,
Pin 1. The Error Amp controls the current through the Pin 9 of T461 senses the increase and increases the voltage
photodiode of photocoupler Q862. When the B+ voltage through R472. This increased voltage is applied to D471,
decreases Q862 conducts less and when it increases, Q862 which rectifies AC to DC. The increase in Vdc is applied
conducts more. to Pin 13, which will trigger the internal latch circuit and
The Switch/Latch circuit is used to turn off SR81 relay in output a Low on Pin 16. As long as +5v-1 is applied to
case of over current, over voltage or under voltage. In shut- pin15, the remote control hand unit will not recover the
down mode, Pin 16 (Protect) latches low, which turns QB30 power. The AC power line must be disconnected to reset
off. When QB30 turns off Q843 turns off. This causes the the latch.
relay (SR81) to open and thereby disconnect the power.
* See Protect Circuits

starting on page 17-9.
+35V Over Current Protect
+30V Over Current Protect
To SR81 +5V-1 Active High +15V Over Current Protect
Relay -15V Over Current Protect
RB30 From ICA01 +30V Over Voltage Protect
QB30 5V
(125V) Power (Pin) R470 +15V Over Voltage Protect
B+ 0.1V .56 (125V) +15V Under Voltage Protect
4.9V
1 Q843 B+ -15V Under Voltage Protect
4 4.4V
0V 200V Under Voltage Protect
Q862 R471 R479
R884
3
2 R890 C472 C474 +25V C471 D471 R472
6.2V 116V 4.9V 5V-1 0V 0.1V 22V
3 16 15 2 1 14 12 13 11 9
5
IZ C-Out Protect OCP Gate X-Ray X-RAY
B+
Protect
T461
Control
Error Switch B+ OCP X-Ray

Amp / Latch Protect 4 , 8 , 9 , 10
PIN: VACANT PIN
14 GATE terminal
When the voltage at this
terminal becomes approx.
Z801 (HIC1019) 1.5V or more, protection
7 17 circuit operates.
GND1 GND2
Figure 17-7 Protector Module Circuit
17-9
9. Sub Supply
This decrease in current through the primary winding, re-
The Sub Supply is located on the Convergence Out/Power2
duces the electromagnetic inductance across the base drive
board. Figure 17-8 shows that the Sub Supply is a ringing
winding, which decreases the voltage to the base of Q1 and
choke converter, using hybrid IC STR57041. Operation
thereby rapidly turns Q1 off.
begins with a start-up voltage that is applied through R852.
This provides a trickle base current to Q1 (internal to the T888 uses a detection type winding through Pins 7 and 8.
IC, Pin 2 of Q802), which causes it to turn on. When Q1 The secondary windings are proportional to the detection
turns on, the collector current begins to flow. During this winding. Subsequently, any fluctuation in voltage across
start-up time the current is flowing through the primary the secondary windings is sensed across the detection wind-
winding of T888 through Pins 2 and 5. At the same time ing which is fed back through Vo sense (Pin 1). This feed-
current will flow through Pins 7 and 8, which create the back is used to regulate the On/Off time of the internal
detection winding, as well as Pins 8 and 9, which create switching transistor Q1.
the base drive winding. During the first half cycle of the
AC pulse no current flows through the detection winding R846, C845, R852 and D848 create a voltage clamping
because of the reversed polarity of D856. Pin 9, however, circuit that allow the collector voltage of Q1 to stay within
provides positive feedback for the base, as the electromag- a specified level. R847, C855, R848 and D849 filter the
netic inductance increases, to rapidly turn Q1 on. As Q1 base voltage. Q850, Q851, Q852, C856, D855, R857 and
becomes saturated the current through the primary wind- R859 create the Slow-start circuit. C856 determines the
ing decreases. rate of the start-up time.
D857 L853 F851

Bridge rectifier
output 5 17 +30V
C856 +
R846 C845
D855 +
R852 L858 C858 C859
C857
R857
163.7V
Input (C) 3 2 15
C850 C849 D848
D858 L855
0.2V C851 R858 C855 10 +15V
Base Drive (B) 2 9
D850 +
C880 C881 C882
R847 D849
Earth (E) 4 8
0.0V +
11
C853 R850
Vo Control 5 7 12
-35V D856
+
-42V
Vout Sense (-) 1 C848 C847 C846
R859
R860
Q802 13 −15V
STR57041 D859 L857
R853 R854
Q851 T888
Q852
Figure 17-8 Sub Supply
17-10
10. Protect Circuits
D370
Protect (active high)
To Pin 14 of Z801
R372
35V
Q370 LOAD
3.9K
35.3V
5.6K 1.5
+35V
C370 R371 R370
+35V OVER CURRENT PROTECT CIRCUIT

(Located on Deflection/Power board)
Figure 17-9 +35V Over Current Protect Circuit
(Located on Deflection/Power Board)
LOAD +30V
R7782
0.82
R7783 R7784
330 C7770 470
29V
To Pin 14 of Z801
Q768
29V
0V
Q758 Q757
R7763
2.2K

(Located on Convergence Out/Power2 Board)
17-11
LOAD +15V
R7750
0.33
R7749 R7751
330 C7760 470
16.1V Protect (active high)

To Pin 14 of Z801
Q759
15.8V
0V
Q758 Q757
R7747
2.2K

LOAD -15V
R7765
0.39
R7764 R7763
330 C7763 470
-16.2V
To Pin 14 of Z801
Q762
-16V
1.5V
R7758 Q761 Q757
2.2K
Figure 17-11 -15V Over Current Protect Circuit

17-12
(36V)
+30V
R848 D865 D863
(24V)
+15V
To Pin 14 of Z801
R849 D860 D861
Figure 17-12 +30V/+15V Over Voltage Protect Circuit

(5.1V)
+12V
D854
+15V R877
D866
R873
0V
R879
Q853
0.7V D867
0V
R874
R880
R875 -14.9V Protect (active high)

To Pin 14 of Z801
-15V -14.3V Q854
R876 -15V
Figure 17-13 +15V/-15V Under Voltage Protect Circuit

17-13
+9V-1V 9.4V
R389 R390
6.2V 0V
Q352
6.8V
Q340
D315 0V CRT PROTECT
6.2V
R347 6.1V
Q341 R346
D341 0V
200V Protect (active high)
To Pin 14 of Z801
C340 R392
Figure 17-14 200V Under Voltage Protect Circuit

D471 R472
To X-RAY Q757From X-RAY
Pin 13 (Z801) Pin 9 of T461
(23V) C471
Figure 17-15 X-Ray Protect Circuit

(Located on Deflection/Power Board)
17-14
LAB 4
POWER SUPPLY SHUTDOWN CIRCUITS
SECTION 1
VOLTAGES UNDER NORMAL CONDITIONS
Place the unit in the service position by removing the chassis light box and place it on its side in an
upright position with the power cord up. (See FIG. 17-16) Connect a signal to the ANT1 input. You
may want to refer to the actual schematic diagram for a clearer understanding of the circuitry.
PROTECT CIRCUIT MEASUREMENTS:
1. Connect the (-) lead of the peak/hold meter to pin 17 of Z801 (See FIG. 17-16, #1) and record
the DC voltages on the following pins:
PIN 11)__________
PIN 13)__________
PIN 14)__________
PIN 15)__________
PIN 16)__________
RELAY CONTROL CIRCUIT MEASUREMENTS:
2. Locate Q843. (See FIG. 17-16, #2) Record the voltages on the following:
C__________
B__________
E__________
3. What does Q843 control, and how does it control it?
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
OVER CURRENT, OVER VOLTAGE, AND UNDER VOLTAGE PROTECT CIRCUIT

MEASUREMENTS:
4. Connect the (-) lead of the p/h meter to the (-) side of C882 (See FIG.17-16, #3).
5. Measure the voltage on the anode side of D865. (See FIG.17-16, #4)
Anode D865__________
17-15
6. Measure the voltage on the anode side of D860. (See FIG. 17-16, #5)
Anode D860__________
7. Measure the voltage on the collector of Q853. (See FIG. 17-16, #6)
Collector Q853__________
8. Measure the voltage on the anode side of D867. (See FIG. 17-16, #7)
Anode D867__________
10. Connect the (-) lead of the p/h meter to the (-) side of C310 (see FIG. 17-16, #9).
SECTION 2
VOLTAGES UNDER SHUTDOWN CONDITION
1. Locate the (X) pin (P415) and the (R) pin (P416) (See FIG. 17-16, #11)
2. While monitoring pins 13 and 16 of Z801 on the p/h meter, jumper pins (X) and (R) together.
3. After the shutdown, record the voltages on pins 13 and 16 of Z801. (See FIG. 17-16, #1)
PIN 13)__________
PIN 16)__________
The above exercise allows you to see what happens when the X-Ray protect circuit shuts down
the set.
4. How is this determined?
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
NOTE: SHUTDOWN OCCURS WHEN THE VOLTAGE INCREASES TO

APPROXIMATELY 25V.
17-16
5. While shorting the base of Q853 (See FIG. 17-16, #6) to ground, monitor and record the
collector voltage using the p/h meter.
6. What have you simulated by shorting the base to ground?
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
7. Why does a change occur on the collector and where is this change sensed?
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
8. Look on the schematic diagram labeled “Convergence Out/Power2”, in the upper right side.
Find D865 (zener diode) on the +30V supply line. How would you determine what the peak
voltage would be before the over voltage protect circuit would operate?
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
9. Look on the schematic diagram labeled “Convergence Out/Power2”, in the upper right side.
Find D860 (zener diode) on the +15v supply line. How would you determine what the peak
voltage would be before the over voltage protect circuit would operate?
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
10. Remember when you measured the anode sides of D865 and D860 earlier? Well, if the set, your
working on, is in shutdown mode, how would you determine if it was caused by over voltage on
the +30v or +15v lines?
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
17-17
11. While shorting the base of Q757 (See FIG. 17-16, #8) to ground, monitor and record the
collector voltage using the p/h meter.
12. What have you simulated by shorting the base to ground?
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
13. Measure the voltage drop across R7750 (See FIG. 17-16, #12), R7782 (See FIG. 17-16, #13)
and R7765 (See FIG. 17-16, #14).
R7750__________
R7782__________
R7765__________
14. List a procedure of how would you determine which one of the over current protect circuits
were causing the shutdown?
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
17-18
R7782 R7765
#14 R7750
#13
#12
Q757
#8 Q843
#2
D865 #4
Q853 C882
#6 #3
D867 D860
#7 #5
C310
#9
Z801 X R
#1 Q370 #11
#10
17
Figure 17-16
17-19
NOTES
17-20
SECTION XVIII
DYNAMIC FOCUS CIRCUIT
18-1
1. OUTLINE
2. H DYNAMIC FOCUS CIRCUIT
In TP48C51, a static focus system is employed in the projection
tube. 2-1. Theory of Operation
Degradation of the focus quality at peripheral screen is Fig. 18-1 shows a block diagram of the circuit which develops
improved by applying focus correction voltages (parabola an H parabora correction voltage.
voltages in H/V periods).
The dynamic focus circuit creates this focus correction
voltage and consists of an H and a V dynamic focus circuit.
To obtain a flat focus characteristics at center and peripheral

of the screen, the focus correction is carried out by applying
the H sync parabola correction voltage (efH=700 Vp-p) and
the V sync parabola correction voltage (eifv=300 Vp-p) to
the focus electrode in addition to the focus DC voltage of Ef
(=EHx0.27~0.29).
ef H
+ CO
ef V
H pulse Integrated Step-up
(AFC) circuit transformer
Copuling Focus
EF
capasitor electrode
ef H ef V
V dynamic
focus circuit EF
0
Fig. 18-1 Block diagram of H dynamic focus circuit
18-2
C1=n2Cs
2-2. Circuit Operation The H pulse is integrated with L450 and C1, and a sawtooth
The H pulse developed at pin 10 of the pulse transformer wave current of IC1 flows into C1.
T461 enters the integration circuit consisting of L450 and C1. Accordingly, a parabora voltage V1 integrated is developed
The C1 does not exist in the actual circuit as shown in a dotted across C1 and this is used as the input voltage (primary side
line. The C1 is an equivalent capacitance of the stray voltage) for the step-up transformer. A parabora voltage V2
capacitance of Cs in secondary side of the step-up transformer stepped-up and inverted is obtained at secondary side (F, P
T405 converted into the primary side and can be expressed terminals) of T400. This parabola voltage is mixed with the
as: V parabola voltage described under the V dynamic focus
circuit, and the mixed voltage is superimposed with the focus
DC voltage (about 9kV) through a coupling capacitor Co,
and supplied to the focus electrodes of three R, G, B tubes.
GREEN DRIVE
BLUE DRIVE
RED DRIVE
To
To
To
S
S
F
F
S
F
EF
From FBT
!
1V V2
V1
1H
F.P
L450
L401
2 9
T461
10
9 C1
Focus Pack
5 1:n 12
2
3 T400 C477
From v dynamic focus circuit
1
Fig. 18-2
18-3
3. V DYNAMIC FOCUS CIRCUIT

Fig. 18-3 shows the circuit which develops the V parabola
correction voltage.
Flyback pulse
Integrated Amplifier Rectification Deflection

circuit circuit block output
efH+efV
H dynamic
focus circuit
Sawtooth wave
CO
Coupling Focus
capacitor EF electrode
ef H
ef
V
EF
0
Fig. 18-3 Block diagram of V dyanamic focus circuit
18-4
3-2. Circuit Operation The parabola level of the V focus parabola output voltage can
A sawtooth wave voltage developed across (R305) in the V be adjusted by varying R369 and the DC voltage level by
output circuit is cut in its DC component and the AC varying R354.
components of the voltage is integrated into a parabola form The power for Q361 is obtained by rectifying collector pulse
by a mirror integrator in the first stage and amplified with a of the deflection output circuit with the rectification circuit
specified gain level set by R362/R361. The amplified parabola Z470. The rectification circuit Z470 is assembled as a separate
wave enters an op. amplifier in the next stage and again block in considering safety because of its high rectified
amplified. The op. amplifier works as an inverting amplifier output voltage of about 1000V.
and the gain is determined by (R368/R369)/R366. The
parabola voltage amplified in this way enters base of Q361,
amplified in an inverted form, and developed as the V focus
parabola voltage (300 Vp-p, DC component 60V). This
voltage is mixed with the H focus parabola voltage in passing
through R483, resulting in mixed parabora voltage consisting
of a H component of 700 Vp-p and a V component of 300 Vp-
p. Thus obtained mixed output is fed to the focus electrodes
of R, G, B projection tubes through the coupling capacitor
stated under 2-2.
18-5
H. deflection output circuit
Q360
V Coil
Q404
C306 Focus power supply lock

VCC GND VCC Z470
1 2 3 4 5 6 7 8 9
D305
R368 H. dynamic focus circuit

C362 R357
C361 R367 T400
R362 C363 12 2
R361 R480
Q301
Fig. 18-4 V output circuit
R369
R363 D364
R365 R366
R356 9 5
+12V
L401
18-6
C300 R360
C364
D360 F.P
R354 EF
!
F
To
RED DRIVE
S
F To
GREEN DRIVE
S
F
To
BLUE DRIVE
S

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NTDPJTV04

SERVICING THE N5SS

TOSHIBA AMERICA CONSUMER PRODUCTS, INC.

SERVICING TOSHIBA'S N5SS TELEVISION CHASSIS

TOSHIBA AMERICA CONSUMER PRODUCTS, INC.

SECTION I 6. ON SCREEN FUNCTION ....................... 3-6

Digital data which is passed along the bus is received by

Typical Chassis Exam ples

5-1. Front View

Press to open the door. Remote sensor location

Behind the door

VIDEO/AUDIO INPUT MENU buttom

* These buttons have dual functions.

S-VIDEO INPUT jack

AUDio* SET UP*

To operate buttons inside the cover,

* These functions do not have

Basic Circuit Operation

Figure 1-8 Audio Signal Flow Block Diagram

Figure 1-9 Power Supply/Protection Block Diagram

Figure 1-10 Horizontal and Vertical Deflection Block Diagram

18 KEY B 35 IC501 H001

Figure 1-11 I2C Communication Block Diagram

Figure 1-13 Convergence Block Diagram

3. In the Picture Menu, What is Color Temperature?

5. In the Setup Menu, What is Favorite Channel?, What is Channel Lock?

8. Reattach the control panel to the light box.

9. Remove the six screws on the front of the light box.

10. Remove the three screws on the back of the cabinet.

2. Is there a convergence board in this unit?

3. How does this convergence setup differ from previous models?

2. Use the test signals for troubleshooting.

3. Use the set’s self diagnostic feature.

6. What happened to the cross hairs?

7. If something did happen to the cross hairs, why did it happen?

9. If there is video on the screen, where does it come from?

10. Unplug the video cable.

3. Select AUD on the remote control.

7. What happened to audio?

8. If something did happen to the audio, why did it happen?

9. Push the 8 button to turn off the audio test signal.

1. Push the 9 button to activate the self diagnostic feature.

2. What does POWER indicate?

3. What does BUS LINE indicate?

4. What does BUS CONT indicate?

5. What does BLOCK indicate?

6. Push the EXIT button to exit the self diagnostic feature.

8. Push MENU on the control panel to display the registers.

9. Push 9 to activate the self diagnostic feature.

10. Is the display different from the previous display. ______

11. If it is, explain why.

13. Push MENU on the control panel to display the registers.

H002 - IF/MTS/A.PRO Module MVUS34S

Fig. 2-1 Block diagram

1-2. Major Features

MPX TV DAC-out1 TV DAC-out2

Monitor the input Stereo 0V SAP 0V OFF 0V RF1 0V

TV waveform detection TV waveform detection

Fig. 2-2 Block diagram of MVUS34S