Unit I Coa

Computer Organization and Architecture 1
GUDLAVALLERU ENGINEERING COLLEGE

(An Autonomous Institute with Permanent Affiliation to JNTUK, Kakinada)
Seshadri Rao Knowledge Village, Gudlavalleru – 521 356
Department of Computer Science and Engineering
HANDOUT
on
COMPUTER ORGANIZATION AND ARCHITECTURE
II Year - II Semester UNIT-I CSE

Vision
To be a Centre of Excellence in computer science and engineering education and training to
meet the challenging needs of the industry and society.
Mission
 To impart quality education through well-designed curriculum in tune with the growing
software needs of the industry.
 To be a Centre of Excellence in computer science and engineering education and training to
meet the challenging needs of the industry and society.
 To serve our students by inculcating in them problem solving, leadership, teamwork skills
and the value of commitment to quality, ethical behavior & respect for others.
 To foster industry-academia relationship for mutual benefit and growth

Program Educational Objectives
• Identify, analyze, formulate and solve Computer Science and Engineering problems both
independently and in a team environment by using the appropriate modern tools.
• Manage software projects with significant technical, legal, ethical, social, environmental and
economic considerations
• Demonstrate commitment and progress in lifelong learning, professional development,

leadership and Communicate effectively with professional clients and the public.

HANDOUT ON COMPUTER ORGANIZATION AND ARCHITECTURE
Class & Sem. : II B.Tech – II Semester Year: 2016-17

Branch : CSE Credits: 3
========================================================================
1. Brief History and Scope of the Subject
The term Computer Architecture was first defined in the paper by Amdahl, Blaauw and
Brooks of IBM Corporation announcing IBM System/360 computer family on April 7,1964. On that
day IBM Corporation introduced, in the words of IBM spokesman, "the most important product
announcement that this corporation has made in its history". There were six models introduced
originally, ranging in performance from 25 to 1. Six years later this performance range was increased
to about 200 to 1.
This was the keyfeature which prompted IBM's effort to design architecture for a new line of
computers that are to be code compatible with each other. The recognition that architecture and
implementation could be separated and that one need not imply the other led to establishment of a
common System/360 machine architecture implemented in the range of models.
Recent Developments
 machine level representation of data
 assembly level machine organization
 memory system organization and architecture
 interfacing and communication
2. Pre-Requisites
 Binary arithmetic operations
 Operations of MUX, DEMUX, ENCODER, DECODER and Registers.
3. Course Objectives
 To familiarize with organizational aspects of memory, processor and I/O
4. Course Outcomes
Students will be able to
Co1: Understand different types of instructions.
Co2: Differentiate micro-programmed and hard-wired control units.
Co3: Represent data in fixed and floating point formats.
Co4: Analyze the performance of the hierarchical organization of memory
Co5: Summarize different data transfer techniques.
Co6: Demonstrate the use of pipelining and multiprocessor
5. Program Outcomes
Graduates of the Computer Science and Engineering Program will have ability to
a. apply knowledge of computing, mathematics, science and engineering fundamentals to
solve complex engineering problems.

b. formulate and analyze a problem, and define the computing requirements appropriate to
its solution using basic principles of mathematics, science and computer engineering.
c. design, implement, and evaluate a computer based system, process, component, or
software to meet the desired needs.
d. design and conduct experiments, perform analysis and interpretation of data and provide
valid conclusions.
e. use current techniques, skills, and tools necessary for computing practice.
f. understand legal, health, security and social issues in Professional Engineering practice.
g. understand the impact of professional engineering solutions on environmental context and
the need for sustainable development.
h. understand the professional and ethical responsibilities of an engineer.
i. function effectively as an individual, and as a team member/ leader in accomplishing a
common goal.
j. communicate effectively, make effective presentations and write and comprehend
technical reports and publications.
k. learn and adopt new technologies, and use them effectively towards continued
professional development throughout the life.
l. understand engineering and management principles and their application to manage
projects in the software industry.
6. Mapping of Course Outcomes with Program Outcomes:
a b c d e f g h i j k l
CO1 2 2
CO2 2
CO3 3
CO4 1
CO5 2 2
CO6 3
7. Prescribed Text Books

1. M. Moris Mano, Computer Systems Architecture, Pearson/PHI, 3rd edition
8. Reference Text Books
1. Carl Hamacher, Zvonks Vranesic, SafeaZaky, Computer Organization, McGraw Hill, 5th
edition.
2. William Stallings, Computer Organization and Architecture, Pearson/PHI, 6th edition.

3. John L. Hennessy and David A. Patterson, Computer Architecture a quantitative approach,

Elsevier, 4th Edition.
9. URLs and Other E-Learning Resources
Journals
 History of computing
 Computational science & Engineering
 Computer & Digital techniques.
URL’s
1. http://ieeexplore.ieee.org/servlet/opac?punaumber=85
6. Digital Learning Materials:

1. SONET volumes -8
2. Computer Architecture --38 volumes
By Prof.Anshul Kumar
Dept.of Comp.sc.&Engg
I.I.T. Delhi.
3. Computer Organization –33 volumes
By Prof. S.RAMAN
Dept.of Comp.sc.&Engg
I.I.T. MADRAS.
7. Lecture Schedule / Lesson Plan

No. of Periods
Topic
Theory Tutorial
UNIT –1: Introduction
Computer Types, Functional Units 1
Computer Registers, Register Transfer Languages 1
Register Transfer, Bus and Memory Transfers 1 1
Arithmetic Micro operations 2
Logic Micro operations, 1
Shift Micro operations, Arithmetic logic shift unit. 2
Instruction codes 1
1
Computer Instructions 1
Instruction Cycle 1
Memory– Reference Instructions 1
Input – Output and Interrupt, Stack Organization 2 1
Instruction Formats 1

Addressing Modes 1
RISC 1
Total 17 3
UNIT – 2: Micro Programmed Control
Control Memory 1
Address Sequencing 1
Design of Control Unit- Hard Wired Control, Micro Programmed 1
2
Control
1
Total 4 2
UNIT – 3: Computer Arithmetic
Data Representation, Fixed Point, Floating Point 1
Addition and Subtraction 1 1
Multiplication Algorithms 2
Division Algorithms 2
Floating – Point Arithmetic Operations 2 1
Decimal Arithmetic Operations 3
Total 11 2
UNIT – 4: Memory
Memory Hierarchy 1
Main Memory 1 1
Auxiliary Memory 1
Associative Memory 1
Cache Memory 2
1
Virtual Memory 1
Memory Management Hardware 1
Total 8 2
UNIT – 5: Input-Output Organization
Peripheral Devices, Input-Output Interface 1
Asynchronous data transfer 1 1
Modes of Transfer, Priority Interrupt 2
Direct memory Access 1
1
Input –Output Processor (IOP), Serial communication 2
Total 7 2
UNIT – 6: Parallel Processing
Parallel Processing 1
Pipelining 1
1
Arithmetic Pipeline, Instruction Pipeline, RISC Pipeline 3
Multi Processors: Characteristics of Multiprocessors 1
Interconnection Structures 1
Inter Processor Arbitration 1
1
Inter Processor Communication and Synchronization 1
Cache Coherence. 1
Total 9 2
Total No.of Periods: 56 15
8. Seminar Topics:
Booths multiplication algorithm
Inter Processor Arbitration

UNIT – I
Objective:
 To explore To familiarize with organizational aspects of memory.
Syllabus:
Computer Types, functional units, Computer Registres, Register Transfer language, Register Transfer
Bus and memory transfers, Arithmetic, logic and shift micro-operations, Arithmetic logic shift unit.
Instruction codes, Computer instructions, Instruction cycle.
Memory – Reference Instructions, Input – Output and Interrupt, STACK organization, Instruction
formats, Addressing modes, RISC
Learning Outcomes:
At the end of the unit student will be able to:

1. Understand Different Types Of Instructions.
2. Describe about Instruction Cycle.
3. Describe about Different Types of Addressing Modes.
Learning Material
Computer Types
 Computer is a fast electronic calculating machine which accepts digital input, processes it
according to the internally stored instructions (Programs) and produces the result on the
output device.
 The computers can be classified into various categories as given below.
1. Micro Computer
2. Laptop Computer
3. Work Station
4. Super Computer
5. Main Frame
6. Hand Held
7. Multi core

1. Micro Computer: A personal computer is designed to meet the computer needs of an individual,
providing access to a wide variety of computing applications, such as word processing, photo editing,
e-mail, and internet.
2. Laptop Computer: A portable, compact computer that can run on power supply or a battery unit.
All components are integrated as one compact unit. It is generally more expensive than a comparable
desktop. It is also called a Notebook.
3. Work Station: Powerful desktop computer designed for specialized tasks. Generally used for tasks
that requires a lot of processing speed. Can also be an ordinary personal computer attached to a LAN
(local area network).
4. Super Computer: A computer that is considered to be fastest in the world. It is used to execute tasks
that would take lot of time for other computers. For Eg: Modeling weather systems, genome
sequence, etc.
5. Main Frame: Large expensive computer capable of simultaneously processing data for hundreds or
thousands of users. Used to store, manage, and process large amounts of data that need to be reliable,
secure, and centralized.
6. Hand Held: It is also called a PDA (Personal Digital Assistant). A computer that fits into a pocket,
runs on batteries, and is used while holding the unit in your hand. Typically used as an appointment
book, address book, calculator and notepad.
7. Multi Core: Have Multiple Cores – parallel computing platforms. Many Cores or computing
elements are present in a single chip. Typical Examples: Sony Play station, Core 2 Duo, i3, i7 etc.
Functional Unit
 A computer in its simplest form comprises of five functional units namely input unit, output
unit, memory unit, arithmetic & logic unit and control unit. Below figure depicts the
functional units of a computer system.

Arithmetic &
Input Unit
Logic Unit
Memory Unit
Output Unit Control Unit
I/O CPU / Processor
Figure 1: Basic functional units of a computer

1. Input Unit: Computer accepts encoded information through input unit. The standard input device is
a keyboard. Whenever a key is pressed, keyboard controller sends the code to CPU/Memory.
Examples include Mouse, Joystick, Tracker ball, Light pen, Digitizer, Scanner etc.
2. Output Unit: Computer after computation returns the computed results, error messages, etc. via
output unit. The standard output device is a video monitor, LCD/TFT monitor. Other output devices
are printers, plotters etc.
3. Memory Unit: Memory unit stores the program instructions (Code), data and results of
computations etc.
Memory unit is classified as:
 Primary /Main Memory
 Secondary /Auxiliary Memory
4. Arithmetic and logic unit: ALU consist of necessary logic circuits like adder, comparator etc., to
perform operations of addition, multiplication, comparison of two numbers etc.
5. Control Unit: Control unit co-ordinates activities of all units by issuing control signals. Control
signals issued by control unit govern the data transfers and then appropriate operations take place.
Control unit interprets or decides the operation/action to be performed.
Computer registers
 Computer registers are designated by capital letters (sometimes followed by numerals) to
denote the function of the register.

 For example, the register that holds an address for the memory unit is usually called a
memory address register and is designated by the name MAR.
 Other designations for registers are PC (for program counter), IR (for instruction register),
and R1 (for processor register).
 The individual flip-flops in an n-bit register are numbered in sequence from 0 through n - 1,
starting from 0 in the rightmost position and increasing the numbers toward the left.
 The following diagram shows the representation of registers.
Figure 2: Block diagram of register

Table 1: List of Registers for the Basic Computer

Figure 3: Basic computer registers and memory

S2
S1 BUS
S0
Memory Unit
7
4096 × 16
Address
Write Read
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR
E
Adder and 4
AC
Logic
LD INR CLR
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit Common Bus
Figure 4: Basic Computer Register Connected to a Common BUS

 The outputs of seven registers and memory are connected to the common bus. The specific
output that is selected for the bus lines at any given time is determined from the binary value
of the selection variables S2, S1, and S0.

 The number along each output shows the decimal equivalent of the required binary selection.
For example, the number along the output of DR is 3.
 The 16-bit outputs of DR are placed on the bus lines when S2S1 S0 = 011 since this is the
binary value of decimal 3. The lines from the common bus are connected to the inputs of each
register and the data inputs of the memory.
 The particular register whose LD (load) input is enabled receives the data from the bus during
the next clock pulse. The memory receives the contents of the bus when its write pin is
enabled.
 The memory places its 16-bit output onto the bus when the read pin is enabled and S2S1S0=11.
 Four registers, D R, AC, IR, and TR, have 16 bits each. Two registers, AR and PC, have 12
bits each since they hold a memory address.
 When the contents of AR or PC are applied to the 16-bit common bus, the four most
significant bits are set to 0's. When AR or PC receives information from the bus, only the 12
least significant bits are transferred into the register.
 The input register INPR and the output register OUTR have 8 bits each and communicate
with the eight least significant bits in the bus.
 INPR receives a character from an input device to provide information onto the bus which
inturn is then transferred to AC.
 OUTR receives a character from AC and delivers it to an output device. There is no transfer
from OUTR to any of the other registers.
 Five registers have three control inputs: LD (load), INR (increment), and CLR (clear). This
type of register is equivalent to a binary counter with parallel load and synchronous clear.
Micro operation: is an elementary operation performed on information stored in one or more

registers.
Eg: Shift, Count, Clear and Load.
Register Transfer Language
 The symbolic notation used to describe the Micro operation transfers among registers is called
a Register Transfer Language.
 Information transferred from one register to another register is designed in symbolic form by
means of replacement operator().
 The statement R2  R1 denotes a transfer of the contents of register R1 into register R2.
 If we want to transfer only under a predefined condition, this can be shown by means of if-
then statement.
if(p = 1) then R2  R1

where p is a control signal generated in the control section.

 A Control function is a Boolean variable that is equal to 0 or 1.
 The control function included in the statement is represented as follows.
p: R2  R1
 Here the transfer operation is performed by hardware only if p = 1.
 Every statement written in a register transfer notation implies a hardware construction for
implementing the transfer.
p Load
Control Circuit R2 Clock
/n
R1
(a) Block Diagram
t t+1
Clock
Load
(b) Timing Diagram
Figure 5: Transfer from R1 to R2 when p =1

The basic symbols of the register transfer notation are listed in the following table.
Table 2: Basic Symbols for Register Transfer
S.No Symbol Description Example
1 Letters (and Numbers) Denotes a register MAR, R2
2 Parenthesis ( ) Denotes a part of register R2(0-7), R2(L)
3 Arrow  Denotes transfer of information R2  R1
4 Comma , Separates two microoperations R2  R1, R1  R2

* A comma is used to separate two or more operations that are executed at the same time.
Eg: R2  R1, R1  R2
 The above statement denotes an operation that exchanges the content of two registers during
one common clock pulse.
Bus Transfer
 Digital computers have many registers, and paths must be provided to transfer information
from one register to another register.
 The no. of wires will be excessive if separate lines are used between each registers and all
other registers in the system.
 A Bus structure consists of a set of common lines, one for each bit of a register, through
which binary information is transferred one at a time.
 Control signal determines which register is selected by the bus during each particular register
transfer.
 The construction of a bus system for 4 registers is shown in the following figure.
Figure 6: Bus system for four registers

 Here each register has 4 bits, numbered 0 through 3.
 The bus consists of four 4×1 multiplexers, each having four data inputs, 0 through 3, and two
selection inputs S1 and S0.

 The selection lines choose the four bits of one register and transfer them into the 4-line
common bus.
 When S1S0 = 00, then 0 data input of all four multiplexers are selected and applied to output
that form the bus.
 The following table shows the register that is selected by the bus for each of the four possible
binary values of selection lines.
Table 3: Selection of Registers
S1 S2 Register Selected
0 0 A
0 1 B
1 0 C
1 1 D
 The transfer of information from a bus into one of many registers can be accomplished by
connecting the bus lines to inputs of all destination registers and activating the load control of
particular destination register.
Eg: BUS  C
 In the above statement the content of register C is placed onto BUS
Eg: R1  BUS
 In the above statement the content of register C, placed onto BUS is loaded into Register
R1by activating the load pin.
Three( Tri) state Bus Buffer

 A Bus system can be constructed with three-state gates instead of multiplexers.
 A three-state gate is a digital circuit that exhibits three states.
 Two of the states are signals equivalent to logic 1 or 0 as a conventional gate.
 The third state is a high-impedance state. The high-impedance behaves like an open circuit.
 The graphical symbol of a three state buffer is shown in the following figure.
Figure 7: Graphic symbol of a three state buffer

 In the above diagram, control input determines the output state.

 When the control input is equal to 1, the output is enabled like as any conventional buffer.
 When the control input is equal to 0, the output is disabled and the gate goes to a high-
impedance state.
 The following figure shows construction of a bus system with Three state Bus Buffer
Figure 8: Bus Line with three state buffer

 Here the output of 4 buffers are connected together to form a single bus line.
 The control inputs to the buffers determine which of the four normal inputs will communicate
with the bus line.
 No more than one buffer may be in the active state at any given time.
 Only one three-state buffer has access to the bus line while all other buffers are maintained in
high impedance state.
 With the help of the decoder, three state buffers are controlled.
 When the enable input of the decoder is 0, all of its four outputs are 0, and the bus line is in a
high-impedance state because all four buffers are disabled.
 When the enable input is active, i.e. 1, one of the three-state buffers will be active, depending
on the select lines of the decoder.
 To construct a common bus for four registers of n bits each using three-state buffers, we need
n circuits with four buffers in each circuit.
 Each group of four buffers receives one significant bit from the four registers.
 Each common output produces one of the lines for the common bus for a total of n lines.
Table 4: Active Three State Buffer with respect to enable input
E S 1 S0 Active Three State Buffer

0 X X High impedance state
1 0 0 A
1 0 1 B
1 1 0 C
1 1 1 D
Memory Transfer
 The transfer of information from a memory word symbolized by M, to the outside
environment is called a read operation.
 The transfer of new information to be stored into the memory is called a write operation.
 The particular memory word among the many available is selected by the memory address
during the transfer.
 Consider a memory unit that receives the address from a register, called the address register,
symbolized by AR.
 The data is transferred to another register, called the data register, symbolized by DR.
 The memory read operation can be stated as follows
Read: DR M [AR]
 Here data is transferred into DR from the memory location specified by AR.
 The memory write operation can be stated as follows
Write: M [AR] DR
 Here write operation transfers the content of a data register to a memory word M specified by
the address in AR.
The micro operations most often encountered in digital computers are classified into four
categories:
1. Register transfer micro operations transfer binary information from one register to another.
2. Arithmetic micro operations perform arithmetic operation on numeric data stored in registers.
3. Logic micro operations perform bit manipulation operations on non-numeric data stored in
registers
4. Shift micro operations perform shift operations on data stored in registers
Arithmetic micro operations

 The basic arithmetic microoperations are addition, subtraction, increment and decrement.
Add Microoperation:
R3 ← R1 + R2
 The above statement states that the contents of register R1 are added to the contents of
register R2 and the sum transferred to register R3.
Subtract Microoperation:
R3 ← R1 + R2+ 1
 In the above statement R2 is the symbol for the 1’s complement of R2. Adding 1 to the 1’s
complement produces the 2’s complement. Adding the contents of R1 to the 2’s complement
of R2 is equivalent to R1 – R2.
 The increment and decrement microoperations are symbolized by plus-one and minus-one
operations, respectively.
Table 5: Arithmetic Microoperations
Symbolic designation Description

R3 ←R1 + R2 Contents of R1 plus R2 transferred to R3
R3 ←R1−R2 Contents of R1 minus R2 transferred to R3
R2 ←R2 Complement the contents of R2 (1’s complement)
R2 ←R2 + 1 2’s complement the contents of R2 (negate)
R3 ←R1 + R2 + 1 R1 plus the 2’s complement of R2 (subtraction)
R1 ←R1 + 1 Increment the contents of R1 by one
R1 ←R1 – 1 Decrement the contents of R1 by one
Binary Adder
 To implement the add microoperation with hardware, we need the registers that hold
the data and the digital component that performs the arithmetic addition.
 The binary adder is constructed with full-adder circuits connected in cascade, with the
output carry from one full-adder connected to the input carry of the next full-adder.
Figure 9: 4-bit binary adder

 The S outputs of the full-adders generate the required sum bits.

 An n-bit binary adder requires n full-adders. The output carry from each full-adder is
connected to the input carry of the next-higher-order full-adder.
Binary Adder-Subtractor
 The addition and subtraction operations can be combined into one common circuit by
including an exclusive-OR gate with each full-adder.
 A 4-bit adder-subtractor circuit is shown in the following figure.
Figure 10: Adder-subtractor

 In the above figure, mode input M controls the operation.
 When M = 0 the circuit is an adder and when M = 1 the circuit becomes a subtractor.
 Each exclusive-OR gate receives input M and one of the inputs B. When M = 0, we
have B0 = B. The full-adders receive the value of B, the input carry is 0, and the
circuit performs A+B.
 When M = 1, we have B1 = B' and C0 = 1. The B inputs are all complemented and 1
is added through the input carry. The circuit performs the operation A+2's
complement of B.
Binary lncrementer
 The increment microoperation adds one to a number in the register.
 The diagram of a 4-bit incrementer circuit is shown below. One of the inputs of the
least significant half-adder (HA) circuit is connected to logic-1 and the other input is
connected to the least significant bit of the number to be incremented.

Figure 11: 4-Bit Binary Incrementer

 The output carry from one half-adder is connected to one of the inputs of the next-
higher-order half-adder. The circuit receives the four bits from A0 through A3, adds
one to it, and generates the incremented output S0 through S3.
Arithmetic Circuit
 The basic component of an arithmetic circuit is the parallel adder. By controlling the
data inputs to the adder, it is possible to obtain different types of arithmetic
operations.
 The diagram of a 4-bit arithmetic circuit is as shown in the following figure. It has
four full-adder circuits that constitute the 4-bit adder and four multiplexers for
choosing different operations.
 There are two 4-bit inputs A and B and a 4-bit output D. The four inputs from A go
directly to the X inputs of the full adder. Each of the four inputs from B are connected
to the data inputs of the multiplexers.
 The four multiplexers are controlled by two selection inputs, S1 and S0.

Figure 12: 4-bit arithmetic circuit

 The input carry Cin goes to the carry input of the FA in the least significant position.
The other carries are connected from one stage to the next.
 The output of the binary adder is calculated from the following arithmetic sum:
D =A+ Y + Cin
 where A is the 4-bit binary number at the X inputs and Y is the 4-bit binary number at
the Y inputs of the binary adder. Cin is the input carry, which can be equal to 0 or 1.
 By controlling the value of Y with the two selection inputs S1 and S0 and making Cin
equal to 0 or 1, it is possible to generate the eight arithmetic microoperations listed in
the following table.

Table 6: Arithmetic Circuit Function Table
Logic Microoperations
 Logic microoperations specify binary operations for strings of bits stored in registers. These
operations consider each bit of the register separately and treat them as binary variables.
 For example, the exclusive-OR microoperation on the contents of two registers R 1 and R2 is
symbolized by the statement.
P: R1  R1 R2
 The above specifies a logic microoperation to be executed on the individual bits of the
registers provided that the control variable P = 1.
 As a numerical example, assume that each register has four bits. Let the content of R1 be
1010 and the content of R2 be 1100. The exclusive-OR microoperation stated above
symbolizes the following logic computation:
1010 Content of R1
1100 Content of R2
0110 Content of R1 if P = 1
 The symbol V will be used to denote an OR microoperation and the symbol  to denote an
AND microoperation. The complement microoperation is the same as the 1's complement and
uses a bar on top of the symbol that denotes the register name.
List of Logic Microoperations
 There are 16 different logic operations that can be performed with two binary variables. They
can be determined from all possible truth tables obtained with two binary variables.

Table 7: Sixteen Logic Microoperations
 In the following table, each of the 16 columns F0 through F15 represents a truth table of one
possible Boolean function for the two variables x and y. Note that the functions are
determined from the 16 binary combinations that can be assigned to F.
Table 8: Truth Tables for 16 Functions of Two Variables
Hardware Implementation for Logic Microoperations

 The hardware implementation of logic microoperations requires that logic gates be
inserted for each bit or pair of bits in the registers to perform the required logic
function.

 The following figure shows one stage of a circuit that generates the four basic logic
mnicrooperations. It consists of four gates and a multiplexer.
 The outputs of the gates are applied to the data inputs of the multiplexer. The two
selection inputs S1 and S0 choose one of the data inputs of the multiplexer and direct
its value to the output.
Figure 13: One stage of logic circuit

Applications of logic microoperations
1. selective-set
 The selective-set operation sets to 1 the bits in register A where there are
corresponding 1's in register B. It does not affect bit positions that have 0's in B. The
following numerical example clarifies this operation:
1010 A before
1100 B (logic operand)
1110 A after
2. selective-complement
 The selective-complement operation complements bits in A where there are
corresponding l's in B. It does not affect bit positions that have 0's in B.
For example:
1010 A before
0110 A after

3. Selective-clear
 The selective-clear operation clears to 0 the bits in A only where there are
corresponding 1's in B.
For example:
1010 A before
0010 A after
4. mask
 The mask operation is similar to the selective-clear operation except that the bits of A
are cleared only where there are corresponding 0'sin B. The mask operation is an
AND micro operation as seen from the following numerical example:
1010 A before
1000 A after masking
5. Insert
 The insert operation inserts a new value into a group of bits.
 This is done by first masking the bits and then ORing them with the required value.
 For example, an A register contains eight bits, 0110 1010. To replace the four
leftmost bits by the value 1001.
First mask the four unwanted bits.
0110 1010 A before masking
0000 1111 B (mask)
0000 1010 A after masking
Now insert the new value.
0000 1010 A before insert
1001 0000 B (insert)
1001 1010 A after insertion
**The mask operation is an AND microoperation and the insert operation is an OR
microoperation.
6. clear
 The clear operation compares the words in A and B and produces an all 0's result, if
the two numbers are equal.

 This operation is achieved by an exclusive-OR microoperation as shown by the

following example.
1010 A
1010 B
0000 A AB
Shift Microoperations
 Shift rnicrooperations are used for serial transfer of data.
 They are also used in conjunction with arithmetic, logic, and other data-processing operations.
 The contents of a register can be shifted to the left or the right.
 There are three types of shifts:
1. Logical Shift
2. Circular Shift
3. Arithmetic Shift
1. Logical Shift
 A logical shift is one that transfers 0 through the serial input to fill the vacancy created by
shift operation.
 The symbols shl is used for logical shift-left rnicrooperation.
Shr is used for shift-right rnicrooperation.
shl: Example: R1 shl R1
the above statement left shifts the content of register R1 by 1-bit.
Example: R1 = 0110
After performing shift left, R1 has the content 1100
shr: Example: R1 shr R1
the above statement right shifts the content of register R1 by 1-bit.
Example: R1 = 1100
After performing shift left, R1 has the content 0110
2. Circular Shift
 The circular shift also known as a rotate operation.
 It circulates the bits of the register around the two ends without loss of information.
 The symbols cil used for logical circular shift-left rnicrooperation.
cir used for circular shift-right rnicrooperation.
cil: Example: R1 cil R1
the above statement specifies circular shift left of the content of register R1.

Here all the bits are shifted one bit position to LEFT, the Left most bit (MSB) was circulated
to Right most bit (LSB).
Example: R1 = 1011
After performing circular shift left, R1 has the content 0111
cir: Example: R1 cir R1
the above statement specifies circular shift right of the content of register R1.
Here all the bits are shifted one bit position to RIGHT, the Right most bit (LSB) was
circulated to Left most bit (MSB).
Example: R1 = 1011
After performing circular shift right, R1 has the content 1101
3. Arithmetic Shift
 An arithmetic shift is a microoperation that shifts a signed binary number to the left or right.
 After the shift microoperation the sign of the number is to be restored.
 The symbols ashl used for logical arithmetic shift-left rnicrooperation.
ashr used forarithmetic shift-right rnicrooperation
ashl: Example: R1 ashl R1
the above statement specifies arithmetic shift left of the content of register R1
Here all the bits except the MSB, shift one bit position to LEFT.The second Left most bit was
discarded and Right most bit (LSB) was loaded by 0.
Example: R1 = 1011
After performing arithmetic shift left, R1 has the content 1110
ashr: Example: R1 ashr R1
the above statement specifies arithmetic shift right of the content of register R1
Here all the bits shifted one bit position to RIGHT. The Left most bit (MSB) remains same.
Example: R1 = 1011
After performing arithmetic shift right, R1 has the content 1101
Table 8: Shift Microoperations
Symbolic designation Description
R ← shl R Shift-left register R

R ← shr R Shift-right register R
R ← cil R Circular shift-left register R
R ← cir R Circular shift-right register R
R ← ashl R Arithmetic shift-left R
R ← ashr R Arithmetic shift-right R

Hardware Implementation for Shift Microoperations

 A combinational circuit shifter can be constructed with multiplexers as shown in
figure.
Figure 14: 4-bit combinational circuit shifter

** Here H0 bit is considered as MSB and H3 bit is considered as LSB.
 The 4-bit combinational circuit shifter uses four multiplexers, each of 2X1.
 The 4-bit shifter has four data inputs, A0 through A3, and four data outputs H0 through
H3.
 There are two serial inputs, one for shift left (IL) and the other for shift right (IR).
 When the selection input S = 0, the input data are shifted right (down in the diagram).
 When S = 1, the input data are shifted left (up in the diagram).

 The above function table shows which input goes to each output after the shift.
 A shifter with n data inputs and n data outputs requires n multiplexers each of 2X1.
Arithmetic Logic Shift Unit
 Instead of having individual registers performing the microoperations directly, computer
systems employ a number of storage registers connected to a common operational unit called
an arithmetic logic unit, abbreviated ALU.
 To perform a microoperation, the contents of specified registers are placed in the inputs of the
ALU. The ALU performs an operation and the result of the operation is then transferred to a
destination register.
 The ALU is a combinational circuit, so that the entire register transfer operation from the
source registers through the ALU and into the destination register can be performed during
one clock pulse period.
 The arithmetic, logic, and shift circuits can be combined into one ALU with common
selection variables.
 One stage of an arithmetic logic shift unit is shown in the following figure.
Figure 15: One stage of Arithmetic Logic Shift Unit

 Inputs Ai and Bi are applied to both the arithmetic and logic units.
 A particular microoperation is selected with inputs S1 and S0.
 A 4 x 1 multiplexer at the output chooses between an arithmetic output in Di and a logic
output in Ei.
 The data in the multiplexer are selected with inputs S3 and S2.The other two data inputs to the
multiplexer receive inputs Ai-1 for the shift-right operation and Ai+1 for the shift-left operation.
 The circuit whose one stage is specified in the above figure provides eight arithmetic
microoperation, four logic microoperations, and two shift microoperations.
 Each operation is selected with the five variables S3, S2, S1, S0 and Cin The input carry Cin is
used for arithmetic operations only.
 The first eight are arithmetic microoperations, which are selected with S3S2 = 00.
 The next four are logic microoperations, which are selected with S3S2 = 01.
 The input carry has no effect during the logic microoperations and is marked with don't-care
x.
 The last two operations are shift microoperations and are selected with S3S2 = 10 for shift
right microoperation and S3S2=and 11 for shift left microoperation. The other three inputs
have no effect on the shift.
Table 9: Function Table for Arithmetic Logic Shift Unit

Instruction Codes
 An instruction code is a group of bits which instructs the computer to perform certain
operation.
 Instructions are encoded as binary instruction codes. Each instruction code contains
a operation code, or opcode, which designates the overall purpose of the instruction (e.g. add,
subtract, move, input, etc.).
 The number of bits allocated for the opcode determines how many different instructions the
architecture supports.
 In addition to the opcode, many instructions also contain one or more operands, which
indicate where in registers or memory the data required for the operation is located.
 For example, an add instruction requires two operands, and a not instruction requires one.
15 12 11 65 0
+-----------------------------------+
| Opcode | Operand |Operand |
+-----------------------------------+
 Suppose all instruction codes of a hypothetical accumulator-based CPU are exactly 16 bits. A
simple instruction code format could consist of a 4-bit operation code (opcode) and a 12-bit
memory address.
15 12 11 0
+-----------------------+
| Opcode | Address |
+-----------------------+
Stored Program Organization
 The simplest way to organize a computer is to have one process register and an instruction
code formats with two parts.
 The first part specifies the operation to be performed and the second specifies the address.
 The instructions are stored in one section of the memory and the data is stored in the another
section.
 The figure considers the memory of size 4096 x 16. The number of Address lines required to
represent the 4096 words are 12 because 4096=212 . The number of data lines required are 16.

Figure 16: Stored program organization

Instruction Format
 A 16 bit instruction code format could consist of a 4-bit operation code (opcode) and a 12-bit
memory address, where the 4 bits are divided into 2 parts as shown in the figure below.
 The bits 12-14 represent the operation code and the 15th bit which is represented with I states
whether the given address is Direct or Indirect.
Figure 17: Instruction format

 If the value of I = 0 then the given address is Direct address and if the value of I = 1 then the
given address is Indirect address.
 Direct : Instruction code contains address of operand.
 Immediate : Instruction code contains operand
 Indirect : Instruction code contains address of address of operand.
 Effective address = actual address of the data in memory.

Figure 18: Demonstration of direct and indirect address

Example: The following examples use the following piece of computer memory.
Computer Instructions
The basic computer has three instruction code formats:
1. Memory Reference Instructions
2. Register Reference Instructions
3. Input / Output Instructions
1. Memory Reference Instructions
In Memory reference instruction:
 First 12 bits(0-11) specify an address.
 Next 3 bits specify operation code (opcode) and can range from 000 to 110.
 Left most bit specify the addressing mode I
 I = 0 for direct address
 I = 1 for indirect address

 The address field is denoted by three x’s (in hexadecimal notation) and is equivalent to 12-bit
address.
 When I = 0, the last four bits of an instruction have a hexadecimal digit equivalent from 0 to 6
since the last bit is zero (0).
 When I = 1 the last four bits of an instruction have a hexadecimal digit equivalent from 8 to E
since the last bit is one (1).
Figure 19: Memory - reference instruction format

Table 10: Basic Computer Instructions for Memory Reference Instructions
Hexadecimal code
Symbol Description
I=0 I=1
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx ADD memory word to AC
LDA 2xxx Axxx LOAD Memory word to AC
STA 3xxx Bxxx Store content of AC in memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and Skip if zero
2. Register Reference Instructions

In Register Reference Instruction:
 First 12 bits (0-11) specify the register operation.
 The next three bits equals to 111 specify opcode.
 The last mode bit of the instruction is 0.
 Therefore, left most 4 bits are always 0111 which is equal to hexadecimal 7.
Figure 20: Register - reference instruction format

Table 11: Basic Computer Instructions for Register - reference instructions
Symbol Hexadecimal code Description

CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC

CME 7100 Complement E

CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction is AC is negative
SZA 7004 Skip next instruction is AC is 0
SZE 7002 Skip next instruction is E is 0
HLT 7001 Halt computer
3. Input / Output Instructions
In I/O Reference Instruction:
 First 12 bits (0-11) specify the I/O operation.
 The next three bits equals to 111 specify opcode.
 The last mode bit of the instruction is 1.
 Therefore, left most 4 bits are always 1111 which is equal to hexadecimal F.
Figure 21: Input - output instruction format
Table 12: Basic Computer Instructions for Input - output instructions

INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on Output flag
ION F080 Interrupt on
IOF F040 Interrupt off
Instruction Cycle
The program is executed in the computer by going through a cycle for each instruction. Each
instruction cycle in turn is subdivided into a sequence of sub cycles or phases.
In the basic computer each instruction cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.

4. Execute the instruction.

After the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the next
instruction. This process continues indefinitely unless a HALT instruction is encountered or no further
instructions to be executed.
Fetch and Decode
 Initially, the program counter PC is loaded with the address of the first instruction in the
program. The sequence counter SC is cleared to 0, providing a decoded timing signal T0.
After each clock pulse, SC is incremented by one, so that the timing signals go through a
sequence T0, T1, T2, and so on.
 The Microoperations for the fetch and decode phases can be specified by the following
register transfer statements.
T0: AR  PC
T1: IR M[AR], PC  PC + 1
T2: D0, • • • , D7  Decode IR(12-14), AR  IR(0-11), 1  IR(l5)
 Since only AR is connected to the address inputs of memory, it is necessary to transfer the
address from PC to AR during the clock transition associated with timing signal T0.
 The instruction read from memory is then placed in the instruction register IR with the clock
transition associated with timing signal T1. At the same time, PC is incremented by one to
prepare it for the address of the next instruction in the program.
 At time T2, the operation code in IR is decoded, the indirect bit is transferred to flip-flop I,
and the address part of the instruction is transferred to AR .
 The first two register transfer statements are implemented in the bus system. To provide the
data path for the transfer of PC to AR we must apply timing signal T0 to achieve the following
connection:
1. Place the content of PC onto the bus by making the bus selection inputs S2 S1 S0 equal to
010.
2. Transfer the content of the bus to AR by enabling the LD input of AR. To implement this
it is necessary to use timing signal T1 to provide the following connections in the bus
system.
T1: IR  M[AR], PC  PC + 1

Figure 22: Register Transfers for the Fetch Phase

1. Enable the read input of memory.
2. Place the content of memory onto the bus by making S2S1S0 = 111.
3. Transfer the content of the bus to IR by enabling the LD input of IR .
4. Increment PC by enabling the INR input of PC.
Determine the Type of Instruction
 Decoder output D7= 1 and I = 1 then it is called I/O reference instruction.
 If D7 = 1, and I = 0 the instruction must be a register-reference.
 If D7 = 0, the operation code must be one of the other seven values 000 through 110,
specifying a memory-reference instruction.
 If D7 = 0 and I = 1, we have a memory reference instruction with an indirect address.
 If D7 = 0 and I = 0, we have a memory reference instruction with a direct address.

Figure 23: Flow Chart for Instruction Cycle (Initial Configuration)

The micro operation for the indirect address condition can be symbolized by the register
transfer statement.
AR  M [AR]
The three instruction types are subdivided into four separate paths. The selected operation is
activated with the clock transition associated with timing signal T3. This can be symbolized as
follows:
′
IT3 : AR  M [AR]
′
I' T3: Nothing
D7 I' T3 : Execute a register-reference instruction

D7IT3 : Execute an input-output instruction

MEMORY-REFERENCE INSTRUCTIONS
 In order to specify the micro operations needed for the execution of each instruction, it is
necessary that the function that they are intended to perform be defined precisely.
 The function of the memory-reference instructions can be defined precisely by means of
register transfer notation. Table given below lists the seven memory-reference instructions.
The decoded output Di for i = 0, 1, 2, 3, 4, 5, and 6 from the operation decoder that belongs to
each instruction is included in the table.
 The data must be read from memory to a register where they can be operated on. We will see
the operation of each instruction and list the control functions and micro operations needed
for their execution.
Table 13: Memory Reference Instructions
Symbol operation Decoder Symbolic description

AND Do AC  AC /\ M[AR]
ADD D1 AC  AC + M[A R ] , E  COUT
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC , PC AR + 1
ISZ D6 M[AR]  M[AR] + 1 ,if M[AR] + 1 = 0 then PC  PC + 1
 After the instruction is fetched from memory and decoded, only one output of the operation
decoder will be active, and that output determines the sequence of micro operations that the
control follows during the execution of a memory-reference instruction.
AND to AC
 This is an instruction that performs the logic AND operation on pairs of bits in AC and the
memory word specified by the effective address. The result of the operation is transferred to
AC. The micro operations that execute this instruction are:
D0T4 : DR  M [AR]
D0T5 : AC  AC /\ DR, SC  0
 Two timing signals are needed to execute the instruction.

ADD to AC
 This instruction adds the content of the memory word specified by the effective address to the
value of AC. The sum is transferred into AC and the output carry Cout is transferred to the E
(extended bit of accumulator). The micro operations needed to execute this instruction are
D1T4 : DR  M [AR]
D1T5 : AC  AC + DR, E  Cout, SC  0
LDA: Load to AC
 This instruction transfers the memory word specified by the effective address to AC. The
micro operations needed to execute this instruction are
D2T4 : DR  M [AR]
D2T5 : AC  DR, SC  0
 As we know that there is no direct path from the bus into AC. The adder and logic circuit
receive information from DR which can be transferred into AC. Therefore, it is necessary to
read the memory word into DR first and then transfer the content of DR into AC.
STA: Store AC
 This instruction stores the content of AC into the memory word specified by the effective
address. Since the output of AC is applied to the bus and the data input of memory is
connected to the bus, we can complete the execution of this instruction in 1 timing signal.
D3T4 : M [AR] AC, SC 0
BUN: Branch Unconditionally
 It allows the programmer to specify an instruction out of sequence and we say that the
program branches (or jumps) unconditionally to the location specified by effective address.
The instruction is executed with one micro operation:
D4T4 : PC AR, SC 0
Branch and Save Return Address (BSA)
 This instruction is useful for branching to a portion of the program called a subroutine or
procedure. When executed, the BSA instruction stores the address of the next instruction in
sequence (which is available in PC) into a memory location specified by the effective address.
 The effective address plus one is then transferred to PC to serve as the address of the first
instruction in the subroutine.
M [AR] PC, PC AR + 1
 The BSA instruction performs the following numerical operation:
M[135] 21, PC 135 + 1 = 136
 The result of this operation is shown in part (b) of the figure. The return address 21 is stored
in memory location 135 and control continues with the subroutine program starting from

address 136. The return to the original program (at address 21) is accomplished by means of
an indirect BUN instruction placed at the end of the subroutine.
 The BSA instruction performs the function usually referred to as a subroutine call. The
indirect BUN instruction at the end of the subroutine performs the function referred to as a
subroutine return.
Figure 24: Example of BSA Instruction Execution
 It is not possible to perform the operation of the BSA instruction in one clock cycle when we
use the bus system of the basic computer.
 To use the memory and the bus properly, the BSA instruction must be executed with a
sequence of two micro operations:
D5T4 : M [AR] PC, AR AR + 1
D5T5 : PC AR, SC 0
 Timing signal T4 initiates a memory write operation, places the content of PC onto the bus,
and enables the INR input of AR.
 The memory write operation is completed and AR is incremented by the time the next clock
transition occurs. The bus is used at T5 to transfer the content of AR to PC.
Increment and Skip if Zero (ISZ)
 This instruction increment the word specified by the effective address, and if the incremented
value is equal to 0, PC is incremented by 1.
 The programmer usually stores a negative number (in 2's complement) in the memory word.
As this negative number is repeatedly incremented by one, it eventually reaches the value of
zero. At that time PC is incremented by 1 in order to skip the next instruction in the program.

 Since it is not possible to increment a word inside the memory, it is necessary to read the
word into DR, increment DR, and store the word back into memory. This is done with the
following sequence of micro operations:
D6T4 : DR M [AR]
D6T5 : DR DR + 1
D6T6 : M [AR] DR, if (DR = 0) then (PC PC + 1), SC 0
Control Flowchart
 A flowchart showing all micro operations for the execution of the seven memory- reference
instructions is shown in Fig. given below.
 The control functions are indicated on top of each box. The micro operations that are
performed during time T4, T5, or T6, depending on the opcode value. This is indicated in the
flowchart by six different paths, one of which the control takes after the instruction is
decoded.
 The sequence counter SC is cleared to 0 during the last timing signal in each case. This causes
a transfer of control to timing signal T0 to start the next instruction cycle.
 Note that we need only seven timing signals to execute the longest instruction (ISZ) requiring
the 3-bit sequence counter.
Figure 25: Flowchart for Memory Reference Instructions

STACK ORGANIZATION
 A stack is a storage device that stores information in such a manner that the item stored last is
the first item to be retrieved.
 The stack in digital computers is essentially a memory unit with an address register that can
count.
 The register that holds the address for the stack is the stack pointer (SP) that points to the top
of stack.
 The operations like push and pop are performed by incrementing or decrementing the SP.
Register Stack
 A stack can be placed in a portion of a large memory or it can be organized as a collection of
finite number of memory words or registers.
 Consider a stack of 64 words. The SP contains a binary number whose value is equal to the
address of the word that is currently on top of the stack. Three items are placed in the stack:
A, B, C in that order. C is on top of the stack so that the content of SP is now 3.
Figure 26: Block Diagram of 64-Word Stack

 To remove the top item, the stack is popped by reading the memory word at address 3 and
decrementing the content of SP.
 Item B is now on top of the stack since SP holds address 2.To insert a new item, the stack is
pushed by incrementing SP and writing a word in the next-higher location in the stack.
 The PUSH operation is implemented with the following sequence of micro operations:
1. SPSP+1 increment stack pointer
2. M[SP]DR write item on top of stack

3. if(SP=0) then (FULL1) check if stack is full

4. EMPTY0 mark the stack not empty
 The POP operation is implemented with the following sequence of micro operations:
1. DRM[SP] read item from top of the stack
2. SPSP-1 increment stack pointer
3. if(SP=0) then (EMPTY1) check if stack is empty
4. FULL0 mark the stack not full
Memory Stack
 Memory stack is implemented in RAM attached to a CPU. The implementation of a stack in
the CPU is done by assigning a portion of memory for stack operations and using a processor
register as a stack pointer.
 The figure given below shows a portion of computer memory partitioned into three segments:
program, data and stack.
Figure 27: Computer Memory with Program Data and Stack Segments
 In the above figure, the PC points to the address of the next instruction in the program.
 The AR points to an array of data.
 The SP points to the top of the stack.
 The three registers are connected through a common address bus, and either one can provide
an address for memory.

 A new item is inserted with the PUSH operation as follows:

SPSP-1
M[SP]DR
 An item is deleted with the POP operation as follows:
DRM[SP]
SPSP+1
 Stack limits can be checked by using two processor registers, one for upper and other for
lower limits.
Reverse Polish Notation

 Polish notation, in which the operator comes before the operands, was invented in the 1920s
by the Polish mathematician Jan Lucasiewicz
 A stack organization is very effective for evaluating arithmetic expressions.
A+B infix notation
+AB prefix notation
AB+ postfix notation
Example: (3*4)+(5*6) in reverse polish notation is expressed as 34*56*+
PUSH 3
PUSH 4
ADD
PUSH 5
PUSH 6
ADD
MUL
POP
INSTRUCTION FORMATS
 The format of an instruction is usually depicted in a rectangular box symbolizing the bits of
the instruction as they appear in memory words or in a control register. The bits of the
instruction are divided into 3 fields with each field consisting of a group of bits.
a. Operation code field that specifies the operation to be performed
b. Address field that designates a memory address or processor register where the
operand is present
c. Mode field that specifies the way the operand or the effective address is to be
determined.

 Other special fields are sometimes employed under certain circumstances.

 Instruction formats are concerned with the address fields in an instruction.
 Operations specified by computer instructions are executed on some data stored in memory or
registers.
 Operands residing in memory are specified by their memory address.
 Operands residing in registers are specified with a register address.
 A CPU with 16 processor registers labelled R0 through R15 will have a register address field
of 4 bits.
 The number of address fields in the instruction format of a computer depends on the internal
organization of its registers.
i. Single accumulator organization
 All operations are performed in combination with accumulator. It requires only one address
field.
 ADD X, where X is the address of the operand. The ADD instruction results in the
operation
 ACAC+M[X]
ii. General register organization
 It requires two or three register address fields
ADD R1,R2,R3 resulting in the operation R1R2+R3.
 The number of address fields in the instruction can be reduced from three to two if the
destination register is one of the source registers.
ADD R1,R2 resulting in operation R1R1+R2. These instructions need
two address fields to specify the source and the destination.
iii. Stack organization
 It has PUSH and POP instructions which require no address field.
 Consider the instruction ADD, this operation has the effect of popping the top two elements
from the stack, adding the numbers, and pushing the sum into the stack.
Let us see the assembly language programs in different instruction formats that evaluates
X=(A+B)*(C+D) as follows.
THREE ADDRESS INSTRUCTIONS

 Computers with three-address instruction formats can use each address field to specify either
a processor register or a memory operand.
ADD R1,A,B R1M[A]+M[B]

ADD R2,C,D R2M[C]+M[D]

MUL X,R1,R2 M[X]R1*R2
Merit: it results in short programs when evaluating arithmetic expressions.
Demerit: The binary-coded instructions require too many bits to specify three addresses.
TWO ADDRESS INSTRUCTIONS

 Each address field can specify either a processor register or a memory word.
MOV R1,A R1M[A]
ADD R1,B R1R1+M[B]
MOV R2,C R2M[C]
ADD R2,D R2R2+M[D]
MUL R1,R2 R1R1*R2
MOV X,R1 M[X]R1
The MOV instruction moves or transfers the operands to and from memory and processor registers.
ONE ADDRESS INSTRUCTIONS

 One address instructions use an implied accumulator (AC) register for all data manipulations.
LOAD A ACM[A]
ADD B ACAC+M[B]
STORE T M[T]AC
LOAD C ACM[C]
ADD D ACAC+M[D]
MUL T ACAC*M[T]
STORE X M[X]AC
 All operations are done between accumulator register and a memory operand. T is the address
of the temporary memory location required for storing the intermediate result.
ZERO ADDRESS INSTRUCTIONS

 A stack organized computer does not use an address field in the instructions. The PUSH and
POP instructions, however, need an address field to specify the operand that communicates
with the stack.
PUSH A TOSA
PUSH B TOSB
ADD TOS(A+B)
PUSH C TOSC
PUSH D TOSD

ADD TOS(C+D)
MUL TOS(A+B)* (C+D)
POP X M[X]TOS
 To evaluate arithmetic expressions in a stack computer, it is necessary to convert the
expression into reverse polish (Postfix) notation.
ADDRESSING MODES
In some computers the addressing mode of the instruction is specified with a distinct binary
code, just like the operation code is specified. Other computers use a single binary code that
designates both the operation and the mode of the instruction. Instructions may be defined with a
variety of addressing modes, and sometimes, two or more addressing modes are combined in one
instruction. An example of an instruction format with a distinct addressing mode field is shown in the
below figure.
Figure 28: Instruction format with mode field
The operation code specifies the operation to be performed. The mode field is used to locate
the operands needed for the operation. There may or may not be an address field in the instruction. If
there is an address field, it may designate a memory address or a processor register. Moreover, as
discussed in the preceding section, the instruction may have more than one address field, and each
address field may be associated with its own particular addressing mode. Although most addressing
modes modify the address field of the instruction, there are two modes that need no address field at
all. These are the implied and immediate modes.
1. Implied Mode: In this mode the operands are specified implicitly in the definition of the
instruction.
For example, the instruction “complement accumulator” is an implied-mode instruction because the
operand in the accumulator register is implied in the definition of the instruction. In fact, all register
reference instructions that use an accumulator are implied-mode instructions.
Example: Zero-address instructions in a stack-organized computer are implied-mode instructions
since the operands are implied to be on top of the stack.

CMA, CME, CLE, CLA
2. Immediate Mode: In this mode the operand is specified in the address part of the instruction itself.
In other words, an immediate-mode instruction has an operand field rather than an address field.
Immediate-mode instructions are useful for initializing registers to a constant value.
LD #20
3. Register Mode: In this mode the operands are in registers that reside within the CPU. The
particular register is selected from a register field in the instruction. A k-bit field can specify any one
of 2 k registers.
LD R
4. Register Indirect Mode: In this mode the instruction specifies a register in the CPU whose
contents give the address of the operand in memory. In other words, the selected register contains the
address of the operand rather than the operand itself. Before using a register indirect mode instruction,
the programmer must ensure that the memory address for the operand is placed in the processor
register with a previous instruction. A reference to the register is then equivalent to specifying a
memory address. The advantage of a register indirect mode instruction is that the address field of the
instruction sues fewer bits to select a register than would have been required to specify a memory
address directly.
LD (R) OR LD @R
5. Auto increment or Auto decrement Mode: This is similar to the register indirect mode except
that the register value is incremented or decremented after (or before) its value is used to access
memory. When the address stored in the register refers to a table of data in memory, it is necessary to
increment or decrement the register after every access to the table.
LD (R) + Auto increment
LD (R) - Auto decrement
6. Direct Address Mode: In this mode the effective address is equal to the address part of the
instruction. The operand resides in memory. In a branch-type instruction the address field specifies
the actual branch address.
LD 10

7. Indirect Address Mode: In this mode the address field of the instruction gives the address where
the effective address is stored in memory. Control fetches the instruction from memory and uses its
address part to access memory again to read the effective address.
LD (10)
8. Relative Address Mode: In this mode the content of the program counter is added to the address
part of the instruction in order to obtain the effective address. The address part of the instruction is
usually a signed number (in 2’s complement representation) which can be either positive or negative.
When this number is added to the content of the program counter, the result produces an effective
address whose position in memory is relative to the address of the next instruction.
LD $5
9. Indexed Addressing Mode: In this mode the content of an index register is added to the address
part of the instruction to obtain the effective address. The index register is a special CPU register that
contains an index value. The address field of the instruction defines the beginning address of a data
array in memory.
LD 5(IR)
10. Base Register Addressing Mode: In this mode the content of a base register is added to the
address part of the instruction to obtain the effective address. This is similar to the indexed addressing
mode except that the register is now called a base register instead of an index register.
The difference between the two modes is in the way they are used rather than in the way that
they are computed. An index register is assumed to hold an index number that is relative to the
address part of the instruction. A base register is assumed to hold a base address and the address field
of the instruction gives a displacement relative to this base address. The base register addressing mode
is used in computers to facilitate the relocation of programs in memory. When programs and data are
moved from one segment of memory to another, as required in multiprogramming systems, the
address values of the base register requires updating to reflect the beginning of a new memory
segment.
LD 5(BR)

Numerical Example of Addressing Modes:
Figure 29: Numerical example for addressing modes

Table 14: Tabular List of Numerical Example
Reduced Instruction Set Computer (RISC):

Early computers had small and simple instruction sets, forced mainly by the need to
minimize the hardware used to implement them. As digital hardware became cheaper with
the advent of integrated circuits, computer instructions tended to increase both in number and
complexity. Many computers have instruction sets that include more than 100 and sometimes
even more than 200 instructions. These computers also employ a variety of data types and a
large number of addressing modes. A computer with a large number of instructions is
classified as a complex instruction set computer, abbreviated CISC.

In the early 1980s, a number of computer designers recommended that computers use fewer
instructions with simple constructs so they can be executed much faster within the CPU
without having to use memory as often. This type of computer is classified as a reduced
instruction set computer or RISC.
CISC Characteristics
The instructions in a typical CISC processor provide direct manipulation of operands residing
in memory. As more instructions and addressing modes are incorporated into a computer, the
more hardware logic is needed to implement and support them, and this may cause the
computations to slow down. The major characteristics of CISC architecture are:
1. A large number of instructions-typically from 100 to 250 instructions
2. Some instructions that perform specialized tasks and are used infrequently
3. A large variety of addressing modes-typically from 5 to 20 different modes
4. Variable-length instruction formats
5. Instructions that manipulate operands in memory
RISC Characteristics
The concept of RISC architecture involves an attempt to reduce execution time by
simplifying the instruction set of the computer. The major characteristics of a RISC processor
are:
1. Relatively few instructions
2. Relatively few addressing modes
3. Memory access limited to load and store instructions
4. All operations done within the registers of the CPU
5. Fixed-length, easily decoded instruction format
6. Single-cycle instruction execution
7. Hardwired rather than micro programmed control
The small set of instructions of a typical RISC processor consists mostly of register-
to-register operations, with only simple load and store operations for memory access. Thus
each operand is brought into a processor register with a load instruction. All computations are
done among the data stored in processor registers. Results are transferred to memory by
means of store instructions. This architectural feature simplifies the instruction set and
encourages the optimization of register manipulation. The use of only few addressing modes
results from the fact that almost all instructions have simple register addressing. Other
addressing modes may be included, such as immediate operands and relative mode.

By using a relatively simple instruction format, the instruction length can be fixed and
aligned on word boundaries. An important aspect of RISC instruction format is that it is easy
to decode. Thus the operation code and register fields of the instruction code can be accessed
simultaneously by the control. Characteristics attributed to RISC architecture are:
1. A relatively large number of registers in the processor unit
2. Use of overlapped register windows to speed-up procedure call and return
3. Efficient instruction pipeline
4. Compiler support for efficient translation of high-level language programs into
machine language programs
Overlapped Register Windows

Procedure call and return occurs quite often in high-level programming languages.
When translated into machine language, a procedure call produces a sequence of instructions
that save register values, pass parameters needed for the procedure, and then calls a
subroutine to execute the body of the procedure. After a procedure return, the program
restores the old register values, passes results to the calling program, and returns from the
subroutine. Saving and restoring registers and passing of parameters and results involve time
consuming operations.
The concept of overlapped register windows is illustrated in Fig given below. The
system has a total of 74 registers. Registers R0 through R9 are global registers that hold
parameters shared by all procedures. The other 64 registers are divided into four windows to
accommodate procedures A, B, C, and D. Each register window consists of 10 local registers
and two sets of six registers common to adjacent windows. Local registers are used for local
variables. Common registers are used for exchange of parameters and results between
adjacent procedures. The common overlapped registers permit parameters to be passed
without the actual movement of data. Only one register window is activated at any given time
with a pointer indicating the active window. Each procedure call activates a new register
window by incrementing the pointer. The high registers of the calling procedure overlap the
low registers of the called procedure, and therefore the parameters automatically transfer
from calling to called procedure.
Eg: Each procedure has available a total of 32 registers while it is active. This includes 10
global registers, 10 local registers, 6 low overlapping registers, and 6 high overlapping

registers. In general, the organization of register windows will have the following
relationships:
 number of global registers = G
 number of local registers in each window = L
 number of registers common to two windows = C
 number of windows = W
Figure 30: Overlapped Register Windows
The number of registers available for each window is calculated as follows:
window size = L + 2C + G
The total number of registers needed in the processor is register file = (L + C)W + G
In the example we have G = 10, L = 10, C = 6, and W = 4. The window size is 10 + 12 + 10 =
32 registers, and the register file consists of (10 + 6) x 4 + 10 = 74 registers.

Figure 31: Berkeley RISC1 Instruction Formats

Assignment-Cum-Tutorial Questions
A. Questions testing the remembering / understanding level of students
I) Objective Questions
1. A group of bits that tell the computer to perform a specific operation is known as___ [ ]
A. Operation code B. Micro-operation
C. Accumulator D. Register
2. Which language is termed as the symbolic depiction used for indicating the Operations?[ ]
A. Random transfer language B. Register transfer language
C. Arithmetic transfer language D. All of these
3. Micro operation is shown as? [ ]
A. R1 R2 B.R1  R2 C. Both D. None of these
4. Write the RTL code for transferring the contents of register R1 into R2, when p=1.
5. The load instruction is mostly used to designate a transfer from memory to a processor register
known as____. [ ]
A. Accumulator B. Instruction Register
C. Program counter D. Memory address Register
6. In 3 state buffer, two states act as signals equal to? [ ]
A. Logic 0 B. Logic 1 C. Both a & b D. None of these
7. In 3 state buffer third position termed as high impedance state which acts as? [ ]
A. Open circuit B. Close circuit C. Both a & b D. None of these
8. Which operations are used for addition, subtraction, increment, decrement and complement
function
A. Bus B. Memory transfer [ ]
C. Arithmetic operation D. All of these
9. The register that includes the address of the memory unit is termed as the ____ [ ]
A. MAR B. PC C. IR D. None of these
10. Operation to transfer contents into memory is termed as _____ [ ]
A. Read B. Write C. Both a & b D. None of these
11. What are the operations that a computer performs on the data that is stored in a register? [ ]
A. Register transfer B. Arithmetic C. Logical D. All of these
II) Descriptive Questions
1. Explain various Micro operations with example.
2. Explain how various registers and memory are connected using a common bus with diagram.
3. Draw the circuit diagram of Arithmetic Unit and explain the micro operations.
4. Explain different types of interrupt and explain its life cycle.
5. Explain the working of the circuit that performs Logic operations.
6. Explain different types of instruction formats.

B. Question testing the ability of students in applying the concepts.

I) Multiple Choice Questions:
1. Which operation places memory address in memory address register and data in MDR [ ]
A. Memory read B. Memory write C. Both a & b D. None of these
2. Which operation is extremely useful in serial transfer of data? [ ]
A. Logical micro operation B. Arithmetic micro operation
C. Shift micro operation D. None of these
3. In case of Zero-address instruction format the operands are stored in _____ [ ]
A. Registers B. Accumulator C. Push down stack D. Cache
4. What is the combination of I and Opcode bits for I/O instructions?
5. Consider a memory of size 16M ×16, how many address lines and data lines are required?
6. The CPU of a Computer takes instruction from the memory and executes them. This process is
called
as_____? [ ]
A. Load cycle B. Time sequence
C. Fetch-execute cycle D. None of these
7. The addressing mode used in an instruction of the form ADD X, Y is____? [ ]
A. Direct B. immediate C. indirect D. Relative
8. The addressing mode used in the instruction PUSH B is____? [ ]
A. Direct B. Register C. Register indirect D. Index
9. The addressing mode, where you directly specify the operand value is ______. [ ]
A. Immediate B. Direct C. Definite D. Relative
10. The addressing mode/s, which uses the PC instead of a general purpose register is __. [ ]
A. Indexed with offset B. Relative
C. direct D. both a and c
11. The addressing mode which makes use of in-direction pointers is ______. [ ]
A. Indirect addressing mode B. Index addressing mode
C Relative addressing mode D. Offset addressing mode
II)Problems:
1. Design a bus system for connecting 4 registers each of size 8 bits.
2. Explain the life cycle of an instruction with a suitable flow chart.
3. Explain different types of addressing modes with relevant examples.
4. Design a 6-bit Adder/Subtractor circuit.
5. Write the code in various instruction formats for the statement a=b+c*d.

6. Calculate the effective address for indexed addressing mode instruction, MOV 5(R1)
7. Design a 4-bit Incrementer Circuit.
8. Calculate effective address for the following using various addressing modes.

Unit I Coa

Uploaded by

Copyright:

Available Formats

Unit I Coa

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Unit I Coa

Uploaded by

Copyright:

Available Formats

Computer Organization and Architecture 1

GUDLAVALLERU ENGINEERING COLLEGE

Department of Computer Science and Engineering

II Year - II Semester UNIT-I CSE

 To foster industry-academia relationship for mutual benefit and growth

• Demonstrate commitment and progress in lifelong learning, professional development,

II Year - II Semester UNIT-I CSE

HANDOUT ON COMPUTER ORGANIZATION AND ARCHITECTURE

Class & Sem. : II B.Tech – II Semester Year: 2016-17

II Year - II Semester UNIT-I CSE

7. Prescribed Text Books

II Year - II Semester UNIT-I CSE

3. John L. Hennessy and David A. Patterson, Computer Architecture a quantitative approach,

6. Digital Learning Materials:

7. Lecture Schedule / Lesson Plan

II Year - II Semester UNIT-I CSE

II Year - II Semester UNIT-I CSE

 To explore To familiarize with organizational aspects of memory.

At the end of the unit student will be able to:

II Year - II Semester UNIT-I CSE

e-mail, and internet.

desktop. It is also called a Notebook.

(local area network).

secure, and centralized.

book, address book, calculator and notepad.

functional units of a computer system.

II Year - II Semester UNIT-I CSE

Output Unit Control Unit

I/O CPU / Processor

Figure 1: Basic functional units of a computer

II Year - II Semester UNIT-I CSE

Figure 2: Block diagram of register

II Year - II Semester UNIT-I CSE

Figure 3: Basic computer registers and memory

II Year - II Semester UNIT-I CSE

16-bit Common Bus

Figure 4: Basic Computer Register Connected to a Common BUS

II Year - II Semester UNIT-I CSE

Micro operation: is an elementary operation performed on information stored in one or more

II Year - II Semester UNIT-I CSE

where p is a control signal generated in the control section.

(a) Block Diagram

(b) Timing Diagram

Figure 5: Transfer from R1 to R2 when p =1

S.No Symbol Description Example

1 Letters (and Numbers) Denotes a register MAR, R2

2 Parenthesis ( ) Denotes a part of register R2(0-7), R2(L)

3 Arrow  Denotes transfer of information R2  R1

4 Comma , Separates two microoperations R2  R1, R1  R2

II Year - II Semester UNIT-I CSE

Figure 6: Bus system for four registers

II Year - II Semester UNIT-I CSE

Table 3: Selection of Registers

Three( Tri) state Bus Buffer

Figure 7: Graphic symbol of a three state buffer

II Year - II Semester UNIT-I CSE

 In the above diagram, control input determines the output state.

Figure 8: Bus Line with three state buffer

E S 1 S0 Active Three State Buffer