User Manual lpc17xx
User Manual lpc17xx
User Manual lpc17xx
Document information
Info Content
Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763,
LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM
Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller
Abstract LPC17xx user manual
NXP Semiconductors UM10360
LPC17xx user manual
Revision history
Rev Date Description
2 20100819 LPC17xx user manual revision.
Modifications:
• UART0/1/2/3: FIFOLVL register removed.
• ADC: reset value of the ADCTRM register changed to 0xF00 (Table 536).
• Timer0/1/2/3: Description of DMA operation updated.
• USB Device: Corrected error in the USBCmdCode register (0x01 = write, 0x02 = read)
(Table 220).
• Clocking and power control: add bit 15 (PCGPIO) to PCONP register (Table 46).
• Part LPC1763 added.
• Update register bit description of USBIntStat register in Host and Device mode (Table 191 and
Table 257).
• Motor control PWM: update description of match and limit registers.
• GPIO: update register bit description of the FIOPIN register (Table 109).
• Numerous editorial updates throughout the user manual.
1 20100104 LPC17xx user manual revision.
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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1.1 Introduction
The LPC17xx is an ARM Cortex-M3 based microcontroller for embedded applications
requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as modernized debug
features and a higher level of support block integration.
High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU
frequency. Other versions operate at up to an 100 MHz CPU frequency. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branches.
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1.2 Features
Refer to Section 1.4.1 for details of features on specific part numbers.
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– I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I2S interface can be used with the GPDMA. The I2S interface supports
3-wire data transmit and receive or 4-wire combined transmit and receive
connections, as well as master clock output.
• Other peripherals:
– 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with
configurable pull-up/down resistors, open drain mode, and repeater mode. All
GPIOs are located on an AHB bus for fast access, and support Cortex-M3
bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any
pin of ports 0 and 2 can be used to generate an interrupt.
– 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
– 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
– Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
– One motor control PWM with support for three-phase motor control.
– Quadrature encoder interface that can monitor one external quadrature encoder.
– One standard PWM/timer block with external count input.
– Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V Lithium button
cell. The RTC will continue working when the battery voltage drops to as low as
2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.
– Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
– Cortex-M3 system tick timer, including an external clock input option.
– Repetitive interrupt timer provides programmable and repeating timed interrupts.
• Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire
Trace Port options.
• Emulation trace module supports real-time trace.
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
• Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.
• Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
• Non-maskable Interrupt (NMI) input.
• Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, or the USB clock.
• The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from
any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep power-down modes.
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• Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).
• Each peripheral has its own clock divider for further power savings.
• Brownout detect with separate threshold for interrupt and forced reset.
• On-chip Power-On Reset (POR).
• On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
• 4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a
system clock.
• An on-chip PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
• A second, dedicated PLL may be used for the USB interface in order to allow added
flexibility for the Main PLL settings.
• Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.
• Available as 100-pin LQFP (14 x 14 x 1.4 mm) and 80-pin LQFP (12 x 12 x 1.4 mm)
packages.
1.3 Applications
• eMetering
• Lighting
• Industrial networking
• Alarm systems
• White goods
• Motor control
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Ethernet
RST
Xtalin
Xtalout
Trace JTAG PHY USB
Port interface interface interface
Test/Debug Interface
Trace Module
USB Clock Generation,
Ethernet
DMA device, Clocks Power Control,
10/100
ARM Cortex-M3 controller host, and Brownout Detect,
MAC
OTG Controls and other
system functions
System
D-code
I-code
bus
bus
bus
Flash Flash
Accelerator 512 kB
ROM
8 kB
AHB to AHB to
APB bridge APB bridge
APB slave group 0 APB slave group 1
SSP1 SSP0
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The LPC17xx uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other
bus masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals on different slaves ports of the matrix to be accessed simultaneously by
different bus masters. Details of the multilayer matrix connections are shown in Figure 2.
APB peripherals are connected to the CPU via two APB busses using separate slave
ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller. The APB bus bridges are configured
to buffer writes so that the CPU or DMA controller can write to APB devices without
always waiting for APB write completion.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is
appended to this manual.
System options:
• The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the
SYSTICK timer.
• The Wakeup Interrupt Controller (WIC) is included. The WIC allows more powerful
options for waking up the CPU from reduced power modes.
• A Memory Protection Unit (MPU) is included.
• A ROM Table in included. The ROM Table provides addresses of debug components
to external debug systems.
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This architecture allows the possibility for CPU and DMA accesses to be separated in
such a way that there are few or no delays for the bus masters.
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RST
Xtalin
X32Kin
Xtalout
X32Kout
interface Debug Port interface interface
TRACE MODULE
USB clocks power control, OUT
EMULATION
INTERFACE Ethernet
DMA device, and and other
controller 10/100 host, controls
MAC system functions
ARM Cortex-M3 OTG
internal Vdd
power voltage regulator
SRAM ROM
32 kB 8 kB
SRAM
16 kB
SRAM HS
16 kB GPIO
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APB1 peripherals LPC1768 memory space
0x4010 0000 4 GB 0xFFFF FFFF
0x400F C000 31 system control
30 - 16 reserved reserved
0x400C 0000 AHB peripherals
0xE010 0000 0x5020 0000
15 QEI
0x400B C000 private peripheral bus 127- 4 reserved
0x400B 8000 14 motor control PWM 0xE000 0000
3 USB controller
0x400B 4000 13 reserved 0x5000 C000
reserved
12 repetitive interrupt timer 0x5020 0000 2 reserved
0x400B 0000 0x5000 8000
0x400A C000 11 reserved 1
AHB periherals GPDMA controller
10 I2S 0x5000 0000 0x5000 4000
0x400A 8000
reserved 0 Ethernet controller
0x400A 4000 9 reserved 0x4400 0000 0x5000 0000
8 I2C2 peripheral bit band alias addressing
0x400A 0000 0x4200 0000
7 UART3
0x4009 C000 reserved
6 UART2 0x4010 0000
0x4009 8000 APB1 peripherals APB0 peripherals
0x4008 0000
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TIMER1
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2 0x4000 8000
1 TIMER0 0x4000 4000
0 WDT 0x4000 0000
13 of 840
Figure 3 and Table 4 show different views of the peripheral address space. The AHB
peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required
to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
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For these areas, both attempted data access and instruction fetch generate an exception.
In addition, a Bus Fault exception is generated for any instruction fetch that maps to an
AHB or APB peripheral address.
Within the address space of an existing APB peripheral, an exception is not generated in
response to an access to an undefined address. Address decoding within each peripheral
is limited to that needed to distinguish defined registers within the peripheral itself. For
example, an access to address 0x4000 D000 (an undefined address within the UART0
space) may result in an access to the register defined at address 0x4000 C000. Details of
such address aliasing within a peripheral space are not defined in the LPC17xx
documentation and are not a supported feature.
If software executes a write directly to the flash memory, the flash accelerator will
generate a Bus Fault exception. Flash programming must be accomplished by using the
specified flash programming interface provided by the Boot Code.
Note that the Cortex-M3 core stores the exception flag along with the associated
instruction in the pipeline and processes the exception only if an attempt is made to
execute the instruction fetched from the disallowed address. This prevents accidental
aborts that could be caused by prefetches that occur when code is executed very near a
memory boundary.
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3.1 Introduction
The system control block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
• Reset
• Brown-Out Detection
• External Interrupt Inputs
• Miscellaneous System Controls and Status
Each type of function has its own register(s) if any are required and unneeded bits are
defined as reserved in order to allow future expansion. Unrelated functions never share
the same register addresses
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3.4 Reset
Reset has 4 sources on the LPC17xx: the RESET pin, Watchdog Reset, Power On Reset
(POR), and Brown Out Detect (BOD).
The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once
the operating voltage attains a usable level, starts the wake-up timer (see description in
Section 4.9 “Wake-up timer” in this chapter), causing reset to remain asserted until the
external Reset is de-asserted, the oscillator is running, a fixed number of clocks have
passed, and the flash controller has completed its initialization. The reset logic is shown in
the following block diagram (see Figure 4).
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BOD
WAKE-UP TIMER
START
power-down
COUNT 2 n C
internal RC Q
EINT0 wake-up oscillator S
EINT1 wake-up
write “1”
EINT2 wake-up
from APB
EINT3 wake-up
RTC wake-up reset
BOD wake-up
Ethernet MAC wake-up
APB read of
USB need_clk wake-up
PDBIT
CAN wake-up
in PCON
GPIO0 port wake-up
GPIO2 port wake-up
FOSC
to other
blocks
On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset,
External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time
(maximum of 60 μs on power-up) and after the IRC provides a stable clock output, the
reset signal is latched and synchronized on the IRC clock. Then the following two
sequences start simultaneously:
1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is
de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times
out. The boot code performs the boot tasks and may jump to the flash. If the flash is
not ready to access, the Flash Accelerator will insert wait cycles until the flash is
ready.
2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is
de-asserted. The flash wakeup-timer generates the 100 μs flash start-up time. Once it
times out, the flash initialization sequence is started, which takes about 250 cycles.
When it’s done, the Flash Accelerator will be granted access to the flash.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Figure 5 shows an example of the relationship between the RESET, the IRC, and the
processor status when the LPC17xx starts up after reset. See Section 4.3.2 “Main
oscillator” for start-up of the main oscillator if selected by the user code.
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IRC IRC
starts stable
IRC status
RESET
VDD(REG)(3V3)
valid threshold
GND
60 μs
1 μs; IRC stability count
processor status
flash read flash read boot code
starts finishes execution
finishes;
user code starts
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Table 8. Reset Source Identification register (RSID - address 0x400F C180) bit description
Bit Symbol Description Reset
value
0 POR Assertion of the POR signal sets this bit, and clears all of the other bits in See
this register. But if another Reset signal (e.g., External Reset) remains text
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.
1 EXTR Assertion of the RESET signal sets this bit. This bit is cleared only by See
software or POR. text
2 WDTR This bit is set when the Watchdog Timer times out and the WDTRESET bit See
in the Watchdog Mode Register is 1. This bit is cleared only by software or text
POR.
3 BODR This bit is set when the VDD(REG)(3V3) voltage reaches a level below the See
BOD reset trip level (typically 1.85 V under nominal room temperature text
conditions).
If the VDD(REG)(3V3) voltage dips from the normal operating range to below
the BOD reset trip level and recovers, the BODR bit will be set to 1.
If the VDD(REG)(3V3) voltage dips from the normal operating range to below
the BOD reset trip level and continues to decline to the level at which POR
is asserted (nominally 1 V), the BODR bit is cleared.
If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level
above the BOD reset trip level, the BODR will be set to 1.
This bit is cleared only by software or POR.
Note: Only in the case where a reset occurs and the POR = 0, the BODR
bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level
or not.
31:4 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
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The second stage of low-voltage detection asserts Reset to inactivate the LPC17xx when
the voltage on the VDD(REG)(3V3) pins falls below the BOD reset trip level (typically 1.85 V
under nominal room temperature conditions). This Reset prevents alteration of the flash
as operation of the various elements of the chip would otherwise become unreliable due
to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the
Power-On Reset circuitry maintains the overall Reset.
Both the BOD reset interrupt level and the BOD reset trip level thresholds include some
hysteresis. In normal operation, this hysteresis allows the BOD reset interrupt level
detection to reliably interrupt, or a regularly-executed event loop to sense the condition.
But when Brown-Out Detection is enabled to bring the LPC17xx out of Power-down mode
(which is itself not a guaranteed operation -- see Section 4.8.7 “Power Mode Control
register (PCON - 0x400F C0C0)”), the supply voltage may recover from a transient before
the wake-up timer has completed its delay. In this case, the net result of the transient BOD
is that the part wakes up and continues operation after the instructions that set
Power-down mode, without any interrupt occurring and with the BOD bit in the RSID being
0. Since all other wake-up conditions have latching flags (see Section 3.6.2 “External
Interrupt flag register (EXTINT - 0x400F C140)” and Section 27.6.2), a wake-up of this
type, without any apparent cause, can be assumed to be a Brown-Out that has gone
away.
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internal reset
write to EXTINTi 100621
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[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding
bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
event that was just triggered by activity on the EINT pin will not be recognized in future.
For example, if a system wakes up from Power-down using low level on external interrupt
0 pin, its post wake-up code must reset EINT0 bit in order to allow future entry into the
Power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke
Power-down mode will fail. The same goes for external interrupt handling.
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Table 10. External Interrupt Flag register (EXTINT - address 0x400F C140) bit description
Bit Symbol Description Reset
value
0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for 0
its pin, and the pin is in its active state. In edge-sensitive mode, this bit is
set if the EINT0 function is selected for its pin, and the selected edge
occurs on the pin.
This bit is cleared by writing a one to it, except in level sensitive mode
when the pin is in its active state.[1]
1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for 0
its pin, and the pin is in its active state. In edge-sensitive mode, this bit is
set if the EINT1 function is selected for its pin, and the selected edge
occurs on the pin.
This bit is cleared by writing a one to it, except in level sensitive mode
when the pin is in its active state.[1]
2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for 0
its pin, and the pin is in its active state. In edge-sensitive mode, this bit is
set if the EINT2 function is selected for its pin, and the selected edge
occurs on the pin.
This bit is cleared by writing a one to it, except in level sensitive mode
when the pin is in its active state.[1]
3 EINT3 In level-sensitive mode, this bit is set if the EINT3 function is selected for 0
its pin, and the pin is in its active state. In edge-sensitive mode, this bit is
set if the EINT3 function is selected for its pin, and the selected edge
occurs on the pin.
This bit is cleared by writing a one to it, except in level sensitive mode
when the pin is in its active state.[1]
31:4 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
[1] Example: e.g. if the EINTx is selected to be low level sensitive and low level is present on
corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the
pin becomes high.
Note: Software should only change a bit in this register when its interrupt is
disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write
the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the
interrupt. An extraneous interrupt(s) could be set by changing the mode and not
having the EXTINT cleared.
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Table 11. External Interrupt Mode register (EXTMODE - address 0x400F C148) bit
description
Bit Symbol Value Description Reset
value
0 EXTMODE0 0 Level-sensitivity is selected for EINT0. 0
1 EINT0 is edge sensitive.
1 EXTMODE1 0 Level-sensitivity is selected for EINT1. 0
1 EINT1 is edge sensitive.
2 EXTMODE2 0 Level-sensitivity is selected for EINT2. 0
1 EINT2 is edge sensitive.
3 EXTMODE3 0 Level-sensitivity is selected for EINT3. 0
1 EINT3 is edge sensitive.
31:4 - - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
Note: Software should only change a bit in this register when its interrupt is
disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write
the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the
interrupt. An extraneous interrupt(s) could be set by changing the polarity and not
having the EXTINT cleared.
Table 12. External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit
description
Bit Symbol Value Description Reset
value
0 EXTPOLAR0 0 EINT0 is low-active or falling-edge sensitive (depending on 0
EXTMODE0).
1 EINT0 is high-active or rising-edge sensitive (depending on
EXTMODE0).
1 EXTPOLAR1 0 EINT1 is low-active or falling-edge sensitive (depending on 0
EXTMODE1).
1 EINT1 is high-active or rising-edge sensitive (depending on
EXTMODE1).
2 EXTPOLAR2 0 EINT2 is low-active or falling-edge sensitive (depending on 0
EXTMODE2).
1 EINT2 is high-active or rising-edge sensitive (depending on
EXTMODE2).
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Table 12. External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit
description
Bit Symbol Value Description Reset
value
3 EXTPOLAR3 0 EINT3 is low-active or falling-edge sensitive (depending on 0
EXTMODE3).
1 EINT3 is high-active or rising-edge sensitive (depending on
EXTMODE3).
31:4 - - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
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Table 13. System Controls and Status register (SCS - address 0x400F C1A0) bit description
Bit Symbol Value Description Access Reset
value
3:0 - - Reserved. User software should not write ones to - NA
reserved bits. The value read from a reserved bit is
not defined.
4 OSCRANGE Main oscillator range select. R/W 0
0 The frequency range of the main oscillator is 1 MHz
to 20 MHz.
1 The frequency range of the main oscillator is
15 MHz to 25 MHz.
5 OSCEN Main oscillator enable. R/W 0
0 The main oscillator is disabled.
1 The main oscillator is enabled, and will start up if
the correct external circuitry is connected to the
XTAL1 and XTAL2 pins.
6 OSCSTAT Main oscillator status. RO 0
0 The main oscillator is not ready to be used as a
clock source.
1 The main oscillator is ready to be used as a clock
source. The main oscillator must be enabled via the
OSCEN bit.
31:7 - - Reserved. User software should not write ones to - NA
reserved bits. The value read from a reserved bit is
not defined.
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• Oscillators
• Clock source selection
• PLLs
• Clock dividers
• APB dividers
• Power control
• Wake-up timer
• External clock output
USB PLL
(PLL1) usb_clk
USB
CPU PLL Clock
main PLL Divider
settings select
(PLL0...) (PLL0CON)
USB clock divider setting
osc_clk USBCLKCFG[3:0]
rtc_clk sysclk Main PLL
CPU cclk
irc_osc (PLL0) ` pllclk
Clock
Divider
system clock select
CLKSRCSEL[1:0] CPU clock divider setting
CCLKCFG[7:0] pclk1
Peripheral pclk2
watchdog clock select Clock pclk4
WDCLKSEL[1:0] Divider
pclk8
wd_clk
PCLK_WDT
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4.3 Oscillators
The LPC17xx includes three independent oscillators. These are the Main Oscillator, the
Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than
one purpose as required in a particular application. This can be seen in Figure 7.
Following Reset, the LPC17xx will operate from the Internal RC Oscillator until switched
by software. This allows systems to operate without any external crystal, and allows the
boot loader code to operate at a known frequency.
Upon power-up or any chip reset, the LPC17xx uses the IRC as the clock source.
Software may later switch to one of the other available clock sources.
The on-board oscillator in the LPC17xx can operate in one of two modes: slave mode and
oscillation mode.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(CC in Figure 8, drawing a), with an amplitude between 200 mVrms and 1000 mVrms.
This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4
V. The XTAL2 pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 8,
drawings b and c, and in Table 15 and Table 16. Since the feedback resistance is
integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected
externally in case of fundamental mode oscillation (the fundamental frequency is
represented by L, CL and RS). Capacitance CP in Figure 8, drawing c, represents the
parallel package capacitance and should not be larger than 7 pF. Parameters FC, CL, RS
and CP are supplied by the crystal manufacturer.
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LPC17xx LPC17xx
<=>
CC CL CP
Xtal
Clock CX1 CX2
RS
a) b) c)
Fig 8. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external
crystal model used for CX1/X2 evaluation
Table 15. Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) low frequency mode (OSCRANGE = 0, see Table 13)
Fundamental oscillation Crystal load Maximum crystal External load
frequency FOSC capacitance CL series resistance RS capacitors CX1, CX2
1 MHz - 5 MHz 10 pF < 300 Ω 18 pF, 18 pF
20 pF < 300 Ω 39 pF, 39 pF
30 pF < 300 Ω 57 pF, 57 pF
5 MHz - 10 MHz 10 pF < 300 Ω 18 pF, 18 pF
20 pF < 200 Ω 39 pF, 39 pF
30 pF < 100 Ω 57 pF, 57 pF
10 MHz - 15 MHz 10 pF < 160 Ω 18 pF, 18 pF
20 pF < 60 Ω 39 pF, 39 pF
15 MHz - 20 MHz 10 pF < 80 Ω 18 pF, 18 pF
Table 16. Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) high frequency mode (OSCRANGE = 1, see Table 13)
Fundamental oscillation Crystal load Maximum crystal External load
frequency FOSC capacitance CL series resistance RS capacitors CX1, CX2
15 MHz - 20 MHz 10 pF < 180 Ω 18 pF, 18 pF
20 pF < 100 Ω 39 pF, 39 pF
20 MHz - 25 MHz 10 pF < 160 Ω 18 pF, 18 pF
20 pF < 80 Ω 39 pF, 39 pF
Since chip operation always begins using the Internal RC Oscillator, and the main
oscillator may not be used at all in some applications, it will only be started by software
request. This is accomplished by setting the OSCEN bit in the SCS register, as described
in Table 13. The main oscillator provides a status flag (the OSCSTAT bit in the SCS
register) so that software can determine when the oscillator is running and stable. At that
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point, software can control switching to the main oscillator as a clock source. Prior to
starting the main oscillator, a frequency range must be selected by configuring the
OSCRANGE bit in the SCS register.
Remark: The RTC oscillator must not be used as a clock source when the PLL0 output is
selected to drive the USB controller. In this case select the main oscillator as clock source
for PLL0 (see also Table 17).
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The clock source selection can only be changed safely when PLL0 is not connected. For a
detailed description of how to change the clock source in a system using PLL0 see
Section 4.5.13 “PLL0 setup sequence”.
• Only the main oscillator must be used (via PLL0) as the clock source for the USB
subsystem. The IRC or RTC oscillators do not provide the proper tolerances for this
use.
• The IRC oscillator should not be used (via PLL0) as the clock source for the CAN
controllers if the CAN baud rate is higher than 100 kbit/s.
Table 17. Clock Source Select register (CLKSRCSEL - address 0x400F C10C) bit
description
Bit Symbol Value Description Reset
value
1:0 CLKSRC Selects the clock source for PLL0 as follows: 0
00 Selects the Internal RC oscillator as the PLL0 clock source
(default).
01 Selects the main oscillator as the PLL0 clock source.
Remark: Select the main oscillator as PLL0 clock source if the
PLL0 clock output is used for USB or for CAN with baudrates
> 100 kBit/s.
10 Selects the RTC oscillator as the PLL0 clock source.
11 Reserved, do not use this setting.
Warning: Improper setting of this value, or an incorrect sequence of
changing this value may result in incorrect operation of the device.
31:2 - 0 Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
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Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the
range of 6 through 512, plus additional values listed in Table 21. The resulting frequency
must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO
output by the value of M, then using a phase-frequency detector to compare the divided
CCO output to the multiplier input. The error value is used to adjust the CCO frequency.
There are additional dividers at the output of PLL0 to bring the frequency down to what is
needed for the CPU, peripherals, and potentially the USB subsystem. PLL0 output
dividers are described in the Clock Dividers section following the PLL0 description. A
block diagram of PLL0 is shown in Figure 9
PLL activation is controlled via the PLL0CON register. PLL0 multiplier and divider values
are controlled by the PLL0CFG register. These two registers are protected in order to
prevent accidental alteration of PLL0 parameters or deactivation of the PLL. Since all chip
operations, including the Watchdog Timer, could be dependent on PLL0 if so configured
(for example when it is providing the chip clock), accidental changes to the PLL0 setup
values could result in unexpected or fatal behavior of the microcontroller. The protection is
accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLL0FEED register.
PLL0 is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL0 must be configured, enabled, and connected to the system by software.
It is important that the setup procedure described in Section 4.5.13 “PLL0 setup
sequence” is followed or PLL0 might not operate at all!
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Warning: Improper setting of PLL0 values may result in incorrect operation of the
device!
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
PLLC
PLLE
PLOCK
pd
refclk
PHASE-
pllclkin N-DIVIDER FREQUENCY FILTER CCO
pllclk
DETECTOR
NSEL
[7:0]
M-DIVIDER /2
MSEL
[14:0]
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output clock. Changes to the PLL0CON register do not take effect until a correct PLL0
feed sequence has been given (see Section 4.5.8 “PLL0 Feed register (PLL0FEED -
0x400F C08C)”).
Table 19. PLL Control register (PLL0CON - address 0x400F C080) bit description
Bit Symbol Description Reset
value
0 PLLE0 PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate 0
PLL0 and allow it to lock to the requested frequency. See PLL0STAT
register, Table 22.
1 PLLC0 PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and 0
locked, then followed by a valid PLL0 feed sequence causes PLL0 to
become the clock source for the CPU, AHB peripherals, and used to
derive the clocks for APB peripherals. The PLL0 output may potentially
be used to clock the USB subsystem if the frequency is 48 MHz. See
PLL0STAT register, Table 22.
31:2 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
PLL0 must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL0 output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that PLL0 is locked before it is connected or automatically
disconnect PLL0 if lock is lost during operation. In the event of loss of lock on PLL0, it is
likely that the oscillator clock has become unstable and disconnecting PLL0 will not
remedy the situation.
Table 20. PLL0 Configuration register (PLL0CFG - address 0x400F C084) bit description
Bit Symbol Description Reset
value
14:0 MSEL0 PLL0 Multiplier value. Supplies the value "M" in PLL0 frequency 0
calculations. The value stored here is M - 1. Supported values for M
are 6 through 512 and those listed in Table 21.
Note: Not all values of M are needed, and therefore some are not
supported by hardware. For details on selecting values for MSEL0 see
Section 4.5.10 “PLL0 frequency calculation”.
15 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
23:16 NSEL0 PLL0 Pre-Divider value. Supplies the value "N" in PLL0 frequency 0
calculations. The value stored here is N - 1. Supported values for N are
1 through 32.
Note: For details on selecting the right value for NSEL0 see
Section 4.5.10 “PLL0 frequency calculation”.
31:24 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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Table 22. PLL Status register (PLL0STAT - address 0x400F C088) bit description
Bit Symbol Description Reset
value
14:0 MSEL0 Read-back for the PLL0 Multiplier value. This is the value currently 0
used by PLL0, and is one less than the actual multiplier.
15 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
23:16 NSEL0 Read-back for the PLL0 Pre-Divider value. This is the value 0
currently used by PLL0, and is one less than the actual divider.
24 PLLE0_STAT Read-back for the PLL0 Enable bit. This bit reflects the state of the 0
PLEC0 bit in PLL0CON (see Table 19) after a valid PLL0 feed.
When one, PLL0 is currently enabled. When zero, PLL0 is turned
off. This bit is automatically cleared when Power-down mode is
entered.
25 PLLC0_STAT Read-back for the PLL0 Connect bit. This bit reflects the state of 0
the PLLC0 bit in PLL0CON (see Table 19) after a valid PLL0 feed.
When PLLC0 and PLLE0 are both one, PLL0 is connected as the
clock source for the CPU. When either PLLC0 or PLLE0 is zero,
PLL0 is bypassed. This bit is automatically cleared when
Power-down mode is entered.
26 PLOCK0 Reflects the PLL0 Lock status. When zero, PLL0 is not locked. 0
When one, PLL0 is locked onto the requested frequency. See text
for details.
31:27 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
PLOCK0 is connected to the interrupt controller. This allows for software to turn on PLL0
and continue with other functions without having to wait for PLL0 to achieve lock. When
the interrupt occurs, PLL0 may be connected, and the interrupt disabled. PLOCK0
appears as interrupt 32 in Table 50. Note that PLOCK0 remains asserted whenever PLL0
is locked, so if the interrupt is used, the interrupt service routine must disable the PLOCK0
interrupt prior to exiting.
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The two writes must be in the correct sequence, and there must be no other register
access in the same address space (0x400F C000 to 0x400F FFFF) between them.
Because of this, it may be necessary to disable interrupts for the duration of the PLL0 feed
operation, if there is a possibility that an interrupt service routine could write to another
register in that space. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLL0CON or PLL0CFG register will
not become effective.
Table 24. PLL Feed register (PLL0FEED - address 0x400F C08C) bit description
Bit Symbol Description Reset
value
7:0 PLL0FEED The PLL0 feed sequence must be written to this register in order for 0x00
PLL0 configuration and control register changes to take effect.
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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The PLL0 output frequency (when PLL0 is both active and connected) is given by:
FCCO = (2 × M × FIN) / N
M = (FCCO × N) / (2 × FIN)
N = (2 × M × FIN) / FCCO
FIN = (FCCO × N) / (2 × M)
At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are
allowed. This supports the entire useful range of both the main oscillator and the IRC.
For lower frequencies, specifically when the RTC is used to clock PLL0, a set of 65
additional M values have been selected for supporting baud rate generation, CAN
operation, and obtaining integer MHz frequencies. These values are shown in Table 26.
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Table 26. Additional Multiplier Values for use with a Low Frequency Clock Input
Low Frequency PLL Multipliers
4272 4395 4578 4725 4807
5127 5188 5400 5493 5859
6042 6075 6104 6409 6592
6750 6836 6866 6958 7050
7324 7425 7690 7813 7935
8057 8100 8545 8789 9155
9613 10254 10376 10986 11719
12085 12207 12817 13184 13672
13733 13916 14099 14420 14648
15381 15564 15625 15869 16113
16479 17578 18127 18311 19226
19775 20508 20599 20874 21149
21973 23071 23438 23804 24170
1. Determine if the application requires use of the USB interface, and whether it will be
clocked from PLL0. The USB requires a 50% duty cycle clock of 48 MHz within a very
small tolerance, which means that FCCO must be an even integer multiple of 48 MHz
(i.e. an integer multiple of 96 MHz), within a very small tolerance.
2. Choose the desired processor operating frequency (CCLK). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
frequency than that of the processor (see Section 4.7 “Clock dividers” on page 54 and
Section 4.8 “Power control” on page 58). Find a value for FCCO that is close to a
multiple of the desired CCLK frequency, bearing in mind the requirement for USB
support in [1] above, and that lower values of FCCO result in lower power dissipation.
3. Choose a value for the PLL input frequency (FIN). This can be a clock obtained from
the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support,
the main oscillator should be used. Bear in mind that if PLL1 rather than PLL0 is used
to clock the USB subsystem, this affects the choice of the main oscillator frequency.
4. Calculate values for M and N to produce a sufficiently accurate FCCO frequency. The
desired M value -1 will be written to the MSEL0 field in PLL0CFG. The desired N value
-1 will be written to the NSEL0 field in PLL0CFG.
In general, it is better to use a smaller value for N, to reduce the level of multiplication that
must be accomplished by the CCO. Due to the difficulty in finding the best values in some
cases, it is recommended to use a spreadsheet or similar method to show many
possibilities at once, from which an overall best choice may be selected. A spreadsheet is
available from NXP for this purpose.
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Example 1
Assumptions:
• The USB interface will not be used in the application, or will be clocked by PLL1.
• The desired CPU rate is 100 MHz.
• An external 10 MHz crystal or clock source will be used as the system clock source.
Calculations:
M = (FCCO × N) / (2 × FIN)
A smaller value for the PLL pre-divide (N) as well as a smaller value of the multiplier (M),
both result in better PLL operational stability and lower output jitter. Lower values of FCCO
also save power. So, the process of determining PLL setup parameters involves looking
for the smallest N and M values giving the lowest FCCO value that will support the required
CPU and/or USB clocks. It is usually easier to work backward from the desired output
clock rate and determine a target FCCO rate, then find a way to obtain that FCCO rate from
the available input clock.
Potential precise values of FCCO are integer multiples of the desired CPU clock. In this
example, it is clear that the smallest frequency for FCCO that can produce the desired CPU
clock rate and is within the PLL0 operating range of 275 to 550 MHz is 300 MHz
(3 × 100 MHz).
Assuming that the PLL pre-divide is 1 (N = 1), the equation above gives
M = ((300 × 106 × 1) / (2 × 10 × 106) = 300 / 20 = 15. Since the result is an integer, there is
no need to look any further for a good set of PLL0 configuration values. The value written
to PLL0CFG would be 0x0E (N - 1 = 0; M - 1 = 14 gives 0x0E).
The PLL output must be further divided in order to produce the CPU clock. This is
accomplished using a separate divider that is described later in this chapter, see
Section 4.7.1.
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Example 2
Assumptions:
• The USB interface will be used in the application and will be clocked from PLL0.
• The desired CPU rate is 60 MHz.
• An external 4 MHz crystal or clock source will be used as the system clock source.
This clock source could be the Internal RC oscillator (IRC).
Calculations:
M = (FCCO × N) / (2 × FIN)
Because supporting USB requires a precise 48 MHz clock with a 50% duty cycle, that
need must be addressed first. Potential precise values of FCCO are integer multiples of the
2 × the 48 MHz USB clock. The 2 × insures that the clock has a 50% duty cycle, which
would not be the case for a division of the PLL output by an odd number.
The possibilities for the FCCO rate when the USB is used are 288 MHz, 384 MHz, and 480
MHz. The smallest frequency for FCCO that can produce a valid USB clock rate and is
within the PLL0 operating range is 288 MHz (3 × 2 × 48 MHz).
Start by assuming N = 1, since this produces the smallest multiplier needed for PLL0. So,
M = ((288 × 106) × 1) / (2 × (4 × 106)) = 288 / 8 = 36. The result is an integer, which is
necessary to obtain a precise USB clock. The value written to PLL0CFG would be 0x23
(N - 1 = 0; M - 1 = 35 = 0x23).
The potential CPU clock rate can be determined by dividing FCCO by the desired CPU
frequency: 288 × 106 / 60 × 106 = 4.8. The nearest integer value for the CPU Clock
Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
If it is important to obtain exactly 60 MHz, an FCCO rate must be found that can be divided
down to both 48 MHz and 60 MHz. As previously noted, the possibilities for the FCCO rate
when the USB is used are 288 MHz, 384 MHz, and 480 MHz. Of these, only is 480 MHz is
also evenly divisible by 60. Divided by 10, this gives the 48 MHz with a 50% duty cycle
needed by the USB subsystem. Divided by 8, it gives 60 MHz for the CPU clock. PLL0
settings for 480 MHz are N = 1 and M = 60.
The PLL output must be further divided in order to produce both the CPU clock and the
USB clock. This is accomplished using separate dividers that are described later in this
chapter. See Section 4.7.1 and Section 4.7.2.
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Example 3
Assumptions:
• The USB interface will not be used in the application, or will be clocked by PLL1.
• The desired CPU rate is 72 MHz
• The 32.768 kHz RTC clock source will be used as the system clock source
Calculations:
M = (FCCO × N) / (2 × FIN)
The smallest integer multiple of the desired CPU clock rate that is within the PLL0
operating range is 288 MHz (4 × 72 MHz).
Using the equation above and assuming that N = 1, M = ((288 × 106) × 1) / (2 × 32,768) =
4,394.53125. This is not an integer, so the CPU frequency will not be exactly 72 MHz with
this setting. Since this example is less obvious, it may be useful to make a table of
possibilities for different values of N (see below).
Beyond N = 5, the value of M is out of range or not supported, so the table stops at that
point. In the third column of the table, the calculated M value is rounded to the nearest
integer. If this results in CCLK being above the maximum operating frequency, it is
allowed if it is not more than 1/2 % above the maximum frequency.
In general, larger values of FREF result in a more stable PLL when the input clock is a low
frequency. Even the first table entry shows a very small error of just over 1 hundredth of a
percent, or 107 parts per million (ppm). If that is not accurate enough in the application,
the second case gives a much smaller error of 7 ppm. There are no allowed combinations
that give a smaller error than that.
Remember that when a frequency below about 1 MHz is used as the PLL0 clock source,
not all multiplier values are available. As it turns out, all of the rounded M values found in
Table 28 of this example are supported, which may be confirmed in Table 26. If PLL0
calculations suggest use of unsupported multiplier values, those values must be
disregarded and other values examined to find the best fit.
The value written to PLL0CFG for the second table entry would be 0x12254
(N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254).
The PLL output must be further divided in order to produce the CPU clock. This is
accomplished using a separate divider that is described later in this chapter, see
Section 4.7.1.
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It is very important not to merge any steps above. For example, do not update the
PLL0CFG and enable PLL0 simultaneously with the same feed sequence.
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PLL1 is disabled and powered off on reset. If PLL1 is left disabled, the USB clock can be
supplied by PLL0 if everything is set up to provide 48 MHz through that route. If PLL1 is
enabled and connected via the PLL1CON register (see Section 4.6.2), it is automatically
selected to drive the USB subsystem (see Figure 7).
PLL1 activation is controlled via the PLL1CON register. PLL1 multiplier and divider values
are controlled by the PLL1CFG register. These two registers are protected in order to
prevent accidental alteration of PLL1 parameters or deactivation of PLL1. The protection
is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLL1FEED register.
PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input
frequency is multiplied up to the range of 48 MHz for the USB clock using a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (for USB,
the multiplier value cannot be higher than 4. The CCO operates in the range of 156 MHz
to 320 MHz, so there is an additional divider in the loop to keep the CCO within its
frequency range while PLL1 is providing the desired output frequency. The output divider
may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum
output divider value is 2, it is insured that the output of PLL1 has a 50% duty cycle. A
block diagram of PLL1 is shown in Figure 10.
Warning: Improper setting of PLL1 values may result in incorrect operation of the
USB subsystem!
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[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
PLOCK
PLLSTAT[10]
PLL input
clock PLL output
Current- Fcco clock
Phase
Controlled Divide by 2P
Detector
Oscillator
PSEL
PLLSTAT[6:5]
Divide by M
MSEL
PLLSTAT[4:0] 100416
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Table 30. PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description
Bit Symbol Description Reset
value
0 PLLE1 PLL1 Enable. When one, and after a valid PLL1 feed, this bit will 0
activate PLL1 and allow it to lock to the requested frequency. See
PLL1STAT register, Table 32.
1 PLLC1 PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and 0
locked, then followed by a valid PLL1 feed sequence causes PLL1 to
become the clock source for the USB subsystem via the USB clock
divider. See PLL1STAT register, Table 32.
31:2 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
PLL1 must be set up, enabled, and lock established before it may be used as a clock
source for the USB subsystem. The hardware does not insure that the PLL is locked
before it is connected nor does it automatically disconnect the PLL if lock is lost during
operation.
Table 31. PLL Configuration register (PLL1CFG - address 0x400F C0A4) bit description
Bit Symbol Description Reset
value
4:0 MSEL1 PLL1 Multiplier value. Supplies the value "M" in the PLL1 frequency 0
calculations.
Note: For details on selecting the right value for MSEL1 see
Section 4.6.8.
6:5 PSEL1 PLL1 Divider value. Supplies the value "P" in the PLL1 frequency 0
calculations.
Note: For details on selecting the right value for PSEL1 see
Section 4.6.8.
31:7 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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Table 32. PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description
Bit Symbol Description Reset
value
4:0 MSEL1 Read-back for the PLL1 Multiplier value. This is the value currently 0
used by PLL1.
6:5 PSEL1 Read-back for the PLL1 Divider value. This is the value currently 0
used by PLL1.
7 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
8 PLLE1_STAT Read-back for the PLL1 Enable bit. When one, PLL1 is currently 0
activated. When zero, PLL1 is turned off. This bit is automatically
cleared when Power-down mode is activated.
9 PLLC1_STAT Read-back for the PLL1 Connect bit. When PLLC and PLLE are 0
both one, PLL1 is connected as the clock source for the
microcontroller. When either PLLC or PLLE is zero, PLL1 is
bypassed and the oscillator clock is used directly by the
microcontroller. This bit is automatically cleared when Power-down
mode is activated.
10 PLOCK1 Reflects the PLL1 Lock status. When zero, PLL1 is not locked. 0
When one, PLL1 is locked onto the requested frequency.
31:11 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
PLOCK1 is connected to the interrupt controller. This allows for software to turn on the
PLL and continue with other functions without having to wait for the PLL to achieve lock.
When the interrupt occurs, the PLL may be connected, and the interrupt disabled.
PLOCK1 appears as interrupt 48 in Table 50. Note that PLOCK1 remains asserted
whenever PLL1 is locked, so if the interrupt is used, the interrupt service routine must
disable the PLOCK1 interrupt prior to exiting.
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The two writes must be in the correct sequence, and there must be no other register
access in the same address space (0x400F C000 to 0x400F FFFF) between them.
Because of this, it may be necessary to disable interrupts for the duration of the PLL feed
operation, if there is a possibility that an interrupt service routine could write to another
register in that space. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLL1CON or PLL1CFG register will
not become effective.
Table 34. PLL1 Feed register (PLL1FEED - address 0x400F C0AC) bit description
Bit Symbol Description Reset
value
7:0 PLL1FEED The PLL1 feed sequence must be written to this register in order for 0x00
PLL1 configuration and control register changes to take effect.
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
If activity on the USB data lines is not selected to wake the microcontroller from
Power-down mode (see Section 4.8.8 for details of wake up from reduced modes), both
the Main PLL (PLL0) and the USB PLL (PLL1) will be automatically be turned off and
disconnected when Power-down mode is invoked, as described above. However, if the
USB activity interrupt is enabled and USB_NEED_CLK = 1 (see Table 191 for a
description of USB_NEED_CLK), it is not possible to go into Power-down mode and any
attempt to set the PD bit will fail, leaving the PLLs in the current state.
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The PLL1 output frequency (when the PLL is both active and connected) is given by:
The PLL1 inputs and settings must meet the following criteria:
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Note: when the USB interface is used in an application, CCLK must be at least 18 MHz in
order to support internal operations of the USB subsystem.
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Table 38. CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit
description
Bit Symbol Value Description Reset
value
7:0 CCLKSEL Selects the divide value for creating the CPU clock (CCLK) 0x00
from the PLL0 output.
0 pllclk is divided by 1 to produce the CPU clock. This setting is
not allowed when the PLL0 is connected, because the rate
would always be greater than the maximum allowed CPU
clock.
1 pllclk is divided by 2 to produce the CPU clock. This setting is
not allowed when the PLL0 is connected, because the rate
would always be greater than the maximum allowed CPU
clock.
2 pllclk is divided by 3 to produce the CPU clock.
3 pllclk is divided by 4 to produce the CPU clock.
4 pllclk is divided by 5 to produce the CPU clock.
: :
255 pllclk is divided by 256 to produce the CPU clock.
31:8 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1. Having
CCLKSEL = 2 results in CCLK being one third of the PLL0 output, CCLKSEL = 3 results in
CCLK being one quarter of the PLL0 output, etc.
The USBCLKCFG register controls the division of the PLL0 output before it is used by the
USB subsystem.The PLL0 output must be divided in order to bring the USB clock
frequency to 48 MHz with a 50% duty cycle. A 4-bit divider allows obtaining the correct
USB clock from any even multiple of 48 MHz (i.e. any multiple of 96 MHz) within the PLL
operating range.
Remark: The Internal RC oscillator should not be used to drive PLL0 when the USB is
using PLL0 as a clock source because a more precise clock is needed for USB
specification compliance (see Table 17).
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Table 39. USB Clock Configuration register (USBCLKCFG - address 0x400F C108) bit
description
Bit Symbol Value Description Reset
value
3:0 USBSEL Selects the divide value for creating the USB clock from the 0
PLL0 output. Only the values shown below can produce even
number multiples of 48 MHz from the PLL0 output.
Warning: Improper setting of this value will result in incorrect
operation of the USB interface.
5 PLL0 output is divided by 6. PLL0 output must be 288 MHz.
7 PLL0 output is divided by 8. PLL0 output must be 384 MHz.
9 PLL0 output is divided by 10. PLL0 output must be 480 MHz.
31:4 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
Remark: The peripheral clock for the RTC block is fixed at CCLK/8.
Table 40. Peripheral Clock Selection register 0 (PCLKSEL0 - address 0x400F C1A8) bit
description
Bit Symbol Description Reset
value
1:0 PCLK_WDT Peripheral clock selection for WDT. 00
3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0. 00
5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1. 00
7:6 PCLK_UART0 Peripheral clock selection for UART0. 00
9:8 PCLK_UART1 Peripheral clock selection for UART1. 00
11:10 - Reserved. NA
13:12 PCLK_PWM1 Peripheral clock selection for PWM1. 00
15:14 PCLK_I2C0 Peripheral clock selection for I2C0. 00
17:16 PCLK_SPI Peripheral clock selection for SPI. 00
19:18 - Reserved. NA
21:20 PCLK_SSP1 Peripheral clock selection for SSP1. 00
23:22 PCLK_DAC Peripheral clock selection for DAC. 00
25:24 PCLK_ADC Peripheral clock selection for ADC. 00
27:26 PCLK_CAN1 Peripheral clock selection for CAN1.[1] 00
29:28 PCLK_CAN2 Peripheral clock selection for CAN2.[1] 00
31:30 PCLK_ACF Peripheral clock selection for CAN acceptance filtering.[1] 00
[1] PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.
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Table 41. Peripheral Clock Selection register 1 (PCLKSEL1 - address 0x400F C1AC) bit
description
Bit Symbol Description Reset
value
1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder 00
Interface.
3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00
5:4 PCLK_PCB Peripheral clock selection for the Pin Connect block. 00
7:6 PCLK_I2C1 Peripheral clock selection for I2C1. 00
9:8 - Reserved. NA
11:10 PCLK_SSP0 Peripheral clock selection for SSP0. 00
13:12 PCLK_TIMER2 Peripheral clock selection for TIMER2. 00
15:14 PCLK_TIMER3 Peripheral clock selection for TIMER3. 00
17:16 PCLK_UART2 Peripheral clock selection for UART2. 00
19:18 PCLK_UART3 Peripheral clock selection for UART3. 00
21:20 PCLK_I2C2 Peripheral clock selection for I2C2. 00
23:22 PCLK_I2S Peripheral clock selection for I2S. 00
25:24 - Reserved. NA
27:26 PCLK_RIT Peripheral clock selection for Repetitive Interrupt Timer. 00
29:28 PCLK_SYSCON Peripheral clock selection for the System Control block. 00
31:30 PCLK_MC Peripheral clock selection for the Motor Control PWM. 00
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Entry to any reduced power mode begins with the execution of either a WFI (Wait For
Interrupt) or WFE (Wait For Exception) instruction by the Cortex-M3. The Cortex-M3
internally supports two reduced power modes: Sleep and Deep Sleep. These are selected
by the SLEEPDEEP bit in the cortex-M3 System Control Register. Power-down and Deep
Power-down modes are selected by bits in the PCON register. See Table 44. The same
register contains flags that indicate whether entry into each reduced power mode actually
occurred.
The LPC17xx also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the Real Time Clock.
Reduced power modes have some limitation during debug, see Section 33.5 for more
information.
When Sleep mode is entered, the clock to the core is stopped, and the SMFLAG bit in
PCON is set, see Table 44.Resumption from the Sleep mode does not need any special
sequence but re-enabling the clock to the ARM core.
The GPDMA may operate in Sleep mode to access AHB SRAMs and peripherals with
GPDMA support, but the GPDMA cannot access the flash memory or the main SRAM,
which are disabled in order to save power.
Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.
When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly
all clocks are stopped, and the DSFLAG bit in PCON is set, see Table 44. The IRC
remains running and can be configured to drive the Watchdog Timer, allowing the
Watchdog to wake up the CPU. The 32 kHz RTC oscillator is not stopped and RTC
interrupts may be used as a wake-up source. The flash is left in the standby mode
allowing a quick wake-up. The PLLs are automatically turned off and disconnected. The
CCLK and USBCLK clock dividers automatically get reset to zero.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Deep Sleep mode and the logic levels of chip pins remain static.
The Deep Sleep mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Deep Sleep mode reduces chip power
consumption to a very low value.
On the wake-up of Deep Sleep mode, if the IRC was used before entering Deep Sleep
mode, a 2-bit IRC timer starts counting and the code execution and peripherals activities
will resume after the timer expires (4 cycles). If the main external oscillator was used, the
12-bit main oscillator timer starts counting and the code execution will resume when the
timer expires (4096 cycles). The user must remember to re-configure any required PLLs
and clock dividers after the wake-up.
Wake-up from Deep Sleep mode can be brought about by NMI, External Interrupts EINT0
through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,
an RTC Alarm interrupt, a Watchdog Timer timeout, a USB input pin transition (USB
activity interrupt), or a CAN input pin transition, when the related interrupt is enabled.
Wake-up will occur whenever any enabled interrupt occurs.
When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are
stopped. The RTC remains running if it has been enabled and RTC interrupts may be
used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are
automatically turned off and disconnected. The CCLK and USBCLK clock dividers
automatically get reset to zero.
Upon wake-up from Power-down mode, if the IRC was used before entering Power-down
mode, after IRC-start-up time (about 60 μs), the 2-bit IRC timer starts counting and
expiring in 4 cycles. Code execution can then be resumed immediately following the
expiration of the IRC timer if the code was running from SRAM. In the meantime, the flash
wake-up timer measures flash start-up time of about 100 μs. When it times out, access to
the flash is enabled. The user must remember to re-configure any required PLLs and
clock dividers after the wake-up.
Wake-up from Power-down mode can be brought about by NMI, External Interrupts EINT0
through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,
an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), or a CAN input
pin transition, when the related interrupt is enabled.
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To optimize power conservation, the user has the additional option of turning off or
retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn
off power to the on-chip regulator via the VDD(REG)(3V3) pins after entering Deep
Power-down mode.Power to the on-chip regulator must be restored before device
operation can be restarted.
Wake-up from Deep Power-down mode will occur when an external reset signal is
applied, or the RTC interrupt is enabled and an RTC interrupt is generated.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
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Table 44. Power Mode Control register (PCON - address 0x400F C0C0) bit description
Bit Symbol Description Reset
value
0 PM0 Power mode control bit 0. This bit controls entry to the Power-down 0
mode. See Section 4.8.7.1 below for details.
1 PM1 Power mode control bit 1. This bit controls entry to the Deep 0
Power-down mode. See Section 4.8.7.1 below for details.
2 BODRPM Brown-Out Reduced Power Mode. When BODRPM is 1, the 0
Brown-Out Detect circuitry will be turned off when chip Power-down
mode or Deep Sleep mode is entered, resulting in a further reduction
in power usage. However, the possibility of using Brown-Out Detect as
a wake-up source from the reduced power mode will be lost.
When 0, the Brown-Out Detect function remains active during
Power-down and Deep Sleep modes.
See the System Control Block chapter for details of Brown-Out
detection.
3 BOGD Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect 0
circuitry is fully disabled at all times, and does not consume power.
When 0, the Brown-Out Detect circuitry is enabled.
See the System Control Block chapter for details of Brown-Out
detection.
4 BORD Brown-Out Reset Disable. When BORD is 1, the BOD will not reset 0
the device when the VDD(REG)(3V3) voltage dips goes below the BOD
reset trip level. The Brown-Out interrupt is not affected.
When BORD is 0, the BOD reset is enabled.
See the Section 3.5 for details of Brown-Out detection.
7:3 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
8 SMFLAG Sleep Mode entry flag. Set when the Sleep mode is successfully 0 [1][2]
entered. Cleared by software writing a one to this bit.
9 DSFLAG Deep Sleep entry flag. Set when the Deep Sleep mode is successfully 0 [1][2]
entered. Cleared by software writing a one to this bit.
10 PDFLAG Power-down entry flag. Set when the Power-down mode is 0 [1][2]
successfully entered. Cleared by software writing a one to this bit.
11 DPDFLAG Deep Power-down entry flag. Set when the Deep Power-down mode 0 [1][3]
is successfully entered. Cleared by software writing a one to this bit.
31:12 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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Interrupts that can occur during Deep Sleep or Power-down mode will wake up the CPU if
the interrupt is enabled. After wake-up, execution will continue to the appropriate interrupt
service routine. These interrupts are NMI, External Interrupts EINT0 through EINT3, GPIO
interrupts, Ethernet Wake-on-LAN interrupt, Brownout Detect, RTC Alarm, CAN Activity
Interrupt, and USB Activity Interrupt. In addition, the watchdog timer can wake up the part
from Deep Sleep mode if the watchdog timer is being clocked by the IRC oscillator. For
the wake-up process to take place the corresponding interrupt must be enabled in the
NVIC. For pin-related peripheral functions, the related functions must also be mapped to
pins.
The CAN Activity Interrupt is generated by activity on the CAN bus pins, and the USB
Activity Interrupt is generated by activity on the USB bus pins. These interrupts are only
useful to wake up the CPU when it is on Deep Sleep or Power-down mode, when the
peripheral functions are powered up, but not active. Typically, if these interrupts are used,
their flags should be polled just before enabling the interrupt and entering the desired
reduced power mode. This can save time and power by avoiding an immediate wake-up.
Upon wake-up, the interrupt service can turn off the related activity interrupt, do any
application specific setup, and exit to await a normal peripheral interrupt.
In Deep Power-down mode, internal power to most of the device is removed, which limits
the possibilities for waking up from this mode. Wake-up from Deep Power-down mode will
occur when an external reset signal is applied, or the RTC interrupt is enabled and an
RTC interrupt is generated.
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Some peripherals, particularly those that include analog functions, may consume power
that is not clock dependent. These peripherals may contain a separate disable control that
turns off additional circuitry to reduce power. Information on peripheral specific power
saving features may be found in the chapter describing that peripheral.
If a peripheral control bit is 1, that peripheral is enabled. If a peripheral control bit is 0, that
peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the
I2C1 interface is enabled. If bit 19 is 0, the I2C1 interface is disabled.
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit
description
Bit Symbol Description Reset
value
0 - Reserved. NA
1 PCTIM0 Timer/Counter 0 power/clock control bit. 1
2 PCTIM1 Timer/Counter 1 power/clock control bit. 1
3 PCUART0 UART0 power/clock control bit. 1
4 PCUART1 UART1 power/clock control bit. 1
5 - Reserved. NA
6 PCPWM1 PWM1 power/clock control bit. 1
7 PCI2C0 The I2C0 interface power/clock control bit. 1
8 PCSPI The SPI interface power/clock control bit. 1
9 PCRTC The RTC power/clock control bit. 1
10 PCSSP1 The SSP 1 interface power/clock control bit. 1
11 - Reserved. NA
12 PCADC A/D converter (ADC) power/clock control bit. 0
Note: Clear the PDN bit in the AD0CR before clearing this bit, and set
this bit before setting PDN.
13 PCCAN1 CAN Controller 1 power/clock control bit. 0
14 PCCAN2 CAN Controller 2 power/clock control bit. 0
15 PCGPIO Power/clock control bit for IOCON, GPIO, and GPIO interrupts. 1
16 PCRIT Repetitive Interrupt Timer power/clock control bit. 0
17 PCMCPWM Motor Control PWM 0
18 PCQEI Quadrature Encoder Interface power/clock control bit. 0
19 PCI2C1 The I2C1 interface power/clock control bit. 1
20 - Reserved. NA
21 PCSSP0 The SSP0 interface power/clock control bit. 1
22 PCTIM2 Timer 2 power/clock control bit. 0
23 PCTIM3 Timer 3 power/clock control bit. 0
24 PCUART2 UART 2 power/clock control bit. 0
25 PCUART3 UART 3 power/clock control bit. 0
26 PCI2C2 I2C interface 2 power/clock control bit. 1
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Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit
description
Bit Symbol Description Reset
value
27 PCI2S I2S interface power/clock control bit. 0
28 - Reserved. NA
29 PCGPDMA GPDMA function power/clock control bit. 0
30 PCENET Ethernet block power/clock control bit. 0
31 PCUSB USB interface power/clock control bit. 0
Note that the DAC peripheral does not have a control bit in PCONP. To enable the DAC,
its output must be selected to appear on the related pin, P0.26, by configuring the
PINSEL1 register. See Section 8.5.2 “Pin Function Select Register 1 (PINSEL1 -
0x4002 C004)”.
Power saving oriented systems should have 1s in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. Whenever the device core
power is present, that power is used to operate the RTC, causing no power drain from a
battery when main power is available.
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When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power-on, all types of Reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD(REG)(3V3) ramp (in the case of power on), the type
of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other
external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the
existing ambient conditions.
Once a clock is detected, the Wake-up Timer counts a fixed number of clocks (4,096),
then sets the flag (OSCSTAT bit in the SCS register) that indicates that the main oscillator
is ready for use. Software can then switch to the main oscillator and start any required
PLLs. Refer to the Main Oscillator description in this chapter for details.
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Clocks that may be observed via CLKOUT are the CPU clock (cclk), the main oscillator
(osc_clk), the internal RC oscillator (irc_osc), the USB clock (usb_clk), and the RTC clock
(rtc_clk).
CLKOUTCFG[3:0]
cclk
000 CLKOUTCFG[7:4] CLKOUTCFG[8]
osc_clk
001
irc_osc CLKOUT Clock Enable CLKOUT
010
Divider Syncronizer
usb_clk
011
rtc_clk
100 CLKOUTCFG[9]
Note: The CLKOUT multiplexer is designed to switch cleanly, without glitches, between
the possible clock sources. The divider is also designed to allow changing the divide value
without glitches.
Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description
Bit Symbol Value Description Reset
value
3:0 CLKOUTSEL Selects the clock source for the CLKOUT function. 0
0000 Selects the CPU clock as the CLKOUT source.
0001 Selects the main oscillator as the CLKOUT source.
0010 Selects the Internal RC oscillator as the CLKOUT source.
0011 Selects the USB clock as the CLKOUT source.
0100 Selects the RTC oscillator as the CLKOUT source.
others Reserved, do not use these settings.
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Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description
Bit Symbol Value Description Reset
value
7:4 CLKOUTDIV Integer value to divide the output clock by, minus one. 0
0000 Clock is divided by 1.
0001 Clock is divided by 2.
0010 Clock is divided by 3.
... ...
1111 Clock is divided by 16.
8 CLKOUT_EN CLKOUT enable control, allows switching the CLKOUT 0
source without glitches. Clear to stop CLKOUT on the
next falling edge. Set to enable CLKOUT.
9 CLKOUT_ACT CLKOUT activity indication. Reads as 1 when CLKOUT is 0
enabled. Read as 0 when CLKOUT has been disabled via
the CLKOUT_EN bit and the clock has completed being
stopped.
31:10 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
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5.1 Introduction
The flash accelerator block in the LPC17xx allows maximization of the performance of the
Cortex-M3 processor when it is running code from flash memory, while also saving power.
The flash accelerator also provides speed and power improvements for data accesses to
the flash memory.
• AHB-Lite bus interface, accessible by the Cortex-M3 I-code and D-code buses, as
well as by the General Purpose DMA Controller
• An array of eight 128-bit buffers
• Flash accelerator control logic, including address compare and flash control
• A flash memory interface
Figure 13 shows a simplified diagram of the flash accelerator blocks and data paths.
Bus
DCode Matrix Flash Accelerator
bus
Combined
Cortex-M3 AHB AHB-Lite Buffer Flash Flash
ICode
CPU bus bus interface Array Interface Memory
Flash
General DMA
Master Port Accelerator
Purpose Control
DMA
Controller
Fig 13. Simplified block diagram of the flash accelerator showing potential bus connections
In the following descriptions, the term “fetch” applies to an explicit flash read request from
the CPU. “Prefetch” is used to denote a flash read of instructions beyond the current
processor fetch address.
Flash programming operations are not controlled by the flash accelerator, but are handled
as a separate function. A Boot ROM contains flash programming algorithms that may be
called as part of the application program, and a loader that may be run to allow
programming of the flash memory.
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In order to preclude the possibility of stale data being read from the flash memory, the
LPC17xx flash accelerator buffers are automatically invalidated at the beginning of any
flash programming or erase operation. Any subsequent read from a flash address will
cause a new fetch to be initiated after the flash operation has completed.
[1] Reset Value reflects the data stored in defined bits only. It does not include reserved bits content.
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Following reset, flash accelerator functions are enabled and flash access timing is set to a
default value of 4 clocks.
Changing the FLASHCFG register value causes the flash accelerator to invalidate all of
the holding latches, resulting in new reads of flash information as required. This
guarantees synchronization of the flash accelerator to CPU operation.
Table 49. Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) bit description
Bit Symbol Value Description Reset
value
11:0 - - Reserved, user software should not change these bits from the reset value. 0x03A
15:12 FLASHTIM Flash access time. The value of this field plus 1 gives the number of CPU clocks used 0x3
for a flash access.
Warning: improper setting of this value may result in incorrect operation of the device.
0000 Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock.
0001 Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock.
0010 Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock.
0011 Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock.
0100 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock.
Use for up to 120 Mhz for LPC1759 and LPC1769 only.
0101 Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions.
Other Intended for potential future higher speed devices.
31:16 - Reserved. The value read from a reserved bit is not defined. NA
5.5 Operation
Simply put, the flash accelerator attempts to have the next Cortex-M3 instruction that will
be needed in its latches in time to prevent CPU fetch stalls. The LPC17xx uses one bank
of flash memory. The flash accelerator includes an array of eight 128-bit buffers to store
both instructions and data in a configurable manner. Each 128-bit buffer in the array can
include four 32-bit instructions, eight 16-bit instructions or some combination of the two.
During sequential code execution, a buffer typically contains the current instruction and
the entire flash line that contains that instruction, or one flash line of data containing a
previously requested address. Buffers are marked according to how they are used (as
instruction or data buffers), and when they have been accessed. This information is used
to carry out the buffer replacement strategy.
The Cortex-M3 provides a separate bus for instruction access (I-code) and data access
(D-code) in the code memory space. These buses, plus the General Purpose DMA
Controllers’s master port, are arbitrated by the AHB multilayer matrix. Any access to the
flash memory’s address space is presented to the flash accelerator.
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If a flash instruction fetch and a flash data access from the CPU occur at the same time,
the multilayer matrix gives precedence to the data access. This is because a stalled data
access always slows down execution, while a stalled instruction fetch often does not.
When the flash data access is concluded, any flash fetch or prefetch that had been in
progress is re-initiated.
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. Buffer replacement strategy in the flash accelerator
attempts to maximize the chances that potentially reusable information is retained until it
is needed again.
If an attempt is made to write directly to the flash memory without using the normal flash
programming interface (via Boot ROM function calls), the flash accelerator generates an
error condition. The CPU treats this error as a data abort. The GPDMA handles error
conditions as described in Section 31.4.1.6.3.
When an Instruction Fetch is not satisfied by existing contents of the buffer array, nor has
a prefetch been initiated for that flash line, the CPU will be stalled while a fetch is initiated
for the related 128-bit flash line. If a prefetch has been initiated but not yet completed, the
CPU is stalled for a shorter time since the required flash access is already in progress.
A prefetched flash line is latched within the flash memory, but the flash accelerator does
not capture the line in a buffer until the CPU presents an address that is contained within
the prefetched flash line. If the core presents an instruction address that is not already
buffered and is not contained in the prefetched flash line, the prefetched line will be
discarded.
Some special cases include the possibility that the CPU will request a data access to an
address already contained in an instruction buffer. In this case, the data will be read from
the buffer as if it was a data buffer. The reverse case, if the CPU requests an instruction
address that can be satisfied from an existing data buffer, causes the instruction to be
supplied from the data buffer, and the buffer to be changed into an instruction buffer. This
causes the buffer to be handled differently when the flash accelerator is determining which
buffer is to be overwritten next.
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6.1 Features
• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3
• Tightly coupled interrupt controller provides low interrupt latency
• Controls system exceptions and peripheral interrupts
• In the LPC17xx, the NVIC supports 35 vectored interrupts
• 32 programmable interrupt priority levels, with hardware priority level masking
• Relocatable vector table
• Non-Maskable Interrupt
• Software interrupt generation
6.2 Description
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
Refer to the Cortex-M3 User Guide Section 34.4.2 for details of NVIC operation.
Exception numbers relate to where entries are stored in the exception vector table.
Interrupt numbers are used in some other contexts, such as software interrupts.
In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to
operate from an external signal, the NMI function must be connected to the related device
pin (P2.10 / EINT0n / NMI). When connected, a logic 1 on the pin will cause the NMI to be
processed. For details, refer to the Cortex-M3 User Guide that is an appendix to this User
Manual.
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The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table should be located on a 256 word (1024 byte) boundary to insure
alignment on LPC17xx family devices. Refer to Section 34.4.3.5 of the Cortex-M3 User
Guide appended to this manual for details of the Vector Table Offset feature.
ARM describes bit 29 of the VTOR (TBLOFF) as selecting a memory region, either code
or SRAM. For simplicity, this bit can be thought as simply part of the address offset since
the split between the “code” space and the “SRAM” space occurs at the location
corresponding to bit 29 in a memory address.
Examples:
To place the vector table at the beginning of the “local” static RAM, starting at address
0x1000 0000, place the value 0x1000 0000 in the VTOR register. This indicates address
0x1000 0000 in the code space, since bit 29 of the VTOR equals 0.
To place the vector table at the beginning of the AHB static RAM, starting at address
0x2007 C000, place the value 0x2007 C000 in the VTOR register. This indicates address
0x2007 C000 in the SRAM space, since bit 29 of the VTOR equals 1.
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By default, only privileged software can write to the STIR register. Unprivileged software
can be given this ability if privileged software sets the USERSETMPEND bit in the CCR
register (see Section 34.4.3.8).
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100
76
1 75
25 51
26
50
002aad945_1
61
1 60
20 41
21
40
002aae158
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ball A1
LPC1768FET100
index area
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
002aaf723
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8.2 Description
The pin connect block allows most pins of the microcontroller to have more than one
potential function. Configuration registers control the multiplexers to allow connection
between the pin and the on chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Selection of a single function on a port pin excludes other peripheral functions available
on the same pin. However, the GPIO input stays connected and may be read by software
or used to contribute to the GPIO interrupt feature.
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The direction control bit in the GPIO registers is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled automatically. Each
derivative typically has a different pinout and therefore a different set of functions possible
for each pin. Details for a specific derivative may be found in the appropriate data sheet.
Multiple connections
Since a particular peripheral function may be allowed on more than one pin, it is in
principle possible to configure more than one pin to perform the same function. If a
peripheral output function is configured to appear on more than one pin, it will in fact be
routed to those pins. If a peripheral input function is configured to appear on more than
one pin for some reason, the peripheral will receive its input from the lowest port number.
For instance, any pin of port 0 will take precedence over any pin of a higher numbered
port, and pin 0 of any port will take precedence over a higher numbered pin of the same
port.
Repeater mode enables the pull-up resistor if the pin is at a logic high and enables the
pull-down resistor if the pin is at a logic low. This causes the pin to retain its last known
state if it is configured as an input and is not driven externally. The state retention is not
applicable to the Deep Power-down mode. Repeater mode may typically be used to
prevent a pin from floating (and potentially using significant power if it floats to an
indeterminate state) if it is temporarily not driven.
The PINMODE_OD registers control the open drain mode for ports. The open drain mode
causes the pin to be pulled low normally if it is configured as an output and the data value
is 0. If the data value is 1, the output drive of the pin is turned off, equivalent to changing
the pin direction. This combination simulates an open drain output.
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[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
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Table 79. Pin function select register 0 (PINSEL0 - address 0x4002 C000) bit description
PINSEL0 Pin Function when Function when 01 Function Function Reset
name 00 when 10 when 11 value
1:0 P0.0 GPIO Port 0.0 RD1 TXD3 SDA1 00
3:2 P0.1 GPIO Port 0.1 TD1 RXD3 SCL1 00
5:4 P0.2 GPIO Port 0.2 TXD0 AD0.7 Reserved 00
7:6 P0.3 GPIO Port 0.3 RXD0 AD0.6 Reserved 00
9:8 P0.4[1] GPIO Port 0.4 I2SRX_CLK RD2 CAP2.0 00
11:10 P0.5[1] GPIO Port 0.5 I2SRX_WS TD2 CAP2.1 00
13:12 P0.6 GPIO Port 0.6 I2SRX_SDA SSEL1 MAT2.0 00
15:14 P0.7 GPIO Port 0.7 I2STX_CLK SCK1 MAT2.1 00
17:16 P0.8 GPIO Port 0.8 I2STX_WS MISO1 MAT2.2 00
19:18 P0.9 GPIO Port 0.9 I2STX_SDA MOSI1 MAT2.3 00
21:20 P0.10 GPIO Port 0.10 TXD2 SDA2 MAT3.0 00
23:22 P0.11 GPIO Port 0.11 RXD2 SCL2 MAT3.1 00
29:24 - Reserved Reserved Reserved Reserved 0
31:30 P0.15 GPIO Port 0.15 TXD1 SCK0 SCK 00
Table 80. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description
PINSEL1 Pin name Function when Function Function Function Reset
00 when 01 when 10 when 11 value
1:0 P0.16 GPIO Port 0.16 RXD1 SSEL0 SSEL 00
3:2 P0.17 GPIO Port 0.17 CTS1 MISO0 MISO 00
5:4 P0.18 GPIO Port 0.18 DCD1 MOSI0 MOSI 00
7:6 P0.19[1] GPIO Port 0.19 DSR1 Reserved SDA1 00
9:8 P0.20[1] GPIO Port 0.20 DTR1 Reserved SCL1 00
11:10 P0.21[1] GPIO Port 0.21 RI1 Reserved RD1 00
13:12 P0.22 GPIO Port 0.22 RTS1 Reserved TD1 00
15:14 P0.23[1] GPIO Port 0.23 AD0.0 I2SRX_CLK CAP3.0 00
17:16 P0.24[1] GPIO Port 0.24 AD0.1 I2SRX_WS CAP3.1 00
19:18 P0.25 GPIO Port 0.25 AD0.2 I2SRX_SDA TXD3 00
21:20 P0.26 GPIO Port 0.26 AD0.3 AOUT RXD3 00
23:22 P0.27[1][2] GPIO Port 0.27 SDA0 USB_SDA Reserved 00
25:24 P0.28[1][2] GPIO Port 0.28 SCL0 USB_SCL Reserved 00
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Table 80. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description
PINSEL1 Pin name Function when Function Function Function Reset
00 when 01 when 10 when 11 value
27:26 P0.29 GPIO Port 0.29 USB_D+ Reserved Reserved 00
29:28 P0.30 GPIO Port 0.30 USB_D− Reserved Reserved 00
31:30 - Reserved Reserved Reserved Reserved 00
Table 81. Pin function select register 2 (PINSEL2 - address 0x4002 C008) bit description
PINSEL2 Pin Function when Function when Function Function Reset
name 00 01 when 10 when 11 value
1:0 P1.0 GPIO Port 1.0 ENET_TXD0 Reserved Reserved 00
3:2 P1.1 GPIO Port 1.1 ENET_TXD1 Reserved Reserved 00
7:4 - Reserved Reserved Reserved Reserved 0
9:8 P1.4 GPIO Port 1.4 ENET_TX_EN Reserved Reserved 00
15:10 - Reserved Reserved Reserved Reserved 0
17:16 P1.8 GPIO Port 1.8 ENET_CRS Reserved Reserved 00
19:18 P1.9 GPIO Port 1.9 ENET_RXD0 Reserved Reserved 00
21:20 P1.10 GPIO Port 1.10 ENET_RXD1 Reserved Reserved 00
27:22 - Reserved Reserved Reserved Reserved 0
29:28 P1.14 GPIO Port 1.14 ENET_RX_ER Reserved Reserved 00
31:30 P1.15 GPIO Port 1.15 ENET_REF_CLK Reserved Reserved 00
Table 82. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description
PINSEL3 Pin Function when Function when Function Function Reset
name 00 01 when 10 when 11 value
1:0 P1.16[1] GPIO Port 1.16 ENET_MDC Reserved Reserved 00
3:2 P1.17[1] GPIO Port 1.17 ENET_MDIO Reserved Reserved 00
5:4 P1.18 GPIO Port 1.18 USB_UP_LED PWM1.1 CAP1.0 00
7:6 P1.19 GPIO Port 1.19 MCOA0 USB_PPWR CAP1.1 00
9:8 P1.20 GPIO Port 1.20 MCI0 PWM1.2 SCK0 00
11:10 P1.21[1] GPIO Port 1.21 MCABORT PWM1.3 SSEL0 00
13:12 P1.22 GPIO Port 1.22 MCOB0 USB_PWRD MAT1.0 00
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Table 82. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description
PINSEL3 Pin Function when Function when Function Function Reset
name 00 01 when 10 when 11 value
15:14 P1.23 GPIO Port 1.23 MCI1 PWM1.4 MISO0 00
17:16 P1.24 GPIO Port 1.24 MCI2 PWM1.5 MOSI0 00
19:18 P1.25 GPIO Port 1.25 MCOA1 Reserved MAT1.1 00
21:20 P1.26 GPIO Port 1.26 MCOB1 PWM1.6 CAP0.0 00
23:22 P1.27[1] GPIO Port 1.27 CLKOUT USB_OVRCR CAP0.1 00
25:24 P1.28 GPIO Port 1.28 MCOA2 PCAP1.0 MAT0.0 00
27:26 P1.29 GPIO Port 1.29 MCOB2 PCAP1.1 MAT0.1 00
29:28 P1.30 GPIO Port 1.30 Reserved VBUS AD0.4 00
31:30 P1.31 GPIO Port 1.31 Reserved SCK1 AD0.5 00
Table 83. Pin function select register 4 (PINSEL4 - address 0x4002 C010) bit description
PINSEL4 Pin Function when Function when 01 Function Function when Reset
name 00 when 10 11 value
1:0 P2.0 GPIO Port 2.0 PWM1.1 TXD1 Reserved 00
3:2 P2.1 GPIO Port 2.1 PWM1.2 RXD1 Reserved 00
5:4 P2.2 GPIO Port 2.2 PWM1.3 CTS1 Reserved [2] 00
7:6 P2.3 GPIO Port 2.3 PWM1.4 DCD1 Reserved [2] 00
9:8 P2.4 GPIO Port 2.4 PWM1.5 DSR1 Reserved [2] 00
11:10 P2.5 GPIO Port 2.5 PWM1.6 DTR1 Reserved [2] 00
13:12 P2.6 GPIO Port 2.6 PCAP1.0 RI1 Reserved [2] 00
15:14 P2.7 GPIO Port 2.7 RD2 RTS1 Reserved 00
17:16 P2.8 GPIO Port 2.8 TD2 TXD2 ENET_MDC 00
19:18 P2.9 GPIO Port 2.9 USB_CONNECT RXD2 ENET_MDIO 00
21:20 P2.10 GPIO Port 2.10 EINT0 NMI Reserved 00
23:22 P2.11[1] GPIO Port 2.11 EINT1 Reserved I2STX_CLK 00
25:24 P2.12[1] GPIO Port 2.12 EINT2 Reserved I2STX_WS 00
27:26 P2.13[1] GPIO Port 2.13 EINT3 Reserved I2STX_SDA 00
31:28 - Reserved Reserved Reserved Reserved 0
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Table 84. Pin function select register 7 (PINSEL7 - address 0x4002 C01C) bit description
PINSEL7 Pin Function when Function Function Function Reset
name 00 when 01 when 10 when 11 value
17:0 - Reserved Reserved Reserved Reserved 0
19:18 P3.25[1] GPIO Port 3.25 Reserved MAT0.0 PWM1.2 00
21:20 P3.26[1] GPIO Port 3.26 STCLK MAT0.1 PWM1.3 00
31:22 - Reserved Reserved Reserved Reserved 0
Table 85. Pin function select register 9 (PINSEL9 - address 0x4002 C024) bit description
PINSEL9 Pin Function when Function Function Function Reset
name 00 when 01 when 10 when 11 value
23:0 - Reserved Reserved Reserved Reserved 00
25:24 P4.28 GPIO Port 4.28 RX_MCLK MAT2.0 TXD3 00
27:26 P4.29 GPIO Port 4.29 TX_MCLK MAT2.1 RXD3 00
31:28 - Reserved Reserved Reserved Reserved 00
Table 86. Pin function select register 10 (PINSEL10 - address 0x4002 C028) bit description
Bit Symbol Value Description Reset
value
2:0 - - Reserved. Software should not write 1 to these bits. NA
3 GPIO/TRACE TPIU interface pins control. 0
0 TPIU interface is disabled.
1 TPIU interface is enabled. TPIU signals are
available on the pins hosting them regardless of the
PINSEL4 content.
31:4 - - Reserved. Software should not write 1 to these bits. NA
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Table 87. Pin Mode select register 0 (PINMODE0 - address 0x4002 C040) bit description
PINMODE0 Symbol Value Description Reset
value
1:0 P0.00MODE Port 0 pin 0 on-chip pull-up/down resistor control. 00
00 P0.0 pin has a pull-up resistor enabled.
01 P0.0 pin has repeater mode enabled.
10 P0.0 pin has neither pull-up nor pull-down.
11 P0.0 has a pull-down resistor enabled.
3:2 P0.01MODE Port 0 pin 1 control, see P0.00MODE. 00
5:4 P0.02MODE Port 0 pin 2 control, see P0.00MODE. 00
7:6 P0.03MODE Port 0 pin 3 control, see P0.00MODE. 00
9:8 P0.04MODE[1] Port 0 pin 4 control, see P0.00MODE. 00
11:10 P0.05MODE[1] Port 0 pin 5 control, see P0.00MODE. 00
13:12 P0.06MODE Port 0 pin 6 control, see P0.00MODE. 00
15:14 P0.07MODE Port 0 pin 7 control, see P0.00MODE. 00
17:16 P0.08MODE Port 0 pin 8 control, see P0.00MODE. 00
19:18 P0.09MODE Port 0 pin 9control, see P0.00MODE. 00
21:20 P0.10MODE Port 0 pin 10 control, see P0.00MODE. 00
23:22 P0.11MODE Port 0 pin 11 control, see P0.00MODE. 00
29:24 - Reserved. NA
31:30 P0.15MODE Port 0 pin 15 control, see P0.00MODE. 00
Table 88. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description
PINMODE1 Symbol Description Reset
value
1:0 P0.16MODE Port 1 pin 16 control, see P0.00MODE. 00
3:2 P0.17MODE Port 1 pin 17 control, see P0.00MODE. 00
5:4 P0.18MODE Port 1 pin 18 control, see P0.00MODE. 00
7:6 P0.19MODE[1] Port 1 pin 19 control, see P0.00MODE. 00
9:8 P0.20MODE[1] Port 1 pin 20control, see P0.00MODE. 00
11:10 P0.21MODE[1] Port 1 pin 21 control, see P0.00MODE. 00
13:12 P0.22MODE Port 1 pin 22 control, see P0.00MODE. 00
15:14 P0.23MODE[1] Port 1 pin 23 control, see P0.00MODE. 00
17:16 P0.24MODE[1] Port 1 pin 24 control, see P0.00MODE. 00
19:18 P0.25MODE Port 1 pin 25 control, see P0.00MODE. 00
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Table 88. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description
PINMODE1 Symbol Description Reset
value
21:20 P0.26MODE Port 1 pin 26 control, see P0.00MODE. 00
29:22 - Reserved. [2] NA
31:30 - Reserved. NA
Table 89. Pin Mode select register 2 (PINMODE2 - address 0x4002 C048) bit description
PINMODE2 Symbol Description Reset
value
1:0 P1.00MODE Port 1 pin 0 control, see P0.00MODE. 00
3:2 P1.01MODE Port 1 pin 1 control, see P0.00MODE. 00
7:4 - Reserved. NA
9:8 P1.04MODE Port 1 pin 4 control, see P0.00MODE. 00
15:10 - Reserved. NA
17:16 P1.08MODE Port 1 pin 8 control, see P0.00MODE. 00
19:18 P1.09MODE Port 1 pin 9 control, see P0.00MODE. 00
21:20 P1.10MODE Port 1 pin 10 control, see P0.00MODE. 00
27:22 - Reserved. NA
29:28 P1.14MODE Port 1 pin 14 control, see P0.00MODE. 00
31:30 P1.15MODE Port 1 pin 15 control, see P0.00MODE. 00
Table 90. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description
PINMODE3 Symbol Description Reset
value
1:0 P1.16MODE[1] Port 1 pin 16 control, see P0.00MODE. 00
3:2 P1.17MODE[1] Port 1 pin 17 control, see P0.00MODE. 00
5:4 P1.18MODE Port 1 pin 18 control, see P0.00MODE. 00
7:6 P1.19MODE Port 1 pin 19 control, see P0.00MODE. 00
9:8 P1.20MODE Port 1 pin 20 control, see P0.00MODE. 00
11:10 P1.21MODE[1] Port 1 pin 21 control, see P0.00MODE. 00
13:12 P1.22MODE Port 1 pin 22 control, see P0.00MODE. 00
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Table 90. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description
PINMODE3 Symbol Description Reset
value
15:14 P1.23MODE Port 1 pin 23 control, see P0.00MODE. 00
17:16 P1.24MODE Port 1 pin 24 control, see P0.00MODE. 00
19:18 P1.25MODE Port 1 pin 25 control, see P0.00MODE. 00
21:20 P1.26MODE Port 1 pin 26 control, see P0.00MODE. 00
23:22 P1.27MODE[1] Port 1 pin 27 control, see P0.00MODE. 00
25:24 P1.28MODE Port 1 pin 28 control, see P0.00MODE. 00
27:26 P1.29MODE Port 1 pin 29 control, see P0.00MODE. 00
29:28 P1.30MODE Port 1 pin 30 control, see P0.00MODE. 00
31:30 P1.31MODE Port 1 pin 31 control, see P0.00MODE. 00
Table 91. Pin Mode select register 4 (PINMODE4 - address 0x4002 C050) bit description
PINMODE4 Symbol Description Reset
value
1:0 P2.00MODE Port 2 pin 0 control, see P0.00MODE. 00
3:2 P2.01MODE Port 2 pin 1 control, see P0.00MODE. 00
5:4 P2.02MODE Port 2 pin 2 control, see P0.00MODE. 00
7:6 P2.03MODE Port 2 pin 3 control, see P0.00MODE. 00
9:8 P2.04MODE Port 2 pin 4 control, see P0.00MODE. 00
11:10 P2.05MODE Port 2 pin 5 control, see P0.00MODE. 00
13:12 P2.06MODE Port 2 pin 6 control, see P0.00MODE. 00
15:14 P2.07MODE Port 2 pin 7 control, see P0.00MODE. 00
17:16 P2.08MODE Port 2 pin 8 control, see P0.00MODE. 00
19:18 P2.09MODE Port 2 pin 9 control, see P0.00MODE. 00
21:20 P2.10MODE Port 2 pin 10 control, see P0.00MODE. 00
23:22 P2.11MODE[1] Port 2 pin 11 control, see P0.00MODE. 00
25:24 P2.12MODE[1] Port 2 pin 12 control, see P0.00MODE. 00
27:26 P2.13MODE[1] Port 2 pin 13 control, see P0.00MODE. 00
31:28 - Reserved. NA
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Table 92. Pin Mode select register 7 (PINMODE7 - address 0x4002 C05C) bit description
PINMODE7 Symbol Description Reset
value
17:0 - Reserved NA
19:18 P3.25MODE[1] Port 3 pin 25 control, see P0.00MODE. 00
21:20 P3.26MODE[1] Port 3 pin 26 control, see P0.00MODE. 00
31:22 - Reserved. NA
Table 93. Pin Mode select register 9 (PINMODE9 - address 0x4002 C064) bit description
PINMODE9 Symbol Description Reset
value
23:0 - Reserved. NA
25:24 P4.28MODE Port 4 pin 28 control, see P0.00MODE. 00
27:26 P4.29MODE Port 4 pin 29 control, see P0.00MODE. 00
31:28 - Reserved. NA
8.5.16 Open Drain Pin Mode select register 0 (PINMODE_OD0 - 0x4002 C068)
This register controls the open drain mode for Port 0 pins. For details see Section 8.4 “Pin
mode select register values”.
Table 94. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit
description
PINMODE Symbol Value Description Reset
_OD0 value
0 P0.00OD[3] Port 0 pin 0 open drain mode control. 0
0 P0.0 pin is in the normal (not open drain) mode.
1 P0.0 pin is in the open drain mode.
1 P0.01OD[3] Port 0 pin 1 open drain mode control, see P0.00OD 0
2 P0.02OD Port 0 pin 2 open drain mode control, see P0.00OD 0
3 P0.03OD Port 0 pin 3 open drain mode control, see P0.00OD 0
4 P0.04OD Port 0 pin 4 open drain mode control, see P0.00OD 0
5 P0.05OD Port 0 pin 5 open drain mode control, see P0.00OD 0
6 P0.06OD Port 0 pin 6 open drain mode control, see P0.00OD 0
7 P0.07OD Port 0 pin 7 open drain mode control, see P0.00OD 0
8 P0.08OD Port 0 pin 8 open drain mode control, see P0.00OD 0
9 P0.09OD Port 0 pin 9 open drain mode control, see P0.00OD 0
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Table 94. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit
description
PINMODE Symbol Value Description Reset
_OD0 value
10 P0.10OD[3] Port 0 pin 10 open drain mode control, see P0.00OD 0
11 P0.11OD[3] Port 0 pin 11 open drain mode control, see P0.00OD 0
14:12 - Reserved. NA
15 P0.15OD Port 0 pin 15 open drain mode control, see P0.00OD 0
16 P0.16OD Port 0 pin 16 open drain mode control, see P0.00OD 0
17 P0.17OD Port 0 pin 17 open drain mode control, see P0.00OD 0
18 P0.18OD Port 0 pin 18 open drain mode control, see P0.00OD 0
19 P0.19OD[3] Port 0 pin 19 open drain mode control, see P0.00OD 0
20 P0.20OD[3] Port 0 pin 20open drain mode control, see P0.00OD 0
21 P0.21OD Port 0 pin 21 open drain mode control, see P0.00OD 0
22 P0.22OD Port 0 pin 22 open drain mode control, see P0.00OD 0
23 P0.23OD Port 0 pin 23 open drain mode control, see P0.00OD 0
24 P0.24OD Port 0 pin 24open drain mode control, see P0.00OD 0
25 P0.25OD Port 0 pin 25 open drain mode control, see P0.00OD 0
26 P0.26OD Port 0 pin 26 open drain mode control, see P0.00OD 0
28:27 - [2] Reserved. NA
29 P0.29OD Port 0 pin 29 open drain mode control, see P0.00OD 0
30 P0.30OD Port 0 pin 30 open drain mode control, see P0.00OD 0
31 - Reserved. NA
Table 95. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit
description
PINMODE Symbol Value Description Reset
_OD1 value
0 P1.00OD Port 1 pin 0 open drain mode control. 0
0 P1.0 pin is in the normal (not open drain) mode.
1 P1.0 pin is in the open drain mode.
1 P1.01OD Port 1 pin 1 open drain mode control, see P1.00OD 0
3:2 - Reserved. NA
4 P1.04OD Port 1 pin 4 open drain mode control, see P1.00OD 0
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Table 95. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit
description
PINMODE Symbol Value Description Reset
_OD1 value
7:5 - Reserved. NA
8 P1.08OD Port 1 pin 8 open drain mode control, see P1.00OD 0
9 P1.09OD Port 1 pin 9 open drain mode control, see P1.00OD 0
10 P1.10OD Port 1 pin 10 open drain mode control, see P1.00OD 0
13:11 - Reserved. NA
14 P1.14OD Port 1 pin 14 open drain mode control, see P1.00OD 0
15 P1.15OD Port 1 pin 15 open drain mode control, see P1.00OD 0
16 P1.16OD[1] Port 1 pin 16 open drain mode control, see P1.00OD 0
17 P1.17OD[1] Port 1 pin 17 open drain mode control, see P1.00OD 0
18 P1.18OD Port 1 pin 18 open drain mode control, see P1.00OD 0
19 P1.19OD Port 1 pin 19 open drain mode control, see P1.00OD 0
20 P1.20OD Port 1 pin 20open drain mode control, see P1.00OD 0
21 P1.21OD[1] Port 1 pin 21 open drain mode control, see P1.00OD 0
22 P1.22OD Port 1 pin 22 open drain mode control, see P1.00OD 0
23 P1.23OD Port 1 pin 23 open drain mode control, see P1.00OD 0
24 P1.24OD Port 1 pin 24open drain mode control, see P1.00OD 0
25 P1.25OD Port 1 pin 25 open drain mode control, see P1.00OD 0
26 P1.26OD Port 1 pin 26 open drain mode control, see P1.00OD 0
27 P1.27OD[1] Port 1 pin 27 open drain mode control, see P1.00OD 0
28 P1.28OD Port 1 pin 28 open drain mode control, see P1.00OD 0
29 P1.29OD Port 1 pin 29 open drain mode control, see P1.00OD 0
30 P1.30OD Port 1 pin 30 open drain mode control, see P1.00OD 0
31 P1.31OD Port 1 pin 31 open drain mode control. 0
8.5.18 Open Drain Pin Mode select register 2 (PINMODE_OD2 - 0x4002 C070)
This register controls the open drain mode for Port 2 pins. For details see Section 8.4 “Pin
mode select register values”.
Table 96. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit
description
PINMODE Symbol Value Description Reset
_OD2 value
0 P2.00OD Port 2 pin 0 open drain mode control. 0
0 P2.0 pin is in the normal (not open drain) mode.
1 P2.0 pin is in the open drain mode.
1 P2.01OD Port 2 pin 1 open drain mode control, see P2.00OD 0
2 P2.02OD Port 2 pin 2 open drain mode control, see P2.00OD 0
3 P2.03OD Port 2 pin 3 open drain mode control, see P2.00OD 0
4 P2.04OD Port 2 pin 4 open drain mode control, see P2.00OD 0
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Table 96. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit
description
PINMODE Symbol Value Description Reset
_OD2 value
5 P2.05OD Port 2 pin 5 open drain mode control, see P2.00OD 0
6 P2.06OD Port 2 pin 6 open drain mode control, see P2.00OD 0
7 P2.07OD Port 2 pin 7 open drain mode control, see P2.00OD 0
8 P2.08OD Port 2 pin 8 open drain mode control, see P2.00OD 0
9 P2.09OD Port 2 pin 9 open drain mode control, see P2.00OD 0
10 P2.10OD Port 2 pin 10 open drain mode control, see P2.00OD 0
11 P2.11OD[1] Port 2 pin 11 open drain mode control, see P2.00OD 0
12 P2.12OD[1] Port 2 pin 12 open drain mode control, see P2.00OD 0
13 P2.13OD[1] Port 2 pin 13 open drain mode control, see P2.00OD 0
31:14 - Reserved. NA
8.5.19 Open Drain Pin Mode select register 3 (PINMODE_OD3 - 0x4002 C074)
This register controls the open drain mode for Port 3 pins. For details see Section 8.4 “Pin
mode select register values”.
Table 97. Open Drain Pin Mode select register 3 (PINMODE_OD3 - address 0x4002 C074) bit
description
PINMODE Symbol Value Description Reset
_OD3 value
24:0 - Reserved. NA
25 P3.25OD[1] Port 3 pin 0 open drain mode control. 0
0 P3.25 pin is in the normal (not open drain) mode.
1 P3.25 pin is in the open drain mode.
26 P3.26OD[1] Port 3 pin 26 open drain mode control, see P3.25OD 0
31:27 - Reserved. NA
8.5.20 Open Drain Pin Mode select register 4 (PINMODE_OD4 - 0x4002 C078)
This register controls the open drain mode for Port 4 pins. For details see Section 8.4 “Pin
mode select register values”.
Table 98. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit
description
PINMODE Symbol Value Description Reset
_OD4 value
27:0 - Reserved. NA
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Table 98. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit
description
PINMODE Symbol Value Description Reset
_OD4 value
28 P4.28OD Port 4 pin 28 open drain mode control. 0
0 P4.28 pin is in the normal (not open drain) mode.
1 P4.28 pin is in the open drain mode.
29 P4.28OD Port 4 pin 29 open drain mode control, see P4.28OD 0
31:30 - Reserved. NA
Table 99. I2C Pin Configuration register (I2CPADCFG - address 0x4002 C07C) bit
description
I2CPADCFG Symbol Value Description Reset
value
0 SDADRV0 Drive mode control for the SDA0 pin, P0.27. 0
0 The SDA0 pin is in the standard drive mode.
1 The SDA0 pin is in Fast Mode Plus drive mode.
1 SDAI2C0 I2C mode control for the SDA0 pin, P0.27. 0
0 The SDA0 pin has I2C glitch filtering and slew rate
control enabled.
1 The SDA0 pin has I2C glitch filtering and slew rate
control disabled.
2 SCLDRV0 Drive mode control for the SCL0 pin, P0.28. 0
0 The SCL0 pin is in the standard drive mode.
1 The SCL0 pin is in Fast Mode Plus drive mode.
3 SCLI2C0 I2C mode control for the SCL0 pin, P0.28. 0
0 The SCL0 pin has I2C glitch filtering and slew rate
control enabled.
1 The SCL0 pin has I2C glitch filtering and slew rate
control disabled.
31:4 - Reserved. NA
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9.2 Features
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• Registers provide a software view of pending rising edge interrupts, pending falling
edge interrupts, and overall pending GPIO interrupts.
• GPIO0 and GPIO2 interrupts share the same position in the NVIC with External
Interrupt 3.
9.3 Applications
• General purpose I/O
• Driving LEDs or other indicators
• Controlling off-chip devices
• Sensing digital inputs, detecting edges
• Bringing the part out of Power-down mode
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The registers in Table 101 represent the enhanced GPIO features available on all of the
GPIO ports. These registers are located on an AHB bus for fast read and write timing.
They can all be accessed in byte, half-word, and word sizes. A mask register allows
access to a group of bits in a single GPIO port independently from other bits in the same
port.
Table 101. GPIO register map (local bus accessible registers - enhanced GPIO features)
Generic Description Access Reset PORTn Register
Name value[1] Name & Address
FIODIR Fast GPIO Port Direction control register. This register R/W 0 FIO0DIR - 0x2009 C000
individually controls the direction of each port pin. FIO1DIR - 0x2009 C020
FIO2DIR - 0x2009 C040
FIO3DIR - 0x2009 C060
FIO4DIR - 0x2009 C080
FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to R/W 0 FIO0MASK - 0x2009 C010
port (done via writes to FIOPIN, FIOSET, and FIOCLR, and FIO1MASK - 0x2009 C030
reads of FIOPIN) alter or return only the bits enabled by zeros FIO2MASK - 0x2009 C050
in this register. FIO3MASK - 0x2009 C070
FIO4MASK - 0x2009 C090
FIOPIN Fast Port Pin value register using FIOMASK. The current state R/W 0 FIO0PIN - 0x2009 C014
of digital port pins can be read from this register, regardless of FIO1PIN - 0x2009 C034
pin direction or alternate function selection (as long as pins are FIO2PIN - 0x2009 C054
not configured as an input to ADC). The value read is masked FIO3PIN - 0x2009 C074
by ANDing with inverted FIOMASK. Writing to this register FIO4PIN - 0x2009 C094
places corresponding values in all bits enabled by zeros in
FIOMASK.
Important: if an FIOPIN register is read, its bit(s) masked with
1 in the FIOMASK register will be read as 0 regardless of the
physical pin state.
FIOSET Fast Port Output Set register using FIOMASK. This register R/W 0 FIO0SET - 0x2009 C018
controls the state of output pins. Writing 1s produces highs at FIO1SET - 0x2009 C038
the corresponding port pins. Writing 0s has no effect. Reading FIO2SET - 0x2009 C058
this register returns the current contents of the port output FIO3SET - 0x2009 C078
register. Only bits enabled by 0 in FIOMASK can be altered. FIO4SET - 0x2009 C098
FIOCLR Fast Port Output Clear register using FIOMASK. This register WO 0 FIO0CLR - 0x2009 C01C
controls the state of output pins. Writing 1s produces lows at FIO1CLR - 0x2009 C03C
the corresponding port pins. Writing 0s has no effect. Only bits FIO2CLR - 0x2009 C05C
enabled by 0 in FIOMASK can be altered. FIO3CLR - 0x2009 C07C
FIO4CLR - 0x2009 C09C
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
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[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Note that GPIO pins P0.29 and P0.30 are shared with the USB_D+ and USB_D- pins and
must have the same direction. If either FIO0DIR bit 29 or 30 are configured as zero, both
P0.29 and P0.30 will be inputs. If both FIO0DIR bits 29 and 30 are ones, both P0.29 and
P0.30 will be outputs.
Table 103. Fast GPIO port Direction register FIO0DIR to FIO4DIR - addresses 0x2009 C000 to
0x2009 C080) bit description
Bit Symbol Value Description Reset
value
31:0 FIO0DIR Fast GPIO Direction PORTx control bits. Bit 0 in FIOxDIR 0x0
FIO1DIR controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31.
FIO2DIR 0 Controlled pin is input.
FIO3DIR
FIO4DIR 1 Controlled pin is output.
Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
Table 104, too. Next to providing the same functions as the FIODIR register, these
additional registers allow easier and faster access to the physical port pins.
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Table 104. Fast GPIO port Direction control byte and half-word accessible register
description
Generic Description Register Reset PORTn Register
Register length (bits) value Address & Name
name & access
FIOxDIR0 Fast GPIO Port x Direction 8 (byte) 0x00 FIO0DIR0 - 0x2009 C000
control register 0. Bit 0 in R/W FIO1DIR0 - 0x2009 C020
FIOxDIR0 register corresponds FIO2DIR0 - 0x2009 C040
to pin Px.0 … bit 7 to pin Px.7. FIO3DIR0 - 0x2009 C060
FIO4DIR0 - 0x2009 C080
FIOxDIR1 Fast GPIO Port x Direction 8 (byte) 0x00 FIO0DIR1 - 0x2009 C001
control register 1. Bit 0 in R/W FIO1DIR1 - 0x2009 C021
FIOxDIR1 register corresponds FIO2DIR1 - 0x2009 C041
to pin Px.8 … bit 7 to pin Px.15. FIO3DIR1 - 0x2009 C061
FIO4DIR1 - 0x2009 C081
FIOxDIR2 Fast GPIO Port x Direction 8 (byte) 0x00 FIO0DIR2 - 0x2009 C002
control register 2. Bit 0 in R/W FIO1DIR2 - 0x2009 C022
FIOxDIR2 register corresponds FIO2DIR2 - 0x2009 C042
to pin Px.16 … bit 7 to pin FIO3DIR2 - 0x2009 C062
Px.23. FIO4DIR2 - 0x2009 C082
FIOxDIR3 Fast GPIO Port x Direction 8 (byte) 0x00 FIO0DIR3 - 0x2009 C003
control register 3. Bit 0 in R/W FIO1DIR3 - 0x2009 C023
FIOxDIR3 register corresponds FIO2DIR3 - 0x2009 C043
to pin Px.24 … bit 7 to pin FIO3DIR3 - 0x2009 C063
Px.31. FIO4DIR3 - 0x2009 C083
FIOxDIRL Fast GPIO Port x Direction 16 (half-word) 0x0000 FIO0DIRL - 0x2009 C000
control Lower half-word R/W FIO1DIRL - 0x2009 C020
register. Bit 0 in FIOxDIRL FIO2DIRL - 0x2009 C040
register corresponds to pin FIO3DIRL - 0x2009 C060
Px.0 … bit 15 to pin Px.15. FIO4DIRL - 0x2009 C080
FIOxDIRU Fast GPIO Port x Direction 16 (half-word) 0x0000 FIO0DIRU - 0x2009 C002
control Upper half-word R/W FIO1DIRU - 0x2009 C022
register. Bit 0 in FIOxDIRU FIO2DIRU - 0x2009 C042
register corresponds to Px.16 FIO3DIRU - 0x2009 C062
… bit 15 to Px.31. FIO4DIRU - 0x2009 C082
9.5.2 GPIO port output Set register FIOxSET (FIO0SET to FIO4SET - 0x2009
C018 to 0x2009 C098)
This register is used to produce a HIGH level output at the port pins configured as GPIO in
an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins.
Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing
1 to the corresponding bit in the FIOxSET has no effect.
Reading the FIOxSET register returns the value of this register, as determined by
previous writes to FIOxSET and FIOxCLR (or FIOxPIN as noted above). This value does
not reflect the effect of any outside world influence on the I/O pins.
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Access to a port pin via the FIOxSET register is conditioned by the corresponding bit of
the FIOxMASK register (see Section 9.5.5).
Table 105. Fast GPIO port output Set register (FIO0SET to FIO4SET - addresses 0x2009 C018
to 0x2009 C098) bit description
Bit Symbol Value Description Reset
value
31:0 FIO0SET Fast GPIO output value Set bits. Bit 0 in FIOxSET controls pin 0x0
FIO1SET Px.0, bit 31 in FIOxSET controls pin Px.31.
FIO2SET 0 Controlled pin output is unchanged.
FIO3SET
FIO4SET 1 Controlled pin output is set to HIGH.
Aside from the 32-bit long and word only accessible FIOxSET register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 106, too. Next to providing the same functions as the FIOxSET register, these
additional registers allow easier and faster access to the physical port pins.
Table 106. Fast GPIO port output Set byte and half-word accessible register description
Generic Description Register Reset PORTn Register
Register length (bits) value Address & Name
name & access
FIOxSET0 Fast GPIO Port x output Set 8 (byte) 0x00 FIO0SET0 - 0x2009 C018
register 0. Bit 0 in FIOxSET0 R/W FIO1SET0 - 0x2009 C038
register corresponds to pin FIO2SET0 - 0x2009 C058
Px.0 … bit 7 to pin Px.7. FIO3SET0 - 0x2009 C078
FIO4SET0 - 0x2009 C098
FIOxSET1 Fast GPIO Port x output Set 8 (byte) 0x00 FIO0SET1 - 0x2009 C019
register 1. Bit 0 in FIOxSET1 R/W FIO1SET1 - 0x2009 C039
register corresponds to pin FIO2SET1 - 0x2009 C059
Px.8 … bit 7 to pin Px.15. FIO3SET1 - 0x2009 C079
FIO4SET1 - 0x2009 C099
FIOxSET2 Fast GPIO Port x output Set 8 (byte) 0x00 FIO0SET2 - 0x2009 C01A
register 2. Bit 0 in FIOxSET2 R/W FIO1SET2 - 0x2009 C03A
register corresponds to pin FIO2SET2 - 0x2009 C05A
Px.16 … bit 7 to pin Px.23. FIO3SET2 - 0x2009 C07A
FIO4SET2 - 0x2009 C09A
FIOxSET3 Fast GPIO Port x output Set 8 (byte) 0x00 FIO0SET3 - 0x2009 C01B
register 3. Bit 0 in FIOxSET3 R/W FIO1SET3 - 0x2009 C03B
register corresponds to pin FIO2SET3 - 0x2009 C05B
Px.24 … bit 7 to pin Px.31. FIO3SET3 - 0x2009 C07B
FIO4SET3 - 0x2009 C09B
FIOxSETL Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETL - 0x2009 C018
Lower half-word register. Bit 0 R/W FIO1SETL - 0x2009 C038
in FIOxSETL register FIO2SETL - 0x2009 C058
corresponds to pin Px.0 … bit FIO3SETL - 0x2009 C078
15 to pin Px.15. FIO4SETL - 0x2009 C098
FIOxSETU Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETU - 0x2009 C01A
Upper half-word register. Bit 0 R/W FIO1SETU - 0x2009 C03A
in FIOxSETU register FIO2SETU - 0x2009 C05A
corresponds to Px.16 … bit FIO3SETU - 0x2009 C07A
15 to Px.31. FIO4SETU - 0x2009 C09A
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Access to a port pin via the FIOxCLR register is conditioned by the corresponding bit of
the FIOxMASK register (see Section 9.5.5).
Table 107. Fast GPIO port output Clear register (FIO0CLR to FIO4CLR- addresses 0x2009
C01C to 0x2009 C09C) bit description
Bit Symbol Value Description Reset
value
31:0 FIO0CLR Fast GPIO output value Clear bits. Bit 0 in FIOxCLR controls pin 0x0
FIO1CLR Px.0, bit 31 controls pin Px.31.
FIO2CLR 0 Controlled pin output is unchanged.
FIO3CLR
FIO4CLR 1 Controlled pin output is set to LOW.
Aside from the 32-bit long and word only accessible FIOxCLR register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 108, too. Next to providing the same functions as the FIOxCLR register, these
additional registers allow easier and faster access to the physical port pins.
Table 108. Fast GPIO port output Clear byte and half-word accessible register description
Generic Description Register Reset PORTn Register
Register length (bits) value Address & Name
name & access
FIOxCLR0 Fast GPIO Port x output 8 (byte) 0x00 FIO0CLR0 - 0x2009 C01C
Clear register 0. Bit 0 in WO FIO1CLR0 - 0x2009 C03C
FIOxCLR0 register FIO2CLR0 - 0x2009 C05C
corresponds to pin Px.0 … FIO3CLR0 - 0x2009 C07C
bit 7 to pin Px.7. FIO4CLR0 - 0x2009 C09C
FIOxCLR1 Fast GPIO Port x output 8 (byte) 0x00 FIO0CLR1 - 0x2009 C01D
Clear register 1. Bit 0 in WO FIO1CLR1 - 0x2009 C03D
FIOxCLR1 register FIO2CLR1 - 0x2009 C05D
corresponds to pin Px.8 … FIO3CLR1 - 0x2009 C07D
bit 7 to pin Px.15. FIO4CLR1 - 0x2009 C09D
FIOxCLR2 Fast GPIO Port x output 8 (byte) 0x00 FIO0CLR2 - 0x2009 C01E
Clear register 2. Bit 0 in WO FIO1CLR2 - 0x2009 C03E
FIOxCLR2 register FIO2CLR2 - 0x2009 C05E
corresponds to pin Px.16 … FIO3CLR2 - 0x2009 C07E
bit 7 to pin Px.23. FIO4CLR2 - 0x2009 C09E
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Table 108. Fast GPIO port output Clear byte and half-word accessible register description
Generic Description Register Reset PORTn Register
Register length (bits) value Address & Name
name & access
FIOxCLR3 Fast GPIO Port x output 8 (byte) 0x00 FIO0CLR3 - 0x2009 C01F
Clear register 3. Bit 0 in WO FIO1CLR3 - 0x2009 C03F
FIOxCLR3 register FIO2CLR3 - 0x2009 C05F
corresponds to pin Px.24 … FIO3CLR3 - 0x2009 C07F
bit 7 to pin Px.31. FIO4CLR3 - 0x2009 C09F
FIOxCLRL Fast GPIO Port x output 16 (half-word) 0x0000 FIO0CLRL - 0x2009 C01C
Clear Lower half-word WO FIO1CLRL - 0x2009 C03C
register. Bit 0 in FIOxCLRL FIO2CLRL - 0x2009 C05C
register corresponds to pin FIO3CLRL - 0x2009 C07C
Px.0 … bit 15 to pin Px.15. FIO4CLRL - 0x2009 C09C
FIOxCLRU Fast GPIO Port x output 16 (half-word) 0x0000 FIO0CLRU - 0x2009 C01E
Clear Upper half-word WO FIO1CLRU - 0x2009 C03E
register. Bit 0 in FIOxCLRU FIO2CLRU - 0x2009 C05E
register corresponds to pin FIO3CLRU - 0x2009 C07E
Px.16 … bit 15 to Px.31. FIO4CLRU - 0x2009 C09E
9.5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009
C014 to 0x2009 C094)
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to be
read from the corresponding FIOxPIN register.
If a pin has an analog function as one of its options, the pin state cannot be read if the
analog configuration is selected. Selecting the pin as an A/D input disconnects the digital
features of the pin. In that case, the pin value read in the FIOxPIN register is not valid.
Writing to the FIOxPIN register stores the value in the port output register, bypassing the
need to use both the FIOxSET and FIOxCLR registers to obtain the entire written value.
This feature should be used carefully in an application since it affects the entire port.
Access to a port pin via the FIOxPIN register is conditioned by the corresponding bit of
the FIOxMASK register (see Section 9.5.5).
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Only pins masked with zeros in the Mask register (see Section 9.5.5) will be correlated to
the current content of the Fast GPIO port pin value register.
Table 109. Fast GPIO port Pin value register (FIO0PIN to FIO4PIN- addresses 0x2009 C014 to
0x2009 C094) bit description
Bit Symbol Value Description Reset
value
31:0 FIO0VAL Fast GPIO output value bits. Bit 0 corresponds to pin Px.0, bit 31 0x0
FIO1VAL corresponds to pin Px.31. Only bits also set to 0 in the
FIO2VAL FIOxMASK register are affected by a write or show the pin’s
FIO3VAL actual logic state.
FIO4VAL 0 Reading a 0 indicates that the port pin’s current state is LOW.
Writing a 0 sets the output register value to LOW.
1 Reading a 1 indicates that the port pin’s current state is HIGH.
Writing a 1 sets the output register value to HIGH.
Aside from the 32-bit long and word only accessible FIOxPIN register, every fast GPIO
port can also be controlled via several byte and half-word accessible register listed in
Table 110, too. Next to providing the same functions as the FIOxPIN register, these
additional registers allow easier and faster access to the physical port pins.
Table 110. Fast GPIO port Pin value byte and half-word accessible register description
Generic Description Register Reset PORTn Register
Register length (bits) value Address & Name
name & access
FIOxPIN0 Fast GPIO Port x Pin value 8 (byte) 0x00 FIO0PIN0 - 0x2009 C014
register 0. Bit 0 in FIOxPIN0 R/W FIO1PIN0 - 0x2009 C034
register corresponds to pin FIO2PIN0 - 0x2009 C054
Px.0 … bit 7 to pin Px.7. FIO3PIN0 - 0x2009 C074
FIO4PIN0 - 0x2009 C094
FIOxPIN1 Fast GPIO Port x Pin value 8 (byte) 0x00 FIO0PIN1 - 0x2009 C015
register 1. Bit 0 in FIOxPIN1 R/W FIO1PIN1 - 0x2009 C035
register corresponds to pin FIO2PIN1 - 0x2009 C055
Px.8 … bit 7 to pin Px.15. FIO3PIN1 - 0x2009 C075
FIO4PIN1 - 0x2009 C095
FIOxPIN2 Fast GPIO Port x Pin value 8 (byte) 0x00 FIO0PIN2 - 0x2009 C016
register 2. Bit 0 in FIOxPIN2 R/W FIO1PIN2 - 0x2009 C036
register corresponds to pin FIO2PIN2 - 0x2009 C056
Px.16 … bit 7 to pin Px.23. FIO3PIN2 - 0x2009 C076
FIO4PIN2 - 0x2009 C096
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Table 110. Fast GPIO port Pin value byte and half-word accessible register description
Generic Description Register Reset PORTn Register
Register length (bits) value Address & Name
name & access
FIOxPIN3 Fast GPIO Port x Pin value 8 (byte) 0x00 FIO0PIN3 - 0x2009 C017
register 3. Bit 0 in FIOxPIN3 R/W FIO1PIN3 - 0x2009 C037
register corresponds to pin FIO2PIN3 - 0x2009 C057
Px.24 … bit 7 to pin Px.31. FIO3PIN3 - 0x2009 C077
FIO4PIN3 - 0x2009 C097
FIOxPINL Fast GPIO Port x Pin value 16 (half-word) 0x0000 FIO0PINL - 0x2009 C014
Lower half-word register. Bit 0 R/W FIO1PINL - 0x2009 C034
in FIOxPINL register FIO2PINL - 0x2009 C054
corresponds to pin Px.0 … bit FIO3PINL - 0x2009 C074
15 to pin Px.15. FIO4PINL - 0x2009 C094
FIOxPINU Fast GPIO Port x Pin value 16 (half-word) 0x0000 FIO0PINU - 0x2009 C016
Upper half-word register. Bit 0 R/W FIO1PINU - 0x2009 C036
in FIOxPINU register FIO2PINU - 0x2009 C056
corresponds to pin Px.16 … bit FIO3PINU - 0x2009 C076
15 to Px.31. FIO4PINU - 0x2009 C096
A zero in this register’s bit enables an access to the corresponding physical pin via a read
or write access. If a bit in this register is one, corresponding pin will not be changed with
write access and if read, will not be reflected in the updated FIOxPIN register. For
software examples, see Section 9.6.
Table 111. Fast GPIO port Mask register (FIO0MASK to FIO4MASK - addresses 0x2009 C010
to 0x2009 C090) bit description
Bit Symbol Value Description Reset
value
31:0 FIO0MASK Fast GPIO physical pin access control. 0x0
FIO1MASK 0 Controlled pin is affected by writes to the port’s FIOxSET,
FIO2MASK FIOxCLR, and FIOxPIN register(s). Current state of the pin
FIO3MASK can be read from the FIOxPIN register.
FIO4MASK
1 Controlled pin is not affected by writes into the port’s
FIOxSET, FIOxCLR and FIOxPIN register(s). When the
FIOxPIN register is read, this bit will not be updated with the
state of the physical pin.
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Aside from the 32-bit long and word only accessible FIOxMASK register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 112, too. Next to providing the same functions as the FIOxMASK register, these
additional registers allow easier and faster access to the physical port pins.
Table 112. Fast GPIO port Mask byte and half-word accessible register description
Generic Description Register Reset PORTn Register
Register length (bits) value Address & Name
name & access
FIOxMASK0 Fast GPIO Port x Mask 8 (byte) 0x0 FIO0MASK0 - 0x2009 C010
register 0. Bit 0 in R/W FIO1MASK0 - 0x2009 C030
FIOxMASK0 register FIO2MASK0 - 0x2009 C050
corresponds to pin Px.0 … FIO3MASK0 - 0x2009 C070
bit 7 to pin Px.7. FIO4MASK0 - 0x2009 C090
FIOxMASK1 Fast GPIO Port x Mask 8 (byte) 0x0 FIO0MASK1 - 0x2009 C011
register 1. Bit 0 in R/W FIO1MASK1 - 0x2009 C031
FIOxMASK1 register FIO2MASK1 - 0x2009 C051
corresponds to pin Px.8 … FIO3MASK1 - 0x2009 C071
bit 7 to pin Px.15. FIO4MASK1 - 0x2009 C091
FIOxMASK2 Fast GPIO Port x Mask 8 (byte) 0x0 FIO0MASK2 - 0x2009 C012
register 2. Bit 0 in R/W FIO1MASK2 - 0x2009 C032
FIOxMASK2 register FIO2MASK2 - 0x2009 C052
corresponds to pin Px.16 … FIO3MASK2 - 0x2009 C072
bit 7 to pin Px.23. FIO4MASK2 - 0x2009 C092
FIOxMASK3 Fast GPIO Port x Mask 8 (byte) 0x0 FIO0MASK3 - 0x2009 C013
register 3. Bit 0 in R/W FIO1MASK3 - 0x2009 C033
FIOxMASK3 register FIO2MASK3 - 0x2009 C053
corresponds to pin Px.24 … FIO3MASK3 - 0x2009 C073
bit 7 to pin Px.31. FIO4MASK3 - 0x2009 C093
FIOxMASKL Fast GPIO Port x Mask 16 0x0 FIO0MASKL - 0x2009 C010
Lower half-word register. (half-word) FIO1MASKL - 0x2009 C030
Bit 0 in FIOxMASKL R/W FIO2MASKL - 0x2009 C050
register corresponds to pin FIO3MASKL - 0x2009 C070
Px.0 … bit 15 to pin Px.15. FIO4MASKL - 0x2009 C090
FIOxMASKU Fast GPIO Port x Mask 16 0x0 FIO0MASKU - 0x2009 C012
Upper half-word register. (half-word) FIO1MASKU - 0x2009 C032
Bit 0 in FIOxMASKU R/W FIO2MASKU - 0x2009 C052
register corresponds to pin FIO3MASKU - 0x2009 C072
Px.16 … bit 15 to Px.31. FIO4MASKU - 0x2009 C092
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Table 113. GPIO overall Interrupt Status register (IOIntStatus - address 0x4002 8080) bit
description
Bit Symbol Value Description Reset
value
0 P0Int Port 0 GPIO interrupt pending. 0
0 There are no pending interrupts on Port 0.
1 There is at least one pending interrupt on Port 0.
1 - - Reserved. The value read from a reserved bit is not defined. NA
2 P2Int Port 2 GPIO interrupt pending. 0
0 There are no pending interrupts on Port 2.
1 There is at least one pending interrupt on Port 2.
31:2 - - Reserved. The value read from a reserved bit is not defined. NA
9.5.6.2 GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090)
Each bit in these read-write registers enables the rising edge interrupt for the
corresponding port 0 pin.
Table 114. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit
description
Bit Symbol Value Description Reset
value
0 P0.0ER Enable rising edge interrupt for P0.0. 0
0 Rising edge interrupt is disabled on P0.0.
1 Rising edge interrupt is enabled on P0.0.
1 P0.1ER Enable rising edge interrupt for P0.1. 0
2 P0.2ER Enable rising edge interrupt for P0.2. 0
3 P0.3ER Enable rising edge interrupt for P0.3. 0
4 P0.4ER[1] Enable rising edge interrupt for P0.4. 0
5 P0.5ER[1] Enable rising edge interrupt for P0.5. 0
6 P0.6ER Enable rising edge interrupt for P0.6. 0
7 P0.7ER Enable rising edge interrupt for P0.7. 0
8 P0.8ER Enable rising edge interrupt for P0.8. 0
9 P0.9ER Enable rising edge interrupt for P0.9. 0
10 P0.10ER Enable rising edge interrupt for P0.10. 0
11 P0.11ER Enable rising edge interrupt for P0.11. 0
14:12 - Reserved NA
15 P0.15ER Enable rising edge interrupt for P0.15. 0
16 P0.16ER Enable rising edge interrupt for P0.16. 0
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Table 114. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit
description
Bit Symbol Value Description Reset
value
17 P0.17ER Enable rising edge interrupt for P0.17. 0
18 P0.18ER Enable rising edge interrupt for P0.18. 0
19 P0.19ER[1] Enable rising edge interrupt for P0.19. 0
20 P0.20ER[1] Enable rising edge interrupt for P0.20. 0
21 P0.21ER[1] Enable rising edge interrupt for P0.21. 0
22 P0.22ER Enable rising edge interrupt for P0.22. 0
23 P0.23ER[1] Enable rising edge interrupt for P0.23. 0
24 P0.24ER[1] Enable rising edge interrupt for P0.24. 0
25 P0.25ER Enable rising edge interrupt for P0.25. 0
26 P0.26ER Enable rising edge interrupt for P0.26. 0
27 P0.27ER[1] Enable rising edge interrupt for P0.27. 0
28 P0.28ER[1] Enable rising edge interrupt for P0.28. 0
29 P0.29ER Enable rising edge interrupt for P0.29. 0
30 P0.30ER Enable rising edge interrupt for P0.30. 0
31 - Reserved. NA
9.5.6.3 GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0)
Each bit in these read-write registers enables the rising edge interrupt for the
corresponding port 2 pin.
Table 115. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit
description
Bit Symbol Value Description Reset
value
0 P2.0ER Enable rising edge interrupt for P2.0. 0
0 Rising edge interrupt is disabled on P2.0.
1 Rising edge interrupt is enabled on P2.0.
1 P2.1ER Enable rising edge interrupt for P2.1. 0
2 P2.2ER Enable rising edge interrupt for P2.2. 0
3 P2.3ER Enable rising edge interrupt for P2.3. 0
4 P2.4ER Enable rising edge interrupt for P2.4. 0
5 P2.5ER Enable rising edge interrupt for P2.5. 0
6 P2.6ER Enable rising edge interrupt for P2.6. 0
7 P2.7ER Enable rising edge interrupt for P2.7. 0
8 P2.8ER Enable rising edge interrupt for P2.8. 0
9 P2.9ER Enable rising edge interrupt for P2.9. 0
10 P2.10ER Enable rising edge interrupt for P2.10. 0
11 P2.11ER[1] Enable rising edge interrupt for P2.11. 0
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Table 115. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit
description
Bit Symbol Value Description Reset
value
12 P2.12ER[1] Enable rising edge interrupt for P2.12. 0
13 P2.13ER[1] Enable rising edge interrupt for P2.13. 0
31:14 - Reserved. NA
9.5.6.4 GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - 0x4002 8094)
Each bit in these read-write registers enables the falling edge interrupt for the
corresponding GPIO port 0 pin.
Table 116. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094)
bit description
Bit Symbol Value Description Reset
value
0 P0.0EF Enable falling edge interrupt for P0.0 0
0 Falling edge interrupt is disabled on P0.0.
1 Falling edge interrupt is enabled on P0.0.
1 P0.1EF Enable falling edge interrupt for P0.1. 0
2 P0.2EF Enable falling edge interrupt for P0.2. 0
3 P0.3EF Enable falling edge interrupt for P0.3. 0
4 P0.4EF[1] Enable falling edge interrupt for P0.4. 0
5 P0.5EF[1] Enable falling edge interrupt for P0.5. 0
6 P0.6EF Enable falling edge interrupt for P0.6. 0
7 P0.7EF Enable falling edge interrupt for P0.7. 0
8 P0.8EF Enable falling edge interrupt for P0.8. 0
9 P0.9EF Enable falling edge interrupt for P0.9. 0
10 P0.10EF Enable falling edge interrupt for P0.10. 0
11 P0.11EF Enable falling edge interrupt for P0.11. 0
14:12 - Reserved. NA
15 P0.15EF Enable falling edge interrupt for P0.15. 0
16 P0.16EF Enable falling edge interrupt for P0.16. 0
17 P0.17EF Enable falling edge interrupt for P0.17. 0
18 P0.18EF Enable falling edge interrupt for P0.18. 0
19 P0.19EF[1] Enable falling edge interrupt for P0.19. 0
20 P0.20EF[1] Enable falling edge interrupt for P0.20. 0
21 P0.21EF[1] Enable falling edge interrupt for P0.21. 0
22 P0.22EF Enable falling edge interrupt for P0.22. 0
23 P0.23EF[1] Enable falling edge interrupt for P0.23. 0
24 P0.24EF[1] Enable falling edge interrupt for P0.24. 0
25 P0.25EF Enable falling edge interrupt for P0.25. 0
26 P0.26EF Enable falling edge interrupt for P0.26. 0
27 P0.27EF[1] Enable falling edge interrupt for P0.27. 0
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Table 116. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094)
bit description
Bit Symbol Value Description Reset
value
28 P0.28EF[1] Enable falling edge interrupt for P0.28. 0
29 P0.29EF Enable falling edge interrupt for P0.29. 0
30 P0.30EF Enable falling edge interrupt for P0.30. 0
31 - Reserved. NA
9.5.6.5 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4)
Each bit in these read-write registers enables the falling edge interrupt for the
corresponding GPIO port 2 pin.
Table 117. GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) bit
description
Bit Symbol Value Description Reset
value
0 P2.0EF Enable falling edge interrupt for P2.0 0
0 Falling edge interrupt is disabled on P2.0.
1 Falling edge interrupt is enabled on P2.0.
1 P2.1EF Enable falling edge interrupt for P2.1. 0
2 P2.2EF Enable falling edge interrupt for P2.2. 0
3 P2.3EF Enable falling edge interrupt for P2.3. 0
4 P2.4EF Enable falling edge interrupt for P2.4. 0
5 P2.5EF Enable falling edge interrupt for P2.5. 0
6 P2.6EF Enable falling edge interrupt for P2.6. 0
7 P2.7EF Enable falling edge interrupt for P2.7. 0
8 P2.8EF Enable falling edge interrupt for P2.8. 0
9 P2.9EF Enable falling edge interrupt for P2.9. 0
10 P2.10EF Enable falling edge interrupt for P2.10. 0
11 P2.11EF[1] Enable falling edge interrupt for P2.11. 0
12 P2.12EF[1] Enable falling edge interrupt for P2.12. 0
13 P2.13EF[1] Enable falling edge interrupt for P2.13. 0
31:14 - Reserved. NA
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9.5.6.6 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR -
0x4002 8084)
Each bit in these read-only registers indicates the rising edge interrupt status for port 0.
Table 118. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084)
bit description
Bit Symbol Value Description Reset
value
0 P0.0REI Status of Rising Edge Interrupt for P0.0 0
0 A rising edge has not been detected on P0.0.
1 Interrupt has been generated due to a rising edge on P0.0.
1 P0.1REI Status of Rising Edge Interrupt for P0.1. 0
2 P0.2REI Status of Rising Edge Interrupt for P0.2. 0
3 P0.3REI Status of Rising Edge Interrupt for P0.3. 0
4 P0.4REI[1] Status of Rising Edge Interrupt for P0.4. 0
5 P0.5REI[1] Status of Rising Edge Interrupt for P0.5. 0
6 P0.6REI Status of Rising Edge Interrupt for P0.6. 0
7 P0.7REI Status of Rising Edge Interrupt for P0.7. 0
8 P0.8REI Status of Rising Edge Interrupt for P0.8. 0
9 P0.9REI Status of Rising Edge Interrupt for P0.9. 0
10 P0.10REI Status of Rising Edge Interrupt for P0.10. 0
11 P0.11REI Status of Rising Edge Interrupt for P0.11. 0
14:12 - Reserved. NA
15 P0.15REI Status of Rising Edge Interrupt for P0.15. 0
16 P0.16REI Status of Rising Edge Interrupt for P0.16. 0
17 P0.17REI Status of Rising Edge Interrupt for P0.17. 0
18 P0.18REI Status of Rising Edge Interrupt for P0.18. 0
19 P0.19REI[1] Status of Rising Edge Interrupt for P0.19. 0
20 P0.20REI[1] Status of Rising Edge Interrupt for P0.20. 0
21 P0.21REI[1] Status of Rising Edge Interrupt for P0.21. 0
22 P0.22REI Status of Rising Edge Interrupt for P0.22. 0
23 P0.23REI[1] Status of Rising Edge Interrupt for P0.23. 0
24 P0.24REI[1] Status of Rising Edge Interrupt for P0.24. 0
25 P0.25REI Status of Rising Edge Interrupt for P0.25. 0
26 P0.26REI Status of Rising Edge Interrupt for P0.26. 0
27 P0.27REI[1] Status of Rising Edge Interrupt for P0.27. 0
28 P0.28REI[1] Status of Rising Edge Interrupt for P0.28. 0
29 P0.29REI Status of Rising Edge Interrupt for P0.29. 0
30 P0.30REI Status of Rising Edge Interrupt for P0.30. 0
31 - Reserved. NA
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9.5.6.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR -
0x4002 80A4)
Each bit in these read-only registers indicates the rising edge interrupt status for port 2.
Table 119. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4)
bit description
Bit Symbol Value Description Reset
value
0 P2.0REI Status of Rising Edge Interrupt for P2.0 0
0 A rising edge has not been detected on P2.0.
1 Interrupt has been generated due to a rising edge on P2.0.
1 P2.1REI Status of Rising Edge Interrupt for P2.1. 0
2 P2.2REI Status of Rising Edge Interrupt for P2.2. 0
3 P2.3REI Status of Rising Edge Interrupt for P2.3. 0
4 P2.4REI Status of Rising Edge Interrupt for P2.4. 0
5 P2.5REI Status of Rising Edge Interrupt for P2.5. 0
6 P2.6REI Status of Rising Edge Interrupt for P2.6. 0
7 P2.7REI Status of Rising Edge Interrupt for P2.7. 0
8 P2.8REI Status of Rising Edge Interrupt for P2.8. 0
9 P2.9REI Status of Rising Edge Interrupt for P2.9. 0
10 P2.10REI Status of Rising Edge Interrupt for P2.10. 0
11 P2.11REI[1] Status of Rising Edge Interrupt for P2.11. 0
12 P2.12REI[1] Status of Rising Edge Interrupt for P2.12. 0
13 P2.13REI[1] Status of Rising Edge Interrupt for P2.13. 0
31:14 - Reserved. NA
9.5.6.8 GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF -
0x4002 8088)
Each bit in these read-only registers indicates the falling edge interrupt status for port 0.
Table 120. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088)
bit description
Bit Symbol Value Description Reset
value
0 P0.0FEI Status of Falling Edge Interrupt for P0.0 0
0 A falling edge has not been detected on P0.0.
1 Interrupt has been generated due to a falling edge on P0.0.
1 P0.1FEI Status of Falling Edge Interrupt for P0.1. 0
2 P0.2FEI Status of Falling Edge Interrupt for P0.2. 0
3 P0.3FEI Status of Falling Edge Interrupt for P0.3. 0
4 P0.4FEI[1] Status of Falling Edge Interrupt for P0.4. 0
5 P0.5FEI[1] Status of Falling Edge Interrupt for P0.5. 0
6 P0.6FEI Status of Falling Edge Interrupt for P0.6. 0
7 P0.7FEI Status of Falling Edge Interrupt for P0.7. 0
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Table 120. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088)
bit description
Bit Symbol Value Description Reset
value
8 P0.8FEI Status of Falling Edge Interrupt for P0.8. 0
9 P0.9FEI Status of Falling Edge Interrupt for P0.9. 0
10 P0.10FEI Status of Falling Edge Interrupt for P0.10. 0
11 P0.11FEI Status of Falling Edge Interrupt for P0.11. 0
14:12 - Reserved. NA
15 P0.15FEI Status of Falling Edge Interrupt for P0.15. 0
16 P0.16FEI Status of Falling Edge Interrupt for P0.16. 0
17 P0.17FEI Status of Falling Edge Interrupt for P0.17. 0
18 P0.18FEI Status of Falling Edge Interrupt for P0.18. 0
19 P0.19FEI[1] Status of Falling Edge Interrupt for P0.19. 0
20 P0.20FEI[1] Status of Falling Edge Interrupt for P0.20. 0
21 P0.21FEI[1] Status of Falling Edge Interrupt for P0.21. 0
22 P0.22FEI Status of Falling Edge Interrupt for P0.22. 0
23 P0.23FEI[1] Status of Falling Edge Interrupt for P0.23. 0
24 P0.24FEI[1] Status of Falling Edge Interrupt for P0.24. 0
25 P0.25FEI Status of Falling Edge Interrupt for P0.25. 0
26 P0.26FEI Status of Falling Edge Interrupt for P0.26. 0
27 P0.27FEI[1] Status of Falling Edge Interrupt for P0.27. 0
28 P0.28FEI[1] Status of Falling Edge Interrupt for P0.28. 0
29 P0.29FEI Status of Falling Edge Interrupt for P0.29. 0
30 P0.30FEI Status of Falling Edge Interrupt for P0.30. 0
31 - Reserved. NA
9.5.6.9 GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF -
0x4002 80A8)
Each bit in these read-only registers indicates the falling edge interrupt status for port 2.
Table 121. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8)
bit description
Bit Symbol Value Description Reset
value
0 P2.0FEI Status of Falling Edge Interrupt for P2.0 0
0 A falling edge has not been detected on P2.0.
1 Interrupt has been generated due to a falling edge on P2.0.
1 P2.1FEI Status of Falling Edge Interrupt for P2.1. 0
2 P2.2FEI Status of Falling Edge Interrupt for P2.2. 0
3 P2.3FEI Status of Falling Edge Interrupt for P2.3. 0
4 P2.4FEI Status of Falling Edge Interrupt for P2.4. 0
5 P2.5FEI Status of Falling Edge Interrupt for P2.5. 0
6 P2.6FEI Status of Falling Edge Interrupt for P2.6. 0
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Table 121. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8)
bit description
Bit Symbol Value Description Reset
value
7 P2.7FEI Status of Falling Edge Interrupt for P2.7. 0
8 P2.8FEI Status of Falling Edge Interrupt for P2.8. 0
9 P2.9FEI Status of Falling Edge Interrupt for P2.9. 0
10 P2.10FEI Status of Falling Edge Interrupt for P2.10. 0
11 P2.11FEI[1] Status of Falling Edge Interrupt for P2.11. 0
12 P2.12FEI[1] Status of Falling Edge Interrupt for P2.12. 0
13 P2.13FEI[1] Status of Falling Edge Interrupt for P2.13. 0
31:14 - Reserved. NA
9.5.6.10 GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)
Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding
port 0 pin.
Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description
Bit Symbol Value Description Reset
value
0 P0.0CI Clear GPIO port Interrupts for P0.0 0
0 Corresponding bits in IOxIntStatR and IOxIntStatF are
unchanged.
1 Corresponding bits in IOxIntStatR and IOxStatF are cleared.
1 P0.1CI Clear GPIO port Interrupts for P0.1. 0
2 P0.2CI Clear GPIO port Interrupts for P0.2. 0
3 P0.3CI Clear GPIO port Interrupts for P0.3. 0
4 P0.4CI[1] Clear GPIO port Interrupts for P0.4. 0
5 P0.5CI[1] Clear GPIO port Interrupts for P0.5. 0
6 P0.6CI Clear GPIO port Interrupts for P0.6. 0
7 P0.7CI Clear GPIO port Interrupts for P0.7. 0
8 P0.8CI Clear GPIO port Interrupts for P0.8. 0
9 P0.9CI Clear GPIO port Interrupts for P0.9. 0
10 P0.10CI Clear GPIO port Interrupts for P0.10. 0
11 P0.11CI Clear GPIO port Interrupts for P0.11. 0
14:12 - Reserved. NA
15 P0.15CI Clear GPIO port Interrupts for P0.15. 0
16 P0.16CI Clear GPIO port Interrupts for P0.16. 0
17 P0.17CI Clear GPIO port Interrupts for P0.17. 0
18 P0.18CI Clear GPIO port Interrupts for P0.18. 0
19 P0.19CI[1] Clear GPIO port Interrupts for P0.19. 0
20 P0.20CI[1] Clear GPIO port Interrupts for P0.20. 0
21 P0.21CI[1] Clear GPIO port Interrupts for P0.21. 0
22 P0.22CI Clear GPIO port Interrupts for P0.22. 0
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Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description
Bit Symbol Value Description Reset
value
23 P0.23CI[1] Clear GPIO port Interrupts for P0.23. 0
24 P0.24CI[1] Clear GPIO port Interrupts for P0.24. 0
25 P0.25CI Clear GPIO port Interrupts for P0.25. 0
26 P0.26CI Clear GPIO port Interrupts for P0.26. 0
27 P0.27CI[1] Clear GPIO port Interrupts for P0.27. 0
28 P0.28CI[1] Clear GPIO port Interrupts for P0.28. 0
29 P0.29CI Clear GPIO port Interrupts for P0.29. 0
30 P0.30CI Clear GPIO port Interrupts for P0.30. 0
31 - Reserved. NA
9.5.6.11 GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC)
Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding
port 2 pin.
Table 123. GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC) bit description
Bit Symbol Value Description Reset
value
0 P2.0CI Clear GPIO port Interrupts for P2.0 0
0 Corresponding bits in IOxIntStatR and IOxIntStatF are
unchanged.
1 Corresponding bits in IOxIntStatR and IOxStatF are cleared.
1 P2.1CI Clear GPIO port Interrupts for P2.1. 0
2 P2.2CI Clear GPIO port Interrupts for P2.2. 0
3 P2.3CI Clear GPIO port Interrupts for P2.3. 0
4 P2.4CI Clear GPIO port Interrupts for P2.4. 0
5 P2.5CI Clear GPIO port Interrupts for P2.5. 0
6 P2.6CI Clear GPIO port Interrupts for P2.6. 0
7 P2.7CI Clear GPIO port Interrupts for P2.7. 0
8 P2.8CI Clear GPIO port Interrupts for P2.8. 0
9 P2.9CI Clear GPIO port Interrupts for P2.9. 0
10 P2.10CI Clear GPIO port Interrupts for P2.10. 0
11 P2.11CI[1] Clear GPIO port Interrupts for P2.11. 0
12 P2.12CI[1] Clear GPIO port Interrupts for P2.12. 0
13 P2.13CI[1] Clear GPIO port Interrupts for P2.13. 0
31:14 - Reserved. NA
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FIO0MASK = 0xFFFF00FF ;
FIO0PIN = 0x0000A500;
FIO0MASKL = 0x00FF;
FIO0PINL = 0xA500;
FIO0PIN1 = 0xA5;
Writing to the FIOPIN register enables instantaneous output of a desired value on the
parallel GPIO. Data written to the FIOPIN register will affect all pins configured as outputs
on that port: zeroes in the value will produce low level pin outputs and ones in the value
will produce high level pin outputs.
A subset of a port’s pins may be changed by using the FIOMASK register to define which
pins are affected. FIOMASK is set up to contain zeroes in bits corresponding to pins that
will be changed, and ones for all others. Solution 2 from Section 9.6.1 above illustrates
output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as
they were before.
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10.2 Introduction
The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media
Access Controller) designed to provide optimized performance through the use of DMA
hardware acceleration. Features include a generous suite of control registers, half or full
duplex operation, flow control, control frames, hardware acceleration for transmit retry,
receive packet filtering and wake-up on LAN activity. Automatic frame transmission and
reception with Scatter-Gather DMA off-loads many operations from the CPU.
The Ethernet block is an AHB master that drives the AHB bus matrix. Through the matrix,
it has access to all on-chip RAM memories. A recommended use of RAM by the Ethernet
is to use one of the RAM blocks exclusively for Ethernet traffic. That RAM would then be
accessed only by the Ethernet and the CPU, and possibly the GPDMA, giving maximum
bandwidth to the Ethernet function.
The Ethernet block interfaces between an off-chip Ethernet PHY using the RMII (Reduced
Media Independent Interface) protocol and the on-chip MIIM (Media Independent
Interface Management) serial bus, also referred to as MDIO (Management Data
Input/Output).
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10.3 Features
• Ethernet standards support:
– Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
pressure.
– Flexible transmit and receive frame options.
– VLAN frame support.
• Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and prefetching.
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– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision backoff and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
• Physical interface:
– Attachment of external PHY chip through a standard Reduced MII (RMII) interface.
– PHY register access is available via the Media Independent Interface Management
(MIIM) interface.
TRANSMIT
HOST
BU S
FLOW
REGISTERS
register CONTROL
interface (AHB
BUS IN T ERF AC E
TRANSMIT TRANSMIT
ET HE RN ET PHY
DMA RETRY RMII
MIIM
RECEIVE
FILTER
ETHERNET
BLOCK
• The host registers module containing the registers in the software view and handling
AHB accesses to the Ethernet block. The host registers connect to the transmit and
receive data path as well as the MAC.
• The DMA to AHB interface. This provides an AHB master connection that allows the
Ethernet block to access on-chip SRAM for reading of descriptors, writing of status,
and reading and writing data buffers.
• The Ethernet MAC, which interfaces to the off-chip PHY via an RMII interface.
• The transmit data path, including:
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– The transmit DMA manager which reads descriptors and data from memory and
writes status to memory.
– The transmit retry module handling Ethernet retry and abort situations.
– The transmit flow control module which can insert Ethernet pause frames.
Descriptors, which are stored in memory, contain information about fragments of incoming
or outgoing Ethernet frames. A fragment may be an entire frame or a much smaller
amount of data. Each descriptor contains a pointer to a memory buffer that holds data
associated with a fragment, the size of the fragment buffer, and details of how the
fragment will be transmitted or received.
Descriptors are stored in arrays in memory, which are located by pointer registers in the
Ethernet block. Other registers determine the size of the arrays, point to the next
descriptor in each array that will be used by the DMA engine, and point to the next
descriptor in each array that will be used by the Ethernet device driver.
The base address registers for the descriptor array, registers indicating the number of
descriptor array entries, and descriptor array input/output pointers are contained in the
Ethernet block. The descriptor entries and all transmit and receive packet data are stored
in memory which is not a part of the Ethernet block. The descriptor entries tell where
related frame data is stored in memory, certain aspects of how the data is handled, and
the result status of each Ethernet transaction.
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Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved
to memory, causes fragment related status to be saved, and advances the hardware
receive pointer for incoming data. Driver software must handle the disposition of received
data, changing of descriptor data addresses (to avoid unnecessary data movement), and
advancing the software receive pointer. The two pointers create a circular queue in the
descriptor array and allow both the DMA hardware and the driver software to know which
descriptors (if any) are available for their use, including whether the descriptor array is
empty or full.
Similarly, driver software must set up pointers to data that will be transmitted by the
Ethernet MAC, giving instructions for each fragment of data, and advancing the software
transmit pointer for outgoing data. Hardware in the DMA engine reads this information and
sends the data to the Ethernet MAC interface when possible, updating the status and
advancing the hardware transmit pointer.
ethernet packet
PREAMBLE
ETHERNET FRAME
7 bytes
start-of-frame
delimiter
1 byte
DesA DesA DesA DesA DesA DesA SrcA SrcA SrcA SrcA SrcA SrcA
oct6 oct5 oct4 oct3 oct2 oct1 oct6 oct5 oct4 oct3 oct2 oct1
LSB MSB
oct(0) oct(1) oct(2) oct(3) oct(4) oct(5) oct(6) oct(7)
time
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The Ethernet frame consists of the destination address, the source address, an optional
VLAN field, the length/type field, the payload and the frame check sequence.
Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred
starting with the least significant bit.
10.8 Overview
10.8.1 Partitioning
The Ethernet block and associated device driver software offer the functionality of the
Media Access Control (MAC) sublayer of the data link layer in the OSI reference model
(see IEEE std 802.3). The MAC sublayer offers the service of transmitting and receiving
frames to the next higher protocol level, the MAC client layer, typically the Logical Link
Control sublayer. The device driver software implements the interface to the MAC client
layer. It sets up registers in the Ethernet block, maintains descriptor arrays pointing to
frames in memory and receives results back from the Ethernet block through interrupts.
When a frame is transmitted, the software partially sets up the Ethernet frames by
providing pointers to the destination address field, source address field, the length/type
field, the MAC client data field and optionally the CRC in the frame check sequence field.
Preferably concatenation of frame fields should be done by using the scatter/gather
functionality of the Ethernet core to avoid unnecessary copying of data. The hardware
adds the preamble and start frame delimiter fields and can optionally add the CRC, if
requested by software. When a packet is received the hardware strips the preamble and
start frame delimiter and passes the rest of the packet - the Ethernet frame - to the device
driver, including destination address, source address, length/type field, MAC client data
and frame check sequence (FCS).
Apart from the MAC, the Ethernet block contains receive and transmit DMA managers that
control receive and transmit data streams between the MAC and the AHB interface.
Frames are passed via descriptor arrays located in host memory, so that the hardware
can process many frames without software/CPU support. Frames can consist of multiple
fragments that are accessed with scatter/gather DMA. The DMA managers optimize
memory bandwidth using prefetching and buffering.
A receive filter block is used to identify received frames that are not addressed to this
Ethernet station, so that they can be discarded. The Rx filters include a perfect address
filter and a hash filter.
Wake-on-LAN power management support makes it possible to wake the system up from
a power-down state -a state in which some of the clocks are switched off -when wake-up
frames are received over the LAN. Wake-up frames are recognized by the receive filtering
modules or by a Magic Frame detection technology. System wake-up occurs by triggering
an interrupt.
An interrupt logic block raises and masks interrupts and keeps track of the cause of
interrupts. The interrupt block sends an interrupt request signal to the host system.
Interrupts can be enabled, cleared and set by software.
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Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block.
Receive flow control frames are automatically handled by the MAC. Transmit flow control
frames can be initiated by software. In half duplex mode, the flow control module will
generate back pressure by sending out continuous preamble only, interrupted by pauses
to prevent the jabber limit from being exceeded.
The Ethernet block has a standard Reduced Media Independent Interface (RMII) to
connect to an external Ethernet PHY chip. Registers in the PHY chip are accessed via the
AHB interface through the serial management connection of the MIIM bus, typically
operating at 2.5 MHz.
Table 127 shows the signals used for Media Independent Interface Management (MIIM) of
the external PHY.
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After a hard reset or a soft reset via the RegReset bit of the Command register all bits in
all registers are reset to 0 unless stated otherwise in the following register descriptions.
Some registers will have unused bits which will return a 0 on a read via the AHB interface.
Writing to unused register bits of an otherwise writable register will not have side effects.
The register map consists of registers in the Ethernet MAC and registers around the core
for controlling DMA transfers, flow control and filtering.
Reading from reserved addresses or reserved bits leads to unpredictable data. Writing to
reserved addresses or reserved bits has no effect.
Reading of write-only registers will return a read error on the AHB interface. Writing of
read-only registers will return a write error on the AHB interface.
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The third column in the table lists the accessibility of the register: read-only, write-only,
read/write.
All AHB register write transactions except for accesses to the interrupt registers are
posted i.e. the AHB transaction will complete before write data is actually committed to the
register. Accesses to the interrupt registers will only be completed by accepting the write
data when the data has been committed to the register.
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Table 129. MAC Configuration register 1 (MAC1 - address 0x5000 0000) bit description
Bit Symbol Function Reset
value
0 RECEIVE ENABLE Set this to allow receive frames to be received. Internally the MAC synchronizes 0
this control bit to the incoming receive stream.
1 PASS ALL RECEIVE When enabled (set to ’1’), the MAC will pass all frames regardless of type (normal 0
FRAMES vs. Control). When disabled, the MAC does not pass valid Control frames.
2 RX FLOW CONTROL When enabled (set to ’1’), the MAC acts upon received PAUSE Flow Control 0
frames. When disabled, received PAUSE Flow Control frames are ignored.
3 TX FLOW CONTROL When enabled (set to ’1’), PAUSE Flow Control frames are allowed to be 0
transmitted. When disabled, Flow Control frames are blocked.
4 LOOPBACK Setting this bit will cause the MAC Transmit interface to be looped back to the MAC 0
Receive interface. Clearing this bit results in normal operation.
7:5 - Unused 0x0
8 RESET TX Setting this bit will put the Transmit Function logic in reset. 0
9 RESET MCS / TX Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic 0
implements flow control.
10 RESET RX Setting this bit will put the Ethernet receive logic in reset. 0
11 RESET MCS / RX Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic 0x0
implements flow control.
13:12 - Reserved. User software should not write ones to reserved bits. The value read 0x0
from a reserved bit is not defined.
14 SIMULATION RESET Setting this bit will cause a reset to the random number generator within the 0
Transmit Function.
15 SOFT RESET Setting this bit will put all modules within the MAC in reset except the Host 1
Interface.
31:16 - Reserved. User software should not write ones to reserved bits. The value read 0x0
from a reserved bit is not defined.
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Table 130. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description
Bit Symbol Function Reset
value
0 FULL-DUPLEX When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled, 0
the MAC operates in Half-Duplex mode.
1 FRAME LENGTH When enabled (set to ’1’), both transmit and receive frame lengths are compared to 0
CHECKING the Length/Type field. If the Length/Type field represents a length then the check is
performed. Mismatches are reported in the StatusInfo word for each received frame.
2 HUGE FRAME When enabled (set to ’1’), frames of any length are transmitted and received. 0
ENABLE
3 DELAYED CRC This bit determines the number of bytes, if any, of proprietary header information 0
that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored
by the CRC function) are added. When 0, there is no proprietary header.
4 CRC ENABLE Set this bit to append a CRC to every frame whether padding was required or not. 0
Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the
MAC contain a CRC.
5 PAD / CRC ENABLE Set this bit to have the MAC pad all short frames. Clear this bit if frames presented 0
to the MAC have a valid length. This bit is used in conjunction with AUTO PAD
ENABLE and VLAN PAD ENABLE. See Table 132 - Pad Operation for details on the
pad function.
6 VLAN PAD ENABLE Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid 0
CRC. Consult Table 132 - Pad Operation for more information on the various
padding features.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.
7 AUTO DETECT PAD Set this bit to cause the MAC to automatically detect the type of frame, either tagged 0
ENABLE or un-tagged, by comparing the two octets following the source address with
0x8100 (VLAN Protocol ID) and pad accordingly. Table 132 - Pad Operation
provides a description of the pad function based on the configuration of this register.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.
8 PURE PREAMBLE When enabled (set to ’1’), the MAC will verify the content of the preamble to ensure 0
ENFORCEMENT it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded.
When disabled, no preamble checking is performed.
9 LONG PREAMBLE When enabled (set to ’1’), the MAC only allows receive packets which contain 0
ENFORCEMENT preamble fields less than 12 bytes in length. When disabled, the MAC allows any
length preamble as per the Standard.
11:10 - Reserved. User software should not write ones to reserved bits. The value read 0x0
from a reserved bit is not defined.
12 NO BACKOFF When enabled (set to ’1’), the MAC will immediately retransmit following a collision 0
rather than using the Binary Exponential Backoff algorithm as specified in the
Standard.
13 BACK PRESSURE / When enabled (set to ’1’), after the MAC incidentally causes a collision during back 0
NO BACKOFF pressure, it will immediately retransmit without backoff, reducing the chance of
further collisions and ensuring transmit packets get sent.
14 EXCESS DEFER When enabled (set to ’1’) the MAC will defer to carrier indefinitely as per the 0
Standard. When disabled, the MAC will abort when the excessive deferral limit is
reached.
31:15 - Reserved. User software should not write ones to reserved bits. The value read 0x0
from a reserved bit is not defined.
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Table 132. Back-to-back Inter-packet-gap register (IPGT - address 0x5000 0008) bit description
Bit Symbol Function Reset
value
6:0 BACK-TO-BACK This is a programmable field representing the nibble time offset of the minimum 0x0
INTER-PACKET-GAP possible period between the end of any transmitted packet to the beginning of the
next. In Full-Duplex mode, the register value should be the desired period in
nibble times minus 3. In Half-Duplex mode, the register value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is
0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or
9.6 µs (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d),
which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs
(in 10 Mbps mode).
31:7 - Reserved. User software should not write ones to reserved bits. The value read 0x0
from a reserved bit is not defined.
Table 133. Non Back-to-back Inter-packet-gap register (IPGR - address 0x5000 000C) bit description
Bit Symbol Function Reset
value
6:0 NON-BACK-TO-BACK This is a programmable field representing the Non-Back-to-Back 0x0
INTER-PACKET-GAP PART2 Inter-Packet-Gap. The recommended value is 0x12 (18d), which
represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in
10 Mbps mode).
7 - Reserved. User software should not write ones to reserved bits. The value 0x0
read from a reserved bit is not defined.
14:8 NON-BACK-TO-BACK This is a programmable field representing the optional carrierSense 0x0
INTER-PACKET-GAP PART1 window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is
detected during the timing of IPGR1, the MAC defers to carrier. If,
however, carrier becomes active after IPGR1, the MAC continues timing
IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x0 to IPGR2. The recommended
value is 0xC (12d)
31:15 - Reserved. User software should not write ones to reserved bits. The value 0x0
read from a reserved bit is not defined.
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Table 134. Collision Window / Retry register (CLRT - address 0x5000 0010) bit description
Bit Symbol Function Reset
value
3:0 RETRANSMISSION This is a programmable field specifying the number of retransmission attempts 0xF
MAXIMUM following a collision before aborting the packet due to excessive collisions. The
Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5.
7:4 - Reserved. User software should not write ones to reserved bits. The value read from 0x0
a reserved bit is not defined.
13:8 COLLISION This is a programmable field representing the slot time or collision window during 0x37
WINDOW which collisions occur in properly configured networks. The default value of 0x37
(55d) represents a 56 byte window following the preamble and SFD.
31:14 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
Table 135. Maximum Frame register (MAXF - address 0x5000 0014) bit description
Bit Symbol Function Reset
value
15:0 MAXIMUM FRAME This field resets to the value 0x0600, which represents a maximum receive frame of 0x0600
LENGTH 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged
frame adds four octets for a total of 1522 octets. If a shorter maximum length
restriction is desired, program this 16-bit field.
31:16 - Unused 0x0
Table 136. PHY Support register (SUPP - address 0x5000 0018) bit description
Bit Symbol Function Reset
value
7:0 - Unused 0x0
8 SPEED This bit configures the Reduced MII logic for the current operating speed. When set, 0
100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.
31:9 - Unused 0x0
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Table 138. MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description
Bit Symbol Function Reset
value
0 SCAN INCREMENT Set this bit to cause the MII Management hardware to perform read cycles across a 0
range of PHYs. When set, the MII Management hardware will perform read cycles
from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow
continuous reads of the same PHY.
1 SUPPRESS Set this bit to cause the MII Management hardware to perform read/write cycles 0
PREAMBLE without the 32-bit preamble field. Clear this bit to cause normal cycles to be
performed. Some PHYs support suppressed preamble.
5:2 CLOCK SELECT This field is used by the clock divide logic in creating the MII Management Clock 0
(MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs
support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided
by the specified amount. Refer to Table 139 below for the definition of values for this
field.
14:6 - Unused 0x0
15 RESET MII MGMT This bit resets the MII Management hardware. 0
31:16 - Unused 0x0
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[1] The maximum AHB clock rate allowed is limited to the maximum CPU clock rate for the device.
Table 140. MII Mgmt Command register (MCMD - address 0x5000 0024) bit description
Bit Symbol Function Reset
value
0 READ This bit causes the MII Management hardware to perform a single Read cycle. The Read data is 0
returned in Register MRDD (MII Mgmt Read Data).
1 SCAN This bit causes the MII Management hardware to perform Read cycles continuously. This is 0
useful for monitoring Link Fail for example.
31:2 - Unused 0x0
Table 141. MII Mgmt Address register (MADR - address 0x5000 0028) bit description
Bit Symbol Function Reset
value
4:0 REGISTER This field represents the 5-bit Register Address field of Mgmt 0x0
ADDRESS cycles. Up to 32 registers can be accessed.
7:5 - Unused 0x0
12:8 PHY ADDRESS This field represents the 5-bit PHY Address field of Mgmt 0x0
cycles. Up to 31 PHYs can be addressed (0 is reserved).
31:13 - Unused 0x0
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Table 142. MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description
Bit Symbol Function Reset
value
15:0 WRITE When written, an MII Mgmt write cycle is performed using the 16-bit 0x0
DATA data and the pre-configured PHY and Register addresses from the
MII Mgmt Address register (MADR).
31:16 - Unused 0x0
Table 143. MII Mgmt Read Data register (MRDD - address 0x5000 0030) bit description
Bit Symbol Function Reset
value
15:0 READ Following an MII Mgmt Read Cycle, the 16-bit data can be read from 0x0
DATA this location.
31:16 - Unused 0x0
Table 144. MII Mgmt Indicators register (MIND - address 0x5000 0034) bit description
Bit Symbol Function Reset
value
0 BUSY When ’1’ is returned - indicates MII Mgmt is currently performing an 0
MII Mgmt Read or Write cycle.
1 SCANNING When ’1’ is returned - indicates a scan operation (continuous MII 0
Mgmt Read cycles) is in progress.
2 NOT VALID When ’1’ is returned - indicates MII Mgmt Read cycle has not 0
completed and the Read Data is not yet valid.
3 MII Link Fail When ’1’ is returned - indicates that an MII Mgmt link fail has 0
occurred.
31:4 - Unused 0x0
Here are two examples to access PHY via the MII Management Controller.
1. Write 0 to MCMD
2. Write PHY address and register address to MADR
3. Write data to MWTD
4. Wait for busy bit to be cleared in MIND
1. Write 1 to MCMD
2. Write PHY address and register address to MADR
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Table 145. Station Address register (SA0 - address 0x5000 0040) bit description
Bit Symbol Function Reset
value
7:0 STATION ADDRESS, This field holds the second octet of the station address. 0x0
2nd octet
15:8 STATION ADDRESS, This field holds the first octet of the station address. 0x0
1st octet
31:16 - Unused 0x0
The station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to Figure 18.
Table 146. Station Address register (SA1 - address 0x5000 0044) bit description
Bit Symbol Function Reset
value
7:0 STATION ADDRESS, This field holds the fourth octet of the station address. 0x0
4th octet
15:8 STATION ADDRESS, This field holds the third octet of the station address. 0x0
3rd octet
31:16 - Unused 0x0
The station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to Figure 18.
Table 147. Station Address register (SA2 - address 0x5000 0048) bit description
Bit Symbol Function Reset
value
7:0 STATION ADDRESS, This field holds the sixth octet of the station address. 0x0
6th octet
15:8 STATION ADDRESS, This field holds the fifth octet of the station address. 0x0
5th octet
31:16 - Unused 0x0
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The station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to Figure 18.
Table 148. Command register (Command - address 0x5000 0100) bit description
Bit Symbol Function Reset
value
0 RxEnable Enable receive. 0
1 TxEnable Enable transmit. 0
2 - Unused 0x0
3 RegReset When a ’1’ is written, all datapaths and the host registers are 0
reset. The MAC needs to be reset separately.
4 TxReset When a ’1’ is written, the transmit datapath is reset. 0
5 RxReset When a ’1’ is written, the receive datapath is reset. 0
6 PassRuntFrame When set to ’1’, passes runt frames smaller than 64 bytes to 0
memory unless they have a CRC error. If ’0’ runt frames are
filtered out.
7 PassRxFilter When set to ’1’, disables receive filtering i.e. all frames 0
received are written to memory.
8 TxFlowControl Enable IEEE 802.3 / clause 31 flow control sending pause 0
frames in full duplex and continuous preamble in half duplex.
9 RMII When set to “1”, RMII mode is selected. This bit must be set to 0
one during Ethernet initialization. See Section 10.17.2.
10 FullDuplex When set to “1”, indicates full duplex operation. 0
31:11 - Unused 0x0
All bits can be written and read. The Tx/RxReset bits are write-only, reading will return a 0.
Table 149. Status register (Status - address 0x5000 0104) bit description
Bit Symbol Function Reset
value
0 RxStatus If 1, the receive channel is active. If 0, the receive channel is inactive. 0
1 TxStatus If 1, the transmit channel is active. If 0, the transmit channel is inactive. 0
31:2 - Unused 0x0
The values represent the status of the two channels/data paths. When the status is 1, the
channel is active, meaning:
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• It is enabled and the Rx/TxEnable bit is set in the Command register or it just got
disabled while still transmitting or receiving a frame.
• Also, for the transmit channel, the transmit queue is not empty
i.e. ProduceIndex != ConsumeIndex.
• Also, for the receive channel, the receive queue is not full
i.e. ProduceIndex != ConsumeIndex - 1.
The status transitions from active to inactive if the channel is disabled by a software reset
of the Rx/TxEnable bit in the Command register and the channel has committed the status
and data of the current frame to memory. The status also transitions to inactive if the
transmit queue is empty or if the receive queue is full and status and data have been
committed to memory.
Table 150. Receive Descriptor Base Address register (RxDescriptor - address 0x5000 0108)
bit description
Bit Symbol Function Reset
value
1:0 - Fixed to ’00’ -
31:2 RxDescriptor MSBs of receive descriptor base address. 0x0
The receive descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of
descriptors.
Table 151. receive Status Base Address register (RxStatus - address 0x5000 010C) bit
description
Bit Symbol Function Reset
value
2:0 - Fixed to ’000’ -
31:3 RxStatus MSBs of receive status base address. 0x0
The receive status base address is a byte address aligned to a double word boundary i.e.
LSB 2:0 are fixed to “000”.
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Table 152. Receive Number of Descriptors register (RxDescriptor - address 0x5000 0110) bit
description
Bit Symbol Function Reset
value
15:0 RxDescriptorNumber Number of descriptors in the descriptor array for which 0x0
RxDescriptor is the base address. The number of
descriptors is minus one encoded.
31:16 - Unused 0x0
The receive number of descriptors register defines the number of descriptors in the
descriptor array for which RxDescriptor is the base address. The number of descriptors
should match the number of statuses. The register uses minus one encoding i.e. if the
array has 8 elements, the value in the register should be 7.
Table 153. Receive Produce Index register (RxProduceIndex - address 0x5000 0114) bit
description
Bit Symbol Function Reset
value
15:0 RxProduceIndex Index of the descriptor that is going to be filled next by the 0x0
receive datapath.
31:16 - Unused 0x0
The receive produce index register defines the descriptor that is going to be filled next by
the hardware receive process. After a frame has been received, hardware increments the
index. The value is wrapped to 0 once the value of RxDescriptorNumber has been
reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any
further frames being received will cause a buffer overrun error.
Table 154. Receive Consume Index register (RxConsumeIndex - address 0x5000 0118) bit
description
Bit Symbol Function Reset
value
15:0 RxConsumeIndex Index of the descriptor that is going to be processed next by
the receive
31:16 - Unused 0x0
The receive consume register defines the descriptor that is going to be processed next by
the software receive driver. The receive array is empty as long as RxProduceIndex equals
RxConsumeIndex. As soon as the array is not empty, software can process the frame
pointed to by RxConsumeIndex. After a frame has been processed by software, software
should increment the RxConsumeIndex. The value must be wrapped to 0 once the value
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Table 155. Transmit Descriptor Base Address register (TxDescriptor - address 0x5000 011C)
bit description
Bit Symbol Function Reset
value
1:0 - Fixed to ’00’ -
31:2 TxDescriptor MSBs of transmit descriptor base address. 0x0
The transmit descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of
descriptors.
Table 156. Transmit Status Base Address register (TxStatus - address 0x5000 0120) bit
description
Bit Symbol Function Reset
value
1:0 - Fixed to ’00’ -
31:2 TxStatus MSBs of transmit status base address. 0x0
The transmit status base address is a byte address aligned to a word boundary i.e. LSB
1:0 are fixed to “00”. The register contains the lowest address in the array of statuses.
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The transmit number of descriptors register defines the number of descriptors in the
descriptor array for which TxDescriptor is the base address. The number of descriptors
should match the number of statuses. The register uses minus one encoding i.e. if the
array has 8 elements, the value in the register should be 7.
Table 158. Transmit Produce Index register (TxProduceIndex - address 0x5000 0128) bit
description
Bit Symbol Function Reset
value
15:0 TxProduceIndex Index of the descriptor that is going to be filled next by the 0x0
transmit software driver.
31:16 - Unused 0x0
The transmit produce index register defines the descriptor that is going to be filled next by
the software transmit driver. The transmit descriptor array is empty as long as
TxProduceIndex equals TxConsumeIndex. If the transmit hardware is enabled, it will start
transmitting frames as soon as the descriptor array is not empty. After a frame has been
processed by software, it should increment the TxProduceIndex. The value must be
wrapped to 0 once the value of TxDescriptorNumber has been reached. If the
TxProduceIndex equals TxConsumeIndex - 1 the descriptor array is full and software
should stop producing new descriptors until hardware has transmitted some frames and
updated the TxConsumeIndex.
Table 159. Transmit Consume Index register (TxConsumeIndex - address 0x5000 012C) bit
description
Bit Symbol Function Reset
value
15:0 TxConsumeIndex Index of the descriptor that is going to be transmitted next by 0x0
the transmit datapath.
31:16 - Unused 0x0
The transmit consume index register defines the descriptor that is going to be transmitted
next by the hardware transmit process. After a frame has been transmitted hardware
increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has
been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is
empty and the transmit channel will stop transmitting until software produces new
descriptors.
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distributed over two registers TSV0 and TSV1. These registers are provided for debug
purposes, because the communication between driver software and the Ethernet block
takes place primarily through the frame descriptors. The status register contents are valid
as long as the internal status of the MAC is valid and should typically only be read when
the transmit and receive processes are halted.
Table 160. Transmit Status Vector 0 register (TSV0 - address 0x5000 0158) bit description
Bit Symbol Function Reset
value
0 CRC error The attached CRC in the packet did not match the 0
internally generated CRC.
1 Length check error Indicates the frame length field does not match the actual 0
number of data items and is not a type field.
2 Length out of range[1] Indicates that frame type/length field was larger than 0
1500 bytes.
3 Done Transmission of packet was completed. 0
4 Multicast Packet’s destination was a multicast address. 0
5 Broadcast Packet’s destination was a broadcast address. 0
6 Packet Defer Packet was deferred for at least one attempt, but less than 0
an excessive defer.
7 Excessive Defer Packet was deferred in excess of 6071 nibble times in 0
100 Mbps or 24287 bit times in 10 Mbps mode.
8 Excessive Collision Packet was aborted due to exceeding of maximum allowed 0
number of collisions.
9 Late Collision Collision occurred beyond collision window, 512 bit times. 0
10 Giant Byte count in frame was greater than can be represented 0
in the transmit byte count field in TSV1.
11 Underrun Host side caused buffer underrun. 0
27:12 Total bytes The total number of bytes transferred including collided 0x0
attempts.
28 Control frame The frame was a control frame. 0
29 Pause The frame was a control frame with a valid PAUSE 0
opcode.
30 Backpressure Carrier-sense method backpressure was previously 0
applied.
31 VLAN Frame’s length/type field contained 0x8100 which is the 0
VLAN protocol identifier.
[1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length
out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the
status of the received frame.
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purposes, because the communication between driver software and the Ethernet block
takes place primarily through the frame descriptors. The status register contents are valid
as long as the internal status of the MAC is valid and should typically only be read when
the transmit and receive processes are halted.Table 161 lists the bit definitions of the
TSV1 register.
Table 161. Transmit Status Vector 1 register (TSV1 - address 0x5000 015C) bit description
Bit Symbol Function Reset
value
15:0 Transmit byte count The total number of bytes in the frame, not counting the 0x0
collided bytes.
19:16 Transmit collision Number of collisions the current packet incurred during 0x0
count transmission attempts. The maximum number of collisions
(16) cannot be represented.
31:20 - Unused 0x0
Table 162. Receive Status Vector register (RSV - address 0x5000 0160) bit description
Bit Symbol Function Reset
value
15:0 Received byte count Indicates length of received frame. 0x0
16 Packet previously Indicates that a packet was dropped. 0
ignored
17 RXDV event Indicates that the last receive event seen was not long 0
previously seen enough to be a valid packet.
18 Carrier event Indicates that at some time since the last receive statistics, 0
previously seen a carrier event was detected.
19 Receive code Indicates that received PHY data does not represent a 0
violation valid receive code.
20 CRC error The attached CRC in the packet did not match the 0
internally generated CRC.
21 Length check error Indicates the frame length field does not match the actual 0
number of data items and is not a type field.
22 Length out of range[1] Indicates that frame type/length field was larger than 0
1518 bytes.
23 Receive OK The packet had valid CRC and no symbol errors. 0
24 Multicast The packet destination was a multicast address. 0
25 Broadcast The packet destination was a broadcast address. 0
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Table 162. Receive Status Vector register (RSV - address 0x5000 0160) bit description
Bit Symbol Function Reset
value
26 Dribble Nibble Indicates that after the end of packet another 1-7 bits were 0
received. A single nibble, called dribble nibble, is formed
but not sent out.
27 Control frame The frame was a control frame. 0
28 PAUSE The frame was a control frame with a valid PAUSE 0
opcode.
29 Unsupported Opcode The current frame was recognized as a Control Frame but 0
contains an unknown opcode.
30 VLAN Frame’s length/type field contained 0x8100 which is the 0
VLAN protocol identifier.
31 - Unused 0x0
[1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length
out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the
status of the received frame.
Table 163. Flow Control Counter register (FlowControlCounter - address 0x5000 0170) bit
description
Bit Symbol Function Reset
value
15:0 MirrorCounter In full duplex mode the MirrorCounter specifies the number 0x0
of cycles before re-issuing the Pause control frame.
31:16 PauseTimer In full-duplex mode the PauseTimer specifies the value 0x0
that is inserted into the pause timer field of a pause flow
control frame. In half duplex mode the PauseTimer
specifies the number of backpressure cycles.
Table 164. Flow Control Status register (FlowControlStatus - address 0x5000 0174) bit
description
Bit Symbol Function Reset
value
15:0 MirrorCounterCurrent In full duplex mode this register represents the current 0x0
value of the datapath’s mirror counter which counts up to
the value specified by the MirrorCounter field in the
FlowControlCounter register. In half duplex mode the
register counts until it reaches the value of the PauseTimer
bits in the FlowControlCounter register.
31:16 - Unused 0x0
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Table 165. Receive Filter Control register (RxFilterCtrl - address 0x5000 0200) bit description
Bit Symbol Function Reset
value
0 AcceptUnicastEn When set to ’1’, all unicast frames are accepted. 0
1 AcceptBroadcastEn When set to ’1’, all broadcast frames are accepted. 0
2 AcceptMulticastEn When set to ’1’, all multicast frames are accepted. 0
3 AcceptUnicastHashEn When set to ’1’, unicast frames that pass the imperfect 0
hash filter are accepted.
4 AcceptMulticastHashEn When set to ’1’, multicast frames that pass the 0
imperfect hash filter are accepted.
5 AcceptPerfectEn When set to ’1’, the frames with a destination address 0
identical to the
station address are accepted.
11:6 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
12 MagicPacketEnWoL When set to ’1’, the result of the magic packet filter will 0
generate a WoL interrupt when there is a match.
13 RxFilterEnWoL When set to ’1’, the result of the perfect address 0
matching filter and the imperfect hash filter will
generate a WoL interrupt when there is a match.
31:14 - Unused 0x0
Table 166 lists the definition of the individual bits in the register.
Table 166. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit
description
Bit Symbol Function Reset
value
0 AcceptUnicastWoL When the value is ’1’, a unicast frames caused WoL. 0
1 AcceptBroadcastWoL When the value is ’1’, a broadcast frame caused WoL. 0
2 AcceptMulticastWoL When the value is ’1’, a multicast frame caused WoL. 0
3 AcceptUnicastHashWoL When the value is ’1’, a unicast frame that passes the 0
imperfect hash filter caused WoL.
4 AcceptMulticastHashWoL When the value is ’1’, a multicast frame that passes the 0
imperfect hash filter caused WoL.
5 AcceptPerfectWoL When the value is ’1’, the perfect address matching filter 0
caused WoL.
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Table 166. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit
description
Bit Symbol Function Reset
value
6 - Unused 0x0
7 RxFilterWoL When the value is ’1’, the receive filter caused WoL. 0
8 MagicPacketWoL When the value is ’1’, the magic packet filter caused 0
WoL.
31:9 - Unused 0x0
The bits in this register record the cause for a WoL. Bits in RxFilterWoLStatus can be
cleared by writing the RxFilterWoLClear register.
Table 167 lists the definition of the individual bits in the register.
Table 167. Receive Filter WoL Clear register (RxFilterWoLClear - address 0x5000 0208) bit
description
Bit Symbol Function Reset
value
0 AcceptUnicastWoLClr When a ’1’ is written to one of these bits (0 to 5), the 0
1 AcceptBroadcastWoLClr corresponding status bit in the RxFilterWoLStatus 0
register is cleared.
2 AcceptMulticastWoLClr 0
3 AcceptUnicastHashWoLClr 0
4 AcceptMulticastHashWoLClr 0
5 AcceptPerfectWoLClr 0
6 - Unused 0x0
7 RxFilterWoLClr When a ’1’ is written to one of these bits (7 and/or 8), 0
8 MagicPacketWoLClr the corresponding status bit in the RxFilterWoLStatus 0
register is cleared.
31:9 - Unused 0x0
The bits in this register are write-only; writing resets the corresponding bits in the
RxFilterWoLStatus register.
Table 168. Hash Filter Table LSBs register (HashFilterL - address 0x5000 0210) bit
description
Bit Symbol Function Reset
value
31:0 HashFilterL Bits 31:0 of the imperfect filter hash table for receive 0x0
filtering.
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Table 169. Hash Filter MSBs register (HashFilterH - address 0x5000 0214) bit description
Bit Symbol Function Reset
value
31:0 HashFilterH Bits 63:32 of the imperfect filter hash table for receive 0x0
filtering.
Table 170. Interrupt Status register (IntStatus - address 0x5000 0FE0) bit description
Bit Symbol Function Reset
value
0 RxOverrunInt Interrupt set on a fatal overrun error in the receive queue. The 0
fatal interrupt should be resolved by a Rx soft-reset. The bit is not
set when there is a nonfatal overrun error.
1 RxErrorInt Interrupt trigger on receive errors: AlignmentError, RangeError, 0
LengthError, SymbolError, CRCError or NoDescriptor or Overrun.
2 RxFinishedInt Interrupt triggered when all receive descriptors have been 0
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
3 RxDoneInt Interrupt triggered when a receive descriptor has been processed 0
while the Interrupt bit in the Control field of the descriptor was set.
4 TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The 0
fatal interrupt should be resolved by a Tx soft-reset. The bit is not
set when there is a nonfatal underrun error.
5 TxErrorInt Interrupt trigger on transmit errors: LateCollision, 0
ExcessiveCollision and ExcessiveDefer, NoDescriptor or
Underrun.
6 TxFinishedInt Interrupt triggered when all transmit descriptors have been 0
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
7 TxDoneInt Interrupt triggered when a descriptor has been transmitted while 0
the Interrupt bit in the Control field of the descriptor was set.
11:8 - Unused 0x0
12 SoftInt Interrupt triggered by software writing a 1 to the SoftintSet bit in 0
the IntSet register.
13 WakeupInt Interrupt triggered by a Wake-up event detected by the receive 0
filter.
31:14 - Unused 0x0
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The interrupt status register is read-only. Setting can be done via the IntSet register. Reset
can be accomplished via the IntClear register.
Table 171. Interrupt Enable register (intEnable - address 0x5000 0FE4) bit description
Bit Symbol Function Reset
value
0 RxOverrunIntEn Enable for interrupt trigger on receive buffer overrun or 0
descriptor underrun situations.
1 RxErrorIntEn Enable for interrupt trigger on receive errors. 0
2 RxFinishedIntEn Enable for interrupt triggered when all receive descriptors have 0
been processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
3 RxDoneIntEn Enable for interrupt triggered when a receive descriptor has 0
been processed while the Interrupt bit in the Control field of the
descriptor was set.
4 TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor 0
underrun situations.
5 TxErrorIntEn Enable for interrupt trigger on transmit errors. 0
6 TxFinishedIntEn Enable for interrupt triggered when all transmit descriptors 0
have been processed i.e. on the transition to the situation
where ProduceIndex == ConsumeIndex.
7 TxDoneIntEn Enable for interrupt triggered when a descriptor has been 0
transmitted while the Interrupt bit in the Control field of the
descriptor was set.
11:8 - Unused 0x0
12 SoftIntEn Enable for interrupt triggered by the SoftInt bit in the IntStatus 0
register, caused by software writing a 1 to the SoftIntSet bit in
the IntSet register.
13 WakeupIntEn Enable for interrupt triggered by a Wake-up event detected by 0
the receive filter.
31:14 - Unused 0x0
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Table 172. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description
Bit Symbol Function Reset
value
0 RxOverrunIntClr Writing a ’1’ to one of these bits clears (0 to 7) the 0
1 RxErrorIntClr corresponding status bit in interrupt status register 0
IntStatus.
2 RxFinishedIntClr 0
3 RxDoneIntClr 0
4 TxUnderrunIntClr 0
5 TxErrorIntClr 0
6 TxFinishedIntClr 0
7 TxDoneIntClr 0
11:8 - Unused 0x0
12 SoftIntClr Writing a ’1’ to one of these bits (12 and/or 13) clears the 0
13 WakeupIntClr corresponding status bit in interrupt status register 0
IntStatus.
31:14 - Unused 0x0
The interrupt clear register is write-only. Writing a 1 to a bit of the IntClear register clears
the corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
Table 173. Interrupt Set register (IntSet - address 0x5000 0FEC) bit description
Bit Symbol Function Reset
value
0 RxOverrunIntSet Writing a ’1’ to one of these bits (0 to 7) sets the 0
1 RxErrorIntSet corresponding status bit in interrupt status register 0
IntStatus.
2 RxFinishedIntSet 0
3 RxDoneIntSet 0
4 TxUnderrunIntSet 0
5 TxErrorIntSet 0
6 TxFinishedIntSet 0
7 TxDoneIntSet 0
11:8 - Unused 0x0
12 SoftIntSet Writing a ’1’ to one of these bits (12 and/or 13) sets the 0
13 WakeupIntSet corresponding status bit in interrupt status register 0
IntStatus.
31:14 - Unused 0x0
The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the
corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
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Table 174. Power-Down register (PowerDown - address 0x5000 0FF4) bit description
Bit Symbol Function Reset
value
30:0 - Unused 0x0
31 PowerDownMACAHB If true, all AHB accesses will return a read/write error, 0
except accesses to the Power-Down register.
Setting the bit will return an error on all read and write accesses on the MACAHB interface
except for accesses to the Power-Down register.
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RxDescriptor RxStatus
CONTROL StatusHashCRC
CONTROL StatusHashCRC
CONTROL StatusHashCRC
CONTROL StatusHashCRC
CONTROL StatusHashCRC
CONTROL StatusHashCRC
Receive descriptors are stored in an array in memory. The base address of the array is
stored in the RxDescriptor register, and should be aligned on a 4 byte address boundary.
The number of descriptors in the array is stored in the RxDescriptorNumber register using
a minus one encoding style e.g. if the array has 8 elements the register value should be 7.
Parallel to the descriptors there is an array of statuses. For each element of the descriptor
array there is an associated status field in the status array. The base address of the status
array is stored in the RxStatus register, and must be aligned on an 8 byte address
boundary. During operation (when the receive data path is enabled) the RxDescriptor,
RxStatus and RxDescriptorNumber registers should not be modified.
received. The RxConsumeIndex is programmed by software and is the index of the next
descriptor that the software receive driver is going to process. When RxProduceIndex ==
RxConsumeIndex, the receive buffer is empty. When RxProduceIndex ==
RxConsumeIndex -1 (taking wraparound into account), the receive buffer is full and newly
received data would generate an overflow unless the software driver frees up one or more
descriptors.
Each receive descriptor takes two word locations (8 bytes) in memory. Likewise each
status field takes two words (8 bytes) in memory. Each receive descriptor consists of a
pointer to the data buffer for storing receive data (Packet) and a control word (Control).
The Packet field has a zero address offset, the control field has a 4 byte address offset
with respect to the descriptor address as defined in Table 175.
The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the
base address of the data buffer. The definition of the control word bits is listed in
Table 176.
Table 177 lists the fields in the receive status elements from the status array.
Each receive status consists of two words. The StatusHashCRC word contains a
concatenation of the two 9-bit hash CRCs calculated from the destination and source
addresses contained in the received frame. After detecting the destination and source
addresses, StatusHashCRC is calculated once, then held for every fragment of the same
frame.
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The StatusInfo word contains flags returned by the MAC and flags generated by the
receive data path reflecting the status of the reception. Table 179 lists the bit definitions in
the StatusInfo word.
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[1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range"
error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the
received frame.
TxDescriptor TxStatus
Transmit descriptors are stored in an array in memory. The lowest address of the transmit
descriptor array is stored in the TxDescriptor register, and must be aligned on a 4 byte
address boundary. The number of descriptors in the array is stored in the
TxDescriptorNumber register using a minus one encoding style i.e. if the array has 8
elements the register value should be 7. Parallel to the descriptors there is an array of
statuses. For each element of the descriptor array there is an associated status field in the
status array. The base address of the status array is stored in the TxStatus register, and
must be aligned on a 4 byte address boundary. During operation (when the transmit data
path is enabled) the TxDescriptor, TxStatus, and TxDescriptorNumber registers should
not be modified.
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Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that
will be used next by hardware and software. Both register act as counters starting at 0 and
wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex
contains the index of the next descriptor that is going to be filled by the software driver.
The TxConsumeIndex contains the index of the next descriptor going to be transmitted by
the hardware. When TxProduceIndex == TxConsumeIndex, the transmit buffer is empty.
When TxProduceIndex == TxConsumeIndex -1 (taking wraparound into account), the
transmit buffer is full and the software driver cannot add new descriptors until the
hardware has transmitted one or more frames to free up descriptors.
Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise each
status field takes one word (4 bytes) in memory. Each transmit descriptor consists of a
pointer to the data buffer containing transmit data (Packet) and a control word (Control).
The Packet field has a zero address offset, whereas the control field has a 4 byte address
offset, see Table 180.
The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the
base address of the data buffer. The definition of the control word bits is listed in
Table 181.
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The transmit status consists of one word which is the StatusInfo word. It contains flags
returned by the MAC and flags generated by the transmit data path reflecting the status of
the transmission. Table 183 lists the bit definitions in the StatusInfo word.
10.16.1 Overview
The Ethernet block can transmit and receive Ethernet packets from an off-chip Ethernet
PHY connected through the RMII interface.
Typically during system start-up, the Ethernet block will be initialized. Software
initialization of the Ethernet block should include initialization of the descriptor and status
arrays as well as the receiver fragment buffers.
Remark: when initializing the Ethernet block, it is important to first configure the PHY and
insure that reference clocks (ENET_REF_CLK signal in RMII mode, or both
ENET_RX_CLK and ENET_TX_CLK signals in MII mode) are present at the external pins
and connected to the EMAC module (selecting the appropriate pins using the PINSEL
registers) prior to continuing with Ethernet configuration. Otherwise the CPU can become
locked and no further functionality will be possible. This will cause JTAG lose
communication with the target, if debug mode is being used.
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To transmit a packet the software driver has to set up the appropriate Control registers
and a descriptor to point to the packet data buffer before transferring the packet to
hardware by incrementing the TxProduceIndex register. After transmission, hardware will
increment TxConsumeIndex and optionally generate an interrupt.
The hardware will receive packets from the PHY and apply filtering as configured by the
software driver. While receiving a packet the hardware will read a descriptor from memory
to find the location of the associated receiver data buffer. Receive data is written in the
data buffer and receive status is returned in the receive descriptor status word. Optionally
an interrupt can be generated to notify software that a packet has been received. Note
that the DMA manager will prefetch and buffer up to three descriptors.
The AHB interface has a 32-bit data path, which supports only word accesses and has an
address aperture of 4 kB. Table 128 lists the registers of the Ethernet block.
All AHB write accesses to registers are posted except for accesses to the IntSet, IntClear
and IntEnable registers. AHB write operations are executed in order.
If the PowerDown bit of the PowerDown register is set, all AHB read and write accesses
will return a read or write error except for accesses to the PowerDown register.
Bus Errors
• The AHB interface will return a read error when there is an AHB read access to a
write-only register; likewise a write error is returned when there is an AHB write
access to the read-only register. An AHB read or write error will be returned on AHB
read or write accesses to reserved registers. These errors are propagated back to the
CPU. Registers defined as read-only and write-only are identified in Table 128.
• If the PowerDown bit is set all accesses to AHB registers will result in an error
response except for accesses to the PowerDown register.
10.17 Interrupts
The Ethernet block has a single interrupt request output to the CPU (via the NVIC).
The interrupt service routine must read the IntStatus register to determine the origin of the
interrupt. All interrupt statuses can be set by software writing to the IntSet register;
statuses can be cleared by software writing to the IntClear register.
The transmit and receive data paths can only set interrupt statuses, they cannot clear
statuses. The SoftInt interrupt cannot be set by hardware and can be used by software for
test purposes.
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The Ethernet block includes two DMA managers. The DMA managers make it possible to
transfer frames directly to and from memory with little support from the processor and
without the need to trigger an interrupt for each frame.
The DMA managers work with arrays of frame descriptors and statuses that are stored in
memory. The descriptors and statuses act as an interface between the Ethernet hardware
and the device driver software. There is one descriptor array for receive frames and one
descriptor array for transmit frames. Using buffering for frame descriptors, the memory
traffic and memory bandwidth utilization of descriptors can be kept small.
Each frame descriptor contains two 32-bit fields: the first field is a pointer to a data buffer
containing a frame or a fragment, whereas the second field is a control word related to
that frame or fragment.
The software driver must write the base addresses of the descriptor and status arrays in
the TxDescriptor/RxDescriptor and TxStatus/RxStatus registers. The number of
descriptors/statuses in each array must be written in the
TxDescriptorNumber/RxDescriptorNumber registers. The number of descriptors in an
array corresponds to the number of statuses in the associated status array.
Transmit descriptor arrays, receive descriptor arrays and transmit status arrays must be
aligned on a 4 byte (32bit)address boundary, while the receive status array must be
aligned on a 8 byte (64bit) address boundary.
Ownership of descriptors
Both device driver software and Ethernet hardware can read and write the descriptor
arrays at the same time in order to produce and consume descriptors. A descriptor is
"owned" either by the device driver or by the Ethernet hardware. Only the owner of a
descriptor reads or writes its value. Typically, the sequence of use and ownership of
descriptors and statuses is as follows: a descriptor is owned and set up by the device
driver; ownership of the descriptor/status is passed by the device driver to the Ethernet
block, which reads the descriptor and writes information to the status field; the Ethernet
block passes ownership of the descriptor back to the device driver, which uses the status
information and then recycles the descriptor to be used for another frame. Software must
pre-allocate the memory used to hold the descriptor arrays.
Software can hand over ownership of descriptors and statuses to the hardware by
incrementing (and wrapping if on the array boundary) the
TxProduceIndex/RxConsumeIndex registers. Hardware hands over descriptors and
status to software by updating the TxConsumeIndex/ RxProduceIndex registers.
After handing over a descriptor to the receive and transmit DMA hardware, device driver
software should not modify the descriptor or reclaim the descriptor by decrementing the
TxProduceIndex/ RxConsumeIndex registers because descriptors may have been
prefetched by the hardware. In this case the device driver software will have to wait until
the frame has been transmitted or the device driver has to soft-reset the transmit and/or
receive data paths which will also reset the descriptor arrays.
When descriptors are read from and statuses are written to the arrays, this is done in
sequential order with wrap-around. Sequential order means that when the Ethernet block
has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes is
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the one at the next higher, adjacent memory address. Wrap around means that when the
Ethernet block has finished reading/writing the last descriptor/status of the array (with the
highest memory address), the next descriptor/status it reads/writes is the first
descriptor/status of the array at the base address of the array.
The descriptor arrays can be empty, partially full or full. A descriptor array is empty when
all descriptors are owned by the producer. A descriptor array is partially full if both
producer and consumer own part of the descriptors and both are busy processing those
descriptors. A descriptor array is full when all descriptors (except one) are owned by the
consumer, so that the producer has no more room to process frames. Ownership of
descriptors is indicated with the use of a consume index and a produce index. The
produce index is the first element of the array owned by the producer. It is also the index
of the array element that is next going to be used by the producer of frames (it may
already be busy using it and subsequent elements). The consume index is the first
element of the array that is owned by the consumer. It is also the number of the array
element next to be consumed by the consumer of frames (it and subsequent elements
may already be in the process of being consumed). If the consume index and the produce
index are equal, the descriptor array is empty and all array elements are owned by the
producer. If the consume index equals the produce index plus one, then the array is full
and all array elements (except the one at the produce index) are owned by the consumer.
With a full descriptor array, still one array element is kept empty, to be able to easily
distinguish the full or empty state by looking at the value of the produce index and
consume index. An array must have at least 2 elements to be able to indicate a full
descriptor array with a produce index of value 0 and a consume index of value 1. The
wrap around of the arrays is taken into account when determining if a descriptor array is
full, so a produce index that indicates the last element in the array and a consume index
that indicates the first element in the array, also means the descriptor array is full. When
the produce index and the consume index are unequal and the consume index is not the
produce index plus one (with wrap around taken into account), then the descriptor array is
partially full and both the consumer and producer own enough descriptors to be able to
operate actively on the descriptor array.
Interrupt bit
The descriptors have an Interrupt bit, which is programmed by software. When the
Ethernet block is processing a descriptor and finds this bit set, it will allow triggering an
interrupt (after committing status to memory) by passing the RxDoneInt or TxDoneInt bits
in the IntStatus register to the interrupt output pin. If the Interrupt bit is not set in the
descriptor, then the RxDoneInt or TxDoneInt are not set and no interrupt is triggered (note
that the corresponding bits in IntEnable must also be set to trigger interrupts). This offers
flexible ways of managing the descriptor arrays. For instance, the device driver could add
10 frames to the Tx descriptor array, and set the Interrupt bit in descriptor number 5 in the
descriptor array. This would invoke the interrupt service routine before the transmit
descriptor array is completely exhausted. The device driver could add another batch of
frames to the descriptor array, without interrupting continuous transmission of frames.
Frame fragments
For maximum flexibility in frame storage, frames can be split up into multiple frame
fragments with fragments located in different places in memory. In this case one
descriptor is used for each frame fragment. So, a descriptor can point to a single frame or
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By stringing together fragments it is possible to create large frames from small memory
areas. Another use of fragments is to be able to locate a frame header and frame payload
in different places and to concatenate them without copy operations in the device driver.
For transmissions, the Last bit in the descriptor Control field indicates if the fragment is the
last in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the status
words indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next
descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor
is a new Ethernet frame.
10.17.2 Initialization
After reset, the Ethernet software driver needs to initialize the Ethernet block. During
initialization the software needs to:
Depending on the PHY, the software needs to initialize registers in the PHY via the MII
Management interface. The software can read and write PHY registers by programming
the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the
MWTD register; read data and status information can be read from the MRDD and MIND
registers.
The Ethernet block supports RMII PHYs. During initialization software must select RMII
mode by programming the Command register.
Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to be
de-asserted. The phy_ref_clk must be running and internally connected during this
operation.
Transmit and receive DMA engines should be initialized by the device driver by allocating
the descriptor and status arrays in memory. Transmit and receive functions have their own
dedicated descriptor and status arrays. The base addresses of these arrays need to be
programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The
number of descriptors in an array matches the number of statuses in an array.
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Please note that the transmit descriptors, receive descriptors and receive statuses are 8
bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit
statuses need to be aligned on 4 byte boundaries; receive status arrays need to be
aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to
be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding
i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor
array has 4 descriptors the value of the number of descriptors register should be 3.
After setting up the descriptor arrays, frame buffers need to be allocated for the receive
descriptors before enabling the receive data path. The Packet field of the receive
descriptors needs to be filled with the base address of the frame buffer of that descriptor.
Amongst others the Control field in the receive descriptor needs to contain the size of the
data buffer using -1 encoding.
The receive data path has a configurable filtering function for discarding/ignoring specific
Ethernet frames. The filtering function should also be configured during initialization.
After an assertion of the hardware reset, the soft reset bit in the MAC will be asserted. The
soft reset condition must be removed before the Ethernet block can be enabled.
Enabling of the receive function is located in two places. The receive DMA manager
needs to be enabled and the receive data path of the MAC needs to be enabled. To
prevent overflow in the receive DMA engine the receive DMA engine should be enabled
by setting the RxEnable bit in the Command register before enabling the receive data path
in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register.
The transmit DMA engine can be enabled at any time by setting the TxEnable bit in the
Command register.
Before enabling the data paths, several options can be programmed in the MAC, such as
automatic flow control, transmit to receive loop-back for verification, full/half duplex
modes, etc.
Base addresses of descriptor arrays and descriptor array sizes cannot be modified
without a (soft) reset of the receive and transmit data paths.
If the descriptor array is full the device driver should wait for the descriptor arrays to
become not full before writing to a descriptor in the descriptor array. If the descriptor array
is not full, the device driver should use the descriptor numbered TxProduceIndex of the
array pointed to by TxDescriptor.
The Packet pointer in the descriptor is set to point to a data frame or frame fragment to be
transmitted. The Size field in the Command field of the descriptor should be set to the
number of bytes in the fragment buffer, -1 encoded. Additional control information can be
indicated in the Control field in the descriptor (bits Interrupt, Last, CRC, Pad).
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After writing the descriptor the descriptor needs to be handed over to the hardware by
incrementing (and possibly wrapping) the TxProduceIndex register.
If the transmit data path is disabled, the device driver should not forget to enable the
transmit data path by setting the TxEnable bit in the Command register.
When there is a multi-fragment transmission for fragments other than the last, the Last bit
in the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To
trigger an interrupt when the frame has been transmitted and transmission status has
been committed to memory, set the Interrupt bit in the descriptor Control field to 1. To have
the hardware add a CRC in the frame sequence control field of this Ethernet frame, set
the CRC bit in the descriptor. This should be done if the CRC has not already been added
by software. To enable automatic padding of small frames to the minimum required frame
size, set the Pad bit in the Control field of the descriptor to 1. In typical applications bits
CRC and Pad are both set to 1.
The device driver can set up interrupts using the IntEnable register to wait for a signal of
completion from the hardware or can periodically inspect (poll) the progress of
transmission. It can also add new frames at the end of the descriptor array, while
hardware consumes descriptors at the start of the array.
The device driver can stop the transmit process by resetting the TxEnable bit in the
Command register to 0. The transmission will not stop immediately; frames already being
transmitted will be transmitted completely and the status will be committed to memory
before deactivating the data path. The status of the transmit data path can be monitored
by the device driver reading the TxStatus bit in the Status register.
As soon as the transmit data path is enabled and the corresponding TxConsumeIndex
and TxProduceIndex are not equal i.e. the hardware still needs to process frames from
the descriptor array, the TxStatus bit in the Status register will return to 1 (active).
When the TxEnable bit is set, the Tx DMA manager reads the descriptors from memory at
the address determined by TxDescriptor and TxConsumeIndex. The number of
descriptors requested is determined by the total number of descriptors owned by the
hardware: TxProduceIndex - TxConsumeIndex. Block transferring descriptors minimizes
memory loading. Read data returned from memory is buffered and consumed as needed.
After reading the descriptor the transmit DMA engine reads the associated frame data
from memory and transmits the frame. After transfer completion, the Tx DMA manager
writes status information back to the StatusInfo and StatusHashCRC words of the status
field. The value of the TxConsumeIndex is only updated after status information has been
committed to memory, which is checked by an internal tag protocol in the memory
interface. The Tx DMA manager continues to transmit frames until the descriptor array is
empty. If the transmit descriptor array is empty the TxStatus bit in the Status register will
return to 0 (inactive). If the descriptor array is empty the Ethernet hardware will set the
TxFinishedInt bit of the IntStatus register. The transmit data path will still be enabled.
The Tx DMA manager inspects the Last bit of the descriptor Control field when loading the
descriptor. If the Last bit is 0, this indicates that the frame consists of multiple fragments.
The Tx DMA manager gathers all the fragments from the host memory, visiting a string of
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frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection.
When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1,
this indicates the last fragment of the frame and thus the end of the frame is found.
Update ConsumeIndex
Each time the Tx DMA manager commits a status word to memory it completes the
transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around
into account) to hand the descriptor back to the device driver software. Software can
re-use the descriptor for new transmissions after hardware has handed it back.
The device driver software can keep track of the progress of the DMA manager by reading
the TxConsumeIndex register to see how far along the transmit process is. When the Tx
descriptor array is emptied completely, the TxConsumeIndex register retains its last value.
After the frame has been transmitted over the RMII bus, the StatusInfo word of the frame
descriptor is updated by the DMA manager.
If the descriptor is for the last fragment of a frame (or for the whole frame if there are no
fragments), then depending on the success or failure of the frame transmission, error
flags (Error, LateCollision, ExcessiveCollision, Underrun, ExcessiveDefer, Defer) are set
in the status. The CollisionCount field is set to the number of collisions the frame incurred,
up to the Retransmission Maximum programmed in the Collision window/retry register of
the MAC.
Statuses for all but the last fragment in the frame will be written as soon as the data in the
frame has been accepted by the Tx DMA manager. Even if the descriptor is for a frame
fragment other than the last fragment, the error flags are returned via the AHB interface. If
the Ethernet block detects a transmission error during transmission of a (multi-fragment)
frame, all remaining fragments of the frame are still read via the AHB interface. After an
error, the remaining transmit data is discarded by the Ethernet block. If there are errors
during transmission of a multi-fragment frame the error statuses will be repeated until the
last fragment of the frame. Statuses for all but the last fragment in the frame will be written
as soon as the data in the frame has been accepted by the Tx DMA manager. These may
include error information if the error is detected early enough. The status for the last
fragment in the frame will only be written after the transmission has completed on the
Ethernet connection. Thus, the status for the last fragment will always reflect any error
that occurred anywhere in the frame.
The status of the last frame transmission can also be inspected by reading the TSV0 and
TSV1 registers. These registers do not report statuses on a fragment basis and do not
store information of previously sent frames. They are provided primarily for debug
purposes, because the communication between driver software and the Ethernet block
takes place through the frame descriptors. The status registers are valid as long as the
internal status of the MAC is valid and should typically only be read when the transmit and
receive processes are halted.
If an error occurs during the transmit process, the Tx DMA manager will report the error
via the transmission StatusInfo word written in the Status array and the IntStatus interrupt
status register.
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The first and second situations are nonfatal and the device driver has to re-send the frame
or have upper software layers re-send the frame. In the third case the hardware is in an
undefined state and needs to be soft reset by setting the TxReset bit in the Command
register.
Device drivers should catch the transmission errors and take action.
The transmit data path can generate four different interrupt types:
• If the Interrupt bit in the descriptor Control field is set, the Tx DMA will set the
TxDoneInt bit in the IntStatus register after sending the fragment and committing the
associated transmission status to memory. Even if a descriptor (fragment) is not the
last in a multi-fragment frame the Interrupt bit in the descriptor can be used to
generate an interrupt.
• If the descriptor array is empty while the Ethernet hardware is enabled the hardware
will set the TxFinishedInt bit of the IntStatus register.
• If the AHB interface does not consume the transmission statuses at a sufficiently high
bandwidth the transmission may underrun in which case the TxUnderrun bit will be set
in the IntStatus register. This is a fatal error which requires a soft reset of the
transmission queue.
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All of the above interrupts can be enabled and disabled by setting or resetting the
corresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU (via the
NVIC).
The interrupts, either of individual frames or of the whole list, are a good means of
communication between the DMA manager and the device driver, triggering the device
driver to inspect the status words of descriptors that have been processed.
Transmit example
Figure 21 illustrates the transmit process in an example transmitting uses a frame header
of 8 bytes and a frame payload of 12 bytes.
0x2008131B
0x20081314
TxDescriptor TxStatus
0x200810EC 0x200811F8
status 0
0x200810EC 0x200811F8
Packet StatusInfo
descriptor 0
0x2008141C
0x20081411
0x20081419
0x20081314
status 1
0x200810F0 0x200811FC
0 0 CONTROL
Control 7 StatusInfo
status array
PACKET 0 PAYLOAD (12 bytes)
0x200810F4
status 2
Packet
descriptor 1
0x20081200
0x20081411 StatusInfo
descriptor array
0x200810F8
status 3
0 0 CONTROL
Control 7
StatusInfo 0x20081204
Packet
0x200810FC
descriptor 2
0x2008132B
0x20081324
0x20081419
0x20081100 1 1 CONTROL
Control 3
TxProduceIndex
0x20081104 0x20081324
TxDescriptorNumber
=3
0 0 CONTROL
Control 7
0x20081108
After reset the values of the DMA registers will be zero. During initialization the device
driver will allocate the descriptor and status array in memory. In this example, an array of
four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address
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boundary. Since the number of descriptors matches the number of statuses the status
array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address
boundary. The device driver writes the base address of the descriptor array
(0x2008 10EC) to the TxDescriptor register and the base address of the status array
(0x2008 11F8) to the TxStatus register. The device driver writes the number of descriptors
and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and
statuses in the arrays need not be initialized, yet.
At this point, the transmit data path may be enabled by setting the TxEnable bit in the
Command register. If the transmit data path is enabled while there are no further frames to
send the TxFinishedInt interrupt flag will be set. To reduce the processor interrupt load
only the desired interrupts can be enabled by setting the relevant bits in the IntEnable
register.
Now suppose application software wants to transmit a frame of 12 bytes using a TCP/IP
protocol (in real applications frames will be larger than 12 bytes). The TCP/IP stack will
add a header to the frame. The frame header need not be immediately in front of the
payload data in memory. The device driver can program the Tx DMA to collect header and
payload data. To do so, the device driver will program the first descriptor to point at the
frame header; the Last flag in the descriptor will be set to false/0 to indicate a
multi-fragment transmission. The device driver will program the next descriptor to point at
the actual payload data. The maximum size of a payload buffer is 2 kB so a single
descriptor suffices to describe the payload buffer. For the sake of the example though the
payload is distributed across two descriptors. After the first descriptor in the array
describing the header, the second descriptor in the array describes the initial 8 bytes of
the payload; the third descriptor in the array describes the remaining 4 bytes of the frame.
In the third descriptor the Last bit in the Control word is set to true/1 to indicate it is the last
descriptor in the frame. In this example the Interrupt bit in the descriptor Control field is set
in the last fragment of the frame in order to trigger an interrupt after the transmission
completed. The Size field in the descriptor’s Control word is set to the number of bytes in
the fragment buffer, -1 encoded.
Note that in real device drivers, the payload will typically only be split across multiple
descriptors if it is more than 2 kB. Also note that transmission payload data is forwarded to
the hardware without the device driver copying it (zero copy device driver).
After setting up the descriptors for the transaction the device driver increments the
TxProduceIndex register by 3 since three descriptors have been programmed. If the
transmit data path was not enabled during initialization the device driver needs to enable
the data path now.
If the transmit data path is enabled the Ethernet block will start transmitting the frame as
soon as it detects the TxProduceIndex is not equal to TxConsumeIndex - both were zero
after reset. The Tx DMA will start reading the descriptors from memory. The memory
system will return the descriptors and the Ethernet block will accept them one by one
while reading the transmit data fragments.
As soon as transmission read data is returned from memory, the Ethernet block will try to
start transmission on the Ethernet connection via the RMII interface.
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After transmitting each fragment of the frame the Tx DMA will write the status of the
fragment’s transmission. Statuses for all but the last fragment in the frame will be written
as soon as the data in the frame has been accepted by the Tx DMA manager. The status
for the last fragment in the frame will only be written after the transmission has completed
on the Ethernet connection.
Since the Interrupt bit in the descriptor of the last fragment is set, after committing the
status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt,
which triggers the device driver to inspect the status information.
In this example the device driver cannot add new descriptors as long as the Ethernet
block has not incremented the TxConsumeIndex because the descriptor array is full (even
though one descriptor is not programmed yet). Only after the hardware commits the status
for the first fragment to memory and the TxConsumeIndex is set to 1 by the DMA manager
can the device driver program the next (the fourth) descriptor. The fourth descriptor can
already be programmed before completely transmitting the first frame.
In this example the hardware adds the CRC to the frame. If the device driver software
adds the CRC, the CRC trailer can be considered another frame fragment which can be
added by doing another gather DMA.
Each data byte is transmitted across the RMII interface as four 2-bit values. The Ethernet
block adds the preamble, frame delimiter leader, and the CRC trailer if hardware CRC is
enabled. Once transmission on the RMII interface commences the transmission cannot
be interrupted without generating an underrun error, which is why descriptors and data
read commands are issued as soon as possible and pipelined.
Using an RMII PHY, the data communication between the Ethernet block and the PHY is
communicated at 50 MHz. In 10 Mbps mode data will only be transmitted once every 10
clock cycles.
After initializing the receive descriptor and status arrays to receive frames from the
Ethernet connection, the receive data path should be enabled in the MAC1 register and
the Control register.
During initialization, each Packet pointer in the descriptors is set to point to a data
fragment buffer. The size of the buffer is stored in the Size bits of the Control field of the
descriptor. Additionally, the Control field in the descriptor has an Interrupt bit. The Interrupt
bit allows generation of an interrupt after a fragment buffer has been filled and its status
has been committed to memory.
After the initialization and enabling of the receive data path, all descriptors are owned by
the receive hardware and should not be modified by the software unless hardware hands
over the descriptor by incrementing the RxProduceIndex, indicating that a frame has been
received. The device driver is allowed to modify the descriptors after a (soft) reset of the
receive data path.
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When the RxEnable bit in the Command register is set, the Rx DMA manager reads the
descriptors from memory at the address determined by RxDescriptor and
RxProduceIndex. The Ethernet block will start reading descriptors even before actual
receive data arrives on the RMII interface (descriptor prefetching). The block size of the
descriptors to be read is determined by the total number of descriptors owned by the
hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors
minimizes memory load. Read data returned from memory is buffered and consumed as
needed.
After reading the descriptor, the receive DMA engine waits for the MAC to return receive
data from the RMII interface that passes the receive filter. Receive frames that do not
match the filtering criteria are not passed to memory. Once a frame passes the receive
filter, the data is written in the fragment buffer associated with the descriptor. The Rx DMA
does not write beyond the size of the buffer. When a frame is received that is larger than a
descriptor’s fragment buffer, the frame will be written to multiple fragment buffers of
consecutive descriptors. In the case of a multi-fragment reception, all but the last fragment
in the frame will return a status where the LastFrag bit is set to 0. Only on the last
fragment of a frame the LastFrag bit in the status will be set to 1. If a fragment buffer is the
last of a frame, the buffer may not be filled completely. The first receive data of the next
frame will be written to the fragment buffer of the next descriptor.
After receiving a fragment, the Rx DMA manager writes status information back to the
StatusInfo and StatusHashCRC words of the status. The Ethernet block writes the size in
bytes of a descriptor’s fragment buffer in the RxSize field of the Status word. The value of
the RxProduceIndex is only updated after the fragment data and the fragment status
information has been committed to memory, which is checked by an internal tag protocol
in the memory interface. The Rx DMA manager continues to receive frames until the
descriptor array is full. If the descriptor array is full, the Ethernet hardware will set the
RxFinishedInt bit of the IntStatus register. The receive data path will still be enabled. If the
receive descriptor array is full any new receive data will generate an overflow error and
interrupt.
Update ProduceIndex
Each time the Rx DMA manager commits a data fragment and the associated status word
to memory, it completes the reception of a descriptor and increments the RxProduceIndex
(taking wrap around into account) in order to hand the descriptor back to the device driver
software. Software can re-use the descriptor for new receptions by handing it back to
hardware when the receive data has been processed.
The device driver software can keep track of the progress of the DMA manager by reading
the RxProduceIndex register to see how far along the receive process is. When the Rx
descriptor array is emptied completely, the RxProduceIndex retains its last value.
After the frame has been received from the RMII bus, the StatusInfo and StatusHashCRC
words of the frame descriptor are updated by the DMA manager.
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If the descriptor is for the last fragment of a frame (or for the whole frame if there are no
fragments), then depending on the success or failure of the frame reception, error flags
(Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or
CRCError) are set in StatusInfo. The RxSize field is set to the number of bytes actually
written to the fragment buffer, -1 encoded. For fragments not being the last in the frame
the RxSize will match the size of the buffer. The hash CRCs of the destination and source
addresses of a packet are calculated once for all the fragments belonging to the same
packet and then stored in every StatusHashCRC word of the statuses associated with the
corresponding fragments. If the reception reports an error, any remaining data in the
receive frame is discarded and the LastFrag bit will be set in the receive status field, so
the error flags in all but the last fragment of a frame will always be 0.
The status of the last received frame can also be inspected by reading the RSV register.
The register does not report statuses on a fragment basis and does not store information
of previously received frames. RSV is provided primarily for debug purposes, because the
communication between driver software and the Ethernet block takes place through the
frame descriptors.
When an error occurs during the receive process, the Rx DMA manager will report the
error via the receive StatusInfo written in the Status array and the IntStatus interrupt status
register.
The receive process can generate several types of errors: AlignmentError, RangeError,
LengthError, SymbolError, CRCError, Overrun, and NoDescriptor. All have corresponding
bits in the receive StatusInfo. In addition to the separate bits in the StatusInfo,
AlignmentError, RangeError, LengthError, SymbolError, and CRCError are ORed together
into the Error bit of the StatusInfo. Errors are also propagated to the IntStatus register; the
RxError bit in the IntStatus register is set if there is an AlignmentError, RangeError,
LengthError, SymbolError, CRCError, or NoDescriptor error; nonfatal overrun errors are
reported in the RxError bit of the IntStatus register; fatal Overrun errors are report in the
RxOverrun bit of the IntStatus register. On fatal overrun errors, the Rx data path needs to
be soft reset by setting the RxReset bit in the Command register.
• In the case of a multi-fragment reception, the next descriptor may be missing. In this
case the NoDescriptor field is set in the status word of the previous descriptor and the
RxError in the IntStatus register is set. This error is nonfatal.
• The data flow on the receiver data interface stalls, corrupting the packet. In this case
the overrun bit in the status word is set and the RxError bit in the IntStatus register is
set. This error is nonfatal.
• The flow of reception statuses stalls and a new status has to be written while a
previous status still waits to be transferred across the memory interface. This error will
corrupt the hardware state and requires the hardware to be soft reset. The error is
detected and sets the Overrun bit in the IntStatus register.
The first overrun situation will result in an incomplete frame with a NoDescriptor status
and the RxError bit in IntStatus set. Software should discard the partially received frame.
In the second overrun situation the frame data will be corrupt which results in the Overrun
status bit being set in the Status word while the IntError interrupt bit is set. In the third case
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receive errors cannot be reported in the receiver Status arrays which corrupts the
hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The
RxReset bit in the Command register should be used to soft reset the hardware.
Device drivers should catch the above receive errors and take action.
The receive data path can generate four different interrupt types:
• If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the
RxDoneInt bit in the IntStatus register after receiving a fragment and committing the
associated data and status to memory. Even if a descriptor (fragment) is not the last in
a multi-fragment frame, the Interrupt bit in the descriptor can be used to generate an
interrupt.
• If the descriptor array is full while the Ethernet hardware is enabled, the hardware will
set the RxFinishedInt bit of the IntStatus register.
• If the AHB interface does not consume receive statuses at a sufficiently high
bandwidth, the receive status process may overrun, in which case the RxOverrun bit
will be set in the IntStatus register.
• If there is a receive error (AlignmentError, RangeError, LengthError, SymbolError, or
CRCError), or a multi-fragment frame where the device driver did provide descriptors
for the initial fragments but did not provide the descriptors for the rest of the
fragments, or if a nonfatal data Overrun occurred, the hardware will set the RxErrorInt
bit of the IntStatus register.
All of the above interrupts can be enabled and disabled by setting or resetting the
corresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU (via the
NVIC).
The interrupts, either of individual frames or of the whole list, are a good means of
communication between the DMA manager and the device driver, triggering the device
driver to inspect the status words of descriptors that have been processed.
The device driver can forward receive data and status to upper software layers. After
processing of data and status, the descriptors, statuses and data buffers may be recycled
and handed back to hardware by incrementing the RxConsumeIndex.
Receive example
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0x20081409
0x20081410
RxDescriptor RxStatus
0x200810EC 0x200811F8
Status 0
0x200810EC StatusInfo 7 0x200811F8
PACKET
Descriptor 0
0x20081411
0x20081418
0x20081409 StatusHashCRC
Status 1
0x200810F0 StatusInfo 7 0x20081200
1 CONTROL 7
status array
StatusHashCRC
FRAGMENT 1 BUFFER(8 bytes)
Status 2
0x200810F4 PACKET StatusInfo 2 0x20081208
Descriptor 1
0x2008141B
0x20081419
0x20081411
StatusHashCRC
descriptor array
0x200810F8 1 CONTROL 7
Status 3
StatusInfo 7 0x20081210
0x2008132C
0x20081419
0x20081325
0x20081100 1 CONTROL 7
0x20081104 0x20081325
RxConsumeIndex
1 CONTROL 7
0x20081108 RxDescriptorNumber= 3
After reset, the values of the DMA registers will be zero. During initialization, the device
driver will allocate the descriptor and status array in memory. In this example, an array of
four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address
boundary. Since the number of descriptors matches the number of statuses, the status
array consists of four elements; the array is 4x2x4 bytes and aligned on a 8 byte address
boundary. The device driver writes the base address of the descriptor array
(0x2008 10EC) in the RxDescriptor register, and the base address of the status array
(0x2008 11F8) in the RxStatus register. The device driver writes the number of descriptors
and statuses minus 1 (3) in the RxDescriptorNumber register. The descriptors and
statuses in the arrays need not be initialized yet.
After allocating the descriptors, a fragment buffer needs to be allocated for each of the
descriptors. Each fragment buffer can be between 1 byte and 2 k bytes. The base
address of the fragment buffer is stored in the Packet field of the descriptors. The number
of bytes in the fragment buffer is stored in the Size field of the descriptor Control word.
The Interrupt field in the Control word of the descriptor can be set to generate an interrupt
as soon as the descriptor has been filled by the receive process. In this example the
fragment buffers are 8 bytes, so the value of the Size field in the Control word of the
descriptor is set to 7. Note that in this example, the fragment buffers are actually a
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continuous memory space; even when a frame is distributed over multiple fragments it will
typically be in a linear, continuous memory space; when the descriptors wrap at the end of
the descriptor array the frame will not be in a continuous memory space.
The device driver should enable the receive process by writing a 1 to the RxEnable bit of
the Command register, after which the MAC needs to be enabled by writing a 1 to the
‘RECEIVE ENABLE’ bit of the MAC1 configuration register. The Ethernet block will now
start receiving Ethernet frames. To reduce the processor interrupt load, some interrupts
can be disabled by setting the relevant bits in the IntEnable register.
After the Rx DMA manager is enabled, it will start issuing descriptor read commands. In
this example the number of descriptors is 4. Initially the RxProduceIndex and
RxConsumeIndex are 0. Since the descriptor array is considered full if RxProduceIndex
== RxConsumeIndex - 1, the Rx DMA manager can only read (RxConsumeIndex -
RxProduceIndex - 1 =) 3 descriptors; note the wrapping.
After enabling the receive function in the MAC, data reception will begin starting at the
next frame i.e. if the receive function is enabled while the RMII interface is halfway
through receiving a frame, the frame will be discarded and reception will start at the next
frame. The Ethernet block will strip the preamble and start of frame delimiter from the
frame. If the frame passes the receive filtering, the Rx DMA manager will start writing the
frame to the first fragment buffer.
Suppose the frame is 19 bytes long. Due to the buffer sizes specified in this example, the
frame will be distributed over three fragment buffers. After writing the initial 8 bytes in the
first fragment buffer, the status for the first fragment buffer will be written and the Rx DMA
will continue filling the second fragment buffer. Since this is a multi-fragment receive, the
status of the first fragment will have a 0 for the LastFrag bit in the StatusInfo word; the
RxSize field will be set to 7 (8, -1 encoded). After writing the 8 bytes in the second
fragment the Rx DMA will continue writing the third fragment. The status of the second
fragment will be like the status of the first fragment: LastFrag = 0, RxSize = 7. After writing
the three bytes in the third fragment buffer, the end of the frame has been reached and the
status of the third fragment is written. The third fragment’s status will have the LastFrag bit
set to 1 and the RxSize equal to 2 (3, -1 encoded).
The next frame received from the RMII interface will be written to the fourth fragment
buffer i.e. five bytes of the third buffer will be unused.
The Rx DMA manager uses an internal tag protocol in the memory interface to check that
the receive data and status have been committed to memory. After the status of the
fragments are committed to memory, an RxDoneInt interrupt will be triggered, which
activates the device driver to inspect the status information. In this example, all
descriptors have the Interrupt bit set in the Control word i.e. all descriptors will generate
an interrupt after committing data and status to memory.
In this example the receive function cannot read new descriptors as long as the device
driver does not increment the RxConsumeIndex, because the descriptor array is full (even
though one descriptor is not programmed yet). Only after the device driver has forwarded
the receive data to application software, and after the device driver has updated the
RxConsumeIndex by incrementing it, will the Ethernet block can continue reading
descriptors and receive data. The device driver will probably increment the
RxConsumeIndex by 3, since the driver will forward the complete frame consisting of
three fragments to the application, and hence free up three descriptors at the same time.
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Each four pairs of bits transferred on the RMII interface are transferred as a byte on the
data write interface after being delayed by 128 or 136 cycles for filtering by the receive
filter and buffer modules. The Ethernet block removes preamble, frame start delimiter, and
CRC from the data and checks the CRC. To limit the buffer NoDescriptor error probability,
three descriptors are buffered. The value of the RxProduceIndex is only updated after
status information has been committed to memory, which is checked by an internal tag
protocol in the memory interface. The software device driver will process the receive data,
after which the device driver will update the RxConsumeIndex.
When a collision occurs outside of the 64 byte collision window, a LateCollision error is
triggered, and the transmission is aborted. After a LateCollision error, the remaining data
in the transmit frame will be discarded. The Ethernet block will set the Error and
LateCollision bits in the frame’s status fields. The TxError bit in the IntStatus register will
be set. If the corresponding bit in the IntEnable register is set, the TxError bit in the
IntStatus register will be propagated to the CPU (via the NVIC). The device driver software
should catch the interrupt and take appropriate actions.
The ‘RETRANSMISSION MAXIMUM’ field of the CLRT register can be used to configure
the maximum number of retries before aborting the transmission.
When a new frame is detected, internal signaling notifies the controller.The controller
starts counting the incoming bytes of the frame, which correspond to the destination
address bytes. When the sixth (and last) byte is counted, the controller notifies the
calculator to store the corresponding 32-bit CRC into a first inner register. Then the
controller repeats counting the next incoming bytes, in order to get synchronized with the
source address. When the last byte of the source address is encountered, the controller
again notifies the CRC calculator, which freezes until the next new frame. When the
calculator receives this second notification, it stores the present 32-bit CRC into a second
inner register. Then the CRCs remain frozen in their own registers until new notifications
arise.
The destination address and source address hash CRCs being written in the
StatusHashCRC word are the nine most significant bits of the 32-bit CRCs as calculated
by the CRC calculator.
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For a full duplex connection the FullDuplex bit of the Command register needs to be set to
1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1; for
half duplex the same bits need to be set to 0.
For full duplex connections, the Ethernet block supports IEEE 802.3/clause 31 flow control
using pause frames. This type of flow control may be used in full-duplex point-to-point
connections. Flow control allows a receiver to stall a transmitter e.g. when the receive
buffers are (almost) full. For this purpose, the receiving side sends a pause frame to the
transmitting side.
Pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles.
In full-duplex mode, the Ethernet block will suspend its transmissions when the it receives
a pause frame. Rx flow control is initiated by the receiving side of the transmission. It is
enabled by setting the ‘RX FLOW CONTROL’ bit in the MAC1 configuration register. If the
RX FLOW CONTROL’ bit is zero, then the Ethernet block ignores received pause control
frames. When a pause frame is received on the Rx side of the Ethernet block,
transmission on the Tx side will be interrupted after the currently transmitting frame has
completed, for an amount of time as indicated in the received pause frame. The transmit
data path will stop transmitting data for the number of 512 bit slot times encoded in the
pause-timer field of the received pause control frame.
By default the received pause control frames are not forwarded to the device driver. To
forward the receive flow control frames to the device driver, set the ‘PASS ALL RECEIVE
FRAMES’ bit in the MAC1 configuration register.
If case device drivers need to stall the receive data e.g. because software buffers are full,
the Ethernet block can transmit pause control frames. Transmit flow control needs to be
initiated by the device driver software; there is no IEEE 802.3/31 flow control initiated by
hardware, such as the DMA managers.
With software flow control, the device driver can detect a situation in which the process of
receiving frames needs to be interrupted by sending out Tx pause frames. Note that due
to Ethernet delays, a few frames can still be received before the flow control takes effect
and the receive stream stops.
Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command
register. When the Ethernet block operates in full duplex mode, this will result in
transmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is
written to TxFlowControl bit of the Command register.
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If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the
Command register will start a pause frame transmission. The value inserted into the
pause-timer value field of transmitted pause frames is programmed via the
PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is
de-asserted, another pause frame having a pause-timer value of 0x0000 is automatically
sent to abort flow control and resume transmission.
When flow control be in force for an extended time, a sequence of pause frames must be
transmitted. This is supported with a mirror counter mechanism. To enable mirror
counting, a nonzero value is written to the MirrorCounter[15:0] bits in the
FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame is
transmitted. After sending the pause frame, an internal mirror counter is initialized to zero.
The internal mirror counter starts incrementing one every 512 bit-slot times. When the
internal mirror counter reaches the MirrorCounter value, another pause frame is
transmitted with pause-timer value equal to the PauseTimer field from the
FlowControlCounter register, the internal mirror counter is reset to zero and restarts
counting. The register MirrorCounter[15:0] is usually set to a smaller value than register
PauseTimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send
a new pause frame before the transmission on the other side can resume. By continuing
to send pause frames before the transmitting side finishes counting the pause timer, the
pause can be extended as long as TxFlowControl is asserted. This continues until
TxFlowControl is de-asserted when a final pause frame having a pause-timer value of
0x0000 is automatically sent to abort flow control and resume transmission. To disable the
mirror counter mechanism, write the value 0 to MirrorCounter field in the
FlowControlCounter register. When using the mirror counter mechanism, account for
time-of-flight delays, frame transmission time, queuing delays, crystal frequency
tolerances, and response time delays by programming the MirrorCounter conservatively,
typically about 80% of the PauseTimer value.
If the software device driver sets the MirrorCounter field of the FlowControlCounter
register to zero, the Ethernet block will only send one pause control frame. After sending
the pause frame an internal pause counter is initialized at zero; the internal pause counter
is incremented by one every 512 bit-slot times. Once the internal pause counter reaches
the value of the PauseTimer register, the TxFlowControl bit in the Command register will
be reset. The software device driver can poll the TxFlowControl bit to detect when the
pause completes.
The value of the internal counter in the flow control module can be read out via the
FlowControlStatus register. If the MirrorCounter is nonzero, the FlowControlStatus register
will return the value of the internal mirror counter; if the MirrorCounter is zero the
FlowControlStatus register will return the value of the internal pause counter value.
The device driver is allowed to dynamically modify the MirrorCounter register value and
switch between zero MirrorCounter and nonzero MirrorCounter modes.
Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1
configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will not
transmit pause control frames, software must not initiate pause frame transmissions, and
the TxFlowControl bit in the Command register should be zero.
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MirrorCounter
(1/515 bit
slots)
RMII
normal receive pause in effect normal receive
receive
In this example, a frame is received while transmitting another frame (full duplex.) The
device driver detects that some buffer might overrun and enables the transmit flow control
by programming the PauseTimer and MirrorCounter fields of the FlowControlCounter
register, after which it enables the transmit flow control by setting the TxFlowControl bit in
the Command register.
As a response to the enabling of the flow control a pause control frame will be sent after
the currently transmitting frame has been transmitted. When the pause frame
transmission completes the internal mirror counter will start counting bit slots; as soon as
the counter reaches the value in the MirrorCounter field another pause frame is
transmitted. While counting the transmit data path will continue normal transmissions.
As soon as software disables transmit flow control a zero pause control frame is
transmitted to resume the receive process.
In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent
until TxFlowControl is de-asserted. If the medium is idle, the Ethernet block begins
transmitting preamble, which raises carrier sense causing all other stations to defer. In the
event the transmitting of preamble causes a collision, the backpressure ‘rides through’ the
collision. The colliding station backs off and then defers to the backpressure. If during
backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame
sent and then the backpressure resumed. If TxFlowControl is asserted for longer than
3.3 ms in 10 Mbps mode or 0.33 ms in 100 Mbps mode, backpressure will cease sending
preamble for several byte times to avoid the jabber limit.
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The Ethernet MAC has several receive packet filtering functions that can be configured
from the software driver:
• Perfect address filter: allows packets with a perfectly matching station address to be
identified and passed to the software driver.
• Hash table filter: allows imperfect filtering of packets based on the station address.
• Unicast/multicast/broadcast filtering: allows passing of all unicast, multicast, and/or
broadcast packets.
• Magic packet filter: detection of magic packets to generate a Wake-on-LAN interrupt.
The filtering functions can be logically combined to create complex filtering functions.
Furthermore, the Ethernet block can pass or reject runt packets smaller than 64 bytes; a
promiscuous mode allows all packets to be passed to software.
Overview
The Ethernet block has the capability to filter out receive frames by analyzing the Ethernet
destination address in the frame. This capability greatly reduces the load on the host
system, because Ethernet frames that are addressed to other stations would otherwise
need to be inspected and rejected by the device driver software, using up bandwidth,
memory space, and host CPU time. Address filtering can be implemented using the
perfect address filter or the (imperfect) hash filter. The latter produces a 6-bit hash code
which can be used as an index into a 64 entry programmable hash table. Figure 24
depicts a functional view of the receive filter.
At the top of the diagram the Ethernet receive frame enters the filters. Each filter is
controlled by signals from control registers; each filter produces a ‘Ready’ output and a
‘Match’ output. If ‘Ready’ is 0 then the Match value is ‘don’t care’; if a filter finishes filtering
then it will assert its Ready output; if the filter finds a matching frame it will assert the
Match output along with the Ready output. The results of the filters are combined by logic
functions into a single RxAbort output. If the RxAbort output is asserted, the frame does
not need to be received.
In order to reduce memory traffic, the receive data path has a buffer of 68 bytes. The
Ethernet MAC will only start writing a frame to memory after 68 byte delays. If the RxAbort
signal is asserted during the initial 68 bytes of the frame, the frame can be discarded and
removed from the buffer and not stored to memory at all, not using up receive descriptors,
etc. If the RxAbort signal is asserted after the initial 68 bytes in a frame (probably due to
reception of a Magic Packet), part of the frame is already written to memory and the
Ethernet MAC will stop writing further data in the frame to memory; the FailFilter bit in the
status word of the frame will be set to indicate that the software device driver can discard
the frame immediately.
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packet
AcceptUnicastEn
AcceptMulticastEn
StationAddress
IMPERFECT PERFECT
AcceptMulticastHashEn
HASH ADDRESS
AcceptPerfectEn
AcceptUnicastHashEn FILTER FILTER
HashFilter
PAReady
H FMatc h
PAMatch
HFReady
CRC
OK?
FMatch
RxFilterWoL
RxFilterEnWoL
RxAbort
FReady
Generic filtering based on the type of frame (unicast, multicast or broadcast) can be
programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bits
of the RxFilterCtrl register. Setting the AcceptUnicast, AcceptMulticast, and
AcceptBroadcast bits causes all frames of types unicast, multicast and broadcast,
respectively, to be accepted, ignoring the Ethernet destination address in the frame. To
program promiscuous mode, i.e. to accept all frames, set all 3 bits to 1.
When a frame with a unicast destination address is received, a perfect filter compares the
destination address with the 6 byte station address programmed in the station address
registers SA0, SA1, SA2. If the AcceptPerfectEn bit in the RxFilterCtrl register is set to 1,
and the address matches, the frame is accepted.
An imperfect filter is available, based on a hash mechanism. This filter applies a hash
function to the destination address and uses the hash to access a table that indicates if
the frame should be accepted. The advantage of this type of filter is that a small table can
cover any possible address. The disadvantage is that the filtering is imperfect, i.e.
sometimes frames are accepted that should have been discarded.
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• Hash function:
– The standard Ethernet cyclic redundancy check (CRC) function is calculated from
the 6 byte destination address in the Ethernet frame (this CRC is calculated
anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of
the 32-bit CRC result are taken to form the hash. The 6-bit hash is used to access
the hash table: it is used as an index in the 64-bit HashFilter register that has been
programmed with accept values. If the selected accept value is 1, the frame is
accepted.
– The device driver can initialize the hash filter table by writing to the registers
HashFilterL and HashfilterH. HashFilterL contains bits 0 through 31 of the table
and HashFilterH contains bit 32 through 63 of the table. So, hash value 0
corresponds to bit 0 of the HashfilterL register and hash value 63 corresponds to
bit 31 of the HashFilterH register.
• Multicast and unicast
– The imperfect hash filter can be applied to multicast addresses, by setting the
AcceptMulticastHashEn bit in the RxFilter register to 1.
– The same imperfect hash filter that is available for multicast addresses can also be
used for unicast addresses. This is useful to be able to respond to a multitude of
unicast addresses without enabling all unicast addresses. The hash filter can be
applied to unicast addresses by setting the AcceptUnicastHashEn bit in the
RxFilter register to 1.
The filters as defined in the sections above can be bypassed by setting the PassRxFilter
bit in the Command register. When the PassRxFilter bit is set, all receive frames will be
passed to memory. In this case the device driver software has to implement all filtering
functionality in software. Setting the PassRxFilter bit does not affect the runt frame filtering
as defined in the next section.
Runt frames
A frame with less than 64 bytes (or 68 bytes for VLAN frames) is shorter than the
minimum Ethernet frame size and therefore considered erroneous; they might be collision
fragments. The receive data path automatically filters and discards these runt frames
without writing them to memory and using a receive descriptor.
When a runt frame has a correct CRC there is a possibility that it is intended to be useful.
The device driver can receive the runt frames with correct CRC by setting the
PassRuntFrame bit of the Command register to 1.
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The Ethernet block supports power management with remote wake-up over LAN. The
host system can be powered down, even including part of the Ethernet block itself, while
the Ethernet block continues to listen to packets on the LAN. Appropriately formed
packets can be received and recognized by the Ethernet block and used to trigger the
host system to wake up from its power-down state.
Wake-up of the system takes effect through an interrupt. When a wake-up event is
detected, the WakeupInt bit in the IntStatus register is set. The interrupt status will trigger
an interrupt if the corresponding WakeupIntEn bit in the IntEnable register is set. This
interrupt should be used by system power management logic to wake up the system.
While in a power-down state the packet that generates a Wake-up on LAN event is lost.
There are two ways in which Ethernet packets can trigger wake-up events: generic
Wake-up on LAN and Magic Packet. Magic Packet filtering uses an additional filter for
Magic Packet detection. In both cases a Wake-up on LAN event is only triggered if the
triggering packet has a valid CRC. Figure 24 shows the generation of the wake-up signal.
The RxFilterWoLStatus register can be read by the software to inspect the reason for a
Wake-up event. Before going to power-down the power management software should
clear the register by writing the RxFilterWolClear register.
NOTE: when entering in power-down mode, a receive frame might be not entirely stored
into the Rx buffer. In this situation, after turning exiting power-down mode, the next
receive frame is corrupted due to the data of the previous frame being added in front of
the last received frame. Software drivers have to reset the receive data path just after
exiting power-down mode.
The receive filter functionality can be used to generate Wake-up on LAN events. If the
RxFilterEnWoL bit of the RxFilterCtrl register is set, the receive filter will set the WakeupInt
bit of the IntStatus register if a frame is received that passes the filter. The interrupt will
only be generated if the CRC of the frame is correct.
The Ethernet block supports wake-up using Magic Packet technology (see ‘Magic Packet
technology’, Advanced Micro Devices). A Magic Packet is a specially formed packet solely
intended for wake-up purposes. This packet can be received, analyzed and recognized by
the Ethernet block and used to trigger a wake-up event.
A Magic Packet is a packet that contains in its data portion the station address repeated
16 times with no breaks or interruptions, preceded by 6 Magic Packet synchronization
bytes with the value 0xFF. Other data may be surrounding the Magic Packet pattern in the
data portion of the packet. The whole packet must be a well-formed Ethernet frame.
The magic packet detection unit analyzes the Ethernet packets, extracts the packet
address and checks the payload for the Magic Packet pattern. The address from the
packet is used for matching the pattern (not the address in the SA0/1/2 registers.) A magic
packet only sets the wake-up interrupt status bit if the packet passes the receive filter as
illustrated in Figure 24: the result of the receive filter is ANDed with the magic packet filter
result to produce the result.
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Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl
register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the
RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all
packets for a matching address, not just the Magic Packets i.e. WoL using Magic Packets
is more strict.
When a magic packet is detected, apart from the WakeupInt bit in the IntStatus register,
the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software can reset the
bit writing a 1 to the corresponding bit of the RxFilterWoLClear register.
Example: An example of a Magic Packet with station address 0x11 0x22 0x33 0x44 0x55
0x66 is the following (MISC indicates miscellaneous additional data bytes in the packet):
After reset, the receive function of the Ethernet block is disabled. The receive function can
be enabled by the device driver setting the RxEnable bit in the Command register and the
“RECEIVE ENABLE’ bit in the MAC1 configuration register (in that order).
The status of the receive data path can be monitored by the device driver by reading the
RxStatus bit of the Status register. Figure 25 illustrates the state machine for the
generation of the RxStatus bit.
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ACTIVE
RxStatus = 1
xxxxxxxxxxxxxxxxxx
INACTIVE
RxStatus = 0
reset
After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is
set in the Command register, the state machine transitions to the ACTIVE state. As soon
as the RxEnable bit is cleared, the state machine returns to the INACTIVE state. If the
receive data path is busy receiving a packet while the receive data path gets disabled, the
packet will be received completely, stored to memory along with its status before returning
to the INACTIVE state. Also if the Receive descriptor array is full, the state machine will
return to the INACTIVE state.
For the state machine in Figure 25, a soft reset is like a hardware reset assertion, i.e. after
a soft reset the receive data path is inactive until the data path is re-enabled.
After reset, the transmit function of the Ethernet block is disabled. The Tx transmit data
path can be enabled by the device driver setting the TxEnable bit in the Command
register to 1.
The status of the transmit data paths can be monitored by the device driver reading the
TxStatus bit of the Status register. Figure 26 illustrates the state machine for the
generation of the TxStatus bit.
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ACTIVE
TxStatus = 1
xxxxxxxxxxxxxxxxxxxxxx
INACTIVE
TxStatus = 0
reset
After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set
in the Command register and the Produce and Consume indices are not equal, the state
machine transitions to the ACTIVE state. As soon as the TxEnable bit is cleared and the
transmit data path has completed all pending transmissions, including committing the
transmission status to memory, the state machine returns to the INACTIVE state. The
state machine will also return to the INACTIVE state if the Produce and Consume indices
are equal again i.e. all frames have been transmitted.
For the state machine in Figure 26, a soft reset is like a hardware reset assertion, i.e. after
a soft reset the transmit data path is inactive until the data path is re-enabled.
The effective pad enable (EPADEN) is equal to the ‘PAD/CRC ENABLE’ bit from the
MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then
EPADEN will be taken from the descriptor Pad bit. Likewise the effective CRC enable
(ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from the
descriptor.
If padding is required and enabled, a CRC will always be appended to the padded frames.
A CRC will only be appended to the non-padded frames if ECRCE is set.
If EPADEN is 0, the frame will not be padded and no CRC will be added unless ECRCE is
set.
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If EPADEN is 1, then small frames will be padded and a CRC will always be added to the
padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be
padded to 60 bytes and a CRC will be added creating 64 bytes frames; if VLPEN is 1, the
frames will be padded to 64 bytes and a CRC will be added creating 68 bytes frames; if
ADPEN is 1, while VLPEN is 0 VLAN frames will be padded to 64 bytes, non VLAN
frames will be padded to 60 bytes, and a CRC will be added to padded frames, creating
64 or 68 bytes padded frames.
If CRC generation is enabled, CRC generation can be delayed by four bytes by setting the
DELAYED CRC bit in the MAC2 register, in order to skip proprietary header information.
When enabling huge frames, the Ethernet block will not check frame lengths and report
frame length errors (RangeError and LengthError). If huge frames are enabled, the
received byte count in the RSV register may be invalid because the frame may exceed the
maximum size; the RxSize fields from the receive status arrays will be valid.
Frame lengths are checked by comparing the length/type field of the frame to the actual
number of bytes in the frame. A LengthError is reported by setting the corresponding bit in
the receive StatusInfo word.
The MAXF register allows the device driver to specify the maximum number of bytes in a
frame. The Ethernet block will compare the actual receive frame to the MAXF value and
report a RangeError in the receive StatusInfo word if the frame is larger.
The approach taken here is that by default all counters are implemented in software. With
the help of the StatusInfo field in frame statuses, many of the important statistics events
listed in the standards can be counted by software.
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10.17.18 Reset
The Ethernet block has a hard reset input which is connected to the chip reset, as well as
several soft resets which can be activated by setting the appropriate bit(s) in registers. All
registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise
specified.
Hard reset
After a hard reset, all registers will be set to their default value.
Soft reset
Parts of the Ethernet block can be soft reset by setting bits in the Command register and
the MAC1 configuration register.The MAC1 register has six different reset bits:
• SOFT RESET: Setting this bit will put all modules in the MAC in reset, except for the
MAC registers (at addresses 0x000 to 0x0FC). The value of the soft reset after a
hardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware
reset.
• TxReset: Writing a ‘1’ to the TxReset bit will reset the transmit data path, excluding the
MAC portions, including all (read-only) registers in the transmit data path, as well as
the TxProduceIndex register in the host registers module. A soft reset of the transmit
data path will abort all AHB transactions of the transmit data path. The reset bit will be
cleared autonomously by the Ethernet block. A soft reset of the Tx data path will clear
the TxStatus bit in the Status register.
• RxReset: Writing a ‘1’ to the RxReset bit will reset the receive data path, excluding the
MAC portions, including all (read-only) registers in the receive data path, as well as
the RxConsumeIndex register in the host registers module. A soft reset of the receive
data path will abort all AHB transactions of the receive data path. The reset bit will be
cleared autonomously by the Ethernet block. A soft reset of the Rx data path will clear
the RxStatus bit in the Status register.
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• RegReset: Resets all of the data paths and registers in the host registers module,
excluding the registers in the MAC. A soft reset of the registers will also abort all AHB
transactions of the transmit and receive data path. The reset bit will be cleared
autonomously by the Ethernet block.
To do a full soft reset of the Ethernet block, device driver software must:
To reset just the transmit data path, the device driver software has to:
• Disable the receive function by resetting the ‘RECEIVE ENABLE’ bit in the MAC1
configuration register and resetting of the RxEnable bit of the Command register.
• Set the ‘RESET MCS/Rx’ bit in the MAC1 register to 1.
• Set the RxReset bit in the Command register, this bit clears automatically.
• Reset the ‘RESET MCS/Rx’ bit in the MAC1 register to 0.
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By making some assumptions, the bandwidth needed for each type of AHB transfer can
be calculated and added in order to find the overall bandwidth requirement.
The flexibility of the descriptors used in the Ethernet block allows the possibility of defining
memory buffers in a range of sizes. In order to analyze bus bandwidth requirements,
some assumptions must be made about these buffers. The "worst case" is not addressed
since that would involve all descriptors pointing to single byte buffers, with most of the
memory occupied in holding descriptors and very little data. It can easily be shown that
the AHB cannot handle the huge amount of bus traffic that would be caused by such a
degenerate (and illogical) case.
This analysis does not reflect the flow of Ethernet traffic over time, which would include
inter-packet gaps in both the transmit and receive channels that reduce the bandwidth
requirements over a larger time frame.
The interface to an external Ethernet PHY is via RMII. RMII operates at 50 MHz,
transferring a byte in 4 clock cycles. The data transfer rate is 12.5 Mbps.
The Ethernet block initiates DMA accesses for the following cases:
• Tx descriptor read:
– Transmit descriptors occupy 2 words (8 bytes) of memory and are read once for
each use of a descriptor.
– Two word read happens once every 64 bytes (16 words) of transmitted data.
– This gives 1/8th of the data rate, which = 1.5625 Mbps.
• Rx descriptor read:
– Receive descriptors occupy 2 words (8 bytes) of memory and are read once for
each use of a descriptor.
– Two word read happens once every 64 bytes (16 words) of received data.
– This gives 1/8th of the data rate, which = 1.5625 Mbps.
• Tx status write:
– Transmit status occupies 1 word (4 bytes) of memory and is written once for each
use of a descriptor.
– One word write happens once every 64 bytes (16 words) of transmitted data.
– This gives 1/16th of the data rate, which = 0.7813 Mbps.
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• Rx status write:
– Receive status occupies 2 words (8 bytes) of memory and is written once for each
use of a descriptor.
– Two word write happens once every 64 bytes (16 words) of received data.
– This gives 1/8 of the data rate, which = 1.5625 Mbps.
• Tx data read:
– Data transmitted in an Ethernet frame, the size is variable.
– Basic Ethernet rate = 12.5 Mbps.
• Rx data write:
– Data to be received in an Ethernet frame, the size is variable.
– Basic Ethernet rate = 12.5 Mbps.
This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function.
This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function.
The peak bandwidth requirement can be somewhat higher due to the use of small
memory buffers, in order to hold often used addresses (e.g. the station address) for
example. Driver software can determine how to build frames in an efficient manner that
does not overutilize the AHB.
The bandwidth available on the AHB bus depends on the system clock frequency. As an
example, assume that the system clock is set at 60 MHz. All or nearly all of bus accesses
related to the Ethernet will be word transfers. The raw AHB bandwidth can be
approximated as 4 bytes per two system clocks, which equals 2 times the system clock
rate. With a 60 MHz system clock, the bandwidth is 120 MB/s, giving about 55% utilization
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for Ethernet traffic during simultaneous transmit and receive operations. This shows that it
is not necessary to use the maximum CPU frequency for the Ethernet to work with plenty
of bandwidth headroom.
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For FCS calculation, this function is passed a pointer to the first byte of the frame and the
length of the frame without the FCS.
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For hash filtering, this function is passed a pointer to the destination address part of the
frame and the CRC is only calculated on the 6 address bytes. The hash filter uses bits
[28:23] for indexing the 64-bits { HashFilterH, HashFilterL } vector. If the corresponding bit
is set the packet is passed, otherwise it is rejected by the hash filter.
For obtaining the destination and source address hash CRCs, this function calculates first
both the 32-bit CRCs, then the nine most significant bits from each 32-bit CRC are
extracted, concatenated, and written in every StatusHashCRC word of every fragment
status.
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11.3 Introduction
The Universal Serial Bus (USB) is a four-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
For more information on the Universal Serial Bus, see the USB Implementers Forum
website.
The USB device controller on the LPC17xx enables full-speed (12 Mb/s) data exchange
with a USB host controller.
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Table 184. USB related acronyms, abbreviations, and definitions used in this chapter
Acronym/abbreviation Description
AHB Advanced High-performance bus
ATLE Auto Transfer Length Extraction
ATX Analog Transceiver
DD DMA Descriptor
DDP DMA Description Pointer
DMA Direct Memory Access
EOP End-Of-Packet
EP Endpoint
EP_RAM Endpoint RAM
FS Full Speed
LED Light Emitting Diode
LS Low Speed
MPS Maximum Packet Size
NAK Negative Acknowledge
PLL Phase Locked Loop
RAM Random Access Memory
SOF Start-Of-Frame
SIE Serial Interface Engine
SRAM Synchronous RAM
UDCA USB Device Communication Area
USB Universal Serial Bus
11.4 Features
• Fully compliant with the USB 2.0 specification (full speed).
• Supports 32 physical (16 logical) endpoints.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
• Supports SoftConnect and GoodLink features.
• Supports DMA transfers on all non-control endpoints.
• Allows dynamic switching between CPU controlled and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.
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BUS VBUS
MASTER DMA
USB_CONNECT
INTERFACE ENGINE
DMA interface
(AHB master)
USB_D+
AHB BUS
USB ATX
EP_RAM SERIAL
REGISTER
ACCESS INTERFACE
INTERFACE
CONTROL ENGINE
USB_D-
USB_UP_LED
register
interface EP_RAM
(AHB slave) USB DEVICE (4K)
BLOCK
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11.6.7 SoftConnect
The connection to the USB is accomplished by bringing D+ (for a full-speed device) HIGH
through a 1.5 kOhm pull-up resistor. The SoftConnect feature can be used to allow
software to finish its initialization sequence before deciding to establish connection to the
USB. Re-initialization of the USB bus connection can also be performed without having to
unplug the cable.
To use the SoftConnect feature, the CONNECT signal should control an external switch
that connects the 1.5 kOhm resistor between D+ and +3.3V. Software can then control the
CONNECT signal by writing to the CON bit using the SIE Set Device Status command.
11.6.8 GoodLink
Good USB connection indication is provided through GoodLink technology. When the
device is successfully enumerated and configured, the LED indicator will be permanently
ON. During suspend, the LED will be OFF.
This feature provides a user-friendly indicator on the status of the USB device. It is a
useful field diagnostics tool to isolate faulty equipment.
To use the GoodLink feature the UP_LED signal should control an LED. The UP_LED
signal is controlled using the SIE Configure Device command.
For an OUT transaction, the USB ATX receives the bi-directional D+ and D- signals of the
USB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX and
converts it into a parallel data stream. The parallel data is written to the corresponding
endpoint buffer in the EP_RAM.
For IN transactions, the SIE reads the parallel data from the endpoint buffer in EP_RAM,
converts it into serial data, and transmits it onto the USB bus using the USB ATX.
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Once data has been received or sent, the endpoint buffer can be read or written. How this
is accomplished depends on the endpoint’s type and operating mode. The two operating
modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode.
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface. See Section 11.14 “Slave mode operation” for a detailed description of
this mode.
In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See
Section 11.15 “DMA operation” for a detailed description of this mode.
1. A device in the non-configured state should draw a maximum of 100 mA from the bus.
2. A configured device can draw only up to what is specified in the Max Power field of
the configuration descriptor. The maximum value is 500 mA.
3. A suspended device can draw a maximum of 2.5 mA.
11.9.2 Clocks
The USB device controller clocks are shown in Table 187
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When the USB Device Controller goes into the suspend state (bus is idle for 3 ms), the
usbclk input to the device controller is automatically disabled, helping to conserve power.
However, if software wishes to access the device controller registers, usbclk must be
active. To allow access to the device controller registers while in the suspend state, the
USBClkCtrl and USBClkSt registers are provided.
When software wishes to access the device controller registers, it should first ensure
usbclk is enabled by setting DEV_CLK_EN in the USBClkCtrl register, and then poll the
corresponding DEV_CLK_ON bit in USBClkSt until set. Once set, usbclk will remain
enabled until DEV_CLK_EN is cleared by software.
When a DMA transfer occurs, the device controller automatically turns on the AHB master
clock. Once asserted, it remains active for a minimum of 2 ms (2 frames), to help ensure
that DMA throughput is not affected by turning off the AHB master clock. 2 ms after the
last DMA access, the AHB master clock is automatically disabled to help conserve power.
If desired, software also has the capability of forcing this clock to remain enabled using the
USBClkCtrl register.
Note that the AHB slave clock is always enabled as long as the PCUSB bit of PCONP is
set. When the device controller is not in use, all of the device controller clocks may be
disabled by clearing PCUSB.
The USB_NEED_CLK signal is used to facilitate going into and waking up from chip
Power-down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt
register are asserted.
After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the
DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off.
When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put
into Power-down mode by writing to the PCON register. The status of USB_NEED_CLK
can be read from the USBIntSt register.
Any bus activity in the suspend state will cause the USB_NEED_CLK signal to be
asserted. When the chip is in Power-down mode and the USB interrupt is enabled, the
assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode.
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[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
[2] Reading WO register will return an invalid value.
The software does not have to repeat this exercise for every register access, provided that
the corresponding USBClkCtrl bits are already set. Note that this register is functional only
when the PCUSB bit of PCONP is set; when PCUSB is cleared, all clocks to the device
controller are disabled irrespective of the contents of this register. USBClkCtrl is a
read/write register.
Table 189. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description
Bit Symbol Description Reset value
0 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
1 DEV_CLK_EN Device clock enable. Enables the usbclk input to the device controller 0
2 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
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Table 189. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description
Bit Symbol Description Reset value
3 - Reserved. User software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
4 AHB_CLK_EN AHB clock enable 0
31:5 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
Table 190. USB Clock Status register (USBClkSt - address 0x5000 CFF8) bit description
Bit Symbol Description Reset value
0 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
1 DEV_CLK_ON Device clock on. The usbclk input to the device controller is active. 0
3:2 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
4 AHB_CLK_ON AHB clock on. 0
31:5 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
Table 191. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description
Bit Symbol Description Reset value
0 USB_INT_REQ_LP Low priority interrupt line status. This bit is read-only. 0
1 USB_INT_REQ_HP High priority interrupt line status. This bit is read-only. 0
2 USB_INT_REQ_DMA DMA interrupt line status. This bit is read-only. 0
7:3 - These bits are reserved in a device-only configuration. User software should NA
not write ones to reserved bits. The value read from a reserved bit is not
defined. See Table 257 for OTG configuration.
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Table 191. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description
Bit Symbol Description Reset value
8 USB_NEED_CLK USB need clock indicator. This bit is set to 1 when USB activity or a change 1
of state on the USB data pins is detected, and it indicates that a PLL supplied
clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets
to zero 5 ms after the last packet has been received/sent, or 2 ms after the
Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from
0 to 1 can wake up the microcontroller if activity on the USB bus is selected
to wake up the part from the Power-down mode (see Section 4.8.8 “Wake-up
from Reduced Power Modes” for details). Also see Section 4.5.9 “PLL0 and
Power-down mode” and Section 4.8.9 “Power Control for Peripherals
register (PCONP - 0x400F C0C4)” for considerations about the PLL and
invoking the Power-down mode. This bit is read-only.
30:9 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
31 EN_USB_INTS Enable all USB interrupts. When this bit is cleared, the Vectored Interrupt 1
Controller does not see the ORed output of the USB interrupt lines.
Table 192. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol - - - - - - - -
Bit 23 22 21 20 19 18 17 16
Symbol - - - - - - - -
Bit 15 14 13 12 11 10 9 8
Symbol - - - - - - ERR_INT EP_RLZED
Bit 7 6 5 4 3 2 1 0
Symbol TxENDPKT Rx CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME
ENDPKT
Table 193. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description
Bit Symbol Description Reset value
0 FRAME The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. 0
1 EP_FAST Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, 0
the corresponding endpoint interrupt will be routed to this bit.
2 EP_SLOW Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is 0
not set, the corresponding endpoint interrupt will be routed to this bit.
3 DEV_STAT Set when USB Bus reset, USB suspend change or Connect change event occurs. 0
Refer to Section 11.12.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” on
page 247.
4 CCEMPTY The command code register (USBCmdCode) is empty (New command can be written). 1
5 CDFULL Command data register (USBCmdData) is full (Data can be read now). 0
6 RxENDPKT The current packet in the endpoint buffer is transferred to the CPU. 0
7 TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of bytes 0
programmed in the TxPacket length register (USBTxPLen).
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Table 193. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description
Bit Symbol Description Reset value
8 EP_RLZED Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize 0
register (USBMaxPSize) is updated and the corresponding operation is completed.
9 ERR_INT Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 11.12.9 0
“Read Error Status (Command: 0xFB, Data: read 1 byte)” on page 249
31:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 194. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol - - - - - - - -
Bit 23 22 21 20 19 18 17 16
Symbol - - - - - - - -
Bit 15 14 13 12 11 10 9 8
Symbol - - - - - - ERR_INT EP_RLZED
Bit 7 6 5 4 3 2 1 0
Symbol TxENDPKT Rx CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME
ENDPKT
Table 195. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit description
Bit Symbol Value Description Reset value
31:0 See 0 No interrupt is generated. 0
USBDevIntEn 1 An interrupt will be generated when the corresponding bit in the Device
bit allocation Interrupt Status (USBDevIntSt) register (Table 192) is set. By default, the
table above interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
interrupt line by changing the value of USBDevIntPri.
Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding
endpoint interrupts in USBEpIntSt should be cleared.
Table 196. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol - - - - - - - -
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Bit 23 22 21 20 19 18 17 16
Symbol - - - - - - - -
Bit 15 14 13 12 11 10 9 8
Symbol - - - - - - ERR_INT EP_RLZED
Bit 7 6 5 4 3 2 1 0
Symbol TxENDPKT Rx CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME
ENDPKT
Table 197. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit description
Bit Symbol Value Description Reset value
31:0 See 0 No effect. 0
USBDevIntClr 1 The corresponding bit in USBDevIntSt (Section 11.10.2.2) is cleared.
bit allocation
table above
Table 198. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol - - - - - - - -
Bit 23 22 21 20 19 18 17 16
Symbol - - - - - - - -
Bit 15 14 13 12 11 10 9 8
Symbol - - - - - - ERR_INT EP_RLZED
Bit 7 6 5 4 3 2 1 0
Symbol TxENDPKT Rx CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME
ENDPKT
Table 199. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit description
Bit Symbol Value Description Reset value
31:0 See 0 No effect. 0
USBDevIntSet 1 The corresponding bit in USBDevIntSt (Section 11.10.2.2) is set.
bit allocation
table above
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Table 200. USB Device Interrupt Priority register (USBDevIntPri - address 0x5000 C22C) bit description
Bit Symbol Value Description Reset
value
0 FRAME 0 FRAME interrupt is routed to USB_INT_REQ_LP. 0
1 FRAME interrupt is routed to USB_INT_REQ_HP.
1 EP_FAST 0 EP_FAST interrupt is routed to USB_INT_REQ_LP. 0
1 EP_FAST interrupt is routed to USB_INT_REQ_HP.
31:2 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Note that for Isochronous endpoints, handling of packet data is done when the FRAME
interrupt occurs.
Table 201. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX
Table 202. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description
Bit Symbol Description Reset value
0 EP0RX Endpoint 0, Data Received Interrupt bit. 0
1 EP0TX Endpoint 0, Data Transmitted Interrupt bit or sent a NAK. 0
2 EP1RX Endpoint 1, Data Received Interrupt bit. 0
3 EP1TX Endpoint 1, Data Transmitted Interrupt bit or sent a NAK. 0
4 EP2RX Endpoint 2, Data Received Interrupt bit. 0
5 EP2TX Endpoint 2, Data Transmitted Interrupt bit or sent a NAK. 0
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Table 202. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description
Bit Symbol Description Reset value
6 EP3RX Endpoint 3, Isochronous endpoint. NA
7 EP3TX Endpoint 3, Isochronous endpoint. NA
8 EP4RX Endpoint 4, Data Received Interrupt bit. 0
9 EP4TX Endpoint 4, Data Transmitted Interrupt bit or sent a NAK. 0
10 EP5RX Endpoint 5, Data Received Interrupt bit. 0
11 EP5TX Endpoint 5, Data Transmitted Interrupt bit or sent a NAK. 0
12 EP6RX Endpoint 6, Isochronous endpoint. NA
13 EP6TX Endpoint 6, Isochronous endpoint. NA
14 EP7RX Endpoint 7, Data Received Interrupt bit. 0
15 EP7TX Endpoint 7, Data Transmitted Interrupt bit or sent a NAK. 0
16 EP8RX Endpoint 8, Data Received Interrupt bit. 0
17 EP8TX Endpoint 8, Data Transmitted Interrupt bit or sent a NAK. 0
18 EP9RX Endpoint 9, Isochronous endpoint. NA
19 EP9TX Endpoint 9, Isochronous endpoint. NA
20 EP10RX Endpoint 10, Data Received Interrupt bit. 0
21 EP10TX Endpoint 10, Data Transmitted Interrupt bit or sent a NAK. 0
22 EP11RX Endpoint 11, Data Received Interrupt bit. 0
23 EP11TX Endpoint 11, Data Transmitted Interrupt bit or sent a NAK. 0
24 EP12RX Endpoint 12, Isochronous endpoint. NA
25 EP12TX Endpoint 12, Isochronous endpoint. NA
26 EP13RX Endpoint 13, Data Received Interrupt bit. 0
27 EP13TX Endpoint 13, Data Transmitted Interrupt bit or sent a NAK. 0
28 EP14RX Endpoint 14, Data Received Interrupt bit. 0
29 EP14TX Endpoint 14, Data Transmitted Interrupt bit or sent a NAK. 0
30 EP15RX Endpoint 15, Data Received Interrupt bit. 0
31 EP15TX Endpoint 15, Data Transmitted Interrupt bit or sent a NAK. 0
Table 203. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
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Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX
Table 204. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit description
Bit Symbol Value Description Reset value
31:0 See USBEpIntEn bit 0 The corresponding bit in USBDMARSt is set when an interrupt occurs 0
allocation table above for this endpoint.
1 The corresponding bit in USBEpIntSt is set when an interrupt
occurs for this endpoint. Implies Slave mode for this endpoint.
Notes:
• When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be
set to ensure the corresponding interrupt has been cleared before proceeding.
• While setting multiple bits in USBEpIntClr simultaneously is possible, it is not
recommended; only the status of the endpoint corresponding to the least significant
interrupt bit cleared will be available at the end of the operation.
• Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly
invoked using the SIE command registers, but using USBEpIntClr is recommended
because of its ease of use.
Each physical endpoint has its own reserved bit in this register. The bit field definition is
the same as that of USBEpIntSt shown in Table 201. USBEpIntClr is a write-only register.
Table 205. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX
Table 206. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit description
Bit Symbol Value Description Reset value
31:0 See USBEpIntClr bit 0 No effect. 0
allocation table above 1 Clears the corresponding bit in USBEpIntSt, by executing the SIE
Select Endpoint/Clear Interrupt command for this endpoint.
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Table 207. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX
Table 208. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit description
Bit Symbol Value Description Reset value
31:0 See USBEpIntSet bit 0 No effect. 0
allocation table above 1 Sets the corresponding bit in USBEpIntSt.
Note that the USBDevIntPri register determines whether the EP_FAST interrupt is routed
to the USB_INT_REQ_HP or USB_INT_REQ_LP interrupt line.
Table 209. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX E14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX
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Table 210. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit description
Bit Symbol Value Description Reset value
31:0 See USBEpIntPri bit 0 The corresponding interrupt is routed to the EP_SLOW bit of 0
allocation table above USBDevIntSt
1 The corresponding interrupt is routed to the EP_FAST bit of
USBDevIntSt
The EP_ RAM space (in words) required for the physical endpoint can be expressed as
EPRAMspace = ⎛ -------------------------------------------------
MaxPacketSize + 3 + 1⎞ × dbstatus
⎝ - ⎠
4
where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint.
Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is
TotalEPRAMspace = 32 + ∑ EPRAMspace ( n )
n=0
where N is the number of realized endpoints. Total EP_RAM space should not exceed
4096 bytes (4 kB, 1 kwords).
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Table 211. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit allocation
Reset value: 0x0000 0003
Bit 31 30 29 28 27 26 25 24
Symbol EP31 EP30 EP29 EP28 EP27 EP26 EP25 EP24
Bit 23 22 21 20 19 18 17 16
Symbol EP23 EP22 EP21 EP20 EP19 EP18 EP17 EP16
Bit 15 14 13 12 11 10 9 8
Symbol EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8
Bit 7 6 5 4 3 2 1 0
Symbol EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
Table 212. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit description
Bit Symbol Value Description Reset value
0 EP0 0 Control endpoint EP0 is not realized. 1
1 Control endpoint EP0 is realized.
1 EP1 0 Control endpoint EP1 is not realized. 1
1 Control endpoint EP1 is realized.
31:2 EPxx 0 Endpoint EPxx is not realized. 0
1 Endpoint EPxx is realized.
On reset, only the control endpoints are realized. Other endpoints, if required, are realized
by programming the corresponding bits in USBReEp. To calculate the required EP_RAM
space for the realized endpoints, see Section 11.10.4.1.
/* check whether the EP_RLZED bit in the Device Interrupt Status register is set
*/
while (!(USBDevIntSt & EP_RLZED))
{
/* wait until endpoint realization is complete */
}
/* Clear the EP_RLZED bit */
Clear EP_RLZED bit in USBDevIntSt;
}
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The device will not respond to any transactions to unrealized endpoints. The SIE
Configure Device command will only cause realized and enabled endpoints to respond to
transactions. For details see Table 243.
The USBEpIn register will hold the physical endpoint number. Writing to USBMaxPSize
will set the array element pointed to by USBEpIn. USBEpIn is a write-only register.
Table 213. USB Endpoint Index register (USBEpIn - address 0x5000 C248) bit description
Bit Symbol Description Reset value
4:0 PHY_EP Physical endpoint number (0-31) 0
31:5 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
Table 214. USB MaxPacketSize register (USBMaxPSize - address 0x5000 C24C) bit description
Bit Symbol Description Reset value
9:0 MPS The maximum packet size value. 0x008[1]
31:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
[1] Reset value for EP0 and EP1. All other endpoints have a reset value of 0x0.
MPS_EP0
ENDPOINT INDEX
MPS_EP31
The Endpoint Index is set via the USBEpIn register. MPS_EP0 to MPS_EP31 are accessed via the
USBMaxPSize register.
Fig 28. USB MaxPacketSize register array indexing
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Table 215. USB Receive Data register (USBRxData - address 0x5000 C218) bit description
Bit Symbol Description Reset value
31:0 RX_DATA Data received. 0x0000 0000
Table 216. USB Receive Packet Length register (USBRxPlen - address 0x5000 C220) bit description
Bit Symbol Value Description Reset value
9:0 PKT_LNGTH - The remaining number of bytes to be read from the currently selected 0
endpoint’s buffer. When this field decrements to 0, the RxENDPKT bit will be
set in USBDevIntSt.
10 DV Data valid. This bit is useful for isochronous endpoints. Non-isochronous 0
endpoints do not raise an interrupt when an erroneous data packet is
received. But invalid data packet can be produced with a bus reset. For
isochronous endpoints, data transfer will happen even if an erroneous
packet is received. In this case DV bit will not be set for the packet.
0 Data is invalid.
1 Data is valid.
11 PKT_RDY - The PKT_LNGTH field is valid and the packet is ready for reading. 0
31:12 - - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
Table 217. USB Transmit Data register (USBTxData - address 0x5000 C21C) bit description
Bit Symbol Description Reset value
31:0 TX_DATA Transmit Data. 0x0000 0000
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For data buffers larger than the endpoint’s MaxPacketSize, software should submit data in
packets of MaxPacketSize, and send the remaining extra bytes in the last packet. For
example, if the MaxPacketSize is 64 bytes and the data buffer to be transferred is of
length 130 bytes, then the software sends two 64-byte packets and the remaining 2 bytes
in the last packet. So, a total of 3 packets are sent on USB. USBTxPLen is a write-only
register.
Table 218. USB Transmit Packet Length register (USBTxPLen - address 0x5000 C224) bit description
Bit Symbol Value Description Reset value
9:0 PKT_LNGTH - The remaining number of bytes to be written to the selected endpoint buffer. 0x000
This field is decremented by 4 by hardware after each write to USBTxData.
When this field decrements to 0, the TxENDPKT bit will be set in
USBDevIntSt.
31:10 - - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
Table 219. USB Control register (USBCtrl - address 0x5000 C228) bit description
Bit Symbol Value Description Reset value
0 RD_EN Read mode control. Enables reading data from the OUT endpoint buffer 0
for the endpoint specified in the LOG_ENDPOINT field using the
USBRxData register. This bit is cleared by hardware when the last word
of the current packet is read from USBRxData.
0 Read mode is disabled.
1 Read mode is enabled.
1 WR_EN Write mode control. Enables writing data to the IN endpoint buffer for the 0
endpoint specified in the LOG_ENDPOINT field using the USBTxData
register. This bit is cleared by hardware when the number of bytes in
USBTxLen have been sent.
0 Write mode is disabled.
1 Write mode is enabled.
5:2 LOG_ENDPOINT - Logical Endpoint number. 0x0
31:6 - - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 220. USB Command Code register (USBCmdCode - address 0x5000 C210) bit description
Bit Symbol Value Description Reset value
7:0 - - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
15:8 CMD_PHASE The command phase: 0x00
0x01 Write
0x02 Read
0x05 Command
23:16 CMD_CODE/ This is a multi-purpose field. When CMD_PHASE is Command or Read, 0x00
CMD_WDATA this field contains the code for the command (CMD_CODE). When
CMD_PHASE is Write, this field contains the command write data
(CMD_WDATA).
31:24 - - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
Table 221. USB Command Data register (USBCmdData - address 0x5000 C214) bit description
Bit Symbol Description Reset value
7:0 CMD_RDATA Command Read Data. 0x00
31:8 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
Table 222. USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP31 EP30 EP29 EP28 EP27 EP26 EP25 EP24
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Bit 23 22 21 20 19 18 17 16
Symbol EP23 EP22 EP21 EP20 EP19 EP18 EP17 EP16
Bit 15 14 13 12 11 10 9 8
Symbol EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8
Bit 7 6 5 4 3 2 1 0
Symbol EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
Table 223. USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit description
Bit Symbol Value Description Reset value
0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit 0
must be 0).
1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit 0
must be 0).
31:2 EPxx Endpoint xx (2 ≤ xx ≤ 31) DMA request. 0
0 DMA not requested by endpoint xx.
1 DMA requested by endpoint xx.
[1] DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0.
This register is intended for initialization prior to enabling the DMA for an endpoint. When
the DMA is enabled for an endpoint, hardware clears the corresponding bit in
USBDMARSt on completion of a packet transfer. Therefore, software should not clear the
bit using this register while the endpoint is enabled for DMA operation.
The USBDMARClr bit allocation is identical to the USBDMARSt register (Table 222).
Table 224. USB DMA Request Clear register (USBDMARClr - address 0x5000 C254) bit description
Bit Symbol Value Description Reset value
0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 0
bit must be 0).
1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit 0
must be 0).
31:2 EPxx Clear the endpoint xx (2 ≤ xx ≤ 31) DMA request. 0
0 No effect.
1 Clear the corresponding bit in USBDMARSt.
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This register allows software to raise a DMA request. This can be useful when switching
from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA
mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is
not raised by hardware. Software can then use this register to manually start the DMA
transfer.
Software can also use this register to initiate a DMA transfer to proactively fill an IN
endpoint buffer before an IN token packet is received from the host.
The USBDMARSet bit allocation is identical to the USBDMARSt register (Table 222).
Table 225. USB DMA Request Set register (USBDMARSet - address 0x5000 C258) bit description
Bit Symbol Value Description Reset value
0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit 0
must be 0).
1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must 0
be 0).
31:2 EPxx Set the endpoint xx (2 ≤ xx ≤ 31) DMA request. 0
0 No effect.
1 Set the corresponding bit in USBDMARSt.
Table 226. USB UDCA Head register (USBUDCAH - address 0x5000 C280) bit description
Bit Symbol Description Reset value
6:0 - Reserved. Software should not write ones to reserved bits. The UDCA is aligned to 0x00
128-byte boundaries.
31:7 UDCA_ADDR Start address of the UDCA. 0
Table 227. USB EP DMA Status register (USBEpDMASt - address 0x5000 C284) bit description
Bit Symbol Value Description Reset value
0 EP0_DMA_ENABLE 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and 0
the EP0_DMA_ENABLE bit must be 0).
1 EP1_DMA_ENABLE 0 Control endpoint IN (DMA cannot be enabled for this endpoint and 0
the EP1_DMA_ENABLE bit must be 0).
31:2 EPxx_DMA_ENABLE endpoint xx (2 ≤ xx ≤ 31) DMA enabled bit. 0
0 The DMA for endpoint EPxx is disabled.
1 The DMA for endpoint EPxx is enabled.
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Table 228. USB EP DMA Enable register (USBEpDMAEn - address 0x5000 C288) bit description
Bit Symbol Value Description Reset value
0 EP0_DMA_ENABLE 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and 0
the EP0_DMA_ENABLE bit value must be 0).
1 EP1_DMA_ENABLE 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the 0
EP1_DMA_ENABLE bit must be 0).
31:2 EPxx_DMA_ENABLE Endpoint xx(2 ≤ xx ≤ 31) DMA enable control bit. 0
0 No effect.
1 Enable the DMA operation for endpoint EPxx.
Table 229. USB EP DMA Disable register (USBEpDMADis - address 0x5000 C28C) bit description
Bit Symbol Value Description Reset value
0 EP0_DMA_DISABLE 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and 0
the EP0_DMA_DISABLE bit value must be 0).
1 EP1_DMA_DISABLE 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the 0
EP1_DMA_DISABLE bit value must be 0).
31:2 EPxx_DMA_DISABLE Endpoint xx (2 ≤ xx ≤ 31) DMA disable control bit. 0
0 No effect.
1 Disable the DMA operation for endpoint EPxx.
Table 230. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description
Bit Symbol Value Description Reset value
0 EOT End of Transfer Interrupt bit. 0
0 All bits in the USBEoTIntSt register are 0.
1 At least one bit in the USBEoTIntSt is set.
1 NDDR New DD Request Interrupt bit. 0
0 All bits in the USBNDDRIntSt register are 0.
1 At least one bit in the USBNDDRIntSt is set.
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Table 230. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description
Bit Symbol Value Description Reset value
2 ERR System Error Interrupt bit. 0
0 All bits in the USBSysErrIntSt register are 0.
1 At least one bit in the USBSysErrIntSt is set.
31:3 - - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
Table 231. USB DMA Interrupt Enable register (USBDMAIntEn - address 0x5000 C294) bit description
Bit Symbol Value Description Reset value
0 EOT End of Transfer Interrupt enable bit. 0
0 The End of Transfer Interrupt is disabled.
1 The End of Transfer Interrupt is enabled.
1 NDDR New DD Request Interrupt enable bit. 0
0 The New DD Request Interrupt is disabled.
1 The New DD Request Interrupt is enabled.
2 ERR System Error Interrupt enable bit. 0
0 The System Error Interrupt is disabled.
1 The System Error Interrupt is enabled.
31:3 - - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
11.10.7.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0x5000 C2A0)
When the DMA transfer completes for the current DMA descriptor, either normally
(descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in
this register. The cause of the interrupt is recorded in the DD_status field of the descriptor.
USBEoTIntSt is a read-only register.
Table 232. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0x5000 C2A0s) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0
0 There is no End of Transfer interrupt request for endpoint xx.
1 There is an End of Transfer Interrupt request for endpoint xx.
11.10.7.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0x5000 C2A4)
Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt
register. Writing zero has no effect. USBEoTIntClr is a write-only register.
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Table 233. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address 0x5000 C2A4) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Clear endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0
0 No effect.
1 Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
11.10.7.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0x5000 C2A8)
Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register.
Writing zero has no effect. USBEoTIntSet is a write-only register.
Table 234. USB End of Transfer Interrupt Set register (USBEoTIntSet - address 0x5000 C2A8) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Set endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0
0 No effect.
1 Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
Table 235. USB New DD Request Interrupt Status register (USBNDDRIntSt - address 0x5000 C2AC) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0
0 There is no new DD interrupt request for endpoint xx.
1 There is a new DD interrupt request for endpoint xx.
Table 236. USB New DD Request Interrupt Clear register (USBNDDRIntClr - address 0x5000 C2B0) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Clear endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0
0 No effect.
1 Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
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Table 237. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0x5000 C2B4) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Set endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0
0 No effect.
1 Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
11.10.7.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0x5000 C2B8)
If a system error (AHB bus error) occurs when transferring the data or when fetching or
updating the DD the corresponding bit is set in this register. USBSysErrIntSt is a read-only
register.
Table 238. USB System Error Interrupt Status register (USBSysErrIntSt - address 0x5000 C2B8) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0
0 There is no System Error Interrupt request for endpoint xx.
1 There is a System Error Interrupt request for endpoint xx.
11.10.7.17 USB System Error Interrupt Clear register (USBSysErrIntClr - 0x5000 C2BC)
Writing one to a bit in this register clears the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntClr is a write-only register.
Table 239. USB System Error Interrupt Clear register (USBSysErrIntClr - address 0x5000 C2BC) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Clear endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0
0 No effect.
1 Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
11.10.7.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0x5000 C2C0)
Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntSet is a write-only register.
Table 240. USB System Error Interrupt Set register (USBSysErrIntSet - address 0x5000 C2C0) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Set endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0
0 No effect.
1 Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet has been successfully transmitted or when a NAK
signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see
Section 11.12.3. For isochronous endpoints, a frame interrupt is generated every 1 ms.
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Slave mode
If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the
USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For
non-isochronous endpoints, all endpoint interrupt events are divided into two types by the
corresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpoint
interrupt events. All fast endpoint interrupt events are ORed and routed to bit EP_FAST in
the USBDevIntSt register. All slow endpoint interrupt events are ORed and routed to the
EP_SLOW bit in USBDevIntSt.
For isochronous endpoints, the FRAME bit in USBDevIntSt is set every 1 ms.
The USBDevIntSt register holds the status of all endpoint interrupt events as well as the
status of various other interrupts (see Section 11.10.2.2). By default, all interrupts (if
enabled in USBDevIntEn) are routed to the USB_INT_REQ_LP bit in the USBIntSt
register to request low priority interrupt handling. However, the USBDevIntPri register can
route either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt
register.
Only one of the EP_FAST and FRAME interrupt events can be routed to the
USB_INT_REQ_HP bit. If routing both bits to USB_INT_REQ_HP is attempted, both
interrupt events are routed to USB_INT_REQ_LP.
Slow endpoint interrupt events are always routed directly to the USB_INT_REQ_LP bit for
low priority interrupt handling by software.
The final interrupt signal to the NVIC is gated by the EN_USB_INTS bit in the USBIntSt
register. The USB interrupts are routed to the NVIC only if EN_USB_INTS is set.
DMA mode
If an interrupt event occurs on a non-control endpoint and the endpoint interrupt is not
enabled in the USBEpIntEn register, the corresponding status bit in the USBDMARSt is
set by hardware. This serves as a flag for the DMA engine to transfer data if DMA transfer
is enabled for the corresponding endpoint in the USBEpDMASt register.
Three types of interrupts can occur for each endpoint for data transfers in DMA mode: End
of transfer interrupt, new DD request interrupt, and system error interrupt. These interrupt
events set a bit for each endpoint in the respective registers USBEoTIntSt,
USBNDDRIntSt, and USBSysErrIntSt. The End of transfer interrupts from all endpoints
are then Ored and routed to the EOT bit in USBDMAIntSt. Likewise, all New DD request
interrupts and system error interrupt events are routed to the NDDR and ERR bits
respectively in the USBDMAStInt register.
The EOT, NDDR, and ERR bits (if enabled in USBDMAIntEn) are ORed to set the
USB_INT_REQ_DMA bit in the USBIntSt register. If the EN_USB_INTS bit is set in
USBIntSt, the interrupt is routed to the NVIC.
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interrupt
event on
EPn
Slave mode
from other
USBEpIntSt Endpoints
. USBDevIntSt
.
.
. FRAME
. EP_FAST
n . EP_SLOW
.
. USBDevIntPri[0] .
.
.
.
. .
. .
. .
USBEpIntEn[n] . .
.
USBEpIntPri[n] .. USBDevIntPri[1]
.
ERR_INT
USBDMARSt USBIntSt
USB_INT_REQ_HP
USB_INT_REQ_LP to NVIC
USB_INT_REQ_DMA
n to DMA engine
EN_USB_INTS
USBEoTIntST
DMA Mode
0
.
.
.
.
31
USBNDDRIntSt
0 USBDMAIntSt
. EOT
.
. NDDR
.
ERR
31
USBSysErrIntSt
0
.
.
.
.
31
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1. Command phase: the USBCmdCode register is written with the CMD_PHASE field
set to the value 0x05 (Command), and the CMD_CODE field set to the desired
command code. On completion of the command, the CCEMPTY bit of USBDevIntSt is
set.
2. Data phase (optional): for writes, the USBCmdCode register is written with the
CMD_PHASE field set to the value 0x01 (Write), and the CMD_WDATA field set with
the desired write data. On completion of the write, the CCEMPTY bit of USBDevIntSt
is set. For reads, USBCmdCode register is written with the CMD_PHASE field set to
the value 0x02 (Read), and the CMD_CODE field set with command code the read
corresponds to. On completion of the read, the CDFULL bit of USBDevInSt will be set,
indicating the data is available for reading in the USBCmdData register. In the case of
multi-byte registers, the least significant byte is accessed first.
Here is an example of the Read Current Frame Number command (reading 2 bytes):
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[1] This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints.
[2] This bit should be reset to 0 if the DMA is enabled for any of the Bulk OUT endpoints.
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• In case no SOF was received by the device at the beginning of a frame, the frame
number returned is that of the last successfully received SOF.
• In case the SOF frame number contained a CRC error, the frame number returned will
be the corrupted frame number as received by the device.
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Remark: To ensure correct operation, the DEV_STAT bit of USBDevIntSt must be cleared
before executing the Get Device Status command.
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11.12.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))
The Select Endpoint command initializes an internal pointer to the start of the selected
buffer in EP_RAM. Optionally, this command can be followed by a data read, which
returns some additional information on the packet(s) in the endpoint buffer(s). The
command code of the Select Endpoint command is equal to the physical endpoint
number. In the case of a single buffered endpoint the B_2_FULL bit is not valid.
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• They clear the bit corresponding to the endpoint in the USBEpIntSt register.
• In case of a control OUT endpoint, they clear the STP and PO bits in the
corresponding Select Endpoint Register.
• Reading one byte is obligatory.
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Remark: This command may be invoked by using the USBCmdCode and USBCmdData
registers, or by setting the corresponding bit in USBEpIntClr. For ease of use, using the
USBEpIntClr register is recommended.
11.12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte
(optional))
The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The
Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical
endpoint number in hex. Not all bits can be set for all types of endpoints.
When bit 0 of the optional data byte is 1, the previously received packet was over-written
by a SETUP packet. The Packet over-written bit is used only in control transfers.
According to the USB specification, a SETUP packet should be accepted irrespective of
the buffer status. The software should always check the status of the PO bit after reading
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the SETUP data. If it is set then it should discard the previously read data, clear the PO bit
by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and
again check the status of the PO bit.
See Section 11.14 “Slave mode operation” for a description of when this command is
used.
Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the
Validate Buffer command and cleared when the data has been sent on the USB bus and
the buffer is empty.
A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet
Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP
packet. For the control endpoint the validated buffer will be invalidated when a SETUP
packet is received.
See Section 11.14 “Slave mode operation” for a description of when this command is
used.
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6. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the
EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized.
7. Enable endpoint interrupts (Slave mode):
– Clear all endpoint interrupts using USBEpIntClr.
– Clear any device interrupts using USBDevIntClr.
– Enable Slave mode for the desired endpoints by setting the corresponding bits in
USBEpIntEn.
– Set the priority of each enabled interrupt using USBEpIntPri.
– Configure the desired interrupt mode using the SIE Set Mode command.
– Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW,
and possibly EP_FAST).
8. Configure the DMA (DMA mode):
– Disable DMA operation for all endpoints using USBEpDMADis.
– Clear any pending DMA requests using USBDMARClr.
– Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and
USBSysErrIntClr.
– Prepare the UDCA in system memory.
– Write the desired address for the UDCA to USBUDCAH.
– Enable the desired endpoints for DMA operation using USBEpDMAEn.
– Set EOT, DDR, and ERR bits in USBDMAIntEn.
9. Install USB interrupt handler in the NVIC by writing its address to the appropriate
vector table location and enabling the USB interrupt in the NVIC.
10. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address
command. A bus reset will also cause this to happen.
11. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status
command.
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All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a
packet without an error. All non-isochronous IN endpoints generate an interrupt when a
packet is successfully transmitted, or when a NAK handshake is sent on the bus and the
interrupt on NAK feature is enabled.
For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in
USBDevIntSt) occurs.
Software can now start reading the data from the USBRxData register (Table 215). When
the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is set in
the USBDevSt register. Software now issues a Clear Buffer (refer to Table 250) command.
The endpoint is now ready to accept the next packet. For OUT isochronous endpoints, the
next packet will be received irrespective of whether the buffer has been cleared. Any data
not read from the buffer before the end of the frame is lost. See Section 11.16 “Double
buffered endpoint operation” for more details.
If the software clears RD_EN before the entire packet is read, reading is terminated, and
the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the
data will be read from the beginning.
When the number of bytes programmed in USBTxPLen have been written to USBTxData,
the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt register.
Software issues a Validate Buffer (Section 11.12.14 “Validate Buffer (Command: 0xFA,
Data: none)”) command. The endpoint is now ready to send the packet. For IN
isochronous endpoints, the data in the buffer will be sent only if the buffer is validated
before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in the
next frame. If the software clears WR_EN before the entire packet is written, writing will
start again from the beginning the next time WR_EN is set for this endpoint.
Both RD_EN and WR_EN can be high at the same time for the same logical endpoint.
Interleaved read and write operation is possible.
The following sections discuss DMA mode operation. Background information is given in
sections Section 11.15.2 “USB device communication area” and Section 11.15.3
“Triggering the DMA engine”. The fields of the DMA Descriptor are described in
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Section 11.15.4 “The DMA descriptor”. The last three sections describe DMA operation:
Section 11.15.5 “Non-isochronous endpoint operation”, Section 11.15.6 “Isochronous
endpoint operation”, and Section 11.15.7 “Auto Length Transfer Extraction (ATLE) mode
operation”.
1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers
to these simply as transfers. Within this section they are referred to as USB transfers
to distinguish them from DMA transfers. A USB transfer is composed of transactions.
Each transaction is composed of packets.
2. DMA transfers – the transfer of data between an endpoint buffer and system memory
(RAM).
3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet of
data between an endpoint buffer and system memory (RAM). A DMA transfer is
composed of one or more packet transfers.
The start address of the UDCA is stored in the USBUDCAH register. The UDCA can
reside at any 128-byte boundary of RAM that is accessible to both the CPU and DMA
controller.
Figure 30 illustrates the UDCA and its relationship to the UDCA Head (USBUDCAH)
register and DMA Descriptors.
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UDCA NULL
0
NULL
NULL
1 Next_DD_pointer Next_DD_pointer Next_DD_pointer
2
DDP-EP2
DD-EP2-a DD-EP2-b DD-EP2-c
NULL
UDCA HEAD
REGISTER NULL
Next_DD_pointer Next_DD_pointer
16
DDP-EP16
DD-EP16-a DD-EP16-b
31
DDP-EP31
A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in
USBEpDMASt, the corresponding bit in USBDMARSt is set, and a valid DD is found for
the endpoint.
All endpoints share a single DMA channel to minimize hardware overhead. If more than
one DMA request is active in USBDMARSt, the endpoint with the lowest physical endpoint
number is processed first.
In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT
endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command
(Section 11.12.3).
DDs are placed in RAM. These descriptors can be located anywhere in on-chip RAM at
word-aligned addresses.
DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints
are five words long.
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11.15.4.1 Next_DD_pointer
Pointer to the memory location from where the next DMA descriptor will be fetched.
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11.15.4.2 DMA_mode
Specifies the DMA mode of operation. Two modes have been defined: Normal and
Automatic Transfer Length Extraction (ATLE) mode. In normal mode, software initializes
the DMA_buffer_length for OUT endpoints. In ATLE mode, the DMA_buffer_length is
extracted from the incoming data. See Section 11.15.7 “Auto Length Transfer Extraction
(ATLE) mode operation” on page 263 for more details.
11.15.4.3 Next_DD_valid
This bit indicates whether the software has prepared the next DMA descriptor. If set, the
DMA engine fetches the new descriptor when it is finished with the current one.
11.15.4.4 Isochronous_endpoint
When set, this bit indicates that the descriptor belongs to an isochronous endpoint. Hence
5 words have to be read when fetching it.
11.15.4.5 Max_packet_size
The maximum packet size of the endpoint. This parameter is used while transferring the
data for IN endpoints from the memory. It is used for OUT endpoints to detect the short
packet. This is applicable to non-isochronous endpoints only. This field should be set to
the same MPS value that is assigned for the endpoint using the USBMaxPSize register.
11.15.4.6 DMA_buffer_length
This indicates the depth of the DMA buffer allocated for transferring the data. The DMA
engine will stop using this descriptor when this limit is reached and will look for the next
descriptor.
In Normal mode operation, software sets this value for both IN and OUT endpoints. In
ATLE mode operation, software sets this value for IN endpoints only. For OUT endpoints,
hardware sets this value using the extracted length of the data stream.
11.15.4.7 DMA_buffer_start_addr
The address where the data is read from or written to. This field is updated each time the
DMA engine finishes transferring a packet.
11.15.4.8 DD_retired
This bit is set by hardware when the DMA engine finishes the current descriptor. This
happens when the end of the buffer is reached, a short packet is transferred
(non-isochronous endpoints), or an error condition is detected.
11.15.4.9 DD_status
The status of the DMA transfer is encoded in this field. The following codes are defined:
• DataUnderrun - Before reaching the end of the DMA buffer, the USB transfer is
terminated because a short packet is received. The DD_retired bit is also set.
• DataOverrun - The end of the DMA buffer is reached in the middle of a packet
transfer. This is an error situation. The DD_retired bit is set. The present DMA count
field is equal to the value of DMA_buffer_length. The packet must be re-transmitted
from the endpoint buffer in another DMA transfer. The corresponding
EPxx_DMA_ENABLE bit in USBEpDMASt is cleared.
• SystemError - The DMA transfer being serviced is terminated because of an error on
the AHB bus. The DD_retired bit is not set in this case. The corresponding
EPxx_DMA_ENABLE in USBEpDMASt is cleared. Since a system error can happen
while updating the DD, the DD fields in RAM may be unreliable.
11.15.4.10 Packet_valid
This bit is used for isochronous endpoints. It indicates whether the last packet transferred
to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was
received without errors. See Section 11.15.6 “Isochronous endpoint operation” on page
261 for isochronous endpoint operation.
11.15.4.11 LS_byte_extracted
Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of
the transfer length has been extracted. The extracted size is reflected in the
DMA_buffer_length field, bits 23:16.
11.15.4.12 MS_byte_extracted
Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of
the transfer size has been extracted. The size extracted is reflected in the
DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted and
MS_byte_extracted bits are set.
11.15.4.13 Present_DMA_count
The number of bytes transferred by the DMA engine. The DMA engine updates this field
after completing each packet transfer.
11.15.4.14 Message_length_position
Used in ATLE mode. This field gives the offset of the message length position embedded
in the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicates
that the message length starts from the first byte of the first packet.
11.15.4.15 Isochronous_packetsize_memory_address
The memory buffer address where the packet size information along with the frame
number has to be transferred or fetched. See Figure 31. This is applicable to isochronous
endpoints only.
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DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints).
If a new descriptor has to be read, the DMA engine will calculate the location of the DDP
for this endpoint and will fetch the start address of the DD from this location. A DD start
address at location zero is considered invalid. In this case the NDDR interrupt is raised.
All other word-aligned addresses are considered valid.
When the DD is fetched, the DD status word (word 3) is read first and the status of the
DD_retired bit is checked. If not set, DDP points to a valid DD. If DD_retired is set, the
DMA engine will read the control word (word 1) of the DD.
If Next_DD_valid bit is set, the DMA engine will fetch the Next_DD_pointer field (word 0)
of the DD and load it to the DDP. The new DDP is written to the UDCA area.
The full DD (4 words) will then be fetched from the address in the DDP. The DD will give
the details of the DMA transfer to be done. The DMA engine will load its hardware
resources with the information fetched from the DD (start address, DMA count etc.).
If Next_DD_valid is not set and DD_retired bit is set, the DMA engine raises the NDDR
interrupt for this endpoint and clears the corresponding EPxx_DMA_ENABLE bit.
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The DMA_PROCEED flag is cleared after the required number of bytes specified in the
DMA_buffer_length field is transferred. It is also cleared when the software writes into the
USBEpDMADis register. The ability to clear the DMA_PROCEED flag allows software to
to force the DD to be re-fetched for the next packet transfer. Writing all zeros into the
USBEpDMADis register clears the DMA_PROCEED flag without disabling DMA operation
for any endpoint.
11.15.5.6 No_Packet DD
For an IN transfer, if the system does not have any data to send for a while, it can respond
to an NDDR interrupt by programming a No_Packet DD. This is done by setting both the
Max_packet_size and DMA_buffer_length fields in the DD to 0. On processing a
No_Packet DD, the DMA engine clears the DMA request bit in USBDMARSt
corresponding to the endpoint without transferring a packet. The DD is retired with a
status code of NormalCompletion. This can be repeated as often as necessary. The
device will respond to IN token packets on the USB bus with a NAK until a DD with a data
packet is programmed and the DMA transfers the packet into the endpoint buffer.
A DMA request will be placed for DMA-enabled isochronous endpoints on every FRAME
interrupt. On processing the request, the DMA engine will fetch the descriptor and if
Isochronous_endpoint is set, will fetch the Isochronous_packetsize_memory_address
from the fifth word of the DD.
The isochronous packet size is stored in memory as shown in Figure 31. Each word in the
packet size memory shown is divided into fields: Frame_number (bits 31 to 17),
Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet
size memory for a given DD should be DMA_buffer_length words in size – one word for
each packet to transfer.
OUT endpoints
At the completion of each frame, the packet size is written to the address location in
Isochronous_packet_size_memory_address, and
Isochronous_packet_size_memory_address is incremented by 4.
IN endpoints
Only the Packet_length field of the isochronous packet size word is used. For each frame,
an isochronous data packet of size specified by this field is transferred from the USB
device to the host, and Isochronous_packet_size_memory_address is incremented by 4
at the end of the packet transfer. If Packet_length is zero, an empty packet will be sent by
the USB device.
The Packet_valid bit (bit 16) of all the words in the packet length memory is set to 1.
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Next_DD_Pointer
W0
NULL
W1
0x000A 0x0 1 0 0
DMA_buffer_start_addr
W2
0x80000000
Present_DMA_Count ATLE settings Packet_Valid DD_Status DD_Retired
W3
0x0 NA NA 0x0 0
Isocronous_packetsize_memory_address
W4
0x60000000
after 4 packets
W0 0x0
W1 0x000A0010
FULL
W2 0x80000035
W3 0x4 - - 0x1 0
frame_ number Packet_Valid Packet_Length
EMPTY
W4 0x60000010 31 16 15 0
21 1 10
22 1 15
23 1 8
24 1 20
data memory
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64 bytes
32 bytes
32 bytes
100 bytes
100 bytes
64 bytes DMA_buffer_start_addr
of DD2
4 bytes
Figure 32 shows a typical OUT USB transfer in ATLE mode, where the host concatenates
two USB transfers of 160 bytes and 100 bytes, respectively. Given a MaxPacketSize of
64, the device hardware interprets this USB transfer as four packets of 64 bytes and a
short packet of 4 bytes. The third and fourth packets are concatenated. Note that in
Normal mode, the USB transfer would be interpreted as packets of 64, 64, 32, and 64 and
36 bytes.
It is now the responsibility of the DMA engine to separate these two USB transfers and put
them in the memory locations in the DMA_buffer_start_addr field of DMA Descriptor 1
(DD1) and DMA Descriptor 2 (DD2).
Hardware reads the two-byte-wide DMA_buffer_length at the offset (from the start of the
USB transfer) specified by Message_length_position from the incoming data packets and
writes it in the DMA_buffer_length field of the DD. To ensure that both bytes of the
DMA_buffer_length are extracted in the event they are split between two packets, the
flags LS_byte_extracted and MS_byte_extracted are set by hardware after the respective
byte is extracted. After the extraction of the MS byte, the DMA transfer continues as in the
normal mode.
If DD1 is retired during the transfer of a concatenated packet (such as the third packet in
Figure 32), and DD2 is not programmed (Next_DD_valid field of DD1 is 0), then DD1 is
retired with DD_status set to the DataOverrun status code. This is treated as an error
condition and the corresponding EPxx_DMA_ENABLE bit of USBEpDMASt is cleared by
hardware.
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In ATLE mode, the last buffer length to be transferred always ends with a short or empty
packet indicating the end of the USB transfer. If the concatenated transfer lengths are
such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host
will send an empty packet to mark the end of the USB transfer.
For IN USB transfers from the device to the host, DMA_buffer_length is set by the device
software as in normal mode.
In ATLE mode, the device concatenates data from multiple DDs to form a single USB
transfer. If a DD is retired in the middle of a packet (packet size is less than
MaxPacketSize), the next DD referenced by Next_DD_pointer is fetched, and the
remaining bytes to form a packet of MaxPacketSize are transferred from the next DD’s
buffer.
If the next DD is not programmed (i.e. Next_DD_valid field in DD is 0), and the DMA buffer
length for the current DD has completed before the MaxPacketSize packet boundary, then
the available bytes from current DD are sent as a short packet on USB, which marks the
end of the USB transfer for the host.
If the last buffer length completes on a MaxPacketSize packet boundary, the device
software must program the next DD with DMA_buffer_length field 0, so that an empty
packet is sent by the device to mark the end of the USB transfer for the host.
For IN endpoints, descriptors are set in the same way as in normal mode operation.
Since a single packet can be split between two DDs, software should always keep two
DDs ready, except for the last DMA transfer which ends with a short or empty packet.
If the LS_byte_extracted or MS_byte_extracted bit in the status field is not set, the
hardware will extract the transfer length from the data stream and program
DMA_buffer_length. Once the extraction is complete both the LS_byte_extracted and
MS_byte_extracted bits will be set.
IN endpoints
The DMA transfer proceeds as in normal mode and continues until the number of bytes
transferred equals the DMA_buffer_length.
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OUT endpoints
If the linked DD is not valid and the packet is partially transferred to memory, the DD ends
with DataOverrun status code set, and the DMA will be disabled for this endpoint.
Otherwise DD_status will be updated with the NormalCompletion status code.
IN endpoints
If the linked DD is not valid and the packet is partially transferred to USB, the DD ends
with a status code of NormalCompletion in the DD_status field. This situation corresponds
to the end of the USB transfer, and the packet will be sent as a short packet. Also, when
the linked DD is valid and buffer length is 0, an empty packet will be sent to indicate the
end of the USB transfer.
When a double-buffered endpoint is realized, enough space for both endpoint buffers is
automatically allocated in the EP_RAM. See Section 11.10.4.1.
For the following discussion, the endpoint buffer currently accessible to the CPU or DMA
engine for reading or writing is said to be the active buffer.
The following example illustrates how double buffering works for a Bulk OUT endpoint in
Slave mode:
Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty, and that the active buffer is
B_1.
1. The host sends a data packet to the endpoint. The device hardware puts the packet
into B_1, and generates an endpoint interrupt.
2. Software clears the endpoint interrupt and begins reading the packet data from B_1.
While B_1 is still being read, the host sends a second packet, which device hardware
places in B_2, and generates an endpoint interrupt.
3. Software is still reading from B_1 when the host attempts to send a third packet. Since
both B_1 and B_2 are full, the device hardware responds with a NAK.
4. Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer
command to free B_1 to receive another packet. B_2 becomes the active buffer.
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5. Software sends the SIE Select Endpoint command to read the Select Endpoint
Register and test the FE bit. Software finds that the active buffer (B_2) has data
(FE=1). Software clears the endpoint interrupt and begins reading the contents of
B_2.
6. The host re-sends the third packet which device hardware places in B_1. An endpoint
interrupt is generated.
7. Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer
command to free B_2 to receive another packet. B_1 becomes the active buffer.
Software waits for the next endpoint interrupt to occur (it already has been generated
back in step 6).
8. Software responds to the endpoint interrupt by clearing it and begins reading the third
packet from B_1.
9. Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer
command to free B_1 to receive another packet. B_2 becomes the active buffer.
10. Software tests the FE bit and finds that the active buffer (B_2) is empty (FE=0).
11. Both B_1 and B_2 are empty. Software waits for the next endpoint interrupt to occur.
The active buffer is now B_2. The next data packet sent by the host will be placed in
B_2.
The following example illustrates how double buffering works for a Bulk IN endpoint in
Slave mode:
Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty and that the active buffer is
B_1. The interrupt on NAK feature is enabled.
1. The host requests a data packet by sending an IN token packet. The device responds
with a NAK and generates an endpoint interrupt.
2. Software clears the endpoint interrupt. The device has three packets to send.
Software fills B_1 with the first packet and sends a SIE Validate Buffer command. The
active buffer is switched to B_2.
3. Software sends the SIE Select Endpoint command to read the Select Endpoint
Register and test the FE bit. It finds that B_2 is empty (FE=0) and fills B_2 with the
second packet. Software sends a SIE Validate Buffer command, and the active buffer
is switched to B_1.
4. Software waits for the endpoint interrupt to occur.
5. The device successfully sends the packet in B_1 and clears the buffer. An endpoint
interrupt occurs.
6. Software clears the endpoint interrupt. Software fills B_1 with the third packet and
validates it using the SIE Validate Buffer command. The active buffer is switched to
B_2.
7. The device successfully sends the second packet from B_2 and generates an
endpoint interrupt.
8. Software has no more packets to send, so it simply clears the interrupt.
9. The device successfully sends the third packet from B_1 and generates an endpoint
interrupt.
10. Software has no more packets to send, so it simply clears the interrupt.
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11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by
software will go into B_2.
In DMA mode, switching of the active buffer is handled automatically in hardware. For
Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double
buffering can be accomplished by manually starting a packet transfer using the
USBDMARSet register.
Double buffering allows the software to make full use of the frame interval writing or
reading a packet to or from the active buffer, while the packet in the other buffer is being
sent or received on the bus.
For an OUT isochronous endpoint, any data not read from the active buffer before the end
of the frame is lost when it switches.
For an IN isochronous endpoint, if the active buffer is not validated before the end of the
frame, an empty packet is sent on the bus when the active buffer is switched, and its
contents will be overwritten when it becomes active again.
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12.3 Introduction
This section describes the host portion of the USB 2.0 OTG dual role core which
integrates the host controller (OHCI compliant), device controller, and I2C interface. The
I2C interface controls the external OTG ATX.
The USB is a 4 wire bus that supports communication between a host and a number (127
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.
Table 252. USB (OHCI) related acronyms and abbreviations used in this chapter
Acronym/abbreviation Description
AHB Advanced High-Performance Bus
ATX Analog Transceiver
DMA Direct Memory Access
FS Full Speed
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Table 252. USB (OHCI) related acronyms and abbreviations used in this chapter
Acronym/abbreviation Description
LS Low Speed
OHCI Open Host Controller Interface
USB Universal Serial Bus
12.3.1 Features
• OHCI compliant.
• OpenHCI specifies the operation and interface of the USB Host Controller and SW
Driver
– USBOperational: Process Lists and generate SOF Tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wake-up activity.
– USBResume: Forces resume signaling on the bus.
• The Host Controller has four USB states visible to the SW Driver.
• HCCA register points to Interrupt and Isochronous Descriptors List.
• ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List.
12.3.2 Architecture
The architecture of the USB host controller is shown below in Figure 33.
register
interface
(AHB slave) REGISTER
INTERFACE
ATX
HOST CONTROL USB
AHB bus
12.4 Interfaces
The USB interface is controlled by the OTG controller. It has one USB port.
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The USB device/host/OTG controller is disabled after RESET and must be enabled by
writing a 1 to the PCUSB bit in the PCONP register, see Table 46.
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[1] The R/W column in Table 254 lists the accessibility of the register:
a) Registers marked ‘R’ for access will return their current value when read.
b) Registers marked ‘R/W’ allow both read and write.
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13.3 Introduction
This chapter describes the OTG and I2C portions of the USB 2.0 OTG dual role device
controller which integrates the (OHCI) host controller, device controller, and I2C. The I2C
interface that is part of the USB block is intended to control an external OTG transceiver,
and is not the same as the I2C peripherals described in Section 19.1.
USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals. The specification and more information on USB OTG can
be found on the USB Implementers Forum web site.
13.4 Features
• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
• Hardware support for Host Negotiation Protocol (HNP).
• Includes a programmable timer required for HNP and SRP.
• Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
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13.5 Architecture
The architecture of the USB OTG controller is shown below in the block diagram.
The host, device, OTG, and I2C controllers can be programmed through the register
interface. The OTG controller enables dynamic switching between host and device roles
through the HNP protocol. One port may be connected to an external OTG transceiver to
support an OTG connection. The communication between the register interface and an
external OTG transceiver is handled through an I2C interface and through the external
OTG transceiver interrupt signal.
For USB connections that use the device or host controller only (not OTG), the ports use
an embedded USB Analog Transceiver (ATX).
OTG
TRANSCEIVER
register I2C
interface CONTROLLER
(AHB slave) REGISTER
USB
INTERFACE
port
OTG
CONTROLLER USB
ATX
ATX
CONTROL
AHB bus
EP_RAM
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The following figures show different ways to realize connections to an USB device. The
example described here uses an ISP1302 (ST-Ericsson) for the external OTG transceiver
and the USB Host power switch LM3526-L (National Semiconductors).
VDD
USB_D+
USB_D−
USB_UP_LED
VDD
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VDD
USB_UP_LED
VSS
USB_D+ 33 Ω D+
USB_D− 33 Ω D−
USB-A
LPC176x 15 kΩ 15 kΩ connector
VDD
USB_PWRD VBUS
USB_OVRCR
graphicID
VDD
USB_UP_LED
VDD
USB_CONNECT
LPC176x
VSS
USB_D+ 33 Ω D+
33 Ω
USB-B
USB_D− D−
connector
VBUS VBUS
graphicID
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The Device and Host registers are explained in Table 254 and Table 188 in the USB
Device Controller and USB Host (OHCI) Controller chapters. All registers are 32 bits wide
and aligned to word address boundaries.
The interrupt lines are ORed together to a single channel of the vectored interrupt
controller.
Table 257. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description
Bit Symbol Description Reset
Value
0 USB_INT_REQ_LP Low priority interrupt line status. This bit is read-only. 0
1 USB_INT_REQ_HP High priority interrupt line status. This bit is read-only. 0
2 USB_INT_REQ_DMA DMA interrupt line status. This bit is read-only. 0
3 USB_HOST_INT USB host interrupt line status. This bit is read-only. 0
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Table 257. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description
Bit Symbol Description Reset
Value
4 USB_ATX_INT External ATX interrupt line status. This bit is read-only. 0
5 USB_OTG_INT OTG interrupt line status. This bit is read-only. 0
6 USB_I2C_INT I2C module interrupt line status. This bit is read-only. 0
7 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
8 USB_NEED_CLK USB need clock indicator. This bit is read-only. 1
30:9 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
31 EN_USB_INTS Enable all USB interrupts. When this bit is cleared, the 1
NVIC does not see the ORed output of the USB interrupt
lines.
Table 258. OTG Interrupt Status register (OTGIntSt - address 0x5000 C100) bit description
Bit Symbol Description Reset
Value
0 TMR Timer time-out. 0
1 REMOVE_PU Remove pull-up. 0
This bit is set by hardware to indicate that software
needs to disable the D+ pull-up resistor.
2 HNP_FAILURE HNP failed. 0
This bit is set by hardware to indicate that the HNP
switching has failed.
3 HNP_SUCCESS HNP succeeded. 0
This bit is set by hardware to indicate that the HNP
switching has succeeded.
31:4 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.
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Time critical events during the switching sequence are controlled by the OTG timer. The
timer can operate in two modes:
Table 259. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description
Bit Symbol Description Reset
Value
1:0 PORT_FUNC Controls port function. Bit 0 is set or cleared by hardware -
when B_HNP_TRACK or A_HNP_TRACK is set and
HNP succeeds. See Section 13.9. Bit 1 is reserved.
3:2 TMR_SCALE Timer scale selection. This field determines the duration 0x0
of each timer count.
00: 10 μs (100 KHz)
01: 100 μs (10 KHz)
10: 1000 μs (1 KHz)
11: Reserved
4 TMR_MODE Timer mode selection. 0
0: monoshot
1: free running
5 TMR_EN Timer enable. When set, TMR_CNT increments. When 0
cleared, TMR_CNT is reset to 0.
6 TMR_RST Timer reset. Writing one to this bit resets TMR_CNT to 0. 0
This provides a single bit control for the software to
restart the timer when the timer is enabled.
7 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
8 B_HNP_TRACK Enable HNP tracking for B-device (peripheral), see 0
Section 13.9. Hardware clears this bit when
HNP_SUCCESS or HNP_FAILURE is set.
9 A_HNP_TRACK Enable HNP tracking for A-device (host), see 0
Section 13.9. Hardware clears this bit when
HNP_SUCCESS or HNP_FAILURE is set.
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Table 259. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description
Bit Symbol Description Reset
Value
10 PU_REMOVED When the B-device changes its role from peripheral to 0
host, software sets this bit when it removes the D+
pull-up, see Section 13.9. Hardware clears this bit when
HNP_SUCCESS or HNP_FAILURE is set.
15:11 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
31:16 TMR_CNT Current timer count value. 0x0
Table 261. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit
description
Bit Symbol Value Description Reset
Value
0 HOST_CLK_EN Host clock enable 0
0 Disable the Host clock.
1 Enable the Host clock.
1 DEV_CLK_EN Device clock enable 0
0 Disable the Device clock.
1 Enable the Device clock.
2 I2C_CLK_EN I2C clock enable 0
0 Disable the I2C clock.
1 Enable the I2C clock.
3 OTG_CLK_EN OTG clock enable 0
0 Disable the OTG clock.
1 Enable the OTG clock.
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Table 261. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit
description
Bit Symbol Value Description Reset
Value
4 AHB_CLK_EN AHB master clock enable 0
0 Disable the AHB clock.
1 Enable the AHB clock.
31:5 - NA Reserved, user software should not write ones NA
to reserved bits. The value read from a
reserved bit is not defined.
Table 262. OTG clock status register (OTGClkSt - address 0x5000 CFF8) bit description
Bit Symbol Value Description Reset
Value
0 HOST_CLK_ON Host clock status. 0
0 Host clock is not available.
1 Host clock is available.
1 DEV_CLK_ON Device clock status. 0
0 Device clock is not available.
1 Device clock is available.
2 I2C_CLK_ON I2C clock status. 0
0 I2C clock is not available.
1 I2C clock is available.
3 OTG_CLK_ON OTG clock status. 0
0 OTG clock is not available.
1 OTG clock is available.
4 AHB_CLK_ON AHB master clock status. 0
0 AHB clock is not available.
1 AHB clock is available.
31:5 - NA Reserved, user software should not write ones NA
to reserved bits. The value read from a
reserved bit is not defined.
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Table 263. I2C Receive register (I2C_RX - address 0x5000 C300) bit description
Bit Symbol Description Reset
Value
7:0 RX Data Receive data. -
The Tx FIFO is flushed by a hard reset, soft reset (I2C_CTL bit 7) or if an arbitration failure
occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored.
I2C_TX must be written for both write and read operations to transfer each byte. Bits [7:0]
are ignored for master-receive operations. The master-receiver must write a dummy byte
to the TX FIFO for each byte it expects to receive in the RX FIFO. When the STOP bit is
set or the START bit is set to cause a RESTART condition on a byte written to the TX
FIFO (master-receiver), then the byte read from the slave is not acknowledged. That is,
the last byte of a master-receive operation is not acknowledged.
Table 264. I2C Transmit register (I2C_TX - address 0x5000 C300) bit description
Bit Symbol Description Reset
Value
7:0 TX Data Transmit data. -
8 START When 1, issue a START condition before transmitting this byte. -
9 STOP When 1, issue a STOP condition after transmitting this byte. -
31:10 - Reserved. User software should not write ones to reserved bits. The -
value read from a reserved bit is not defined.
Table 265. I2C status register (I2C_STS - address 0x5000 C304) bit description
Bit Symbol Value Description Reset
Value
0 TDI Transaction Done Interrupt. This flag is set if a transaction 0
completes successfully. It is cleared by writing a one to bit 0 of
the status register. It is unaffected by slave transactions.
0 Transaction has not completed.
1 Transaction completed.
1 AFI Arbitration Failure Interrupt. When transmitting, if the SDA is low 0
when SDAOUT is high, then this I2C has lost the arbitration to
another device on the bus. The Arbitration Failure bit is set when
this happens. It is cleared by writing a one to bit 1 of the status
register.
0 No arbitration failure on last transmission.
1 Arbitration failure occurred on last transmission.
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Table 265. I2C status register (I2C_STS - address 0x5000 C304) bit description
Bit Symbol Value Description Reset
Value
2 NAI No Acknowledge Interrupt. After every byte of data is sent, the 0
transmitter expects an acknowledge from the receiver. This bit is
set if the acknowledge is not received. It is cleared when a byte
is written to the master TX FIFO.
0 Last transmission received an acknowledge.
1 Last transmission did not receive an acknowledge.
3 DRMI Master Data Request Interrupt. Once a transmission is started, 0
the transmitter must have data to transmit as long as it isn’t
followed by a stop condition or it will hold SCL low until more
data is available. The Master Data Request bit is set when the
master transmitter is data-starved. If the master TX FIFO is
empty and the last byte did not have a STOP condition flag, then
SCL is held low until the CPU writes another byte to transmit.
This bit is cleared when a byte is written to the master TX FIFO.
0 Master transmitter does not need data.
1 Master transmitter needs data.
4 DRSI Slave Data Request Interrupt. Once a transmission is started, 0
the transmitter must have data to transmit as long as it isn’t
followed by a STOP condition or it will hold SCL low until more
data is available. The Slave Data Request bit is set when the
slave transmitter is data-starved. If the slave TX FIFO is empty
and the last byte transmitted was acknowledged, then SCL is
held low until the CPU writes another byte to transmit. This bit is
cleared when a byte is written to the slave Tx FIFO.
0 Slave transmitter does not need data.
1 Slave transmitter needs data.
5 Active Indicates whether the bus is busy. This bit is set when a START 0
condition has been seen. It is cleared when a STOP condition is
seen..
6 SCL The current value of the SCL signal. -
7 SDA The current value of the SDA signal. -
8 RFF Receive FIFO Full (RFF). This bit is set when the RX FIFO is full 0
and cannot accept any more data. It is cleared when the RX
FIFO is not full. If a byte arrives when the Receive FIFO is full,
the SCL is held low until the CPU reads the RX FIFO and makes
room for it.
0 RX FIFO is not full
1 RX FIFO is full
9 RFE Receive FIFO Empty. RFE is set when the RX FIFO is empty 1
and is cleared when the RX FIFO contains valid data.
0 RX FIFO contains data.
1 RX FIFO is empty
10 TFF Transmit FIFO Full. TFF is set when the TX FIFO is full and is 0
cleared when the TX FIFO is not full.
0 TX FIFO is not full.
1 TX FIFO is full
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Table 265. I2C status register (I2C_STS - address 0x5000 C304) bit description
Bit Symbol Value Description Reset
Value
11 TFE Transmit FIFO Empty. TFE is set when the TX FIFO is empty 1
and is cleared when the TX FIFO contains valid data.
0 TX FIFO contains valid data.
1 TX FIFO is empty
31:12 - NA Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
Table 266. I2C Control register (I2C_CTL - address 0x5000 C308) bit description
Bit Symbol Value Description Reset
Value
0 TDIE Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C 0
issued a STOP condition.
0 Disable the TDI interrupt.
1 Enable the TDI interrupt.
1 AFIE Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is 0
asserted during transmission when trying to set SDA high, but the bus is driven low by
another device.
0 Disable the AFI.
1 Enable the AFI.
2 NAIE Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling 0
that transmitted byte was not acknowledged.
0 Disable the NAI.
1 Enable the NAI.
3 DRMIE Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which 0
signals that the master transmitter has run out of data, has not issued a STOP, and is
holding the SCL line low.
0 Disable the DRMI interrupt.
1 Enable the DRMI interrupt.
4 DRSIE Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which 0
signals that the slave transmitter has run out of data and the last byte was acknowledged,
so the SCL line is being held low.
0 Disable the DRSI interrupt.
1 Enable the DRSI interrupt.
5 REFIE Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to 0
indicate that the receive FIFO cannot accept any more data.
0 Disable the RFFI.
1 Enable the RFFI.
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Table 266. I2C Control register (I2C_CTL - address 0x5000 C308) bit description
Bit Symbol Value Description Reset
Value
6 RFDAIE Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that 0
data is available in the receive FIFO (i.e. not empty).
0 Disable the DAI.
1 Enable the DAI.
7 TFFIE Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt 0
to indicate that the more data can be written to the transmit FIFO. Note that this is not full.
It is intended help the CPU to write to the I2C block only when there is room in the FIFO
and do this without polling the status register.
0 Disable the TFFI.
1 Enable the TFFI.
8 SRST Soft reset. This is only needed in unusual circumstances. If a device issues a start 0
condition without issuing a stop condition. A system timer may be used to reset the I2C if
the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx
FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset
to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are
NOT modified by a soft reset.
0 See the text.
1 Reset the I2C to idle state. Self clearing.
31:9 - NA Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 267. I2C_CLKHI register (I2C_CLKHI - address 0x5000 C30C) bit description
Bit Symbol Description Reset
Value
7:0 CDHI Clock divisor high. This value is the number of 48 MHz 0xB9
clocks the serial clock (SCL) will be high.
Table 268. I2C_CLKLO register (I2C_CLKLO - address 0x5000 C310) bit description
Bit Symbol Description Reset
Value
7:0 CDLO Clock divisor low. This value is the number of 48 MHz 0xB9
clocks the serial clock (SCL) will be low.
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I2C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL,
to the USB_I2C_INT bit.
For more details on the interrupts created by device controller, see the USB device
chapter. For interrupts created by the host controllers, see the OHCI specification.
The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB
related interrupts to the NVIC controller (see Figure 38).
Remark: During the HNP switching between host and device with the OTG stack active,
an action may raise several levels of interrupts. It is advised to let the OTG stack initiate
any actions based on interrupts and ignore device and host level interrupts. This means
that during HNP switching, the OTG stack provides the communication to the host and
device controllers.
USBIntSt
USB_INT_REQ_HP
USB DEVICE USB_INT_REQ_LP
INTERRUPTS to NVIC
USB_INT_REQ_DMA
USB_HOST_INT
USB_OTG_INT
USB HOST
INTERRUPTS USB_I2C_INT
OTGIntSt
TMR
REMOVE_PU
HNP_SUCCESS
HNP_FAILURE
USB_NEED_CLOCK
When two dual-role OTG devices are connected to each other, the plug inserted into the
mini-AB receptacle determines the default role of each device. The device with the mini-A
plug inserted becomes the default Host (A-device), and the device with the mini-B plug
inserted becomes the default Peripheral (B-device).
Once connected, the default Host (A-device) and the default Peripheral (B-device) can
switch Host and Peripheral roles using HNP.
The context of the OTG controller operation is shown in Figure 39. Each controller (Host,
Device, or OTG) communicates with its software stack through a set of status and control
registers and interrupts. In addition, the OTG software stack communicates with the
external OTG transceiver through the I2C interface and the external transceiver interrupt
signal.
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The OTG software stack is responsible for implementing the HNP state machines as
described in the On-The-Go Supplement to the USB 2.0 Specification.
The OTG controller hardware provides support for some of the state transitions in the
HNP state machines as described in the following subsections.
The USB state machines, the HNP switching, and the communications between the USB
controllers are described in more detail in the following documentation:
OHCI HOST
STACK CONTROLLER
DEVICE DEVICE
STACK CONTROLLER
I2C
CONTROLLER ISP1302
The On-The-Go Supplement defines the behavior of a dual-role B-device during HNP
using a state machine diagram. The OTG software stack is responsible for implementing
all of the states in the Dual-Role B-Device State Diagram.
The OTG controller hardware provides support for the state transitions between the states
b_peripheral, b_wait_acon, and b_host in the Dual-Role B-Device state diagram. Setting
B_HNP_TRACK in the OTGStCtrl register enables hardware support for the B-device
switching from peripheral to host. The hardware actions after setting this bit are shown in
Figure 40.
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idle
B_HNP_TRACK = 0
no
B_HNP_TRACK = 1 ?
set HNP_FAILURE,
clear B_HNP_TRACK,
clear PU_REMOVED
no
bus suspended ?
no
disconnect device controller from U1 PU_REMOVED set?
set REMOVE_PU
yes
PU_REMOVED set?
reconnect port U1 to the
device controller
yes
bus reset/resume detected?
no
yes yes
connect from A-device detected? bus reset/resume detected?
no no
Fig 40. Hardware support for B-device switching from peripheral state to host state
Figure 41 shows the actions that the OTG software stack should take in response to the
hardware actions setting REMOVE_PU, HNP_SUCCESS, AND HNP_FAILURE. The
relationship of the software actions to the Dual-Role B-Device states is also shown.
B-device states are in bold font with a circle around them.
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b_peripheral
when host sends SET_FEATURE
with b_hnp_enable,
set B_HNP_TRACK
no
REMOVE_PU set?
yes
remove D+ pull-up,
set PU_REMOVED
go to go to
b_wait_acon b_peripheral
yes
HNP_FAILURE set? add D+ pull-up
no
no
HNP_SUCCESS set?
yes
go to
b_host
Fig 41. State transitions implemented in software during B-device switching from peripheral to host
Note that only the subset of B-device HNP states and state transitions supported by
hardware are shown. Software is responsible for implementing all of the HNP states.
Figure 41 may appear to imply that the interrupt bits such as REMOVE_PU should be
polled, but this is not necessary if the corresponding interrupt is enabled.
Following are code examples that show how the actions in Figure 41 are accomplished.
The examples assume that ISP1302 is being used as the external OTG transceiver.
Remove D+ pull-up
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/* Clear TDI */
OTG_I2C_STS = TDI;
Add D+ pull-up
/* Clear TDI */
OTG_I2C_STS = TDI;
The On-The-Go Supplement defines the behavior of a dual-role A-device during HNP
using a state machine diagram. The OTG software stack is responsible for implementing
all of the states in the Dual-Role A-Device State Diagram.
The OTG controller hardware provides support for the state transitions between a_host,
a_suspend, a_wait_vfall, and a_peripheral in the Dual-Role A-Device state diagram.
Setting A_HNP_TRACK in the OTGStCtrl register enables hardware support for switching
the A-device from the host state to the device state. The hardware actions after setting
this bit are shown in Figure 42.
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idle
A_HNP_TRACK = 0
no
A_HNP_TRACK = 1 ? set HNP_FAILURE,
clear A_HNP_TRACK
no no
bus suspended ? resume detected ?
yes yes
bus reset detected? resume detected?
no no
yes
clear A_HNP_TRACK
set HNP_SUCCESS
connect device to U1 by clearing
PORT_FUNC[0]
Fig 42. Hardware support for A-device switching from host state to peripheral state
Figure 43 shows the actions that the OTG software stack should take in response to the
hardware actions setting TMR, HNP_SUCCESS, and HNP_FAILURE. The relationship of
the software actions to the Dual-Role A-Device states is also shown. A-device states are
shown in bold font with a circle around them.
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a_host
when host sends SET_FEATURE
with a_hnp_enable,
set A_HNP_TRACK
set BDIS_ACON_EN
in external OTG transceiver
go to
a_suspend
no
no no
TMR set? HNP_SUCCESS set? HNP_FAILURE set?
yes yes
yes
clear BDIS_ACON_EN
stop the OTG timer stop OTG timer
bit in external OTG transceiver
discharge VBUS
go to
clear BDIS_ACON_EN
a_peripheral bit in external OTG transceiver
go to
a_wait_vfall go to
a_host
Fig 43. State transitions implemented in software during A-device switching from host to peripheral
Note that only the subset of A-device HNP states and state transitions supported by
hardware are shown. Software is responsible for implementing all of the HNP states.
Figure 43 may appear to imply that the interrupt bits such as TMR should be polled, but
this is not necessary if the corresponding interrupt is enabled.
Following are code examples that show how the actions in Figure 43 are accomplished.
The examples assume that ISP1302 is being used as the external OTG transceiver.
/* Clear TDI */
OTG_I2C_STS = TDI;
/* Clear TDI */
OTG_I2C_STS = TDI;
Discharge VBUS
/* Clear TDI */
OTG_I2C_STS = TDI;
/* Clear TDI */
OTG_I2C_STS = TDI;
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/* The following assumes that the OTG timer has previously been */
A clock switch controls each clock with the exception of ahb_slave_clk. When the enable
of the clock switch is asserted, its clock output is turned on and its CLK_ON output is
asserted. The CLK_ON signals are observable in the OTGClkSt register.
To conserve power, the clocks to the Device, Host, OTG, and I2C controllers can be
disabled when not in use by clearing the respective CLK_EN bit in the OTGClkCtrl
register. When the entire USB block is not in use, all of its clocks can be disabled by
clearing the PCUSB bit in the PCONP register.
When software wishes to access registers in one of the controllers, it should first ensure
that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the
OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set.
Once set, the controller’s clock will remain enabled until CLK_EN is cleared by software.
Accessing the register of a controller when its 48 MHz clock is not enabled will result in a
data abort exception.
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ahb_master_clk
CLOCK
SWITCH
EN AHB_CLK_ON
ahb_need_clk
AHB_CLK_EN
CLOCK dev_dma_need_clk
USB CLOCK SWITCH DEVICE
DIVIDER usbclk EN CONTROLLER dev_need_clk
DEV_CLK_ON
(48 MHz)
DEV_CLK_EN
CLOCK host_dma_need_clk
SWITCH HOST
EN CONTROLLER host_need_clk
HOST_CLK_ON
HOST_CLK_EN
CLOCK
SWITCH OTG USB_NEED_CLK
CONTROLLER
EN OTG_CLK_ON
OTG_CLK_EN
CLOCK
I2C
SWITCH
CONTROLLER
EN I2C_CLK_ON
I2C_CLK_EN
The dev_need_clk signal is asserted while the device is not in the suspend state, or if the
device is in the suspend state and activity is detected on the USB bus. The dev_need_clk
signal is de-asserted if a disconnect is detected (CON bit is cleared in the SIE Get Device
Status register – Section 11.10.6). This signal allows DEV_CLK_EN to be cleared during
normal operation when software does not need to access the Device controller registers –
the Device will continue to function normally and automatically shut off its clock when it is
suspended or disconnected.
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The host_need_clk signal is asserted while the Host controller functional state is not
UsbSuspend, or if the functional state is UsbSuspend and resume signaling or a
disconnect is detected on the USB bus. This signal allows HOST_CLK_EN to be cleared
during normal operation when software does not need to access the Host controller
registers – the Host will continue to function normally and automatically shut off its clock
when it goes into the UsbSuspend state.
Before Power-down mode can be entered when the USB activity interrupt is enabled,
USB_NEED_CLK must be de-asserted. This is accomplished by clearing all of the
CLK_EN bits in OTGClkCtrl and putting the Host controller into the UsbSuspend
functional state. If it is necessary to wait for either of the dma_need_clk signals or the
dev_need_clk to be de-asserted, the status of USB_NEED_CLK can be polled in the
USBIntSt register to determine when they have all been de-asserted.
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4. Enable the desired USB pin functions by writing to the corresponding PINSEL
registers.
5. Follow the appropriate steps in Section 11.13 “USB device controller initialization” to
initialize the device controller.
6. Follow the guidelines given in the OpenHCI specification for initializing the host
controller.
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14.2 Features
• Data sizes of 5, 6, 7, and 8 bits.
• Parity generation and checking: odd, even mark, space or none.
• One or two stop bits.
• 16 byte Receive and Transmit FIFOs.
• Built-in baud rate generator, including a fractional rate divider for great versatility.
• Supports DMA for both transmit and receive.
• Auto-baud capability
• Break generation and detection.
• Multiprocessor addressing mode.
• IrDA mode to support infrared communication.
• Support for software flow control.
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[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
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The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the UnRBR.
The UnRBR is always read-only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the UnRBR.
Table 271: UARTn Receiver Buffer Register (U0RBR - address 0x4000 C000, U2RBR - 0x4009 8000, U3RBR -
04009 C000 when DLAB = 0) bit description
Bit Symbol Description Reset Value
7:0 RBR The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx Undefined
FIFO.
31:8 - Reserved, the value read from a reserved bit is not defined. NA
The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the
UnTHR. The UnTHR is always write-only.
Table 272: UARTn Transmit Holding Register (U0THR - address 0x4000 C000, U2THR - 0x4009 8000, U3THR -
0x4009 C000 when DLAB = 0) bit description
Bit Symbol Description Reset Value
7:0 THR Writing to the UARTn Transmit Holding Register causes the data to be stored in the NA
UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and
the transmitter is available.
31:8 - Reserved, user software should not write ones to reserved bits. NA
14.4.3 UARTn Divisor Latch LSB register (U0DLL - 0x4000 C000, U2DLL -
0x4009 8000, U3DLL - 0x4009 C000 when DLAB = 1) and UARTn
Divisor Latch MSB register (U0DLM - 0x4000 C004, U2DLL -
0x4009 8004, U3DLL - 0x4009 C004 when DLAB = 1)
The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce
the baud rate clock, which must be 16× the desired baud rate. The UnDLL and UnDLM
registers together form a 16-bit divisor where UnDLL contains the lower 8 bits of the
divisor and UnDLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like
a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in
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UnLCR must be one in order to access the UARTn Divisor Latches. Details on how to
select the right value for UnDLL and UnDLM can be found later in this chapter, see
Section 14.4.12.
Table 273: UARTn Divisor Latch LSB register (U0DLL - address 0x4000 C000, U2DLL - 0x4009 8000, U3DLL -
0x4009 C000 when DLAB = 1) bit description
Bit Symbol Description Reset Value
7:0 DLLSB The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the 0x01
baud rate of the UARTn.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 274: UARTn Divisor Latch MSB register (U0DLM - address 0x4000 C004, U2DLM - 0x4009 8004, U3DLM -
0x4009 C004 when DLAB = 1) bit description
Bit Symbol Description Reset Value
7:0 DLMSB The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the 0x00
baud rate of the UARTn.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 275: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER -
0x4009 C004 when DLAB = 0) bit description
Bit Symbol Value Description Reset Value
0 RBR Interrupt Enables the Receive Data Available interrupt for UARTn. It also controls 0
Enable the Character Receive Time-out interrupt.
0 Disable the RDA interrupts.
1 Enable the RDA interrupts.
1 THRE Interrupt Enables the THRE interrupt for UARTn. The status of this can be read 0
Enable from UnLSR[5].
0 Disable the THRE interrupts.
1 Enable the THRE interrupts.
2 RX Line Status Enables the UARTn RX line status interrupts. The status of this interrupt 0
Interrupt Enable can be read from UnLSR[4:1].
0 Disable the RX line status interrupts.
1 Enable the RX line status interrupts.
7:3 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
8 ABEOIntEn Enables the end of auto-baud interrupt. 0
0 Disable end of auto-baud Interrupt.
1 Enable end of auto-baud Interrupt.
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Table 275: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER -
0x4009 C004 when DLAB = 0) bit description
Bit Symbol Value Description Reset Value
9 ABTOIntEn Enables the auto-baud time-out interrupt. 0
0 Disable auto-baud time-out Interrupt.
1 Enable auto-baud time-out Interrupt.
31:10 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
Table 276: UARTn Interrupt Identification Register (U0IIR - address 0x4000 C008, U2IIR - 0x4009 8008, U3IIR -
0x4009 C008) bit description
Bit Symbol Value Description Reset Value
0 IntStatus Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be 1
determined by evaluating UnIIR[3:1].
0 At least one interrupt is pending.
1 No interrupt is pending.
3:1 IntId Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the 0
UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below
are reserved (000,100,101,111).
011 1 - Receive Line Status (RLS).
010 2a - Receive Data Available (RDA).
110 2b - Character Time-out Indicator (CTI).
001 3 - THRE Interrupt
5:4 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
7:6 FIFO Enable Copies of UnFCR[0]. 0
8 ABEOInt End of auto-baud interrupt. True if auto-baud has finished successfully and 0
interrupt is enabled.
9 ABTOInt Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is 0
enabled.
31:10 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
Bit UnIIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in Table 277. Given the status of UnIIR[3:0], an
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The UnIIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
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The UARTn RLS interrupt (UnIIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UARTn Rx input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UARTn Rx error
condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared
upon an UnLSR read.
The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI
interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the
trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls
below the trigger level. When the RDA interrupt goes active, the CPU can read a block of
data defined by the trigger level.
The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn
Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) will
clear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2] For details see Section 14.4.8 “UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR -
0x4009 8014, U3LSR - 0x4009 C014)”
[3] For details see Section 14.4.1 “UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR -
0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0)”
[4] For details see Section 14.4.5 “UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR -
0x4009 8008, U3IIR - 0x4009 C008)” and Section 14.4.2 “UARTn Transmit Holding Register (U0THR -
0x4000 C000, U2THR - 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0)”
The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activated
when the UARTn THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UARTn THR FIFO a chance to
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fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the UnTHR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UARTn THR FIFO has held two or more characters at one time and
currently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs or
a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).
Table 278: UARTn FIFO Control Register (U0FCR - address 0x4000 C008, U2FCR - 0x4009 8008, U3FCR -
0x4007 C008) bit description
Bit Symbol Value Description Reset Value
0 FIFO Enable 0 UARTn FIFOs are disabled. Must not be used in the application. 0
1 Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access.
This bit must be set for proper UART operation. Any transition on this bit will
automatically clear the related UART FIFOs.
1 RX FIFO 0 No impact on either of UARTn FIFOs. 0
Reset 1 Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the
pointer logic. This bit is self-clearing.
2 TX FIFO 0 No impact on either of UARTn FIFOs. 0
Reset 1 Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the
pointer logic. This bit is self-clearing.
3 DMA Mode When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA 0
Select mode. See Section 14.4.6.1.
5:4 - - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
7:6 RX Trigger These two bits determine how many receiver UARTn FIFO characters must be 0
Level written before an interrupt or DMA request is activated.
00 Trigger level 0 (1 character or 0x01)
01 Trigger level 1 (4 characters or 0x04)
10 Trigger level 2 (8 characters or 0x08)
11 Trigger level 3 (14 characters or 0x0E)
31:8 - Reserved, user software should not write ones to reserved bits. NA
In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO
level becoming equal to or greater than trigger level, or if a character timeout occurs. See
the description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
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In DMA mode, the transmitter DMA request is asserted on the event of the transmitter
FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA
controller.
Table 279: UARTn Line Control Register (U0LCR - address 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR -
0x4009 C00C) bit description
Bit Symbol Value Description Reset Value
1:0 Word Length Select 00 5-bit character length 0
01 6-bit character length
10 7-bit character length
11 8-bit character length
2 Stop Bit Select 0 1 stop bit. 0
1 2 stop bits (1.5 if UnLCR[1:0]=00).
3 Parity Enable 0 Disable parity generation and checking. 0
1 Enable parity generation and checking.
5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and the attached 0
parity bit will be odd.
01 Even Parity. Number of 1s in the transmitted character and the attached
parity bit will be even.
10 Forced "1" stick parity.
11 Forced "0" stick parity.
6 Break Control 0 Disable break transmission. 0
1 Enable break transmission. Output pin UARTn TXD is forced to logic 0
when UnLCR[6] is active high.
7 Divisor Latch 0 Disable access to Divisor Latches. 0
Access Bit (DLAB) 1 Enable access to Divisor Latches.
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)
bit description
Bit Symbol Value Description Reset
Value
0 Receiver Data UnLSR0 is set when the UnRBR holds an unread character and is cleared when 0
Ready (RDR) the UARTn RBR FIFO is empty.
0 The UARTn receiver FIFO is empty.
1 The UARTn receiver FIFO is not empty.
1 Overrun Error The overrun error condition is set as soon as it occurs. An UnLSR read clears 0
(OE) UnLSR1. UnLSR1 is set when UARTn RSR has a new character assembled and
the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be
overwritten and the character in the UARTn RSR will be lost.
0 Overrun error status is inactive.
1 Overrun error status is active.
2 Parity Error (PE) When the parity bit of a received character is in the wrong state, a parity error 0
occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is
dependent on UnFCR[0].
Note: A parity error is associated with the character at the top of the UARTn RBR
FIFO.
0 Parity error status is inactive.
1 Parity error status is active.
3 Framing Error When the stop bit of a received character is a logic 0, a framing error occurs. An 0
(FE) UnLSR read clears UnLSR[3]. The time of the framing error detection is
dependent on UnFCR0. Upon detection of a framing error, the Rx will attempt to
resynchronize to the data and assume that the bad stop bit is actually an early
start bit. However, it cannot be assumed that the next received byte will be correct
even if there is no Framing Error.
Note: A framing error is associated with the character at the top of the UARTn
RBR FIFO.
0 Framing error status is inactive.
1 Framing error status is active.
4 Break Interrupt When RXDn is held in the spacing state (all zeroes) for one full character 0
(BI) transmission (start, data, parity, stop), a break interrupt occurs. Once the break
condition has been detected, the receiver goes idle until RXDn goes to marking
state (all ones). An UnLSR read clears this status bit. The time of break detection
is dependent on UnFCR[0].
Note: The break interrupt is associated with the character at the top of the UARTn
RBR FIFO.
0 Break interrupt status is inactive.
1 Break interrupt status is active.
5 Transmitter THRE is set immediately upon detection of an empty UARTn THR and is cleared 1
Holding Register on a UnTHR write.
Empty (THRE)) 0 UnTHR contains valid data.
1 UnTHR is empty.
6 Transmitter TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when 1
Empty (TEMT) either the UnTSR or the UnTHR contain valid data.
0 UnTHR and/or the UnTSR contains valid data.
1 UnTHR and the UnTSR are empty.
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Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)
bit description
Bit Symbol Value Description Reset
Value
7 Error in RX FIFO UnLSR[7] is set when a character with a Rx error such as framing error, parity 0
(RXFE) error or break interrupt, is loaded into the UnRBR. This bit is cleared when the
UnLSR register is read and there are no subsequent errors in the UARTn FIFO.
0 UnRBR contains no UARTn RX errors or UnFCR[0]=0.
1 UARTn RBR contains at least one UARTn RX error.
31:8 - Reserved, the value read from a reserved bit is not defined. NA
Table 281: UARTn Scratch Pad Register (U0SCR - address 0x4000 C01C, U2SCR - 0x4009 801C, U3SCR -
0x4009 C01C) bit description
Bit Symbol Description Reset Value
7:0 Pad A readable, writable byte. 0x00
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 282: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR -
0x4009 C020) bit description
Bit Symbol Value Description Reset value
0 Start This bit is automatically cleared after auto-baud completion. 0
0 Auto-baud stop (auto-baud is not running).
1 Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
automatically cleared after auto-baud completion.
1 Mode Auto-baud mode select bit. 0
0 Mode 0.
1 Mode 1.
2 AutoRestart 0 No restart. 0
1 Restart in case of time-out (counter restarts at next UARTn Rx falling edge) 0
7:3 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
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Table 282: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR -
0x4009 C020) bit description
Bit Symbol Value Description Reset value
8 ABEOIntClr End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will 0
clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.
9 ABTOIntClr Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will 0
clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.
31:10 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
14.4.10.1 Auto-baud
The UARTn auto-baud function can be used to measure the incoming baud-rate based on
the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit
time of the receive data stream and set the divisor latch registers UnDLM and UnDLL
accordingly.
Remark: the fractional rate divider is not connected during auto-baud operations, and
therefore should not be used when the auto-baud feature is needed.
Auto-baud is started by setting the UnACR Start bit. Auto-baud can be stopped by clearing
the UnACR Start bit. The Start bit will clear once auto-baud has finished and reading the
bit will return the status of auto-baud (pending/finished).
Two auto-baud measuring modes are available which can be selected by the UnACR
Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the
UARTn Rx pin (the falling edge of the start bit and the falling edge of the least significant
bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent
rising edge of the UARTn Rx pin (the length of the start bit).
The UnACR AutoRestart bit can be used to automatically restart baud-rate measurement
if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate
measurement will restart at the next falling edge of the UARTn Rx pin.
• The UnIIR ABTOInt interrupt will get set if the interrupt is enabled (UnIER ABToIntEn
is set and the auto-baud rate measurement counter overflows).
• The UnIIR ABEOInt interrupt will get set if the interrupt is enabled (UnIER ABEOIntEn
is set and the auto-baud has completed successfully).
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(1)
2 × P CLK PCLK
ratemin = ------------------------- ≤ UART n baudrate ≤ ------------------------------------------------------------------------------------------------------------ = ratemax
16 × 2 15 16 × ( 2 + databits + paritybits + stopbits )
1. On UnACR Start bit setting, the baud rate measurement counter is reset and the
UARTn UnRSR is reset. The UnRSR baud rate is switch to the highest rate.
2. A falling edge on UARTn Rx pin triggers the beginning of the start bit. The rate
measuring counter will start counting pclk cycles optionally pre-scaled by the
fractional baud-rate generator.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
the frequency of the (fractional baud-rate pre-scaled) UARTn input clock,
guaranteeing the start bit is stored in the UnRSR.
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
counter will continue incrementing with the pre-scaled UARTn input clock (pclk).
5. If Mode = 0 then the rate counter will stop on next falling edge of the UARTn Rx pin. If
Mode = 1 then the rate counter will stop on the next rising edge of the UARTn Rx pin.
6. The rate counter is loaded into UnDLM/UnDLL and the baud-rate will be switched to
normal operation. After setting the UnDLM/UnDLL the end of auto-baud interrupt
UnIIR ABEOInt will be set, if enabled. The UnRSR will now continue receiving the
remaining bits of the “A/a” character.
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start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop
UARTn RX
start bit LSB of 'A' or 'a'
UnACR start
rate counter
16xbaud_rate
16 cycles 16 cycles
start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop
UARTn RX
start bit LSB of 'A' or 'a'
UnACR start
rate counter
16xbaud_rate
16 cycles
14.4.11 UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009
8024, U3ICR - 0x4009 C024)
The IrDA Control Register enables and configures the IrDA mode on each UART. The
value of UnICR should not be changed while transmitting or receiving data, or data loss or
corruption may occur.
Table 283: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit
description
Bit Symbol Value Description Reset value
0 IrDAEn 0 IrDA mode on UARTn is disabled, UARTn acts as a standard UART. 0
1 IrDA mode on UARTn is enabled.
1 IrDAInv When 1, the serial input is inverted. This has no effect on the serial output. 0
When 0, the serial input is not inverted.
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Table 283: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit
description
Bit Symbol Value Description Reset value
2 FixPulseEn When 1, enabled IrDA fixed pulse width mode. 0
5:3 PulseDiv Configures the pulse when FixPulseEn = 1. See text below for details. 0
31:6 - NA Reserved, user software should not write ones to reserved bits. The value read 0
from a reserved bit is not defined.
The PulseDiv bits in UnICR are used to select the pulse width when the fixed pulse width
mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits
should be set so that the resulting pulse width is at least 1.63 µs. Table 284 shows the
possible pulse widths.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be greater than 2.
Table 285: UARTn Fractional Divider Register (U0FDR - address 0x4000 C028, U2FDR - 0x4009 8028, U3FDR -
0x4009 C028) bit description
Bit Function Value Description Reset value
3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional 0
baud-rate generator will not impact the UARTn baudrate.
7:4 MULVAL 1 Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for 1
UARTn to operate properly, regardless of whether the fractional baud-rate
generator is used or not.
31:8 - NA Reserved, user software should not write ones to reserved bits. The value read 0
from a reserved bit is not defined.
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This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART0/2/3 disabled making sure that
UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this
feature.
(2)
PCLK
UARTn baudrate = ----------------------------------------------------------------------------------------------------------------------------------
16 × ( 256 × UnDLM + UnDLL ) × ⎛ 1 + -----------------------------⎞
DivAddVal
⎝ MulVal ⎠
Where PCLK is the peripheral clock, U0/2/3DLM and U0/2/3DLL are the standard
UART0/2/3 baud rate divider registers, and DIVADDVAL and MULVAL are UART0/2/3
fractional baud rate generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1 ≤ MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 14
3. DIVADDVAL < MULVAL
The value of the U0/2/3FDR should not be modified while transmitting/receiving data or
data may be lost or corrupted.
If the U0/2/3FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
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Calculating UART
baudrate (BR)
PCLK,
BR
DL est is an True
integer?
False DIVADDVAL = 0
MULVAL = 1
FR est = 1.5
False
1.1 < FR est < 1.9?
True
End
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The closest value for FRest = 1.628 in the look-up Table 286 is FR = 1.625. It is
equivalent to DIVADDVAL = 5 and MULVAL = 8.
Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,
DIVADDVAL = 5, and MULVAL = 8. According to Equation 2 the UART rate is 115384.
This rate has a relative error of 0.16% from the originally specified 115200.
Table 287 describes how to use TXEn bit in order to achieve software flow control.
Table 287: UARTn Transmit Enable Register (U0TER - address 0x4000 C030, U2TER - 0x4009 8030, U3TER -
0x4009 C030) bit description
Bit Symbol Description Reset Value
6:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
7 TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as 1
soon as any preceding data has been sent. If this bit is cleared to 0 while a character is
being sent, the transmission of that character is completed, but no further characters are
sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters
from the THR or TX FIFO into the transmit shift register. Software implementing
software-handshaking can clear this bit when it receives an XOFF character (DC3). Software
can set this bit again when it receives an XON (DC1) character.
14.5 Architecture
The architecture of the UARTs 0, 2 and 3 are shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART.
The UARTn receiver block, UnRX, monitors the serial input line, RXDn, for valid input.
The UARTn RX Shift Register (UnRSR) accepts valid characters via RXDn. After a valid
character is assembled in the UnRSR, it is passed to the UARTn RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
The UARTn transmitter block, UnTX, accepts data written by the CPU or host and buffers
the data in the UARTn TX Holding Register FIFO (UnTHR). The UARTn TX Shift Register
(UnTSR) reads the data stored in the UnTHR and assembles the data to transmit via the
serial output pin, TXDn.
The UARTn Baud Rate Generator block, UnBRG, generates the timing enables used by
the UARTn TX block. The UnBRG clock input source is the APB clock (PCLK). The main
clock is divided down per the divisor specified in the UnDLL and UnDLM registers. This
divided down clock is the 16x oversample clock.
The interrupt interface contains registers UnIER and UnIIR. The interrupt interface
receives several one clock wide enables from the UnTX and UnRX blocks.
Status information from the UnTX and UnRX is stored in the UnLSR. Control information
for the UnTX and UnRX is stored in the UnLCR.
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Transmitter
Transmitter Transmitter
Transmitter Un_TXD
Holding Shift
FIFO
Register Register
Transmitter
DMA
Interface
TX_DMA_REQ
TX_DMA_CLR
FIFO Control
& Status
Interrupt
UARTn interrupt Control & Line Control
& Status
Status
Un_OE
IrDA, & Auto-
baud
Receiver
Receiver Receiver
Receiver Un_RXD
Buffer Shift
FIFO
Register Register
Receiver
DMA
Interface
RX_DMA_REQ
RX_DMA_CLR
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15.2 Features
• Full modem control handshaking available
• Data sizes of 5, 6, 7, and 8 bits.
• Parity generation and checking: odd, even mark, space or none.
• One or two stop bits.
• 16 byte Receive and Transmit FIFOs.
• Built-in baud rate generator, including a fractional rate divider for great versatility.
• Supports DMA for both transmit and receive.
• Auto-baud capability
• Break generation and detection.
• Multiprocessor addressing mode.
• RS-485 support.
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[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
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The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1RBR. The U1RBR is always read-only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U1LSR
register, and then to read a byte from the U1RBR.
Table 290: UART1 Receiver Buffer Register (U1RBR - address 0x4001 0000 when DLAB = 0) bit description
Bit Symbol Description Reset Value
7:0 RBR The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX undefined
FIFO.
31:8 - Reserved, the value read from a reserved bit is not defined. NA
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1THR. The U1THR is write-only.
Table 291: UART1 Transmitter Holding Register (U1THR - address 0x4001 0000 when DLAB = 0) bit description
Bit Symbol Description Reset Value
7:0 THR Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 NA
transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the
transmitter is available.
31:8 - Reserved, user software should not write ones to reserved bits. NA
15.4.3 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0x4001 0000
and U1DLM - 0x4001 0004, when DLAB = 1)
The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce
the baud rate clock, which must be 16x the desired baud rate. The U1DLL and U1DLM
registers together form a 16-bit divisor where U1DLL contains the lower 8 bits of the
divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like
a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in
U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to
select the right value for U1DLL and U1DLM can be found later in this chapter, see
Section 15.4.16.
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Table 292: UART1 Divisor Latch LSB Register (U1DLL - address 0x4001 0000 when DLAB = 1) bit description
Bit Symbol Description Reset Value
7:0 DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the 0x01
baud rate of the UART1.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 293: UART1 Divisor Latch MSB Register (U1DLM - address 0x4001 0004 when DLAB = 1) bit description
Bit Symbol Description Reset Value
7:0 DLMSB The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the 0x00
baud rate of the UART1.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description
Bit Symbol Value Description Reset
Value
0 RBR enables the Receive Data Available interrupt for UART1. It also controls the Character 0
Interrupt Receive Time-out interrupt.
Enable 0 Disable the RDA interrupts.
1 Enable the RDA interrupts.
1 THRE enables the THRE interrupt for UART1. The status of this interrupt can be read from 0
Interrupt U1LSR[5].
Enable 0 Disable the THRE interrupts.
1 Enable the THRE interrupts.
2 RX Line enables the UART1 RX line status interrupts. The status of this interrupt can be read 0
Interrupt from U1LSR[4:1].
Enable 0 Disable the RX line status interrupts.
1 Enable the RX line status interrupts.
3 Modem enables the modem interrupt. The status of this interrupt can be read from U1MSR[3:0]. 0
Status 0 Disable the modem interrupt.
Interrupt
Enable 1 Enable the modem interrupt.
6:4 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
7 CTS If auto-cts mode is enabled this bit enables/disables the modem status interrupt 0
Interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition
Enable will generate an interrupt if Modem Status Interrupt Enable (U1IER[3]) is set.
In normal operation a CTS1 signal transition will generate a Modem Status Interrupt
unless the interrupt has been disabled by clearing the U1IER[3] bit in the U1IER
register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both
the U1IER[3] and U1IER[7] bits are set.
0 Disable the CTS interrupt.
1 Enable the CTS interrupt.
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Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description
Bit Symbol Value Description Reset
Value
8 ABEOIntEn Enables the end of auto-baud interrupt. 0
0 Disable end of auto-baud Interrupt.
1 Enable end of auto-baud Interrupt.
9 ABTOIntEn Enables the auto-baud time-out interrupt. 0
0 Disable auto-baud time-out Interrupt.
1 Enable auto-baud time-out Interrupt.
31:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 295: UART1 Interrupt Identification Register (U1IIR - address 0x4001 0008) bit description
Bit Symbol Value Description Reset
Value
0 IntStatus Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be 1
determined by evaluating U1IIR[3:1].
0 At least one interrupt is pending.
1 No interrupt is pending.
3:1 IntId Interrupt identification. U1IER[3:1] identifies an interrupt corresponding to the 0
UART1 Rx or TX FIFO. All other combinations of U1IER[3:1] not listed below
are reserved (100,101,111).
011 1 - Receive Line Status (RLS).
010 2a - Receive Data Available (RDA).
110 2b - Character Time-out Indicator (CTI).
001 3 - THRE Interrupt.
000 4 - Modem Interrupt.
5:4 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
7:6 FIFO Enable Copies of U1FCR[0]. 0
8 ABEOInt End of auto-baud interrupt. True if auto-baud has finished successfully and 0
interrupt is enabled.
9 ABTOInt Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is 0
enabled.
31:10 - Reserved, the value read from a reserved bit is not defined. NA
Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in Table 296. Given the status of U1IIR[3:0], an
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interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART1RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error
condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared
upon an U1LSR read.
The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the
trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1
Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will
clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2] For details see Section 15.4.10 “UART1 Line Status Register (U1LSR - 0x4001 0014)”
[3] For details see Section 15.4.1 “UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0)”
[4] For details see Section 15.4.5 “UART1 Interrupt Identification Register (U1IIR - 0x4001 0008)” and
Section 15.4.2 “UART1 Transmitter Holding Register (U1THR - 0x4001 0000 when DLAB = 0)”
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The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated
when the UART1 THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART1 THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U1THR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U1THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART1 THR FIFO has held two or more characters at one time and
currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or
a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001).
It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.
Table 297: UART1 FIFO Control Register (U1FCR - address 0x4001 0008) bit description
Bit Symbol Value Description Reset Value
0 FIFO Enable 0 UART1 FIFOs are disabled. Must not be used in the application. 0
1 Active high enable for both UART1 Rx and TX FIFOs and U1FCR[7:1] access.
This bit must be set for proper UART1 operation. Any transition on this bit will
automatically clear the UART1 FIFOs.
1 RX FIFO 0 No impact on either of UART1 FIFOs. 0
Reset 1 Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx FIFO, reset the
pointer logic. This bit is self-clearing.
2 TX FIFO 0 No impact on either of UART1 FIFOs. 0
Reset 1 Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX FIFO, reset the
pointer logic. This bit is self-clearing.
3 DMA Mode When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA 0
Select mode. See Section 15.4.6.1.
5:4 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
7:6 RX Trigger These two bits determine how many receiver UART1 FIFO characters must be 0
Level written before an interrupt is activated.
00 Trigger level 0 (1 character or 0x01).
01 Trigger level 1 (4 characters or 0x04).
10 Trigger level 2 (8 characters or 0x08).
11 Trigger level 3 (14 characters or 0x0E).
31:8 - Reserved, user software should not write ones to reserved bits. NA
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In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO
level becoming equal to or greater than trigger level, or if a character timeout occurs. See
the description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
In DMA mode, the transmitter DMA request is asserted on the event of the transmitter
FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA
controller.
Table 298: UART1 Line Control Register (U1LCR - address 0x4001 000C) bit description
Bit Symbol Value Description Reset Value
1:0 Word Length 00 5-bit character length. 0
Select 01 6-bit character length.
10 7-bit character length.
11 8-bit character length.
2 Stop Bit Select 0 1 stop bit. 0
1 2 stop bits (1.5 if U1LCR[1:0]=00).
3 Parity Enable 0 Disable parity generation and checking. 0
1 Enable parity generation and checking.
5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and the attached 0
parity bit will be odd.
01 Even Parity. Number of 1s in the transmitted character and the attached
parity bit will be even.
10 Forced "1" stick parity.
11 Forced "0" stick parity.
6 Break Control 0 Disable break transmission. 0
1 Enable break transmission. Output pin UART1 TXD is forced to logic 0
when U1LCR[6] is active high.
7 Divisor Latch 0 Disable access to Divisor Latches. 0
Access Bit (DLAB) 1 Enable access to Divisor Latches.
31:8 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
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Table 299: UART1 Modem Control Register (U1MCR - address 0x4001 0010) bit description
Bit Symbol Value Description Reset
value
0 DTR Control Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode 0
is active.
1 RTS Control Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is 0
active.
3-2 - NA Reserved, user software should not write ones to reserved bits. The value read from a 0
reserved bit is not defined.
4 Loopback The modem loopback mode provides a mechanism to perform diagnostic loopback 0
Mode Select testing. Serial data from the transmitter is connected internally to serial input of the
receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in
marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected
externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4
modem outputs are connected to the 4 modem inputs. As a result of these
connections, the upper 4 bits of the U1MSR will be driven by the lower 4 bits of the
U1MCR rather than the 4 modem inputs in normal mode. This permits modem status
interrupts to be generated in loopback mode by writing the lower 4 bits of U1MCR.
0 Disable modem loopback mode.
1 Enable modem loopback mode.
5 - NA Reserved, user software should not write ones to reserved bits. The value read from a 0
reserved bit is not defined.
6 RTSen 0 Disable auto-rts flow control. 0
1 Enable auto-rts flow control.
7 CTSen 0 Disable auto-cts flow control. 0
1 Enable auto-cts flow control.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
15.4.9.1 Auto-RTS
The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control
originates in the U1RBR module and is linked to the programmed receiver FIFO trigger
level. If auto-RTS is enabled, the data-flow is controlled as follows:
When the receiver FIFO level reaches the programmed trigger level, RTS1 is de-asserted
(to a high value). It is possible that the sending UART sends an additional byte after the
trigger level is reached (assuming the sending UART has another byte to send) because it
might not recognize the de-assertion of RTS1 until after it has begun sending the
additional byte. RTS1 is automatically reasserted (to a low value) once the receiver FIFO
has reached the previous trigger level. The re-assertion of RTS1 signals to the sending
UART to continue transmitting data.
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If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If
Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of
RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled,
the value of the RTS Control bit is read-only for software.
Example: Suppose the UART1 operating in ‘550 mode has trigger level in U1FCR set to
0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the
receive FIFO contains 8 bytes (Table 297 on page 325). The RTS1 output will be
reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.
UART1 Rx
~
~
start byte N stop start bits0..7 stop start bits0..7 stop
~
~
RTS1 pin
UART1 Rx
FIFO read
~~
~ ~
UART1 Rx N-1 N N-1 N-2 N-1 N-2 M+2 M+1 M M-1
FIFO level
~
~
Fig 48. Auto-RTS Functional Timing
15.4.9.2 Auto-CTS
The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the
transmitter circuitry in the U1TSR module checks CTS1 input before sending the next
data byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the
transmitter from sending the following byte, CTS1 must be released before the middle of
the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1
signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set,
Delta CTS bit in the U1MSR will be set though. Table 300 lists the conditions for
generating a Modem Status interrupt.
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The auto-CTS function reduces interrupts to the host system. When flow control is
enabled, a CTS1 state change does not trigger host interrupts because the device
automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error can result. Figure 49
illustrates the Auto-CTS functional timing.
UART1 TX
~
~
~
~
start bits0..7 stop start bits0..7 stop start bits0..7 stop
~
~
CTS1 pin ~
~
While starting transmission of the initial character the CTS1 signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS1 is de-asserted (high). As soon as CTS1 gets
de-asserted transmission resumes and a start bit is sent followed by the data bits of the
next character.
Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description
Bit Symbol Value Description Reset
Value
0 Receiver Data U1LSR[0] is set when the U1RBR holds an unread character and is cleared when 0
Ready (RDR) the UART1 RBR FIFO is empty.
0 The UART1 receiver FIFO is empty.
1 The UART1 receiver FIFO is not empty.
1 Overrun Error The overrun error condition is set as soon as it occurs. An U1LSR read clears 0
(OE) U1LSR[1]. U1LSR[1] is set when UART1 RSR has a new character assembled
and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be
overwritten and the character in the UART1 RSR will be lost.
0 Overrun error status is inactive.
1 Overrun error status is active.
2 Parity Error (PE) When the parity bit of a received character is in the wrong state, a parity error 0
occurs. An U1LSR read clears U1LSR[2]. Time of parity error detection is
dependent on U1FCR[0].
Note: A parity error is associated with the character at the top of the UART1 RBR
FIFO.
0 Parity error status is inactive.
1 Parity error status is active.
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Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description
Bit Symbol Value Description Reset
Value
3 Framing Error When the stop bit of a received character is a logic 0, a framing error occurs. An 0
(FE) U1LSR read clears U1LSR[3]. The time of the framing error detection is
dependent on U1FCR0. Upon detection of a framing error, the RX will attempt to
resynchronize to the data and assume that the bad stop bit is actually an early
start bit. However, it cannot be assumed that the next received byte will be correct
even if there is no Framing Error.
Note: A framing error is associated with the character at the top of the UART1
RBR FIFO.
0 Framing error status is inactive.
1 Framing error status is active.
4 Break Interrupt When RXD1 is held in the spacing state (all zeroes) for one full character 0
(BI) transmission (start, data, parity, stop), a break interrupt occurs. Once the break
condition has been detected, the receiver goes idle until RXD1 goes to marking
state (all ones). An U1LSR read clears this status bit. The time of break detection
is dependent on U1FCR[0].
Note: The break interrupt is associated with the character at the top of the UART1
RBR FIFO.
0 Break interrupt status is inactive.
1 Break interrupt status is active.
5 Transmitter THRE is set immediately upon detection of an empty UART1 THR and is cleared 1
Holding Register on a U1THR write.
Empty (THRE) 0 U1THR contains valid data.
1 U1THR is empty.
6 Transmitter TEMT is set when both U1THR and U1TSR are empty; TEMT is cleared when 1
Empty (TEMT) either the U1TSR or the U1THR contain valid data.
0 U1THR and/or the U1TSR contains valid data.
1 U1THR and the U1TSR are empty.
7 Error in RX FIFO U1LSR[7] is set when a character with a RX error such as framing error, parity 0
(RXFE) error or break interrupt, is loaded into the U1RBR. This bit is cleared when the
U1LSR register is read and there are no subsequent errors in the UART1 FIFO.
0 U1RBR contains no UART1 RX errors or U1FCR[0]=0.
1 UART1 RBR contains at least one UART1 RX error.
31:8 - Reserved, the value read from a reserved bit is not defined. NA
Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description
Bit Symbol Value Description Reset Value
0 Delta CTS Set upon state change of input CTS. Cleared on an U1MSR read. 0
0 No change detected on modem input, CTS.
1 State change detected on modem input, CTS.
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Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description
Bit Symbol Value Description Reset Value
1 Delta DSR Set upon state change of input DSR. Cleared on an U1MSR read. 0
0 No change detected on modem input, DSR.
1 State change detected on modem input, DSR.
2 Trailing Edge RI Set upon low to high transition of input RI. Cleared on an U1MSR read. 0
0 No change detected on modem input, RI.
1 Low-to-high transition detected on RI.
3 Delta DCD Set upon state change of input DCD. Cleared on an U1MSR read. 0
0 No change detected on modem input, DCD.
1 State change detected on modem input, DCD.
4 CTS Clear To Send State. Complement of input signal CTS. This bit is 0
connected to U1MCR[1] in modem loopback mode.
5 DSR Data Set Ready State. Complement of input signal DSR. This bit is 0
connected to U1MCR[0] in modem loopback mode.
6 RI Ring Indicator State. Complement of input RI. This bit is connected to 0
U1MCR[2] in modem loopback mode.
7 DCD Data Carrier Detect State. Complement of input DCD. This bit is connected 0
to U1MCR[3] in modem loopback mode.
31:8 - Reserved, the value read from a reserved bit is not defined. NA
Table 303: UART1 Scratch Pad Register (U1SCR - address 0x4001 0014) bit description
Bit Symbol Description Reset Value
7:0 Pad A readable, writable byte. 0x00
Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description
Bit Symbol Value Description Reset value
0 Start This bit is automatically cleared after auto-baud completion. 0
0 Auto-baud stop (auto-baud is not running).
1 Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
automatically cleared after auto-baud completion.
1 Mode Auto-baud mode select bit. 0
0 Mode 0.
1 Mode 1.
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Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description
Bit Symbol Value Description Reset value
2 AutoRestart 0 No restart 0
1 Restart in case of time-out (counter restarts at next UART1 Rx falling edge) 0
7:3 - NA Reserved, user software should not write ones to reserved bits. The value read 0
from a reserved bit is not defined.
8 ABEOIntClr End of auto-baud interrupt clear bit (write-only accessible). 0
0 Writing a 0 has no impact.
1 Writing a 1 will clear the corresponding interrupt in the U1IIR.
9 ABTOIntClr Auto-baud time-out interrupt clear bit (write-only accessible). 0
0 Writing a 0 has no impact.
1 Writing a 1 will clear the corresponding interrupt in the U1IIR.
31:10 - NA Reserved, user software should not write ones to reserved bits. The value read 0
from a reserved bit is not defined.
15.4.14 Auto-baud
The UART1 auto-baud function can be used to measure the incoming baud-rate based on
the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit
time of the receive data stream and set the divisor latch registers U1DLM and U1DLL
accordingly.
Remark: the fractional rate divider is not connected during auto-baud operations, and
therefore should not be used when the auto-baud feature is needed.
Auto-baud is started by setting the U1ACR Start bit. Auto-baud can be stopped by clearing
the U1ACR Start bit. The Start bit will clear once auto-baud has finished and reading the
bit will return the status of auto-baud (pending/finished).
Two auto-baud measuring modes are available which can be selected by the U1ACR
Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the
UART1 Rx pin (the falling edge of the start bit and the falling edge of the least significant
bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent
rising edge of the UART1 Rx pin (the length of the start bit).
The U1ACR AutoRestart bit can be used to automatically restart baud-rate measurement
if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate
measurement will restart at the next falling edge of the UART1 Rx pin.
• The U1IIR ABTOInt interrupt will get set if the interrupt is enabled (U1IER ABToIntEn
is set and the auto-baud rate measurement counter overflows).
• The U1IIR ABEOInt interrupt will get set if the interrupt is enabled (U1IER ABEOIntEn
is set and the auto-baud has completed successfully).
register is not going to be modified after rate measurement. Also, when auto-baud is used,
any write to U1DLM and U1DLL registers should be done before U1ACR register write.
The minimum and the maximum baud rates supported by UART1 are function of pclk,
number of data bits, stop bits and parity bits.
(3)
2 × P CLK PCLK
ratemin = ------------------------- ≤ UART 1 baudrate ≤ ------------------------------------------------------------------------------------------------------------ = ratemax
16 × 2 15 16 × ( 2 + databits + paritybits + stopbits )
1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and the
UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate.
2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The rate
measuring counter will start counting pclk cycles optionally pre-scaled by the
fractional baud-rate generator.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
the frequency of the (fractional baud-rate pre-scaled) UART1 input clock,
guaranteeing the start bit is stored in the U1RSR.
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
counter will continue incrementing with the pre-scaled UART1 input clock (pclk).
5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If
Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin.
6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched to
normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt
U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the
remaining bits of the “A/a” character.
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start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop
UARTn RX
start bit LSB of 'A' or 'a'
U0ACR start
rate counter
16xbaud_rate
16 cycles 16 cycles
start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop
UARTn RX
start bit LSB of 'A' or 'a'
U1ACR start
rate counter
16xbaud_rate
16 cycles
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be greater than 2.
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Table 305: UART1 Fractional Divider Register (U1FDR - address 0x4001 0028) bit description
Bit Function Value Description Reset value
3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional 0
baud-rate generator will not impact the UARTn baudrate.
7:4 MULVAL 1 Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for 1
UARTn to operate properly, regardless of whether the fractional baud-rate
generator is used or not.
31:8 - NA Reserved, user software should not write ones to reserved bits. The value read 0
from a reserved bit is not defined.
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART1 disabled making sure that UART1
is fully software and hardware compatible with UARTs not equipped with this feature.
(4)
PCLK
UART1 baudrate = ----------------------------------------------------------------------------------------------------------------------------------
16 × ( 256 × U1DLM + U1DLL ) × ⎛ 1 + -----------------------------⎞
DivAddVal
⎝ MulVal ⎠
Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud
rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1 ≤ MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 14
3. DIVADDVAL < MULVAL
The value of the U1FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
If the U1FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
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Calculating UART
baudrate (BR)
PCLK,
BR
DL est is an True
integer?
False DIVADDVAL = 0
MULVAL = 1
FR est = 1.5
False
1.1 < FR est < 1.9?
True
End
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The closest value for FRest = 1.628 in the look-up Table 306 is FR = 1.625. It is
equivalent to DIVADDVAL = 5 and MULVAL = 8.
Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,
DIVADDVAL = 5, and MULVAL = 8. According to Equation 4 the UART rate is 115384.
This rate has a relative error of 0.16% from the originally specified 115200.
Although Table 307 describes how to use TxEn bit in order to achieve hardware flow
control, it is strongly suggested to let UART1 hardware implemented auto flow control
features take care of this, and limit the scope of TxEn to software flow control.
U1TER enables implementation of software and hardware flow control. When TXEn=1,
UART1 transmitter will keep sending data as long as they are available. As soon as TXEn
becomes 0, UART1 transmission will stop.
Table 307 describes how to use TXEn bit in order to achieve software flow control.
Table 307: UART1 Transmit Enable Register (U1TER - address 0x4001 0030) bit description
Bit Symbol Description Reset Value
6:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
7 TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as 1
soon as any preceding data has been sent. If this bit cleared to 0 while a character is being
sent, the transmission of that character is completed, but no further characters are sent until
this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the
THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects
that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software
handshaking, when it receives an XOFF character (DC3). Software can set this bit again
when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1)
character.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description
Bit Symbol Value Description Reset value
0 NMMEN 0 RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0
1 RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an
address is detected when a received byte causes the UART to set the parity error
and generate an interrupt.
1 RXDIS 0 The receiver is enabled. 0
1 The receiver is disabled.
2 AADEN 0 Auto Address Detect (AAD) is disabled. 0
1 Auto Address Detect (AAD) is enabled.
3 SEL 0 If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0
1 If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.
4 DCTRL 0 Disable Auto Direction Control. 0
1 Enable Auto Direction Control.
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Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description
Bit Symbol Value Description Reset value
5 OINV This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 0
0 The direction control pin will be driven to logic ‘0’ when the transmitter has data to
be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted.
1 The direction control pin will be driven to logic ‘1’ when the transmitter has data to
be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted.
31:6 - - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
Table 309. UART1 RS-485 Address Match register (U1RS485ADRMATCH - address 0x4001 0050) bit description
Bit Symbol Description Reset value
7:0 ADRMATCH Contains the address match value. 0x00
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 310. UART1 RS-485 Delay value register (U1RS485DLY - address 0x4001 0054) bit description
Bit Symbol Description Reset value
7:0 DLY Contains the direction control (RTS or DTR) delay value. This register works in 0x00
conjunction with an 8-bit counter.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
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If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received data bytes will be
ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit
= ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated.
The processor can then read the address byte and decide whether or not to enable the
receiver to accept the following data.
While the receiver is ENABLED (RS485CTRL bit 1 =’0’) all received bytes will be
accepted and stored in the RXFIFO regardless of whether they are data or address. When
an address character is received a parity error interrupt will be generated and the
processor can decide whether or not to disable the receiver.
In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit
value programmed into the RS485ADRMATCH register.
If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received byte will be discarded if
it is either a data byte OR an address byte which fails to match the RS485ADRMATCH
value.
When a matching address character is detected it will be pushed onto the RXFIFO along
with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be
cleared by hardware). The receiver will also generate n Rx Data Ready Interrupt.
While the receiver is ENABLED (RS485CTRL bit 1 = ‘0’) all bytes received will be
accepted and stored in the RXFIFO until an address byte which does not match the
RS485ADRMATCH value is received. When this occurs, the receiver will be automatically
disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address
character will not be stored in the RXFIFO.
Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use
the DTR pin when RS485CTRL bit 3 = ‘1’.
When Auto Direction Control is enabled, the selected pin will be asserted (driven low)
when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven high) once
the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register.
The RS485CTRL bit 4 takes precedence over all other mechanisms controlling RTS (or
DTR) with the exception of loopback mode.
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15.5 Architecture
The architecture of the UART1 is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART1.
The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input.
The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1. After a valid
character is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers
the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register
(U1TSR) reads the data stored in the U1THR and assembles the data to transmit via the
serial output pin, TXD1.
The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by
the UART1 TX block. The U1BRG clock input source is the APB clock (PCLK). The main
clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This
divided down clock is the 16x oversample clock.
The modem interface contains registers U1MCR and U1MSR. This interface is
responsible for handshaking between a modem peripheral and the UART1.
The interrupt interface contains registers U1IER and U1IIR. The interrupt interface
receives several one clock wide enables from the U1TX and U1RX blocks.
Status information from the U1TX and U1RX is stored in the U1LSR. Control information
for the U1TX and U1RX is stored in the U1LCR.
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Transmitter
Transmitter Transmitter
Transmitter U1_TXD
Holding Shift
FIFO
Register Register
Transmitter
DMA
Interface
TX_DMA_REQ
TX_DMA_CLR
UART1 interrupt
FIFO Control
U1_CTS & Status
U1_RTS Interrupt
Line Control
Modem Control &
U1_DSR & Status
Control Status
U1_DTR
& U1_OE RS485, IrDA,
U1_DCD Status & Auto-baud
U1_RI
Receiver
Receiver Receiver
Receiver U1_RXD
Buffer Shift
FIFO
Register Register
Receiver
DMA
Interface
RX_DMA_REQ
RX_DMA_CLR
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The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
various applications.
The CAN module consists of two elements: the controller and the Acceptance Filter. All
registers and the RAM are accessed as 32-bit words.
16.3 Features
• APB Interface
• Acceptance Filter
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TRANSMIT
BUFFERS 1,2
AND 3 BIT
COMMON
TIMING
STATUS
LOGIC
REGISTER
BIT
RECEIVE
ACCEPTANCE STREAM
BUFFERS 1
FILTER PROCESSOR
AND 2
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31 24 23 16 15 87 0
31 24 23 16 15 87 0
Fig 54. Transmit buffer layout for standard and extended frame format configurations
The global layout of the Receive Buffer is very similar to the Transmit Buffer described
earlier. Identifier, Frame Format, Remote Transmission Request bit and Data Length
Code have the same meaning as described for the Transmit Buffer. In addition, the
Receive Buffer includes an ID Index field (see Section 16.7.9.1 “ID index field”).
The received Data Length Code represents the real transmitted Data Length Code, which
may be greater than 8 depending on transmitting CAN node. Nevertheless, the maximum
number of received data bytes is 8. This should be taken into account by reading a
message from the Receive Buffer. If there is not enough space for a new message within
the Receive Buffer, the CAN Controller generates a Data Overrun condition when this
message becomes valid and the acceptance test was positive. A message that is partly
written into the Receive Buffer (when the Data Overrun situation occurs) is deleted. This
situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if
enabled.
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31 24 23 16 15 10 9 8 7 0
31 24 23 16 15 10 9 8 7 0
Fig 55. Receive buffer layout for standard and extended frame format configurations
• Global Self-Test (setting the self reception request bit in normal Operating Mode)
• Local Self-Test (setting the self reception request bit in Self Test Mode)
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Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self
Reception Request, the transmitted message is also received and stored in the receive
buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the
CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled.
TX
TXBuffer
Buffer CAN Bus
TX Buffer
LPC17xx Transceiver
ack
RX Buffer
Initiating a Global Self-Test is similar to a normal CAN transmission. In this case the
transmission of a CAN message(s) is initiated by setting Self Reception Request bit
(SRR) in conjunction with the selected Message Buffer bits (STB3, STB2, STB1) in the
CAN Controller Command register (CANCMR).
TX
TXBuffer
TXBuffer
Buffer
LPC17xx Transceiver
RX Buffer
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The internal registers of each CAN Controller appear to the CPU as on-chip memory
mapped peripheral registers. Because the CAN Controller can operate in different modes
(Operating/Reset, see also Section 16.7.1 “CAN Mode register (CAN1MOD -
0x4004 4000, CAN2MOD - 0x4004 8000)”), one has to distinguish between different
internal address definitions. Note that write access to some registers is only allowed in
Reset Mode.
In the following register tables, the column “Reset Value” shows how a hardware reset
affects each bit or field, while the column “RM Set” indicates how each bit or field is
affected if software sets the RM bit, or RM is set because of a Bus-Off condition. Note that
while hardware reset sets RM, in this case the setting noted in the “Reset Value” column
prevails over that shown in the “RM Set” column, in the few bits where they differ. In both
columns, X indicates the bit or field is unchanged.
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Table 317. CAN Mode register (CAN1MOD - address 0x4004 4000, CAN2MOD - address 0x4004 8000) bit description
Bit Symbol Value Function Reset RM
Value Set
0 RM[1][6] Reset Mode. 1 1
0 (normal) The CAN Controller is in the Operating Mode, and certain registers can not
be written.
1 (reset) CAN operation is disabled, writable registers can be written and the current
transmission/reception of a message is aborted.
1 LOM[3][2] Listen Only Mode. 0 x
[6]
0 (normal) The CAN controller acknowledges a successfully received message on the
CAN bus. The error counters are stopped at the current value.
1 (listen only) The controller gives no acknowledgment, even if a message is successfully
received. Messages cannot be sent, and the controller operates in “error
passive” mode. This mode is intended for software bit rate detection and
“hot plugging”.
2 STM[3][6] Self Test Mode. 0 x
0 (normal) A transmitted message must be acknowledged to be considered successful.
1 (self test) The controller will consider a Tx message successful even if there is no
acknowledgment received.
In this mode a full node test is possible without any other active node on the
bus using the SRR bit in CANxCMR.
3 TPM[4] Transmit Priority Mode. 0 x
0 (CAN ID) The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.
1 (local prio) The transmit priority for 3 Transmit Buffers depends on the contents of the
Tx Priority register within the Transmit Buffer.
4 SM[5] Sleep Mode. 0 0
0 (wake-up) Normal operation.
1 (sleep) The CAN controller enters Sleep Mode if no CAN interrupt is pending and
there is no bus activity. See the Sleep Mode description Section 16.8.2 on
page 371.
5 RPM Receive Polarity Mode. 0 x
0 (low active) RD input is active Low (dominant bit = 0).
1 (high active) RD input is active High (dominant bit = 1) -- reverse polarity.
6 - - Reserved, user software should not write ones to reserved bits. 0 0
7 TM Test Mode. 0 x
0 (disabled) Normal operation.
1 (enabled) The TD pin will reflect the bit, detected on RD pin, with the next positive
edge of the system clock.
31:8 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
[1] During a Hardware reset or when the Bus Status bit is set '1' (Bus-Off), the Reset Mode bit is set '1' (present). After the Reset Mode bit
is set '0' the CAN Controller will wait for:
- one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by a Hardware reset or a CPU-initiated
reset.
- 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off, before re-entering the
Bus-On mode.
[2] This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The Listen Only Mode can
be used e.g. for software driven bit rate detection and "hot plugging".
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[3] A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously.
[4] Transmit Priority Mode is explained in more detail in Section 16.5.3 “Transmit Buffers (TXB)”.
[5] The CAN Controller will enter Sleep Mode, if the Sleep Mode bit is set '1' (sleep), there is no bus activity, and none of the CAN interrupts
is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN
Controller will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping
CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits
(Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible only
when Bus-Free is detected again.
[6] The LOM and STM bits can only be written if the RM bit is 1 prior to the write operation.
At least one internal clock cycle is needed for processing between two commands.
Table 318. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit
description
Bit Symbol Value Function Reset RM
Value Set
0[1][2] TR Transmission Request. 0 0
0 (absent) No transmission request.
1 (present) The message, previously written to the CANxTFI, CANxTID, and
optionally the CANxTDA and CANxTDB registers, is queued for
transmission from the selected Transmit Buffer. If at two or all three of
STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit
Buffer will be selected based on the chosen priority scheme (for details
see Section 16.5.3 “Transmit Buffers (TXB)”)
1[1][3] AT Abort Transmission. 0 0
0 (no action) Do not abort the transmission.
1 (present) if not already in progress, a pending Transmission Request for the
selected Transmit Buffer is cancelled.
2[4] RRB Release Receive Buffer. 0 0
0 (no action) Do not release the receive buffer.
1 (released) The information in the Receive Buffer (consisting of CANxRFS,
CANxRID, and if applicable the CANxRDA and CANxRDB registers) is
released, and becomes eligible for replacement by the next received
frame. If the next received frame is not available, writing this command
clears the RBS bit in the Status Register(s).
3[5] CDO Clear Data Overrun. 0 0
0 (no action) Do not clear the data overrun bit.
1 (clear) The Data Overrun bit in Status Register(s) is cleared.
4[1][6] SRR Self Reception Request. 0 0
0 (absent) No self reception request.
1 (present) The message, previously written to the CANxTFS, CANxTID, and
optionally the CANxTDA and CANxTDB registers, is queued for
transmission from the selected Transmit Buffer and received
simultaneously. This differs from the TR bit above in that the receiver is
not disabled during the transmission, so that it receives the message if its
Identifier is recognized by the Acceptance Filter.
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Table 318. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit
description
Bit Symbol Value Function Reset RM
Value Set
5 STB1 Select Tx Buffer 1. 0 0
0 (not selected) Tx Buffer 1 is not selected for transmission.
1 (selected) Tx Buffer 1 is selected for transmission.
6 STB2 Select Tx Buffer 2. 0 0
0 (not selected) Tx Buffer 2 is not selected for transmission.
1 (selected) Tx Buffer 2 is selected for transmission.
7 STB3 Select Tx Buffer 3. 0 0
0 (not selected) Tx Buffer 3 is not selected for transmission.
1 (selected) Tx Buffer 3 is selected for transmission.
31:8 - Reserved, user software should not write ones to reserved bits. NA
[1] - Setting the command bits TR and AT simultaneously results in transmitting a message once. No re-transmission will be performed in
case of an error or arbitration lost (single shot transmission).
- Setting the command bits SRR and TR simultaneously results in sending the transmit message once using the self-reception feature.
No re-transmission will be performed in case of an error or arbitration lost.
- Setting the command bits TR, AT and SRR simultaneously results in transmitting a message once as described for TR and AT. The
moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit is cleared automatically.
- Setting TR and SRR simultaneously will ignore the set SRR bit.
[2] If the Transmission Request or the Self-Reception Request bit was set '1' in a previous command, it cannot be cancelled by resetting the
bits. The requested transmission may only be cancelled by setting the Abort Transmission bit.
[3] The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a
more urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been either
transmitted successfully or aborted, the Transmission Complete Status bit should be checked. This should be done after the Transmit
Buffer Status bit has been set to '1' or a Transmit Interrupt has been generated.
[4] After reading the contents of the Receive Buffer, the CPU can release this memory space by setting the Release Receive Buffer bit '1'.
This may result in another message becoming immediately available. If there is no other message available, the Receive Interrupt bit is
reset. If the RRB command is given, it will take at least 2 internal clock cycles before a new interrupt is generated.
[5] This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as the Data Overrun
Status bit is set no further Data Overrun Interrupt is generated.
[6] Upon Self Reception Request, a message is transmitted and simultaneously received if the Acceptance Filter is set to the corresponding
identifier. A receive and a transmit interrupt will indicate correct self reception (see also Self Test Mode in Section 16.7.1 “CAN Mode
register (CAN1MOD - 0x4004 4000, CAN2MOD - 0x4004 8000)”).
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Table 319. CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit
description
Bit Symbol Value Function Reset RM
Value Set
0 RBS[1] Receive Buffer Status. 0 0
0 (empty) No message is available.
1 (full) At least one complete message is received by the Double Receive Buffer
and available in the CANxRFS, CANxRID, and if applicable the CANxRDA
and CANxRDB registers. This bit is cleared by the Release Receive Buffer
command in CANxCMR, if no subsequent received message is available.
1 DOS[2] Data Overrun Status. 0 0
0 (absent) No data overrun has occurred since the last Clear Data Overrun command
was given/written to CANxCMR (or since Reset).
1 (overrun) A message was lost because the preceding message to this CAN controller
was not read and released quickly enough (there was not enough space for
a new message in the Double Receive Buffer).
2 TBS Transmit Buffer Status. 1 1
0 (locked) At least one of the Transmit Buffers is not available for the CPU, i.e. at least
one previously queued message for this CAN controller has not yet been
sent, and therefore software should not write to the CANxTFI, CANxTID,
CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).
1 (released) All three Transmit Buffers are available for the CPU. No transmit message is
pending for this CAN controller (in any of the 3 Tx buffers), and software may
write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
3 TCS[3] Transmit Complete Status. 1 x
0 (incomplete) At least one requested transmission has not been successfully completed
yet.
1 (complete) All requested transmission(s) has (have) been successfully completed.
4 RS[4] Receive Status. 1 0
0 (idle) The CAN controller is idle.
1 (receive) The CAN controller is receiving a message.
5 TS[4] Transmit Status. 1 0
0 (idle) The CAN controller is idle.
1 (transmit) The CAN controller is sending a message.
6 ES[5] Error Status. 0 0
0 (ok) Both error counters are below the Error Warning Limit.
1 (error) One or both of the Transmit and Receive Error Counters has reached the
limit set in the Error Warning Limit register.
7 BS[6] Bus Status. 0 0
0 (Bus-On) The CAN Controller is involved in bus activities
1 (Bus-Off) The CAN controller is currently not involved/prohibited from bus activity
because the Transmit Error Counter reached its limiting value of 255.
15:8 - - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
23:16 RXERR - The current value of the Rx Error Counter (an 8-bit value). 0 X
31:24 TXERR - The current value of the Tx Error Counter (an 8-bit value). 0 X
[1] After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.
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[2] If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is
signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an
error), no overrun condition is signalled.
[3] The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit
is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are
transmitted successfully.
[4] If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to
become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this
will take 128 times of 11 consecutive recessive bits.
[5] Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is
set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if
enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 16.7.7 “CAN Error Warning
Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)”.
[6] Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and
the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN
Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error
Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error
Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the
Bus-Off recovery.
RX error counter
The RX Error Counter Register, which is part of the Status Register, reflects the current
value of the Receive Error Counter. After hardware reset this register is initialized to 0. In
Operating Mode this register appears to the CPU as a read-only memory. A write access
to this register is possible only in Reset Mode. If a Bus Off event occurs, the RX Error
Counter is initialized to 0. As long as Bus Off is valid, writing to this register has no
effect.The Rx Error Counter is determined as follows:
Note that a CPU-forced content change of the RX Error Counter is possible only if the
Reset Mode was entered previously. An Error Status change (Status Register), an Error
Warning or an Error Passive Interrupt forced by the new register content will not occur
until the Reset Mode is cancelled again.
TX error counter
The TX Error Counter Register, which is part of the Status Register, reflects the current
value of the Transmit Error Counter. In Operating Mode this register appears to the CPU
as a read-only memory. After hardware reset this register is initialized to 0. A write access
to this register is possible only in Reset Mode. If a bus-off event occurs, the TX Error
Counter is initialized to 127 to count the minimum protocol-defined time (128 occurrences
of the Bus-Free signal). Reading the TX Error Counter during this time gives information
about the status of the Bus-Off recovery. If Bus Off is active, a write access to TXERR in
the range of 0 to 254 clears the Bus Off Flag and the controller will wait for one occurrence
of 11 consecutive recessive bits (bus free) after clearing of Reset Mode. The Tx error
counter is determined as follows:
Writing 255 to TXERR allows initiation of a CPU-driven Bus Off event. Note that a
CPU-forced content change of the TX Error Counter is possible only if the Reset Mode
was entered previously. An Error or Bus Status change (Status Register), an Error
Warning, or an Error Passive Interrupt forced by the new register content will not occur
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until the Reset Mode is cancelled again. After leaving the Reset Mode, the new TX
Counter content is interpreted and the Bus Off event is performed in the same way as if it
was forced by a bus error event. That means, that the Reset Mode is entered again, the
TX Error Counter is initialized to 127, the RX Counter is cleared, and all concerned Status
and Interrupt Register bits are set. Clearing of Reset Mode now will perform the protocol
defined Bus Off recovery sequence (waiting for 128 occurrences of the Bus-Free signal).
If the Reset Mode is entered again before the end of Bus Off recovery (TXERR>0), Bus
Off keeps active and TXERR is frozen.
The Interrupt flags of the Interrupt and Capture Register allow the identification of an
interrupt source. When one or more bits are set, a CAN interrupt will be indicated to the
CPU. After this register is read from the CPU all interrupt bits are reset except of the
Receive Interrupt bit. The Interrupt Register appears to the CPU as a read-only memory.
Bits 16-23 are captured when a bus error occurs. At the same time, if the BEIE bit in
CANIER is 1, the BEI bit in this register is set, and a CAN interrupt can occur.
Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in
CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either
of these bytes is captured, its value will remain the same until it is read, at which time it is
released to capture a new value.
The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read
from CANxICR, regardless of whether part or all of the register is read. This means that
software should always read CANxICR as a word, and process and deal with all bits of the
register as appropriate for the application.
Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)
bit description
Bit Symbol Value Function Reset RM
Value Set
0 RI[1] 0 (reset) Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE 0 0
1 (set) bit in CANxIER are both 1, indicating that a new message was received and
stored in the Receive Buffer.
1 TI1 0 (reset) Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 0 0
1 (set) 1 (whenever a message out of TXB1 was successfully transmitted or aborted),
indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.
2 EI 0 (reset) Error Warning Interrupt. This bit is set on every change (set or clear) of either the 0 X
1 (set) Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the
Interrupt Enable Register at the time of the change.
3 DOI 0 (reset) Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 0 0
1 (set) to 1 and the DOIE bit in CANxIER is 1.
4 WUI[2] 0 (reset) Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity 0 0
1 (set) is detected and the WUIE bit in CANxIER is 1.
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Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)
bit description
Bit Symbol Value Function Reset RM
Value Set
5 EPI 0 (reset) Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the 0 0
1 (set) CAN controller switches between Error Passive and Error Active mode in either
direction.
This is the case when the CAN Controller has reached the Error Passive Status
(at least one error counter exceeds the CAN protocol defined level of 127) or if
the CAN Controller is in Error Passive Status and enters the Error Active Status
again.
6 ALI 0 (reset) Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the 0 0
1 (set) CAN controller loses arbitration while attempting to transmit. In this case the
CAN node becomes a receiver.
7 BEI 0 (reset) Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN 0 X
1 (set) controller detects an error on the bus.
8 IDI 0 (reset) ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN 0 0
1 (set) Identifier has been received (a message was successfully transmitted or
aborted). This bit is set whenever a message was successfully transmitted or
aborted and the IDIE bit is set in the IER register.
9 TI2 0 (reset) Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 0 0
1 (set) 1 (whenever a message out of TXB2 was successfully transmitted or aborted),
indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.
10 TI3 0 (reset) Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 0 0
1 (set) 1 (whenever a message out of TXB3 was successfully transmitted or aborted),
indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.
15:11 - - Reserved, user software should not write ones to reserved bits. 0 0
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Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)
bit description
Bit Symbol Value Function Reset RM
Value Set
20:16 ERRBIT Error Code Capture: when the CAN controller detects a bus error, the location of 0 X
4:0[3] the error within the frame is captured in this field. The value reflects an internal
state variable, and as a result is not very linear:
00011 Start of Frame
00010 ID28 ... ID21
00110 ID20 ... ID18
00100 SRTR Bit
00101 IDE bit
00111 ID17 ... 13
01111 ID12 ... ID5
01110 ID4 ... ID0
01100 RTR Bit
01101 Reserved Bit 1
01001 Reserved Bit 0
01011 Data Length Code
01010 Data Field
01000 CRC Sequence
11000 CRC Delimiter
11001 Acknowledge Slot
11011 Acknowledge Delimiter
11010 End of Frame
10010 Intermission
10001 Active Error Flag
10110 Passive Error Flag
10011 Tolerate Dominant Bits
10111 Error Delimiter
11100 Overload flag
21 ERRDIR When the CAN controller detects a bus error, the direction of the current bit is 0 X
captured in this bit.
0 Error occurred during transmitting.
1 Error occurred during receiving.
23:22 ERRC1:0 When the CAN controller detects a bus error, the type of error is captured in this 0 X
field:
00 Bit error
01 Form error
10 Stuff error
11 Other error
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Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)
bit description
Bit Symbol Value Function Reset RM
Value Set
31:24 ALCBIT[4] - Each time arbitration is lost while trying to send on the CAN, the bit number 0 X
within the frame is captured into this field. After the content of ALCBIT is read,
the ALI bit is cleared and a new Arbitration Lost interrupt can occur.
00 arbitration lost in the first bit (MS) of identifier
...
11 arbitration lost in SRTS bit (RTR bit for standard frame messages)
12 arbitration lost in IDE bit
13 arbitration lost in 12th bit of identifier (extended frame only)
...
30 arbitration lost in last bit of identifier (extended frame only)
31 arbitration lost in RTR bit (extended frame only)
[1] The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command
“Release Receive Buffer” will clear RI temporarily. If there is another message available within the Receive
Buffer after the release command, RI is set again. Otherwise RI remains cleared.
[2] A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is
involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the
according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.
[3] Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time,
the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The
content within this register is fixed until the user software has read out its content once. From now on, the
capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt.
[4] On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current
bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content
within this register is fixed until the user application has read out its contents once. From now on, the
capture mechanism is activated again.
Table 321. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit
description
Bit Symbol Function Reset RM
Value Set
0 RIE Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller 0 X
requests the respective interrupt.
1 TIE1 Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted 0 X
out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission
command), the CAN Controller requests the respective interrupt.
2 EIE Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the 0 X
CAN Controller requests the respective interrupt.
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Table 321. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit
description
Bit Symbol Function Reset RM
Value Set
3 DOIE Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the 0 X
CAN Controller requests the respective interrupt.
4 WUIE Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt 0 X
is requested.
5 EPIE Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error 0 X
active to error passive or vice versa, the respective interrupt is requested.
6 ALIE Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective 0 X
interrupt is requested.
7 BEIE Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the 0 X
respective interrupt.
8 IDIE ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller 0 X
requests the respective interrupt.
9 TIE2 Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted 0 X
out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission
command), the CAN Controller requests the respective interrupt.
10 TIE3 Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted 0 X
out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission
command), the CAN Controller requests the respective interrupt.
31:11 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 322. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit
description
Bit Symbol Value Function Reset RM
Value Set
9:0 BRP Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the 0 X
CAN clock.
13:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
15:14 SJW The Synchronization Jump Width is (this value plus one) CAN clocks. 0 X
19:16 TESG1 The delay from the nominal Sync point to the sample point is (this value plus one) 1100 X
CAN clocks.
22:20 TESG2 The delay from the sample point to the next nominal sync point is (this value plus one) 001 X
CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3)
CAN clocks.
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Table 322. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit
description
Bit Symbol Value Function Reset RM
Value Set
23 SAM Sampling
0 The bus is sampled once (recommended for high speed buses) 0 X
1 The bus is sampled 3 times (recommended for low to medium speed buses to filter
spikes on the bus-line)
31:24 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
(5)
t SCL = t CANsuppliedCLK × ( BRP + 1 )
(6)
t SJW = t SCL × ( SJW + 1 )
(7)
t SYNCSEG = t SCL
(8)
t TSEG1 = t SCL × ( TSEG1 + 1 )
(9)
t TSEG2 = t SCL × ( TSEG2 + 1 )
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Table 323. CAN Error Warning Limit register (CAN1EWL - address 0x4004 4018, CAN2EWL - address 0x4004 8018)
bit description
Bit Symbol Function Reset RM
Value Set
7:0 EWL During CAN operation, this value is compared to both the Tx and Rx Error Counters. If 9610 = 0x60 X
either of these counter matches this value, the Error Status (ES) bit in CANSR is set.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Note that a content change of the Error Warning Limit Register is possible only if the
Reset Mode was entered previously. An Error Status change (Status Register) and an
Error Warning Interrupt forced by the new register content will not occur until the Reset
Mode is cancelled again.
Table 324. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description
Bit Symbol Value Function Reset RM
Value Set
0 RBS Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. 0 0
1 DOS Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0
2 TBS1[1] Transmit Buffer Status 1. 1 1
0(locked) Software cannot access the Tx Buffer 1 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
1(released) Software may write a message into the Transmit Buffer 1 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
3 TCS1[2] Transmission Complete Status. 1 x
0(incomplete) The previously requested transmission for Tx Buffer 1 is not complete.
1(complete) The previously requested transmission for Tx Buffer 1 has been successfully
completed.
4 RS Receive Status. This bit is identical to the RS bit in the GSR. 1 0
5 TS1 Transmit Status 1. 1 0
0(idle) There is no transmission from Tx Buffer 1.
1(transmit) The CAN Controller is transmitting a message from Tx Buffer 1.
6 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0
7 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0
8 RBS Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. 0 0
9 DOS Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0
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Table 324. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description
Bit Symbol Value Function Reset RM
Value Set
10 TBS2[1] Transmit Buffer Status 2. 1 1
0(locked) Software cannot access the Tx Buffer 2 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
1(released) Software may write a message into the Transmit Buffer 2 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
11 TCS2[2] Transmission Complete Status. 1 x
0(incomplete) The previously requested transmission for Tx Buffer 2 is not complete.
1(complete) The previously requested transmission for Tx Buffer 2 has been successfully
completed.
12 RS Receive Status. This bit is identical to the RS bit in the GSR. 1 0
13 TS2 Transmit Status 2. 1 0
0(idle) There is no transmission from Tx Buffer 2.
1(transmit) The CAN Controller is transmitting a message from Tx Buffer 2.
14 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0
15 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0
16 RBS Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. 0 0
17 DOS Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0
18 TBS3[1] Transmit Buffer Status 3. 1 1
0(locked) Software cannot access the Tx Buffer 3 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
1(released) Software may write a message into the Transmit Buffer 3 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
19 TCS3[2] Transmission Complete Status. 1 x
0(incomplete) The previously requested transmission for Tx Buffer 3 is not complete.
1(complete) The previously requested transmission for Tx Buffer 3 has been successfully
completed.
20 RS Receive Status. This bit is identical to the RS bit in the GSR. 1 0
21 TS3 Transmit Status 3. 1 0
0(idle) There is no transmission from Tx Buffer 3.
1(transmit) The CAN Controller is transmitting a message from Tx Buffer 3.
22 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0
23 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0
31:24 - Reserved, the value read from a reserved bit is not defined. NA
[1] If the CPU tries to write to this Transmit Buffer when the Transmit Buffer Status bit is '0' (locked), the written byte is not accepted and is
lost without this being signalled.
[2] The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit
is set '1' for this TX buffer. The Transmission Complete Status bit remains '0' until a message is transmitted successfully.
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Table 325. CAN Receive Frame Status register (CAN1RFS - address 0x4004 4020, CAN2RFS - address 0x4004 8020)
bit description
Bit Symbol Function Reset RM
Value Set
9:0 ID Index If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry 0 X
at which the Acceptance Filter matched the received Identifier. Disabled entries in the
Standard tables are included in this numbering, but will not be matched. See Section 16.17
“Examples of acceptance filter tables and ID index values” on page 393 for examples of ID
Index values.
10 BP If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field 0 X
(above) is meaningless.
15:11 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
19:16 DLC The field contains the Data Length Code (DLC) field of the current received message. When 0 X
RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB
registers as follows:
0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes
With RTR = 1, this value indicates the number of data bytes requested to be sent back, with
the same encoding.
29:20 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
30 RTR This bit contains the Remote Transmission Request bit of the current received message. 0 0 X
indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA
and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC
value identifies the number of data bytes requested to be sent using the same Identifier.
31 FF A 0 in this bit indicates that the current received message included an 11-bit Identifier, while 0 X
a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described
below.
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Table 326. CAN Receive Identifier register (CAN1RID - address 0x4004 4024, CAN2RID - address 0x4004 8024) bit
description
Bit Symbol Function Reset Value RM Set
10:0 ID The 11-bit Identifier field of the current received message. In CAN 2.0A, these 0 X
bits are called ID10-0, while in CAN 2.0B they’re called ID29-18.
31:11 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
Table 328. CAN Receive Data register A (CAN1RDA - address 0x4004 4028, CAN2RDA - address 0x4004 8028) bit
description
Bit Symbol Function Reset Value RM Set
7:0 Data 1 If the DLC field in CANRFS ≥ 0001, this contains the first Data byte of the current 0 X
received message.
15:8 Data 2 If the DLC field in CANRFS ≥ 0010, this contains the first Data byte of the current 0 X
received message.
23:16 Data 3 If the DLC field in CANRFS ≥ 0011, this contains the first Data byte of the current 0 X
received message.
31:24 Data 4 If the DLC field in CANRFS ≥ 0100, this contains the first Data byte of the current 0 X
received message.
Table 329. CAN Receive Data register B (CAN1RDB - address 0x4004 402C, CAN2RDB - address 0x4004 802C) bit
description
Bit Symbol Function Reset Value RM Set
7:0 Data 5 If the DLC field in CANRFS ≥ 0101, this contains the first Data byte of the current 0 X
received message.
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Table 329. CAN Receive Data register B (CAN1RDB - address 0x4004 402C, CAN2RDB - address 0x4004 802C) bit
description
Bit Symbol Function Reset Value RM Set
15:8 Data 6 If the DLC field in CANRFS ≥ 0110, this contains the first Data byte of the current 0 X
received message.
23:16 Data 7 If the DLC field in CANRFS ≥ 0111, this contains the first Data byte of the current 0 X
received message.
31:24 Data 8 If the DLC field in CANRFS ≥ 1000, this contains the first Data byte of the current 0 X
received message.
The values for the reserved bits of the CANxTFI register in the Transmit Buffer should be
set to the values expected in the Receive Buffer for an easy comparison, when using the
Self Reception facility (self test), otherwise they are not defined.
The CAN Controller consist of three Transmit Buffers. Each of them has a length of 4
words and is able to store one complete CAN message as shown in Figure 54.
The buffer layout is subdivided into Descriptor and Data Field where the first word of the
Descriptor Field includes the TX Frame Info that describes the Frame Format, the Data
Length and whether it is a Remote or Data Frame. In addition, a TX Priority register allows
the definition of a certain priority for each transmit message. Depending on the chosen
Frame Format, an 11-bit identifier for Standard Frame Format (SFF) or an 29-bit identifier
for Extended Frame Format (EFF) follows. Note that unused bits in the TID field have to
be defined as 0. The Data Field in TDA and TDB contains up to eight data bytes.
Table 330. CAN Transmit Frame Information register (CAN1TFI[1/2/3] - address 0x4004 40[30/40/50], CAN2TFI[1/2/3] -
0x4004 80[30/40/50]) bit description
Bit Symbol Function Reset RM
Value Set
7:0 PRIO If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx x
Buffers contend for the right to send their messages based on this field. The buffer with the
lowest TX Priority value wins the prioritization and is sent first.
15:8 - Reserved. 0
19:16 DLC Data Length Code. This value is sent in the DLC field of the next transmit message. In 0 X
addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit
message, from the CANxTDA and CANxTDB registers:
0000-0111 = 0-7 bytes
1xxx = 8 bytes
29:20 - Reserved. 0
30 RTR This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of 0 X
data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers.
If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
31 FF If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame 0 X
format), while if it’s 1, the message will be sent with a 29-bit Identifier (extended frame
format).
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Tx DLC
The number of bytes in the Data Field of a message is coded with the Data Length Code
(DLC). At the start of a Remote Frame transmission the DLC is not considered due to the
RTR bit being '1 ' (remote). This forces the number of transmitted/received data bytes to
be 0. Nevertheless, the DLC must be specified correctly to avoid bus errors, if two CAN
Controllers start a Remote Frame transmission with the same identifier simultaneously.
For reasons of compatibility no DLC > 8 should be used. If a value greater than 8 is
selected, 8 bytes are transmitted in the data frame with the Data Length Code specified in
DLC. The range of the Data Byte Count is 0 to 8 bytes and is coded as follows:
(10)
DataByteCount = DLC
In Standard Frame Format messages, the CAN Identifier consists of 11 bits (ID.28 to
ID.18), and in Extended Frame Format messages, the CAN identifier consists of 29 bits
(ID.28 to ID.0). ID.28 is the most significant bit, and it is transmitted first on the bus during
the arbitration process. The Identifier acts as the message's name, used in a receiver for
acceptance filtering, and also determines the bus access priority during the arbitration
process.
Table 331. CAN Transfer Identifier register (CAN1TID[1/2/3] - address 0x4004 40[34/44/54], CAN2TID[1/2/3] - address
0x4004 80[34/44/54]) bit description
Bit Symbol Function Reset Value RM Set
10:0 ID The 11-bit Identifier to be sent in the next transmit message. 0 X
31:11 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
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Table 333. CAN Transmit Data register A (CAN1TDA[1/2/3] - address 0x4004 40[38/48/58], CAN2TDA[1/2/3] - address
0x4004 80[38/48/58]) bit description
Bit Symbol Function Reset Value RM Set
7:0 Data 1 If RTR = 0 and DLC ≥ 0001 in the corresponding CANxTFI, this byte is sent as 0 X
the first Data byte of the next transmit message.
15;8 Data 2 If RTR = 0 and DLC ≥ 0010 in the corresponding CANxTFI, this byte is sent as 0 X
the 2nd Data byte of the next transmit message.
23:16 Data 3 If RTR = 0 and DLC ≥ 0011 in the corresponding CANxTFI, this byte is sent as 0 X
the 3rd Data byte of the next transmit message.
31:24 Data 4 If RTR = 0 and DLC ≥ 0100 in the corresponding CANxTFI, this byte is sent as 0 X
the 4th Data byte of the next transmit message.
Table 334. CAN Transmit Data register B (CAN1TDB[1/2/3] - address 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - address
0x4004 80[3C/4C/5C]) bit description
Bit Symbol Function Reset Value RM Set
7:0 Data 5 If RTR = 0 and DLC ≥ 0101 in the corresponding CANTFI, this byte is sent as the 0 X
5th Data byte of the next transmit message.
15;8 Data 6 If RTR = 0 and DLC ≥ 0110 in the corresponding CANTFI, this byte is sent as the 0 X
6th Data byte of the next transmit message.
23:16 Data 7 If RTR = 0 and DLC ≥ 0111 in the corresponding CANTFI, this byte is sent as the 0 X
7th Data byte of the next transmit message.
31:24 Data 8 If RTR = 0 and DLC ≥ 1000 in the corresponding CANTFI, this byte is sent as the 0 X
8th Data byte of the next transmit message.
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Table 335. CAN Sleep Clear register (CANSLEEPCLR - address 0x400F C110) bit description
Bit Symbol Function Reset Value
0 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
1 CAN1SLEEP Sleep status and control for CAN channel 1. 0
Read: when 1, indicates that CAN channel 1 is in the sleep mode.
Write: writing a 1 causes clocks to be restored to CAN channel 1.
2 CAN2SLEEP Sleep status and control for CAN channel 2. 0
Read: when 1, indicates that CAN channel 2 is in the sleep mode.
Write: writing a 1 causes clocks to be restored to CAN channel 2.
31:3 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 336. CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description
Bit Symbol Function Reset Value
0 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
1 CAN1WAKE Wake-up status for CAN channel 1. 0
Read: when 1, indicates that a falling edge has occurred on the receive data line of
CAN channel 1.
Write: writing a 1 clears this bit.
2 CAN2WAKE Wake-up status for CAN channel 2. 0
Read: when 1, indicates that a falling edge has occurred on the receive data line of
CAN channel 2.
Write: writing a 1 clears this bit.
31:3 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
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recessive bits). Software can monitor this countdown by reading the Tx Error Counter.
When this countdown is complete, the CAN Controller clears BS and ES in CANxSR, and
sets EI in CANxSR if EIE in IER is 1.
The Tx and Rx error counters can be written if RM in CANxMOD is 1. Writing 255 to the
Tx Error Counter forces the CAN Controller to Bus-Off state. If Bus-Off (BS in CANxSR) is
1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When software
clears RM in CANxMOD thereafter, only one Bus Free condition (11 consecutive
recessive bits) is needed before operation resumes.
The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the
CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b)
software clearing SM in the CAN Mode register. A sleeping CAN Controller that wakes up
in response to bus activity is not able to receive an initial message until after it detects
Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is
active when software sets SM, the wake-up is immediate.
If the LPC17xx is in Deep Sleep or Power-down mode, CAN activity will wake up the
device if the CAN activity interrupt is enabled. See Section 4.8 “Power control”.
16.8.3 Interrupts
Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”.
The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each
Receive and Transmit interrupt request from each controller is assigned its own channel in
the NVIC, and can have its own interrupt service routine. The “other status” interrupts from
all of the CAN controllers, and the Acceptance Filter LUTerr condition, are ORed into one
NVIC channel.
The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it
sends each message.
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All Status registers are read-only and allow byte, half word and word access.
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A write access to all section configuration registers is only possible during the Acceptance
Filter Off and Bypass Mode. Read access is allowed in all Acceptance Filter Modes.
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It is recommended to use the ID ready Interrupt (ID Index) and the Receive Interrupt (RI).
In this mode all CAN message are accepted and stored in the Receive Buffers of active
CAN Controllers.
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If Standard (11-bit) Identifiers are used in the application, at least one of 3 tables in
Acceptance Filter RAM must not be empty. If the optional “FullCAN mode” is enabled, the
first table contains Standard identifiers for which reception is to be handled in this mode.
The next table contains individual Standard Identifiers and the third contains ranges of
Standard Identifiers, for which messages are to be received via the CAN Controllers. The
tables of FullCAN and individual Standard Identifiers must be arranged in ascending
numerical order, one per halfword, two per word. Since each CAN bus has its own
address map, each entry also contains the number of the CAN Controller (001-010) to
which it applies.
31 29 26 16
15 13 10 0
DIS NOT
CONTROLLER # IDENTIFIER
ABLE USED
The table of Standard Identifier Ranges contains paired upper and lower (inclusive)
bounds, one pair per word. These must also be arranged in ascending numerical order.
31 29 26 16 10 0
NOT USED
NOT USED
DISABLE
DISABLE
The disable bits in Standard entries provide a means to turn response, to particular CAN
Identifiers or ranges of Identifiers, on and off dynamically. When the Acceptance Filter
function is enabled, only the disable bits in Acceptance Filter RAM can be changed by
software. Response to a range of Standard addresses can be enabled by writing 32 zero
bits to its word in RAM, and turned off by writing 32 one bits (0xFFFF FFFF) to its word in
RAM. Only the disable bits are actually changed. Disabled entries must maintain the
ascending sequence of Identifiers.
If Extended (29-bit) Identifiers are used in the application, at least one of the other two
tables in Acceptance Filter RAM must not be empty, one for individual Extended Identifiers
and one for ranges of Extended Identifiers. The table of individual Extended Identifiers
must be arranged in ascending numerical order.
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31 29 28 0
CONTROLLER # IDENTIFIER
The table of ranges of Extended Identifiers must contain an even number of entries, of the
same form as in the individual Extended Identifier table. Like the Individual Extended
table, the Extended Range must be arranged in ascending numerical order. The first and
second (3rd and 4th …) entries in the table are implicitly paired as an inclusive range of
Extended addresses, such that any received address that falls in the inclusive range is
received (accepted). Software must maintain the table to consist of such word pairs.
Five address registers point to the boundaries between the tables in Acceptance Filter
RAM: FullCAN Standard addresses, Standard Individual addresses, Standard address
ranges, Extended Individual addresses, and Extended address ranges. These tables
must be consecutive in memory. The start of each of the latter four tables is implicitly the
end of the preceding table. The end of the Extended range table is given in an End of
Tables register. If the start address of a table equals the start of the next table or the End
Of Tables register, that table is empty.
When the Receive side of a CAN controller has received a complete Identifier, it signals
the Acceptance Filter of this fact. The Acceptance Filter responds to this signal, and reads
the Controller number, the size of the Identifier, and the Identifier itself from the Controller.
It then proceeds to search its RAM to determine whether the message should be received
or ignored.
If FullCAN mode is enabled and the CAN controller signals that the current message
contains a Standard identifier, the Acceptance Filter first searches the table of identifiers
for which reception is to be done in FullCAN mode. Otherwise, or if the AF doesn’t find a
match in the FullCAN table, it searches its individual Identifier table for the size of Identifier
signalled by the CAN controller. If it finds an equal match, the AF signals the CAN
controller to retain the message, and provides it with an ID Index value to store in its
Receive Frame Status register.
If the Acceptance Filter does not find a match in the appropriate individual Identifier table,
it then searches the Identifier Range table for the size of Identifier signalled by the CAN
controller. If the AF finds a match to a range in the table, it similarly signals the CAN
controller to retain the message, and provides it with an ID Index value to store in its
Receive Frame Status register. If the Acceptance Filter does not find a match in either the
individual or Range table for the size of Identifier received, it signals the CAN controller to
discard/ignore the received message.
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Table 342. Acceptance Filter Mode Register (AFMR - address 0x4003 C000) bit description
Bit Symbol Value Description Reset Value
0 AccOff[2] 1 if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN 1
buses are ignored.
1 AccBP[1] 1 All Rx messages are accepted on enabled CAN controllers. Software must set this 0
bit before modifying the contents of any of the registers described below, and
before modifying the contents of Lookup Table RAM in any way other than setting
or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff
are 0, the Acceptance filter operates to screen received CAN Identifiers.
2 eFCAN[3] 0 Software must read all messages for all enabled IDs on all enabled CAN buses, 0
from the receiving CAN controllers.
1 The Acceptance Filter itself will take care of receiving and storing messages for
selected Standard ID values on selected CAN buses. See Section 16.16 “FullCAN
mode” on page 382.
31:3 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
[1] Acceptance Filter Bypass Mode (AccBP): By setting the AccBP bit in the Acceptance Filter Mode Register,
the Acceptance filter is put into the Acceptance Filter Bypass mode. During bypass mode, the internal state
machine of the Acceptance Filter is reset and halted. All received CAN messages are accepted, and
acceptance filtering can be done by software.
[2] Acceptance Filter Off mode (AccOff): After power-up or hardware reset, the Acceptance filter will be in Off
mode, the AccOff bit in the Acceptance filter Mode register 0 will be set to 1. The internal state machine of
the acceptance filter is reset and halted. If not in Off mode, setting the AccOff bit, either by hardware or by
software, will force the acceptance filter into Off mode.
[3] FullCAN Mode Enhancements: A FullCAN mode for received CAN messages can be enabled by setting the
eFCAN bit in the acceptance filter mode register.
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[1] Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
[1] Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
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[1] Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
[1] Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
[1] Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
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information under which address during an ID screening an error in the look-up table was
encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up table
interrupt.
Table 350. Global FullCAN Enable register (FCANIE - address 0x4003 C020) bit description
Bit Symbol Description Reset Value
0 FCANIE Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. 0
31:1 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
16.14.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0x4003 C024 and
FCANIC1 - 0x4003 C028)
For detailed description on these two registers, see Section 16.16.2 “FullCAN interrupts”.
Table 351. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0x4003 C024) bit description
Bit Symbol Description Reset Value
0 IntPnd0 FullCan Interrupt Pending bit 0. 0
... IntPndx (0<x<31) FullCan Interrupt Pending bit x. 0
31 IntPnd31 FullCan Interrupt Pending bit 31. 0
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Table 352. FullCAN Interrupt and Capture register 1 (FCANIC1 - address 0x4003 C028) bit description
Bit Symbol Description Reset Value
0 IntPnd32 FullCan Interrupt Pending bit 32. 0
... IntPndx (32<x<63) FullCan Interrupt Pending bit x. 0
31 IntPnd63 FullCan Interrupt Pending bit 63. 0
SCC value equals CAN_controller - 1, i.e., SCC = 0 matches CAN1 and SCC = 1
matches CAN2.
Every CAN identifier is linked to an ID Index number. In case of a CAN Identifier match,
the matching ID Index is stored in the Identifier Index of the Frame Status Register
(CANRFS) of the according CAN Controller.
Note: Only activated sections will take part in the screening process.
In cases where equal message identifiers of same frame format are defined in more than
one section, the first match will end the screening process for this identifier.
For example, if the same Source CAN Channel in conjunction with the identifier is defined
in the FullCAN, the Explicit Standard Frame Format and the Group of Standard Frame
Format Identifier Sections, the screening will already be finished with the match in the
FullCAN section.
In the example of Figure 61, Identifiers with their Source CAN Channel have been defined
in the FullCAN, Explicit and Group of Standard Frame Format Identifier Sections. This
example corresponds part with 6 CAN controllers.
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Message Message
disable bit disable bit
Explicit
Index 8, 9 SCC = 1 0 ID = 0x5A SCC = 1 0 ...
Standard
Frame
Index 10, 11 SCC = 2 0 ... SCC = 3 0 ...
Format
Identifier
Index 12, 13 SCC = 4 0 ... SCC = 5 0 ...
Section
Group of
Index 14 SCC = 1 0 ID = 0x5A SCC = 1 0 ID = 0x5F
0x5A Standard
Frame
Index 15 SCC = 2 0 ... SCC = 2 0 ... Format
Identifier
Section
The identifier 0x5A of the CAN Controller 1 with the Source CAN Channel SCC = 1, is
defined in all three sections. With this configuration incoming CAN messages on CAN
Controller 1 with a 0x5A identifier will find a match in the FullCAN section.
It is possible to disable the ‘0x5A identifier’ in the FullCAN section. With that, the
screening process would be finished with the match in the Explicit Identifier Section.
The first group in the Group Identifier Section has been defined in that way, that incoming
CAN messages with identifiers of 0x5A up to 0x5F are accepted on CAN Controller 1 with
the Source CAN Channel SCC = 1. As stated above, the identifier 0x5A would find a
match already in the FullCAN or in the Explicit Identifier section if enabled. The rest of the
defined identifiers of this group (0x5B to 0x5F) will find a match in this Group Identifier
Section.
This way the user can switch dynamically between different filter modes for same
identifiers.
The concept of the CAN Gateway block is mainly based on a BasicCAN functionality. This
concept fits perfectly in systems where a gateway is used to transfer messages or
message data between different CAN channels. A BasicCAN device is generating a
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receive interrupt whenever a CAN message is accepted and received. Software has to
move the received message out of the receive buffer from the according CAN controller
into the user RAM.
To cover dashboard like applications where the controller typically receives data from
several CAN channels for further processing, the CAN Gateway block was extended by a
so-called FullCAN receive function. This additional feature uses an internal message
handler to move received FullCAN messages from the receive buffer of the according
CAN controller into the FullCAN message object data space of Look-up Table RAM.
When FullCAN mode is enabled, the Acceptance Filter itself takes care of receiving and
storing messages for selected Standard ID values on selected CAN buses, in the style of
“FullCAN” controllers.
In order to set this bit and use this mode, two other conditions must be met with respect to
the contents of Acceptance Filter RAM and the pointers into it:
• The Standard Frame Individual Start Address Register (SFF_sa) must be greater than
or equal to the number of IDs for which automatic receive storage is to be done, times
two. SFF_sa must be rounded up to a multiple of 4 if necessary.
• The EndOfTable register must be less than or equal to 0x800 minus 6 times the
SFF_sa value, to allow 12 bytes of message storage for each ID for which automatic
receive storage will be done.
• The area between the start of Acceptance Filter RAM and the SFF_sa address, is
used for a table of individual Standard IDs and CAN Controller/bus identification,
sorted in ascending order and in the same format as in the Individual Standard ID
table (see Figure 58 “Entry in FullCAN and individual standard identifier tables” on
page 375). Entries can be marked as “disabled” as in the other Standard tables. If
there are an odd number of “FullCAN” ID’s, at least one entry in this table must be so
marked.
• The first (SFF_sa)/2 IDindex values are assigned to these automatically-stored ID’s.
That is, IDindex values stored in the Rx Frame Status Register, for IDs not handled in
this way, are increased by (SFF_sa)/2 compared to the values they would have when
eFCAN is 0.
• When a Standard ID is received, the Acceptance Filter searches this table before the
Standard Individual and Group tables.
• When a message is received for a controller and ID in this table, the Acceptance filter
reads the received message out of the CAN controller and stores it in Acceptance
Filter RAM, starting at (EndOfTable) + its IDindex*12.
• The format of such messages is shown in Table 353.
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The FF, RTR, and DLC fields are as described in Table 325.
Since the FullCAN message object section of the Look-up table RAM can be accessed
both by the Acceptance Filter and the CPU, there is a method for insuring that no CPU
reads from FullCAN message object occurs while the Acceptance Filter hardware is
writing to that object.
For this purpose the Acceptance Filter uses a 3-state semaphore, encoded with the two
semaphore bits SEM1 and SEM0 (see Table 353 “Format of automatically stored Rx
messages”) for each message object. This mechanism provides the CPU with information
about the current state of the Acceptance Filter activity in the FullCAN message object
section.
Prior to writing the first data byte into a message object, the Acceptance Filter will write
the FrameInfo byte into the according buffer location with SEM[1:0] = 01.
After having written the last data byte into the message object, the Acceptance Filter will
update the semaphore bits by setting SEM[1:0] = 11.
Before reading a message object, the CPU should read SEM[1:0] to determine the current
state of the Acceptance Filter activity therein. If SEM[1:0] = 01, then the Acceptance Filter
is currently active in this message object. If SEM[1:0] = 11, then the message object is
available to be read.
Before the CPU begins reading from the message object, it should clear SEM[1:0] = 00.
When the CPU is finished reading, it can check SEM[1:0] again. At the time of this final
check, if SEM[1:0] = 01 or 11, then the Acceptance Filter has updated the message object
during the time when the CPU reads were taking place, and the CPU should discard the
data. If, on the other hand, SEM[1:0] = 00 as expected, then valid data has been
successfully read by the CPU.
Figure 62 shows how software should use the SEM field to ensure that all three words
read from the message are all from the same received message.
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START
SEM == 01?
SEM == 00?
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The FullCAN Interrupt Register-set contains interrupt flags (IntPndx) for (pending)
FullCAN receive interrupts. As soon as a FullCAN message is received, the according
interrupt bit (IntPndx) in the FCAN Interrupt Register gets asserted. In case that the Global
FullCAN Interrupt Enable bit is set, the FullCAN Receive Interrupt is passed to the
Vectored Interrupt Controller.
1. Index/Object number calculation based on the bit position in the FCANIC Interrupt
Register for more than one pending interrupt.
2. Interrupt priority handling if more than one FullCAN receive interrupt is pending.
The software that covers the interrupt priority handling has to assign a receive interrupt
priority to every FullCAN object. If more than one interrupt is pending, then the software
has to decide, which received FullCAN object has to be served next.
To each FullCAN object a new FullCAN Interrupt Enable bit (FCANIntxEn) is added, so
that it is possible to enable or disable FullCAN interrupts for each object individually. The
new Message Lost flag (MsgLstx) is introduced to indicate whether more than one
FullCAN message has been received since last time this message object was read by the
CPU. The Interrupt Enable and the Message Lost bits reside in the existing Look-up Table
RAM.
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Message Message
disable bit disable bit
3 2 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
New: New:
FullCAN FullCAN
Message Message
Interrupt Interrupt
enable bit enable bit
New: New:
FullCAN CAN
Message Source
lost bit Channel
APB 31 24 23 16 15 10 9 8 7 0
Base +
R S S
F T
E E un- ID.2 ID.1
Msg_ObjAddr + 0 unused M M unused RX DLC SCC ............................
R used 8 8
F 1 0
The new message lost bit (MsgLst) is introduced to indicate whether more than one
FullCAN message has been received since last time this message object was read. For
more information the CAN Source Channel (SCC) of the received FullCAN message is
added to Message Object.
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During the last write access from the data storage of a FullCAN message object the
interrupt pending bit of a FullCAN object (IntPndx) gets asserted.
16.16.2.5 Setting the message lost bit of a FullCAN message object (MsgLost 63 to 0)
The Message Lost bit of a FullCAN message object gets asserted in case of an accepted
FullCAN message and when the FullCAN Interrupt of the same object is asserted already.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets asserted if the interrupt pending bit
is set already.
16.16.2.6 Clearing the message lost bit of a FullCAN message object (MsgLost 63 to
0)
The Message Lost bit of a FullCAN message object gets cleared when the FullCAN
Interrupt of the same object is not asserted.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets cleared if the interrupt pending bit
is not set.
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semaphore
01 11 00
bits
IntPndx
look-up Write write write write read clear read read read
ID, SEM D1 D2 SEM SEM SEM D1 D2 SEM
table
access
MsgLostx
message ARM
handler processor
access access
semaphore 01 11 00 01 11 11
bits
IntPndx
MsgLostx
message ARM
handler processor
access access
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semaphore 01 11 00 01 11 00
bits
IntPndx
MsgLostx
message ARM
handler processor
access access
16.16.3.4 Scenario 3.1: Message gets overwritten indicated by Semaphore bits and
Message Lost
This scenario is a sub-case to Scenario 3 in which the lost message is indicated by the
existing semaphore bits and by Message Lost.
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semaphore 01 11 00 01 11 00
bits
IntPndx
write write
look-up write write write read clear write write write read read read clear read read read
ID, ID,
table D1 D2 SEM SEM SEM D1 D2 SEM D1 D2 SEM SEM D1 D2 SEM
SEM SEM
access 1st Object 2nd Object
write write
1st Object read 2nd Object
read
Interrupt Service
Routine
MsgLostx
message ARM
handler processor
access access
Fig 68. Message overwritten indicated by semaphore bits and message lost
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semaphore 01 11 01 11 00 01 11
bits
IntPndx
MsgLostx
message ARM
handler processor
access access
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semaphore 01 11 01 11 00 11
bits
IntPndx
MsgLostx
message ARM
handler processor
access access
The start address of a section is lower than the end address of all programmed CAN
identifiers.
In cases of a section not being used, the start address has to be set onto the value of the
next section start address.
16.17.3 Example 3: more than one but not all sections are used
If the SFF group is not used, the start address of the SFF Group Section (SFF_GRP_sa
register) has to be set to the same value of the next section start address, in this case the
start address of the Explicit SFF Section (SFF_sa register).
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In cases where explicit identifiers as well as groups of the identifiers are programmed, a
CAN identifier search has to start in the explicit identifier section first. If no match is found,
it continues the search in the group of identifier section. By this order it can be guaranteed
that in case where an explicit identifier match is found, the succeeding software can
directly proceed on this certain message whereas in case of a group of identifier match
the succeeding software needs more steps to identify the message.
• A Standard Individual table starting at the start of Acceptance Filter RAM and
containing 26 Identifiers, followed by:
• A Standard Group table containing 12 ranges of Identifiers, followed by:
• An Extended Individual table containing 3 Identifiers, followed by:
• An Extended Group table containing 2 ranges of Identifiers.
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APB base +
column_lower column_upper
address
0
00d = 00h 0 1
1
04d = 04h 2
2 3
22
44d = 2Ch 22 23
23
24
48d = 30h 24 25
25
2 6 26 d
52d = 34h
38 38 d
lower_boundary 41 41 d
112d = 70h
group EFF table
Fig 71. Detailed example of acceptance filter tables and ID index values
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Explicit extended frame format identifier section (29-bit CAN ID, Figure 72)
The start address of the Explicit Extended Frame Format section is defined with the
EFF_sa register with the value of 0x20. The end of this section is defined with the
EFF_GRP_sa register. In the explicit Extended Frame Format section only one CAN
Identifier with its Source CAN Channel (SCC) is programmed per address line. To provide
memory space for four Explicit Extended Frame Format identifiers, the EFF_GRP_sa
register value is set to 0x30.
Group of extended frame format identifier section (29-bit CAN ID, Figure 72)
The start address of the Group of Extended Frame Format is defined with the
EFF_GRP_sa register with the value of 0x30. The end of this section is defined with the
End of Table address register (ENDofTable). In the Group of Extended Frame Format
section the boundaries are programmed with a pair of address lines; the first is the lower
boundary, the second the upper boundary. To provide memory space for two Groups of
Extended Frame Format Identifiers, the ENDofTable register value is set to 0x40.
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Message Message
disable bit disable bit
Index
ENDofTable
= 0x40
This example uses a typical configuration in which FullCAN as well as Explicit Standard
Frame Format messages are defined. As described in Section 16.15.1 “Acceptance filter
search algorithm”, acceptance filtering takes place in a certain order. With the enabled
FullCAN section, the identifier screening process of the acceptance filter starts always in
the FullCAN section first, before it continues with the rest of enabled sections.e disabled.
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FullCAN explicit standard frame format identifier section (11-bit CAN ID)
The start address of the FullCAN Explicit Standard Frame Format Identifier section is
(automatically) set to 0x00. The end of this section is defined in the SFF_sa register. In the
FullCAN ID section only identifiers of FullCAN Object are stored for acceptance filtering.
In this section two CAN Identifiers with their Source CAN Channels (SCC) share one
32-bit word. Not used or disabled CAN Identifiers can be marked by setting the message
disable bit. The FullCAN Object data for each defined identifier can be found in the
FullCAN Message Object section. In case of an identifier match during the acceptance
filter process, the received FullCAN message object data is moved from the Receive
Buffer of the appropriate CAN Controller into the FullCAN Message Object section. To
provide memory space for eight FullCAN, Explicit Standard Frame Format identifiers, the
SFF_sa register value is set to 0x10. The identifier with the Index 1 of this section is not
used and therefore disabled.
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MSB LSB
FullCAN SCC 0 0 0 SCC 1 1 MSB Disabled, 1 LSB
ID28 ID18 ID28 ID18
Explicit
0 1
MSB LSB 0 0 MSB LSB
Standard SCC ID28 2 ID18 SCC ID28 3 ID18
Frame
0 1
MSB LSB 0 0
MSB LSB
... Format SCC ID28 4 ID18 SCC 5 ID18
ID28
Identifier
0 1
MSB LSB 0 0
MSB LSB
Section SCC ID28 6 ID18 SCC ID28 7 ID18
SFF_sa MSB LSB MSB LSB
SCC 0 0 8 SCC 0 0 9
= 0x10 ID28 ID18 ID28 ID18
Explicit
Standard 0 0
MSB LSB 0 0
MSB LSB
SCC ID28 10 ID18 SCC ID28 11 ID18
Frame
MSB LSB MSB LSB
...Format SCC 0 0 12 SCC 0 0 13
ID28 ID18 ID28 ID18
Identifier
MSB LSB MSB LSB
Section SCC 0 0 14 SCC 0 0 15
ID28 ID18 ID28 ID18
ENDofTable =
FF RTR SEM DLC CAN-ID
SFF_GRP_sa =
EFF_sa = FullCAN Message Object
RXDATA 4, 3, 2, 1
EFF_GRP_sa = Data 0
Message
0x20
Object RXDATA 8, 7, 6, 5
section
Section No Message Data, disabled.
Message Object
No Message Data, disabled.
Data 1
No Message Data, disabled.
Fig 73. ID Look-up table configuration example (FullCAN activated and enabled)
SCC value equals CAN_controller - 1, i.e., SCC = 0 matches CAN1 and SCC = 1
matches CAN2.
In cases, where a syntax error in the ID Look-up Table is encountered, the Look-up Table
address of the incorrect line is made available in the Look-up Table Error Address
Register (LUTerrAd).
The reporting process in the Look-up Table Error Address Register (LUTerrAd) is a
“run-time” process. Only those address lines with syntax error are reported, which were
passed through the acceptance filtering process.
The following general rules for programming the Look-up Table apply:
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• Each section has to be organized as a sorted list or table with an increasing order of
the Source CAN Channel (SCC) in conjunction with the CAN Identifier (there is no
exception for disabled identifiers).
• The upper and lower bound in a Group of Identifiers definition has to be from the
same Source CAN Channel.
• To disable a Group of Identifiers the message disable bit has to be set for both, the
upper and lower bound.
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Remark: SSP0 is intended to be used as an alternative for the SPI interface, which is
included as a legacy peripheral. Only one of these peripherals can be used at the any one
time.
17.2 Features
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex Communication.
• SPI master or slave.
• Maximum data bit rate of one eighth of the peripheral clock rate.
• 8 to 16 bits per transfer.
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In the first part of the timing diagram, note two points. First, the SPI is illustrated with the
Clock Polarity control bit (CPOL) in the SPI Control Register set to both 0 and 1. The
second point to note is the activation and de-activation of the SSEL signal. When
CPHA = 0, the SSEL signal will always go inactive between data transfers. This is not
guaranteed when CPHA = 1 (the signal can remain active).
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SCK (CPOL = 0)
SCK (CPOL = 1)
SSEL
CPHA = 0
Cycle # CPHA = 0 1 2 3 4 5 6 7 8
MOSI (CPHA = 0) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
MISO (CPHA = 0) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
CPHA = 1
Cycle # CPHA = 1 1 2 3 4 5 6 7 8
MOSI (CPHA = 1) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
MISO (CPHA = 1) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
The data and clock phase relationships are summarized in Table 359.
The definition of when a transfer starts and stops is dependent on whether a device is a
master or a slave, and the setting of the CPHA variable.
When a device is a master, the start of a transfer is indicated by the master having a byte
of data that is ready to be transmitted. At this point, the master can activate the clock, and
begin the transfer. The transfer ends when the last clock cycle of the transfer is complete.
When a device is a slave and CPHA is set to 0, the transfer starts when the SSEL signal
goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is
set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on
the last clock edge where data is sampled.
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The SPI Control Register (S0SPCR) contains a number of programmable bits used to
control the function of the SPI block. The settings for this register must be set up prior to a
given data transfer taking place.
The SPI Status Register (S0SPSR) contains read-only bits that are used to monitor the
status of the SPI interface, including normal functions, and exception conditions. The
primary purpose of this register is to detect completion of a data transfer. This is indicated
by the SPI Interrupt Flag (SPIF) in the S0SPINT register. The remaining bits in the register
are exception condition indicators. These exceptions will be described later in this section.
The SPI Data Register (S0SPDR) is used to provide the transmit and receive data bytes.
An internal shift register in the SPI block logic is used for the actual transmission and
reception of the serial data. Data is written to the SPI Data Register for the transmit case.
There is no buffer between the data register and the internal shift register. A write to the
data register goes directly into the internal shift register. Therefore, data should only be
written to this register when a transmit is not currently in progress. Read data is buffered.
When a transfer is complete, the receive data is transferred to a single byte data buffer,
where it is later read. A read of the SPI Data Register returns the value of the read data
buffer.
The SPI Clock Counter Register (S0SPCCR) controls the clock rate when the SPI block is
in master mode. This needs to be set prior to a transfer taking place, when the SPI block
is a master. This register has no function when the SPI block is a slave.
Prior to use, SPI configurations such as the master/slave settings, clock polarity, clock
rate, etc. must be set up in the SPI Control Register and SPI Clock Counter Register.
The I/Os for this implementation of SPI are standard CMOS I/Os. The open drain SPI
option is not implemented in this design. When a device is set up to be a slave, its I/Os are
only active when it is selected by the SSEL signal being active.
1. Set the SPI Clock Counter Register to the desired clock rate.
2. Set the SPI Control Register to the desired settings for master mode.
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be the master. This process assumes that any prior data transfer
has already completed.
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3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set
after the last cycle of the SPI data transfer.
4. Read the SPI Status Register.
5. Read the received data from the SPI Data Register (optional).
6. Go to step 2 if more data is to be transmitted.
Note: A read or write of the SPI Data Register is required in order to clear the SPIF status
bit. Therefore, if the optional read of the SPI Data Register does not take place, a write to
this register is required in order to clear the SPIF status bit.
1. Set the SPI Control Register to the desired settings for slave mode.
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be a slave. This process assumes that any prior data transfer
has already completed. It is required that the system clock driving the SPI logic be at least
8X faster than the SPI.
Note: A read or write of the SPI Data Register is required in order to clear the SPIF status
bit. Therefore, at least one of the optional reads or writes of the SPI Data Register must
take place, in order to clear the SPIF status bit.
A read overrun occurs when the SPI block internal read buffer contains data that has not
been read by the processor, and a new transfer has completed. The read buffer
containing valid data is indicated by the SPIF bit in the SPI Interrupt Register being active.
When a transfer completes, the SPI block needs to move the received data to the read
buffer. If the SPIF bit is active (the read buffer is full), the new receive data will be lost, and
the read overrun (ROVR) bit in the SPI Status Register will be activated.
Write Collision
As stated previously, there is no write buffer between the SPI block bus interface, and the
internal shift register. As a result, data must not be written to the SPI Data Register when
a SPI data transfer is currently in progress. The time frame where data cannot be written
to the SPI Data Register is from when the transfer starts, until after the SPI Status
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Register has been read when the SPIF status is active. If the SPI Data Register is written
in this time frame, the write data will be lost, and the write collision (WCOL) bit in the SPI
Status Register will be activated.
Mode Fault
If the SSEL signal goes active when the SPI block is a master, this indicates another
master has selected the device to be a slave. This condition is known as a mode fault.
When a mode fault is detected, the mode fault (MODF) bit in the SPI Status Register will
be activated, the SPI signal drivers will be de-activated, and the SPI mode will be changed
to be a slave.
If the SSEL function is assigned to its related pin in the relevant Pin Function Select
Register, the SSEL signal must always be inactive when the SPI controller is a master.
Slave Abort
A slave transfer is considered to be aborted if the SSEL signal goes inactive before the
transfer is complete. In the event of a slave abort, the transmit and receive data for the
transfer that was in progress are lost, and the slave abort (ABRT) bit in the SPI Status
Register will be activated.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
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Table 361: SPI Control Register (S0SPCR - address 0x4002 0000) bit description
Bit Symbol Value Description Reset
Value
1:0 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
2 BitEnable 0 The SPI controller sends and receives 8 bits of data per 0
transfer.
1 The SPI controller sends and receives the number of bits
selected by bits 11:8.
3 CPHA Clock phase control determines the relationship between the 0
data and the clock on SPI transfers, and controls when a slave
transfer is defined as starting and ending.
0 Data is sampled on the first clock edge of SCK. A transfer starts
and ends with activation and deactivation of the SSEL signal.
1 Data is sampled on the second clock edge of the SCK. A
transfer starts with the first clock edge, and ends with the last
sampling edge when the SSEL signal is active.
4 CPOL Clock polarity control. 0
0 SCK is active high.
1 SCK is active low.
5 MSTR Master mode select. 0
0 The SPI operates in Slave mode.
1 The SPI operates in Master mode.
6 LSBF LSB First controls which direction each byte is shifted when 0
transferred.
0 SPI data is transferred MSB (bit 7) first.
1 SPI data is transferred LSB (bit 0) first.
7 SPIE Serial peripheral interrupt enable. 0
0 SPI interrupts are inhibited.
1 A hardware interrupt is generated each time the SPIF or MODF
bits are activated.
11:8 BITS When bit 2 of this register is 1, this field controls the number of 0000
bits per transfer:
1000 8 bits per transfer
1001 9 bits per transfer
1010 10 bits per transfer
1011 11 bits per transfer
1100 12 bits per transfer
1101 13 bits per transfer
1110 14 bits per transfer
1111 15 bits per transfer
0000 16 bits per transfer
31:12 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
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Table 362: SPI Status Register (S0SPSR - address 0x4002 0004) bit description
Bit Symbol Description Reset
Value
2:0 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
3 ABRT Slave abort. When 1, this bit indicates that a slave abort has occurred. 0
This bit is cleared by reading this register.
4 MODF Mode fault. when 1, this bit indicates that a Mode fault error has 0
occurred. This bit is cleared by reading this register, then writing the
SPI0 control register.
5 ROVR Read overrun. When 1, this bit indicates that a read overrun has 0
occurred. This bit is cleared by reading this register.
6 WCOL Write collision. When 1, this bit indicates that a write collision has 0
occurred. This bit is cleared by reading this register, then accessing the
SPI Data Register.
7 SPIF SPI transfer complete flag. When 1, this bit indicates when a SPI data 0
transfer is complete. When a master, this bit is set at the end of the last
cycle of the transfer. When a slave, this bit is set on the last data
sampling edge of the SCK. This bit is cleared by first reading this
register, then accessing the SPI Data Register.
Note: this is not the SPI interrupt flag. This flag is found in the SPINT
register.
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 363: SPI Data Register (S0SPDR - address 0x4002 0008) bit description
Bit Symbol Description Reset
Value
7:0 DataLow SPI Bi-directional data port. 0x00
15:8 DataHigh If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all 0x00
of these bits contain the additional transmit and receive bits. When less
than 16 bits are selected, the more significant among these bits read
as zeroes.
31:16 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
In Master mode, this register must be an even number greater than or equal to 8.
Violations of this can result in unpredictable behavior. The SPI0 SCK rate may be
calculated as: PCLK_SPI / SPCCR0 value. The SPI peripheral clock is determined by the
PCLKSEL0 register contents for PCLK_SPI as described in Section 4.7.3.
In Slave mode, the SPI clock rate provided by the master must not exceed 1/8 of the SPI
peripheral clock selected in Section 4.7.3. The content of the S0SPCCR register is not
relevant.
Table 364: SPI Clock Counter Register (S0SPCCR - address 0x4002 000C) bit description
Bit Symbol Description Reset
Value
7:0 Counter SPI0 Clock counter setting. 0x00
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 365: SPI Test Control Register (SPTCR - address 0x4002 0010) bit description
Bit Symbol Description Reset
Value
0 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
7:1 Test SPI test mode. When 0, the SPI operates normally. When 1, SCK will 0
always be on, independent of master mode select, and data availability
setting.
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
This register is a replication of the SPI Status Register. The difference between the
registers is that a read of this register will not start the sequence of events required to
clear these status bits. A write to this register will set an interrupt if the write data for the
respective bit is a 1.
Table 366: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description
Bit Symbol Description Reset
Value
2:0 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
3 ABRT Slave abort. 0
4 MODF Mode fault. 0
5 ROVR Read overrun. 0
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Table 366: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description
Bit Symbol Description Reset
Value
6 WCOL Write collision. 0
7 SPIF SPI transfer complete flag. 0
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 367: SPI Interrupt Register (S0SPINT - address 0x4002 001C) bit description
Bit Symbol Description Reset
Value
0 SPIF SPI interrupt flag. Set by the SPI interface to generate an interrupt. 0
Cleared by writing a 1 to this bit.
Note: this bit will be set once when SPIE = 1 and at least one of SPIF
and WCOL bits is 1. However, only when the SPI Interrupt bit is set and
SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be
processed by interrupt handling software.
7:1 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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17.8 Architecture
The block diagram of the SPI solution implemented in SPI0 interface is shown in the
Figure 75.
MOSI_IN
MOSI_OUT
MISO_IN
MISO_OUT
SCK_IN
SCK_OUT
SS_IN
SPI CLOCK
GENERATOR &
SPI Interrupt DETECTOR
SPI REGISTER
APB Bus INTERFACE
SCK_OUT_EN
MOSI_OUT_EN
MISO_OUT_EN
OUTPUT
ENABLE
LOGIC
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1. Power: In the PCONP register (Table 46), set bit PCSSP0 to enable SSP0 and bit
PCSSP1 to enable SSP1.
Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1).
2. Clock: In PCLKSEL0 select PCLK_SSP1; in PCLKSEL1 select PCLK_SSP0 (see
Section 4.7.3. In master mode, the clock must be scaled down (see Section 18.6.5).
3. Pins: Select the SSP pins through the PINSEL registers (Section 8.5) and pin modes
through the PINMODE registers (Section 8.4).
4. Interrupts: Interrupts are enabled in the SSP0IMSC register for SSP0 and SSP1IMSC
register for SSP1 Table 375. Interrupts are enabled in the NVIC using the appropriate
Interrupt Set Enable register, see Table 50.
5. Initialization: There are two control registers for each of the SSP ports to be
configured: SSP0CR0 and SSP0CR1 for SSP0, SSP1CR0 and SSP1CR1 for SSP1.
See Section 18.6.1 and Section 18.6.2.
6. DMA: The Rx and Tx FIFOs of the SSP interfaces can be connected to the GPDMA
controller (see Section 18.6.10). For GPDMA system connections, see Table 543.
Remark: SSP0 is intended to be used as an alternative for the SPI interface, which is
included as a legacy peripheral. Only one of these peripherals can be used at the any one
time.
18.2 Features
• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
• Synchronous Serial Communication.
• Master or slave operation.
• 8 frame FIFOs for both transmit and receive.
• 4 to 16 bit data frame.
• DMA transfers supported by GPDMA.
18.3 Description
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
The LPC17xx has two Synchronous Serial Port controllers -- SSP0 and SSP1.
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CLK
FS
DX/DR MSB LSB
4 to 16 bits
CLK
FS
DX/DR MSB LSB MSB LSB
4 to 16 bits 4 to 16 bits
For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of the
transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be
transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each CLK. The received data is transferred from the serial
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.
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The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing a
clock transition before the first data capture edge. When the CPHA phase control bit is 0,
data is captured on the first clock edge transition. If the CPHA clock phase control bit is 1,
data is captured on the second clock edge transition.
SCK
SSEL
MSB LSB
MOSI
4 to 16 bits
SCK
SSEL
4 to 16 bits 4 to 16 bits
One half SCK period later, valid master data is transferred to the MOSI pin. Now that both
the master and slave data have been set, the SCK master clock pin goes HIGH after one
further half SCK period.
The data is now captured on the rising and propagated on the falling edges of the SCK
signal.
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In the case of a single word transmission, after all bits of the data word have been
transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last
bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.
SCK
SSEL
MSB LSB
MOSI
MISO Q MSB LSB Q
4 to 16 bits
Data is then captured on the falling edges and propagated on the rising edges of the SCK
signal.
In the case of a single word transfer, after all bits have been transferred, the SSEL line is
returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transfers, the SSEL pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
SCK
SSEL
MSB LSB
MOSI
4 to 16 bits
SCK
SSEL
4 to 16 bits 4 to 16 bits
One half period later, valid master data is transferred to the MOSI line. Now that both the
master and slave data have been set, the SCK master clock pin becomes LOW after one
further half SCK period. This means that data is captured on the falling edges and be
propagated on the rising edges of the SCK signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SSEL line is returned to its idle HIGH state one SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.
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SCK
SSEL
MSB LSB
MOSI
MISO Q MSB LSB Q
4 to 16 bits
After all bits have been transferred, in the case of a single word transmission, the SSEL
line is returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transmissions, the SSEL pins remains in its active LOW
state, until the final bit of the last word has been captured, and then returns to its idle state
as described above. In general, for continuous back-to-back transfers the SSEL pin is
held LOW between successive data words and termination is the same as that of the
single word transfer.
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SK
CS
MSB LSB
SO
8-bit control
SI 0 MSB LSB
4 to 16 bits
output data
Microwire format is very similar to SPI format, except that transmission is half-duplex
instead of full-duplex, using a master-slave message passing technique. Each serial
transmission begins with an 8-bit control word that is transmitted from the SSP to the
off-chip slave device. During this transmission, no incoming data is received by the SSP.
After the message has been sent, the off-chip slave decodes it and, after waiting one
serial clock after the last bit of the 8-bit control message has been sent, responds with the
required data. The returned data is 4 to 16 bits in length, making the total frame length
anywhere from 13 to 25 bits.
The off-chip serial slave device latches each control bit into its serial shifter on the rising
edge of each SK. After the last bit is latched by the slave device, the control byte is
decoded during a one clock wait-state, and the slave responds by transmitting data back
to the SSP. Each bit is driven onto SI line on the falling edge of SK. The SSP in turn
latches each bit on the rising edge of SK. At the end of the frame, for single transfers, the
CS signal is pulled HIGH one clock period after the last bit has been latched in the receive
serial shifter, that causes the data to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of
SK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH.
For continuous transfers, data transmission begins and ends in the same manner as a
single transfer. However, the CS line is continuously asserted (held LOW) and
transmission of data occurs back to back. The control byte of the next frame follows
directly after the LSB of the received data from the current frame. Each of the received
values is transferred from the receive shifter on the falling edge SK, after the LSB of the
frame has been latched into the SSP.
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SK
CS
4 to 16 bits 4 to 16 bits
output data output data
Figure 83 illustrates these setup and hold time requirements. With respect to the SK rising
edge on which the first bit of receive data is to be sampled by the SSP slave, CS must
have a setup of at least two times the period of SK on which the SSP operates. With
respect to the SK rising edge previous to this edge, CS must have a hold of at least one
SK period.
tSETUP=2*tSK
t HOLD= tSK
SK
CS
SI
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[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
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Table 370: SSPn Control Register 0 (SSP0CR0 - address 0x4008 8000, SSP1CR0 -
0x4003 0000) bit description
Bit Symbol Value Description Reset
Value
3:0 DSS Data Size Select. This field controls the number of bits 0000
transferred in each frame. Values 0000-0010 are not supported
and should not be used.
0011 4-bit transfer
0100 5-bit transfer
0101 6-bit transfer
0110 7-bit transfer
0111 8-bit transfer
1000 9-bit transfer
1001 10-bit transfer
1010 11-bit transfer
1011 12-bit transfer
1100 13-bit transfer
1101 14-bit transfer
1110 15-bit transfer
1111 16-bit transfer
5:4 FRF Frame Format. 00
00 SPI
01 TI
10 Microwire
11 This combination is not supported and should not be used.
6 CPOL Clock Out Polarity. This bit is only used in SPI mode. 0
0 SSP controller maintains the bus clock low between frames.
1 SSP controller maintains the bus clock high between frames.
7 CPHA Clock Out Phase. This bit is only used in SPI mode. 0
0 SSP controller captures serial data on the first clock transition of
the frame, that is, the transition away from the inter-frame state
of the clock line.
1 SSP controller captures serial data on the second clock transition
of the frame, that is, the transition back to the inter-frame state of
the clock line.
15:8 SCR Serial Clock Rate. The number of prescaler-output clocks per bit 0x00
on the bus, minus one. Given that CPSDVSR is the prescale
divider, and the APB clock PCLK clocks the prescaler, the bit
frequency is PCLK / (CPSDVSR × [SCR+1]).
31:8 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
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Table 371: SSPn Control Register 1 (SSP0CR1 - address 0x4008 8004, SSP1CR1 -
0x4003 0004) bit description
Bit Symbol Value Description Reset
Value
0 LBM Loop Back Mode. 0
0 During normal operation.
1 Serial input is taken from the serial output (MOSI or MISO) rather
than the serial input pin (MISO or MOSI respectively).
1 SSE SSP Enable. 0
0 The SSP controller is disabled.
1 The SSP controller will interact with other devices on the serial
bus. Software should write the appropriate control information to
the other SSP registers and interrupt controller registers, before
setting this bit.
2 MS Master/Slave Mode.This bit can only be written when the SSE bit 0
is 0.
0 The SSP controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
1 The SSP controller acts as a slave on the bus, driving MISO line
and receiving SCLK, MOSI, and SSEL lines.
3 SOD Slave Output Disable. This bit is relevant only in slave mode 0
(MS = 1). If it is 1, this blocks this SSP controller from driving the
transmit data line (MISO).
31:4 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
18.6.3 SSPn Data Register (SSP0DR - 0x4008 8008, SSP1DR - 0x4003 0008)
Software can write data to be transmitted to this register, and read data that has been
received.
Table 372: SSPn Data Register (SSP0DR - address 0x4008 8008, SSP1DR - 0x4003 0008) bit
description
Bit Symbol Description Reset
Value
15:0 DATA Write: software can write data to be sent in a future frame to this 0x0000
register whenever the TNF bit in the Status register is 1, indicating that
the Tx FIFO is not full. If the Tx FIFO was previously empty and the
SSP controller is not busy on the bus, transmission of the data will
begin immediately. Otherwise the data written to this register will be
sent as soon as all previous data has been sent (and received). If the
data length is less than 16 bits, software must right-justify the data
written to this register.
Read: software can read data from this register whenever the RNE bit
in the Status register is 1, indicating that the Rx FIFO is not empty.
When software reads this register, the SSP controller returns data from
the least recent frame in the Rx FIFO. If the data length is less than 16
bits, the data is right-justified in this field with higher order bits filled with
0s.
31:16 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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Table 373: SSPn Status Register (SSP0SR - address 0x4008 800C, SSP1SR - 0x4003 000C)
bit description
Bit Symbol Description Reset
Value
0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1
1 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
2 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if 0
not.
3 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. 0
4 BSY Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently 0
sending/receiving a frame and/or the Tx FIFO is not empty.
31:5 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 374: SSPn Clock Prescale Register (SSP0CPSR - address 0x4008 8010, SSP1CPSR -
0x4003 0010) bit description
Bit Symbol Description Reset
Value
7:0 CPSDVSR This even value between 2 and 254, by which SSP_PCLK is divided 0
to yield the prescaler output clock. Bit 0 always reads as 0.
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Important: the SSPnCPSR value must be properly initialized or the SSP controller will not
be able to transmit data correctly.
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the
SSP peripheral clock selected in Section 4.7.3. The content of the SSPnCPSR register is
not relevant.
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Table 375: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4008 8014,
SSP1IMSC - 0x4003 0014) bit description
Bit Symbol Description Reset
Value
0 RORIM Software should set this bit to enable interrupt when a Receive Overrun 0
occurs, that is, when the Rx FIFO is full and another frame is completely
received. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
1 RTIM Software should set this bit to enable interrupt when a Receive Timeout 0
condition occurs. A Receive Timeout occurs when the Rx FIFO is not
empty, and no has not been read for a "timeout period". The timeout
period is the same for master and slave modes and is determined by the
SSP bit rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).
2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at 0
least half full.
3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at 0
least half empty.
31:4 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 376: SSPn Raw Interrupt Status register (SSP0RIS - address 0x4008 8018, SSP1RIS -
0x4003 0018) bit description
Bit Symbol Description Reset
Value
0 RORRIS This bit is 1 if another frame was completely received while the RxFIFO 0
was full. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
1 RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a 0
"timeout period". The timeout period is the same for master and slave
modes and is determined by the SSP bit rate: 32 bits at PCLK /
(CPSDVSR × [SCR+1]).
2 RXRIS This bit is 1 if the Rx FIFO is at least half full. 0
3 TXRIS This bit is 1 if the Tx FIFO is at least half empty. 1
31:4 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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Table 377: SSPn Masked Interrupt Status register (SSPnMIS -address 0x4008 801C, SSP1MIS
- 0x4003 001C) bit description
Bit Symbol Description Reset
Value
0 RORMIS This bit is 1 if another frame was completely received while the RxFIFO 0
was full, and this interrupt is enabled.
1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a 0
"timeout period", and this interrupt is enabled. The timeout period is the
same for master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).
2 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is 0
enabled.
3 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is 0
enabled.
31:4 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 378: SSPn interrupt Clear Register (SSP0ICR - address 0x4008 8020, SSP1ICR -
0x4003 0020) bit description
Bit Symbol Description Reset
Value
0 RORIC Writing a 1 to this bit clears the “frame was received when RxFIFO was NA
full” interrupt.
1 RTIC Writing a 1 to this bit clears the "Rx FIFO was not empty and has not NA
been read for a timeout period" interrupt. The timeout period is the same
for master and slave modes and is determined by the SSP bit rate: 32
bits at PCLK / (CPSDVSR × [SCR+1]).
31:2 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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Table 379: SSPn DMA Control Register (SSP0DMACR - address 0x4008 8024, SSP1DMACR -
0x4003 0024) bit description
Bit Symbol Description Reset
Value
0 Receive DMA Enable When this bit is set to one 1, DMA for the receive FIFO is 0
(RXDMAE) enabled, otherwise receive DMA is disabled.
1 Transmit DMA Enable When this bit is set to one 1, DMA for the transmit FIFO is 0
(TXDMAE) enabled, otherwise transmit DMA is disabled
31:2 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
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19.2 Features
• Standard I2C compliant bus interfaces may be configured as Master, Slave, or
Master/Slave.
• Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.
• Programmable clock allows adjustment of I2C transfer rates.
• Data transfer is bidirectional between masters and slaves.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.
• Supports Fast Mode Plus (I2C0 only).
• Optional recognition of up to 4 distinct slave addresses.
• Monitor mode allows observing all I2C-bus traffic, regardless of slave address, without
affecting the actual I2C-bus traffic.
• The I2C-bus can be used for test and diagnostic purposes.
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• I2C0 is a standard I2C compliant bus interface with open-drain pins. This interface
supports functions described in the I2C specification for speeds up to 1 MHz (Fast
Mode Plus). This includes multi-master operation and allows powering off this device
in a working system while leaving the I2C-bus functional.
19.3 Applications
Interfaces to external I2C standard parts, such as serial RAMs, LCDs, tone generators,
other microcontrollers, etc.
19.4 Description
A typical I2C-bus configuration is shown in Figure 84. Depending on the state of the
direction bit (R/W), two types of data transfers are possible on the I2C-bus:
• Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte, unless the slave device is unable
to accept more data.
• Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the I2C-bus will not be
released.
The LPC17xx I2C interfaces are byte oriented and have four operating modes: master
transmitter mode, master receiver mode, slave transmitter mode and slave receiver
mode.
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pull-up pull-up
resistor resistor
SDA
I 2C bus
SCL
SDA SCL
In order to use Fast Mode Plus, the I2C0 pins must be configured, then rates above 400
kHz and up to 1 Mhz may be selected, see Table 394. To configure the pins for Fast Mode
Plus, the SDADRV0 and SCLDRV0 bits in the I2CPADCFG register must be set, see
Section 8.5.21.
[1] I2C0 is only available in 100-pin LPC17xx devices. The SDA0 and SCL0 pins are open-drain pins to comply
with I2C specifications. The pins must be configured in the I2CPADCFG register for Fast Mode Plus.
The internal logic of the 3 I2C interfaces is identical. These interfaces can be brought out
to device pins in several ways, some of which have different pin I/O characteristics. I2C0
on pins P0[27] and P0[28] use specialized I2C pads that support fully spec compliant fast
mode, standard mode, and fast mode plus I2C.
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Any of the I2C interfaces brought out to pins other than those just mentioned use standard
I/O pins. These pins also support I2C operation in fast mode and standard mode. The
primary difference is that these pins do not include an analog spike suppression filter that
exists on the specialized I2C pads. The I2C interfaces all include a digital filter that can
serve the same purpose.
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
The I2C interface will enter master transmitter mode when software sets the STA bit. The
I2C logic will send the START condition as soon as the bus is free. After the START
condition is transmitted, the SI bit is set, and the status code in the I2STAT register is
0x08. This status code is used to vector to a state service routine which will load the slave
address and Write bit to the I2DAT register, and then clear the SI bit. SI is cleared by
writing a 1 to the SIC bit in the I2CONCLR register.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes now are 0x18,
0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled
(by setting AA to 1). The appropriate actions to be taken for each of these status codes
are shown in Table 398 to Table 401.
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When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show the
status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For
slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to
Table 399.
When the LPC17xx needs to acknowledge a received byte, the AA bit needs to be set
accordingly prior to clearing the SI bit and initiating the byte read. When the LPC17xx
needs to not acknowledge a received byte, the AA bit needs to be cleared prior to clearing
the SI bit and initiating the byte read.
Note that the last received byte is always followed by a "Not Acknowledge" from the
LPC17xx so that the master can signal the slave that the reading sequence is finished and
that it needs to issue a STOP or repeated START Command. Once the "Not Acknowledge
has been sent and the SI bit is set, the LPC17xx can send either a STOP (STO bit is set)
or a repeated START (STA bit is set). Then the SI bit is cleared to initiate the requested
operation.
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After a repeated START condition, I2C may switch to the master transmitter mode.
Fig 87. A Master Receiver switches to Master Transmitter after sending repeated START
I2EN must be set to 1 to enable the I2C function. AA bit must be set to 1 to acknowledge
any of its own slave addresses or the General Call address. The STA, STO and SI bits are
set to 0.
After I2ADR and I2CONSET are initialized, the I2C interface waits until it is addressed by
its any of its own slave addresses or General Call address followed by the data direction
bit. If the direction bit is 0 (W), it enters slave receiver mode. If the direction bit is 1 (R), it
enters slave transmitter mode. After the address and direction bit have been received, the
SI bit is set and a valid status code can be read from the Status register (I2STAT). Refer to
Table 400 for the status codes and actions.
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The output for I2C is a special pad designed to conform to the I2C specification.
ADDRESS REGISTERS
I2CnADDR0 to I2CnADDR3
MATCHALL
I2CnMMCTRL[3]
MASK REGISTERS
MASK and COMPARE
I2CnMASK0 to I2CnMASK3
INPUT
FILTER
I2CnDATABUFFER
SDA
SHIFT REGISTER
OUTPUT ACK
I2CnDAT
STAGE
8
MONITOR MODE
REGISTER
I2CnMMCTRL
APB BUS
BIT COUNTER/
INPUT ARBITRATION and PCLK
FILTER SYNC LOGIC
TIMING and
SCL CONTROL
LOGIC
OUTPUT SERIAL CLOCK
interrupt
STAGE GENERATOR
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Remark: in the remainder of this chapter, when the phrase “own slave address” is used, it
refers to any of the four configured slave addresses after address masking.
When an address-match interrupt occurs, the processor will have to read the data register
(I2DAT) to determine which received address actually caused the match.
19.7.4 Comparator
The comparator compares the received 7-bit slave address with any of the four configured
slave addresses in I2ADR0 through I2ADR3 after masking. It also compares the first
received 8-bit byte with the General Call address (0x00). If an a match is found, the
appropriate status bits are set and an interrupt is requested.
Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode
can only occur while the I2C block is returning a “not acknowledge: (logic 1) to the bus.
Arbitration is lost when another device on the bus pulls this signal low. Since this can
occur only at the end of a serial byte, the I2C block generates no further clock pulses.
Figure 91 shows the arbitration procedure.
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SCL line
1 2 3 4 8 9
ACK
The synchronization logic will synchronize the serial clock generator with the clock pulses
on the SCL line from another device. If two or more master devices generate clock pulses,
the “mark” duration is determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the longest “spaces”.
Figure 92 shows the synchronization procedure.
SDA line
SCL line
(2)
high low
period period
(1) Another device pulls the SCL line low before this I2C has timed a complete high time. The other
device effectively determines the (shorter) HIGH period.
(2) Another device continues to pull the SCL line low after this I2C has timed a complete low time and
released SCL. The I2C clock generator is forced to wait until SCL goes HIGH. The other device
effectively determines the (longer) LOW period.
(3) The SCL line is released , and the clock generator begins timing the HIGH time.
Fig 92. Serial clock synchronization
A slave may stretch the space duration to slow down the bus master. The space duration
may also be stretched for handshaking purposes. This can be done after each bit or after
a complete byte transfer. the I2C block will stretch the SCL space duration after a byte has
been transmitted or received and the acknowledge bit has been transferred. The serial
interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is
cleared.
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via the I2C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH
registers for details. The output clock pulses have a duty cycle as programmed unless the
bus is synchronizing with other SCL clock sources as described above.
The contents of the I2C control register may be read as I2CONSET. Writing to I2CONSET
will set bits in the I2C control register that correspond to ones in the value written.
Conversely, writing to I2CONCLR will clear bits in the I2C control register that correspond
to ones in the value written.
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Remark: In the LPC17xx, the following registers have been added to support response to
multiple addresses in Slave mode and a new Monitor mode: I2ADR1 to 3, I2MASK0 To 3,
MMCTRL, and I2DATA_BUFFER.
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[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
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Table 384. I2C Control Set register (I2CONSET: I2C0, I2C0CONSET - address 0x4001 C000,
I2C1, I2C1CONSET - address 0x4005 C000, I2C2, I2C2CONSET - address
0x400A 0000) bit description
Bit Symbol Description Reset
value
1:0 - Reserved. User software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
2 AA Assert acknowledge flag. 0
3 SI I2C interrupt flag. 0
4 STO STOP flag. 0
5 STA START flag. 0
6 I2EN I2C interface enable. 0
31:7 - Reserved. User software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
I2EN I2C Interface Enable. When I2EN is 1, the I2C interface is enabled. I2EN can be
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I2C
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I2C block is in the “not
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I2C-bus since, when I2EN is reset, the
I2C-bus status is lost. The AA flag should be used instead.
STA is the START flag. Setting this bit causes the I2C interface to enter master mode and
transmit a START condition or transmit a repeated START condition if it is already in
master mode.
When STA is 1 and the I2C interface is not already in master mode, it enters master mode,
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition
after a delay of a half clock period of the internal clock generator. If the I2C interface is
already in master mode and data has been transmitted or received, it transmits a repeated
START condition. STA may be set at any time, including when the I2C interface is in an
addressed slave mode.
STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is
0, no START condition or repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I2C-bus if it the
interface is in master mode, and transmits a START condition thereafter. If the I2C
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
STO is the STOP flag. Setting this bit causes the I2C interface to transmit a STOP
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I2C-bus. When the bus detects
the STOP condition, STO is cleared automatically.
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In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to “not addressed” slave receiver mode. The STO flag is
cleared by hardware automatically.
SI is the I2C Interrupt Flag. This bit is set when the I2C state changes. However, entering
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register. The SI bit
should be cleared only after the required bit(s) has (have) been set and the value in I2DAT
has been loaded or read.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:
1. A data byte has been received while the I2C is in the master receiver mode.
2. A data byte has been received while the I2C is in the addressed slave receiver mode.
Table 385. I2C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR - 0x4001 C018; I2C1,
I2C1CONCLR - 0x4005 C018; I2C2, I2C2CONCLR - 0x400A 0018) bit description
Bit Symbol Description
1:0 - Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
2 AAC Assert acknowledge Clear bit.
3 SIC I2C interrupt Clear bit.
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Table 385. I2C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR - 0x4001 C018; I2C1,
I2C1CONCLR - 0x4005 C018; I2C2, I2C2CONCLR - 0x400A 0018) bit description
Bit Symbol Description
4 - Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
5 STAC START flag Clear bit.
6 I2ENC I2C interface Disable bit.
31:7 - Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I2C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
register. Writing 0 has no effect.
STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the
I2CONSET register. Writing 0 has no effect.
I2ENC is the I2C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
I2CONSET register. Writing 0 has no effect.
19.8.3 I2C Status register (I2STAT: I2C0, I2C0STAT - 0x4001 C004; I2C1,
I2C1STAT - 0x4005 C004; I2C2, I2C2STAT - 0x400A 0004)
Each I2C Status register reflects the condition of the corresponding I2C interface. The I2C
Status register is read-only.
Table 386. I2C Status register (I2STAT: I2C0, I2C0STAT - 0x4001 C004; I2C1, I2C1STAT -
0x4005 C004; I2C2, I2C2STAT - 0x400A 0004) bit description
Bit Symbol Description Reset
value
2:0 - These bits are unused and are always 0. 0
7:3 Status These bits give the actual status information about the I2C interface. 0x1F
31:8 - Reserved. The value read from a reserved bit is not defined. NA
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I2C states. When any of these states entered, the SI bit will
be set. For a complete list of status codes, refer to tables from Table 398 to Table 401.
19.8.4 I2C Data register (I2DAT: I2C0, I2C0DAT - 0x4001 C008; I2C1, I2C1DAT -
0x4005 C008; I2C2, I2C2DAT - 0x400A 0008)
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
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Table 387. I2C Data register (I2DAT: I2C0, I2C0DAT - 0x4001 C008; I2C1, I2C1DAT -
0x4005 C008; I2C2, I2C2DAT - 0x400A 0008) bit description
Bit Symbol Description Reset
value
7:0 Data This register holds data values that have been received or are to be 0
transmitted.
31:8 - Reserved. User software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 388. I2C Monitor mode control register (I2MMCTRL: I2C0, I2C0MMCTRL - 0x4001 C01C;
I2C1, I2C1MMCTRL- 0x4005 C01C; I2C2, I2C2MMCTRL- 0x400A 001C) bit
description
Bit Symbol Value Description Reset
value
0 MM_ENA Monitor mode enable. 0
0 Monitor mode disabled.
1 The I2C module will enter monitor mode. In this mode the
SDA output will be put in high impedance mode. This
prevents the I2C module from outputting data of any kind
(including ACK) onto the I2C data bus.
Depending on the state of the ENA_SCL bit, the output may
be also forced high, preventing the module from having
control over the I2C clock line.
1 ENA_SCL SCL output enable. 0
0 When this bit is cleared to ‘0’, the SCL output will be forced
high when the module is in monitor mode. As described
above, this will prevent the module from having any control
over the I2C clock line.
1 When this bit is set, the I2C module may exercise the same
control over the clock line that it would in normal operation.
This means that, acting as a slave peripheral, the I2C
module can “stretch” the clock line (hold it low) until it has
had time to respond to an I2C interrupt.[1]
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Table 388. I2C Monitor mode control register (I2MMCTRL: I2C0, I2C0MMCTRL - 0x4001 C01C;
I2C1, I2C1MMCTRL- 0x4005 C01C; I2C2, I2C2MMCTRL- 0x400A 001C) bit
description
Bit Symbol Value Description Reset
value
2 MATCH_ALL Select interrupt register match. 0
0 When this bit is cleared, an interrupt will only be generated
when a match occurs to one of the (up-to) four address
registers, I2ADR0 through I2ADR3. That is, the module will
respond as a normal slave as far as address-recognition is
concerned.
1 When this bit is set to ‘1’ and the I2C is in monitor mode, an
interrupt will be generated on ANY address received. This
will enable the part to monitor all traffic on the bus.
31:3 - Reserved. User software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
[1] When the ENA_SCL bit is cleared and the I2C no longer has the ability to stretch the clock, interrupt
response time becomes important. To give the part more time to respond to an I2C interrupt under these
conditions, an I2DATA_BUFFER register is used (Section 19.8.6) to hold received data for a full 9-bit word
transmission time.
Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).
Following all of these interrupts, the processor may read the data register to see what was
actually transmitted on the bus.
Software should be aware of the fact that the module is in monitor mode and should not
respond to any loss of arbitration state that is detected.
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To give the processor more time to respond, a new 8-bit, read-only I2DATA_BUFFER
register will be added. The contents of the 8 MSBs of the I2DAT shift register will be
transferred to the I2DATA_BUFFER automatically after every 9 bits (8 bits of data plus
ACK or NACK) has been received on the bus. This means that the processor will have 9
bit transmission times to respond to the interrupt and read the data before it is overwritten.
The processor will still have the ability to read I2DAT directly, as usual, and the behavior of
I2DAT will not be altered in any way.
Although the I2DATA_BUFFER register is primarily intended for use in monitor mode with
the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of
operation.
If these registers contain 0x00, the I2C will not acknowledge any address on the bus. All
four registers will be cleared to this disabled state on reset.
Table 390. I2C Slave Address registers (I2ADR0 to 3: I2C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C,
20, 24, 28]; I2C1, I2C1ADR[0, 1, 2, 3] - address 0x4005 C0[0C, 20, 24, 28]; I2C2,
I2C2ADR[0, 1, 2, 3] - address 0x400A 00[0C, 20, 24, 28]) bit description
Bit Symbol Description Reset
value
0 GC General Call enable bit. 0
7:1 Address The I2C device address for slave mode. 0x00
31:8 - Reserved. User software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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The mask register has no effect on comparison to the General Call address (“0000000”).
When an address-match interrupt occurs, the processor will have to read the data register
(I2DAT) to determine which received address actually caused the match.
Table 391. I2C Mask registers (I2MASK0 to 3: I2C0, I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34,
38, 3C]; I2C1, I2C1MASK[0, 1, 2, 3] - address 0x4005 C0[30, 34, 38, 3C]; I2C2,
I2C2MASK[0, 1, 2, 3] - address 0x400A 00[30, 34, 38, 3C]) bit description
Bit Symbol Description Reset
value
0 - Reserved. User software should not write ones to reserved bits. This bit 0
reads always back as 0.
7:1 MASK Mask bits. 0x00
31:8 - Reserved. User software should not write ones to reserved bits. These 0
bits read always back as zeroes.
19.8.9 I2C SCL HIGH duty cycle register (I2SCLH: I2C0, I2C0SCLH -
0x4001 C010; I2C1, I2C1SCLH - 0x4005 C010; I2C2, I2C2SCLH -
0x400A 0010)
Table 392. I2C SCL HIGH Duty Cycle register (I2SCLH: I2C0, I2C0SCLH - address
0x4001 C010; I2C1, I2C1SCLH - address 0x4005 C010; I2C2, I2C2SCLH -
0x400A 0010) bit description
Bit Symbol Description Reset value
15:0 SCLH Count for SCL HIGH time period selection. 0x0004
31:16 - Reserved. The value read from a reserved bit is not defined. NA
19.8.10 I2C SCL Low duty cycle register (I2SCLL: I2C0 - I2C0SCLL:
0x4001 C014; I2C1 - I2C1SCLL: 0x4005 C014; I2C2 - I2C2SCLL:
0x400A 0014)
Table 393. I2C SCL Low duty cycle register (I2SCLL: I2C0 - I2C0SCLL: 0x4001 C014; I2C1 -
I2C1SCLL: 0x4005 C014; I2C2 - I2C2SCLL: 0x400A 0014) bit description
Bit Symbol Description Reset value
15:0 SCLL Count for SCL low time period selection. 0x0004
31:16 - Reserved. The value read from a reserved bit is not defined. NA
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19.8.11 Selecting the appropriate I2C data rate and duty cycle
Software must set values for the registers I2SCLH and I2SCLL to select the appropriate
data rate and duty cycle. I2SCLH defines the number of PCLK_I2C cycles for the SCL
HIGH time, I2SCLL defines the number of PCLK_I2C cycles for the SCL low time. The
frequency is determined by the following formula (PCLK_I2C is the frequency of the
peripheral bus APB):
(11)
PCLKI2C
I 2 C bitfrequency = ---------------------------------------------------------
I2CSCLH + I2CSCLL
The values for I2SCLL and I2SCLH must ensure that the data rate is in the appropriate
I2C data rate range. Each register value must be greater than or equal to 4. Table 394
gives some examples of I2C-bus rates based on PCLK_I2C frequency and I2SCLL and
I2SCLH values.
I2SCLL and I2SCLH values should not necessarily be the same. Software can set
different duty cycles on SCL by setting these two registers. For example, the I2C-bus
specification defines the SCL low time and high time at different values for a Fast Mode
and Fast Mode Plus I2C.
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• Master Transmitter
• Master Receiver
• Slave Receiver
• Slave Transmitter
Data transfers in each mode of operation are shown in Figure 93, Figure 94, Figure 95,
Figure 96, and Figure 97. Table 395 lists abbreviations used in these figures when
describing the I2C operating modes.
In Figure 93 to Figure 97, circles are used to indicate when the serial interrupt flag is set.
The numbers in the circles show the status code held in the I2STAT register. At these
points, a service routine must be executed to continue or complete the serial transfer.
These service routines are not critical since the serial transfer is suspended until the serial
interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in I2STAT is used to branch to
the appropriate service routine. For each status code, the required software action and
details of the following serial transfer are given in tables from Table 398 to Table 402.
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The I2C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be
set to logic 1 to enable the I2C block. If the AA bit is reset, the I2C block will not
acknowledge its own slave address or the General Call address in the event of another
device becoming master of the bus. In other words, if AA is reset, the I2C interface cannot
enter a slave mode. STA, STO, and SI must be reset.
The master transmitter mode may now be entered by setting the STA bit. The I2C logic will
now test the I2C-bus and generate a START condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status
code in the status register (I2STAT) will be 0x08. This status code is used by the interrupt
service routine to enter the appropriate state service routine that loads I2DAT with the
slave address and the data direction bit (SLA+W). The SI bit in I2CON must then be reset
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in I2STAT are possible. There are 0x18, 0x20, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).
The appropriate action to be taken for each of these status codes is detailed in Table 398.
After a repeated START condition (state 0x10). The I2C block may switch to the master
receiver mode by loading I2DAT with SLA+R).
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MT
successful
transmission
S SLA W A DATA A P
to a Slave
Receiver
next transfer
started with a
S SLA W
Repeated Start
condition
Not 10H
Acknowledge
received after A P R
the Slave
address
20H
to Master
receive
Not
mode,
Acknowledge
A P entry
received after a
= MR
Data byte
30H
arbitration lost
in Slave other Master other Master
A OR A A OR A
address or continues continues
Data byte
38H 38H
arbitration lost
and other Master
A
addressed as continues
Slave
to corresponding
68H 78H B0H
states in Slave mode
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When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in I2STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in Table 399. After
a repeated START condition (state 0x10), the I2C block may switch to the master
transmitter mode by loading I2DAT with SLA+W.
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MR
successful
transmission to S SLA R A DATA A DATA A P
a Slave
transmitter
next transfer
started with a
S SLA R
Repeated Start
condition
10H
Not Acknowledge
received after the A P W
Slave address
48H
to Master
transmit
mode, entry
= MT
arbitration lost in
Slave address or other Master other Master
A OR A A
Acknowledge bit continues continues
38H 38H
arbitration lost
other Master
and addressed A
continues
as Slave
to corresponding
68H 78H B0H states in Slave
mode
from Master to Slave
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The values on the four I2ADR registers combined with the values on the four I2MASK
registers determines which address(es) the I2C block will respond to when slave functions
are enabled. See sections 19.7.2, 19.7.3, 19.8.7, and 19.8.8 for details.
The I2C-bus rate settings do not affect the I2C block in the slave mode. I2EN must be set
to logic 1 to enable the I2C block. The AA bit must be set to enable the I2C block to
acknowledge its own slave address or the General Call address. STA, STO, and SI must
be reset.
When the I2ADR, I2MASK, and I2CON registers have been initialized, the I2C block waits
until it is addressed by its own slave address followed by the data direction bit which must
be “0” (W) for the I2C block to operate in the slave receiver mode. After its own slave
address and the W bit have been received, the serial interrupt flag (SI) is set and a valid
status code can be read from I2STAT. This status code is used to vector to a state service
routine. The appropriate action to be taken for each of these status codes is detailed in
Table 400. The slave receiver mode may also be entered if arbitration is lost while the I2C
block is in the master mode (see status 0x68 and 0x78).
If the AA bit is reset during a transfer, the I2C block will return a not acknowledge (logic 1)
to SDA after the next received data byte. While AA is reset, the I2C block does not
respond to its own slave address or a General Call address. However, the I2C-bus is still
monitored and address recognition may be resumed at any time by setting AA. This
means that the AA bit may be used to temporarily isolate the I2C block from the I2C-bus.
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88H
arbitration lost as
Master and addressed A
as Slave
68H
reception of the
General Call address
GENERAL CALL A DATA A DATA A P OR S
and one or more Data
bytes
98h
arbitration lost as
Master and addressed
A
as Slave by General
Call
78h
DATA A any number of data bytes and their associated Acknowledge bits
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If the AA bit is reset during a transfer, the I2C block will transmit the last byte of the transfer
and enter state 0xC0 or 0xC8. The I2C block is switched to the not addressed slave mode
and will ignore the master receiver if it continues the transfer. Thus the master receiver
receives all 1s as serial data. While AA is reset, the I2C block does not respond to its own
slave address or a General Call address. However, the I2C-bus is still monitored, and
address recognition may be resumed at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the I2C block from the I2C-bus.
arbitration lost as
Master and A
addressed as Slave
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If the I2C hardware detects a repeated START condition on the I2C-bus before generating
a repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I2C block
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.
If the STA flag in I2CON is set by the routines which service these states, then, if the bus
is free again, a START condition (state 0x08) is transmitted without intervention by the
CPU, and a retry of the total serial transfer can commence.
Typically, the SDA line may be obstructed by another device on the bus that has become
out of synchronization with the current bus master by either missing a clock, or by sensing
a noise pulse as a clock. In this case, the problem can be solved by transmitting additional
clock pulses on the SCL line Figure 99. The I2C interface does not include a dedicated
timeout timer to detect an obstructed bus, but this can be implemented using another
timer in the system. When detected, software can force clocks (up to 9 may be required)
on SCL until SDA is released by the offending device. At that point, the slave may still be
out of synchronization, so a START should be generated to insure that all I2C peripherals
are synchronized.
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The I2C hardware only reacts to a bus error when it is involved in a serial transfer either as
a master or an addressed slave. When a bus error is detected, the I2C block immediately
switches to the not addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 0x00. This status code may be used to
vector to a state service routine which either attempts the aborted serial transfer again or
simply recovers from the error condition as shown in Table 402.
OTHER MASTER
S SLA W A DATA A S P S SLA
CONTINUES
time limit
STA flag
STO flag
SDA line
SCL line
start
condition
STA flag
(2) (3)
(1) (1)
SDA line
SCL line
start
condition
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19.9.8.1 Initialization
In the initialization example, the I2C block is enabled for both master and slave modes.
For each mode, a buffer is used for transmission and reception. The initialization routine
performs the following functions:
• The I2ADR registers and I2MASK registers are loaded with values to configure the
part’s own slave address(es) and the General Call bit (GC)
• The I2C interrupt enable and interrupt priority bits are set
• The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON
and the serial clock frequency (for master modes) is defined by loading the I2SCLH
and I2SCLL registers. The master routines must be started in the main program.
The I2C hardware now begins checking the I2C-bus for its own slave address and General
Call. If the General Call or the own slave address is detected, an interrupt is requested
and I2STAT is loaded with the appropriate state information.
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1. Load the I2ADR registers and I2MASK registers with values to configure the own
Slave Address, enable General Call recognition if needed.
2. Enable I2C interrupt.
3. Write 0x44 to I2CONSET to set the I2EN and AA bits, enabling Slave functions. For
Master only functions, write 0x40 to I2CONSET.
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1. Load I2DAT with first data byte from Master Transmit buffer.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Increment Master Transmit buffer pointer.
5. Exit
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1. Decrement the Master data counter, skip to step 5 if not the last data byte.
2. Write 0x14 to I2CONSET to set the STO and AA bits.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Exit
5. Load I2DAT with next data byte from Master Transmit buffer.
6. Write 0x04 to I2CONSET to set the AA bit.
7. Write 0x08 to I2CONCLR to clear the SI flag.
8. Increment Master Transmit buffer pointer
9. Exit
3. Exit
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1. Read data byte from I2DAT into the Slave Receive buffer.
2. Decrement the Slave data counter, skip to step 5 if not the last data byte.
3. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit.
4. Exit.
5. Write 0x04 to I2CONSET to set the AA bit.
6. Write 0x08 to I2CONCLR to clear the SI flag.
7. Increment Slave Receive buffer pointer.
8. Exit
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1. Read data byte from I2DAT into the Slave Receive buffer.
2. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit.
3. Exit
1. Load I2DAT from Slave Transmit buffer with first data byte.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Set up Slave Transmit mode data buffer.
5. Increment Slave Transmit buffer pointer.
6. Exit
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1. Load I2DAT from Slave Transmit buffer with first data byte.
2. Write 0x24 to I2CONSET to set the STA and AA bits.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Set up Slave Transmit mode data buffer.
5. Increment Slave Transmit buffer pointer.
6. Exit
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20.2 Features
The I2S bus provides a standard communication interface for digital audio applications.
The I2S bus specification defines a 3-wire serial bus, having one data, one clock, and one
word select signal. The basic I2S connection has one master, which is always the master,
and one slave. The I2S interface on the LPC17xx provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
• The I2S input can operate in both master and slave mode.
The I2S output can operate in both master and slave mode, independent of the I2S
input.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• Versatile clocking includes independent transmit and receive fractional rate
generators, and an ability to use a single clock input or output for a 4-wire mode.
• The sampling frequency (fs) can range (in practice) from 16 to 96 kHz. (16, 22.05, 32,
44.1, 48, or 96 kHz) for audio applications.
• Separate Master Clock outputs for both transmit and receive channels support a clock
up to 512 times the I2S sampling frequency.
• Word Select period in master mode is configurable (separately for I2S input and I2S
output).
• Two 8 word (32 byte) FIFO data buffers are provided, one for transmit and one for
receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected
to the General Purpose DMA block.
• Controls include reset, stop and mute options separately for I2S input and I2S output.
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20.3 Description
The I2S performs serial data out via the transmit channel and serial data in via the receive
channel. These support the NXP Inter IC Audio format for 8-bit, 16-bit and 32-bit audio
data, both for stereo and mono modes. Configuration, data access and control is
performed by a APB register set. Data streams are buffered by FIFOs with a depth of
8 words.
The I2S receive and transmit stage can operate independently in either slave or master
mode. Within the I2S module the difference between these modes lies in the word select
(WS) signal which determines the timing of data transmissions. Data words start on the
next falling edge of the transmitting clock after a WS change. In stereo mode when WS is
low left data is transmitted and right data when WS is high. In mono mode the same data
is transmitted twice, once when WS is low and again when WS is high.
• In master mode, word select is generated internally with a 9-bit counter. The half
period count value of this counter can be set in the control register.
• In slave mode, word select is input from the relevant bus pin.
• When an I2S bus is active, the word select, receive clock and transmit clock signals
are sent continuously by the bus master, while data is sent continuously by the
transmitter.
• Disabling the I2S can be done with the stop or mute control bits separately for the
transmit and receive.
• The stop bit will disable accesses by the transmit channel or the receive channel to
the FIFOs and will place the transmit channel in mute mode.
• The mute control bit will place the transmit channel in mute mode. In mute mode, the
transmit channel FIFO operates normally, but the output is discarded and replaced by
zeroes. This bit does not affect the receive channel, data reception can occur
normally.
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CONTROLLER
(MASTER)
SCK
TRANSMITTER WS RECEIVER
(SLAVE) SD (SLAVE)
SCK
WS
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 405: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description
Bit Symbol Value Description Reset
Value
1:0 wordwidth Selects the number of bytes in data as follows: 01
00 8-bit data
01 16-bit data
10 Reserved, do not use this setting
11 32-bit data
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Table 405: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description
Bit Symbol Value Description Reset
Value
2 mono When 1, data is of monaural format. When 0, the data is in stereo format. 0
3 stop When 1, disables accesses on FIFOs, places the transmit channel in mute mode. 0
4 reset When 1, asynchronously resets the transmit channel and FIFO. 0
5 ws_sel When 0, the interface is in master mode. When 1, the interface is in slave mode. See 1
Section 20.7 for a summary of useful combinations for this bit with I2STXMODE.
14:6 ws_halfperiod Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F
15 mute When 1, the transmit channel sends only zeroes. 1
31:16 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
Table 406: Digital Audio Input register (I2SDAI - address 0x400A 8004) bit description
Bit Symbol Value Description Reset
Value
1:0 wordwidth Selects the number of bytes in data as follows: 01
00 8-bit data
01 16-bit data
10 Reserved, do not use this setting
11 32-bit data
2 mono When 1, data is of monaural format. When 0, the data is in stereo format. 0
3 stop When 1, disables accesses on FIFOs, places the transmit channel in mute mode. 0
4 reset When 1, asynchronously reset the transmit channel and FIFO. 0
5 ws_sel When 0, the interface is in master mode. When 1, the interface is in slave mode. See 1
Section 20.7 for a summary of useful combinations for this bit with I2SRXMODE.
14:6 ws_halfperiod Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F
31:15 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
Table 407: Transmit FIFO register (I2STXFIFO - address 0x400A 8008) bit description
Bit Symbol Description Reset Value
31:0 I2STXFIFO 8 × 32-bit transmit FIFO. Level = 0
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Table 408: Receive FIFO register (I2RXFIFO - address 0x400A 800C) bit description
Bit Symbol Description Reset Value
31:0 I2SRXFIFO 8 × 32-bit transmit FIFO. level = 0
Table 409: Status Feedback register (I2SSTATE - address 0x400A 8010) bit description
Bit Symbol Description Reset
Value
0 irq This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by 1
comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the I2SIRQ
register.
1 dmareq1 This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by 1
comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the
I2SDMA1 register.
2 dmareq2 This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by 1
comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the
I2SDMA2 register.
7:3 Unused Unused. 0
11:8 rx_level Reflects the current level of the Receive FIFO. 0
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved NA
bit is not defined.
19:16 tx_level Reflects the current level of the Transmit FIFO. 0
31:20 - Reserved, user software should not write ones to reserved bits. The value read from a reserved NA
bit is not defined.
Table 410: DMA Configuration register 1 (I2SDMA1 - address 0x400A 8014) bit description
Bit Symbol Description Reset
Value
0 rx_dma1_enable When 1, enables DMA1 for I2S receive. 0
1 tx_dma1_enable When 1, enables DMA1 for I2S transmit. 0
7:2 - Reserved, user software should not write ones to reserved bits. The value read from a 0
reserved bit is not defined.
11:8 rx_depth_dma1 Set the FIFO level that triggers a receive DMA request on DMA1. 0
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
19:16 tx_depth_dma1 Set the FIFO level that triggers a transmit DMA request on DMA1. 0
31:20 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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Table 411: DMA Configuration register 2 (I2SDMA2 - address 0x400A 8018) bit description
Bit Symbol Description Reset
Value
0 rx_dma2_enable When 1, enables DMA1 for I2S receive. 0
1 tx_dma2_enable When 1, enables DMA1 for I2S transmit. 0
7:2 Unused Unused. 0
11:8 rx_depth_dma2 Set the FIFO level that triggers a receive DMA request on DMA2. 0
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
19:16 tx_depth_dma2 Set the FIFO level that triggers a transmit DMA request on DMA2. 0
31:20 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 412: Interrupt Request Control register (I2SIRQ - address 0x400A 801C) bit description
Bit Symbol Description Reset
Value
0 rx_Irq_enable When 1, enables I2S receive interrupt. 0
1 tx_Irq_enable When 1, enables I2S transmit interrupt. 0
7:2 Unused Unused. 0
11:8 rx_depth_irq Set the FIFO level on which to create an irq request. 0
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
19:16 tx_depth_irq Set the FIFO level on which to create an irq request. 0
31:20 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
The transmitter MCLK rate is generated using a fractional rate generator, dividing down
the frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be
chosen to produce a frequency twice that desired for the transmitter MCLK, which must be
an integer multiple of the transmitter bit clock rate. Fractional rate generators have some
aspects that the user should be aware of when choosing settings. These are discussed in
Section 20.5.9.1. The equation for the fractional rate generator is:
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Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
greater than or equal to X.
Table 413: Transmit Clock Rate register (I2TXRATE - address 0x400A 8020) bit description
Bit Symbol Description Reset
Value
7:0 Y_divider I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the 0
transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of
0 stops the clock.
15:8 X_divider I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the 0
transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide
range of possibilities. Note: the resulting ratio X/Y is divided by 2.
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
For example, if X = 0x07 and Y = 0x11, the fractional rate generator will output 7 clocks for
every 17 (11 hex) input clocks, distributed as evenly as it can. In this example, there is no
way to distribute the output clocks in a perfectly even fashion, so some clocks will be
longer than others. The output is divided by 2 in order to square it up, which also helps
with the jitter. The frequency averages out to exactly (7/17) / 2, but some clocks will be a
slightly different length than their neighbors. It is possible to avoid jitter entirely by
choosing fractions such that X divides evenly into Y, such as 2/4, 2/6, 3/9, 1/N, etc.
The receiver MCLK rate is generated using a fractional rate generator, dividing down the
frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be
chosen to produce a frequency twice that desired for the receiver MCLK, which must be
an integer multiple of the receiver bit clock rate. Fractional rate generators have some
aspects that the user should be aware of when choosing settings. These are discussed in
Section 20.5.9.1. The equation for the fractional rate generator is:
Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
greater than or equal to X.
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Table 414: Receive Clock Rate register (I2SRXRATE - address 0x400A 8024) bit description
Bit Symbol Description Reset
Value
7:0 Y_divider I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the 0
receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of
0 stops the clock.
15:8 X_divider I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the 0
receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide
range of possibilities. Note: the resulting ratio X/Y is divided by 2.
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 415: Transmit Clock Rate register (I2TXBITRATE - address 0x400A 8028) bit description
Bit Symbol Description Reset
Value
5:0 tx_bitrate I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit 0
clock.
31:6 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 416: Receive Clock Rate register (I2SRXBITRATE - address 0x400A 802C) bit description
Bit Symbol Description Reset
Value
5:0 rx_bitrate I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit 0
clock.
31:6 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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Table 417: Transmit Mode Control register (I2STXMODE - 0x400A 8030) bit description
Bit Symbol Value Description Reset
Value
1:0 TXCLKSEL Clock source selection for the transmit bit clock divider. 0
00 Select the TX fractional rate divider clock output as the source
01 Reserved
10 Select the RX_MCLK signal as the TX_MCLK clock source
11 Reserved
2 TX4PIN Transmit 4-pin mode selection. When 1, enables 4-pin mode. 0
3 TXMCENA Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, 0
output of TX_MCLK is enabled.
31:4 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 418: Receive Mode Control register (I2SRXMODE - 0x400A 8034) bit description
Bit Symbol Value Description Reset
Value
1:0 RXCLKSEL Clock source selection for the receive bit clock divider. 0
00 Select the RX fractional rate divider clock output as the source
01 Reserved
10 Select the TX_MCLK signal as the RX_MCLK clock source
11 Reserved
2 RX4PIN Receive 4-pin mode selection. When 1, enables 4-pin mode. 0
3 RXMCENA Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, 0
output of RX_MCLK is enabled.
31:4 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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• When the FIFO is empty, the transmit channel will repeat transmitting the same data
until new data is written to the FIFO.
• When mute is true, the data value 0 is transmitted.
• When mono is false, two successive data words are respectively left and right data.
• Data word length is determined by the wordwidth value in the configuration register.
There is a separate wordwidth value for the receive channel and the transmit channel.
– 0: word is considered to contain four 8-bit data words.
– 1: word is considered to contain two 16-bit data words.
– 3: word is considered to contain one 32-bit data word.
• When the transmit FIFO contains insufficient data the transmit channel will repeat
transmitting the last data until new data is available. This can occur when the
microprocessor or the DMA at some time is unable to provide new data fast enough.
Because of this delay in new data there is a need to fill the gap, which is
accomplished by continuing to transmit the last sample. The data is not muted as this
would produce an noticeable and undesirable effect in the sound.
• The transmit channel and the receive channel only handle 32-bit aligned words, data
chunks must be clipped or extended to a multiple of 32 bits.
When switching between data width or modes the I2S must be reset via the reset bit in the
control register in order to ensure correct synchronization. It is advisable to set the stop bit
also until sufficient data has been written in the transmit FIFO. Note that when stopped
data output is muted.
All data accesses to FIFOs are 32 bits. Figure 113 shows the possible data sequences.
The receive channel will start receiving data after a change of WS. When word select
becomes low it expects this data to be left data, when WS is high received data is
expected to be right data. Reception will stop when the bit counter has reached the limit
set by wordwidth. On the next change of WS the received data will be stored in the
appropriate hold register. When complete data is available it will be written into the receive
FIFO.
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Many configurations are possible that are not considered useful, the following tables and
figures give details of the configurations that are most likely to be useful.
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I2STXMODE[3]
(Pin OE)
I2STX_MCLK
I2STX_RATE[15:8]
I2STX_RATE[7:0] I2STX_CLK
I2STXBITRATE[5:0]
X Y I2S I2STX_SDA
I2S_PCLK 8-bit TX_REF ÷N TX bit clock peripheral
÷2
Fractional (1 to 64) block
Rate Divider (transmit) I2STX_WS
TX_WS ref
Fig 101. Typical transmitter master mode, with or without MCLK output
I2STX_CLK
I2STXBITRATE[5:0]
I2S I2STX_SDA
RX_REF ÷N TX bit clock peripheral
(1 to 64) block
(transmit) I2STX_WS
TX_WS ref
Fig 102. Transmitter master mode sharing the receiver reference clock
I2STX_CLK
I2S I2STX_SDA
RX bit clock peripheral
block
(transmit) I2STX_WS
RX_WS ref
Fig 103. 4-wire transmitter master mode sharing the receiver bit clock and WS
I2STX_CLK
I2STXBITRATE[5:0]
I2S I2STX_SDA
TX_REF ÷N TX bit clock peripheral
(1 to 64) block
(transmit) I2STX_WS
I2STXBITRATE[5:0]
I2S I2STX_SDA
RX_REF ÷N TX bit clock peripheral
(1 to 64) block
(transmit) I2STX_WS
Fig 105. Transmitter slave mode sharing the receiver reference clock
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I2S I2STX_SDA
RX bit clock peripheral
block
(transmit) I2STX_WS
RX_WS ref
Fig 106. 4-wire transmitter slave mode sharing the receiver bit clock and WS
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I2SRXMODE[3]
(Pin OE)
I2SRX_MCLK
I2SRX_RATE[15:8]
I2SRX_RATE[7:0] I2SRX_CLK
I2SRXBITRATE[5:0]
X Y I2S I2SRX_SDA
I2S_PCLK 8-bit RX_REF ÷N RX bit clock peripheral
÷2
Fractional (1 to 64) block
Rate Divider (receive) RX_WS ref I2SRX_WS
Fig 107. Typical receiver master mode, with or without MCLK output
I2SRX_CLK
I2SRXBITRATE[5:0]
I2S I2SRX_SDA
TX_REF ÷N RX bit clock peripheral
(1 to 64) block
(receive) RX_WS ref I2SRX_WS
Fig 108. Receiver master mode sharing the transmitter reference clock
I2SRX_CLK
I2S I2SRX_SDA
TX bit clock peripheral
block
(receive) I2SRX_WS
TX_WS ref
Fig 109. 4-wire receiver master mode sharing the transmitter bit clock and WS
I2SRX_CLK
I2SRXBITRATE[5:0]
I2S I2SRX_SDA
RX_REF ÷N RX bit clock peripheral
(1 to 64) block
(receive) I2SRX_WS
I2SRXBITRATE[5:0]
I2S I2SRX_SDA
TX_REF ÷N RX bit clock peripheral
(1 to 64) block
(receive) I2SRX_WS
Fig 111. Receiver slave mode sharing the transmitter reference clock
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I2S I2SRX_SDA
TX bit clock peripheral
block
(receive) I2SRX_WS
TX_WS ref
Fig 112. 4-wire receiver slave mode sharing the transmitter bit clock and WS
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N+1 N
15 0 15 0
LEFT RIGHT
15 0 15 0
N
31 0
LEFT N
31 0
RIGHT N+1
31 0
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21.2 Features
Remark: The four Timer/Counters are identical except for the peripheral base address. A
minimum of two Capture inputs and two Match outputs are pinned out for all four timers,
with a choice of multiple pins for each. Timer 2 brings out all four Match outputs.
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21.3 Applications
• Interval Timer for counting internal events.
• Pulse Width Demodulator via Capture inputs.
• Free running timer.
21.4 Description
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally-supplied clock, and can optionally generate interrupts or perform other actions
at specified timer values, based on four match registers. It also includes four capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
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[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 426. Interrupt Register (T[0/1/2/3]IR - addresses 0x4000 4000, 0x4000 8000, 0x4009 0000, 0x4009 4000) bit
description
Bit Symbol Description Reset
Value
0 MR0 Interrupt Interrupt flag for match channel 0. 0
1 MR1 Interrupt Interrupt flag for match channel 1. 0
2 MR2 Interrupt Interrupt flag for match channel 2. 0
3 MR3 Interrupt Interrupt flag for match channel 3. 0
4 CR0 Interrupt Interrupt flag for capture channel 0 event. 0
5 CR1 Interrupt Interrupt flag for capture channel 1 event. 0
31:6 - Reserved -
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Table 427. Timer Control Register (TCR, TIMERn: TnTCR - addresses 0x4000 4004, 0x4000 8004, 0x4009 0004,
0x4009 4004) bit description
Bit Symbol Description Reset
Value
0 Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting. When 1, 0
the counters are disabled.
1 Counter Reset When one, the Timer Counter and the Prescale Counter are synchronously reset on the 0
next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
31:2 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one quarter of
the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in
this case can not be shorter than 1/(2 PCLK).
Table 428. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070,
0x4009 4070) bit description
Bit Symbol Value Description Reset
Value
1:0 Counter/ This field selects which rising PCLK edges can increment the Timer’s Prescale Counter 00
Timer (PC), or clear the PC and increment the Timer Counter (TC).
Mode 00 Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale
Register. The Prescale Counter is incremented on every rising PCLK edge.
01 Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
10 Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
11 Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.
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Table 428. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070,
0x4009 4070) bit description
Bit Symbol Value Description Reset
Value
3:2 Count When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for 00
Input clocking.
Select 00 CAPn.0 for TIMERn
01 CAPn.1 for TIMERn
10 Reserved
11 Reserved
Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits
for that input in the Capture Control Register (TnCCR) must be programmed as 000.
However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
same timer.
31:4 - - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
21.6.4 Timer Counter registers (T0TC - T3TC, 0x4000 4008, 0x4000 8008,
0x4009 0008, 0x4009 4008)
The 32-bit Timer Counter register is incremented when the prescale counter reaches its
terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will
count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.
This event does not cause an interrupt, but a match register can be used to detect an
overflow if needed.
21.6.6 Prescale Counter register (T0PC - T3PC, 0x4000 4010, 0x4000 8010,
0x4009 0010, 0x4009 4010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship of the resolution of the
timer versus the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale register,
the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK.
This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 pclks
when PR = 1, etc.
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Table 429. Match Control Register (T[0/1/2/3]MCR - addresses 0x4000 4014, 0x4000 8014, 0x4009 0014, 0x4009 4014)
bit description
Bit Symbol Value Description Reset
Value
0 MR0I 1 Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0
0 This interrupt is disabled
1 MR0R 1 Reset on MR0: the TC will be reset if MR0 matches it. 0
0 Feature disabled.
2 MR0S 1 Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0
the TC.
0 Feature disabled.
3 MR1I 1 Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0
0 This interrupt is disabled
4 MR1R 1 Reset on MR1: the TC will be reset if MR1 matches it. 0
0 Feature disabled.
5 MR1S 1 Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0
the TC.
0 Feature disabled.
6 MR2I 1 Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0
0 This interrupt is disabled
7 MR2R 1 Reset on MR2: the TC will be reset if MR2 matches it. 0
0 Feature disabled.
8 MR2S 1 Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0
the TC.
0 Feature disabled.
9 MR3I 1 Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0
0 This interrupt is disabled
10 MR3R 1 Reset on MR3: the TC will be reset if MR3 matches it. 0
0 Feature disabled.
11 MR3S 1 Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0
the TC.
0 Feature disabled.
31:12 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
Table 430. Capture Control Register (T[0/1/2/3]CCR - addresses 0x4000 4028, 0x4000 8020, 0x4009 0028,
0x4009 4028) bit description
Bit Symbol Value Description Reset
Value
0 CAP0RE 1 Capture on CAPn.0 rising edge: a sequence of 0 then 1 on CAPn.0 will cause CR0 to be 0
loaded with the contents of TC.
0 This feature is disabled.
1 CAP0FE 1 Capture on CAPn.0 falling edge: a sequence of 1 then 0 on CAPn.0 will cause CR0 to be 0
loaded with the contents of TC.
0 This feature is disabled.
2 CAP0I 1 Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event will generate an interrupt. 0
0 This feature is disabled.
3 CAP1RE 1 Capture on CAPn.1 rising edge: a sequence of 0 then 1 on CAPn.1 will cause CR1 to be 0
loaded with the contents of TC.
0 This feature is disabled.
4 CAP1FE 1 Capture on CAPn.1 falling edge: a sequence of 1 then 0 on CAPn.1 will cause CR1 to be 0
loaded with the contents of TC.
0 This feature is disabled.
5 CAP1I 1 Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event will generate an interrupt. 0
0 This feature is disabled.
31:6 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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Match events for Match 0 and Match 1 in each timer can cause a DMA request, see
Section 21.6.12.
Table 431. External Match Register (T[0/1/2/3]EMR - addresses 0x4000 403C, 0x4000 803C, 0x4009 003C,
0x4009 403C) bit description
Bit Symbol Description Reset
Value
0 EM0 External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go 0
low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a
MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
1 EM1 External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go 0
low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a
MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).
2 EM2 External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go 0
low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a
MATn.2 pin, in a positive-logic manner (0 = low, 1 = high).
3 EM3 External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go 0
low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a
MATn.3 pin, in a positive-logic manner (0 = low, 1 = high).
5:4 EMC0 External Match Control 0. Determines the functionality of External Match 0. Table 432 shows the 00
encoding of these bits.
7:6 EMC1 External Match Control 1. Determines the functionality of External Match 1. Table 432 shows the 00
encoding of these bits.
9:8 EMC2 External Match Control 2. Determines the functionality of External Match 2. Table 432 shows the 00
encoding of these bits.
11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3. Table 432 shows the 00
encoding of these bits.
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved NA
bit is not defined.
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When a timer is initially set up to generate a DMA request, the request may already be
asserted before a match condition occurs. An initial DMA request may be avoided by
having software write a one to the interrupt flag location, as if clearing a timer interrupt.
See Section 21.6.1. A DMA request will be cleared automatically when it is acted upon by
the GPDMA controller.
Remark: Because timer DMA requests are generated whenever the timer value is equal
to the related Match Register value, DMA requests are always generated when the timer
is running, unless the Match Register value is higher than the upper count limit of the
timer. It is important not to select and enable timer DMA requests in the GPDMA block
unless the timer is correctly configured to generate valid DMA requests.
Figure 115 shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
PCLK
prescale
2 0 1 2 0 1 2 0 1 2 0 1
counter
timer
4 5 6 0 1
counter
timer counter
reset
interrupt
Fig 114. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.
PCLK
prescale counter 2 0 1 2 0
timer counter
4 5 6
TCR[0]
1 0
(counter enable)
interrupt
Fig 115. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled
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21.8 Architecture
The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in
Figure 116.
MATCH REGISTER 0
MATCH REGISTER 1
MATCH REGISTER 2
MATCH REGISTER 3
INTERRUPT REGISTER
CONTROL
MAT[3:0]
=
INTERRUPT
CAP[3:0] =
DMA REQUEST[1:0]
DMA CLEAR[1:0] =
STOP ON MATCH
=
RESET ON MATCH
LOAD[3:0]
CSN
CAPTURE REGISTER 0 TIMER COUNTER
CAPTURE REGISTER 1 CE
RESERVED
RESERVED
TCI
PCLK
PRESCALE COUNTER
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22.1 Features
• 32-bit counter running from PCLK. Counter can be free-running, or be reset by a
generated interrupt.
• 32-bit compare value.
• 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
22.2 Description
The Repetitive Interrupt Timer provides a versatile means of generating interrupts at
specified time intervals, without using a standard timer. It is intended for repeating
interrupts that aren’t related to Operating System interrupts. However, it could be used as
an alternative to the Cortex-M3 System Tick Timer (Section 23.1) if there are different
system requirements.
[1] Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.
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Counting can be halted in software by writing a ‘0’ to the Enable_Timer bit - RICTRL(2).
Counting will also be halted when the processor is halted for debugging provided the
Enable_Break bit – RICTRL(1) is set. Both the Enable_Timer and Enable_Break bits are
set on reset.
The interrupt flag can be cleared in software by writing a ‘1’ to the Interrupt bit –
RICTRL(0).
Software can load the counter to any value at any time by writing to RICOUNTER.
The counter (RICOUNTER), RICOMPVAL register, RIMASK register and RICTRL register
can all be read by software at any time.
RESET
PBUS CNT_ENA
RESET
CLR ENA
32-bit COUNTER SET
ENABLE_TIMER
3
PBUS
ENABLE_BREAK
32 2
PBUS BREAK
ENABLE_CLK
PBUS
CLR
RESET
32
COMPARATOR EQ SET_INT
S
32 0 INTR
PBUS PBUS C
write '1' to
clear CLR
32
RESET
RESET PBUS CTRL PBUS
register
SET CLR
COMPARE REGISTER MASK REGISTER
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1. Clock Source: Select either the internal CCLK or external STCLK (P3.26) clock as the
source in the STCTRL register.
2. Pins: If STCLK (P3.26) was selected as clock source enable the STCLK pin function
in the PINMODE register (Section 8.5).
3. Interrupt: The System Tick Timer Interrupt is enabled in the NVIC using the
appropriate Interrupt Set Enable register.
23.2 Features
• Times intervals of 10 milliseconds
• Dedicated exception vector
• Can be clocked internally by the CPU clock or by a clock input from a pin (STCLK)
23.3 Description
The System Tick Timer is an integral part of the Cortex-M3. The System Tick Timer is
intended to generate a fixed 10 millisecond interrupt for use by an operating system or
other system management software.
Since the System Tick Timer is a part of the Cortex-M3, it facilitates porting of software by
providing a standard timer that is available on Cortex-M3 based devices.
Refer to the Cortex-M3 User Guide appended to this manual (Section 34.4.4) for details of
System Tick Timer operation.
23.4 Operation
The System Tick Timer is a 24-bit timer that counts down to zero and generates an
interrupt. The intent is to provide a fixed 10 millisecond time interval between interrupts.
The System Tick Timer may be clocked either from the CPU clock or from the external pin
STCLK. The STCLK function shares pin P3.26 with other functions, and must be selected
for use as the System Tick Timer clock. In order to generate recurring interrupts at a
specific interval, the STRELOAD register must be initialized with the correct value for the
desired interval. A default value is provided in the STCALIB register and may be changed
by software. The default value gives a 10 millisecond interrupt rate if the CPU clock is set
to 100 MHz.
The block diagram of the System Tick Timer is shown below in the Figure 118.
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STCALIB
STRELOAD
load data
STCURR private
cclk 24-bit down counter peripheral
bus
clock
STCLK pin under- count
D Q flow enable
load
ENABLE
CLKSOURCE
STCTRL
COUNTFLAG TICKINT
System Tick
interrupt
[1] Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.
23.5.1 System Timer Control and status register (STCTRL - 0xE000 E010)
The STCTRL register contains control information for the System Tick Timer, and provides
a status flag.
Table 439. System Timer Control and status register (STCTRL - 0xE000 E010) bit description
Bit Symbol Description Reset value
0 ENABLE System Tick counter enable. When 1, the counter is enabled. When 0, 0
the counter is disabled.
1 TICKINT System Tick interrupt enable. When 1, the System Tick interrupt is 0
enabled. When 0, the System Tick interrupt is disabled. When enabled,
the interrupt is generated when the System Tick counter counts down to
0.
2 CLKSOURCE System Tick clock source selection. When 1, the CPU clock is selected. 1
When 0, the external clock pin (STCLK) is selected.
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Table 439. System Timer Control and status register (STCTRL - 0xE000 E010) bit description
Bit Symbol Description Reset value
15:3 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
16 COUNTFLAG System Tick counter flag. This flag is set when the System Tick counter 0
counts down to 0, and is cleared by reading this register.
31:17 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 440. System Timer Reload value register (STRELOAD - 0xE000 E014) bit description
Bit Symbol Description Reset value
23:0 RELOAD This is the value that is loaded into the System Tick counter when it 0
counts down to 0.
31:24 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
Table 441. System Timer Current value register (STCURR - 0xE000 E018) bit description
Bit Symbol Description Reset value
23:0 CURRENT Reading this register returns the current value of the System Tick 0
counter. Writing any value clears the System Tick counter and the
COUNTFLAG bit in STCTRL.
31:24 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
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Table 442. System Timer Calibration value register (STCALIB - 0xE000 E01C) bit description
Bit Symbol Value Description Reset value
23:0 TENMS Reload value to get a 10 millisecond System Tick underflow rate when running 0x0F 423F
at 100 MHz. This value initialized at reset with a factory supplied value selected
for the LPC17xx. The provided values of TENMS, SKEW, and NOREF are
applicable only when using a CPU clock or external STCLK source of 100 MHz.
29:24 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
30 SKEW Indicates whether the TENMS value will generate a precise 10 millisecond time, 0
or an approximation. This bit is initialized at reset with a factory supplied value
selected for the LPC17xx. See the description of TENMS above.
When 0, the value of TENMS is considered to be precise. When 1, the value of
TENMS is not considered to be precise.
31 NOREF Indicates whether an external reference clock is available. This bit is initialized 0
at reset with a factory supplied value selected for the LPC17xx. See the
description of TENMS above.
When 0, a separate reference clock is available. When 1, a separate reference
clock is not available.
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Example 1)
This example is for the System Tick Timer running from the CPU clock (cclk), which is
100 MHz.
STCTRL = 7. This enables the timer and its interrupt, and selects cclk as the clock source.
Example 2)
This example is for the System Tick Timer running from the CPU clock (cclk), which is
80 MHz.
STCTRL = 7. This enables the timer and its interrupt, and selects cclk as the clock source.
Example 3)
This example is for the CPU clock (cclk) is taken from the Internal RC Oscillator (IRC),
factory trimmed to 4 MHz.
STCTRL = 7. This enables the timer and its interrupt, and selects cclk as the clock source.
In this case, there is no rounding error, so the result is as accurate as the IRC.
Example 4)
This example is for the System Tick Timer running from an external clock source (the
STCLK pin), which in this case happens to be 32.768 kHz.
STCTRL = 3. This enables the timer and its interrupt, and selects the STCLK pin as the
clock source. STCLK must be selected as the function of the relevant pin. See
Section 8.5.6.
In this case, there is rounding error, so the interrupt rate will drift slightly relative to the
input frequency.
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24.2 Features
• Counter or Timer operation (may use the peripheral clock or one of the capture inputs
as the clock source).
• Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must "release" new match values before they can
become effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit prescaler.
• Two 32-bit capture channels take a snapshot of the timer value when an input signal
transitions. A capture event may also optionally generate an interrupt.
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24.3 Description
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC17xx. The Timer is designed to count
cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other
actions when specified timer values occur, based on seven match registers. The PWM
function is in addition to these features, and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the PWMMR0 match register controls the PWM cycle rate. The other match
registers control the two PWM edge positions. Additional double edge controlled PWM
outputs require only two match registers each, since the repetition rate is the same for all
PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
Figure 119 shows the block diagram of the PWM. The portions that have been added to
the standard timer block are on the right hand side and at the top of the diagram.
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MATCH
SHADOW REGISTER 0
REGISTER 0
LOAD ENABLE
MATCH
REGISTER 1 SHADOW REGISTER 1
LOAD ENABLE
MATCH
REGISTER 2 SHADOW REGISTER 2
LOAD ENABLE
MATCH
REGISTER 3 SHADOW REGISTER 3
LOAD ENABLE
MATCH
SHADOW REGISTER 4
Match 0 PWM1
REGISTER 4 S Q
LOAD ENABLE
MATCH
REGISTER 5 SHADOW REGISTER 5
Match 1 PWMENA1
LOAD ENABLE R EN
MATCH
REGISTER 6 SHADOW REGISTER 6
LOAD ENABLE PWMSEL2
PWM2
MUX S Q
Match 2 PWMENA2
R EN
Match 0
PWMSEL3
LOAD ENABLE REGISTER CLEAR
PWM3
MUX S Q
PWMSEL6
CAPTURE CONTROL REGISTER
PWM6
MUX S Q
CAPTURE REGISTER 0 CSN
Match 6 PWMENA6
TIMER COUNTER
CAPTURE REGISTER 1 R EN
RESERVED
CE
RESERVED
TCI
PRESCALE COUNTER PWMENA1..6 PWMSEL2..6
master
disable reset enable MAXVAL
TIMER CONTROL REGISTER PRESCALE REGISTER PWM CONTROL REGISTER
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24.4 Sample waveform with rules for single and double edge control
A sample of how PWM values relate to waveform outputs is shown in Figure 120. PWM
output logic is shown in Figure 119 that allows selection of either single or double edge
controlled PWM outputs via the muxes controlled by the PWMSELn bits. The match
register selections for various PWM outputs is shown in Table 443. This implementation
supports up to N-1 single edge PWM outputs or (N-1)/2 double edge PWM outputs, where
N is the number of match registers that are implemented. PWM types can be mixed if
desired.
PWM2
PWM4
PWM5
1 27 41 53 65 78 100
(counter is reset)
The waveforms below show a single PWM cycle and demonstrate PWM outputs under the
following conditions:
The timer is configured for PWM mode (counter resets to 1).
Match 0 is configured to reset the timer/counter when a match event occurs.
All PWM related Match registers are configured for toggle on match.
Control bits PWMSEL2 and PWMSEL4 are set.
The Match register values are as follows:
MR0 = 100 (PWM rate)
MR1 = 41, MR2 = 78 (PWM2 output)
MR3 = 53, MR4 = 27 (PWM4 output)
MR5 = 65 (PWM5 output)
Fig 120. Sample PWM waveforms
[1] Identical to single edge mode in this case since Match 0 is the neighboring match register. Essentially,
PWM1 cannot be a double edged output.
[2] It is generally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it
would reduce the number of double edge PWM outputs that are possible. Using PWM 2, PWM4, and
PWM6 for double edge PWM outputs provides the most pairings.
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1. The match values for the next PWM cycle are used at the end of a PWM cycle (a time
point which is coincident with the beginning of the next PWM cycle), except as noted
in rule 3.
2. A match value equal to 0 or the current PWM rate (the same as the Match channel 0
value) have the same effect, except as noted in rule 3. For example, a request for a
falling edge at the beginning of the PWM cycle has the same effect as a request for a
falling edge at the end of a PWM cycle.
3. When match values are changing, if one of the "old" match values is equal to the
PWM rate, it is used again once if the neither of the new match values are equal to 0
or the PWM rate, and there was no old match value equal to 0.
4. If both a set and a clear of a PWM output are requested at the same time, clear takes
precedence. This can occur when the set and clear match values are the same as in,
or when the set or clear value equals 0 and the other value equals the PWM rate.
5. If a match value is out of range (i.e. greater than the PWM rate value), no match event
occurs and that match channel has no effect on the output. This means that the PWM
output will remain always in one state, allowing always low, always high, or
"no change" outputs.
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[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 446: PWM Interrupt Register (PWM1IR - address 0x4001 8000) bit description
Bit Symbol Description Reset
Value
0 PWMMR0 Interrupt Interrupt flag for PWM match channel 0. 0
1 PWMMR1 Interrupt Interrupt flag for PWM match channel 1. 0
2 PWMMR2 Interrupt Interrupt flag for PWM match channel 2. 0
3 PWMMR3 Interrupt Interrupt flag for PWM match channel 3. 0
4 PWMCAP0 Interrupt flag for capture input 0 0
Interrupt
5 PWMCAP1 Interrupt flag for capture input 1. 0
Interrupt
7:6 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
8 PWMMR4 Interrupt Interrupt flag for PWM match channel 4. 0
9 PWMMR5 Interrupt Interrupt flag for PWM match channel 5. 0
10 PWMMR6 Interrupt Interrupt flag for PWM match channel 6. 0
31:11 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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Table 447. PWM Timer Control Register (PWM1TCR address 0x4001 8004) bit description
Bit Symbol Value Description Reset
Value
0 Counter Enable 1 The PWM Timer Counter and PWM Prescale Counter are enabled for counting. 0
0 The counters are disabled.
1 Counter Reset 1 The PWM Timer Counter and the PWM Prescale Counter are synchronously reset 0
on the next positive edge of PCLK. The counters remain reset until this bit is
returned to zero.
0 Clear reset.
2 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
3 PWM Enable 1 PWM mode is enabled (counter resets to 1). PWM mode causes the shadow 0
registers to operate in connection with the Match registers. A program write to a
Match register will not have an effect on the Match result until the corresponding bit
in PWMLER has been set, followed by the occurrence of a PWM Match 0 event.
Note that the PWM Match register that determines the PWM rate (PWM Match
Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a
Match event will not occur to cause shadow register contents to become effective.
0 Timer mode is enabled (counter resets to 0).
31:4 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
Table 448. PWM Count control Register (PWM1CTCR - address 0x4001 8070) bit description
Bit Symbol Value Description Reset
Value
1:0 Counter/ 00 Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale 00
Timer Mode Register.
01 Counter Mode: the TC is incremented on rising edges of the PCAP input selected by
bits 3:2.
10 Counter Mode: the TC is incremented on falling edges of the PCAP input selected by
bits 3:2.
11 Counter Mode: the TC is incremented on both edges of the PCAP input selected by
bits 3:2.
3:2 Count Input When bits 1:0 of this register are not 00, these bits select which PCAP pin which 00
Select carries the signal used to increment the TC.
00 PCAP1.0
01 PCAP1.1 (Other combinations are reserved)
31:4 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description
Bit Symbol Value Description Reset
Value
0 PWMMR0I 1 Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in 0
the PWMTC.
0 This interrupt is disabled.
1 PWMMR0R 1 Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it. 0
0 This feature is disabled.
2 PWMMR0S 1 Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be 0
set to 0 if PWMMR0 matches the PWMTC.
0 This feature is disabled
3 PWMMR1I 1 Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in 0
the PWMTC.
0 This interrupt is disabled.
4 PWMMR1R 1 Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it. 0
0 This feature is disabled.
5 PWMMR1S 1 Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be 0
set to 0 if PWMMR1 matches the PWMTC.
0 This feature is disabled.
6 PWMMR2I 1 Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in 0
the PWMTC.
0 This interrupt is disabled.
7 PWMMR2R 1 Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it. 0
0 This feature is disabled.
8 PWMMR2S 1 Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be 0
set to 0 if PWMMR2 matches the PWMTC.
0 This feature is disabled
9 PWMMR3I 1 Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in 0
the PWMTC.
0 This interrupt is disabled.
10 PWMMR3R 1 Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. 0
0 This feature is disabled
11 PWMMR3S 1 Stop on PWMMR3: The PWMTC and PWMPC will be stopped and PWMTCR[0] will 0
be set to 0 if PWMMR3 matches the PWMTC.
0 This feature is disabled
12 PWMMR4I 1 Interrupt on PWMMR4: An interrupt is generated when PWMMR4 matches the value 0
in the PWMTC.
0 This interrupt is disabled.
13 PWMMR4R 1 Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it. 0
0 This feature is disabled.
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Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description
Bit Symbol Value Description Reset
Value
14 PWMMR4S 1 Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be 0
set to 0 if PWMMR4 matches the PWMTC.
0 This feature is disabled
15 PWMMR5I 1 Interrupt on PWMMR5: An interrupt is generated when PWMMR5 matches the value 0
in the PWMTC.
0 This interrupt is disabled.
16 PWMMR5R 1 Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it. 0
0 This feature is disabled.
17 PWMMR5S 1 Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be 0
set to 0 if PWMMR5 matches the PWMTC.
0 This feature is disabled
18 PWMMR6I 1 Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in 0
the PWMTC.
0 This interrupt is disabled.
19 PWMMR6R 1 Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it. 0
0 This feature is disabled.
20 PWMMR6S 1 Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be 0
set to 0 if PWMMR6 matches the PWMTC.
31:21 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
Table 450: PWM Capture Control Register (PWM1CCR - address 0x4001 8028) bit description
Bit Symbol Value Description Reset
Value
0 Capture on 0 This feature is disabled. 0
CAPn.0 rising 1 A synchronously sampled rising edge on the CAPn.0 input will cause CR0 to be
edge loaded with the contents of the TC.
1 Capture on 0 This feature is disabled. 0
CAPn.0 falling 1 A synchronously sampled falling edge on CAPn.0 will cause CR0 to be loaded with
edge the contents of TC.
2 Interrupt on 0 This feature is disabled. 0
CAPn.0 event 1 A CR0 load due to a CAPn.0 event will generate an interrupt.
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Table 450: PWM Capture Control Register (PWM1CCR - address 0x4001 8028) bit description
Bit Symbol Value Description Reset
Value
3 Capture on 0 This feature is disabled. 0
CAPn.1rising 1 A synchronously sampled rising edge on the CAPn.1 input will cause CR1 to be
edge loaded with the contents of the TC.
4 Capture on 0 This feature is disabled. 0
CAPn.1falling 1 A synchronously sampled falling edge on CAPn.1 will cause CR1 to be loaded with
edge the contents of TC.
5 Interrupt on 0 This feature is disabled. 0
CAPn.1 event 1 A CR1 load due to a CAPn.1 event will generate an interrupt.
31:6 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
Table 451: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description
Bit Symbol Value Description Reset
Value
1:0 Unused Unused, always zero. NA
2 PWMSEL2 1 Selects double edge controlled mode for the PWM2 output. 0
0 Selects single edge controlled mode for PWM2.
3 PWMSEL3 1 Selects double edge controlled mode for the PWM3 output. 0
0 Selects single edge controlled mode for PWM3.
4 PWMSEL4 1 Selects double edge controlled mode for the PWM4 output. 0
0 Selects single edge controlled mode for PWM4.
5 PWMSEL5 1 Selects double edge controlled mode for the PWM5 output. 0
0 Selects single edge controlled mode for PWM5.
6 PWMSEL6 1 Selects double edge controlled mode for the PWM6 output. 0
0 Selects single edge controlled mode for PWM6.
8:7 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
9 PWMENA1 1 The PWM1 output enabled. 0
0 The PWM1 output disabled.
10 PWMENA2 1 The PWM2 output enabled. 0
0 The PWM2 output disabled.
11 PWMENA3 1 The PWM3 output enabled. 0
0 The PWM3 output disabled.
12 PWMENA4 1 The PWM4 output enabled. 0
0 The PWM4 output disabled.
13 PWMENA5 1 The PWM5 output enabled. 0
0 The PWM5 output disabled.
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Table 451: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description
Bit Symbol Value Description Reset
Value
14 PWMENA6 1 The PWM6 output enabled. 0
0 The PWM6 output disabled.
31:15 Unused Unused, always zero. NA
When a PWM Match 0 event occurs (normally also resetting the timer in PWM mode), the
contents of shadow registers will be transferred to the shadow registers if the
corresponding bit in the Latch Enable Register has been set. At that point, the new values
will take effect and determine the course of the next PWM cycle. Once the transfer of new
values has taken place, all bits of the LER are automatically cleared. Until the
corresponding bit in the PWMLER is set and a PWM Match 0 event occurs, any value
written to the PWM Match registers has no effect on PWM operation.
For example, if PWM2 is configured for double edge operation and is currently running, a
typical sequence of events for changing the timing would be:
The order of writing the two PWM Match registers is not important, since neither value will
be used until after the write to LER. This insures that both values go into effect at the
same time, if that is required. A single value may be altered in the same way if needed.
The function of each of the bits in the LER is shown in Table 452.
Table 452: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description
Bit Symbol Description Reset
Value
0 Enable PWM Writing a one to this bit allows the last value written to the PWM Match 0 register to be 0
Match 0 Latch become effective when the timer is next reset by a PWM Match event. See Section 24.6.4
“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.
1 Enable PWM Writing a one to this bit allows the last value written to the PWM Match 1 register to be 0
Match 1 Latch become effective when the timer is next reset by a PWM Match event. See Section 24.6.4
“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.
2 Enable PWM Writing a one to this bit allows the last value written to the PWM Match 2 register to be 0
Match 2 Latch become effective when the timer is next reset by a PWM Match event. See Section 24.6.4
“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.
3 Enable PWM Writing a one to this bit allows the last value written to the PWM Match 3 register to be 0
Match 3 Latch become effective when the timer is next reset by a PWM Match event. See Section 24.6.4
“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.
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Table 452: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description
Bit Symbol Description Reset
Value
4 Enable PWM Writing a one to this bit allows the last value written to the PWM Match 4 register to be 0
Match 4 Latch become effective when the timer is next reset by a PWM Match event. See Section 24.6.4
“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.
5 Enable PWM Writing a one to this bit allows the last value written to the PWM Match 5 register to be 0
Match 5 Latch become effective when the timer is next reset by a PWM Match event. See Section 24.6.4
“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.
6 Enable PWM Writing a one to this bit allows the last value written to the PWM Match 6 register to be 0
Match 6 Latch become effective when the timer is next reset by a PWM Match event. See Section 24.6.4
“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.
31:7 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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25.1 Introduction
The Motor Control PWM (MCPWM) is optimized for three-phase AC and DC motor control
applications, but can be used in many other applications that need timing, counting,
capture, and comparison.
25.2 Description
The MCPWM contains three independent channels, each including:
Input pins MCI0-2 can trigger TC capture or increment a channel’s TC. A global Abort
input can force all of the channels into “A passive” state and cause an interrupt.
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PCLK
MCI0-2
MCCNTCON
MCCAPCON
RT0 cntl RT1 cntl RT2 cntl
interrupt
logic
MCABORT
MCINTEN MCINTF
ACMODE mux ACMODE mux
MCCON
MCCP global output control
MCABORT
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The MCPWM includes 3 channels, each of which controls a pair of outputs that in turn can
control something off-chip, like one set of coils in a motor. Each channel includes a
Timer/Counter (TC) register that is incremented by a processor clock (timer mode) or by
an input pin (counter mode).
Each channel has a Limit register that is compared to the TC value, and when a match
occurs the TC is “recycled” in one of two ways. In “edge-aligned mode” the TC is reset to
0, while in “centered mode” a match switches the TC into a state in which it decrements on
each processor clock or input pin transition until it reaches 0, at which time it starts
counting up again.
Each channel also includes a Match register that holds a smaller value than the Limit
register. In edge-aligned mode the channel’s outputs are switched whenever the TC
matches either the Match or Limit register, while in center-aligned mode they are switched
only when it matches the Match register.
So the Limit register controls the period of the outputs, while the Match register controls
how much of each period the outputs spend in each state. Having a small value in the
Limit register minimizes “ripple” if the output is integrated into a voltage, and allows the
MCPWM to control devices that operate at high speed.
The “downside” of small values in the Limit register is that they reduce the resolution of
the duty cycle controlled by the Match register. If you have 8 in the Limit register, the
Match register can only select the duty cycle among 0%, 12.5%, 25%, …, 87.5%, or
100%. In general, the resolution of each step in the Match value is 1 divided by the Limit
value.
This trade-off between resolution and period/frequency is inherent in the design of pulse
width modulators.
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The Capture registers (MCCAP) are read-only, and the write-only MCCAP_CLR address
can be used to clear one or more of them. All the other MCPWM registers (MCTIM,
MCPER, MCPW, MCDEADTIME, and MCCP) are normal read-write registers.
Table 454. Motor Control Pulse Width Modulator (MCPWM) register map
Name Description Access Reset value Address
MCCON PWM Control read address RO 0 0x400B 8000
MCCON_SET PWM Control set address WO - 0x400B 8004
MCCON_CLR PWM Control clear address WO - 0x400B 8008
MCCAPCON Capture Control read address RO 0 0x400B 800C
MCCAPCON_SET Capture Control set address WO - 0x400B 8010
MCCAPCON_CLR Event Control clear address WO - 0x400B 8014
MCTC0 Timer Counter register, channel 0 R/W 0 0x400B 8018
MCTC1 Timer Counter register, channel 1 R/W 0 0x400B 801C
MCTC2 Timer Counter register, channel 2 R/W 0 0x400B 8020
MCLIM0 Limit register, channel 0 R/W 0xFFFF FFFF 0x400B 8024
MCLIM1 Limit register, channel 1 R/W 0xFFFF FFFF 0x400B 8028
MCLIM2 Limit register, channel 2 R/W 0xFFFF FFFF 0x400B 802C
MCMAT0 Match register, channel 0 R/W 0xFFFF FFFF 0x400B 8030
MCMAT1 Match register, channel 1 R/W 0xFFFF FFFF 0x400B 8034
MCMAT2 Match register, channel 2 R/W 0xFFFF FFFF 0x400B 8038
MCDT Dead time register R/W 0x3FFF FFFF 0x400B 803C
MCCP Commutation Pattern register R/W 0 0x400B 8040
MCCAP0 Capture register, channel 0 RO 0 0x400B 8044
MCCAP1 Capture register, channel 1 RO 0 0x400B 8048
MCCAP2 Capture register, channel 2 RO 0 0x400B 804C
MCINTEN Interrupt Enable read address RO 0 0x400B 8050
MCINTEN_SET Interrupt Enable set address WO - 0x400B 8054
MCINTEN_CLR Interrupt Enable clear address WO - 0x400B 8058
MCCNTCON Count Control read address RO 0 0x400B 805C
MCCNTCON_SET Count Control set address WO - 0x400B 8060
MCCNTCON_CLR Count Control clear address WO - 0x400B 8064
MCINTF Interrupt flags read address RO 0 0x400B 8068
MCINTF_SET Interrupt flags set address WO - 0x400B 806C
MCINTF_CLR Interrupt flags clear address WO - 0x400B 8070
MCCAP_CLR Capture clear address WO - 0x400B 8074
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Table 455. MCPWM Control read address (MCCON - 0x400B 8000) bit description
Bit Symbol Value Description Reset
value
0 RUN0 Stops/starts timer channel 0. 0
0 Stop.
1 Run.
1 CENTER0 Edge/center aligned operation for channel 0. 0
0 Edge-aligned.
1 Center-aligned.
2 POLA0 Selects polarity of the MCOA0 and MCOB0 pins. 0
0 Passive state is LOW, active state is HIGH.
1 Passive state is HIGH, active state is LOW.
3 DTE0 Controls the dead-time feature for channel 0. 0
0 Dead-time disabled.
1 Dead-time enabled.
4 DISUP0 Enable/disable updates of functional registers for channel 0 (see Section 25.8.2, 0
Section 25.7.6.1).
0 Functional registers are updated from the write registers at the end of each PWM
cycle.
1 Functional registers remain the same as long as the timer is running.
7:5 - - Reserved.
8 RUN1 Stops/starts timer channel 1. 0
0 Stop.
1 Run.
9 CENTER1 Edge/center aligned operation for channel 1. 0
0 Edge-aligned.
1 Center-aligned.
10 POLA1 Selects polarity of the MCOA1 and MCOB1 pins. 0
0 Passive state is LOW, active state is HIGH.
1 Passive state is HIGH, active state is LOW.
11 DTE1 Controls the dead-time feature for channel 1. 0
0 Dead-time disabled.
1 Dead-time enabled.
12 DISUP1 Enable/disable updates of functional registers for channel 1 (see Section 25.8.2, 0
Section 25.7.6.1).
0 Functional registers are updated from the write registers at the end of each PWM
cycle.
1 Functional registers remain the same as long as the timer is running.
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Table 455. MCPWM Control read address (MCCON - 0x400B 8000) bit description
Bit Symbol Value Description Reset
value
15:13 - - Reserved. 0
16 RUN2 Stops/starts timer channel 2. 0
0 Stop.
1 Run.
17 CENTER2 Edge/center aligned operation for channel 2. 0
0 Edge-aligned.
1 Center-aligned.
18 POLA2 Selects polarity of the MCOA2 and MCOB2 pins. 0
0 Passive state is LOW, active state is HIGH.
1 Passive state is HIGH, active state is LOW.
19 DTE2 Controls the dead-time feature for channel 1. 0
0 Dead-time disabled.
1 Dead-time enabled.
20 DISUP2 Enable/disable updates of functional registers for channel 2 (see Section 25.8.2, 0
Section 25.7.6.1).
0 Functional registers are updated from the write registers at the end of each PWM
cycle.
1 Functional registers remain the same as long as the timer is running.
28:21 - - Reserved.
29 INVBDC Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set
to 1 only in 3-phase DC mode.
0 The MCOB outputs have opposite polarity from the MCOA outputs (aside from
dead time).
1 The MCOB outputs have the same basic polarity as the MCOA outputs. (see
Section 25.8.6)
30 ACMODE 3-phase AC mode select (see Section 25.8.7). 0
0 3-phase AC-mode off: Each PWM channel uses its own timer-counter and period
register.
1 3-phase AC-mode on: All PWM channels use the timer-counter and period register
of channel 0.
31 DCMODE 3-phase DC mode select (see Section 25.8.6). 0
0 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)
1 3-phase DC mode on: The internal MCOA0 output is routed through the MCCP (i.e.
a mask) register to all six PWM outputs.
Table 456. MCPWM Control set address (MCCON_SET - 0x400B 8004) bit description
Bit Description
31:0 Writing ones to this address sets the corresponding bits in the MCCON register. See Table 455.
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Table 457. MCPWM Control clear address (MCCON_CLR - 0x400B 8008) bit description
Bit Description
31:0 Writing ones to this address clears the corresponding bits in the MCCON register. See Table 455.
Table 458. MCPWM Capture Control read address (MCCAPCON - 0x400B 800C) bit description
Bit Symbol Description Reset
Value
0 CAP0MCI0_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. 0
1 CAP0MCI0_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. 0
2 CAP0MCI1_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. 0
3 CAP0MCI1_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. 0
4 CAP0MCI2_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. 0
5 CAP0MCI2_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. 0
6 CAP1MCI0_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. 0
7 CAP1MCI0_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. 0
8 CAP1MCI1_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. 0
9 CAP1MCI1_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. 0
10 CAP1MCI2_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. 0
11 CAP1MCI2_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. 0
12 CAP2MCI0_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. 0
13 CAP2MCI0_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. 0
14 CAP2MCI1_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. 0
15 CAP2MCI1_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. 0
16 CAP2MCI2_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. 0
17 CAP2MCI2_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. 0
18 RT0 If this bit is 1, TC0 is reset by a channel 0 capture event. 0
19 RT1 If this bit is 1, TC1 is reset by a channel 1 capture event. 0
20 RT2 If this bit is 1, TC2 is reset by a channel 2 capture event. 0
21 HNFCAP0 Hardware noise filter: if this bit is 1, channel 0 capture events are delayed as described in 0
Section 25.8.4.
22 HNFCAP1 Hardware noise filter: if this bit is 1, channel 1 capture events are delayed as described in 0
Section 25.8.4.
23 HNFCAP2 Hardware noise filter: if this bit is 1, channel 2 capture events are delayed as described in 0
Section 25.8.4.
31:24 - Reserved. -
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Table 459. MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) bit description
Bit Description
31:0 Writing ones to this address sets the corresponding bits in the MCCAPCON register. See Table 458.
Table 460. MCPWM Capture control clear register (MCCAPCON_CLR - address 0x400B 8014) bit description
Bit Description
31:0 Writing ones to this address clears the corresponding bits in the MCCAPCON register. See Table 458.
All MCPWM interrupt registers contain one bit for each source as shown in Table 462.
Table 463. MCPWM Interrupt Enable read address (MCINTEN - 0x400B 8050) bit description
Bit Value Description Reset
value
31:0 See Table 462 for the bit allocation. 0
1 Interrupt enabled.
0 Interrupt disabled.
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Table 464. PWM interrupt enable set register (MCINTEN_SET - address 0x400B 8054) bit
description
Bit Description
31:0 Writing ones to this address sets the corresponding bits in MCINTEN, thus enabling
interrupts. See Table 462.
Table 465. PWM interrupt enable clear register (MCINTEN_CLR - address 0x400B 8058) bit
description
Bit Description
31:0 Writing ones to this address clears the corresponding bits in MCINTEN, thus disabling
interrupts. See Table 462.
Table 466. MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068) bit description
Bit Value Description Reset
value
31:0 See Table 462 for the bit allocation. 0
1 If the corresponding bit in MCINTEN is 1, the MCPWM module is asserting its interrupt request to
the Interrupt Controller.
0 This interrupt source is not contributing to the MCPWM interrupt request.
Table 467. MCPWM Interrupt Flags set address (PWMINTF_SET - 0x400B 806C) bit
description
Bit Description
31:0 Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF
register, thus possibly simulating hardware interrupt(s). See Table 462.
Table 468. MCPWM Interrupt Flags clear address (PWMINTF_CLR - 0x400B 8070) bit
description
Bit Description
31:0 Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF
register, thus clearing the corresponding interrupt request(s). See Table 462.
This address is read-only. To set or clear the register bits, write ones to the
MCCNTCON_SET or MCCNTCON_CLR address.
Table 469. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description
Bit Symbol Value Description Reset
Value
0 TC0MCI0_RE 1 If MODE0 is 1, counter 0 advances on a rising edge on MCI0. 0
0 A rising edge on MCI0 does not affect counter 0.
1 TC0MCI0_FE 1 If MODE0 is 1, counter 0 advances on a falling edge on MCI0. 0
0 A falling edge on MCI0 does not affect counter 0.
2 TC0MCI1_RE 1 If MODE0 is 1, counter 0 advances on a rising edge on MCI1. 0
0 A rising edge on MCI1 does not affect counter 0.
3 TC0MCI1_FE 1 If MODE0 is 1, counter 0 advances on a falling edge on MCI1. 0
0 A falling edge on MCI1 does not affect counter 0.
4 TC0MCI2_RE 1 If MODE0 is 1, counter 0 advances on a rising edge on MCI2. 0
0 A rising edge on MCI0 does not affect counter 0.
5 TC0MCI2_FE 1 If MODE0 is 1, counter 0 advances on a falling edge on MCI2. 0
0 A falling edge on MCI0 does not affect counter 0.
6 TC1MCI0_RE 1 If MODE1 is 1, counter 1 advances on a rising edge on MCI0. 0
0 A rising edge on MCI0 does not affect counter 1.
7 TC1MCI0_FE 1 If MODE1 is 1, counter 1 advances on a falling edge on MCI0. 0
0 A falling edge on MCI0 does not affect counter 1.
8 TC1MCI1_RE 1 If MODE1 is 1, counter 1 advances on a rising edge on MCI1. 0
0 A rising edge on MCI1 does not affect counter 1.
9 TC1MCI1_FE 1 If MODE1 is 1, counter 1 advances on a falling edge on MCI1. 0
0 A falling edge on MCI0 does not affect counter 1.
10 TC1MCI2_RE 1 If MODE1 is 1, counter 1 advances on a rising edge on MCI2. 0
0 A rising edge on MCI2 does not affect counter 1.
11 TC1MCI2_FE 1 If MODE1 is 1, counter 1 advances on a falling edge on MCI2. 0
0 A falling edge on MCI2 does not affect counter 1.
12 TC2MCI0_RE 1 If MODE2 is 1, counter 2 advances on a rising edge on MCI0. 0
0 A rising edge on MCI0 does not affect counter 2.
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Table 469. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description
Bit Symbol Value Description Reset
Value
13 TC2MCI0_FE 1 If MODE2 is 1, counter 2 advances on a falling edge on MCI0. 0
0 A falling edge on MCI0 does not affect counter 2.
14 TC2MCI1_RE 1 If MODE2 is 1, counter 2 advances on a rising edge on MCI1. 0
0 A rising edge on MCI1 does not affect counter 2.
15 TC2MCI1_FE 1 If MODE2 is 1, counter 2 advances on a falling edge on MCI1. 0
0 A falling edge on MCI1 does not affect counter 2.
16 TC2MCI2_RE 1 If MODE2 is 1, counter 2 advances on a rising edge on MCI2. 0
0 A rising edge on MCI2 does not affect counter 2.
17 TC2MCI2_FE 1 If MODE2 is 1, counter 2 advances on a falling edge on MCI2. 0
0 A falling edge on MCI2 does not affect counter 2.
28:18 - - Reserved. -
29 CNTR0 1 Channel 0 is in counter mode. 0
0 Channel 0 is in timer mode.
30 CNTR1 1 Channel 1 is in counter mode. 0
0 Channel 1 is in timer mode.
31 CNTR2 1 Channel 2 is in counter mode. 0
0 Channel 2 is in timer mode.
Table 470. MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060) bit description
Bit Description
31:0 Writing one(s) to this write-only address sets the corresponding bit(s) in the MCCNTCON register. See Table 469.
Table 471. MCPWM Count Control clear address (MCCAPCON_CLR - 0x400B 8064) bit description
Bit Description
31:0 Writing one(s) to this write-only address clears the corresponding bit(s) in the MCCNTCON register. See
Table 469.
A TC register can be read at any time. In order to write to the TC register, its channel must
be stopped. If not, the write will not take place, no exception is generated.
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Table 472. MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018, 0x400B 801C, 0x400B 8020) bit description
Bit Symbol Description Reset value
31:0 MCTC0/1/2 Timer/Counter values for channels 0, 1, 2. 0
25.7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028,
0x400B 802C)
These registers hold the limiting values for timer/counters 0-2. When a timer/counter
reaches its corresponding limiting value: 1) in edge-aligned mode, it is reset and starts
over at 0; 2) in center-aligned mode, it begins counting down until it reaches 0, at which
time it begins counting up again.
If the channel’s CENTER bit in MCCON is 0 selecting edge-aligned mode, the match
between TC and LIM switches the channel’s A output from “active” to “passive” state. If
the channel’s CENTER and DTE bits in MCCON are both 0, the match simultaneously
switches the channel’s B output from “passive” to “active” state.
If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s B
output switches from “passive” to “active” state.
Table 473. MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028, 0x400B 802C) bit description
Bit Symbol Description Reset value
31:0 MCLIM0/1/2 Limit values for TC0, 1, 2. 0xFFFF FFFF
Simultaneous update of the Limit and Match registers can be achieved by writing the
MCLIMx and MCMATx registers and then clearing the DISUPx bits in the MCCON register
(see Table 457). The simultaneous update will occur at the beginning of the next PWM
cycle (also see Section 25.8.2).
Remark: In timer mode, the period of a channel’s modulated MCO outputs is determined
by its Limit register, and the pulse width at the start of the period is determined by its
Match register. You can consider the Limit register to be a “Period register” and the Match
register to be a “Pulse Width register”.
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25.7.7 MCPWM Match 0-2 registers (MCMAT0-2 - 0x400B 8030, 0x400B 8034,
0x400B 8038)
These registers also have “write” and “operating” versions as described above for the
Limit registers, and the operating registers are also compared to the channels’ TCs. See
25.7.6 above for details of reading and writing both Limit and Match registers.
The Match and Limit registers control the MCO0-2 outputs. If a Match register is to have
any effect on its channel’s operation, it must contain a smaller value than the
corresponding Limit register.
Table 474. MCPWM Match 0-2 registers (MCMAT0-2 - addresses 0x400B 8030, 0x400B 8034, 0x400B 8038) bit
description
Bit Symbol Description Reset value
31:0 MCMAT0/1/2 Match values for TC0, 1, 2. 0xFFFF FFFF
If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A
output switches from “passive” to “active” state.
If the channel’s CENTER and DTE bits are both 1, a match between TC and MAT triggers
the channel’s deadtime counter to begin counting -- when the deadtime counter expires,
the channel’s B output switches from “passive” to “active” if the TC was counting up at the
time of the match, and the channel’s A output switches from “passive” to “active” if the TC
was counting down at the time of the match.
To lock a channel’s MCO outputs at the opposite state, “A active, B passive”, simply write
0 to its Match register.
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The motivation for the dead-time feature is that power transistors, like those driven by the
A and B outputs in a motor-control application, take longer to fully turn off than they take to
start to turn on. If the A and B transistors are ever turned on at the same time, a wasteful
and damaging current will flow between the power rails through the transistors. In such
applications, the dead-time register should be programmed with the number of PCLK
periods that is greater than or equal to the transistors’ maximum turn-off time minus their
minimum turn-on time.
Table 475. MCPWM Dead-time register (MCDT - address 0x400B 803C) bit description
Bit Symbol Description Reset value
9:0 DT0 Dead time for channel 0.[1] 0x3FF
19:10 DT1 Dead time for channel 1.[2] 0x3FF
29:20 DT2 Dead time for channel 2.[2] 0x3FF
31:30 - reserved
[1] If ACMODE is 1 selecting AC-mode, this field controls the dead time for all three channels.
[2] If ACMODE is 0.
Table 476. MCPWM Commutation Pattern register (MCCP - address 0x400B 8040) bit description
Bit Symbol Description Reset value
0 CCPA0 0 = MCOA0 passive, 1 = internal MCOA0. 0
1 CCPB0 0 = MCOB0 passive, 1 = MCOB0 tracks internal MCOA0. 0
2 CCPA1 0 = MCOA1 passive, 1 = MCOA1 tracks internal MCOA0. 0
3 CCPB1 0 = MCOB1 passive, 1 = MCOB1 tracks internal MCOA0. 0
4 CCPA2 0 = MCOA2 passive, 1 = MCOA2 tracks internal MCOA0. 0
5 CCPB2 0 = MCOB2 passive, 1 = MCOB2 tracks internal MCOA0. 0
31:6 - Reserved.
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25.7.10.1 MCPWM Capture read addresses (MCCAP0-2 - 0x400B 8044, 0x400B 8048,
0x400B 804C)
The MCCAPCON register (Table 458) allows software to select any edge(s) on any of the
MCI0-2 inputs as a capture event for each channel. When a channel’s capture event
occurs, the current TC value for that channel is stored in its read-only Capture register.
These addresses are read-only, but the underlying registers can be cleared by writing to
the CAP_CLR address
Table 477. MCPWM Capture read addresses (MCCAP0/1/2 - 0x400B 8044, 0x400B 8048, 0x400B 804C) bit description
Bit Symbol Description Reset value
31:0 CAP0/1/2 TC value at a capture event for channels 0, 1, 2. 0x0000 0000
Table 478. MCPWM Capture clear address (CAP_CLR - 0x400B 8074) bit description
Bit Symbol Description
0 CAP_CLR0 Writing a 1 to this bit clears the MCCAP0 register.
1 CAP_CLR1 Writing a 1 to this bit clears the MCCAP1 register.
2 CAP_CLR2 Writing a 1 to this bit clears the MCCAP2 register.
31:3 - Reserved
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Each channel’s mapping from “active” and “passive” to “high” and “low” is programmable.
After Reset, the three A outputs are passive/low, and the B outputs are active/high.
Note: In timer mode, the period of a channel’s modulated MCO outputs is determined by
its Limit register, and the pulse width at the start of the period is determined by its Match
register. If it suits your way of thinking, consider the Limit register to be the “Period register”
and the Match register to be the “Pulse Width register”.
MCOB
MCOA POLA = 0
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MCOB
MCOA POLA = 0
Dead-time counter
When the a channel’s DTE bit is set in MCCON, the dead-time counter delays the
passive-to-active transitions of both MCO outputs. The dead-time counter starts counting
down, from the channel’s DT value (in the MCDT register) to 0, whenever the channel’s A
or B output changes from active to passive. The transition of the other output from passive
to active is delayed until the dead-time counter reaches 0. During the dead time, the
MCOA and MCOB output levels are both passive. Figure 124 shows operation in edge
aligned mode with dead time, and Figure 125 shows center-aligned operation with dead
time.
active active
passive passive
MCOB
DT DT
active active
passive passive
MCOA POLA = 0
DT DT
0 MAT LIM MAT LIM
timer reset timer reset
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active active
passive passive
MCOB
DT
active active
passive passive
MCOA POLA = 0
DT DT
0 MAT LIM MAT 0 LIM
Updating of the functional registers can be disabled by setting a channel’s DISUP bit in
the MCCON register. If the DISUP bits are set, the functional registers are not updated
until software stops the channel.
If a channel is not running when software writes to its LIM or MAT register, the functional
register is updated immediately.
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If a channel’s HNF bit in the MCCAPCON register is set to enable “noise filtering”, a
selected edge on an MCI pin starts the dead-time counter for that channel, and the
capture event actions described below are delayed until the dead-time counter reaches 0.
This function is targeted specifically for performing three-phase brushless DC motor
control with Hall sensors.
In this mode, the internal MCOA0 signal can be routed to any or all of the MCO outputs.
Each MCO output is masked by a bit in the current Commutation Pattern register MCCP. If
a bit in the MCCP register is 0, its output pin has the logic level for the passive state of
output MCOA0. The polarity of the off state is determined by the POLA0 bit.
All MCO outputs that have 1 bits in the MCCP register are controlled by the internal
MCOA0 signal.
The three MCOB output pins are inverted when the INVBDC bit is 1 in the MCCON
register. This feature accommodates bridge-drivers that have active-low inputs for the
low-side switches.
The MCCP register is implemented as a shadow register pair, so that changes to the
active commutation pattern occur at the beginning of a new PWM cycle. See 25.7.6 and
25.8.2 for more about writing and reading such registers.
Figure 126 shows sample waveforms of the MCO outputs in three-phase DC mode. Bits 1
and 3 in the MCCP register (corresponding to outputs MCOB1 and MCOB0) are set to 0
so that these outputs are masked and in the off state. Their logic level is determined by
the POLA0 bit (here, POLA0 = 0 so the passive state is logic LOW). The INVBDC bit is set
to 0 (logic level not inverted) so that the B output have the same polarity as the A outputs.
Note that this mode differs from other modes in that the MCOB outputs are not the
opposite of the MCOA outputs.
In the situation shown in Figure 126, bits 0, 2, 4, and 5 in the MCCP register are set to 1.
That means that MCOA1 and both MCO outputs for channel 2 follow the MCOA0 signal.
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MCOB2
CCPB2 = 1, on-state
MCOB0
CCPB0 = 0, off-state
CCPA0 = 1, on-state
MCOA0
POLA0 = 0, INVBDC = 0
In this mode, the value of channel 0’s TC is routed to all channels for comparison with
their MAT registers. (The LIM1-2 registers are not used.)
Each channel controls its MCO output by comparing its MAT value to TC0.
Figure 127 shows sample waveforms for the six MCO outputs in three-phase AC mode.
The POLA bits are set to 0 for all three channels, so that for all MCO outputs the active
levels are high and the passive levels are low. Each channel has a different MAT value
which is compared to the MCTC0 value. In this mode the period value is identical for all
three channels and is determined by MCLIM0. The dead-time mode is disabled.
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MCOB2
POLA2 = 0
MCOA2
MAT2 MAT2
MCOB1
POLA1 = 0
MCOA1
MAT1 MAT1
MCOB0
MCOA0 POLA0 = 0
Fig 127. Three-phase AC mode sample waveforms, edge aligned PWM mode
25.8.8 Interrupts
The MCPWM includes 10 possible interrupt sources:
Section 25.7.3 “MCPWM Interrupt registers” explains how to enable these interrupts, and
Section 25.7.2 “MCPWM Capture Control register” describes how to map edges on the
MCI0-2 inputs to “capture events” on the three channels.
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26.2 Features
This Quadrature Encoder Interface (QEI) has the following features:
26.3 Introduction
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, you can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. This quadrature encoder interface module decodes the digital pulses from a
quadrature encoder wheel to integrate position over time and determine direction of
rotation. In addition, it can capture the velocity of the encoder wheel.
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VELOCITY
RELOAD
RST VELOCITY
CAPTURE
index
RST
Ph A DIGITAL VELOCITY
QUAD CLK
Ph B FILTER COUNTER
DECODER
PCLK
encoder clock interrupt
(ENCLK_Int)
CLK
DIR POSITION
INX COUNTER
direction interrupt
(DIR_Int)
INDEX
COUNTER
index interrupt
(INX_Int)
ERR phase error interrupt
(ERR_Int)
002aad520
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This mode is determined by the SigMode bit of the QEI Configuration (QEICONF) register
(See Table 485). When the SigMode bit = 1, the quadrature decoder is bypassed and the
PhA pin functions as the direction signal and PhB pin functions as the clock signal for the
counters, etc. When the SigMode bit = 0, the PhA pin and PhB pins are decoded by the
quadrature decoder. In this mode the quadrature decoder produces the direction and
clock signals for the counters, etc. In both modes the direction signal is subject to the
effects of the direction invert (DIRINV) bit.
[1] All other state transitions are illegal and should set the ERR bit.
Interchanging of the PhA and PhB input signals are compensated by complementing the
DIR bit. When set = 1, the direction inversion bit (DIRINV) complements the DIR bit.
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Figure 129 shows how quadrature encoder signals equate to direction and count.
PhA
PhB
direction
position -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
The position integrator and velocity capture can be independently enabled. Alternatively,
the phase signals can be interpreted as a clock and direction signal as output by some
encoders.
The position counter is automatically reset on one of two conditions. Incrementing past
the maximum position value (QEIMAXPOS) will reset the position counter to zero. If the
reset on index bit (RESPI) is set, sensing the index pulse will reset the position counter to
zero.
number of edges counted in a given time period is directly proportional to the velocity of
the encoder. Setting the reset velocity bit (RESV) has the same effect as an overflow of
the velocity timer, except that the setting the RESV bit will not generate a velocity
interrupt.
The following equation converts the velocity counter value into an RPM value:
where:
• PCLK is the peripheral clock rate for the QEI block. See Section 4.7.3 for more on the
possibilities for PCLK).
• QEICAP is the captured velocity counter value for the last velocity timer period.
• QEILOAD is the velocity timer reload value.
• PPR is the number of pulses per revolution of the physical encoder used in the
application
• Edges is 2 or 4, based on the capture mode set in the QEICON register (2 for
CapMode set to 0 and 4 for CapMode set to 1)
For example, consider a motor running at 600 RPM. A 2048 pulse per revolution
quadrature encoder is attached to the motor, producing 8192 phase edges per revolution
(PPR * Edges). This results in 81,920 pulses per second (the motor turns 10 times per
second at 600 RPM and there are 8,192 edges per revolution). If the timer were clocked at
10,000 Hz, and the QEILOAD was 2,500 (corresponding to ¼ of a second), it would count
20,480 pulses per update. Using the above equation:
Now, consider that the motor is sped up to 3000 RPM. This results in 409,600 pulses per
second, or 102,400 every ¼ of a second. Again, the above equation gives:
These are simple examples, real-world values will have a higher rate for PCLK, and
probably a larger value for QEILOAD as well.
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[1] The Quadrature Encoder Interface uses the same pin functions as the Motor Control PWM feedback inputs
and are connected when the Motor Control PWM function is selected on these pins. If used as part of motor
control, the QEI is an alternative to feedback directly to the MCPWM.
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Table 484: QEI Control register (QEICON - address 0x400B C000) bit description
Bit Symbol Description Reset
value
0 RESP Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when 0
the position counter is cleared.
1 RESPI Reset position counter on index. When set = 1, resets the position counter to all zeros when an 0
index pulse occurs. Autoclears when the position counter is cleared.
2 RESV Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity 0
timer. Autoclears when the velocity counter is cleared.
3 RESI Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the 0
index counter is cleared.
31:4 - reserved 0
Table 485: QEI Configuration register (QEICONF - address 0x400B C008) bit description
Bit Symbol Description Reset
value
0 DIRINV Direction invert. When = 1, complements the DIR bit. 0
1 SIGMODE Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA 0
functions as the direction signal and PhB functions as the clock signal.
2 CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB 0
edges are counted (4X), increasing resolution but decreasing range.
3 INVINX Invert Index. When set, inverts the sense of the index input. 0
31:4 - reserved 0
Table 486: QEI Interrupt Status register (QEISTAT - address 0x400B C004) bit description
Bit Symbol Description Reset
value
0 DIR Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See
Table 481.
31:1 - reserved 0
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Table 487: QEI Position register (QEIPOS - address 0x400B C00C) bit description
Bit Symbol Description Reset
value
31:0 - Current position value. 0
Table 488: QEI Maximum Position register (QEIMAXPOS - address 0x400B C010) bit description
Bit Symbol Description Reset
value
31:0 - Current maximum position value. 0
Table 489: QEI Position Compare register 0 (CMPOS0 - address 0x400B C014) bit description
Bit Symbol Description Reset
value
31:0 - Position compare value 0. 0
Table 490: QEI Position Compare register 1 (CMPOS1 - address 0x400B C018) bit description
Bit Symbol Description Reset
value
31:0 - Position compare value 1. 0
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Table 491: QEI Position Compare register 2 (CMPOS2 - address 0x400B C01C) bit description
Bit Symbol Description Reset
value
31:0 - Position compare value 2. 0
Table 492: QEI Index Count register (CMPOS - address 0x400B C020) bit description
Bit Symbol Description Reset
value
31:0 - Current index counter value. 0
Table 493: QEI Index Compare register (CMPOS - address 0x400B C024) bit description
Bit Symbol Description Reset
value
31:0 - Index compare value. 0
Table 494: QEI Timer Load register (QEILOAD - address 0x400B C028) bit description
Bit Symbol Description Reset
value
31:0 - Velocity timer reload value. 0
Table 495: QEI Timer register (QEITIME - address 0x400B C02C) bit description
Bit Symbol Description Reset
value
31:0 - Current velocity timer value. 0
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Table 496: QEI Velocity register (QEIVEL - address 0x400B C030) bit description
Bit Symbol Description Reset
value
31:0 - Current velocity pulse count. 0
Table 497: QEI Velocity Capture register (QEICAP - address 0x400B C034) bit description
Bit Symbol Description Reset
value
31:0 - Current velocity pulse count. 0
Table 498: QEI Velocity Compare register (VELCOMP - address 0x400B C038) bit description
Bit Symbol Description Reset
value
31:0 - Velocity compare value. 0
Table 499: QEI Digital Filter register (FILTER - address 0x400B C03C) bit description
Bit Symbol Description Reset
value
31:0 - Digital filter sampling delay 0x0
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Table 500: QEI Interrupt Status register (QEIINTSTAT - address 0x400B CFE0) bit description
Bit Symbol Description Reset
value
0 INX_Int Indicates that an index pulse was detected. 0
1 TIM_Int Indicates that a velocity timer overflow occurred 0
2 VELC_Int Indicates that captured velocity is less than compare velocity. 0
3 DIR_Int Indicates that a change of direction was detected. 0
4 ERR_Int Indicates that an encoder phase error was detected. 0
5 ENCLK_Int Indicates that and encoder clock pulse was detected.
6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0
7 POS1_Int Indicates that the position 1compare value is equal to the current position. 0
8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0
9 REV_Int Indicates that the index compare value is equal to the current index count. 0
10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0
and the REV_Int is set.
11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0
and the REV_Int is set.
12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0
and the REV_Int is set.
31:13 - reserved 0
Table 501: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description
Bit Symbol Description Reset
value
0 INX_Int Indicates that an index pulse was detected. 0
1 TIM_Int Indicates that a velocity timer overflow occurred 0
2 VELC_Int Indicates that captured velocity is less than compare velocity. 0
3 DIR_Int Indicates that a change of direction was detected. 0
4 ERR_Int Indicates that an encoder phase error was detected. 0
5 ENCLK_Int Indicates that and encoder clock pulse was detected.
6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0
7 POS1_Int Indicates that the position 1compare value is equal to the current position. 0
8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0
9 REV_Int Indicates that the index compare value is equal to the current index count. 0
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Table 501: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description
Bit Symbol Description Reset
value
10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0
and the REV_Int is set.
11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0
and the REV_Int is set.
12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0
and the REV_Int is set.
31:13 - reserved 0
Table 502: QEI Interrupt Clear register (QEICLR - 0x400B CFE8) bit description
Bit Symbol Description Reset
value
0 INX_Int Indicates that an index pulse was detected. 0
1 TIM_Int Indicates that a velocity timer overflow occurred 0
2 VELC_Int Indicates that captured velocity is less than compare velocity. 0
3 DIR_Int Indicates that a change of direction was detected. 0
4 ERR_Int Indicates that an encoder phase error was detected. 0
5 ENCLK_Int Indicates that and encoder clock pulse was detected.
6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0
7 POS1_Int Indicates that the position 1compare value is equal to the current position. 0
8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0
9 REV_Int Indicates that the index compare value is equal to the current index count. 0
10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0
and the REV_Int is set.
11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0
and the REV_Int is set.
12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0
and the REV_Int is set.
31:13 - reserved 0
Table 503: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description
Bit Symbol Description Reset
value
0 INX_Int Indicates that an index pulse was detected. 0
1 TIM_Int Indicates that a velocity timer overflow occurred 0
2 VELC_Int Indicates that captured velocity is less than compare velocity. 0
3 DIR_Int Indicates that a change of direction was detected. 0
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Table 503: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description
Bit Symbol Description Reset
value
4 ERR_Int Indicates that an encoder phase error was detected. 0
5 ENCLK_Int Indicates that and encoder clock pulse was detected. 0
6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0
7 POS1_Int Indicates that the position 1compare value is equal to the current position. 0
8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0
9 REV_Int Indicates that the index compare value is equal to the current index count. 0
10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0
and the REV_Int is set.
11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0
and the REV_Int is set.
12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0
and the REV_Int is set.
31:13 - reserved 0
Table 504: QEI Interrupt Enable Set register (QEIIES - address 0x400B CFDC) bit description
Bit Symbol Description Reset
value
0 INX_EN Indicates that an index pulse was detected. 0
1 TIM_EN Indicates that a velocity timer overflow occurred 0
2 VELC_EN Indicates that captured velocity is less than compare velocity. 0
3 DIR_EN Indicates that a change of direction was detected. 0
4 ERR_EN Indicates that an encoder phase error was detected. 0
5 ENCLK_EN Indicates that and encoder clock pulse was detected. 0
6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0
7 POS1_Int Indicates that the position 1compare value is equal to the current position. 0
8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0
9 REV_Int Indicates that the index compare value is equal to the current index count. 0
10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0
and the REV_Int is set.
11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0
and the REV_Int is set.
12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0
and the REV_Int is set.
31:13 - reserved 0
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Table 505: QEI Interrupt Enable Clear register (QEIIEC - address 0x400B CFD8) bit description
Bit Symbol Description Reset
value
0 INX_EN Indicates that an index pulse was detected. 0
1 TIM_EN Indicates that a velocity timer overflow occurred 0
2 VELC_EN Indicates that captured velocity is less than compare velocity. 0
3 DIR_EN Indicates that a change of direction was detected. 0
4 ERR_EN Indicates that an encoder phase error was detected. 0
5 ENCLK_EN Indicates that and encoder clock pulse was detected. 0
6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0
7 POS1_Int Indicates that the position 1compare value is equal to the current position. 0
8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0
9 REV_Int Indicates that the index compare value is equal to the current index count. 0
10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0
and the REV_Int is set.
11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0
and the REV_Int is set.
12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0
and the REV_Int is set.
31:13 - reserved 0
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27.2 Features
• Measures the passage of time to maintain a calendar and clock. Provides seconds,
minutes, hours, day of month, month, year, day of week, and day of year.
• Ultra-low power design to support battery powered systems. Less than 1 microamp
required for battery operation. Uses power from the CPU power supply when it is
present.
• 20 bytes of Battery-backed storage and RTC operation when power is removed from
the CPU.
• Dedicated 32 kHz ultra low power oscillator.
• Dedicated battery power supply pin.
• RTC power supply is isolated from the rest of the chip.
• Calibration counter allows adjustment to better than ±1 sec/day with 1 sec resolution.
• Periodic interrupts can be generated from increments of any field of the time registers
and selected fractional second values.
• Alarm interrupt can be generated for a specific date/time.
27.3 Description
The Real Time Clock (RTC) is a set of counters for measuring time when system power is
on, and optionally when it is off. It uses very little power when its registers are not being
accessed by the CPU, especially reduced power modes. On the LPC17xx, the RTC is
clocked by a separate 32 kHz oscillator that produces a 1 Hz internal time reference. The
RTC is powered by its own power supply pin, VBAT, which can be connected to a battery,
externally tied to a 3V supply, or left floating.
The RTC power domain is shown in conceptual form in Figure 130. A detailed view of the
time keeping portion of the RTC is shown in Figure 131.
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27.4 Architecture
Ultra-low
Power Backup
power
VBAT pin selector Registers
regulator
RTC power
RTCX1
Ultra-low
1 Hz clock Real Time Clock RTC Alarm
power
Functional Block & Interrupt
oscillator
RTCX2
Alarm Registers
second minute hour day month year
Alarm out
and Alarm
Interrupts
alarm compare
1 Hz
Clock Counter
second minute hour day month year Increment
LSB LSB day of Interrupts
Time Registers
out set week
day of
year
sign Calibration
bit
calibration compare register
match
calibration compare
calibration
control counter
logic reset
calibration counter
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[1] Reset values apply only to a power-up of the RTC block, other types of reset have no effect on this block.
Since the RTC is powered whenever either of the VDD(REG)(3V3), or VBAT supplies are present, power-up
reset occurs only when both supplies were absent and then one is turned on. Most registers are not
affected by power-up of the RTC and must be initialized by software if the RTC is enabled. The Reset Value
reflects the data stored in used bits only. It does not include reserved bits content.
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The RTC interrupt can bring the microcontroller out of Power-down mode when the RTC
is operating from its own oscillator on the RTCX1-2 pins. When the RTC interrupt is
enabled for wake-up and its selected event occurs, the oscillator wake-up cycle
associated with the XTAL1/2 pins is started. For details on the RTC based wake-up
process see Section 4.8.8 “Wake-up from Reduced Power Modes” on page 62 and
Section 4.9 “Wake-up timer” on page 65.
Table 508. Interrupt Location Register (ILR - address 0x4002 4000) bit description
Bit Symbol Description Reset
value
0 RTCCIF When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit 0
location clears the counter increment interrupt.
1 RTCALF When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the 0
alarm interrupt.
31:21 - Reserved, user software should not write ones to reserved bits. The value read from a reserved NA
bit is not defined.
Table 509. Clock Control Register (CCR - address 0x4002 4008) bit description
Bit Symbol Value Description Reset
value
0 CLKEN Clock Enable. NC
1 The time counters are enabled.
0 The time counters are disabled so that they may be initialized.
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Table 509. Clock Control Register (CCR - address 0x4002 4008) bit description
Bit Symbol Value Description Reset
value
1 CTCRST CTC Reset. 0
1 When one, the elements in the internal oscillator divider are reset, and remain reset until
CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the
32.768 kHz crystal. The state of the divider is not visible to software.
0 No effect.
3:2 - Internal test mode controls. These bits must be 0 for normal RTC operation. NC
4 CCALEN Calibration counter enable. NC
1 The calibration counter is disabled and reset to zero.
0 The calibration counter is enabled and counting, using the 1 Hz clock. When the
calibration counter is equal to the value of the CALIBRATION register, the counter resets
and repeats counting up to the value of the CALIBRATION register. See Section 27.6.4.2
and Section 27.6.5.
31:5 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 510. Counter Increment Interrupt Register (CIIR - address 0x4002 400C) bit description
Bit Symbol Description Reset
value
0 IMSEC When 1, an increment of the Second value generates an interrupt. 0
1 IMMIN When 1, an increment of the Minute value generates an interrupt. 0
2 IMHOUR When 1, an increment of the Hour value generates an interrupt. 0
3 IMDOM When 1, an increment of the Day of Month value generates an interrupt. 0
4 IMDOW When 1, an increment of the Day of Week value generates an interrupt. 0
5 IMDOY When 1, an increment of the Day of Year value generates an interrupt. 0
6 IMMON When 1, an increment of the Month value generates an interrupt. 0
7 IMYEAR When 1, an increment of the Year value generates an interrupt. 0
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved NA
bit is not defined.
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Table 511. Alarm Mask Register (AMR - address 0x4002 4010) bit description
Bit Symbol Description Reset
value
0 AMRSEC When 1, the Second value is not compared for the alarm. 0
1 AMRMIN When 1, the Minutes value is not compared for the alarm. 0
2 AMRHOUR When 1, the Hour value is not compared for the alarm. 0
3 AMRDOM When 1, the Day of Month value is not compared for the alarm. 0
4 AMRDOW When 1, the Day of Week value is not compared for the alarm. 0
5 AMRDOY When 1, the Day of Year value is not compared for the alarm. 0
6 AMRMON When 1, the Month value is not compared for the alarm. 0
7 AMRYEAR When 1, the Year value is not compared for the alarm. 0
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 512. RTC Auxiliary control register (RTC_AUX - address 0x4002 405C) bit description
Bit Symbol Description Reset
value
3:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
4 RTC_OSCF RTC Oscillator Fail detect flag. 1
Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An
interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the
RTC interrupt is enabled in the NVIC.
Write: writing a 1 to this bit clears the flag.
31:5 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 513. RTC Auxiliary Enable register (RTC_AUXEN - address 0x4002 4058) bit description
Bit Symbol Description Reset
value
3:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
4 RTC_OSCFEN Oscillator Fail Detect interrupt enable. 0
When 0: the RTC Oscillator Fail detect interrupt is disabled.
When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 27.6.2.5.
31:5 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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The Consolidated Time Registers are read-only. To write new values to the Time
Counters, the Time Counter addresses should be used.
Table 514. Consolidated Time register 0 (CTIME0 - address 0x4002 4014) bit description
Bit Symbol Description Reset
value
5:0 Seconds Seconds value in the range of 0 to 59 NC
7:6 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
13:8 Minutes Minutes value in the range of 0 to 59 NC
15:14 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
20:16 Hours Hours value in the range of 0 to 23 NC
23:21 - Reserved, user software should not write ones to reserved bits. The value read from a NC
reserved bit is not defined.
26:24 Day Of Week Day of week value in the range of 0 to 6 NA
31:27 - Reserved, user software should not write ones to reserved bits. The value read from a NC
reserved bit is not defined.
Table 515. Consolidated Time register 1 (CTIME1 - address 0x4002 4018) bit description
Bit Symbol Description Reset
value
4:0 Day of Month Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and NC
whether it is a leap year).
7:5 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
11:8 Month Month value in the range of 1 to 12. NC
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
27:16 Year Year value in the range of 0 to 4095. NC
31:28 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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Table 516. Consolidated Time register 2 (CTIME2 - address 0x4002 401C) bit description
Bit Symbol Description Reset
value
11:0 Day of Year Day of year value in the range of 1 to 365 (366 for leap years). NC
31:12 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
[1] These values are simply incremented at the appropriate intervals and reset at the defined overflow point.
They are not calculated and must be correctly initialized in order to be meaningful.
Table 519. Calibration register (CALIBRATION - address 0x4002 4040) bit description
Bit Symbol Value Description Reset
value
16:0 CALVAL - If enabled, the calibration counter counts up to this value. The maximum value is 131, NC
072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0.
17 CALDIR Calibration direction NC
1 Backward calibration. When CALVAL is equal to the calibration counter, the RTC
timers will stop incrementing for 1 second.
0 Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers
will jump by 2 seconds.
31:12 Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
A recommended method for determining the calibration value is to use the CLKOUT
feature to unintrusively observe the RTC oscillator frequency under the conditions it is to
be trimmed for, and calculating the number of clocks that will be seen before the time is off
by one second. That value is used to determine CALVAL.
If the RTC oscillator is trimmed externally, the same method of unintrusively observing the
RTC oscillator frequency may be helpful in that process.
Backward calibration
Enable the RTC timer and calibration in the CCR register (set bits CLKEN = 1 and
CCALEN = 0). In the CALIBRATION register, set the calibration value CALVAL ≥ 1 and
select CALDIR = 1.
• The SEC timer and the calibration counter count up for every 1 Hz clock cycle.
• When the calibration counter reaches CALVAL, a calibration match occurs and all
RTC timers will be stopped for one clock cycle so that the timers will not increment in
the next cycle.
• If an alarm match event occurs in the same cycle as the calibration match, the alarm
interrupt will be delayed by one cycle to avoid a double alarm interrupt.
Forward calibration
Enable the RTC timer and calibration in the CCR register (set bits CLKEN = 1 and
CCALEN = 0). In the CALIBRATION register, set the calibration value CALVAL ≥ 1 and
select CALDIR = 0.
• The SEC timer and the calibration counter count up for every 1 Hz clock cycle.
• When the calibration counter reaches CALVAL, a calibration match occurs and the
RTC timers are incremented by 2.
• When the calibration event occurs, the LSB of the ALSEC register is forced to be one
so that the alarm interrupt will not be missed when skipping a second.
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Table 520. General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses 0x4002 4044
to 0x4002 4054) bit description
Bit Symbol Description Reset
value
31:0 GP0 to GP4 General purpose storage. N/A
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28.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate Watchdog reset.
• Programmable 32-bit timer with internal pre-scaler.
• Selectable time period from (TWDCLK × 256 × 4) to (TWDCLK × 232 × 4) in multiples of
TWDCLK × 4.
• The Watchdog clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the APB peripheral clock (PCLK, see Table 40), or the RTC oscillator. This
gives a wide range of potential timing choices for Watchdog operation under different
power reduction conditions. For increased reliability, it also provides the ability to run
the Watchdog timer from an entirely internal source that is not dependent on an
external crystal and its associated components and wiring.
• The Watchdog timer can be configured to run in Deep Sleep mode when using the
IRC as the clock source.
28.2 Applications
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined
amount of time.
For interaction of the on-chip watchdog and other peripherals, especially the reset and
boot-up procedures, please read Section 3.4 “Reset” on page 18 of this document.
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28.3 Description
The Watchdog consists of a divide by 4 fixed pre-scaler and a 32-bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum Watchdog interval is (TWDCLK × 256 × 4)
and the maximum Watchdog interval is (TWDCLK × 232 × 4) in multiples of (TWDCLK × 4).
The Watchdog should be used in the following manner:
When the Watchdog is in the reset mode and the counter underflows, the CPU will be
reset, loading the stack pointer and program counter from the vector table as in the case
of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if
the Watchdog has caused the reset condition. The WDTOF flag must be cleared by
software.
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers. The WDCLK is used for the watchdog timer counting.
There is some synchronization logic between these two clock domains. When the
WDMOD and WDTC registers are updated by APB operations, the new value will take
effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog
timer is counting on WDCLK, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV
register by the CPU.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
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Table 523: Watchdog Mode register (WDMOD - address 0x4000 0000) bit description
Bit Symbol Description Reset Value
0 WDEN WDEN Watchdog enable bit (set-only). When 1, the watchdog timer is running. 0
1 WDRESET WDRESET Watchdog reset enable bit (set -only). When 1, a watchdog timeout will 0
cause a chip reset.
2 WDTOF WDTOF Watchdog time-out flag. Set when the watchdog timer times out, cleared by 0 (Only after
software. external reset)
3 WDINT WDINT Watchdog interrupt flag (read-only, not clearable by software). 0
31:4 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both
flags are cleared by an external reset or a Watchdog timer underflow.
WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag is
cleared by software.
WDINT The Watchdog interrupt flag is set when the Watchdog times out. This flag is
cleared when any reset occurs. Once the watchdog interrupt is serviced, it can be
disabled in the NVIC or the watchdog interrupt request will be generated indefinitely. the
intent of the watchdog interrupt is to allow debugging watchdog activity without resetting
the device when the watchdog overflows.
Watchdog reset or interrupt will occur any time the watchdog is running and has an
operating clock source. Any clock source works in Sleep mode, and the IRC works in
Deep Sleep mode. If a watchdog interrupt occurs in Sleep or Deep Sleep mode, it will
wake up the device.
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Table 525: Watchdog Constant register (WDTC - address 0x4000 0004) bit description
Bit Symbol Description Reset Value
31:0 Count Watchdog time-out interval. 0x0000 00FF
Table 526: Watchdog Feed register (WDFEED - address 0x4000 0008) bit description
Bit Symbol Description Reset
Value
7:0 Feed Feed value should be 0xAA followed by 0x55. NA
31:8 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
When reading the value of the 32-bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
Table 527: Watchdog Timer Value register (WDTV - address 0x4000 000C) bit description
Bit Symbol Description Reset Value
31:0 Count Counter timer value. 0x0000 00FF
When the IRC is chosen as the watchdog clock source, the watchdog timer can remain
running in deep sleep mode, and can reset or wake up the device from that mode.
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Table 528: Watchdog Timer Clock Source Selection register (WDCLKSEL - address 0x4000 0010) bit description
Bit Symbol Value Description Reset
Value
1:0 WDSEL These bits select the clock source for the Watchdog timer as described below. 0
Warning: Improper setting of this value may result in incorrect operation of the
Watchdog timer, which could adversely affect system operation. If the WDLOCK bit in
this register is set, the WDSEL bit cannot be modified.
00 Selects the Internal RC oscillator (irc_clk) as the Watchdog clock source (default).
01 Selects the APB peripheral clock (watchdog pclk) as the Watchdog clock source.
10 Selects the RTC oscillator (rtc_clk) as the Watchdog clock source.
11 Reserved, this setting should not be used.
30:2 - - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
31 WDLOCK 0 This bit is set to 0 on any reset. It cannot be cleared by software. 0
1 Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register
cannot be modified.
feed sequence
WDTC
feed ok
WDFEED
feed error
RTC oscillator
wdclk
pclk ÷4 32-BIT DOWN COUNTER
internal RC oscillator
underflow enable
count
WDCLKSEL WDTV
SHADOW BIT
WMOD register
reset
interrupt
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1. Power: In the PCONP register (Table 46), set the PCADC bit.
Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit,
and then enable the ADC in the AD0CR register (bit PDN Table 531). To disable the
ADC, first clear the PDN bit, and then clear the PCADC bit.
2. Clock: In the PCLKSEL0 register (Table 40), select PCLK_ADC. To scale the clock for
the ADC, see bits CLKDIV in Table 531.
3. Pins: Enable ADC0 pins through PINSEL registers. Select the pin modes for the port
pins with ADC0 functions through the PINMODE registers (Section 8.5).
4. Interrupts: To enable interrupts in the ADC, see Table 535. Interrupts are enabled in
the NVIC using the appropriate Interrupt Set Enable register. Disable the ADC
interrupt in the NVIC using the appropriate Interrupt Set Enable register.
5. DMA: See Section 29.6.4. For GPDMA system connections, see Table 543.
29.2 Features
• 12-bit successive approximation analog to digital converter.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage level).
• 12-bit conversion rate of 200 kHz.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
29.3 Description
Basic clocking for the A/D converters is provided by the APB clock. A programmable
divider is included in each converter to scale this clock to the clock (maximum 13 MHz)
needed by the successive approximation process. A fully accurate conversion requires 65
of these clocks.
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[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
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Results of ADC conversion can be read in one of two ways. One is to use the A/D Global
Data Register to read all data from the ADC. Another is to use the A/D Channel Data
Registers. It is important to use one method consistently because the DONE and
OVERRUN flags can otherwise get out of synch between the AD0GDR and the A/D
Channel Data Registers, potentially causing erroneous interrupts or DMA activity.
Table 532: A/D Global Data Register (AD0GDR - address 0x4003 4004) bit description
Bit Symbol Description Reset
value
3:0 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
15:4 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on NA
the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to
VREFN. Zero in the field indicates that the voltage on the input pin was less than,
equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the
input was close to, equal to, or greater than that on VREFP.
23:16 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
26:24 CHN These bits contain the channel from which the RESULT bits were converted (e.g. NA
000 identifies channel 0, 001 channel 1...).
29:27 - Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost 0
and overwritten before the conversion that produced the result in the RESULT bits.
This bit is cleared by reading this register.
31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this 0
register is read and when the ADCR is written. If the ADCR is written while a
conversion is still in progress, this bit is set and a new conversion is started.
Table 533: A/D Status register (AD0INTEN - address 0x4003 400C) bit description
Bit Symbol Value Description Reset
value
0 ADINTEN0 0 Completion of a conversion on ADC channel 0 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 0 will generate an interrupt.
1 ADINTEN1 0 Completion of a conversion on ADC channel 1 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 1 will generate an interrupt.
2 ADINTEN2 0 Completion of a conversion on ADC channel 2 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 2 will generate an interrupt.
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Table 533: A/D Status register (AD0INTEN - address 0x4003 400C) bit description
Bit Symbol Value Description Reset
value
3 ADINTEN3 0 Completion of a conversion on ADC channel 3 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 3 will generate an interrupt.
4 ADINTEN4 0 Completion of a conversion on ADC channel 4 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 4 will generate an interrupt.
5 ADINTEN5 0 Completion of a conversion on ADC channel 5 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 5 will generate an interrupt.
6 ADINTEN6 0 Completion of a conversion on ADC channel 6 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 6 will generate an interrupt.
7 ADINTEN7 0 Completion of a conversion on ADC channel 7 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 7 will generate an interrupt.
8 ADGINTEN 0 Only the individual ADC channels enabled by ADINTEN7:0 will generate 1
interrupts.
1 Only the global DONE flag in ADDR is enabled to generate an interrupt.
31:17 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
Results of ADC conversion can be read in one of two ways. One is to use the A/D Global
Data Register to read all data from the ADC. Another is to use the A/D Channel Data
Registers. It is important to use one method consistently because the DONE and
OVERRUN flags can otherwise get out of synch between the AD0GDR and the A/D
Channel Data Registers, potentially causing erroneous interrupts or DMA activity.
Table 534: A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to 0x4003 402C) bit description
Bit Symbol Description Reset
value
3:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
15:4 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] NA
pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the
voltage on the input was close to, equal to, or greater than that on VREFP.
29:16 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and
overwritten before the conversion that produced the result in the RESULT bits.This bit is
cleared by reading this register.
31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. NA
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Table 535: A/D Status register (AD0STAT - address 0x4003 4030) bit description
Bit Symbol Description Reset
value
0 DONE0 This bit mirrors the DONE status flag from the result register for A/D channel 0. 0
1 DONE1 This bit mirrors the DONE status flag from the result register for A/D channel 1. 0
2 DONE2 This bit mirrors the DONE status flag from the result register for A/D channel 2. 0
3 DONE3 This bit mirrors the DONE status flag from the result register for A/D channel 3. 0
4 DONE4 This bit mirrors the DONE status flag from the result register for A/D channel 4. 0
5 DONE5 This bit mirrors the DONE status flag from the result register for A/D channel 5. 0
6 DONE6 This bit mirrors the DONE status flag from the result register for A/D channel 6. 0
7 DONE7 This bit mirrors the DONE status flag from the result register for A/D channel 7. 0
8 OVERRUN0 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. 0
9 OVERRUN1 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. 0
10 OVERRUN2 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. 0
11 OVERRUN3 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. 0
12 OVERRUN4 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. 0
13 OVERRUN5 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. 0
14 OVERRUN6 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. 0
15 OVERRUN7 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. 0
16 ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done 0
flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.
31:17 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
Table 536: A/D Trim register (ADTRM - address 0x4003 4034) bit description
Bit Symbol Description Reset
value
3:0 - reserved. NA
7:4 ADCOFFS Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user. 0
11:8 TRIM written-to by boot code. Can not be overwritten by the user. These bits are locked after boot 1111
code write.
31:12 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
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29.6 Operation
Once an ADC conversion is started, it cannot be interrupted. A new software write to
launch a new conversion or a new edge-trigger event will be ignored while the previous
conversion is in progress.
29.6.2 Interrupts
An interrupt request is asserted to the NVIC when the DONE bit is 1. Software can use the
Interrupt Enable bit for the A/D Converter in the NVIC to control whether this assertion
results in an interrupt. DONE is negated when the ADDR is read.
Remark: If the DMA is used, the ADC interrupt must be disabled in the NVIC.
For DMA transfers, only burst requests are supported. The burst size can be set to one in
the DMA channel control register (see Section 31.5.20). If the number of ADC channels is
not equal to one of the other DMA-supported burst sizes (applicable DMA burst sizes are
1, 4, 8 - see Section 31.5.20), set the burst size to one.
The DMA transfer size determines when a DMA interrupt is generated. The transfer size
can be set to the number of ADC channels being converted (see Section 31.5.20).
Non-contiguous channels can be transferred by the DMA using the scatter/gather linked
lists (see Section 31.5.19).
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30.2 Features
• 10-bit digital to analog converter
• Resistor string architecture
• Buffered output
• Power-down mode
• Selectable speed vs. power
• Maximum update rate of 1 MHz.
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[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 539: D/A Converter Register (DACR - address 0x4008 C000) bit description
Bit Symbol Value Description Reset
Value
5:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
15:6 VALUE After the selected settling time after this field is written with a new VALUE, the voltage on 0
the AOUT pin (with respect to VSSA) is VALUE × ((VREFP - VREFN)/1024) + VREFN.
16 BIAS[1] 0 The settling time of the DAC is 1 μs max, and the maximum current is 700 μA. This allows 0
a maximum update rate of 1 MHz.
1 The settling time of the DAC is 2.5 μs and the maximum current is 350 μA. This allows a
maximum update rate of 400 kHz.
31:17 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
[1] The settling times noted in the description of the BIAS bit are valid for a capacitance load on the AOUT pin
not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than
the specified time. One or more graph(s) of load impedance vs. settling time will be included in the final data
sheet.
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Table 540. D/A Control register (DACCTRL - address 0x4008 C004) bit description
Bit Symbol Value Description Reset
Value
0 INT_DMA_REQ 0 This bit is cleared on any write to the DACR register. 0
1 This bit is set by hardware when the timer times out.
1 DBLBUF_ENA 0 DACR double-buffering is disabled. 0
1 When this bit and the CNT_ENA bit are both set, the double-buffering feature in the
DACR register will be enabled. Writes to the DACR register are written to a
pre-buffer and then transferred to the DACR on the next time-out of the counter.
2 CNT_ENA 0 Time-out counter operation is disabled. 0
1 Time-out counter operation is enabled.
3 DMA_ENA 0 DMA access is disabled. 0
1 DMA Burst Request Input 7 is enabled for the DAC (see Table 543).
31:4 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
Table 541: D/A Converter register (DACR - address 0x4008 C008) bit description
Bit Symbol Description Reset Value
15:0 VALUE 16-bit reload value for the DAC interrupt/DMA timer. 0
30.5 Operation
Note that the contents of the DACCTRL and DACCNTVAL registers are read and write
accessible, but the timer itself is not accessible for either read or write.
If the DMA_ENA bit is set in the DACCTRL register, the DAC DMA request will be routed
to the GPDMA. When the DMA_ENA bit is cleared, the default state after a reset, DAC
DMA requests are blocked.
Reading the DACR register will only return the contents of the DACR register itself, not the
contents of the pre-buffer register.
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If either the CNT_ENA or the DBLBUF_ENA bits are 0, any writes to the DACR address
will go directly to the DACR register.
pbus
CNTVAL
pbus
pbus_wr_toDACR
pbus
16 LD
EN LD PRE-BUFFER
3 DMA_ena COUNTER
2 cnt_ena
pbus dblbuf_ena 16
1 zero
set_intrpt S
pbus_wr_to_DACR 0 intrptDMA_req
C set_intrpt
ena_cnt_and_dblbuf 1 0
MUX
LD
pbus_wr_to_DACR
DACR
pbus
DAC value
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31.2 Introduction
The DMA controller allows peripheral-to memory, memory-to-peripheral, and
memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA
transfers for a single source and destination. For example, a bi-directional port requires
one stream for transmit and one for receives. The source and destination areas can each
be either a memory region or a peripheral.
31.3 Features
• Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers are
supported.
• GPDMA supports the SSP, I2S, UART, A/D Converter, and D/A Converter peripherals.
DMA can also be triggered by a timer match condition. Memory-to-memory transfers
and transfers to or from GPIO are also supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
• One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8-bit, 16-bit, and 32-bit wide transactions.
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GPDMA
CONTROL
AHB SLAVE
AHB BUS LOGIC AND
INTERFACE
REGISTERS
DMA
requests DMA
REQUEST CHANNEL AHB
DMA AND LOGIC AND MASTER AHB BUS
responses RESPONSE REGISTERS INTERFACE
INTERFACE
DMA
Interrupts INTERRUPT
REQUEST
The functions of the DMA Controller are described in the following sections.
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• Split, retry, and error responses from slaves. If a peripheral performs a split or retry,
the DMA Controller stalls and waits until the transaction can complete.
• Locked transfers for source and destination of each stream.
• Setting of protection bits for transfers on each stream.
31.4.1.6.1 Bus and transfer widths
The physical width of the AHB bus is 32 bits. Source and destination transfers can be of
differing widths and can be the same width or narrower than the physical bus width. The
DMA Controller packs or unpacks data as appropriate.
Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit
quantities. This means that when performing mixed-endian activity, where the endianness
of the source and destination are different, byte swapping of the data within the 32-bit data
bus is observed.
Note: If byte swapping is not required, then use of different endianness between the
source and destination addresses must be avoided. Table 542 shows endian behavior for
different source and destination combinations.
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If the DMA Controller is transferring data for the lower priority channel and then the higher
priority channel goes active, it completes the number of transfers delegated to the master
interface by the lower priority channel before switching over to transfer data for the higher
priority channel. Transfers delegated to the master interface are staged in the DMA
channel FIFO, so the amount of data that needs to transfer could be as large as a 4
words.
Note that peripherals on this device do not support “last” request types, and many do not
support both single and burst request types. See Section 31.4.2.3.
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DMACTC[15:0] — DMA terminal count signals. The DMACTC signal can be used by the
DMA controller to indicate to the peripheral that the DMA transfer is complete.
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Table 546. DMA Interrupt Terminal Count Request Status register (DMACIntTCStat - 0x5000 4004)
Bit Name Function
7:0 IntTCStat Terminal count interrupt request status for DMA channels. Each bit represents one
channel:
0 - the corresponding channel has no active terminal count interrupt request.
1 - the corresponding channel does have an active terminal count interrupt request.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 547. DMA Interrupt Terminal Count Request Clear register (DMACIntTCClear - 0x5000 4008)
Bit Name Function
7:0 IntTCClear Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels.
Each bit represents one channel:
0 - writing 0 has no effect.
1 - clears the corresponding channel terminal count interrupt.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
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Table 548. DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C)
Bit Name Function
7:0 IntErrStat Interrupt error status for DMA channels. Each bit represents one channel:
0 - the corresponding channel has no active error interrupt request.
1 - the corresponding channel does have an active error interrupt request.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 549. DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010)
Bit Name Function
7:0 IntErrClr Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit
represents one channel:
0 - writing 0 has no effect.
1 - clears the corresponding channel error interrupt.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 550. DMA Raw Interrupt Terminal Count Status register (DMACRawIntTCStat - 0x5000 4014)
Bit Name Function
7:0 RawIntTCStat Status of the terminal count interrupt for DMA channels prior to masking. Each bit
represents one channel:
0 - the corresponding channel has no active terminal count interrupt request.
1 - the corresponding channel does have an active terminal count interrupt request.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
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Table 551. DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018)
Bit Name Function
7:0 RawIntErrStat Status of the error interrupt for DMA channels prior to masking. Each bit represents
one channel:
0 - the corresponding channel has no active error interrupt request.
1 - the corresponding channel does have an active error interrupt request.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 553. DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)
Bit Name Function
15:0 SoftBReq Software burst request flags for each of 16 possible sources. Each bit represents one
DMA request line or peripheral function (refer to Table 543 for peripheral hardware
connections to the DMA controller):
0 - writing 0 has no effect.
1 - writing 1 generates a DMA burst request for the corresponding request line.
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Note: It is recommended that software and hardware peripheral requests are not used at
the same time.
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Table 554. DMA Software Single Request register (DMACSoftSReq - 0x5000 4024)
Bit Name Function
15:0 SoftSReq Software single transfer request flags for each of 16 possible sources. Each bit
represents one DMA request line or peripheral function:
0 - writing 0 has no effect.
1 - writing 1 generates a DMA single transfer request for the corresponding request
line.
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 555. DMA Software Last Burst Request register (DMACSoftLBReq - 0x5000 4028)
Bit Name Function
15:0 SoftLBReq Software last burst request flags for each of 16 possible sources. Each bit represents
one DMA request line or peripheral function:
0 - writing 0 has no effect.
1 - writing 1 generates a DMA last burst request for the corresponding request line.
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
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Table 556. DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C)
Bit Name Function
15:0 SoftLSReq Software last single transfer request flags for each of 16 possible sources. Each bit
represents one DMA request line or peripheral function:
0 - writing 0 has no effect.
1 - writing 1 generates a DMA last single transfer request for the corresponding
request line.
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
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When performing scatter/gather DMA, the first four of these are automatically updated.
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Note: The source and destination addresses must be aligned to the source and
destination widths.
Table 560. DMA Channel Source Address registers (DMACCxSrcAddr - 0x5000 41x0)
Bit Name Function
31:0 SrcAddr DMA source address. Reading this register will return the current source address.
Table 561. DMA Channel Destination Address registers (DMACCxDestAddr - 0x5000 41x4)
Bit Name Function
31:0 DestAddr DMA Destination address. Reading this register will return the current destination
address.
31.5.19 DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8)
The eight read/write DMACCxLLI Registers (DMACC0LLI to DMACC7LLI) contain a
word-aligned address of the next Linked List Item (LLI). If the LLI is 0, then the current LLI
is the last in the chain, and the DMA channel is disabled when all DMA transfers
associated with it are completed. Programming this register when the DMA channel is
enabled may have unpredictable side effects. Table 562 shows the bit assignments of the
DMACCxLLI Register.
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Table 562. DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8)
Bit Name Function
1:0 - Reserved, and must be written as 0.
31:2 LLI Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
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Table 563. DMA channel control registers (DMACCxControl - 0x5000 41xC) …continued
Bit Name Function
26 SI Source increment:
0 - the source address is not incremented after each transfer.
1 - the source address is incremented after each transfer.
27 DI Destination increment:
0 - the destination address is not incremented after each transfer.
1 - the destination address is incremented after each transfer.
28 Prot1 This is provided to the peripheral during a DMA bus access and indicates that the access is in user
mode or privileged mode. This information is not used in the LPC17xx.
0 - access is in user mode.
1 - access is in privileged mode.
29 Prot2 This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the
access is bufferable or not bufferable. This information is not used in the LPC17xx.
0 - access is not bufferable.
1 - access is bufferable.
30 Prot3 This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the
access is cacheable or not cacheable. This information is not used in the LPC17xx.
0 - access is not cacheable.
1 - access is cacheable.
31 I Terminal count interrupt enable bit.
0 - the terminal count interrupt is disabled.
1 - the terminal count interrupt is enabled.
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There are situations when the DMA Controller asserts the lock for source transfers
followed by destination transfers. This is possible when internal conditions in the DMA
Controller permit it to perform a source fetch followed by a destination drain back-to-back.
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• Read the DMACEnbldChns register and ensure that all the DMA channels have been
disabled. If any channels are active, see Disabling a DMA channel.
• Disable the DMA controller by writing 0 to the DMA Enable bit in the DMACConfig
register.
• By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost
if this method is used.
• By using the active and halt bits in conjunction with the channel enable bit.
• By waiting until the transfer completes. This automatically clears the channel.
Disabling a DMA channel and losing data in the FIFO
Clear the relevant channel enable bit in the relevant channel configuration register. The
current AHB transfer (if one is in progress) completes and the channel is disabled. Any
data in the FIFO is lost.
• Set the halt bit in the relevant channel configuration register. This causes any future
DMA request to be ignored.
• Poll the active bit in the relevant channel configuration register until it reaches 0. This
bit indicates whether there is any data in the channel that has to be transferred.
• Clear the channel enable bit in the relevant channel configuration register
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1. Read the DMACEnbldChns controller register and find out which channels are
inactive.
2. Choose an inactive channel that has the required priority.
3. Program the DMA controller
1. The DMA Controller issues an acknowledge to the peripheral in order to indicate that
the transfer has finished.
2. A TC interrupt is generated, if enabled.
3. The DMA Controller moves on to the next LLI.
The following sections describe the DMA Controller data flow sequences for the four
allowed transfer types:
• Memory-to-peripheral.
• Peripheral-to-memory.
• Memory-to-memory.
• Peripheral-to-peripheral.
Table 566 indicates the request signals used for each type of transfer.
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7. When the destination DMA request goes active and there is data in the DMA
Controller FIFO, transfer data into the destination peripheral.
8. If an error occurs while transferring the data, an error interrupt is generated, the DMA
stream is disabled, and the flow sequence ends.
9. If the transfer has completed it is indicated by the transfer count reaching 0. The
following happens:
– The DMA Controller responds with a DMA acknowledge to the destination
peripheral.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back
to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.
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1. Read the DMACIntTCStat Register to determine whether the interrupt was generated
due to the end of the transfer (terminal count). A 1 bit indicates that the transfer
completed. If more than one request is active, it is recommended that the highest
priority channels be checked first.
2. Read the DMACIntErrStat Register to determine whether the interrupt was generated
due to an error occurring. A 1 bit indicates that an error occurred.
3. Service the interrupt request.
4. For a terminal count interrupt, write a 1 to the relevant bit of the DMACIntTCClr
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.
Some devices, especially memories, disallow burst accesses across certain address
boundaries. The DMA controller assumes that this is the case with any source or
destination area, which is configured for incrementing addressing. This boundary is
assumed to be aligned with the specified burst size. For example, if the channel is set for
16-transfer burst to a 32-bit wide device then the boundary is 64-bytes aligned (that is
address bits [5:0] equal 0). If a DMA burst is to cross one of these boundaries, then,
instead of a burst, that transfer is split into separate AHB transactions.
31.6.5 Scatter/gather
Scatter/gather is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas in memory. Where
scatter/gather is not required, the DMACCxLLI Register must be set to 0.
The source and destination data areas are defined by a series of linked lists. Each Linked
List Item (LLI) controls the transfer of one block of data, and then optionally loads another
LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed
into the DMA Controller.
The data to be transferred described by an LLI (referred to as the packet of data) usually
requires one or more DMA bursts (to each of the source and destination).
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1. DMACCxSrcAddr.
2. DMACCxDestAddr.
3. DMACCxLLI.
4. DMACCxControl.
Note: The DMACCxConfig DMA channel Configuration Register is not part of the linked
list item.
1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains
four words:
– Source address.
– Destination address.
– Pointer to next LLI.
– Control word.
The last LLI has its linked list word pointer set to 0.
2. Choose a free DMA channel with the priority required. DMA channel 0 has the highest
priority and DMA channel 7 the lowest priority.
3. Write the first linked list item, previously written to memory, to the relevant channel in
the DMA Controller.
4. Write the channel configuration information to the channel Configuration Register and
set the Channel Enable bit. The DMA Controller then transfers the first and then
subsequent packets of data as each linked list item is loaded.
5. An interrupt can be generated at the end of each LLI depending on the Terminal
Count bit in the DMACCxControl Register. If this bit is set an interrupt is generated at
the end of the relevant LLI. The interrupt request must then be serviced and the
relevant bit in the DMACIntTCClear Register must be set to clear the interrupt.
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The first LLI, stored at 0x2002 0000, defines the first block of data to be transferred, which
is the data stored from address 0x2002 A200 to 0x2002 ADFF:
The second LLI, stored at 0x2002 0010, describes the next block of data to be transferred:
A chain of descriptors is built up, each one pointing to the next in the series. To initialize
the DMA stream, the first LLI, 0x2002 0000, is programmed into the DMA Controller.
When the first packet of data has been transferred the next LLI is automatically loaded.
Because the next LLI address is set to zero, this is the last descriptor, and the DMA
channel is disabled after transferring the last item of data. The channel is probably set to
generate an interrupt at this point to indicate to the ARM processor that the channel can
be reprogrammed.
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32.1 Introduction
The boot loader controls initial operation after reset and also provides the tools for
programming the flash memory. This could be initial programming of a blank device,
erasure and re-programming of a previously programmed device, or programming of the
flash memory by the application program in a running system.
32.2 Features
• In-System Programming: In-System programming (ISP) is programming or
reprogramming the on-chip flash memory, using the boot loader software and UART0
serial port. This can be done when the part resides in the end-user board.
• In Application Programming: In-Application (IAP) programming is performing erase
and write operation on the on-chip flash memory, as directed by the end-user
application code.
• Flash signature generation: built-in hardware can generate a signature for a range of
flash addresses, or for the entire flash memory.
32.3 Description
The flash boot loader code is executed every time the part is powered on or reset. The
loader can execute the ISP command handler or the user application code. A LOW level
after reset at pin P2.10 is considered an external hardware request to start the ISP
command handler. Assuming that power supply pins are on their nominal levels when the
rising edge on RESET pin is generated, it may take up to 3 ms before P2.10 is sampled
and the decision on whether to continue with user code or ISP handler is made. If P2.10 is
sampled low and the watchdog overflow flag is set, the external hardware request to start
the ISP command handler is ignored. If there is no request for the ISP command handler
execution (P2.10 is sampled HIGH after reset), a search is made for a valid user program.
If a valid user program is found then the execution control is transferred to it. If a valid user
program is not found, the auto-baud routine is invoked.
Pin P2.10 is used as a hardware request signal for ISP and therefore requires special
attention. Since P2.10 is in high impedance mode after reset, it is important that the user
provides external hardware (a pull-up resistor or other device) to put the pin in a defined
state. Otherwise unintended entry into ISP mode may occur.
When ISP mode is entered after a power on reset, the IRC and PLL are used to generate
the CCLK of 14.748 MHz. The baud rates that can easily be obtained in this case are:
9600 baud, 19200 baud, 38400 baud, 57600 baud, 115200 baud, and 230400 baud. This
may not be the case when ISP is invoked by the user application (see Section 32.8.9
“Re-invoke ISP” on page 636).
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A hardware flash signature generation capability is built into the flash memory. this feature
can be used to create a signature that can then be used to verify flash contents. Details of
flash signature generation are in Section 32.10.
If the signature is not valid, the auto-baud routine synchronizes with the host via serial port
0. The host should send a “?” (0x3F) as a synchronization character and wait for a
response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.
The auto-baud routine measures the bit time of the received synchronization character in
terms of its own frequency and programs the baud rate generator of the serial port. It also
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sends an ASCII string ("Synchronized<CR><LF>") to the host. In response to this the host
should send the same string ("Synchronized<CR><LF>"). The auto-baud routine looks at
the received characters to verify synchronization. If synchronization is verified then
"OK<CR><LF>" string is sent to the host. The host should respond by sending the crystal
frequency (in kHz) at which the part is running. For example, if the part is running at 10
MHz, the response from the host should be "10000<CR><LF>". "OK<CR><LF>" string is
sent to the host after receiving the crystal frequency. If synchronization is not verified then
the auto-baud routine waits again for a synchronization character. For auto-baud to work
correctly in case of user invoked ISP, the CCLK frequency should be greater than or equal
to 10 MHz.
For more details on Reset, PLL and startup/boot code interaction see Section 4.5.1.1
“PLL0 and startup/boot code interaction”.
Once the crystal frequency is received the part is initialized and the ISP command handler
is invoked. For safety reasons an "Unlock" command is required before executing the
commands resulting in flash erase/write operations and the "Go" command. The rest of
the commands can be executed without the unlock command. The Unlock command is
required to be executed once per ISP session. The Unlock command is explained in
Section 32.7 “ISP commands” on page 623.
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RESET
INITIALIZE
no
CRP1/2/3 ENABLED?
ENABLE DEBUG
yes
yes
WATCHDOG
FLAG SET?
A
no
yes
EXECUTE INTERNAL
USER CODE
Enter ISP
USER CODE VALID? MODE?
no (P2.10=LOW) no
yes
yes
A RUN AUTO-BAUD
no AUTO-BAUD
SUCCESSFUL?
yes
(1) For details on handling the crystal frequency, see Section 32.8.9 “Re-invoke ISP” on page 636
(2) For details on available ISP commands based on the CRP settings see Section 32.6 “Code Read Protection (CRP)”
Fig 137. Boot process flowchart
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Important: Any CRP change becomes effective only after the device has gone
through a power cycle.
[1] CRP is supported by all LPC17xx parts with the exception of part LPC1751 with
partID 0x2500 1110. Part LPC1751 with partID 0x2500 1118 supports all three CRP
levels (see Errata note).
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If any CRP mode is enabled and access to the chip is allowed via the ISP, an unsupported
or restricted ISP command will be terminated with return code
CODE_READ_PROTECTION_ENABLED.
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CMD_SUCCESS is sent by ISP command handler only when received ISP command has
been completely executed and the new ISP command can be given by the host.
Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go"
commands.
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Table 573. Correlation between possible ISP baudrates and CCLK frequency (in MHz)
ISP Baudrate .vs. 9600 19200 38400 57600 115200 230400
CCLK Frequency
10.0000 + + +
11.0592 + + +
12.2880 + + +
14.7456[1] + + + + + +
15.3600 +
18.4320 + + +
19.6608 + + +
24.5760 + + +
25.0000 + + +
[1] ISP entry after reset uses the on chip IRC and PLL to run the device at CCLK = 14.748 MHz
The ISP command handler compares it with the check-sum of the received bytes. If the
check-sum matches, the ISP command handler responds with "OK<CR><LF>" to
continue further transmission. If the check-sum does not match, the ISP command
handler responds with "RESEND<CR><LF>". In response the host should retransmit the
bytes.
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32.7.6 Prepare sector(s) for write operation <start sector number> <end
sector number>
This command makes flash write/erase operation a two step process.
32.7.7 Copy RAM to Flash <flash address> <RAM address> <no of bytes>
Table 578. ISP Copy command
Command C
Input Flash Address(DST): Destination flash address where data bytes are to be
written. The destination address should be a 256 byte boundary.
RAM Address(SRC): Source RAM address from where data bytes are to be read.
Number of Bytes: Number of bytes to be written. Should be 256 | 512 | 1024 |
4096.
Return Code CMD_SUCCESS |
SRC_ADDR_ERROR (Address not on word boundary) |
DST_ADDR_ERROR (Address not on correct boundary) |
SRC_ADDR_NOT_MAPPED |
DST_ADDR_NOT_MAPPED |
COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) |
SECTOR_NOT_PREPARED_FOR WRITE_OPERATION |
BUSY |
CMD_LOCKED |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED
Description This command is used to program the flash memory. The "Prepare Sector(s) for
Write Operation" command should precede this command. The affected sectors are
automatically protected again once the copy command is successfully executed.
This command is blocked when code read protection levels CRP2 or CRP3 are
enabled. When code read protection level CRP1 is enabled, individual sectors
other than sector 0 can be written.
Example "C 0 268468224 512<CR><LF>" copies 512 bytes from the RAM address
0x1000 8000 to the flash address 0.
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When the GO command is used, execution begins at the specified address (assuming it is
an executable address) with the device left as it was configured for the ISP code. This
means that some things are different than they would be for entering user code directly
following a chip reset. Most importantly, the main PLL will be running and connected,
configured to generate a CPU clock with a frequency of approximately 14.7456 MHz.
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[1] This part does not support CRP (see Errata note).
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Define the IAP location entry point. Bit 0 of the IAP location is set since the Cortex-M3
uses only Thumb mode.
Define data structure or pointers to pass IAP command table and result table to the IAP
function:
or
Define pointer to function type, which takes two parameters and returns void. Note the IAP
returns the result with the base address of the table residing in R1.
iap_entry=(IAP) IAP_LOCATION;
Whenever you wish to call IAP you could use the following statement.
The IAP call could be simplified further by using the symbol definition file feature
supported by ARM Linker in ADS (ARM Developer Suite). You could also call the IAP
routine using assembly code.
As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC
0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers
respectively. Additional parameters are passed on the stack. Up to 4 parameters can be
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returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned
indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM
suggested scheme is used for the parameter passing/returning then it might create
problems due to difference in the C compiler implementation from different vendors. The
suggested parameter passing scheme reduces such risk.
The flash memory is not accessible during a write or erase operation. IAP commands,
which results in a flash write/erase operation, use 32 bytes of space in the top portion of
the on-chip RAM for execution. The user program should not be use this space if IAP flash
programming is permitted in the application.
COMMAND CODE
command
PARAMETER 1 parameter table
PARAMETER 2
ARM REGISTER r0
PARAMETER n
ARM REGISTER r1
STATUS CODE
RESULT 1 command
result table
RESULT 2
RESULT n
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The address range for generating a signature must be aligned on flash-word boundaries,
i.e. 128-bit boundaries. Once started, signature generation completes independently.
While signature generation is in progress, the flash memory cannot be accessed for other
purposes, and an attempted read will cause a wait state to be asserted until signature
generation is complete. Code outside of the flash (e.g. internal RAM) can be executed
during signature generation. This can include interrupt services, if the interrupt vector
table is re-mapped to memory other than the flash memory. The code that initiates
signature generation should also be placed outside of the flash memory.
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Signature generation is started by setting the SIG_START bit in the FMSSTOP register.
Setting the SIG_START bit is typically combined with the signature stop address in a
single write.
Table 600 and Table 601 show the bit assignments in the FMSSTART and FMSSTOP
registers respectively.
Table 600. Flash Module Signature Start register (FMSSTART - 0x4008 4020) bit description
Bit Symbol Description Reset Value
31:17 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
16:0 START Signature generation start address (corresponds to AHB byte address bits[20:4]). 0
Table 601. Flash Module Signature Stop register (FMSSTOP - 0x4008 4024) bit description
Bit Symbol Value Description Reset Value
31:18 - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
17 SIG_START Start control bit for signature generation. 0
0 Signature generation is stopped
1 Initiate signature generation
16:0 STOP BIST stop address divided by 16 (corresponds to AHB byte address [20:4]). 0
The generated flash signature can be used to verify the flash memory contents. The
generated signature can be compared with an expected signature and thus makes saves
time and code space. The method for generating the signature is described in
Section 32.10.2.
Table 605 show bit assignment of the FMSW0 and FMSW1, FMSW2, FMSW3 registers
respectively.
Table 602. FMSW0 register bit description (FMSW0, address: 0x4008 402C)
Bit Symbol Description Reset Value
31:0 SW0[31:0] Word 0 of 128-bit signature (bits 31 to 0). -
Table 603. FMSW1 register bit description (FMSW1, address: 0x4008 4030)
Bit Symbol Description Reset Value
31:0 SW1[63:32] Word 1 of 128-bit signature (bits 63 to 32). -
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Table 604. FMSW2 register bit description (FMSW2, address: 0x4008 4034)
Bit Symbol Description Reset Value
31:0 SW2[95:64] Word 2 of 128-bit signature (bits 95 to 64). -
Table 605. FMSW3 register bit description (FMSW3, address: 0x4008 4038)
Bit Symbol Description Reset Value
31:0 SW3[127:96] Word 3 of 128-bit signature (bits 127 to 96). -
Table 606. Flash module Status register (FMSTAT - 0x4008 4FE0) bit description
Bit Symbol Description Reset Value
31:2 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
2 SIG_DONE When 1, a previously started signature generation has completed. See 0
FMSTATCLR register description for clearing this flag.
1:0 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
Table 607. Flash Module Status Clear register (FMSTATCLR - 0x0x4008 4FE8) bit description
Bit Symbol Description Reset Value
31:2 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
2 SIG_DONE_CLR Writing a 1 to this bits clears the signature generation completion flag 0
(SIG_DONE) in the FMSTAT register.
1:0 - Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.
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The time that the signature generation takes is proportional to the address range for which
the signature is generated. Reading of the flash memory for signature generation uses a
self-timed read mechanism and does not depend on any configurable timing settings for
the flash. A safe estimation for the duration of the signature generation is:
When signature generation is triggered via software, the duration is in AHB clock cycles,
and tcy is the time in ns for one AHB clock. The SIG_DONE bit in FMSTAT can be polled
by software to determine when signature generation is complete.
If signature generation is triggered via JTAG, the duration is in JTAG tck cycles, and tcy is
the time in ns for one JTAG clock. Polling the SIG_DONE bit in FMSTAT is not possible in
this case.
After signature generation, a 128-bit signature can be read from the FMSW0 to FMSW3
registers. The 128-bit signature reflects the corrected data read from the flash. The 128-bit
signature reflects flash parity bits and check bit values.
Content verification
The signature as it is read from the FMSW0 to FMSW3 registers must be equal to the
reference signature. The algorithms to derive the reference signature is given in
Figure 139.
sign = 0
FOR address = FMSTART.FMSTART TO FMSTOP.FMSTOP
{
FOR i = 0 TO 126
nextSign[i] = f_Q[address][i] XOR sign[i+1]
nextSign[127] = f_Q[address][127] XOR sign[0] XOR sign[2] XOR
sign[27] XOR sign[29]
sign = nextSign
}
signature128 = sign
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33.1 Features
• Supports both standard JTAG and ARM Serial Wire Debug modes.
• Direct debug access to all memories, registers, and peripherals.
• No target resources are required for the debugging session.
• Trace port provides CPU instruction trace capability. Output can be via a 4-bit trace
data port, or Serial Wire Viewer.
• Eight Breakpoints. Six instruction breakpoints that can also be used to remap
instruction addresses for code patches. Two data comparators that can be used to
remap addresses for patches to literal values.
• Four data Watchpoints that can also be used as trace triggers.
• Instrumentation Trace Macrocell allows additional software controlled trace.
33.2 Introduction
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four
watchpoints.
33.3 Description
Debugging with the LPC17xx defaults to JTAG. Once in the JTAG debug mode, the debug
tool can switch to Serial Wire Debug mode.
Trace can be done using either a 4-bit parallel interface or the Serial Wire Output. When
the Serial Wire Output is used, less data can be traced, but it uses no application related
pins. Parallel trace has a greater bandwidth, but uses 5 functional pins that may be
needed in the application. Note that the trace function available for the Cortex-M3 is
functionally very different than the trace that was available for previous ARM7 based
devices, using only 5 pins instead of 10.
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Another issue is that debug mode changes the way in which reduced power modes are
handled by the Cortex-M3 CPU. This causes power modes at the device level to be
different from normal modes operation. These differences mean that power
measurements should not be made while debugging, the results will be higher than during
normal operation in an application.
During a debugging session, the System Tick Timer and the Repetitive Interrupt Timers
are automatically stopped whenever the CPU is stopped. Other peripherals are not
affected. If the Repetitive Interrupt Timer is configured such that its PCLK rate is lower
than the CPU clock rate, the RIT may not increment predictably during some debug
operations, such as single stepping.
However, when a debugger halts CPU execution immediately following reset, the Boot
ROM is still mapped to address 0 and can cause confusion. Ideally, the debugger should
correct the mapping automatically in this case, so that a user does not need to deal with it.
Table 611. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
Bit Symbol Value Description Reset
value
0 MAP Memory map control. 0
0 Boot mode. A portion of the Boot ROM is mapped to address 0.
1 User mode. The on-chip Flash memory is mapped to address 0.
31:1 - Reserved. The value read from a reserved bit is not defined. NA
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Cortex-M3
processor
Processor Embedded
WIC NVIC
core Trace Macrocell
Debug Serial
Memory
Access Wire
protection unit
Port viewer
Flash Data
patch watchpoints
Bus matrix
Code SRAM and
interface peripheral interface
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to be rapidly powered down.
LPC17xx devices support additional reduced power modes, see Section 4.8 “Power
control” for details.
The Cortex-M3 processor has an optional memory protection unit (MPU) that provides
fine grain memory control, enabling applications to implement security privilege levels,
separating code, data and stack on a task-by-task basis. Such requirements are
becoming critical in many embedded applications such as automotive. The MPU is
included in LPC17xx devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM)
alongside data watchpoints and a profiling unit. To enable simple and cost-effective
profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a
stream of software-generated messages, data trace, and profiling information through a
single pin.
The optional Embedded Trace Macrocell (ETM) delivers unrivalled instruction trace
capture in an area far smaller than traditional trace units, enabling many low cost MCUs to
implement full instruction trace for the first time.
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LPC17xx devices support JTAG and Serial Wire Debug, Serial Wire Viewer, and include
the Embedded Trace Macrocell. See Section 33.1 for additional information.
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Note
In Table 612:
For more information on the instructions and operands, see the instruction descriptions.
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The CMSIS provides the following intrinsic functions to generate instructions that ANSI
cannot directly access:
The CMSIS also provides a number of functions for accessing the special registers using
MRS and MSR instructions:
34.2.3.1 Operands
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination
register. When there is a destination register in the instruction, it is usually specified before
the operands.
Operands in some instructions are flexible in that they can either be a register or a
constant. See Section 34.2.3.3.
Remark: Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction
must be 1 for correct execution, because this bit indicates the required instruction set, and
the Cortex-M3 processor only supports Thumb instructions.
Operand2 can be a:
#constant
• any constant that can be produced by shifting an 8-bit value left by any number of bits
within a 32-bit word
• any constant of the form 0x00XY00XY
• any constant of the form 0xXY00XY00
• any constant of the form 0xXYXYXYXY.
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In addition, in a small number of instructions, constant can take a wider range of values.
These are described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS,
BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater
than 255 and can be produced by shifting an 8-bit value. These instructions do not affect
the carry flag if Operand2 is any other constant.
Rm {, shift}
where:
If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.
If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value
is used by the instruction. However, the contents in the register Rm remains unchanged.
Specifying a register with shift also updates the carry flag when used with certain
instructions. For information on the shift operations and how they affect the carry flag, see
Section 34.2.3.4 “Shift Operations”
• directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a
destination register
• during the calculation of Operand2 by the instructions that specify the second
operand as a register with shift, see Section 34.2.3.3. The result is used by the
instruction.
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The permitted shift lengths depend on the shift type and the instruction, see the individual
instruction description or Section 34.2.3.3. If the shift length is 0, no shift occurs. Register
shift operations update the carry flag except when the specified shift length is 0. The
following sub-sections describe the various shift operations and how they affect the carry
flag. In these descriptions, Rm is the register containing the value to be shifted, and n is
the shift length.
34.2.3.4.1 ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right
by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of
the register into the left-hand n bits of the result. See Figure 141.
You can use the ASR #n operation to divide the value in the register Rm by 2n, with the
result being rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
Note
• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of
Rm.
Carry
Flag
31 5 4 3 2 1 0
...
Fig 141. ASR #3
34.2.3.4.2 LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by
n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the
result to 0. See Figure 142.
You can use the LSR #n operation to divide the value in the register Rm by 2n, if the value
is regarded as an unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
Note
0 0 0 Carry
Flag
31 5 4 3 2 1 0
...
Fig 142. LSR#3
34.2.3.4.3 LSL
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n
places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the
result to 0. See Figure 143.
You can use he LSL #n operation to multiply the value in the register Rm by 2n, if the value
is regarded as an unsigned integer or a two’s complement signed integer. Overflow can
occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with
the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated
to the last bit shifted out, bit[32-n], of the register Rm. These instructions do not affect the
carry flag when used with LSL #0.
Note
0 0 0
31 5 4 3 2 1 0
Carry
Flag ...
Fig 143. LSL#3
34.2.3.4.4 ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the
register into the left-hand n bits of the result. See Figure 144.
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
rotation, bit[n-1], of the register Rm.
Note
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• If n is 32, then the value of the result is same as the value in Rm, and if the carry flag
is updated, it is updated to bit[31] of Rm.
• ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
Carry
Flag
31 5 4 3 2 1 0
...
Fig 144. ROR#3
34.2.3.4.5 RRX
Rotate right with extend moves the bits of the register Rm to the right by one bit. And it
copies the carry flag into bit[31] of the result. See Figure 145.
When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register
Rm.
Carry
Flag
31 30 1 0
... ...
Fig 145. RRX
The Cortex-M3 processor supports unaligned access only for the following instructions:
• LDR, LDRT
• LDRH, LDRHT
• LDRSH, LDRSHT
• STR, STRT
• STRH, STRHT
All other load and store instructions generate a usage fault exception if they perform an
unaligned access, and therefore their accesses must be address aligned. For more
information about usage faults see Section 34.3.4 “Fault handling”.
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Unaligned accesses are usually slower than aligned accesses. In addition, some memory
regions might not support unaligned accesses. Therefore, ARM recommends that
programmers ensure that accesses are aligned. To avoid accidental generation of
unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register
to trap all unaligned accesses, see Section 34.4.3.8 “Configuration and Control Register”.
Note
• For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current
instruction plus 4 bytes.
• For all other instructions that use labels, the value of the PC is the address of the
current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it
word-aligned.
• Your assembler might permit other syntaxes for PC-relative expressions, such as a
label plus or minus a number, or an expression of the form [PC, #number].
You can execute an instruction conditionally, based on the condition flags set in another
instruction, either:
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Use the CBZ and CBNZ instructions to compare the value of a register against zero and
branch on the result.
N — Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Z — Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
For more information about the APSR see Section 34.3.1.3.5 “Program Status Register”.
A carry occurs:
Remark: Most instructions update the status flags only if the S suffix is specified. See the
instruction descriptions for more information.
You can use conditional execution with the IT instruction to reduce the number of branch
instructions in code.
Table 615 also shows the relationship between condition code suffixes and the N, Z, C,
and V flags.
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Section shows the use of a conditional instruction to find the absolute value of a number.
R0 = ABS(R1).
Section shows the use of conditional instructions to update the value of R4 if the signed
values R0 is greater than R1 and R2 is greater than R3.
Example: Compare and update value: CMP R0, R1 ; Compare R0 and R1,
setting flags
ITT GT ; IT instruction for the two GT conditions
CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags
MOVGT R4, R5 ; If still 'greater than', do R4 = R5
If you specify an instruction width suffix and the assembler cannot generate an instruction
encoding of the requested width, it generates an error.
Remark: In some cases it might be necessary to specify the .W suffix, for example if the
operand is the label of an instruction or literal data, as in the case of branch instructions.
This is because the assembler might not automatically generate the right size encoding.
To use an instruction width suffix, place it immediately after the instruction mnemonic and
condition code, if any. Section 34.2.3.8.1 shows instructions with the instruction width
suffix.
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ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction
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34.2.4.1 ADR
Load PC-relative address.
34.2.4.1.1 Syntax
ADR{cond} Rd, label
where:
34.2.4.1.2 Operation
ADR determines the address by adding an immediate value to the PC, and writes the result
to the destination register.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that
bit[0] of the address you generate is set to1 for correct execution.
Values of label must be within the range of −4095 to +4095 from the address in the PC.
Remark: You might have to use the .W suffix to get the maximum offset range or to
generate addresses that are not word-aligned. See Section 34.2.3.8 “Instruction width
selection”.
34.2.4.1.3 Restrictions
Rd must not be SP and must not be PC.
34.2.4.1.5 Examples
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34.2.4.2.1 Syntax
op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
where:
op is one of:
offset is an offset from Rn. If offset is omitted, the address is the contents of Rn.
34.2.4.2.2 Operation
LDR instructions load one or two registers with a value from memory.
Load and store instructions with immediate offset can use the following addressing
modes:
• Offset addressing
The offset value is added to or subtracted from the address obtained from the register
Rn. The result is used as the address for the memory access. The register Rn is
unaltered. The assembly language syntax for this mode is:
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[Rn, #offset]
• Pre-indexed addressing
The offset value is added to or subtracted from the address obtained from the register
Rn. The result is used as the address for the memory access and written back into the
register Rn. The assembly language syntax for this mode is:
[Rn, #offset]!
• Post-indexed addressing
The address obtained from the register Rn is used as the address for the memory
access. The offset value is added to or subtracted from the address, and written back
into the register Rn. The assembly language syntax for this mode is:
[Rn], #offset
The value to load or store can be a byte, halfword, word, or two words. Bytes and
halfwords can either be signed or unsigned. See Section 34.2.3.5 “Address alignment”.
Table 617 shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
34.2.4.2.3 Restrictions
For load instructions:
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34.2.4.2.5 Examples
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34.2.4.3.1 Syntax
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op is one of:
34.2.4.3.2 Operation
LDR instructions load a register with a value from memory.
The memory address to load from or store to is at an offset from the register Rn. The
offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes
and halfwords can either be signed or unsigned. See Section 34.2.3.5 “Address
alignment”.
34.2.4.3.3 Restrictions
In these instructions:
• Rn must not be PC
• Rm must not be SP and must not be PC
• Rt can be SP only for word loads and word stores
• Rt can be PC only for word loads.
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• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
34.2.4.3.4 Condition flags
These instructions do not change the flags.
34.2.4.3.5 Examples
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34.2.4.4.1 Syntax
op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset
where:
op is one of:
offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value
in Rn.
34.2.4.4.2 Operation
These load and store instructions perform the same function as the memory access
instructions with immediate offset, see Section 34.2.4.2. The difference is that these
instructions have only unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way
as normal memory access instructions with immediate offset.
34.2.4.4.3 Restrictions
In these instructions:
• Rn must not be PC
• Rt must not be SP and must not be PC.
34.2.4.4.4 Condition flags
These instructions do not change the flags.
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34.2.4.4.5 Examples
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34.2.4.5.1 Syntax
LDR{type}{cond} Rt, label
34.2.4.5.2 Operation
LDR loads a register with a value from a PC-relative memory address. The memory
address is specified by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes
and halfwords can either be signed or unsigned. See Section 34.2.3.5 “Address
alignment”.
label must be within a limited range of the current instruction. Table 618 shows the
possible offsets between label and the PC.
Remark: You might have to use the .W suffix to get the maximum offset range. See
Section 34.2.3.8 “Instruction width selection”.
34.2.4.5.3 Restrictions
In these instructions:
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• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
34.2.4.5.4 Condition flags
These instructions do not change the flags.
34.2.4.5.5 Examples
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34.2.4.6.1 Syntax
op{addr_mode}{cond} Rn{!}, reglist
where:
op is one of:
! is an optional writeback suffix. If ! is present the final address, that is loaded from or
stored to, is written back into Rn.
reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can
contain register ranges. It must be comma separated if it contains more than one register
or register range, see Section 34.2.4.6.5.
LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full
Descending stacks.
LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending
stacks.
STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty
Ascending stacks.
STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending
stacks
34.2.4.6.2 Operation
LDM instructions load the registers in reglist with word values from memory addresses
based on Rn.
STM instructions store the word values in the registers in reglist to memory addresses
based on Rn.
For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses
are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of
registers in reglist. The accesses happens in order of increasing register numbers, with
the lowest numbered register using the lowest memory address and the highest number
register using the highest memory address. If the writeback suffix is specified, the value of
Rn + 4 * (n-1) is written back to Rn.
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For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at
4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in
reglist. The accesses happen in order of decreasing register numbers, with the highest
numbered register using the highest memory address and the lowest number register
using the lowest memory address. If the writeback suffix is specified, the value of
Rn - 4 * (n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See Section 34.2.4.7 for
details.
34.2.4.6.3 Restrictions
In these instructions:
• Rn must not be PC
• reglist must not contain SP
• in any STM instruction, reglist must not contain PC
• in any LDM instruction, reglist must not contain PC if it contains LR
• reglist must not contain Rn if you specify the writeback suffix.
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch
occurs to this halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
34.2.4.6.4 Condition flags
These instructions do not change the flags.
34.2.4.6.5 Examples
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34.2.4.7.1 Syntax
PUSH{cond} reglist
POP{cond} reglist
where:
reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It
must be comma separated if it contains more than one register or register range.
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the
access based on SP, and with the final address for the access written back to the SP. PUSH
and POP are the preferred mnemonics in these cases.
34.2.4.7.2 Operation
PUSH stores registers on the stack in order of decreasing the register numbers, with the
highest numbered register using the highest memory address and the lowest numbered
register using the lowest memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest
numbered register using the lowest memory address and the highest numbered register
using the highest memory address.
34.2.4.7.3 Restrictions
In these instructions:
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch
occurs to this halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
34.2.4.7.4 Condition flags
These instructions do not change the flags.
34.2.4.7.5 Examples
PUSH {R0,R4-R7}
PUSH {R2,LR}
POP {R0,R10,PC}
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34.2.4.8.1 Syntax
LDREX{cond} Rt, [Rn {, #offset}]
where:
offset is an optional offset applied to the value in Rn. If offset is omitted, the address is the
value in Rn.
34.2.4.8.2 Operation
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory
address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a
memory address. The address used in any Store-Exclusive instruction must be the same
as the address in the most recently executed Load-exclusive instruction. The value stored
by the Store-Exclusive instruction must also have the same data size as the value loaded
by the preceding Load-exclusive instruction. This means software must always use a
Load-exclusive instruction and a matching Store-Exclusive instruction to perform a
synchronization operation, see Section 34.3.2.7 “Synchronization primitives”
34.2.4.8.3 Restrictions
In these instructions:
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• do not use PC
• do not use SP for Rd and Rt
• for STREX, Rd must be different from both Rt and Rn
• the value of offset must be a multiple of four in the range 0-1020.
34.2.4.8.5 Examples
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34.2.4.9 CLREX
Clear Exclusive.
34.2.4.9.1 Syntax
CLREX{cond}
where:
34.2.4.9.2 Operation
Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination
register and fail to perform the store. It is useful in exception handler code to force the
failure of the store exclusive if the exception occurs between a load exclusive instruction
and the matching store exclusive instruction in a synchronization operation.
34.2.4.9.4 Examples
CLREX
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34.2.5.1.1 Syntax
op{S}{cond} {Rd,} Rn, Operand2
where:
op is one of:
ADD: Add.
ADC: Add with Carry.
SUB: Subtract.
RSB: Reverse Subtract.
S: is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see Section 34.2.3.7 “Conditional execution”.
Operand2 is a flexible second operand. See Section 34.2.3.3 for details of the options.
34.2.5.1.2 Operation
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag
is clear, the result is reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful
because of the wide range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see Section 34.2.5.1.6.
Remark: ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is
equivalent to the SUB syntax that uses the imm12 operand.
34.2.5.1.3 Restrictions
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– Rn must also be SP
– any shift in Operand2 must be limited to a maximum of 3 bits using LSL
• Rn can be SP only in ADD and SUB
• Rd can be PC only in the cond instruction where:
– you must not specify the S suffix
– Rm must not be PC and must not be SP
– if the instruction is conditional, it must be the last instruction in the IT block
• with the exception of the cond instruction, Rn can be PC only in ADD and SUB, and only
with the additional restrictions:
– you must not specify the S suffix
– the second operand must be a constant in the range 0 to 4095.
Note
• When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to
b00 before performing the calculation, making the base address for the calculation
word-aligned.
• If you want to generate the address of an instruction, you have to adjust the constant
based on the value of the PC. ARM recommends that you use the ADR instruction
instead of ADD or SUB with Rn equal to the PC, because your assembler automatically
calculates the correct constant for the ADR instruction.
34.2.5.1.5 Examples
Multiword values do not have to use consecutive registers. Section shows instructions
that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6,
R2, and R8. The example stores the result in R6, R9, and R2.
64-bit addition:
ADDS R4, R0, R2 ; add the least significant words
ADC R5, R1, R3 ; add the most significant words with carry
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96-bit subtraction:
SUBS R6, R6, R9 ; subtract the least significant words
SBCS R9, R2, R1 ; subtract the middle words with carry
SBC R2, R8, R11 ; subtract the most significant words with carry
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34.2.5.2.1 Syntax
op{S}{cond} {Rd,} Rn, Operand2
where:
op is one of:
S is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see Section 34.2.3.7 “Conditional execution”.
Operand2 is a flexible second operand. See Section 34.2.3.3 for details of the options.
34.2.5.2.2 Operation
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations
on the values in Rn and Operand2.
The BIC instruction performs an AND operation on the bits in Rn with the complements of
the corresponding bits in the value of Operand2.
The ORN instruction performs an OR operation on the bits in Rn with the complements of
the corresponding bits in the value of Operand2.
34.2.5.2.3 Restrictions
Do not use SP and do not use PC.
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34.2.5.3.1 Syntax
op{S}{cond} Rd, Rm, Rs
RRX{S}{cond} Rd, Rm
where:
op is one of:
S is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see Section 34.2.3.7 “Conditional execution”.
Rm is the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
Rs s the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
n is the shift length. The range of shift length depends on the instruction:
Remark: MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.
34.2.5.3.2 Operation
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of
places specified by constant n or register Rs.
In all these instructions, the result is written to Rd, but the value in register Rm remains
unchanged. For details on what result is generated by the different instructions, see
Section 34.2.3.4 “Shift Operations”.
34.2.5.3.3 Restrictions
Do not use SP and do not use PC.
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34.2.5.3.5 Examples
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34.2.5.4 CLZ
Count Leading Zeros.
34.2.5.4.1 Syntax
CLZ{cond} Rd, Rm
where:
34.2.5.4.2 Operation
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the
result in Rd. The result value is 32 if no bits are set in the source register, and zero if
bit[31] is set.
34.2.5.4.3 Restrictions
Do not use SP and do not use PC.
34.2.5.4.5 Examples
CLZ R4,R9
CLZNE R2,R3
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34.2.5.5.1 Syntax
CMP{cond} Rn, Operand2
where:
Operand2 is a flexible second operand. See Flexible second operand on page 3-10for
details of the options.
34.2.5.5.2 Operation
These instructions compare the value in a register with Operand2. They update the
condition flags on the result, but do not write the result to a register.
The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same
as a SUBS instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an
ADDS instruction, except that the result is discarded.
34.2.5.5.3 Restrictions
In these instructions:
• do not use PC
• Operand2 must not be SP.
34.2.5.5.4 Condition flags
These instructions update the N, Z, C and V flags according to the result.
34.2.5.5.5 Examples
CMP R2, R9
CMN R0, #6400
CMPGT SP, R7, LSL #2
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34.2.5.6.1 Syntax
MOV{S}{cond} Rd, Operand2
where:
S is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see Section 34.2.3.7.
Operand2 is a flexible second operand. See Flexible second operand on page 3-10for
details of the options.
34.2.5.6.2 Operation
The MOV instruction copies the value of Operand2 into Rd.
When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the
preferred syntax is the corresponding shift instruction:
• ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
• LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #nn if !=
0
• LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
• ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
• RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift
instructions:
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation
on the value, and places the result into Rd.
Remark: The MOVW instruction provides the same function as MOV, but is restricted to using
the imm16 operand.
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34.2.5.6.3 Restrictions
You can use SP and PC only in the MOV instruction, with the following restrictions:
MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated
MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated
MOVS R10, R12 ; Write value in R12 to R10, flags get updated
MOV R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags
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34.2.5.7 MOVT
Move Top.
34.2.5.7.1 Syntax
MOVT{cond} Rd, #imm16
where:
34.2.5.7.2 Operation
MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its
destination register. The write does not affect Rd[15:0].
The MOV, MOVT instruction pair enables you to generate any 32-bit constant.
34.2.5.7.3 Restrictions
Rd must not be SP and must not be PC.
34.2.5.7.5 Examples
MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged
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34.2.5.8.1 Syntax
op{cond} Rd, Rn
where:
op is any of:
34.2.5.8.2 Operation
Use these instructions to change endianness of data:
REV: converts 32-bit big-endian data into little-endian data or 32-bit little-endian data into
big-endian data.
REV16 converts 16-bit big-endian data into little-endian data or 16-bit little-endian data
into big-endian data.
REVSH converts either:
16-bit signed big-endian data into 32-bit signed little-endian data
16-bit signed little-endian data into 32-bit signed big-endian data.
34.2.5.8.3 Restrictions
Do not use SP and do not use PC.
34.2.5.8.5 Examples
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34.2.5.9.1 Syntax
TST{cond} Rn, Operand2
where:
Operand2 is a flexible second operand. See Section 34.2.3.3 for details of the options.
34.2.5.9.2 Operation
These instructions test the value in a register against Operand2. They update the
condition flags based on the result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of
Operand2. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that
has that bit set to 1 and all other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the
value of Operand2. This is the same as the EORS instruction, except that it discards the
result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the
logical Exclusive OR of the sign bits of the two operands.
34.2.5.9.3 Restrictions
Do not use SP and do not use PC.
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34.2.6.1.1 Syntax
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
where:
S is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see Section 34.2.3.7 “Conditional execution”.
34.2.6.1.2 Operation
The MUL instruction multiplies the values from Rn and Rm, and places the least significant
32 bits of the result in Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and
places the least significant 32 bits of the result in Rd.
The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the
value from Ra, and places the least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or
unsigned.
34.2.6.1.3 Restrictions
In these instructions, do not use SP and do not use PC.
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34.2.6.1.5 Examples
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34.2.6.2.1 Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
RdHi, RdLo are the destination registers. For UMLAL and SMLAL they also hold the
accumulating value.
34.2.6.2.2 Operation
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It
multiplies these integers and places the least significant 32 bits of the result in RdLo, and
the most significant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It
multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in
RdHi and RdLo, and writes the result back to RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed
integers. It multiplies these integers and places the least significant 32 bits of the result in
RdLo, and the most significant 32 bits of the result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed
integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer
contained in RdHi and RdLo, and writes the result back to RdHi and RdLo.
34.2.6.2.3 Restrictions
In these instructions:
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34.2.6.2.5 Examples
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34.2.6.3.1 Syntax
SDIV{cond} {Rd,} Rn, Rm
where:
34.2.6.3.2 Operation
SDIV performs a signed integer division of the value in Rn by the value in Rm.
UDIV performs an unsigned integer division of the value in Rn by the value in Rm.
For both instructions, if the value in Rn is not divisible by the value in Rm, the result is
rounded towards zero.
34.2.6.3.3 Restrictions
Do not use SP and do not use PC.
34.2.6.3.5 Examples
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34.2.7.1.1 Syntax
op{cond} Rd, #n, Rm {, shift #s}
where:
op is one of:
shift #s is an optional shift applied to Rm before saturating. It must be one of the following:
34.2.7.1.2 Operation
These instructions saturate to a signed or unsigned n-bit value.
The SSAT instruction applies the specified shift, then saturates to the signed range
−2n–1 ≤ x ≤ 2n–1−1.
The USAT instruction applies the specified shift, then saturates to the unsigned range
0 ≤ x ≤ 2n−1.
• if the value to be saturated is less than −2n-1, the result returned is −2n-1
• if the value to be saturated is greater than 2n-1−1, the result returned is 2n-1−1
• otherwise, the result returned is the same as the value to be saturated.
For unsigned n-bit saturation using USAT, this means that:
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To read the state of the Q flag, use the MRS instruction, see Section 34.2.10.6.
34.2.7.1.3 Restrictions
Do not use SP and do not use PC.
34.2.7.1.5 Examples
SSAT R7, #16, R7, LSL #4 ; Logical shift left value in R7 by 4, then
; saturate it as a signed 16-bit value and
; write it back to R7
USATNE R0, #7, R5 ; Conditionally saturate value in R5 as an
; unsigned 7 bit value and write it to R0
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34.2.8.1.1 Syntax
BFC{cond} Rd, #lsb, #width
where:
lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31.
width is the width of the bitfield and must be in the range 1 to 32−lsb.
34.2.8.1.2 Operation
BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position
lsb. Other bits in Rd are unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd
starting at the low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd
are unchanged.
34.2.8.1.3 Restrictions
Do not use SP and do not use PC.
34.2.8.1.5 Examples
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34.2.8.2.1 Syntax
SBFX{cond} Rd, Rn, #lsb, #width
where:
lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31.
width is the width of the bitfield and must be in the range 1 to 32−lsb.
34.2.8.2.2 Operation
SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to
the destination register.
UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to
the destination register.
34.2.8.2.3 Restrictions
Do not use SP and do not use PC.
34.2.8.2.5 Examples
SBFX R0, R1, #20, #4 ; Extract bit 20 to bit 23 (4 bits) from R1 and sign
; extend to 32 bits and then write the result to R0.
UBFX R8, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from R11 and zero
; extend to 32 bits and then write the result to R8
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34.2.8.3.1 Syntax
SXTextend{cond} {Rd,} Rm {, ROR #n}
where:
34.2.8.3.2 Operation
These instructions do the following:
34.2.8.3.3 Restrictions
Do not use SP and do not use PC.
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34.2.8.3.5 Examples
SXTH R4, R6, ROR #16 ; Rotate R6 right by 16 bits, then obtain the lower
; halfword of the result and then sign extend to
; 32 bits and write the result to R4.
UXTB R3, R10 ; Extract lowest byte of the value in R10 and zero
; extend it, and write the result to R3
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34.2.9.1.1 Syntax
B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
where:
B is branch (immediate).
Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm must be
1, but the address to branch to is created by changing bit[0] to 0.
34.2.9.1.2 Operation
All these instructions cause a branch to label, or to the address indicated in Rm. In
addition:
• The BL and BLX instructions write the address of the next instruction to LR (the link
register, R14).
• The BX and BLX instructions cause a UsageFault exception if bit[0] of Rm is 0.
Bcond label is the only conditional instruction that can be either inside or outside an IT
block. All other branch instructions must be conditional inside an IT block, and must be
unconditional outside the IT block, see Section 34.2.9.3.
Table 623 shows the ranges for the various branch instructions.
Remark: You might have to use the .W suffix to get the maximum branch range. See
Section 34.2.3.8 “Instruction width selection”.
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34.2.9.1.3 Restrictions
The restrictions are:
Bcond is the only conditional instruction that is not required to be inside an IT block.
However, it has a longer branch range when it is inside an IT block.
34.2.9.1.5 Examples
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34.2.9.2.1 Syntax
CBZ Rn, label
where:
34.2.9.2.2 Operation
Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce
the number of instructions.
CBZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BEQ label
CBNZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BNE label
34.2.9.2.3 Restrictions
The restrictions are:
34.2.9.2.5 Examples
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34.2.9.3 IT
If-Then condition instruction.
34.2.9.3.1 Syntax
IT{x{y{z}}} cond
where:
x specifies the condition switch for the second instruction in the IT block.
y specifies the condition switch for the third instruction in the IT block.
z specifies the condition switch for the fourth instruction in the IT block.
cond specifies the condition for the first instruction in the IT block.
The condition switch for the second, third and fourth instruction in the IT block can be
either:
Remark: It is possible to use AL (the always condition) for cond in an IT instruction. If this
is done, all of the instructions in the IT block must be unconditional, and each of x, y, and
z must be T or omitted but not E.
34.2.9.3.2 Operation
The IT instruction makes up to four following instructions conditional. The conditions can
be all the same, or some of them can be the logical inverse of the others. The conditional
instructions following the IT instruction form the IT block.
The instructions in the IT block, including any branches, must specify the condition in the
{cond} part of their syntax.
Remark: Your assembler might be able to generate the required IT instructions for
conditional instructions automatically, so that you do not need to write them yourself. See
your assembler documentation for details.
Instructions designed for use for exception returns can be used as normal to return from
the exception, and execution of the IT block resumes correctly. This is the only way that a
PC-modifying instruction is permitted to branch to an instruction in an IT block.
34.2.9.3.3 Restrictions
The following instructions are not permitted in an IT block:
• IT
• CBZ and CBNZ
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• a branch or any instruction that modifies the PC must either be outside an IT block or
must be the last instruction inside the IT block. These are:
– ADD PC, PC, Rm
– MOV PC, Rm
– B, BL, BX, BLX
– any LDM, LDR, or POP instruction that writes to the PC
– TBB and TBH
• do not branch to any instruction inside an IT block, except when returning from an
exception handler
• all conditional instructions except Bcond must be inside an IT block. Bcond can be
either outside or inside an IT block but has a larger branch range if it is inside one
• each instruction inside the IT block must specify a condition code suffix that is either
the same or logical inverse as for the other instructions in the block.
Remark: Your assembler might place extra restrictions on the use of IT blocks, such as
prohibiting the use of assembler directives within them.
34.2.9.3.5 Example
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34.2.9.4.1 Syntax
TBB [Rn, Rm]
where:
If Rn is PC, then the address of the table is the address of the byte immediately following
the TBB or TBH instruction.
Rm is the index register. This contains an index into the table. For halfword tables, LSL #1
doubles the value in Rm to form the right offset into the table.
34.2.9.4.2 Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets
for TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an
index into the table. For TBB the branch offset is twice the unsigned value of the byte
returned from the table. and for TBH the branch offset is twice the unsigned value of the
halfword returned from the table. The branch occurs to the address at that offset from the
address of the byte immediately after the TBB or TBH instruction.
34.2.9.4.3 Restrictions
The restrictions are:
• Rn must not be SP
• Rm must not be SP and must not be PC
• when any of these instructions is used inside an IT block, it must be the last
instruction of the IT block.
34.2.9.4.5 Examples
TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the
; branch table
BranchTable_H
DCI ((CaseA - BranchTable_H)/2) ; CaseA offset calculation
DCI ((CaseB - BranchTable_H)/2) ; CaseB offset calculation
DCI ((CaseC - BranchTable_H)/2) ; CaseC offset calculation
CaseA
; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
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34.2.10.1 BKPT
Breakpoint.
34.2.10.1.1 Syntax
BKPT #imm
where:
34.2.10.1.2 Operation
The BKPT instruction causes the processor to enter Debug state. Debug tools can use this
to investigate system state when the instruction at a particular address is reached.
imm is ignored by the processor. If required, a debugger can use it to store additional
information about the breakpoint.
The BKPT instruction can be placed inside an IT block, but it executes unconditionally,
unaffected by the condition specified by the IT instruction.
34.2.10.1.4 Examples
BKPT 0xAB ; Breakpoint with immediate value set to 0xAB (debugger can
; extract the immediate value by locating it using the PC)
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34.2.10.2 CPS
Change Processor State.
34.2.10.2.1 Syntax
CPSeffect iflags
where:
34.2.10.2.2 Operation
CPS changes the PRIMASK and FAULTMASK special register values. See
Section 34.3.1.3.6 “Exception mask registers” for more information about these registers.
34.2.10.2.3 Restrictions
The restrictions are:
• use CPS only from privileged software, it has no effect if used in unprivileged software.
• CPS cannot be conditional and so must not be used inside an IT block.
34.2.10.2.4 Condition flags
This instruction does not change the condition flags.
34.2.10.2.5 Examples
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34.2.10.3 DMB
Data Memory Barrier.
34.2.10.3.1 Syntax
DMB{cond}
where:
34.2.10.3.2 Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that
appear, in program order, before the DMB instruction are completed before any explicit
memory accesses that appear, in program order, after the DMB instruction. DMB does not
affect the ordering or execution of instructions that do not access memory.
34.2.10.3.4 Examples
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34.2.10.4 DSB
Data Synchronization Barrier.
34.2.10.4.1 Syntax
DSB{cond}
where:
34.2.10.4.2 Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the
DSB, in program order, do not execute until the DSB instruction completes. The DSB
instruction completes when all explicit memory accesses before it complete.
34.2.10.4.4 Examples
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34.2.10.5 ISB
Instruction Synchronization Barrier.
34.2.10.5.1 Syntax
ISB{cond}
where:
34.2.10.5.2 Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
so that all instructions following the ISB are fetched from cache or memory again, after the
ISB instruction has been completed.
34.2.10.5.4 Examples
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34.2.10.6 MRS
Move the contents of a special register to a general-purpose register.
34.2.10.6.1 Syntax
MRS{cond} Rd, spec_reg
where:
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI,
BASEPRI_MAX, FAULTMASK, or CONTROL.
34.2.10.6.2 Operation
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a
PSR, for example to clear the Q flag.
In process swap code, the programmers model state of the process being swapped out
must be saved, including relevant PSR contents. Similarly, the state of the process being
swapped in must also be restored. These operations use MRS in the state-saving
instruction sequence and MSR in the state-restoring instruction sequence.
Remark: BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
34.2.10.6.3 Restrictions
Rd must not be SP and must not be PC.
34.2.10.6.5 Examples
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34.2.10.7 MSR
Move the contents of a general-purpose register into the specified special register.
34.2.10.7.1 Syntax
MSR{cond} spec_reg, Rn
where:
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI,
BASEPRI_MAX, FAULTMASK, or CONTROL.
34.2.10.7.2 Operation
The register access operation in MSR depends on the privilege level. Unprivileged software
can only access the APSR, see Table 628 “APSR bit assignments”. Privileged software can
access all special registers.
In unprivileged software writes to unallocated or execution state bits in the PSR are
ignored.
Note
When you write to BASEPRI_MAX, the instruction writes to BASEPRI only if either:
34.2.10.7.3 Restrictions
Rn must not be SP and must not be PC.
34.2.10.7.5 Examples
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34.2.10.8 NOP
No Operation.
34.2.10.8.1 Syntax
NOP{cond}
where:
34.2.10.8.2 Operation
NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might
remove it from the pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the following instruction on a 64-bit boundary.
34.2.10.8.4 Examples
NOP ; No operation
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34.2.10.9 SEV
Send Event.
34.2.10.9.1 Syntax
SEV{cond}
where:
34.2.10.9.2 Operation
SEV is a hint instruction that causes an event to be signaled to all processors within a
multiprocessor system. It also sets the local event register to 1, see Section 34.3.5 “Power
management”.
34.2.10.9.4 Examples
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34.2.10.10 SVC
Supervisor Call.
34.2.10.10.1 Syntax
SVC{cond} #imm
where:
34.2.10.10.2 Operation
The SVC instruction causes the SVC exception.
imm is ignored by the processor. If required, it can be retrieved by the exception handler to
determine what service is being requested.
34.2.10.10.4 Examples
SVC 0x32 ; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
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34.2.10.11 WFE
Wait For Event.
34.2.10.11.1 Syntax
WFE{cond}
where:
34.2.10.11.2 Operation
WFE is a hint instruction.
If the event register is 0, WFE suspends execution until one of the following events occurs:
• an exception, unless masked by the exception mask registers or the current priority
level
• an exception enters the Pending state, if SEVONPEND in the System Control Register is
set
• a Debug Entry request, if Debug is enabled
• an event signaled by a peripheral or another processor in a multiprocessor system
using the SEV instruction.
34.2.10.11.4 Examples
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34.2.10.12 WFI
Wait for Interrupt.
34.2.10.12.1 Syntax
WFI{cond}
where:
34.2.10.12.2 Operation
WFI is a hint instruction that suspends execution until one of the following events occurs:
• an exception
• a Debug Entry request, regardless of whether Debug is enabled.
34.2.10.12.3 Condition flags
This instruction does not change the flags.
34.2.10.12.4 Examples
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• Thread mode
Used to execute application software. The processor enters Thread mode when it
comes out of reset.
• Handler mode
Used to handle exceptions. The processor returns to Thread mode when it has
finished exception processing.
• Unprivileged
The software:
– has limited access to the MSR and MRS instructions, and cannot use the CPS
instruction
– cannot access the system timer, NVIC, or system control block
– might have restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
• Privileged
The software can use all the instructions and has access to all resources.
Privileged software executes at the privileged level.
In Thread mode, the CONTROL register controls whether software execution is privileged
or unprivileged, see Table 634. In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level
for software execution in Thread mode. Unprivileged software can use the SVC instruction
to make a supervisor call to transfer control to privileged software.
34.3.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer indicates the
last stacked item on the stack memory. When the processor pushes a new item onto the
stack, it decrements the stack pointer and then writes the item to the new memory
location. The processor implements two stacks, the main stack and the process stack,
with independent copies of the stack pointer, see Section 34.3.1.3.2.
In Thread mode, the CONTROL register controls whether the processor uses the main
stack or the process stack, see Table 634. In Handler mode, the processor always uses
the main stack. The options for processor operations are:
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Table 625. Summary of processor mode, execution privilege level, and stack use options
Processor Used to Privilege level for Stack used
mode execute software execution
Thread Applications Privileged or Main stack or process
unprivileged [1] stack [1]
Handler Exception handlers Always privileged Main stack
R0
R1
R2
R3
Low registers
R4
R5
R6 General-purpose registers
R7
R8
R9
High registers R10
R11
R12
Stack Pointer SP (R13) PSP‡ MSP‡ ‡
Banked version of SP
Link Register LR (R14)
Program Counter PC (R15)
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[1] Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
[2] An entry of Either means privileged and unprivileged software can access the register.
On reset, the processor loads the MSP with the value from address 0x00000000.
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31 30 29 28 27 26 25 24 23 16 15 10 9 8 0
APSR N Z C V Q Reserved
31 30 29 28 27 26 25 24 23 16 15 10 9 8 0
Reserved
Access these registers individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example:
• read all of the registers using PSR with the MRS instruction
• write to the APSR using APSR with the MSR instruction.
The PSR combinations and attributes are:
See the instruction descriptions Section 34.2.10.6 “MRS” and Section 34.2.10.7 “MSR” for
more information about how to access the program status registers.
Application Program Status Register: The APSR contains the current state of the
condition flags from previous instruction executions. See the register summary in
Table 626 for its attributes. The bit assignments are:
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Interrupt Program Status Register: The IPSR contains the exception type number of
the current Interrupt Service Routine (ISR). See the register summary in Table 626 for
its attributes. The bit assignments are:
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Execution Program Status Register: The EPSR contains the Thumb state bit, and the
execution state bits for either the:
See the register summary in Table 626 for the EPSR attributes. The bit assignments are:
Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application
software are ignored. Fault handlers can examine EPSR value in the stacked PSR to
indicate the operation that is at fault. See Section 34.3.3.7
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If-Then block: The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions for the instructions
are either all the same, or some can be the inverse of others. See Section 34.2.9.3 “IT” for
more information.
To access the exception mask registers use the MSR and MRS instructions, or the CPS
instruction to change the value of PRIMASK or FAULTMASK. See Section 34.2.10.6
“MRS”, Section 34.2.10.7 “MSR”, and Section 34.2.10.2 “CPS” for more information.
Priority Mask Register: The PRIMASK register prevents activation of all exceptions with
configurable priority. See the register summary in Table 626 for its attributes. The bit
assignments are shown in Table 631.
Fault Mask Register: The FAULTMASK register prevents activation of all exceptions
except for Non-Maskable Interrupt (NMI). See the register summary in Table 626 for its
attributes. The bit assignments are shown in Table 632.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except
the NMI handler.
Base Priority Mask Register: The BASEPRI register defines the minimum priority for
exception processing. When BASEPRI is set to a nonzero value, it prevents the activation
of all exceptions with same or lower priority level as the BASEPRI value. See the register
summary in Table 626 for its attributes. The bit assignments are shown in Table 633.
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[1] This field is similar to the priority fields in the interrupt priority registers. The processor implements only
bits[7:M] of this field, bits[M-1:0] read as zero and ignore writes. The value of M depends on the specific
device. See Section 34.4.2.7 “Interrupt Priority Registers” for more information. Remember that higher
priority field values correspond to lower exception priorities.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active
stack pointer bit of the CONTROL register when in Handler mode. The exception entry
and return mechanisms update the CONTROL register.
In an OS environment, ARM recommends that threads running in Thread mode use the
process stack and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode
to the PSP, use the MSR instruction to set the Active stack pointer bit to 1, see
Section 34.2.10.7 “MSR”.
Remark: When changing the stack pointer, software must use an ISB instruction
immediately after the MSR instruction. This ensures that instructions after the ISB execute
using the new stack pointer. See Section 34.2.10.5 “ISB”
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The NVIC registers control interrupt handling. See Section 34.4.2 “Nested Vectored
Interrupt Controller” for more information.
CMSIS simplifies software development by enabling the reuse of template code and the
combination of CMSIS-compliant software components from various middleware vendors.
Software vendors can expand the CMSIS to include their peripheral definitions and
access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short
descriptions of the CMSIS functions that address the processor core and the core
peripherals.
Remark: This document uses the register short names defined by the CMSIS. In a few
cases these differ from the architectural short names that might be used in other
documents.
• Section 34.3.5.4
• Section 34.2.2 “Intrinsic functions”
• Section 34.4.2.1 “The CMSIS mapping of the Cortex-M3 NVIC registers”
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0xFFFFFFFF
Vendor-specific
511MB
memory
0xE0100000
Private peripheral 0xE00FFFFF
1.0MB
bus
0xE0000000
0xDFFFFFFF
0xA0000000
0x9FFFFFFF
0x42000000 0x60000000
0x5FFFFFFF
Peripheral 0.5GB
0x400FFFFF
1MB Bit band region
0x40000000 0x40000000
0x3FFFFFFF
0x23FFFFFF
SRAM 0.5GB
32MB Bit band alias
0x20000000
0x22000000 0x1FFFFFFF
Code 0.5GB
0x200FFFFF
1MB Bit band region
0x20000000 0x00000000
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides
atomic operations to bit data, see Section 34.3.2.5.
The processor reserves regions of the Private peripheral bus (PPB) address range for
core peripheral registers, see Section 34.4.1 “About the Cortex-M3 peripherals”.
• Normal: The processor can re-order transactions for efficiency, or perform speculative
reads.
• Device: The processor preserves transaction order relative to other transactions to
Device or Strongly-ordered memory.
• Strongly-ordered: The processor preserves transaction order relative to all other
transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that
the memory system can buffer a write to Device memory, but must not buffer a write to
Strongly-ordered memory.
• Shareable
For a shareable memory region, the memory system provides data synchronization
between bus masters in a system with multiple bus masters, for example, a processor
with a DMA controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, software must
ensure data coherency between the bus masters.
• Execute Never (XN)
Means the processor prevents instruction accesses. Any attempt to fetch an
instruction from an XN region causes a memory management fault exception.
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs
before A2 in program order, the ordering of the memory accesses caused by two
instructions is:
Normal access - - - -
Where:
‘—’ means that the memory system does not guarantee the ordering of the accesses.
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‘<‘ means that accesses are observed in program order, that is, A1 is always observed
before A2.
The Code, SRAM, and external RAM regions can hold programs. However, the most
efficient access to programs is from the Code region. This is because the processor has
separate buses that enable instruction fetches and data accesses to occur
simultaneously.
The MPU can override the default memory access behavior described in this section. For
more information, see Section 34.4.5 “Memory protection unit”.
• the processor can reorder some memory accesses to improve efficiency, providing
this does not affect the behavior of the instruction sequence.
• the processor has multiple bus interfaces
• memory or devices in the memory map have different wait states
• some memory accesses are buffered or speculative.
Section 34.3.2.2 describes the cases where the memory system guarantees the order of
memory accesses. Otherwise, if the order of memory accesses is critical, software must
include memory barrier instructions to force that ordering. The processor provides the
following memory barrier instructions:
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• DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory
transactions complete before subsequent memory transactions. See
Section 34.2.10.3 “DMB”.
• DSB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding
memory transactions complete before subsequent instructions execute. See
Section 34.2.10.4 “DSB”.
• ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all
completed memory transactions is recognizable by subsequent instructions. See
Section 34.2.10.5 “ISB”.
Memory accesses to Strongly-ordered memory, such as the system control block, do not
require the use of DMB instructions.
• MPU programming:
– Use a DSB instruction to ensure the effect of the MPU takes place immediately at
the end of context switching.
– Use an ISB instruction to ensure the new MPU setting takes effect immediately
after programming the MPU region or regions, if the MPU configuration code was
accessed using a branch or call. If the MPU configuration code is entered using
exception mechanisms, then an ISB instruction is not required.
• Vector table. If the program changes an entry in the vector table, and then enables the
corresponding exception, use a DMB instruction between the operations. This ensures
that if the exception is taken immediately after being enabled the processor uses the
new exception vector.
• Self-modifying code. If a program contains self-modifying code, use an ISB instruction
immediately after the code modification in the program. This ensures subsequent
instruction execution uses the updated program.
• Memory map switching. If the system contains a memory map switching mechanism,
use a DSB instruction after switching the memory map in the program. This ensures
subsequent instruction execution uses the updated memory map.
• Dynamic exception priority change. When an exception priority has to change when
the exception is pending or active, use DSB instructions after the change. This ensures
the change takes effect on completion of the DSB instruction.
• Using a semaphore in multi-master system. If the system contains more than one bus
master, for example, if another processor is present in the system, each processor
must use a DMB instruction after any semaphore instructions, to ensure other bus
masters see the memory transactions in the order in which they were executed.
34.3.2.5 Bit-banding
A bit-band region maps each word in a bit-band alias region to a single bit in the
bit-band region. The bit-band regions occupy the lowest 1MB of the SRAM and
peripheral memory regions.
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The memory map has two 32MB alias regions that map to two 1MB bit-band regions:
• accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as
shown in Table 636
• accesses to the 32MB peripheral alias region map to the 1MB peripheral bit-band
region, as shown in Table 637.
Remark: A word access to the SRAM or peripheral bit-band alias regions map to a single
bit in the SRAM or peripheral bit-band region.
The following formula shows how the alias region maps onto the bit-band region:
where:
• Bit_word_offset is the position of the target bit in the bit-band memory region.
• Bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit.
• Bit_band_base is the starting address of the alias region.
• Byte_offset is the number of the byte in the bit-band region that contains the targeted
bit.
• Bit_number is the bit position, 0-7, of the targeted bit.
Figure 146 shows examples of bit-band mapping between the SRAM bit-band alias region
and the SRAM bit-band region:
• The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF:
0x23FFFFE0 = 0x22000000 + (0xFFFFF*32) + (0*4).
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• The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF:
0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + (7*4).
• The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000:
0x22000000 = 0x22000000 + (0*32) + (0 *4).
• The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000:
0x2200001C = 0x22000000+ (0*32) + (7*4).
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Bit[0] of the value written to a word in the alias region determines the value written to the
targeted bit in the bit-band region. Writing a value with bit[0] set to 1 writes a 1 to the
bit-band bit, and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit.
Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same
effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
• 0x00000000 indicates that the targeted bit in the bit-band region is set to zero
• 0x00000001 indicates that the targeted bit in the bit-band region is set to 1
34.3.2.5.2 Directly accessing a bit-band region
Section 34.3.2.3 describes the behavior of direct byte, halfword, or word accesses to the
bit-band regions.
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Memory Register
7 0
31 24 23 16 15 8 7 0
Address A B0 lsbyte B3 B2 B1 B0
A+1 B1
A+2 B2
A+3 B3 msbyte
• A Load-Exclusive instruction
Used to read the value of a memory location, requesting exclusive access to that
location.
• A Store-Exclusive instruction
Used to attempt to write to the same memory location, returning a status bit to a
register. If this bit is:
– 0: it indicates that the thread or process gained exclusive access to the memory,
and the write succeeds,
– 1: it indicates that the thread or process did not gain exclusive access to the
memory, and no write is performed,
The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor
has executed a Load-Exclusive instruction.
The actual exclusive access instruction generated depends on the data type of the pointer
passed to the intrinsic function. For example, the following C code generates the require
LDREXB operation:
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• Inactive
The exception is not active and not pending.
• Pending
The exception is waiting to be serviced by the processor.
An interrupt request from a peripheral or from software can change the state of the
corresponding interrupt to pending.
• Active
An exception that is being serviced by the processor but has not completed.
Remark: An exception handler can interrupt the execution of another exception
handler. In this case both exceptions are in the active state.
• Active and pending
The exception is being serviced by the processor and there is a pending exception
from the same source.
• Reset
Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor
stops, potentially at any point in an instruction. When reset is deasserted, execution
restarts from the address provided by the reset entry in the vector table. Execution
restarts as privileged execution in Thread mode.
• NMI
A NonMaskable Interrupt (NMI) can be signalled by a peripheral or triggered by
software. This is the highest priority exception other than reset. It is permanently
enabled and has a fixed priority of -2. NMIs cannot be:
– masked or prevented from activation by any other exception
– preempted by any exception other than Reset.
• Hard fault
A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception
mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority
than any exception with configurable priority.
• Memory management fault
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[1] To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than
interrupts. The IPSR returns the Exception number, see Table 629.
[2] See Section 34.3.3.4 for more information.
[3] See Section 34.4.3.9 “System Handler Priority Registers”.
[4] See Section 34.4.2.7 “Interrupt Priority Registers”.
[5] Increasing in steps of 4.
For an asynchronous exception, other than reset, the processor can execute another
instruction between when the exception is triggered and when the processor enters the
exception handler.
Privileged software can disable the exceptions that Table 639 shows as having
configurable priority, see:
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Exception IRQ
number number Offset Vector
127 111 0x1FC IRQ111
. . .
. . .
. . .
18 0x004C IRQ2
17 2 0x0048 IRQ1
16 1 0x0044 IRQ0
15 0 0x0040 Systick
14 -1 0x003C PendSV
13 -2 0x0038 Reserved
12 Reserved for debug
11 SVCall
10 -5 0x002C
9
Reserved
8
7
6 -10 0x0018 Usage fault
5 -11 0x0014 Bus fault
4 -12 0x0010 Memory management fault
3 -13 0x000C Hard fault
2 -14 0x0008 NMI
1 0x0004 Reset
0x0000 Initial SP value.
On system reset, the vector table is fixed at address 0x00000000. Privileged software can
write to the VTOR to relocate the vector table start address to a different memory location,
in the range 0x00000080 to 0x3FFFFF80, see Section 34.4.3.5 “Vector Table Offset Register”.
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For example, assigning a higher priority value to IRQ[0] and a lower priority value to
IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are
asserted, IRQ[1] is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the
lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are
pending and have the same priority, then IRQ[0] is processed before IRQ[1].
Only the group priority determines preemption of interrupt exceptions. When the
processor is executing an interrupt exception handler, another interrupt with the same
group priority as the interrupt being handled does not preempt the handler,
For information about splitting the interrupt priority fields into group priority and subpriority,
see Section 34.4.3.6 “Application Interrupt and Reset Control Register”.
• Preemption
When the processor is executing an exception handler, an exception can preempt the
exception handler if its priority is higher than the priority of the exception being
handled. See Section 34.3.3.6 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions.
See Section 34.3.3.7.1 more information.
• Return
This occurs when the exception handler is completed, and:
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Sufficient priority means the exception has more priority than any limits set by the mask
registers, see Section 34.3.1.3.6. An exception with less priority than this is pending but is
not handled by the processor.
• R0-R3, R12
• Return address
• PSR
• LR.
Immediately after stacking, the stack pointer indicates the lowest address in the stack
frame. Unless stack alignment is disabled, the stack frame is aligned to a double-word
address. If the STKALIGN bit of the Configuration Control Register (CCR) is set to 1,
stack align adjustment is performed during stacking.
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The stack frame includes the return address. This is the address of the next instruction in
the interrupted program. This value is restored to the PC at exception return so that the
interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the
exception handler start address from the vector table. When stacking is complete, the
processor starts executing the exception handler. At the same time, the processor writes
an EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the
stack frame and what operation mode the was processor was in before the entry
occurred.
If no higher priority exception occurs during exception entry, the processor starts
executing the exception handler and automatically changes the status of the
corresponding pending interrupt to active.
If another higher priority exception occurs during exception entry, the processor starts
executing the exception handler for this exception and does not change the pending
status of the earlier exception. This is the late arrival case.
The processor sets EXC_RETURN bits[31:4] to 0xFFFFFFF. When this value is loaded into
the PC it indicates to the processor that the exception is complete, and the processor
initiates the exception return sequence.
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Usually, the exception priority, together with the values of the exception mask registers,
determines whether the processor enters the fault handler, and whether a fault handler
can preempt another fault handler. as described in Section 34.3.3.
In some situations, a fault with configurable priority is treated as a hard fault. This is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to
hard fault occurs when:
• A fault handler causes the same kind of fault as the one it is servicing. This escalation
to hard fault occurs because a fault handler cannot preempt itself because it must
have the same priority as the current priority level.
• A fault handler causes a fault with the same or lower priority as the fault it is servicing.
This is because the handler for the new fault cannot preempt the currently executing
fault handler.
• An exception handler causes a fault for which the priority is the same as or lower than
the currently executing exception.
• A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault
does not escalate to a hard fault. This means that if a corrupted stack causes a fault, the
fault handler executes even though the stack push for the handler failed. The fault handler
operates but the stack contents are corrupted.
Remark: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can
preempt any exception other than Reset, NMI, or another hard fault.
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34.3.4.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard
fault handlers. When the processor is in lockup state it does not execute any instructions.
The processor remains in lockup state until either:
• it is reset
• an NMI occurs.
Remark: If lockup state occurs from the NMI handler a subsequent NMI does not cause
the processor to leave lockup state.
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This section describes the mechanisms for entering sleep mode, and the conditions for
waking up from sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes
up the processor. Therefore software must be able to put the processor back into sleep
mode after such an event. A program might have an idle loop to put the processor back to
sleep mode.
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of
an one-bit event register. When the processor executes a WFE instruction, it checks this
register:
• if the register is 0 the processor stops executing instructions and enters sleep mode
• if the register is 1 the processor clears the register to 0 and continues executing
instructions without entering sleep mode.
If the event register is 1, this indicate that the processor must not enter sleep mode on
execution of a WFE instruction. Typically, this is because an external event signal is
asserted, or a processor in the system has executed an SEV instruction, see
Section 34.2.10.9 “SEV”. Software cannot access this register directly.
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34.3.5.1.3 Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the
execution of an exception handler it returns to Thread mode and immediately enters sleep
mode. Use this mechanism in applications that only require the processor to run when an
exception occurs.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK
bit to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a
higher priority than current exception priority, the processor wakes up but does not
execute the interrupt handler until the processor sets PRIMASK to zero. For more
information about PRIMASK and FAULTMASK see Section 34.3.1.3.6.
Details of wake-up possibilities on the LPC17xx can be found in Section 4.8 “Power
control”.
The WIC is not programmable, and does not have any registers or user interface. It
operates entirely from hardware signals.
When the WIC is enabled and the processor enters deep sleep mode or Power-down
mode, the power management unit in the system can power down most of the Cortex-M3
processor. This has the side effect of stopping the SysTick timer. When the WIC receives
an interrupt, it takes a number of clock cycles to wakeup the processor and restore its
state, before it can process the interrupt. This means interrupt latency is increased in deep
sleep mode. Wake-up from Power-down mode requires startup of many other portions of
the device, and takes longer. Wake-up from Deep Power-down mode adds time to
re-establish the on-chip regulator voltage as well.
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In register descriptions:
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The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
[1] Each array element corresponds to a single NVIC register, for example the element ICER[1] corresponds to the ICER1 register.
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The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority
Registers. For more information see the description of the NVIC_SetPriority function in
Section 34.4.2.10.1 “NVIC programming hints”. Table 645 shows how the interrupts, or
IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that
have one bit per interrupt.
[1] Each array element corresponds to a single NVIC register, for example the element ICER[1] corresponds to the ICER1 register.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to
pending, but the NVIC never activates the interrupt, regardless of its priority.
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Remark: Writing 1 to an ICPR bit does not affect the active state of the corresponding
interrupt.
A bit reads as one if the status of the corresponding interrupt is active or active and
pending.
31 24 23 16 15 8 7 0
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See Table 645 for more information about the IP[0] to IP[111] interrupt priority array, that
provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt N as follows:
When the USERSETMPEND bit in the CCR is set to 1, unprivileged software can access
the STIR, see Section 34.4.3.8 “Configuration and Control Register”.
Remark: Only privileged software can enable unprivileged access to the STIR.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt
signal. Typically this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the
rising edge of the processor clock. To ensure the NVIC detects the interrupt, the
peripheral must assert the interrupt signal for at least one clock cycle, during which the
NVIC detects the pulse and latches the interrupt.
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When the processor enters the ISR, it automatically removes the pending state from the
interrupt, see Section 34.4.2.9.1. For a level-sensitive interrupt, if the signal is not
deasserted before the processor returns from the ISR, the interrupt becomes pending
again, and the processor must execute its ISR again. This means that the peripheral can
hold the interrupt signal asserted until it no longer needs servicing.
• the NVIC detects that the interrupt signal is HIGH and the interrupt is not active
• the NVIC detects a rising edge on the interrupt signal
• software writes to the corresponding interrupt set-pending register bit, see Table 648,
or to the STIR to make an SGI pending, see Table 652.
• The processor enters the ISR for the interrupt. This changes the state of the interrupt
from pending to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this
is pulsed the state of the interrupt changes to pending and active. In this case,
when the processor returns from the ISR the state of the interrupt changes to
pending, which might cause the processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the
processor returns from the ISR the state of the interrupt changes to inactive.
• Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the
interrupt does not change. Otherwise, the state of the interrupt changes to inactive.
For a pulse interrupt, state of the interrupt changes to:
– inactive, if the state was pending
– active, if the state was active and pending.
Before programming VTOR to relocate the vector table, ensure the vector table entries of
the new vector table are setup for fault handlers, NMI and all enabled exception like
interrupts. For more information see Table 658.
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In addition, the CMSIS provides a number of functions for NVIC control, including:
For more information about these functions see the CMSIS documentation.
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• IT folding
• write buffer use for accesses to the default memory map
• interruption of multi-cycle instructions.
See the register summary in Table 654 for the ACTLR attributes. The bit assignments are
shown in Table 655.
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• provides:
– a set-pending bit for the Non-Maskable Interrupt (NMI) exception
– set-pending and clear-pending bits for the PendSV and SysTick exceptions
• indicates:
– the exception number of the exception being processed
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See the register summary in Table 654, and the Type descriptions in Table 657, for the
ICSR attributes. The bit assignments are shown in Table 657.
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[1] This is the same value as IPSR bits[8:0], see Table 629 “IPSR bit assignments”.
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[31:30] - Reserved.
[29:8] TBLOFF Vector table base offset field. It contains bits[29:8] of the offset of the table
base from the bottom of the memory map.
Remark: Bit[29] determines whether the vector table is in the code or
SRAM memory region:
Bit[29] is sometimes called the TBLBASE bit.
• 0 = code
• 1 = SRAM.
[7:0] - Reserved.
When setting TBLOFF, you must align the offset to the number of exception entries in the
vector table. The recommended alignment is 256 words, allowing for 128 interrupts.
Remark: Table alignment requirements mean that bits[7:0] of the table offset are always
zero.
To write to this register, you must write 0x5VA to the VECTKEY field, otherwise the
processor ignores the write.
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[1] PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit. Bits [2:0] are not used
in LPC17xx devices.
Remark: Determining preemption of an exception uses only the group priority field, see
Section 34.3.3.6 “Interrupt priority grouping”.
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• the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore bus
faults
• trapping of divide by zero and unaligned accesses
• access to the STIR by unprivileged software, see Table 652.
See the register summary in Table 654 for the CCR attributes.
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SHPR1-SHPR3 are byte accessible. See the register summary in Table 654 for their
attributes.
The system fault handlers and the priority field and register for each handler are:
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Each PRI_N field is 8 bits wide, but the processor implements only bits[7:3] of each field,
and bits[2:0] read as zero and ignore writes.
• the pending status of the bus fault, memory management fault, and SVC exceptions
• the active status of the system handlers.
See the register summary in Table 654 for the SHCSR attributes. The bit assignments are
shown in Table 667.
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[1] Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception.
[2] Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to
change the pending status of the exceptions.
[3] Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change
the active status of the exceptions, but see the Caution in this section.
If you disable a system handler and the corresponding fault occurs, the processor treats
the fault as a hard fault.
You can write to this register to change the pending or active status of system exceptions.
An OS kernel can write to the active bits to perform a context switch that changes the
current exception type.
Caution
• Software that changes the value of an active bit in this register without correct
adjustment to the stacked content can cause the processor to generate a fault
exception. Ensure software that writes to this register retains and subsequently
restores the current active status.
• After you have enabled the system handlers, if you have to change the value of a bit
in this register you must use a read-modify-write procedure to ensure that you change
only the required bit.
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31 16 15 8 7 0
Bus Fault Status Memory Management
Usage Fault Status Register
Register Fault Status Register
The following subsections describe the subregisters that make up the CFSR:
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Remark: The UFSR bits are sticky. This means as one or more fault occurs, the
associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit,
or by a reset.
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This register is read, write to clear. This means that bits in the register read normally, but
writing 1 to any bit clears that bit to 0. The bit assignments are shown in Table 671.
Remark: The HFSR bits are sticky. This means as one or more fault occurs, the
associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit,
or by a reset.
When an unaligned access faults, the address is the actual address that faulted. Because
a single read or write instruction can be split into multiple aligned accesses, the fault
address can be any address in the range of the requested access size.
Flags in the MMFSR indicate the cause of the fault, and whether the value in the MMFAR
is valid. See Table 668.
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When an unaligned access faults the address in the BFAR is the one requested by the
instruction, even if it is not the address of the fault.
Flags in the BFSR indicate the cause of the fault, and whether the value in the BFAR is
valid. See Table 669.
• except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses
• for the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word
accesses.
The processor does not support unaligned accesses to system control block registers.
Software must follow this sequence because another higher priority exception might
change the MMFAR or BFAR value. For example, if a higher priority handler preempts the
current fault handler, the other fault might change the MMFAR or BFAR value.
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Note: refer to the separate chapter in the LPC17xx User Manual Section 23.1 for
device specific information on the System Timer.
Remark: when the processor is halted for debugging the counter does not decrement.
When ENABLE is set to 1, the counter loads the RELOAD value from the LOAD register
and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts
the SysTick depending on the value of TICKINT. It then loads the RELOAD value again,
and begins counting.
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If a different frequency is used than that intended by the factory preset value, calculate the
calibration value required from the frequency of the processor clock or external clock.
Ensure software uses aligned word accesses to access the SysTick registers.
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The MPU divides the memory map into a number of regions, and defines the location,
size, access permissions, and memory attributes of each region. It supports:
The background region has the same memory access attributes as the default memory
map, but is accessible from privileged software only.
The Cortex-M3 MPU memory map is unified. This means instruction accesses and data
accesses have same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor
generates a memory management fault. This causes a fault exception, and might cause
termination of the process in an OS environment.
In an OS environment, the kernel can update the MPU region setting dynamically based
on the process to be executed. Typically, an embedded OS uses the MPU for memory
protection.
Configuration of MPU regions is based on memory types, see Section 34.3.2.1 “Memory
regions, types and attributes”.
Table 679 shows the possible MPU region attributes. These include Shareability and
cache behavior attributes that are not relevant to most microcontroller implementations.
See Table 690 for guidelines for programming such an implementation.
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Use the MPU registers to define the MPU regions and their attributes. The MPU registers
are:
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See the register summary in Table 680 for the MPU CTRL attributes. The bit assignments
are shown in Table 682.
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• For privileged accesses, the default memory map is as described in Section 34.3.2
“Memory model”. Any access by privileged software that does not address an enabled
memory region behaves as defined by the default memory map.
• Any access by unprivileged software that does not address an enabled memory
region causes a memory management fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of
the value of the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled
for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit
is set to 1 and no regions are enabled, then only privileged software can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the
same memory attributes as if the MPU is not implemented, see Table 635 “Memory
access behavior”. The default memory map applies to accesses from both privileged and
unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are
always permitted. Other areas are accessible based on regions and whether
PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing
the handler for an exception with priority –1 or –2. These priorities are only possible when
handling a hard fault or NMI exception, or when FAULTMASK is enabled. Setting the
HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
Normally, you write the required region number to this register before accessing the
RBAR or RASR. However you can change the region number by writing to the RBAR with
the VALID bit set to 1, see Table 684. This write updates the value of the REGION field.
Write RBAR with the VALID bit set to 1 to change the current region number and update
the RNR. The bit assignments are shown in Table 684.
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[31:N] ADDR Region base address field. The value of N depends on the region size. For
more information see Section 34.4.5.4.1.
[(N-1):5] - Reserved.
[4] VALID MPU Region Number valid bit:
Write:
0 = RNR not changed, and the processor:
• updates the base address for the region specified in the RNR
• ignores the value of the REGION field
1 = the processor:
• updates the value of the RNR to the value of the REGION field
• updates the base address for the region specified in the REGION field.
Always reads as zero.
[3:0] REGION MPU region field:
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the RNR.
If the region size is configured to 4GB, in the RASR, there is no valid ADDR field. In this
case, the region occupies the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64KB region must
be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000.
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The smallest permitted region size is 32B, corresponding to a SIZE value of 4. Table 686
gives example SIZE values, with the corresponding region size and value of N in the
RBAR.
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Table 687 shows the encodings for the TEX, C, B, and S access permission bits.
Table 688 shows the cache policy for memory attribute encodings with a TEX value is in
the range 4-7.
Table 689 shows the AP encodings that define the access permissions for privileged and
unprivileged software.
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; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
Disable a region before writing new region settings to the MPU if you have previously
enabled the region being changed. For example:
; R1 = region number
; R2 = size/enable
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; R3 = attributes
; R4 = address
• before MPU setup if there might be outstanding memory transfers, such as buffered
writes, that might be affected by the change in MPU settings
• after MPU setup if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by
entering an exception handler, or is followed by an exception return, because the
exception entry and exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it
accesses the MPU through the PPB, which is a Strongly-Ordered memory region.
For example, if you want all of the memory access behavior to take effect immediately
after the programming sequence, use a DSB instruction and an ISB instruction. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is
required if the code that programs the MPU region or regions is entered using a branch or
call. If the programming sequence is entered using a return from exception, or by taking
an exception, then you do not require an ISB.
; R1 = region number
; R2 = address
; R1 = region number
; R2 = address
STM R0, {R1-R3} ; Region Number, address, attribute, size and enable
You can do this in two words for pre-packed information. This means that the RBAR
contains the required region number and had the VALID bit set to 1, see Table 684. Use
this when the data is statically packed, for example in a boot loader:
STM R0, {R1-R2} ; Region base address, region number and VALID bit,
34.4.5.8.3 Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the
corresponding bit in the SRD field of the RASR to disable a subregion, see Table 685. The
least significant bit of SRD controls the first subregion, and the most significant bit controls
the last subregion. Disabling a subregion means another region overlapping the disabled
range matches instead. If no other enabled region overlaps the disabled subregion the
MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions, With regions of these sizes,
you must set the SRD field to 0x00, otherwise the MPU behavior is Unpredictable.
Example of SRD use: Two regions with the same base address overlap. Region one is
128KB, and region two is 512KB. To ensure the attributes from region one apply to the
first128KB region, set the SRD field for region two to b00000011 to disable the first two
subregions, as the figure shows.
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Ensure software uses aligned accesses of the correct size to access MPU registers:
When setting up the MPU, and if the MPU has previously been programmed, disable
unused regions to prevent any previous region settings from affecting the new MPU
setup.
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Aligned — A data item stored at an address that is divisible by the number of bytes that
defines the data size is said to be aligned. Aligned words and halfwords have addresses
that are divisible by four and two respectively. The terms word-aligned and
halfword-aligned therefore stipulate addresses that are divisible by four and two
respectively.
Banked register — A register that has multiple physical copies, where the state of the
processor determines which copy is used. The Stack Pointer, SP (R13) is a banked
register.
Cache — A block of on-chip or off-chip fast access memory locations, situated between
the processor and main memory, used for storing and retrieving copies of often used
instructions, data, or instructions and data. This is done to greatly increase the average
speed of memory accesses and so improve processor performance.
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Condition field — A four-bit field in an instruction that specifies a condition under which
the instruction can execute.
Context — The environment that each process operates in for a multitasking operating
system. In ARM processors, this is limited to mean the physical address range that it can
access in memory and the associated memory access permissions.
Coprocessor — A processor that supplements the main processor. Cortex-M3 does not
support any coprocessors.
Debugger — A debugging system that includes a program, used to detect, locate, and
correct software faults, together with custom hardware that supports software debugging.
Direct Memory Access (DMA) — An operation that accesses main memory directly,
without the processor performing any accesses to the data concerned.
Doubleword — A 64-bit data item. The contents are taken as being an unsigned integer
unless otherwise stated.
Endianness — Byte ordering. The scheme that determines the order that successive
bytes of a data word are stored in memory. An aspect of the system’s memory mapping.
See also Little-endian and Big-endian.
Exception — An event that interrupts program execution. When an exception occurs, the
processor suspends the normal program flow and starts execution at the address
indicated by the corresponding exception vector. The indicated address contains the first
instruction of the handler for the exception.
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Index register — In some load and store instruction descriptions, the value of this
register is used as an offset to be added to or subtracted from the base register value to
form the address that is sent to memory. Some addressing modes optionally enable the
index register value to be shifted prior to the addition or subtraction. See also Base
register.
Instruction cycle count — The number of cycles that an instruction occupies the
Execute stage of the pipeline.
Memory Protection Unit (MPU) — Hardware that controls access permissions to blocks
of memory. An MPU does not perform any address translation.
Read — Reads are defined as memory operations that have the semantics of a load.
Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Should Be One (SBO) — Write as 1, or all 1s for bit fields, by software. Writing as 0
produces Unpredictable results.
Should Be Zero (SBZ) — Write as 0, or all 0s for bit fields, by software. Writing as 1
produces Unpredictable results.
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Should Be Zero or Preserved (SBZP) — Write as 0, or all 0s for bit fields, by software,
or preserved by writing the same value back that has been previously read from the same
field on the same processor.
Thumb instruction — One or two halfwords that specify an operation for a processor to
perform. Thumb instructions must be halfword-aligned.
Unaligned — A data item stored at an address that is not divisible by the number of bytes
that defines the data size is said to be unaligned. For example, a word stored at an
address that is not divisible by four.
Unpredictable (UNP) — You cannot rely on the behavior. Unpredictable behavior must
not represent security holes. Unpredictable behavior must not halt or hang the processor,
or any parts of the system.
Warm reset — Also known as a core reset. Initializes the majority of the processor
excluding the debug controller and debug logic. This type of reset is useful if you are using
the debugging features of a processor.
WA — See Write-allocate.
WB — See Write-back.
Write — Writes are defined as operations that have the semantics of a store. Writes
include the Thumb instructions STM, STR, STRH, STRB, and PUSH.
Write-back (WB) — In a write-back cache, data is only written to main memory when it is
forced out of the cache on line replacement following a cache miss. Otherwise, writes by
the processor only update the cache. This is also known as copyback.
Write buffer — A block of high-speed memory, arranged as a FIFO buffer, between the
data cache and main memory, whose purpose is to optimize stores to main memory.
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35.1 Abbreviations
Table 691. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
BOD BrownOut Detection
CAN Controller Area Network
DAC Digital-to-Analog Converter
DCC Debug Communication Channel
DMA Direct Memory Access
DSP Digital Signal Processing
EOP End Of Packet
ETM Embedded Trace Macrocell
GPIO General Purpose Input/Output
IrDA Infrared Data Association
JTAG Joint Test Action Group
MIIM Media Independent Interface Management
PHY Physical Layer
PLL Phase-Locked Loop
PWM Pulse Width Modulator
RMII Reduced Media Independent Interface
SE0 Single Ended Zero
SPI Serial Peripheral Interface
SSI Serial Synchronous Interface
SSP Synchronous Serial Port
TTL Transistor-Transistor Logic
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
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35.3 Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .7 Table 36. PLL1 Divider values . . . . . . . . . . . . . . . . . . . . 53
Table 2. Ordering options for LPC17xx parts . . . . . . . . . .7 Table 37. PLL1 Multiplier values . . . . . . . . . . . . . . . . . . . 53
Table 3. LPC17xx memory usage and details . . . . . . . .12 Table 38. CPU Clock Configuration register (CCLKCFG -
Table 4. APB0 peripherals and base addresses . . . . . .14 address 0x400F C104) bit description . . . . . . . 55
Table 5. APB1 peripherals and base addresses . . . . . .15 Table 39. USB Clock Configuration register (USBCLKCFG -
Table 6. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .17 address 0x400F C108) bit description . . . . . . . 56
Table 7. Summary of system control registers . . . . . . . .18 Table 40. Peripheral Clock Selection register 0 (PCLKSEL0
Table 8. Reset Source Identification register (RSID - - address 0x400F C1A8) bit description. . . . . . 56
address 0x400F C180) bit description . . . . . . .21 Table 41. Peripheral Clock Selection register 1 (PCLKSEL1
Table 9. External Interrupt registers . . . . . . . . . . . . . . . .24 - address 0x400F C1AC) bit description . . . . . 57
Table 10. External Interrupt Flag register (EXTINT - address Table 42. Peripheral Clock Selection register bit values . 57
0x400F C140) bit description . . . . . . . . . . . . . .25 Table 43. Power Control registers . . . . . . . . . . . . . . . . . . 60
Table 11. External Interrupt Mode register (EXTMODE - Table 44. Power Mode Control register (PCON - address
address 0x400F C148) bit description . . . . . . .26 0x400F C0C0) bit description . . . . . . . . . . . . . 61
Table 12. External Interrupt Polarity register (EXTPOLAR - Table 45. Encoding of reduced power modes . . . . . . . . . 62
address 0x400F C14C) bit description . . . . . . .26 Table 46. Power Control for Peripherals register (PCONP -
Table 13. System Controls and Status register (SCS - address 0x400F C0C4) bit description. . . . . . . 63
address 0x400F C1A0) bit description . . . . . . .28 Table 47. Clock Output Configuration register
Table 14. Summary of system control registers . . . . . . . .30 (CLKOUTCFG - 0x400F C1C8) bit description 66
Table 15. Recommended values for CX1/X2 in oscillation Table 48. Summary of flash accelerator registers . . . . . . 69
mode (crystal and external components Table 49. Flash Accelerator Configuration register
parameters) low frequency mode (OSCRANGE = (FLASHCFG - address 0x400F C000) bit
0, see Table 13) . . . . . . . . . . . . . . . . . . . . . . . .32 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 16. Recommended values for CX1/X2 in oscillation Table 50. Connection of interrupt sources to the Vectored
mode (crystal and external components Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . 73
parameters) high frequency mode (OSCRANGE = Table 51. NVIC register map . . . . . . . . . . . . . . . . . . . . . 76
1, see Table 13) . . . . . . . . . . . . . . . . . . . . . . . .32 Table 52. Interrupt Set-Enable Register 0 register (ISER0 -
Table 17. Clock Source Select register (CLKSRCSEL - 0xE000 E100) . . . . . . . . . . . . . . . . . . . . . . . . . 77
address 0x400F C10C) bit description . . . . . . .34 Table 53. Interrupt Set-Enable Register 1 register (ISER1 -
Table 18. PLL0 registers . . . . . . . . . . . . . . . . . . . . . . . . .36 0xE000 E104) . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 19. PLL Control register (PLL0CON - address Table 54. Interrupt Clear-Enable Register 0 (ICER0 -
0x400F C080) bit description . . . . . . . . . . . . . .37 0xE000 E180) . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 20. PLL0 Configuration register (PLL0CFG - address Table 55. Interrupt Clear-Enable Register 1 register (ICER1
0x400F C084) bit description . . . . . . . . . . . . . .37 - 0xE000 E184) . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 21. Multiplier values for PLL0 with a 32 kHz input .38 Table 56. Interrupt Set-Pending Register 0 register (ISPR0 -
Table 22. PLL Status register (PLL0STAT - address 0xE000 E200) . . . . . . . . . . . . . . . . . . . . . . . . . 81
0x400F C088) bit description . . . . . . . . . . . . . .39 Table 57. Interrupt Set-Pending Register 1 register (ISPR1 -
Table 23. PLL control bit combinations . . . . . . . . . . . . . .40 0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 24. PLL Feed register (PLL0FEED - address Table 58. Interrupt Clear-Pending Register 0 register
0x400F C08C) bit description . . . . . . . . . . . . . .40 (ICPR0 - 0xE000 E280) . . . . . . . . . . . . . . . . . 83
Table 25. PLL frequency parameter . . . . . . . . . . . . . . . . .41 Table 59. Interrupt Set-Pending Register 1 register (ISPR1 -
Table 26. Additional Multiplier Values for use with a Low 0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . . 84
Frequency Clock Input . . . . . . . . . . . . . . . . . . .42 Table 60. Interrupt Active Bit Register 0 (IABR0 - 0xE000
Table 27. Summary of PLL0 examples . . . . . . . . . . . . . .43 E300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 28. Potential values for PLL example . . . . . . . . . . .45 Table 61. Interrupt Active Bit Register 1 (IABR1 - 0xE000
Table 29. PLL1 registers . . . . . . . . . . . . . . . . . . . . . . . . .47 E304) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 30. PLL1 Control register (PLL1CON - address Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000
0x400F C0A0) bit description . . . . . . . . . . . . . .49 E400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 31. PLL Configuration register (PLL1CFG - address Table 63. Interrupt Priority Register 1 (IPR1 - 0xE000
0x400F C0A4) bit description . . . . . . . . . . . . . .49 E404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 32. PLL1 Status register (PLL1STAT - address Table 64. Interrupt Priority Register 2 (IPR2 - 0xE000
0x400F C0A8) bit description . . . . . . . . . . . . . .50 E408) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 33. PLL1 control bit combinations . . . . . . . . . . . . .50 Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000
Table 34. PLL1 Feed register (PLL1FEED - address E40C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
0x400F C0AC) bit description. . . . . . . . . . . . . .51 Table 66. Interrupt Priority Register 4 (IPR4 - 0xE000
Table 35. Elements determining PLL frequency. . . . . . . .52 E410) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr description . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
- 0x4002 808C)) bit description . . . . . . . . . . .138 Table 153. Receive Produce Index register
Table 123. GPIO Interrupt Clear register for port 0 (IO2IntClr (RxProduceIndex - address 0x5000 0114) bit
- 0x4002 80AC) bit description . . . . . . . . . . . .139 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 124. Ethernet acronyms, abbreviations, and Table 154. Receive Consume Index register
definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 (RxConsumeIndex - address 0x5000 0118) bit
Table 125. Example PHY Devices. . . . . . . . . . . . . . . . . .147 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 126. Ethernet RMII pin descriptions. . . . . . . . . . . .147 Table 155. Transmit Descriptor Base Address register
Table 127. Ethernet MIIM pin descriptions . . . . . . . . . . .147 (TxDescriptor - address 0x5000 011C) bit
Table 128. Ethernet register definitions . . . . . . . . . . . . . .148 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 129. MAC Configuration register 1 (MAC1 - address Table 156. Transmit Status Base Address register (TxStatus
0x5000 0000) bit description . . . . . . . . . . . . .150 - address 0x5000 0120) bit description . . . . . 161
Table 130. MAC Configuration register 2 (MAC2 - address Table 157. Transmit Number of Descriptors register
0x5000 0004) bit description . . . . . . . . . . . . .151 (TxDescriptorNumber - address 0x5000 0124) bit
Table 131. Pad operation . . . . . . . . . . . . . . . . . . . . . . . .152 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 132. Back-to-back Inter-packet-gap register (IPGT - Table 158. Transmit Produce Index register
address 0x5000 0008) bit description. . . . . . .152 (TxProduceIndex - address 0x5000 0128) bit
Table 133. Non Back-to-back Inter-packet-gap register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
(IPGR - address 0x5000 000C) bit Table 159. Transmit Consume Index register
description . . . . . . . . . . . . . . . . . . . . . . . . . . .152 (TxConsumeIndex - address 0x5000 012C) bit
Table 134. Collision Window / Retry register (CLRT - address description . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
0x5000 0010) bit description . . . . . . . . . . . . .153 Table 160. Transmit Status Vector 0 register (TSV0 -
Table 135. Maximum Frame register (MAXF - address address 0x5000 0158) bit description . . . . . . 163
0x5000 0014) bit description . . . . . . . . . . . . .153 Table 161. Transmit Status Vector 1 register (TSV1 - address
Table 136. PHY Support register (SUPP - address 0x5000 015C) bit description . . . . . . . . . . . . . 164
0x5000 0018) bit description . . . . . . . . . . . . .153 Table 162. Receive Status Vector register (RSV - address
Table 137. Test register (TEST - address 0x5000 ) bit 0x5000 0160) bit description . . . . . . . . . . . . . 164
description . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Table 163. Flow Control Counter register
Table 138. MII Mgmt Configuration register (MCFG - address (FlowControlCounter - address 0x5000 0170) bit
0x5000 0020) bit description . . . . . . . . . . . . .154 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 139. Clock select encoding . . . . . . . . . . . . . . . . . .154 Table 164. Flow Control Status register (FlowControlStatus -
Table 140. MII Mgmt Command register (MCMD - address address 0x5000 0174) bit description . . . . . . 165
0x5000 0024) bit description . . . . . . . . . . . . .155 Table 165. Receive Filter Control register (RxFilterCtrl -
Table 141. MII Mgmt Address register (MADR - address address 0x5000 0200) bit description . . . . . . 166
0x5000 0028) bit description . . . . . . . . . . . . .155 Table 166. Receive Filter WoL Status register
Table 142. MII Mgmt Write Data register (MWTD - address (RxFilterWoLStatus - address 0x5000 0204) bit
0x5000 002C) bit description . . . . . . . . . . . . .156 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 143. MII Mgmt Read Data register (MRDD - address Table 167. Receive Filter WoL Clear register
0x5000 0030) bit description . . . . . . . . . . . . .156 (RxFilterWoLClear - address 0x5000 0208) bit
Table 144. MII Mgmt Indicators register (MIND - address description . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
0x5000 0034) bit description . . . . . . . . . . . . .156 Table 168. Hash Filter Table LSBs register (HashFilterL -
Table 145. Station Address register (SA0 - address address 0x5000 0210) bit description . . . . . . 167
0x5000 0040) bit description . . . . . . . . . . . . .157 Table 169. Hash Filter MSBs register (HashFilterH - address
Table 146. Station Address register (SA1 - address 0x5000 0214) bit description . . . . . . . . . . . . . 168
0x5000 0044) bit description . . . . . . . . . . . . .157 Table 170. Interrupt Status register (IntStatus - address
Table 147. Station Address register (SA2 - address 0x5000 0FE0) bit description . . . . . . . . . . . . . 168
0x5000 0048) bit description . . . . . . . . . . . . .157 Table 171. Interrupt Enable register (intEnable - address
Table 148. Command register (Command - address 0x5000 0FE4) bit description . . . . . . . . . . . . . 169
0x5000 0100) bit description . . . . . . . . . . . . .158 Table 172. Interrupt Clear register (IntClear - address
Table 149. Status register (Status - address 0x5000 0104) bit 0x5000 0FE8) bit description . . . . . . . . . . . . . 170
description . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Table 173. Interrupt Set register (IntSet - address
Table 150. Receive Descriptor Base Address register 0x5000 0FEC) bit description. . . . . . . . . . . . . 170
(RxDescriptor - address 0x5000 0108) bit Table 174. Power-Down register (PowerDown - address
description . . . . . . . . . . . . . . . . . . . . . . . . . . .159 0x5000 0FF4) bit description . . . . . . . . . . . . . 171
Table 151. receive Status Base Address register (RxStatus - Table 175. Receive Descriptor Fields . . . . . . . . . . . . . . . 173
address 0x5000 010C) bit description . . . . . .159 Table 176. Receive Descriptor Control Word . . . . . . . . . 173
Table 152. Receive Number of Descriptors register Table 177. Receive Status Fields . . . . . . . . . . . . . . . . . . 173
(RxDescriptor - address 0x5000 0110) bit Table 178. Receive Status HashCRC Word . . . . . . . . . . 174
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Table 179. Receive status information word . . . . . . . . . .174 (USBEpIntClr - address 0x5000 C238) bit
Table 180. Transmit descriptor fields. . . . . . . . . . . . . . . .176 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 181. Transmit descriptor control word . . . . . . . . . .176 Table 207. USB Endpoint Interrupt Set register
Table 182. Transmit status fields . . . . . . . . . . . . . . . . . . .176 (USBEpIntSet - address 0x5000 C23C) bit
Table 183. Transmit status information word . . . . . . . . . .177 allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 184. USB related acronyms, abbreviations, and Table 208. USB Endpoint Interrupt Set register
definitions used in this chapter . . . . . . . . . . . .214 (USBEpIntSet - address 0x5000 C23C) bit
Table 185. Fixed endpoint configuration . . . . . . . . . . . . .215 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 186. USB external interface . . . . . . . . . . . . . . . . . .218 Table 209. USB Endpoint Interrupt Priority register
Table 187. USB device controller clock sources . . . . . . .219 (USBEpIntPri - address 0x5000 C240) bit
Table 188. USB device register map . . . . . . . . . . . . . . . .220 allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 189. USBClkCtrl register (USBClkCtrl - address Table 210. USB Endpoint Interrupt Priority register
0x5000 CFF4) bit description . . . . . . . . . . . . .221 (USBEpIntPri - address 0x5000 C240) bit
Table 190. USB Clock Status register (USBClkSt - address description . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
0x5000 CFF8) bit description . . . . . . . . . . . . .222 Table 211. USB Realize Endpoint register (USBReEp -
Table 191. USB Interrupt Status register (USBIntSt - address address 0x5000 C244) bit allocation . . . . . . 231
0x5000 C1C0) bit description . . . . . . . . . . . . .222 Table 212. USB Realize Endpoint register (USBReEp -
Table 192. USB Device Interrupt Status register address 0x5000 C244) bit description . . . . . 231
(USBDevIntSt - address 0x5000 C200) bit Table 213. USB Endpoint Index register (USBEpIn - address
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 0x5000 C248) bit description . . . . . . . . . . . . 232
Table 193. USB Device Interrupt Status register Table 214. USB MaxPacketSize register (USBMaxPSize -
(USBDevIntSt - address 0x5000 C200) bit address 0x5000 C24C) bit description . . . . . 232
description . . . . . . . . . . . . . . . . . . . . . . . . . . .223 Table 215. USB Receive Data register (USBRxData -
Table 194. USB Device Interrupt Enable register address 0x5000 C218) bit description . . . . . 233
(USBDevIntEn - address 0x5000 C204) bit Table 216. USB Receive Packet Length register
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 (USBRxPlen - address 0x5000 C220) bit
Table 195. USB Device Interrupt Enable register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
(USBDevIntEn - address 0x5000 C204) bit Table 217. USB Transmit Data register (USBTxData -
description . . . . . . . . . . . . . . . . . . . . . . . . . . .224 address 0x5000 C21C) bit description . . . . . 233
Table 196. USB Device Interrupt Clear register Table 218. USB Transmit Packet Length register
(USBDevIntClr - address 0x5000 C208) bit (USBTxPLen - address 0x5000 C224) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 197. USB Device Interrupt Clear register Table 219. USB Control register (USBCtrl - address 0x5000
(USBDevIntClr - address 0x5000 C208) bit C228) bit description . . . . . . . . . . . . . . . . . . . 234
description . . . . . . . . . . . . . . . . . . . . . . . . . . .225 Table 220. USB Command Code register (USBCmdCode -
Table 198. USB Device Interrupt Set register (USBDevIntSet address 0x5000 C210) bit description . . . . . 235
- address 0x5000 C20C) bit allocation . . . . .225 Table 221. USB Command Data register (USBCmdData -
Table 199. USB Device Interrupt Set register (USBDevIntSet address 0x5000 C214) bit description . . . . . 235
- address 0x5000 C20C) bit description . . . .225 Table 222. USB DMA Request Status register (USBDMARSt
Table 200. USB Device Interrupt Priority register - address 0x5000 C250) bit allocation . . . . . 235
(USBDevIntPri - address 0x5000 C22C) bit Table 223. USB DMA Request Status register (USBDMARSt
description . . . . . . . . . . . . . . . . . . . . . . . . . . .226 - address 0x5000 C250) bit description . . . . 236
Table 201. USB Endpoint Interrupt Status register Table 224. USB DMA Request Clear register (USBDMARClr
(USBEpIntSt - address 0x5000 C230) bit - address 0x5000 C254) bit description . . . . 236
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 Table 225. USB DMA Request Set register (USBDMARSet -
Table 202. USB Endpoint Interrupt Status register address 0x5000 C258) bit description . . . . . 237
(USBEpIntSt - address 0x5000 C230) bit Table 226. USB UDCA Head register (USBUDCAH -
description . . . . . . . . . . . . . . . . . . . . . . . . . . .226 address 0x5000 C280) bit description . . . . . 237
Table 203. USB Endpoint Interrupt Enable register Table 227. USB EP DMA Status register (USBEpDMASt -
(USBEpIntEn - address 0x5000 C234) bit address 0x5000 C284) bit description . . . . . 237
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Table 228. USB EP DMA Enable register (USBEpDMAEn -
Table 204. USB Endpoint Interrupt Enable register address 0x5000 C288) bit description . . . . . 238
(USBEpIntEn - address 0x5000 C234) bit Table 229. USB EP DMA Disable register (USBEpDMADis -
description . . . . . . . . . . . . . . . . . . . . . . . . . . .228 address 0x5000 C28C) bit description . . . . . 238
Table 205. USB Endpoint Interrupt Clear register Table 230. USB DMA Interrupt Status register
(USBEpIntClr - address 0x5000 C238) bit (USBDMAIntSt - address 0x5000 C290) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 206. USB Endpoint Interrupt Clear register Table 231. USB DMA Interrupt Enable register
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(USBDMAIntEn - address 0x5000 C294) bit 0x5000 CFF8) bit description. . . . . . . . . . . . . 281
description . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Table 263. I2C Receive register (I2C_RX - address
Table 232. USB End of Transfer Interrupt Status register 0x5000 C300) bit description . . . . . . . . . . . . . 282
(USBEoTIntSt - address 0x5000 C2A0s) bit Table 264. I2C Transmit register (I2C_TX - address
description . . . . . . . . . . . . . . . . . . . . . . . . . . .239 0x5000 C300) bit description . . . . . . . . . . . . . 282
Table 233. USB End of Transfer Interrupt Clear register Table 265. I2C status register (I2C_STS - address
(USBEoTIntClr - address 0x5000 C2A4) bit 0x5000 C304) bit description . . . . . . . . . . . . . 282
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240 Table 266. I2C Control register (I2C_CTL - address
Table 234. USB End of Transfer Interrupt Set register 0x5000 C308) bit description . . . . . . . . . . . . . 284
(USBEoTIntSet - address 0x5000 C2A8) bit Table 267. I2C_CLKHI register (I2C_CLKHI - address
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240 0x5000 C30C) bit description. . . . . . . . . . . . . 285
Table 235. USB New DD Request Interrupt Status register Table 268. I2C_CLKLO register (I2C_CLKLO - address
(USBNDDRIntSt - address 0x5000 C2AC) bit 0x5000 C310) bit description . . . . . . . . . . . . . 285
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240 Table 269: UARTn Pin description . . . . . . . . . . . . . . . . . 299
Table 236. USB New DD Request Interrupt Clear register Table 270. UART0/2/3 Register Map . . . . . . . . . . . . . . . 300
(USBNDDRIntClr - address 0x5000 C2B0) bit Table 271: UARTn Receiver Buffer Register (U0RBR -
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240 address 0x4000 C000, U2RBR - 0x4009 8000,
Table 237. USB New DD Request Interrupt Set register U3RBR - 04009 C000 when DLAB = 0) bit
(USBNDDRIntSet - address 0x5000 C2B4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241 Table 272: UARTn Transmit Holding Register (U0THR -
Table 238. USB System Error Interrupt Status register address 0x4000 C000, U2THR - 0x4009 8000,
(USBSysErrIntSt - address 0x5000 C2B8) bit U3THR - 0x4009 C000 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 239. USB System Error Interrupt Clear register Table 273: UARTn Divisor Latch LSB register (U0DLL -
(USBSysErrIntClr - address 0x5000 C2BC) bit address 0x4000 C000, U2DLL - 0x4009 8000,
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241 U3DLL - 0x4009 C000 when DLAB = 1) bit
Table 240. USB System Error Interrupt Set register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
(USBSysErrIntSet - address 0x5000 C2C0) bit Table 274: UARTn Divisor Latch MSB register (U0DLM -
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241 address 0x4000 C004, U2DLM - 0x4009 8004,
Table 241. SIE command code table. . . . . . . . . . . . . . . .245 U3DLM - 0x4009 C004 when DLAB = 1) bit
Table 242. Set Address command bit description . . . . . .245 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 243. Configure Device command bit description . .246 Table 275: UARTn Interrupt Enable Register (U0IER -
Table 244. Set Mode command bit description . . . . . . . .246 address 0x4000 C004, U2IER - 0x4009 8004,
Table 245. Set Device Status command bit description. .247 U3IER - 0x4009 C004 when DLAB = 0) bit
Table 246. Get Error Code command bit description. . . .249 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 247. Read Error Status command bit description .249 Table 276: UARTn Interrupt Identification Register (U0IIR -
Table 248. Select Endpoint command bit description . . .250 address 0x4000 C008, U2IIR - 0x4009 8008,
Table 249. Set Endpoint Status command bit description251 U3IIR - 0x4009 C008) bit description. . . . . . . 303
Table 250. Clear Buffer command bit description . . . . . .252 Table 277: UARTn Interrupt Handling . . . . . . . . . . . . . . . 304
Table 251. DMA descriptor . . . . . . . . . . . . . . . . . . . . . . .257 Table 278: UARTn FIFO Control Register (U0FCR - address
Table 252. USB (OHCI) related acronyms and abbreviations 0x4000 C008, U2FCR - 0x4009 8008, U3FCR -
used in this chapter . . . . . . . . . . . . . . . . . . . .269 0x4007 C008) bit description . . . . . . . . . . . . . 305
Table 253. USB Host port pins . . . . . . . . . . . . . . . . . . . .271 Table 279: UARTn Line Control Register (U0LCR - address
Table 254. USB Host register address definitions . . . . .271 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR -
Table 255. USB OTG port pins . . . . . . . . . . . . . . . . . . . .275 0x4009 C00C) bit description. . . . . . . . . . . . . 306
Table 256. USB OTG and I2C register address definitions . . Table 280: UARTn Line Status Register (U0LSR - address
277 0x4000 C014, U2LSR - 0x4009 8014, U3LSR -
Table 257. USB Interrupt Status register - (USBIntSt - 0x4009 C014) bit description . . . . . . . . . . . . . 307
address 0x5000 C1C0) bit description . . . . . .277 Table 281: UARTn Scratch Pad Register (U0SCR - address
Table 258. OTG Interrupt Status register (OTGIntSt - 0x4000 C01C, U2SCR - 0x4009 801C, U3SCR -
address 0x5000 C100) bit description . . . . . .278 0x4009 C01C) bit description. . . . . . . . . . . . . 308
Table 259. OTG Status Control register (OTGStCtrl - address Table 282: UARTn Auto-baud Control Register (U0ACR -
0x5000 C110) bit description . . . . . . . . . . . . .279 address 0x4000 C020, U2ACR - 0x4009 8020,
Table 260. OTG Timer register (OTGTmr - address U3ACR - 0x4009 C020) bit description . . . . . 308
0x5000 C114) bit description . . . . . . . . . . . . .280 Table 283: UARTn IrDA Control Register (U0ICR - 0x4000
Table 261. OTG clock control register (OTG_clock_control - C024, U2ICR - 0x4009 8024, U3ICR - 0x4009
address 0x5000 CFF4) bit description . . . . . .280 C024) bit description . . . . . . . . . . . . . . . . . . . 311
Table 262. OTG clock status register (OTGClkSt - address Table 284: IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . . 312
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Table 336. CAN Wake-up Flags register (CANWAKEFLAGS Table 367: SPI Interrupt Register (S0SPINT - address
- address 0x400F C114) bit description . . . . .370 0x4002 001C) bit description . . . . . . . . . . . . . 410
Table 337. Central Transit Status Register (CANTxSR - Table 368. SSP pin descriptions . . . . . . . . . . . . . . . . . . . 413
address 0x4004 0000) bit description. . . . . . .372 Table 369. SSP Register Map. . . . . . . . . . . . . . . . . . . . . 421
Table 338. Central Receive Status Register (CANRxSR - Table 370: SSPn Control Register 0 (SSP0CR0 - address
address 0x4004 0004) bit description. . . . . . .372 0x4008 8000, SSP1CR0 - 0x4003 0000) bit
Table 339. Central Miscellaneous Status Register (CANMSR description . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
- address 0x4004 0008) bit description . . . . .373 Table 371: SSPn Control Register 1 (SSP0CR1 - address
Table 340. Acceptance filter modes and access control .373 0x4008 8004, SSP1CR1 - 0x4003 0004) bit
Table 341. Section configuration register settings . . . . . .374 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Table 342. Acceptance Filter Mode Register (AFMR - Table 372: SSPn Data Register (SSP0DR - address
address 0x4003 C000) bit description . . . . . .377 0x4008 8008, SSP1DR - 0x4003 0008) bit
Table 343. Standard Frame Individual Start Address register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
(SFF_sa - address 0x4003 C004) bit description . Table 373: SSPn Status Register (SSP0SR - address
378 0x4008 800C, SSP1SR - 0x4003 000C) bit
Table 344. Standard Frame Group Start Address register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
(SFF_GRP_sa - address 0x4003 C008) bit Table 374: SSPn Clock Prescale Register (SSP0CPSR -
description . . . . . . . . . . . . . . . . . . . . . . . . . . .378 address 0x4008 8010, SSP1CPSR -
Table 345. Extended Frame Start Address register (EFF_sa 0x4003 0010) bit description . . . . . . . . . . . . . 424
- address 0x4003 C00C) bit description . . . . .378 Table 375: SSPn Interrupt Mask Set/Clear register
Table 346. Extended Frame Group Start Address register (SSP0IMSC - address 0x4008 8014, SSP1IMSC -
(EFF_GRP_sa - address 0x4003 C010) bit 0x4003 0014) bit description . . . . . . . . . . . . . 425
description . . . . . . . . . . . . . . . . . . . . . . . . . . .379 Table 376: SSPn Raw Interrupt Status register (SSP0RIS -
Table 347. End of AF Tables register (ENDofTable - address address 0x4008 8018, SSP1RIS - 0x4003 0018)
0x4003 C014) bit description . . . . . . . . . . . . .379 bit description. . . . . . . . . . . . . . . . . . . . . . . . . 425
Table 348. LUT Error Address register (LUTerrAd - address Table 377: SSPn Masked Interrupt Status register (SSPnMIS
0x4003 C018) bit description . . . . . . . . . . . . .380 -address 0x4008 801C, SSP1MIS -
Table 349. LUT Error register (LUTerr - address 0x4003 001C) bit description . . . . . . . . . . . . . 426
0x4003 C01C) bit description . . . . . . . . . . . . .380 Table 378: SSPn interrupt Clear Register (SSP0ICR -
Table 350. Global FullCAN Enable register (FCANIE - address 0x4008 8020, SSP1ICR - 0x4003 0020)
address 0x4003 C020) bit description . . . . . .380 bit description. . . . . . . . . . . . . . . . . . . . . . . . . 426
Table 351. FullCAN Interrupt and Capture register 0 Table 379: SSPn DMA Control Register (SSP0DMACR -
(FCANIC0 - address 0x4003 C024) bit address 0x4008 8024, SSP1DMACR -
description . . . . . . . . . . . . . . . . . . . . . . . . . . .380 0x4003 0024) bit description . . . . . . . . . . . . . 427
Table 352. FullCAN Interrupt and Capture register 1 Table 380. I2C Pin Description . . . . . . . . . . . . . . . . . . . . 430
(FCANIC1 - address 0x4003 C028) bit Table 381. I2C0CONSET and I2C1CONSET used to
description . . . . . . . . . . . . . . . . . . . . . . . . . . .381 configure Master mode . . . . . . . . . . . . . . . . . 431
Table 353. Format of automatically stored Rx messages 384 Table 382. I2C0CONSET and I2C1CONSET used to
Table 354. FullCAN semaphore operation. . . . . . . . . . . .384 configure Slave mode . . . . . . . . . . . . . . . . . . 433
Table 355. Example of Acceptance Filter Tables and ID index Table 383. I2C register map . . . . . . . . . . . . . . . . . . . . . . 439
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394 Table 384. I2C Control Set register (I2CONSET: I2C0,
Table 356. Used ID-Look-up Table sections . . . . . . . . . .396 I2C0CONSET - address 0x4001 C000, I2C1,
Table 357. Used ID-Look-up Table sections . . . . . . . . . .397 I2C1CONSET - address 0x4005 C000, I2C2,
Table 358. SPI pin description . . . . . . . . . . . . . . . . . . . . .402 I2C2CONSET - address 0x400A 0000) bit
Table 359. SPI Data To Clock Phase Relationship . . . . .403 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Table 360. SPI register map . . . . . . . . . . . . . . . . . . . . . .406 Table 385. I2C Control Clear register (I2CONCLR: I2C0,
Table 361: SPI Control Register (S0SPCR - address I2C0CONCLR - 0x4001 C018; I2C1,
0x4002 0000) bit description . . . . . . . . . . . . .407 I2C1CONCLR - 0x4005 C018; I2C2,
Table 362: SPI Status Register (S0SPSR - address I2C2CONCLR - 0x400A 0018) bit description 442
0x4002 0004) bit description . . . . . . . . . . . . .408 Table 386. I2C Status register (I2STAT: I2C0, I2C0STAT -
Table 363: SPI Data Register (S0SPDR - address 0x4001 C004; I2C1, I2C1STAT - 0x4005 C004;
0x4002 0008) bit description . . . . . . . . . . . . .408 I2C2, I2C2STAT - 0x400A 0004) bit
Table 364: SPI Clock Counter Register (S0SPCCR - address description . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
0x4002 000C) bit description . . . . . . . . . . . . .409 Table 387. I2C Data register (I2DAT: I2C0, I2C0DAT -
Table 365: SPI Test Control Register (SPTCR - address 0x4001 C008; I2C1, I2C1DAT - 0x4005 C008;
0x4002 0010) bit description . . . . . . . . . . . . .409 I2C2, I2C2DAT - 0x400A 0008) bit description444
Table 366: SPI Test Status Register (SPTSR - address Table 388. I2C Monitor mode control register (I2MMCTRL:
0x4002 0014) bit description . . . . . . . . . . . . .409 I2C0, I2C0MMCTRL - 0x4001 C01C; I2C1,
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I2C1MMCTRL- 0x4005 C01C; I2C2, address 0x400A 8020) bit description . . . . . . 480
I2C2MMCTRL- 0x400A 001C) bit description 444 Table 414: Receive Clock Rate register (I2SRXRATE -
Table 389. I2C Data buffer register (I2DATA_BUFFER: I2C0, address 0x400A 8024) bit description . . . . . . 481
I2CDATA_BUFFER - 0x4001 C02C; I2C1, Table 415: Transmit Clock Rate register (I2TXBITRATE -
I2C1DATA_BUFFER- 0x4005 C02C; I2C2, address 0x400A 8028) bit description . . . . . . 481
I2C2DATA_BUFFER- 0x400A 002C) bit Table 416: Receive Clock Rate register (I2SRXBITRATE -
description . . . . . . . . . . . . . . . . . . . . . . . . . . .446 address 0x400A 802C) bit description . . . . . . 481
Table 390. I2C Slave Address registers (I2ADR0 to 3: I2C0, Table 417: Transmit Mode Control register (I2STXMODE -
I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28]; 0x400A 8030) bit description . . . . . . . . . . . . . 482
I2C1, I2C1ADR[0, 1, 2, 3] - address Table 418: Receive Mode Control register (I2SRXMODE -
0x4005 C0[0C, 20, 24, 28]; I2C2, I2C2ADR[0, 1, 2, 0x400A 8034) bit description . . . . . . . . . . . . . 482
3] - address 0x400A 00[0C, 20, 24, 28]) bit Table 419: I2S transmit modes . . . . . . . . . . . . . . . . . . . . 484
description . . . . . . . . . . . . . . . . . . . . . . . . . . .446 Table 420: I2S receive modes . . . . . . . . . . . . . . . . . . . . 486
Table 391. I2C Mask registers (I2MASK0 to 3: I2C0, Table 421. Conditions for FIFO level comparison . . . . . . 488
I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C]; Table 422. DMA and interrupt request generation . . . . . 488
I2C1, I2C1MASK[0, 1, 2, 3] - address Table 423. Status feedback in the I2SSTATE register . . 488
0x4005 C0[30, 34, 38, 3C]; I2C2, I2C2MASK[0, 1, Table 424. Timer/Counter pin description . . . . . . . . . . . . 491
2, 3] - address 0x400A 00[30, 34, 38, 3C]) bit Table 425. TIMER/COUNTER0-3 register map . . . . . . . 492
description . . . . . . . . . . . . . . . . . . . . . . . . . . .447 Table 426. Interrupt Register (T[0/1/2/3]IR - addresses
Table 392. I2C SCL HIGH Duty Cycle register (I2SCLH: I2C0, 0x4000 4000, 0x4000 8000, 0x4009 0000,
I2C0SCLH - address 0x4001 C010; I2C1, 0x4009 4000) bit description . . . . . . . . . . . . . 493
I2C1SCLH - address 0x4005 C010; I2C2, Table 427. Timer Control Register (TCR, TIMERn: TnTCR -
I2C2SCLH - 0x400A 0010) bit description . . .447 addresses 0x4000 4004, 0x4000 8004,
Table 393. I2C SCL Low duty cycle register (I2SCLL: I2C0 - 0x4009 0004, 0x4009 4004) bit description . . 494
I2C0SCLL: 0x4001 C014; I2C1 - I2C1SCLL: Table 428. Count Control Register (T[0/1/2/3]CTCR -
0x4005 C014; I2C2 - I2C2SCLL: 0x400A 0014) bit addresses 0x4000 4070, 0x4000 8070,
description . . . . . . . . . . . . . . . . . . . . . . . . . . .447 0x4009 0070, 0x4009 4070) bit description . . 494
Table 394. Example I2C clock rates. . . . . . . . . . . . . . . . .448 Table 429. Match Control Register (T[0/1/2/3]MCR -
Table 395. Abbreviations used to describe an I2C addresses 0x4000 4014, 0x4000 8014,
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .449 0x4009 0014, 0x4009 4014) bit description . . 496
Table 396. I2CONSET used to initialize Master Transmitter Table 430. Capture Control Register (T[0/1/2/3]CCR -
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450 addresses 0x4000 4028, 0x4000 8020,
Table 397. I2CONSET used to initialize Slave Receiver 0x4009 0028, 0x4009 4028) bit description . . 497
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454 Table 431. External Match Register (T[0/1/2/3]EMR -
Table 398. Master Transmitter mode. . . . . . . . . . . . . . . .457 addresses 0x4000 403C, 0x4000 803C,
Table 399. Master Receiver mode. . . . . . . . . . . . . . . . . .458 0x4009 003C, 0x4009 403C) bit description . 498
Table 400. Slave Receiver mode. . . . . . . . . . . . . . . . . . .459 Table 432. External Match Control . . . . . . . . . . . . . . . . . 498
Table 401. Slave Transmitter mode. . . . . . . . . . . . . . . . .461 Table 433. Repetitive Interrupt Timer register map. . . . . 501
Table 402. Miscellaneous States . . . . . . . . . . . . . . . . . . .462 Table 434. RI Compare Value register (RICOMPVAL -
Table 403. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . .475 address 0x400B 0000) bit description . . . . . . 501
Table 404. I2S register map. . . . . . . . . . . . . . . . . . . . . . .476 Table 435. RI Compare Value register (RICOMPVAL -
Table 405: Digital Audio Output register (I2SDAO - address address 0x400B 0004) bit description . . . . . . 501
0x400A 8000) bit description . . . . . . . . . . . . .476 Table 436. RI Control register (RICTRL - address 0x400B
Table 406: Digital Audio Input register (I2SDAI - address 0008) bit description. . . . . . . . . . . . . . . . . . . . 502
0x400A 8004) bit description . . . . . . . . . . . . .477 Table 437. RI Counter register (RICOUNTER - address
Table 407: Transmit FIFO register (I2STXFIFO - address 0x400B 000C) bit description. . . . . . . . . . . . . 502
0x400A 8008) bit description . . . . . . . . . . . . .477 Table 438. System Tick Timer register map . . . . . . . . . . 505
Table 408: Receive FIFO register (I2RXFIFO - address Table 439. System Timer Control and status register
0x400A 800C) bit description . . . . . . . . . . . . .478 (STCTRL - 0xE000 E010) bit description. . . . 505
Table 409: Status Feedback register (I2SSTATE - address Table 440. System Timer Reload value register (STRELOAD
0x400A 8010) bit description . . . . . . . . . . . . .478 - 0xE000 E014) bit description. . . . . . . . . . . . 506
Table 410: DMA Configuration register 1 (I2SDMA1 - Table 441. System Timer Current value register (STCURR -
address 0x400A 8014) bit description . . . . . .478 0xE000 E018) bit description . . . . . . . . . . . . . 506
Table 411: DMA Configuration register 2 (I2SDMA2 - Table 442. System Timer Calibration value register
address 0x400A 8018) bit description . . . . . .479 (STCALIB - 0xE000 E01C) bit description . . . 507
Table 412: Interrupt Request Control register (I2SIRQ - Table 443. Set and reset inputs for PWM Flip-Flops. . . . 512
address 0x400A 801C) bit description . . . . . .479 Table 444. Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . 513
Table 413: Transmit Clock Rate register (I2TXRATE - Table 445. PWM1 register map . . . . . . . . . . . . . . . . . . . 514
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Table 446: PWM Interrupt Register (PWM1IR - address - 0x400B 8018, 0x400B 801C, 0x400B 8020) bit
0x4001 8000) bit description . . . . . . . . . . . . .515 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Table 447. PWM Timer Control Register (PWM1TCR Table 473. MCPWM Limit 0-2 registers (MCLIM0-2 -
address 0x4001 8004) bit description. . . . . . .516 0x400B 8024, 0x400B 8028, 0x400B 802C) bit
Table 448. PWM Count control Register (PWM1CTCR - description . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
address 0x4001 8070) bit description. . . . . . .516 Table 474. MCPWM Match 0-2 registers (MCMAT0-2 -
Table 449: Match Control Register (PWM1MCR - address addresses 0x400B 8030, 0x400B 8034,
0x4001 8014) bit description . . . . . . . . . . . . .517 0x400B 8038) bit description . . . . . . . . . . . . . 534
Table 450: PWM Capture Control Register (PWM1CCR - Table 475. MCPWM Dead-time register (MCDT - address
address 0x4001 8028) bit description. . . . . . .518 0x400B 803C) bit description. . . . . . . . . . . . . 535
Table 451: PWM Control Register (PWM1PCR - address Table 476. MCPWM Commutation Pattern register (MCCP -
0x4001 804C) bit description . . . . . . . . . . . . .519 address 0x400B 8040) bit description . . . . . . 535
Table 452: PWM Latch Enable Register (PWM1LER - Table 477. MCPWM Capture read addresses (MCCAP0/1/2
address 0x4001 8050) bit description. . . . . . .520 - 0x400B 8044, 0x400B 8048, 0x400B 804C) bit
Table 453. Pin summary . . . . . . . . . . . . . . . . . . . . . . . . .522 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 454. Motor Control Pulse Width Modulator (MCPWM) Table 478. MCPWM Capture clear address (CAP_CLR -
register map . . . . . . . . . . . . . . . . . . . . . . . . . .525 0x400B 8074) bit description . . . . . . . . . . . . . 536
Table 455. MCPWM Control read address (MCCON - Table 479. Encoder states . . . . . . . . . . . . . . . . . . . . . . . 545
0x400B 8000) bit description . . . . . . . . . . . . .526 Table 480. Encoder state transitions[1] . . . . . . . . . . . . . . 545
Table 456. MCPWM Control set address (MCCON_SET - Table 481. Encoder direction . . . . . . . . . . . . . . . . . . . . . 546
0x400B 8004) bit description . . . . . . . . . . . . .527 Table 482. QEI pin description . . . . . . . . . . . . . . . . . . . . 548
Table 457. MCPWM Control clear address (MCCON_CLR - Table 483. QEI Register summary . . . . . . . . . . . . . . . . . 549
0x400B 8008) bit description . . . . . . . . . . . . .528 Table 484: QEI Control register (QEICON - address
Table 458. MCPWM Capture Control read address 0x400B C000) bit description. . . . . . . . . . . . . 550
(MCCAPCON - 0x400B 800C) bit description 528 Table 485: QEI Configuration register (QEICONF - address
Table 459. MCPWM Capture Control set address 0x400B C008) bit description. . . . . . . . . . . . . 550
(MCCAPCON_SET - 0x400B 8010) bit Table 486: QEI Interrupt Status register (QEISTAT - address
description . . . . . . . . . . . . . . . . . . . . . . . . . . .529 0x400B C004) bit description. . . . . . . . . . . . . 550
Table 460. MCPWM Capture control clear register Table 487: QEI Position register (QEIPOS - address
(MCCAPCON_CLR - address 0x400B 8014) bit 0x400B C00C) bit description . . . . . . . . . . . . 551
description . . . . . . . . . . . . . . . . . . . . . . . . . . .529 Table 488: QEI Maximum Position register (QEIMAXPOS -
Table 461. Motor Control PWM interrupts . . . . . . . . . . . .529 address 0x400B C010) bit description . . . . . . 551
Table 462. Interrupt sources bit allocation table . . . . . . .529 Table 489: QEI Position Compare register 0 (CMPOS0 -
Table 463. MCPWM Interrupt Enable read address address 0x400B C014) bit description . . . . . . 551
(MCINTEN - 0x400B 8050) bit description . . .529 Table 490: QEI Position Compare register 1 (CMPOS1 -
Table 464. PWM interrupt enable set register address 0x400B C018) bit description . . . . . . 551
(MCINTEN_SET - address 0x400B 8054) bit Table 491: QEI Position Compare register 2 (CMPOS2 -
description . . . . . . . . . . . . . . . . . . . . . . . . . . .530 address 0x400B C01C) bit description . . . . . 552
Table 465. PWM interrupt enable clear register Table 492: QEI Index Count register (CMPOS - address
(MCINTEN_CLR - address 0x400B 8058) bit 0x400B C020) bit description. . . . . . . . . . . . . 552
description . . . . . . . . . . . . . . . . . . . . . . . . . . .530 Table 493: QEI Index Compare register (CMPOS - address
Table 466. MCPWM Interrupt Flags read address (MCINTF - 0x400B C024) bit description. . . . . . . . . . . . . 552
0x400B 8068) bit description . . . . . . . . . . . . .530 Table 494: QEI Timer Load register (QEILOAD - address
Table 467. MCPWM Interrupt Flags set address 0x400B C028) bit description. . . . . . . . . . . . . 552
(PWMINTF_SET - 0x400B 806C) bit Table 495: QEI Timer register (QEITIME - address
description . . . . . . . . . . . . . . . . . . . . . . . . . . .530 0x400B C02C) bit description . . . . . . . . . . . . 552
Table 468. MCPWM Interrupt Flags clear address Table 496: QEI Velocity register (QEIVEL - address
(PWMINTF_CLR - 0x400B 8070) bit 0x400B C030) bit description. . . . . . . . . . . . . 553
description . . . . . . . . . . . . . . . . . . . . . . . . . . .531 Table 497: QEI Velocity Capture register (QEICAP - address
Table 469. MCPWM Count Control read address 0x400B C034) bit description. . . . . . . . . . . . . 553
(MCCNTCON - 0x400B 805C) bit description 531 Table 498: QEI Velocity Compare register (VELCOMP -
Table 470. MCPWM Count Control set address address 0x400B C038) bit description . . . . . . 553
(MCCNTCON_SET - 0x400B 8060) bit Table 499: QEI Digital Filter register (FILTER - address
description . . . . . . . . . . . . . . . . . . . . . . . . . . .532 0x400B C03C) bit description . . . . . . . . . . . . 553
Table 471. MCPWM Count Control clear address Table 500: QEI Interrupt Status register (QEIINTSTAT -
(MCCAPCON_CLR - 0x400B 8064) bit address 0x400B CFE0) bit description . . . . . 554
description . . . . . . . . . . . . . . . . . . . . . . . . . . .532 Table 501: QEI Interrupt Set register (QEISET - address
Table 472. MCPWM Timer/Counter 0-2 registers (MCTC0-2 0x400B CFEC) bit description . . . . . . . . . . . . 554
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Table 502: QEI Interrupt Clear register (QEICLR - 0x4003 4010 to 0x4003 402C) bit description 579
0x400B CFE8) bit description . . . . . . . . . . . . .555 Table 535: A/D Status register (AD0STAT - address
Table 503: QEI Interrupt Enable register (QEIIE - address 0x4003 4030) bit description . . . . . . . . . . . . . 580
0x400B CFE4) bit description . . . . . . . . . . . . .555 Table 536: A/D Trim register (ADTRM - address
Table 504: QEI Interrupt Enable Set register (QEIIES - 0x4003 4034) bit description . . . . . . . . . . . . . 580
address 0x400B CFDC) bit description . . . . .556 Table 537. D/A Pin Description . . . . . . . . . . . . . . . . . . . . 582
Table 505: QEI Interrupt Enable Clear register (QEIIEC - Table 538. DAC registers . . . . . . . . . . . . . . . . . . . . . . . . 583
address 0x400B CFD8) bit description . . . . . .557 Table 539: D/A Converter Register (DACR - address
Table 506. RTC pin description . . . . . . . . . . . . . . . . . . . .560 0x4008 C000) bit description . . . . . . . . . . . . . 583
Table 507. Real-Time Clock register map . . . . . . . . . . . .561 Table 540. D/A Control register (DACCTRL - address
Table 508. Interrupt Location Register (ILR - address 0x4008 C004) bit description . . . . . . . . . . . . . 584
0x4002 4000) bit description . . . . . . . . . . . . .562 Table 541: D/A Converter register (DACR - address
Table 509. Clock Control Register (CCR - address 0x4008 C008) bit description . . . . . . . . . . . . . 584
0x4002 4008) bit description . . . . . . . . . . . . .562 Table 542. Endian behavior . . . . . . . . . . . . . . . . . . . . . . 589
Table 510. Counter Increment Interrupt Register (CIIR - Table 543. DMA Connections . . . . . . . . . . . . . . . . . . . . . 592
address 0x4002 400C) bit description . . . . . .563 Table 544. GPDMA register map . . . . . . . . . . . . . . . . . . 593
Table 511. Alarm Mask Register (AMR - address Table 545. DMA Interrupt Status register (DMACIntStat -
0x4002 4010) bit description . . . . . . . . . . . . .564 0x5000 4000) . . . . . . . . . . . . . . . . . . . . . . . . 595
Table 512. RTC Auxiliary control register (RTC_AUX - Table 546. DMA Interrupt Terminal Count Request Status
address 0x4002 405C) bit description . . . . . .564 register (DMACIntTCStat - 0x5000 4004) . . . 595
Table 513. RTC Auxiliary Enable register (RTC_AUXEN - Table 547. DMA Interrupt Terminal Count Request Clear
address 0x4002 4058) bit description. . . . . . .564 register (DMACIntTCClear - 0x5000 4008) . . 595
Table 514. Consolidated Time register 0 (CTIME0 - address Table 548. DMA Interrupt Error Status register
0x4002 4014) bit description . . . . . . . . . . . . .565 (DMACIntErrStat - 0x5000 400C) . . . . . . . . . 596
Table 515. Consolidated Time register 1 (CTIME1 - address Table 549. DMA Interrupt Error Clear register
0x4002 4018) bit description . . . . . . . . . . . . .565 (DMACIntErrClr - 0x5000 4010) . . . . . . . . . . 596
Table 516. Consolidated Time register 2 (CTIME2 - address Table 550. DMA Raw Interrupt Terminal Count Status
0x4002 401C) bit description . . . . . . . . . . . . .566 register (DMACRawIntTCStat - 0x5000 4014) . .
Table 517. Time Counter relationships and values . . . . .566 596
Table 518. Time Counter registers . . . . . . . . . . . . . . . . .566 Table 551. DMA Raw Error Interrupt Status register
Table 519. Calibration register (CALIBRATION - address (DMACRawIntErrStat - 0x5000 4018) . . . . . . 597
0x4002 4040) bit description . . . . . . . . . . . . .567 Table 552. DMA Enabled Channel register
Table 520. General purpose registers 0 to 4 (GPREG0 to (DMACEnbldChns - 0x5000 401C) . . . . . . . . 597
GPREG4 - addresses 0x4002 4044 to 0x4002 Table 553. DMA Software Burst Request register
4054) bit description . . . . . . . . . . . . . . . . . . . .568 (DMACSoftBReq - 0x5000 4020) . . . . . . . . . 597
Table 521. Alarm registers. . . . . . . . . . . . . . . . . . . . . . . .568 Table 554. DMA Software Single Request register
Table 522. Watchdog register map . . . . . . . . . . . . . . . . .570 (DMACSoftSReq - 0x5000 4024) . . . . . . . . . 598
Table 523: Watchdog Mode register (WDMOD - address Table 555. DMA Software Last Burst Request register
0x4000 0000) bit description . . . . . . . . . . . . .571 (DMACSoftLBReq - 0x5000 4028) . . . . . . . . 598
Table 524. Watchdog operating modes selection . . . . . .571 Table 556. DMA Software Last Single Request register
Table 525: Watchdog Constant register (WDTC - address (DMACSoftLSReq - 0x5000 402C) . . . . . . . . 599
0x4000 0004) bit description . . . . . . . . . . . . .572 Table 557. DMA Configuration register (DMACConfig -
Table 526: Watchdog Feed register (WDFEED - address 0x5000 4030) . . . . . . . . . . . . . . . . . . . . . . . . 599
0x4000 0008) bit description . . . . . . . . . . . . .572 Table 558. DMA Synchronization register (DMACSync -
Table 527: Watchdog Timer Value register (WDTV - address 0x5000 4034) . . . . . . . . . . . . . . . . . . . . . . . . 599
0x4000 000C) bit description . . . . . . . . . . . . .572 Table 559. DMA Request Select register (DMAReqSel -
Table 528: Watchdog Timer Clock Source Selection register 0x400F C1C4) . . . . . . . . . . . . . . . . . . . . . . . . 600
(WDCLKSEL - address 0x4000 0010) bit Table 560. DMA Channel Source Address registers
description . . . . . . . . . . . . . . . . . . . . . . . . . . .573 (DMACCxSrcAddr - 0x5000 41x0) . . . . . . . . 601
Table 529. ADC pin description . . . . . . . . . . . . . . . . . . . .575 Table 561. DMA Channel Destination Address registers
Table 530. ADC registers. . . . . . . . . . . . . . . . . . . . . . . . .576 (DMACCxDestAddr - 0x5000 41x4) . . . . . . . 601
Table 531: A/D Control Register (AD0CR - address Table 562. DMA Channel Linked List Item registers
0x4003 4000) bit description . . . . . . . . . . . . .577 (DMACCxLLI - 0x5000 41x8) . . . . . . . . . . . . 602
Table 532: A/D Global Data Register (AD0GDR - address Table 563. DMA channel control registers (DMACCxControl
0x4003 4004) bit description . . . . . . . . . . . . .578 - 0x5000 41xC) . . . . . . . . . . . . . . . . . . . . . . . 603
Table 533: A/D Status register (AD0INTEN - address Table 564. DMA Channel Configuration registers
0x4003 400C) bit description . . . . . . . . . . . . .578 (DMACCxConfig - 0x5000 41x0) . . . . . . . . . 605
Table 534: A/D Data Registers (AD0DR0 to AD0DR7 - Table 565. Transfer type bits . . . . . . . . . . . . . . . . . . . . . 606
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Table 566. DMA request signal usage . . . . . . . . . . . . . .609 Table 608. JTAG pin description . . . . . . . . . . . . . . . . . . . 642
Table 567. Sectors in a LPC17xx device . . . . . . . . . . . . .620 Table 609. Serial Wire Debug pin description. . . . . . . . . 642
Table 568. Code Read Protection options[1] . . . . . . . . . .621 Table 610. Parallel Trace pin description . . . . . . . . . . . . 642
Table 569. Code Read Protection hardware/software Table 611. Memory Mapping Control register (MEMMAP -
interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . .622 0x400F C040) bit description . . . . . . . . . . . . . 643
Table 570. ISP command summary. . . . . . . . . . . . . . . . .623 Table 612. Cortex-M3 instructions . . . . . . . . . . . . . . . . 647
Table 571. ISP Unlock command . . . . . . . . . . . . . . . . . .623 Table 613. CMSIS intrinsic functions to generate some
Table 572. ISP Set Baud Rate command . . . . . . . . . . . .624 Cortex-M3 instructions . . . . . . . . . . . . . . . . . . 650
Table 573. Correlation between possible ISP baudrates and Table 614. CMSIS intrinsic functions to access the special
CCLK frequency (in MHz). . . . . . . . . . . . . . . .624 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Table 574. ISP Echo command . . . . . . . . . . . . . . . . . . . .624 Table 615. Condition code suffixes . . . . . . . . . . . . . . . . . 657
Table 575. ISP Write to RAM command . . . . . . . . . . . . .625 Table 616. Memory access instructions . . . . . . . . . . . . . 660
Table 576. ISP Read Memory command. . . . . . . . . . . . .625 Table 617. Offset ranges. . . . . . . . . . . . . . . . . . . . . . . . . 663
Table 577. ISP Prepare sector(s) for write operation Table 618. Offset ranges. . . . . . . . . . . . . . . . . . . . . . . . . 669
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .626 Table 619. Data processing instructions . . . . . . . . . . . . . 677
Table 578. ISP Copy command . . . . . . . . . . . . . . . . . . . .626 Table 620. Multiply and divide instructions . . . . . . . . . . . 692
Table 579. ISP Go command. . . . . . . . . . . . . . . . . . . . . .627 Table 621. Packing and unpacking instructions . . . . . . . 700
Table 580. ISP Erase sector command . . . . . . . . . . . . . .627 Table 622. Branch and control instructions. . . . . . . . . . . 705
Table 581. ISP Blank check sector command . . . . . . . . .628 Table 623. Branch ranges. . . . . . . . . . . . . . . . . . . . . . . . 706
Table 582. ISP Read Part Identification command . . . . .628 Table 624. Miscellaneous instructions . . . . . . . . . . . . . . 714
Table 583. LPC17xx part identification numbers . . . . . . .628 Table 625. Summary of processor mode, execution privilege
Table 584. ISP Read Boot Code version number command . level, and stack use options . . . . . . . . . . . . . . 728
629 Table 626. Core register set summary . . . . . . . . . . . . . . 728
Table 585. ISP Read device serial number command. . .629 Table 627. PSR register combinations . . . . . . . . . . . . . . 730
Table 586. ISP Compare command. . . . . . . . . . . . . . . . .629 Table 628. APSR bit assignments . . . . . . . . . . . . . . . . . 731
Table 587. ISP Return Codes Summary . . . . . . . . . . . . .630 Table 629. IPSR bit assignments . . . . . . . . . . . . . . . . . . 732
Table 588. IAP Command Summary . . . . . . . . . . . . . . . .632 Table 630. EPSR bit assignments . . . . . . . . . . . . . . . . . 732
Table 589. IAP Prepare sector(s) for write operation Table 631. PRIMASK register bit assignments . . . . . . . . 733
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .633 Table 632. FAULTMASK register bit assignments . . . . . 733
Table 590. IAP Copy RAM to Flash command . . . . . . . .633 Table 633. BASEPRI register bit assignments . . . . . . . . 734
Table 591. IAP Erase Sector(s) command . . . . . . . . . . .634 Table 634. CONTROL register bit assignments . . . . . . . 734
Table 592. IAP Blank check sector(s) command . . . . . . .634 Table 635. Memory access behavior . . . . . . . . . . . . . . . 739
Table 593. IAP Read part identification number command . . Table 636. SRAM memory bit-banding regions . . . . . . . 741
634 Table 637. Peripheral memory bit-banding regions . . . . 741
Table 594. IAP Read Boot Code version number command . Table 638. C compiler intrinsic functions for exclusive access
635 instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Table 595. IAP Read device serial number command. . .635 Table 639. Properties of the different exception types . . 746
Table 596. IAP Compare command. . . . . . . . . . . . . . . . .635 Table 640. Exception return behavior . . . . . . . . . . . . . . . 751
Table 597. Re-invoke ISP . . . . . . . . . . . . . . . . . . . . . . . .636 Table 641. Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
Table 598. IAP Status Codes Summary . . . . . . . . . . . . .636 Table 642. Fault status and fault address registers . . . . 754
Table 599. Register overview: FMC (base address 0x4008 Table 643. Core peripheral register regions . . . . . . . . . . 759
4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637 Table 644. NVIC register summary. . . . . . . . . . . . . . . . . 760
Table 600. Flash Module Signature Start register Table 645. Mapping of interrupts to the interrupt variables . .
(FMSSTART - 0x4008 4020) bit description . .638 761
Table 601. Flash Module Signature Stop register (FMSSTOP Table 646. ISER bit assignments . . . . . . . . . . . . . . . . . . 761
- 0x4008 4024) bit description . . . . . . . . . . . .638 Table 647. ICER bit assignments . . . . . . . . . . . . . . . . . . 762
Table 602. FMSW0 register bit description (FMSW0, Table 648. ISPR bit assignments . . . . . . . . . . . . . . . . . . 762
address: 0x4008 402C) . . . . . . . . . . . . . . . . .638 Table 649. ICPR bit assignments . . . . . . . . . . . . . . . . . . 763
Table 603. FMSW1 register bit description (FMSW1, Table 650. IABR bit assignments . . . . . . . . . . . . . . . . . . 763
address: 0x4008 4030) . . . . . . . . . . . . . . . . .638 Table 651. IPR bit assignments . . . . . . . . . . . . . . . . . . . 764
Table 604. FMSW2 register bit description (FMSW2, Table 652. STIR bit assignments . . . . . . . . . . . . . . . . . . 764
address: 0x4008 4034) . . . . . . . . . . . . . . . . .639 Table 653. CMSIS functions for NVIC control. . . . . . . . . 766
Table 605. FMSW3 register bit description (FMSW3, Table 654. Summary of the system control block registers .
address: 0x4008 4038) . . . . . . . . . . . . . . . . .639 767
Table 606. Flash module Status register (FMSTAT - 0x4008 Table 655. ACTLR bit assignments . . . . . . . . . . . . . . . . 768
4FE0) bit description. . . . . . . . . . . . . . . . . . . .639 Table 656. CPUID register bit assignments . . . . . . . . . . 768
Table 607. Flash Module Status Clear register (FMSTATCLR Table 657. ICSR bit assignments . . . . . . . . . . . . . . . . . . 769
- 0x0x4008 4FE8) bit description . . . . . . . . . .639 Table 658. VTOR bit assignments . . . . . . . . . . . . . . . . . 771
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35.4 Figures
Fig 1. LPC1768 simplified block diagram. . . . . . . . . . . . .8 Fig 50. Auto-baud a) mode 0 and b) mode 1 waveform 334
Fig 2. LPC1768 block diagram, CPU and buses . . . . . . 11 Fig 51. Algorithm for setting UART dividers . . . . . . . . . 336
Fig 3. LPC17xx system memory map . . . . . . . . . . . . . .13 Fig 52. UART1 block diagram . . . . . . . . . . . . . . . . . . . . 342
Fig 4. Reset block diagram including the wake-up timer19 Fig 53. CAN controller block diagram . . . . . . . . . . . . . . 345
Fig 5. Example of start-up after reset. . . . . . . . . . . . . . .20 Fig 54. Transmit buffer layout for standard and extended
Fig 6. External interrupt logic . . . . . . . . . . . . . . . . . . . . .23 frame format configurations . . . . . . . . . . . . . . . 346
Fig 7. Clock generation for the LPC17xx . . . . . . . . . . . .29 Fig 55. Receive buffer layout for standard and extended
Fig 8. Oscillator modes and models: a) slave mode of frame format configurations . . . . . . . . . . . . . . . 347
operation, b) oscillation mode of operation, c) Fig 56. Global Self-Test (high-speed CAN Bus
external crystal model used for CX1/X2 evaluation32 example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Fig 9. PLL0 block diagram . . . . . . . . . . . . . . . . . . . . . . .36 Fig 57. Local self test (high-speed CAN Bus example). 348
Fig 10. PLL1 block diagram . . . . . . . . . . . . . . . . . . . . . . .48 Fig 58. Entry in FullCAN and individual standard identifier
Fig 11. PLLs and clock dividers . . . . . . . . . . . . . . . . . . . .54 tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Fig 12. CLKOUT selection . . . . . . . . . . . . . . . . . . . . . . . .66 Fig 59. Entry in standard identifier range table . . . . . . . 375
Fig 13. Simplified block diagram of the flash accelerator Fig 60. Entry in either extended identifier table . . . . . . . 376
showing potential bus connections . . . . . . . . . . .68 Fig 61. ID Look-up table example explaining the search
Fig 14. LPC176x LQFP100 pin configuration . . . . . . . . .91 algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Fig 15. LPC175x LQFP80 pin configuration . . . . . . . . . .91 Fig 62. Semaphore procedure for reading an auto-stored
Fig 16. Pin configuration TFBGA100 package. . . . . . . . .92 message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Fig 17. Ethernet block diagram . . . . . . . . . . . . . . . . . . .143 Fig 63. FullCAN section example of the ID look-up
Fig 18. Ethernet packet fields . . . . . . . . . . . . . . . . . . . .145 table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Fig 19. Receive descriptor memory layout. . . . . . . . . . .172 Fig 64. FullCAN message object layout . . . . . . . . . . . . 387
Fig 20. Transmit descriptor memory layout . . . . . . . . . .175 Fig 65. Normal case, no messages lost . . . . . . . . . . . . 389
Fig 21. Transmit example memory and registers. . . . . .186 Fig 66. Message lost . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Fig 22. Receive Example Memory and Registers . . . . .192 Fig 67. Message gets overwritten . . . . . . . . . . . . . . . . . 390
Fig 23. Transmit Flow Control . . . . . . . . . . . . . . . . . . . .197 Fig 68. Message overwritten indicated by semaphore bits
Fig 24. Receive filter block diagram. . . . . . . . . . . . . . . .199 and message lost . . . . . . . . . . . . . . . . . . . . . . . 391
Fig 25. Receive Active/Inactive state machine . . . . . . .203 Fig 69. Message overwritten indicated by message lost392
Fig 26. Transmit Active/Inactive state machine . . . . . . .204 Fig 70. Clearing message lost. . . . . . . . . . . . . . . . . . . . 393
Fig 27. USB device controller block diagram . . . . . . . . .216 Fig 71. Detailed example of acceptance filter tables and ID
Fig 28. USB MaxPacketSize register array indexing . . .232 index values . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Fig 29. Interrupt event handling . . . . . . . . . . . . . . . . . . .243 Fig 72. ID Look-up table configuration example (no
Fig 30. UDCA Head register and DMA Descriptors . . . .256 FullCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Fig 31. Isochronous OUT endpoint operation example .263 Fig 73. ID Look-up table configuration example (FullCAN
Fig 32. Data transfer in ATLE mode. . . . . . . . . . . . . . . .264 activated and enabled) . . . . . . . . . . . . . . . . . . . 399
Fig 33. USB Host controller block diagram . . . . . . . . . .270 Fig 74. SPI data transfer format (CPHA = 0 and
Fig 34. USB OTG controller block diagram . . . . . . . . . .274 CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Fig 35. USB OTG port configuration . . . . . . . . . . . . . . .275 Fig 75. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . 411
Fig 36. USB host port configuration . . . . . . . . . . . . . . . .276 Fig 76. Texas Instruments Synchronous Serial Frame
Fig 37. USB device port configuration . . . . . . . . . . . . . .276 Format: a) Single and b) Continuous/back-to-back
Fig 38. USB OTG interrupt handling . . . . . . . . . . . . . . .286 Two Frames Transfer . . . . . . . . . . . . . . . . . . . . 414
Fig 39. USB OTG controller with software stack . . . . . .287 Fig 77. SPI frame format with CPOL=0 and CPHA=0 (a)
Fig 40. Hardware support for B-device switching from Single and b) Continuous Transfer) . . . . . . . . . 415
peripheral state to host state . . . . . . . . . . . . . . .288 Fig 78. SPI frame format with CPOL=0 and CPHA=1. . 416
Fig 41. State transitions implemented in software during Fig 79. SPI frame format with CPOL = 1 and CPHA = 0 (a)
B-device switching from peripheral to host . . . .289 Single and b) Continuous Transfer) . . . . . . . . . 417
Fig 42. Hardware support for A-device switching from host Fig 80. SPI Frame Format with CPOL = 1 and
state to peripheral state . . . . . . . . . . . . . . . . . . .291 CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Fig 43. State transitions implemented in software during Fig 81. Microwire frame format (single transfer) . . . . . . 419
A-device switching from host to peripheral . . . .292 Fig 82. Microwire frame format (continuos transfers) . . 420
Fig 44. Clocking and power control . . . . . . . . . . . . . . . .295 Fig 83. Microwire frame format setup and hold details . 420
Fig 45. Auto-baud a) mode 0 and b) mode 1 waveform 311 Fig 84. I2C-bus configuration. . . . . . . . . . . . . . . . . . . . . 430
Fig 46. Algorithm for setting UART dividers. . . . . . . . . .314 Fig 85. Format in the Master Transmitter mode . . . . . . 432
Fig 47. UART0, 2 and 3 block diagram . . . . . . . . . . . . .317 Fig 86. Format of Master Receiver mode . . . . . . . . . . . 432
Fig 48. Auto-RTS Functional Timing . . . . . . . . . . . . . . .328 Fig 87. A Master Receiver switches to Master Transmitter
Fig 49. Auto-CTS Functional Timing . . . . . . . . . . . . . . .329 after sending repeated START . . . . . . . . . . . . . 433
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35.5 Contents
Chapter 1: LPC17xx Introductory information
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.7 ARM Cortex-M3 processor . . . . . . . . . . . . . . . . 9
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.7.1 Cortex-M3 Configuration Options . . . . . . . . . . 9
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 System options: . . . . . . . . . . . . . . . . . . . . . . . . . 9
Debug related options:. . . . . . . . . . . . . . . . . . . 10
1.4 Ordering information . . . . . . . . . . . . . . . . . . . . . 7
1.4.1 Part options summary. . . . . . . . . . . . . . . . . . . . 7 1.8 On-chip flash memory system. . . . . . . . . . . . 10
1.5 Simplified block diagram . . . . . . . . . . . . . . . . . 8 1.9 On-chip Static RAM. . . . . . . . . . . . . . . . . . . . . 10
1.6 Architectural overview . . . . . . . . . . . . . . . . . . . 9 1.10 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11
continued >>
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continued >>
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6.5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 6.5.18 Interrupt Priority Register 7 (IPR7 - 0xE000
E40C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 E41C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.5.15 Interrupt Priority Register 4 (IPR4 - 0xE000 6.5.19 Interrupt Priority Register 8 (IPR8 - 0xE000
E410) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 E420) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.5.16 Interrupt Priority Register 5 (IPR5 - 0xE000 6.5.20 Software Trigger Interrupt Register (STIR -
E414) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 0xE000 EF00) . . . . . . . . . . . . . . . . . . . . . . . . 90
6.5.17 Interrupt Priority Register 6 (IPR6 - 0xE000
E418) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
continued >>
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9.5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to 9.5.6.6 GPIO Interrupt Status for port 0 Rising Edge
FIO4PIN- 0x2009 C014 to 0x2009 C094) . . 127 Interrupt (IO0IntStatR - 0x4002 8084) . . . . . 135
9.5.5 Fast GPIO port Mask register FIOxMASK 9.5.6.7 GPIO Interrupt Status for port 2 Rising Edge
(FIO0MASK to FIO4MASK - 0x2009 C010 to Interrupt (IO2IntStatR - 0x4002 80A4) . . . . . 136
0x2009 C090) . . . . . . . . . . . . . . . . . . . . . . . . 129 9.5.6.8 GPIO Interrupt Status for port 0 Falling Edge
9.5.6 GPIO interrupt registers . . . . . . . . . . . . . . . . 131 Interrupt (IO0IntStatF - 0x4002 8088) . . . . . 136
9.5.6.1 GPIO overall Interrupt Status register (IOIntStatus 9.5.6.9 GPIO Interrupt Status for port 2 Falling Edge
- 0x4002 8080) . . . . . . . . . . . . . . . . . . . . . . . 131 Interrupt (IO2IntStatF - 0x4002 80A8) . . . . . 137
9.5.6.2 GPIO Interrupt Enable for port 0 Rising Edge 9.5.6.10 GPIO Interrupt Clear register for port 0 (IO0IntClr
(IO0IntEnR - 0x4002 8090) . . . . . . . . . . . . . 131 - 0x4002 808C) . . . . . . . . . . . . . . . . . . . . . . 138
9.5.6.3 GPIO Interrupt Enable for port 2 Rising Edge 9.5.6.11 GPIO Interrupt Clear register for port 0 (IO2IntClr
(IO2IntEnR - 0x4002 80B0) . . . . . . . . . . . . . 132 - 0x4002 80AC) . . . . . . . . . . . . . . . . . . . . . . 139
9.5.6.4 GPIO Interrupt Enable for port 0 Falling Edge 9.6 GPIO usage notes . . . . . . . . . . . . . . . . . . . . . 140
(IO0IntEnF - 0x4002 8094) . . . . . . . . . . . . . . 133 9.6.1 Example: An instantaneous output of 0s and 1s on
9.5.6.5 GPIO Interrupt Enable for port 2 Falling Edge a GPIO port . . . . . . . . . . . . . . . . . . . . . . . . . 140
(IO2IntEnF - 0x4002 80B4) . . . . . . . . . . . . . 134 9.6.2 Writing to FIOSET/FIOCLR vs. FIOPIN . . . . 140
continued >>
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10.12.7 Receive Consume Index Register 10.14.3 Interrupt Clear Register (IntClear - 0x5000
(RxConsumeIndex - 0x5000 0118) . . . . . . . . 160 0FE8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
10.12.8 Transmit Descriptor Base Address Register 10.14.4 Interrupt Set Register (IntSet - 0x5000
(TxDescriptor - 0x5000 011C). . . . . . . . . . . . 161 0FEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.12.9 Transmit Status Base Address Register (TxStatus 10.14.5 Power-Down Register (PowerDown -
- 0x5000 0120) . . . . . . . . . . . . . . . . . . . . . . . 161 0x5000 0FF4). . . . . . . . . . . . . . . . . . . . . . . . 171
10.12.10 Transmit Number of Descriptors Register 10.15 Descriptor and status formats . . . . . . . . . . . 172
(TxDescriptorNumber - 0x5000 0124) . . . . . 161 10.15.1 Receive descriptors and statuses . . . . . . . . 172
10.12.11 Transmit Produce Index Register 10.15.2 Transmit descriptors and statuses . . . . . . . . 175
(TxProduceIndex - 0x5000 0128) . . . . . . . . . 162
10.16 Ethernet block functional description. . . . . 177
10.12.12 Transmit Consume Index Register
10.16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
(TxConsumeIndex - 0x5000 012C). . . . . . . . 162
10.16.2 AHB interface. . . . . . . . . . . . . . . . . . . . . . . . 178
10.12.13 Transmit Status Vector 0 Register (TSV0 -
0x5000 0158) . . . . . . . . . . . . . . . . . . . . . . . . 162 10.17 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10.12.14 Transmit Status Vector 1 Register (TSV1 - 10.17.1 Direct Memory Access (DMA) . . . . . . . . . . . 178
0x5000 015C) . . . . . . . . . . . . . . . . . . . . . . . . 163 10.17.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 181
10.12.15 Receive Status Vector Register (RSV - 10.17.3 Transmit process . . . . . . . . . . . . . . . . . . . . . 182
0x5000 0160) . . . . . . . . . . . . . . . . . . . . . . . . 164 10.17.4 Receive process . . . . . . . . . . . . . . . . . . . . . 188
10.12.16 Flow Control Counter Register 10.17.5 Transmission retry . . . . . . . . . . . . . . . . . . . . 194
(FlowControlCounter - 0x5000 0170) . . . . . . 165 10.17.6 Status hash CRC calculations . . . . . . . . . . . 194
10.12.17 Flow Control Status Register (FlowControlStatus - 10.17.7 Duplex modes . . . . . . . . . . . . . . . . . . . . . . . 195
0x5000 0174) . . . . . . . . . . . . . . . . . . . . . . . . 165 10.17.8 IEE 802.3/Clause 31 flow control. . . . . . . . . 195
10.13 Receive filter register definitions . . . . . . . . . 166 10.17.9 Half-Duplex mode backpressure . . . . . . . . . 197
10.17.10 Receive filtering . . . . . . . . . . . . . . . . . . . . . . 198
10.13.1 Receive Filter Control Register (RxFilterCtrl -
10.17.11 Power management. . . . . . . . . . . . . . . . . . . 200
0x5000 0200) . . . . . . . . . . . . . . . . . . . . . . . . 166
10.17.12 Wake-up on LAN . . . . . . . . . . . . . . . . . . . . . 200
10.13.2 Receive Filter WoL Status Register
10.17.13 Enabling and disabling receive and transmit 202
(RxFilterWoLStatus - 0x5000 0204) . . . . . . . 166
10.17.14 Transmission padding and CRC . . . . . . . . . 204
10.13.3 Receive Filter WoL Clear Register
10.17.15 Huge frames and frame length checking . . . 205
(RxFilterWoLClear - 0x5000 0208) . . . . . . . . 167
10.17.16 Statistics counters . . . . . . . . . . . . . . . . . . . . 205
10.13.4 Hash Filter Table LSBs Register (HashFilterL -
10.17.17 MAC status vectors . . . . . . . . . . . . . . . . . . . 205
0x5000 0210) . . . . . . . . . . . . . . . . . . . . . . . . 167
10.17.18 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
10.13.5 Hash Filter Table MSBs Register (HashFilterH -
10.17.19 Ethernet errors . . . . . . . . . . . . . . . . . . . . . . . 207
0x5000 0214) . . . . . . . . . . . . . . . . . . . . . . . . 168
10.18 AHB bandwidth . . . . . . . . . . . . . . . . . . . . . . . 208
10.14 Module control register definitions . . . . . . . 168
10.18.1 DMA access. . . . . . . . . . . . . . . . . . . . . . . . . 208
10.14.1 Interrupt Status Register (IntStatus -
10.18.2 Types of CPU access. . . . . . . . . . . . . . . . . . 209
0x5000 0FE0) . . . . . . . . . . . . . . . . . . . . . . . . 168
10.18.3 Overall bandwidth . . . . . . . . . . . . . . . . . . . . 209
10.14.2 Interrupt Enable Register (IntEnable -
0x5000 0FE4) . . . . . . . . . . . . . . . . . . . . . . . . 169 10.19 CRC calculation. . . . . . . . . . . . . . . . . . . . . . . . 211
continued >>
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11.9.1 Power requirements . . . . . . . . . . . . . . . . . . . 218 11.10.5.4 USB Transmit Packet Length register
11.9.2 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 (USBTxPLen - 0x5000 C224) . . . . . . . . . . . 234
11.9.3 Power management support . . . . . . . . . . . . 219 11.10.5.5 USB Control register (USBCtrl - 0x5000
11.9.4 Remote wake-up . . . . . . . . . . . . . . . . . . . . . 220 C228) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
11.10 Register description . . . . . . . . . . . . . . . . . . . 220 11.10.6 SIE command code registers. . . . . . . . . . . . 234
11.10.1 Clock control registers . . . . . . . . . . . . . . . . . 221 11.10.6.1 USB Command Code register (USBCmdCode -
11.10.1.1 USB Clock Control register (USBClkCtrl - 0x5000 C210) . . . . . . . . . . . . . . . . . . . . . . . 235
0x5000 CFF4). . . . . . . . . . . . . . . . . . . . . . . . 221 11.10.6.2 USB Command Data register (USBCmdData -
11.10.1.2 USB Clock Status register (USBClkSt - 0x5000 0x5000 C214) . . . . . . . . . . . . . . . . . . . . . . . 235
CFF8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 11.10.7 DMA registers . . . . . . . . . . . . . . . . . . . . . . . 235
11.10.2 Device interrupt registers . . . . . . . . . . . . . . . 222 11.10.7.1 USB DMA Request Status register (USBDMARSt
11.10.2.1 USB Interrupt Status register (USBIntSt - - 0x5000 C250) . . . . . . . . . . . . . . . . . . . . . . 235
0x5000 C1C0) . . . . . . . . . . . . . . . . . . . . . . . 222 11.10.7.2 USB DMA Request Clear register (USBDMARClr
11.10.2.2 USB Device Interrupt Status register - 0x5000 C254) . . . . . . . . . . . . . . . . . . . . . . 236
(USBDevIntSt - 0x5000 C200). . . . . . . . . . . 223 11.10.7.3 USB DMA Request Set register (USBDMARSet -
11.10.2.3 USB Device Interrupt Enable register 0x5000 C258) . . . . . . . . . . . . . . . . . . . . . . . 236
(USBDevIntEn - 0x5000 C204) . . . . . . . . . . 224 11.10.7.4 USB UDCA Head register (USBUDCAH - 0x5000
11.10.2.4 USB Device Interrupt Clear register C280) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
(USBDevIntClr - 0x5000 C208) . . . . . . . . . . 224 11.10.7.5 USB EP DMA Status register (USBEpDMASt -
11.10.2.5 USB Device Interrupt Set register (USBDevIntSet 0x5000 C284) . . . . . . . . . . . . . . . . . . . . . . . 237
- 0x5000 C20C) . . . . . . . . . . . . . . . . . . . . . . 225 11.10.7.6 USB EP DMA Enable register (USBEpDMAEn -
11.10.2.6 USB Device Interrupt Priority register 0x5000 C288) . . . . . . . . . . . . . . . . . . . . . . . 238
(USBDevIntPri - 0x5000 C22C) . . . . . . . . . . 225 11.10.7.7 USB EP DMA Disable register (USBEpDMADis -
11.10.3 Endpoint interrupt registers. . . . . . . . . . . . . . 226 0x5000 C28C). . . . . . . . . . . . . . . . . . . . . . . 238
11.10.3.1 USB Endpoint Interrupt Status register 11.10.7.8 USB DMA Interrupt Status register (USBDMAIntSt
(USBEpIntSt - 0x5000 C230). . . . . . . . . . . . 226 - 0x5000 C290) . . . . . . . . . . . . . . . . . . . . . . 238
11.10.3.2 USB Endpoint Interrupt Enable register 11.10.7.9 USB DMA Interrupt Enable register
(USBEpIntEn - 0x5000 C234) . . . . . . . . . . . 227 (USBDMAIntEn - 0x5000 C294) . . . . . . . . . 239
11.10.3.3 USB Endpoint Interrupt Clear register 11.10.7.10 USB End of Transfer Interrupt Status register
(USBEpIntClr - 0x5000 C238) . . . . . . . . . . . 228 (USBEoTIntSt - 0x5000 C2A0) . . . . . . . . . . 239
11.10.3.4 USB Endpoint Interrupt Set register (USBEpIntSet 11.10.7.11 USB End of Transfer Interrupt Clear register
- 0x5000 C23C) . . . . . . . . . . . . . . . . . . . . . . 229 (USBEoTIntClr - 0x5000 C2A4) . . . . . . . . . 239
11.10.3.5 USB Endpoint Interrupt Priority register 11.10.7.12 USB End of Transfer Interrupt Set register
(USBEpIntPri - 0x5000 C240) . . . . . . . . . . . 229 (USBEoTIntSet - 0x5000 C2A8) . . . . . . . . . 240
11.10.4 Endpoint realization registers . . . . . . . . . . . . 230 11.10.7.13 USB New DD Request Interrupt Status register
11.10.4.1 EP RAM requirements . . . . . . . . . . . . . . . . . 230 (USBNDDRIntSt - 0x5000 C2AC) . . . . . . . . 240
11.10.4.2 USB Realize Endpoint register (USBReEp - 11.10.7.14 USB New DD Request Interrupt Clear register
0x5000 C244) . . . . . . . . . . . . . . . . . . . . . . . 230 (USBNDDRIntClr - 0x5000 C2B0) . . . . . . . 240
11.10.4.3 USB Endpoint Index register (USBEpIn - 0x5000 11.10.7.15 USB New DD Request Interrupt Set register
C248). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 (USBNDDRIntSet - 0x5000 C2B4) . . . . . . . 240
11.10.4.4 USB MaxPacketSize register (USBMaxPSize - 11.10.7.16 USB System Error Interrupt Status register
0x5000 C24C) . . . . . . . . . . . . . . . . . . . . . . . 232 (USBSysErrIntSt - 0x5000 C2B8) . . . . . . . . 241
11.10.5 USB transfer registers . . . . . . . . . . . . . . . . . 232 11.10.7.17 USB System Error Interrupt Clear register
11.10.5.1 USB Receive Data register (USBRxData - 0x5000 (USBSysErrIntClr - 0x5000 C2BC) . . . . . . . 241
C218). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 11.10.7.18 USB System Error Interrupt Set register
11.10.5.2 USB Receive Packet Length register (USBSysErrIntSet - 0x5000 C2C0). . . . . . . 241
(USBRxPLen - 0x5000 C220) . . . . . . . . . . . 233 11.11 Interrupt handling . . . . . . . . . . . . . . . . . . . . 241
11.10.5.3 USB Transmit Data register (USBTxData - 0x5000 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . 242
C21C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
continued >>
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continued >>
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
12.4.2 Software interface. . . . . . . . . . . . . . . . . . . . . 271 12.4.2.2 USB Host Register Definitions . . . . . . . . . . . 272
12.4.2.1 Register map . . . . . . . . . . . . . . . . . . . . . . . . 271
continued >>
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
continued >>
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
continued >>
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
16.14.2 Section configuration registers . . . . . . . . . . . 377 16.16.3 Set and clear mechanism of the FullCAN
16.14.3 Standard Frame Individual Start Address register interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
(SFF_sa - 0x4003 C004) . . . . . . . . . . . . . . . 378 16.16.3.1 Scenario 1: Normal case, no message lost . 388
16.14.4 Standard Frame Group Start Address register 16.16.3.2 Scenario 2: Message lost. . . . . . . . . . . . . . . 389
(SFF_GRP_sa - 0x4003 C008) . . . . . . . . . . 378 16.16.3.3 Scenario 3: Message gets overwritten indicated
16.14.5 Extended Frame Start Address register (EFF_sa - by Semaphore bits . . . . . . . . . . . . . . . . . . . . 390
0x4003 C00C) . . . . . . . . . . . . . . . . . . . . . . . 378 16.16.3.4 Scenario 3.1: Message gets overwritten indicated
16.14.6 Extended Frame Group Start Address register by Semaphore bits and Message Lost. . . . . 390
(EFF_GRP_sa - 0x4003 C010) . . . . . . . . . . 379 16.16.3.5 Scenario 3.2: Message gets overwritten indicated
16.14.7 End of AF Tables register (ENDofTable - by Message Lost . . . . . . . . . . . . . . . . . . . . . 391
0x4003 C014) . . . . . . . . . . . . . . . . . . . . . . . . 379 16.16.3.6 Scenario 4: Clearing Message Lost bit . . . . 392
16.14.8 Status registers . . . . . . . . . . . . . . . . . . . . . . . 379 16.17 Examples of acceptance filter tables and ID
16.14.9 LUT Error Address register (LUTerrAd - index values. . . . . . . . . . . . . . . . . . . . . . . . . . 393
0x4003 C018) . . . . . . . . . . . . . . . . . . . . . . . . 380 16.17.1 Example 1: only one section is used . . . . . . 393
16.14.10 LUT Error register (LUTerr - 0x4003 C01C) . 380 16.17.2 Example 2: all sections are used . . . . . . . . . 393
16.14.11 Global FullCANInterrupt Enable register (FCANIE 16.17.3 Example 3: more than one but not all sections are
- 0x4003 C020). . . . . . . . . . . . . . . . . . . . . . . 380 used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
16.14.12 FullCAN Interrupt and Capture registers 16.17.4 Configuration example 4 . . . . . . . . . . . . . . . 394
(FCANIC0 - 0x4003 C024 and FCANIC1 - 16.17.5 Configuration example 5 . . . . . . . . . . . . . . . 394
0x4003 C028) . . . . . . . . . . . . . . . . . . . . . . . . 380 16.17.6 Configuration example 6 . . . . . . . . . . . . . . . 395
16.15 Configuration and search algorithm . . . . . . 381 Explicit standard frame format identifier section
16.15.1 Acceptance filter search algorithm . . . . . . . . 381 (11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 396
16.16 FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . . 382 Group of standard frame format identifier section
16.16.1 FullCAN message layout . . . . . . . . . . . . . . . 384 (11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 396
16.16.2 FullCAN interrupts . . . . . . . . . . . . . . . . . . . . 386 Explicit extended frame format identifier section
16.16.2.1 FullCAN message interrupt enable bit . . . . . 386 (29-bit CAN ID, Figure 72) . . . . . . . . . . . . . . . 396
16.16.2.2 Message lost bit and CAN channel number . 387 Group of extended frame format identifier section
16.16.2.3 Setting the interrupt pending bits (IntPnd 63 to (29-bit CAN ID, Figure 72) . . . . . . . . . . . . . . . 396
0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 16.17.7 Configuration example 7 . . . . . . . . . . . . . . . 397
16.16.2.4 Clearing the interrupt pending bits (IntPnd 63 to FullCAN explicit standard frame format identifier
0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 section (11-bit CAN ID) . . . . . . . . . . . . . . . . . 398
16.16.2.5 Setting the message lost bit of a FullCAN Explicit standard frame format identifier section
message object (MsgLost 63 to 0) . . . . . . . . 388 (11-bit CAN ID) . . . . . . . . . . . . . . . . . . . . . . . 398
16.16.2.6 Clearing the message lost bit of a FullCAN FullCAN message object data section . . . . . . 398
message object (MsgLost 63 to 0) . . . . . . . . 388 16.17.8 Look-up table programming guidelines . . . . 399
continued >>
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continued >>
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
19.8.5 I2C Monitor mode control register (I2MMCTRL: 19.9.7.4 I2C-bus obstructed by a LOW level on SCL or
I2C0, I2C0MMCTRL - 0x4001 C01C; I2C1, SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
I2C1MMCTRL- 0x4005 C01C; I2C2, 19.9.7.5 Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
I2C2MMCTRL- 0x400A 001C) . . . . . . . . . . . 444 19.9.8 I2C state service routines . . . . . . . . . . . . . . . 465
19.8.5.1 Interrupt in Monitor mode . . . . . . . . . . . . . . . 445 19.9.8.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 465
19.8.5.2 Loss of arbitration in Monitor mode . . . . . . . 445 19.9.8.2 I2C interrupt service . . . . . . . . . . . . . . . . . . . 465
19.8.6 I2C Data buffer register (I2DATA_BUFFER: I2C0, 19.9.8.3 The state service routines . . . . . . . . . . . . . . 465
I2CDATA_BUFFER - 0x4001 C02C; I2C1, 19.9.8.4 Adapting state services to an application. . . 465
I2C1DATA_BUFFER- 0x4005 C02C; I2C2, 19.10 Software example . . . . . . . . . . . . . . . . . . . . . 466
I2C2DATA_BUFFER- 0x400A 002C) . . . . . . 446 19.10.1 Initialization routine . . . . . . . . . . . . . . . . . . . 466
19.8.7 I2C Slave Address registers (I2ADR0 to 3: I2C0, 19.10.2 Start Master Transmit function . . . . . . . . . . . 466
I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28]; 19.10.3 Start Master Receive function . . . . . . . . . . . 466
I2C1, I2C1ADR[0, 1, 2, 3] - address 19.10.4 I2C interrupt routine . . . . . . . . . . . . . . . . . . . 466
0x4005 C0[0C, 20, 24, 28]; I2C2, I2C2ADR[0, 1, 2, 19.10.5 Non mode specific states. . . . . . . . . . . . . . . 466
3] - address 0x400A 00[0C, 20, 24, 28]). . . . 446 19.10.5.1 State: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 466
19.8.8 I2C Mask registers (I2MASK0 to 3: I2C0, 19.10.5.2 Master States . . . . . . . . . . . . . . . . . . . . . . . . 467
I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C]; 19.10.5.3 State: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . 467
I2C1, I2C1MASK[0, 1, 2, 3] - address 19.10.5.4 State: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . 467
0x4005 C0[30, 34, 38, 3C]; I2C2, I2C2MASK[0, 1, 19.10.6 Master Transmitter states . . . . . . . . . . . . . . 467
2, 3] - address 0x400A 00[30, 34, 38, 3C]). . 447 19.10.6.1 State: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . 467
19.8.9 I2C SCL HIGH duty cycle register (I2SCLH: I2C0, 19.10.6.2 State: 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
I2C0SCLH - 0x4001 C010; I2C1, I2C1SCLH - 19.10.6.3 State: 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
0x4005 C010; I2C2, I2C2SCLH - 0x400A 19.10.6.4 State: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
0010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 19.10.6.5 State: 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
19.8.10 I2C SCL Low duty cycle register (I2SCLL: I2C0 - 19.10.7 Master Receive states . . . . . . . . . . . . . . . . . 468
I2C0SCLL: 0x4001 C014; I2C1 - I2C1SCLL: 19.10.7.1 State: 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
0x4005 C014; I2C2 - I2C2SCLL: 0x400A 19.10.7.2 State: 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . . 469
0014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 19.10.7.3 State: 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.8.11 Selecting the appropriate I2C data rate and duty 19.10.7.4 State: 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . 469
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 19.10.8 Slave Receiver states . . . . . . . . . . . . . . . . . 469
19.9 Details of I2C operating modes. . . . . . . . . . . 449 19.10.8.1 State: 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.9.1 Master Transmitter mode . . . . . . . . . . . . . . . 450 19.10.8.2 State: 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.9.2 Master Receiver mode . . . . . . . . . . . . . . . . . 452 19.10.8.3 State: 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.9.3 Slave Receiver mode . . . . . . . . . . . . . . . . . . 454 19.10.8.4 State: 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.9.4 Slave Transmitter mode . . . . . . . . . . . . . . . . 456 19.10.8.5 State: 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.9.5 Detailed state tables . . . . . . . . . . . . . . . . . . . 457 19.10.8.6 State: 0x88 . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.9.6 Miscellaneous states . . . . . . . . . . . . . . . . . . 462 19.10.8.7 State: 0x90 . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.9.6.1 I2STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . 462 19.10.8.8 State: 0x98 . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.9.6.2 I2STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . 462 19.10.8.9 State: 0xA0. . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.9.7 Some special cases . . . . . . . . . . . . . . . . . . . 462 19.10.9 Slave Transmitter states . . . . . . . . . . . . . . . 471
19.9.7.1 Simultaneous repeated START conditions from 19.10.9.1 State: 0xA8. . . . . . . . . . . . . . . . . . . . . . . . . . 471
two masters . . . . . . . . . . . . . . . . . . . . . . . . . 462 19.10.9.2 State: 0xB0. . . . . . . . . . . . . . . . . . . . . . . . . . 472
19.9.7.2 Data transfer after loss of arbitration . . . . . . 463 19.10.9.3 State: 0xB8. . . . . . . . . . . . . . . . . . . . . . . . . . 472
19.9.7.3 Forced access to the I2C-bus . . . . . . . . . . . . 463 19.10.9.4 State: 0xC0 . . . . . . . . . . . . . . . . . . . . . . . . . 472
19.10.9.5 State: 0xC8 . . . . . . . . . . . . . . . . . . . . . . . . . 472
continued >>
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20.5 Register description . . . . . . . . . . . . . . . . . . . 476 20.5.9 Transmit Clock Rate register (I2STXRATE -
20.5.1 Digital Audio Output register (I2SDAO - 0x400A 8020). . . . . . . . . . . . . . . . . . . . . . . . 479
0x400A 8000) . . . . . . . . . . . . . . . . . . . . . . . . 476 20.5.9.1 Notes on fractional rate generators . . . . . . . 480
20.5.2 Digital Audio Input register (I2SDAI - 20.5.10 Receive Clock Rate register (I2SRXRATE -
0x400A 8004) . . . . . . . . . . . . . . . . . . . . . . . . 477 0x400A 8024). . . . . . . . . . . . . . . . . . . . . . . . 480
20.5.3 Transmit FIFO register (I2STXFIFO - 20.5.11 Transmit Clock Bit Rate register (I2STXBITRATE
0x400A 8008) . . . . . . . . . . . . . . . . . . . . . . . . 477 - 0x400A 8028) . . . . . . . . . . . . . . . . . . . . . . 481
20.5.4 Receive FIFO register (I2SRXFIFO - 20.5.12 Receive Clock Bit Rate register (I2SRXBITRATE -
0x400A 800C). . . . . . . . . . . . . . . . . . . . . . . . 477 0x400A 802C) . . . . . . . . . . . . . . . . . . . . . . . 481
20.5.5 Status Feedback register (I2SSTATE - 20.5.13 Transmit Mode Control register (I2STXMODE -
0x400A 8010) . . . . . . . . . . . . . . . . . . . . . . . . 478 0x400A 8030). . . . . . . . . . . . . . . . . . . . . . . . 481
20.5.6 DMA Configuration Register 1 (I2SDMA1 - 20.5.14 Receive Mode Control register (I2SRXMODE -
0x400A 8014) . . . . . . . . . . . . . . . . . . . . . . . . 478 0x400A 8034). . . . . . . . . . . . . . . . . . . . . . . . 482
20.5.7 DMA Configuration Register 2 (I2SDMA2 - 20.6 I2S transmit and receive interfaces . . . . . . . 483
0x400A 8018) . . . . . . . . . . . . . . . . . . . . . . . . 479 20.7 I2S operating modes . . . . . . . . . . . . . . . . . . . 484
20.5.8 Interrupt Request Control register (I2SIRQ -
20.8 FIFO controller . . . . . . . . . . . . . . . . . . . . . . . 488
0x400A 801C). . . . . . . . . . . . . . . . . . . . . . . . 479
continued >>
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23.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 23.5.3 System Timer Current value register (STCURR -
23.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 0xE000 E018) . . . . . . . . . . . . . . . . . . . . . . . 506
23.5 Register description . . . . . . . . . . . . . . . . . . . 505 23.5.4 System Timer Calibration value register
(STCALIB - 0xE000 E01C) . . . . . . . . . . . . . 506
23.5.1 System Timer Control and status register
(STCTRL - 0xE000 E010) . . . . . . . . . . . . . . 505 23.6 Example timer calculations . . . . . . . . . . . . . 508
23.5.2 System Timer Reload value register (STRELOAD Example 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 508
- 0xE000 E014). . . . . . . . . . . . . . . . . . . . . . . 506 Example 2). . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Example 3). . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Example 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 508
continued >>
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25.7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 25.7.10.2 MCPWM Capture clear address (MCCAP_CLR -
0x400B 8024, 0x400B 8028, 0x400B 802C) 533 0x400B 8074). . . . . . . . . . . . . . . . . . . . . . . . 536
25.7.6.1 Match and Limit write and operating registers 533 25.8 PWM operation . . . . . . . . . . . . . . . . . . . . . . . 537
25.7.7 MCPWM Match 0-2 registers (MCMAT0-2 - 25.8.1 Pulse-width modulation . . . . . . . . . . . . . . . . 537
0x400B 8030, 0x400B 8034, 0x400B 8038) . 534 Edge-aligned PWM without dead-time. . . . . . 537
25.7.7.1 Match register in Edge-Aligned mode. . . . . . 534 Center-aligned PWM without dead-time . . . . 537
25.7.7.2 Match register in Center-Aligned mode . . . . 534 Dead-time counter . . . . . . . . . . . . . . . . . . . . . 538
25.7.7.3 0 and 100% duty cycle . . . . . . . . . . . . . . . . . 534 25.8.2 Shadow registers and simultaneous updates 539
25.7.8 MCPWM Dead-time register (MCDT - 25.8.3 Fast Abort (ABORT). . . . . . . . . . . . . . . . . . . 539
0x400B 803C). . . . . . . . . . . . . . . . . . . . . . . . 535 25.8.4 Capture events. . . . . . . . . . . . . . . . . . . . . . . 539
25.7.9 MCPWM Commutation Pattern register (MCCP - 25.8.5 External event counting (Counter mode) . . . 540
0x400B 8040) . . . . . . . . . . . . . . . . . . . . . . . . 535 25.8.6 Three-phase DC mode . . . . . . . . . . . . . . . . 540
25.7.10 MCPWM Capture Registers . . . . . . . . . . . . . 536 25.8.7 Three phase AC mode. . . . . . . . . . . . . . . . . 541
25.7.10.1 MCPWM Capture read addresses (MCCAP0-2 - 25.8.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
0x400B 8044, 0x400B 8048, 0x400B 804C) 536
continued >>
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continued >>
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30.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 582 30.4.3 D/A Converter Counter Value register
30.4 Register description . . . . . . . . . . . . . . . . . . . 583 (DACCNTVAL - 0x4008 C008). . . . . . . . . . . 584
30.4.1 D/A Converter Register (DACR - 0x4008 30.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 30.5.1 DMA counter . . . . . . . . . . . . . . . . . . . . . . . . 584
30.4.2 D/A Converter Control register (DACCTRL - 30.5.2 Double buffering. . . . . . . . . . . . . . . . . . . . . . 584
0x4008 C004) . . . . . . . . . . . . . . . . . . . . . . . . 583
continued >>
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Chapter 33: LPC17xx JTAG, Serial Wire Debug (SWD), and Trace
33.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 33.5 Debug Notes . . . . . . . . . . . . . . . . . . . . . . . . . 642
33.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 641 33.6 Debug memory re-mapping . . . . . . . . . . . . . 643
33.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 33.6.1 Memory Mapping Control register (MEMMAP -
33.4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . 641 0x400F C040) . . . . . . . . . . . . . . . . . . . . . . . 643
continued >>
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continued >>
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
continued >>
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
continued >>
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
34.3.1.6 The Cortex Microcontroller Software Interface 34.4.2.5 Interrupt Clear-pending Registers . . . . . . . . 762
Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 34.4.2.6 Interrupt Active Bit Registers . . . . . . . . . . . . 763
34.3.2 Memory model . . . . . . . . . . . . . . . . . . . . . . . 737 34.4.2.7 Interrupt Priority Registers . . . . . . . . . . . . . . 763
34.3.2.1 Memory regions, types and attributes. . . . . . 737 34.4.2.8 Software Trigger Interrupt Register . . . . . . . 764
34.3.2.2 Memory system ordering of memory 34.4.2.9 Level-sensitive and pulse interrupts. . . . . . . 764
accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 34.4.2.9.1 Hardware and software control of interrupts 765
34.3.2.3 Behavior of memory accesses . . . . . . . . . . . 739 34.4.2.10 NVIC design hints and tips. . . . . . . . . . . . . . 765
34.3.2.4 Software ordering of memory accesses . . . . 739 34.4.2.10.1 NVIC programming hints . . . . . . . . . . . . . . 766
34.3.2.5 Bit-banding . . . . . . . . . . . . . . . . . . . . . . . . . . 740 34.4.3 System control block . . . . . . . . . . . . . . . . . . 767
34.3.2.5.1 Directly accessing an alias region . . . . . . . . 742 34.4.3.1 The CMSIS mapping of the Cortex-M3 SCB
34.3.2.5.2 Directly accessing a bit-band region. . . . . . . 742 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
34.3.2.6 Memory endianness . . . . . . . . . . . . . . . . . . . 743 34.4.3.2 Auxiliary Control Register . . . . . . . . . . . . . . 767
34.3.2.6.1 Little-endian format. . . . . . . . . . . . . . . . . . . . 743 34.4.3.2.1 About IT folding . . . . . . . . . . . . . . . . . . . . . . 768
34.3.2.7 Synchronization primitives . . . . . . . . . . . . . . 743 34.4.3.3 CPUID Base Register . . . . . . . . . . . . . . . . . 768
34.3.2.8 Programming hints for the synchronization 34.4.3.4 Interrupt Control and State Register . . . . . . 768
primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 34.4.3.5 Vector Table Offset Register . . . . . . . . . . . . 770
34.3.3 Exception model . . . . . . . . . . . . . . . . . . . . . . 745 34.4.3.6 Application Interrupt and Reset Control
34.3.3.1 Exception states . . . . . . . . . . . . . . . . . . . . . . 745 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
34.3.3.2 Exception types . . . . . . . . . . . . . . . . . . . . . . 745 34.4.3.6.1 Binary point . . . . . . . . . . . . . . . . . . . . . . . . . 772
34.3.3.3 Exception handlers . . . . . . . . . . . . . . . . . . . . 747 34.4.3.7 System Control Register . . . . . . . . . . . . . . . 772
34.3.3.4 Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . 748 34.4.3.8 Configuration and Control Register . . . . . . . 773
34.3.3.5 Exception priorities . . . . . . . . . . . . . . . . . . . . 748 34.4.3.9 System Handler Priority Registers . . . . . . . . 774
34.3.3.6 Interrupt priority grouping . . . . . . . . . . . . . . . 749 34.4.3.9.1 System Handler Priority Register 1 . . . . . . . 775
34.3.3.7 Exception entry and return . . . . . . . . . . . . . . 749 34.4.3.9.2 System Handler Priority Register 2 . . . . . . . 775
34.3.3.7.1 Exception entry. . . . . . . . . . . . . . . . . . . . . . . 750 34.4.3.9.3 System Handler Priority Register 3 . . . . . . . 775
34.3.3.7.2 Exception return . . . . . . . . . . . . . . . . . . . . . . 751 34.4.3.10 System Handler Control and State Register 775
34.3.4 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . 753 Caution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
34.3.4.1 Fault types . . . . . . . . . . . . . . . . . . . . . . . . . . 753 34.4.3.11 Configurable Fault Status Register . . . . . . . 777
34.3.4.2 Fault escalation and hard faults . . . . . . . . . . 754 34.4.3.11.1 Memory Management Fault Status Register 777
34.3.4.3 Fault status registers and fault address 34.4.3.11.2 Bus Fault Status Register. . . . . . . . . . . . . . 778
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 34.4.3.11.3 Usage Fault Status Register . . . . . . . . . . . 779
34.3.4.4 Lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 34.4.3.12 Hard Fault Status Register. . . . . . . . . . . . . . 781
34.3.5 Power management . . . . . . . . . . . . . . . . . . . 756 34.4.3.13 Memory Management Fault Address
34.3.5.1 Entering sleep mode. . . . . . . . . . . . . . . . . . . 756 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
34.3.5.1.1 Wait for interrupt . . . . . . . . . . . . . . . . . . . . . . 756 34.4.3.14 Bus Fault Address Register . . . . . . . . . . . . . 781
34.3.5.1.2 Wait for event . . . . . . . . . . . . . . . . . . . . . . . . 756 34.4.3.15 System control block design hints and tips . 782
34.3.5.1.3 Sleep-on-exit . . . . . . . . . . . . . . . . . . . . . . . . 757 34.4.4 System timer, SysTick . . . . . . . . . . . . . . . . . 783
34.3.5.2 Wakeup from sleep mode. . . . . . . . . . . . . . . 757 34.4.4.1 SysTick Control and Status Register . . . . . . 783
34.3.5.2.1 Wakeup from WFI or sleep-on-exit. . . . . . . . 757 34.4.4.2 SysTick Reload Value Register . . . . . . . . . . 784
34.3.5.2.2 Wakeup from WFE . . . . . . . . . . . . . . . . . . . . 757 34.4.4.2.1 Calculating the RELOAD value . . . . . . . . . . 784
34.3.5.3 The Wake-up Interrupt Controller . . . . . . . . . 757 34.4.4.3 SysTick Current Value Register . . . . . . . . . . 784
34.3.5.4 Power management programming hints. . . . 758 34.4.4.4 SysTick Calibration Value Register . . . . . . . 784
34.4 ARM Cortex-M3 User Guide: Peripherals . . 759 34.4.4.5 SysTick design hints and tips. . . . . . . . . . . . 785
34.4.1 About the Cortex-M3 peripherals . . . . . . . . . 759 34.4.5 Memory protection unit . . . . . . . . . . . . . . . . 786
34.4.2 Nested Vectored Interrupt Controller . . . . . . 760 34.4.5.1 MPU Type Register . . . . . . . . . . . . . . . . . . . 787
34.4.2.1 The CMSIS mapping of the Cortex-M3 NVIC 34.4.5.2 MPU Control Register . . . . . . . . . . . . . . . . . 788
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 34.4.5.3 MPU Region Number Register . . . . . . . . . . 789
34.4.2.2 Interrupt Set-enable Registers . . . . . . . . . . . 761 34.4.5.4 MPU Region Base Address Register. . . . . . 789
34.4.2.3 Interrupt Clear-enable Registers. . . . . . . . . . 761 34.4.5.4.1 The ADDR field . . . . . . . . . . . . . . . . . . . . . . 790
34.4.2.4 Interrupt Set-pending Registers . . . . . . . . . . 762 34.4.5.5 MPU Region Attribute and Size Register. . . 790
34.4.5.5.1 SIZE field values . . . . . . . . . . . . . . . . . . . . . 791
continued >>
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34.4.5.6 MPU access permission attributes . . . . . . . . 792 34.4.5.8.2 Updating an MPU region using multi-word
34.4.5.7 MPU mismatch . . . . . . . . . . . . . . . . . . . . . . . 793 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
34.4.5.8 Updating an MPU region . . . . . . . . . . . . . . . 793 34.4.5.8.3 Subregions. . . . . . . . . . . . . . . . . . . . . . . . . . 795
34.4.5.8.1 Updating an MPU region using separate 34.4.5.9 MPU design hints and tips . . . . . . . . . . . . . . 796
words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 34.4.5.9.1 MPU configuration for a microcontroller . . . 796
34.5 ARM Cortex-M3 User Guide: Glossary . . . . 797
840 Please be aware that important notices concerning this document and the product(s)
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