Datasheet

VCS Xprop
Increasing the Efficiency of X-related Simulation and Debug

Overview VCS Xprop

Verilog and VHDL are commonly used VCS® Xprop is designed to help find X-related issues at RTL and reduce the
to model digital designs. Designers use requirement for lengthy gate-level simulations. The simulation semantics of
RTL constructs to describe hardware conditional constructs in both HDL languages, Verilog and VHDL, are insufficient
behaviors. However, certain RTL to accurately model the ambiguity inherent in un-initialized registers and power-
simulation semantics are insufficient to on reset values. These issues are particularly problematic when the indeterminate
accurately model hardware behavior. states that are modeled as ‘X’ values become control expressions.
Therefore, simulation results are One of the most common sources of simulation differences highlighted when VCS Xprop
either too optimistic or pessimistic as is enabled is incorrect initialization sequences. The behavior is typically caused by a
compared to actual hardware behavior. reset or clock signal transitioning from 0 to X, 1 to X or vice-versa. If a flip-flop is sensitive
Verilog and VHDL RTL simulators to the rising edge of its clock signal, an X to 1 transition will trigger the flip-flop and pass
ignore the uncertainty of X-valued the value from input to output when coded using the Verilog posedge or the traditional
control signals and assign predictable VHDL flip-flop behavioral code: clk’event and clk’1’. Conversely, if the flip-flop is
output values because of these coded using the VHDL rising_edge(event) construct, the flip-flop will not load a new
semantic limitations. As a result, value. Effectively, the Verilog construct as well as one VHDL construct consider the X to 1
RTL simulations often fail to detect transition as true while the other VHDL construct considers it as false. However, in a VCS
design problems related to the lack Xprop simulation, the same clock transition will cause the flip-flop to merge the input and
of X-propagation. However, these output, possibly resulting in an unknown value. Hence, to effectively load new values
same design problems can be detected onto a flip-flop, you must ensure that clock signals have valid and stable values, which
in gate-level simulations, and often will be shown in RTL run through a VCS Xprop-enabled simulation.
many gate-level simulations must be RTL simulation (Verilog semantics)
run only to debug X-related issues.
Missing reset
With the new X-propagation support
if (a)
at RTL in VCS®, engineers can now a b = 0; b

save time and effort debugging X else

1
X b =1;
differences in X-modeling between
RTL and gate-level simulation results.
X-Prop simulation
Missing reset

if (a)
a b
b = 0;
X else X
X b =1;

Figure 1: Verilog Semantics with and without VCS Xprop

VCS Xprop Scope and Support RTL native low power simulation (Verilog semantics)
VCS Xprop is user-controllable in scope Top domain (always on)
allowing partial instrumentation of
Missing ISO Corruption value from native low power
the design. A user can also configure X X simulation showing missing ISO policy is
Power Power 1 masked by RTL semantics
VCS Xprop to user different merge domain 1 domain 2
X 0
algorithms (providing support more or OFF ISO ON 0 RTL native low power simulation-inferred
isolation is properly blocking corruption
less pessimistic semantics). VCS Xprop value from OFF domain
Power
works with all testbench and high-level management unit

description languages supported

by VCS (SystemVerilog, SystemC/ RTL native low power simulation with VCS Xprop
C++ and VHDL). VCS technologies Top domain (always on)
including coverage, debug, and native
Missing ISO Corruption value from native low power
low power are also supported with a X X simulation showing missing ISO policy is
Power Power properly propagated by VCS Xprop semantics
X
VCS Xprop simulation as well as VCS domain 1
X
domain 2
0
in co-simulation mode including AMS OFF ISO ON 0 RTL native low power simulation-inferred
isolation is properly blocking corruption
co-simulation. value from OFF domain
Power
management unit
VCS Xprop Debug
When a bug is found in VCS Xprop-
Figure 2: VCS native low power simulation with and without VCS Xprop enabled
enabled simulations, the user may
still dump waveforms. Debugging an
X-related simulation mismatch actually
becomes easier at RTL rather than at
gate level because RTL descriptions are
closer to the actual functional intent of
a circuit. There are different methods
to debug RTL simulation failures, but
typically, when VCS Xprop is enabled,
the regression is run, a regression or
test failure is identified, the test is rerun
with waveform dumping enabled, the
user goes to the point of test failure
(usually identified by an assertion or
monitor failure), and the user leverages
signal tracing to identify the origin of the
X and root cause the problem.
Figure 3: X-tracing a VCS Xprop-enabled simulation in Verdi3™
VCS Xprop Improves the
Efficiency of X-related Debug
VCS Xprop has been shown to be additional tools or recoding required. For more information about Synopsys
effective on dozens of commercial Please contact your account team for products, support services or
designs and has been in production more information. training, visit us on the web at:
since 2010. VCS Xprop provides a www.synopsys.com, contact your
methodology to debug X-related Synopsys Verification local sales representative or call
issues quickly in large designs with no See the complete list of verification 650.584.5000.
solutions at http://www.synopsys.com/
verification/.

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07/13.AP.CS2340.