SN54LVC74A, SN74LVC74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET
www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005

FEATURES • Latch-Up Performance Exceeds 250 mA Per

• Operate From 1.65 V to 3.6 V JESD 17
• Inputs Accept Voltages to 5.5 V • ESD Protection Exceeds JESD 22
• Max tpd of 5.2 ns at 3.3 V – 2000-V Human-Body Model (A114-A)
• Typical VOLP (Output Ground Bounce) – 200-V Machine Model (A115-A)
<0.8 V at VCC = 3.3 V, TA = 25°C – 1000-V Charged-Device Model (C101)
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
SN54LVC74A . . . J OR W PACKAGE SN74LVC74A . . . RGY PACKAGE SN54LVC74A . . . FK PACKAGE
SN74LVC74A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW)
(TOP VIEW)

1CLR

1CLR

2CLR
VCC

VCC
NC
1D
1CLR 1 14 VCC
1D 2 13 2CLR 1 14
3 2 1 20 19
1CLK 3 12 2D 1D 2 13 2CLR 1CLK 4 18 2D
1PRE 4 11 2CLK 1CLK 3 12 2D NC 5 17 NC
1Q 5 10 2PRE 1PRE 4 11 2CLK 1PRE 6 16 2CLK
1Q 6 9 2Q 1Q 5 10 2PRE NC 7 15 NC
7 8 1Q 6 9 2Q 1Q 8 14 2PRE
GND 2Q
7 8 9 10 11 12 13
GND

2Q

GND
NC
1Q

2Q
2Q
NC - No internal connection

DESCRIPTION/ORDERING INFORMATION
The SN54LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and
the SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.

ORDERING INFORMATION
TA PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGY Reel of 1000 SN74LVC74ARGYR LC74A
Tube of 50 SN74LVC74AD
SOIC – D Reel of 2500 SN74LVC74ADR LVC74A
Reel of 250 SN74LVC74ADT
–40°C to 85°C SOP – NS Reel of 2000 SN74LVC74ANSR LCV74A
SSOP – DB Reel of 2000 SN74LVC74ADBR LC74A
Tube of 90 SN74LVC74APW
TSSOP – PW Reel of 2000 SN74LVC74APWR LC74A
Reel of 250 SN74LVC74APWT
CDIP – J Tube of 25 SNJ54LVC74AJ SNJ54LVC74AJ
–55°C to 125°C CFP – W Tube of 150 SNJ54LVC74AW SNJ54LVC74AW
LCCC – FK Tube of 55 SNJ54LVC74AFK SNJ54LVC74AFK

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 1993–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters. processing does not necessarily include testing of all parameters.
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET www.ti.com
SCAS287S – JANUARY 1993 – REVISED MAY 2005

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of these devices for
down-translation in a mixed-voltage environment.

FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H (1) H (1)
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q0

(1) This configuration is nonstable; that is, it does not persist when
PRE or CLR returns to its inactive (high) level.

LOGIC DIAGRAM, EACH FLIP-FLOP

(POSITIVE LOGIC)
PRE

CLK C C

C
Q
TG

C C C

D TG TG TG

Q
C C C
CLR

2
 SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
www.ti.com
WITH CLEAR AND PRESET
SCAS287S – JANUARY 1993 – REVISED MAY 2005
(1)
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VI Input voltage range (2) –0.5 6.5 V
VO Output voltage range (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
D package (4) 86
DB package (4) 96
θJA Package thermal impedance NS package (4) 76 °C/W
PW package (4) 113
RGY package (5) 47
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.

Recommended Operating Conditions (1)

SN54LVC74A SN74LVC74A
UNIT
MIN MAX MIN MAX
Operating 2 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8
VI Input voltage 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current mA
VCC = 2.7 V –12 –12
VCC = 3 V –24 –24
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current mA
VCC = 2.7 V 12 12
VCC = 3 V 24 24
∆t/∆v Input transition rise or fall rate 10 10 ns/V
TA Operating free-air temperature –55 125 –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

3
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET www.ti.com
SCAS287S – JANUARY 1993 – REVISED MAY 2005

Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC74A SN74LVC74A
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP (1) MAX MIN TYP (1) MAX
1.65 V to 3.6 V VCC – 0.2
IOH = –100 µA
2.7 V to 3.6 V VCC – 0.2
IOH = –4 mA 1.65 V 1.2
VOH IOH = –8 mA 2.3 V 1.7 V
2.7 V 2.2 2.2
IOH = –12 mA
3V 2.4 2.4
IOH = –24 mA 3V 2.2 2.2
1.65 V to 3.6 V 0.2
IOL = 100 µA
2.7 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
VOL V
IOL = 8 mA 2.3 V 0.7
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3V 0.55 0.55
II VI = 5.5 V or GND 3.6 V ±5 ±5 µA
ICC VI = VCC or GND, IO = 0 3.6 V 10 10 µA
One input at VCC – 0.6 V,
∆ICC 2.7 V to 3.6 V 500 500 µA
Other inputs at VCC or GND
Ci VI = VCC or GND 3.3 V 5 5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC74A
VCC = 3.3 V
VCC = 2.7 V UNIT
± 0.3 V
MIN MAX MIN MAX
fclock Clock frequency 83 100 MHz
PRE or CLR low 3.3 3.3
tw Pulse duration ns
CLK high or low 3.3 3.3
Data 3.4 3
tsu Setup time before CLK↑ ns
PRE or CLR inactive 2.2 2
th Hold time, data after CLK↑ 1 1 ns

4
 SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
www.ti.com
WITH CLEAR AND PRESET
SCAS287S – JANUARY 1993 – REVISED MAY 2005

Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
VCC = 2.7 V UNIT
± 0.15 V ± 0.2 V ± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 83 83 83 150 MHz
PRE or CLR low 4.1 3.3 3.3 3.3
tw Pulse duration ns
CLK high or low 4.1 3.3 3.3 3.3
Data 3.6 2.3 3.4 3
tsu Setup time before CLK↑ ns
PRE or CLR inactive 2.7 1.9 2.2 2
th Hold time, data after CLK↑ 1 1 1 0 ns

Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC74A
FROM TO VCC = 3.3 V
PARAMETER VCC = 2.7 V UNIT
(INPUT) (OUTPUT) ± 0.3 V
MIN MAX MIN MAX
fmax 83 100 MHz
CLK 6 1 5.2
tpd Q or Q ns
PRE or CLR 6.4 1 5.4

Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER VCC = 2.7 V UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 83 83 83 150 MHz
CLK 1 7.1 1 4.4 1 6 1 5.2
tpd Q or Q ns
PRE or CLR 1 6.9 1 4.6 1 6.4 1 5.4
tsk(o) 1 ns

Operating Characteristics
TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP
Cpd Power dissipation capacitance per flip-flop f = 10 MHz 24 24 26 pF

5
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET www.ti.com
SCAS287S – JANUARY 1993 – REVISED MAY 2005

PARAMETER MEASUREMENT INFORMATION

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH - V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6
 PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
5962-9761601Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9761601QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-9761601QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
5962-9761601V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9761601VCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-9761601VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN74LVC74AD ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74LVC74ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ADE4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ADG4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ADR ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ADT ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ADTE4 ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ANSR ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74APW ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74LVC74APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74APWT ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
SN74LVC74APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC74ARGYR ACTIVE QFN RGY 14 1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SN74LVC74ARGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SNJ54LVC74AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LVC74AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SNJ54LVC74AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

NO. OF A B
18 17 16 15 14 13 12
TERMINALS
** MIN MAX MIN MAX

0.342 0.358 0.307 0.358

19 11 20
(8,69) (9,09) (7,80) (9,09)
20 10 0.442 0.458 0.406 0.458
28
(11,23) (11,63) (10,31) (11,63)
21 9
B SQ 0.640 0.660 0.495 0.560
22 8 44
(16,26) (16,76) (12,58) (14,22)
A SQ
23 7 0.739 0.761 0.495 0.560
52
(18,78) (19,32) (12,58) (14,22)
24 6
0.938 0.962 0.850 0.858
68
(23,83) (24,43) (21,6) (21,8)
25 5
1.141 1.165 1.047 1.063
84
(28,99) (29,59) (26,6) (27,0)
26 27 28 1 2 3 4

0.020 (0,51) 0.080 (2,03)

0.010 (0,25) 0.064 (1,63)

0.020 (0,51)
0.010 (0,25)

0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)

0.028 (0,71) 0.045 (1,14)

0.022 (0,54) 0.035 (0,89)
0.050 (1,27)

4040140 / D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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