Nothing Special   »   [go: up one dir, main page]
Scribd Logo
Upload

Welcome to Scribd!

  • 91 views

    Compal Confidential: Schematic Document

    Uploaded by

    WILLPC369
    This document is a cover sheet for a schematic document from Compal Electronics, Inc. dated September 10, 2009. It contains confidential information and trade secrets regarding a mobile penym LV/ULV dual core model named NAT20. The document outlines various components on the motherboard including the CPU, memory, chipsets, ports and connections.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Compal Confidential: Schematic Document

    Uploaded by

    WILLPC369
    91 views43 pages
    This document is a cover sheet for a schematic document from Compal Electronics, Inc. dated September 10, 2009. It contains confidential information and trade secrets regarding a mobile penym LV/ULV dual core model named NAT20. The document outlines various components on the motherboard including the CPU, memory, chipsets, ports and connections.

    Original Description:

    Original Title

    1370 La-5541P

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document is a cover sheet for a schematic document from Compal Electronics, Inc. dated September 10, 2009. It contains confidential information and trade secrets regarding a mobile penym LV/ULV dual core model named NAT20. The document outlines various components on the motherboard including the CPU, memory, chipsets, ports and connections.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    91 views43 pages

    Compal Confidential: Schematic Document

    Uploaded by

    WILLPC369
    This document is a cover sheet for a schematic document from Compal Electronics, Inc. dated September 10, 2009. It contains confidential information and trade secrets regarding a mobile penym LV/ULV dual core model named NAT20. The document outlines various components on the motherboard including the CPU, memory, chipsets, ports and connections.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 43

    A B C D E

    1 1

    Compal Confidential
    2 2

    Schematic Document
    Rev: 1.0
    3

    2009.09.10 3

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cover Sheet
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 1 of 43
    A B C D E
    A B C D E

    Compal Confidential Mobile Penym


    LV/ULV Dual Core Thermal Sensor Clock Generator
    Fan Control
    Model Name : NAT20 page 31
    EMC 1402 ICS9LPRS387
    uFCPGA-956 CPU - SFF page 4 page 16

    page 4,5,6,7
    1 1
    FSB
    800MHz/1066MHz
    HDMI Conn. LCD Conn.
    page 17 page 19
    Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
    Intel Cantiga GS
    LVDS Dual Channel BANK 0, 1, 2, 3 page 14,15

    HDMI TMDS FCBGA 1363 - SFF 1.5V DDRIII 800/1066

    Level Shift page 8,9,10,11,12,13


    page 17

    DMI C-Link

    PCI-Express
    2
    Intel ICH9-M 3.3V 48MHz USB
    2

    Port0 USB conn


    page 28
    1.5V 24.576MHz/48Mhz HD Audio
    SATA WBMMAP-569 - SFF
    Port1
    LAN(GbE) BTB Conn. USB conn
    page 20,21,22,23 page 27
    RTL 8111DL
    page 25 page 27 GMCH HDA Small Board Port2
    Conn. page 27 USB conn
    page 08 page 27

    MINI Card x1 port 1 port 0


    RJ45 WLAN DVD-ROM SATA HDD Port3 Card Reader
    page 25 HDA Codec page 26
    Conn. page 24
    Conn. page 24 ALC272
    LPC BUS Port4
    Camera
    3
    page 19 3

    ENE KB926
    Port5
    page 29 Audio AMP HeadPhone Jack x1 WLAN
    page 27

    Touch Pad Int.KBD Port6


    page 30
    WWAN
    page 30 page 27
    RTC Conn. Speaker 2W X 2
    page 33
    BIOS Port7
    SPI Blue Tooth
    page 29 page 27

    POWER SW
    Power On/Off CKT.
    page 31
    LS-5541P
    4
    DC/DC Interface CKT. USB + AUDIO/B 4

    USB port 1, USB Port 2


    page 32
    LS-5542P

    Power Circuit DC/DC SIM/B Conn. Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title
    page 34~41 Block Diagram
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 2 of 43
    A B C D E
    A

    Board ID Table for AD channel


    Vcc 3.3V +/- 5% BOARD ID Table
    Ra 100K +/- 5%
    Board ID Rb V AD_BID min V AD_BID typ V AD_BID max Board ID PCB Revision
    0 0 0 V 0 V 0 V 0 0.1
    1 18K +/- 5% 0.436 V 0.503 V 0.538 V 1 0.2 Symbol Note :
    2 33K +/- 5% 0.712 V 0.819 V 0.875 V 2 0.3
    3 56K +/- 5% 1.036 V 1.185 V 1.264 V 3 0.4
    : means Digital Ground
    4 100K +/- 5% 1.453 V 1.650 V 1.759 V 4
    5 200K +/- 5% 1.935 V 2.200 V 2.341 V 5
    6 NC 2.500 V 3.300 V 3.300 V 6
    : means Analog Ground
    7 7

    SMBUS Control Table

    THERMAL
    SERIAL SENSOR
    SOURCE INVERTER BATT EEPROM (CPU) SODIMM

    EC_SMB_CK1
    EC_SMB_DA1
    KB926 X V X X X
    EC_SMB_CK2
    EC_SMB_DA2
    KB926 X X X V X
    ICH_SMBCLK
    ICH_SMBDATA ICH9 X X X X V I2C / SMBUS ADDRESSING
    MCP_SMB_CLK DEVICE HEX ADDRESS
    MCP_SMB_DATA ICH9
    X X X X X
    1
    DDR SO-DIMM 0 A0 10100000 1

    DDR SO-DIMM 1 A4 10100100


    MINI CARD 1 RESERVED +3VALW TO PULL HIGH
    CLOCK GENERATOR (EXT.) D2 11010010

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Notes List
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 3 of 43
    A
    5 4 3 2 1

    XDP_TDI +VCCP

    XDP_TMS
    XDP_TDI R1 1 2 54.9_0402_1%
    XDP_TDO
    XDP_TMS R2 1 2 54.9_0402_1%
    XDP_BPM#5
    XDP_TDO R3 1 2 54.9_0402_1%
    XDP_DBRESET#
    D XDP_BPM#5 R4 54.9_0402_1% D
    1 2
    XDP_TRST#

    XDP_TCK
    XDP_TRST# R6 1 2 51_0402_1%
    +VCCP

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    Place close to U1. 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @
    XDP_TCK R7 1 2 54.9_0402_1%
    C1058 C1059 C1060 C1061 C1062 C1063 C1064
    8 H_A#[3..16] This shall place near CPU
    U1A
    H_A#3 2 2 2 2 2 2 2
    P2 A[3]# ADS# M4 H_ADS# 8
    H_A#4 V4 J5
    A[4]# BNR# H_BNR# 8
    H_A#5 W1 L5
    A[5]# BPRI# H_BPRI# 8

    2
    56_0402_5%
    H_A#6 T4 @
    A[6]#

    ADDR GROUP 0
    H_A#7 AA1 N5 R10
    A[7]# DEFER# H_DEFER# 8
    H_A#8 AB4 F38 51_0402_1%
    A[8]# DRDY# H_DRDY# 8
    H_A#9 T2 J1
    A[9]# DBSY# H_DBSY# 8 For EMI

    R9
    H_A#10 AC5 9/20

    1
    A[10]#

    CONTROL
    H_A#11 AD2 M2
    A[11]# BR0# H_BR0# 8
    H_A#12 AD4
    H_A#13 A[12]#
    AA5 A[13]# IERR# B40
    H_A#14 AE5 D8
    A[14]# INIT# H_INIT# 21
    H_A#15 AB2
    H_A#16 A[15]#
    AC1 A[16]# LOCK# N1 H_LOCK# 8
    8 H_ADSTB#0 Y4 ADSTB[0]#
    G5 H_RESET#
    RESET# H_RESET# 8
    8 H_REQ#0 R1 REQ[0]# RS[0]# K2 H_RS#0 8

    0.1U_0402_16V4Z
    8 H_REQ#1 R5 REQ[1]# RS[1]# H4 H_RS#1 8 1
    8 H_REQ#2 U1 REQ[2]# RS[2]# K4 H_RS#2 8
    P4 L1 C1046 @
    8 H_REQ#3 REQ[3]# TRDY# H_TRDY# 8
    8 H_REQ#4 W5 REQ[4]#
    H2
    2 For EMI
    8 H_A#[17..35] HIT# H_HIT# 8
    H_A#17 AN1 F2
    C A[17]# HITM# H_HITM# 8 C
    H_A#18 AK4 Add 0 ohm per EMI request.
    H_A#19 A[18]#
    AG1 AY8
    A[19]# BPM[0]# T149 10/17 +3VS
    ADDR GROUP 1

    H_A#20 AT4 BA7


    A[20]# BPM[1]# T150
    H_A#21 AK2 BA5
    A[21]# BPM[2]# T151
    H_A#22 AT2 AY2 R14
    A[22]# BPM[3]# T152
    H_A#23 AH2 AV10 0_0402_5%
    XDP/ITP SIGNALS

    A[23]# PRDY# T153

    0.1U_0402_16V4Z
    H_A#24 AF4 AV2 XDP_BPM#5_R 1 2 XDP_BPM#5 1
    H_A#25 A[24]# PREQ# XDP_TCK
    AJ5 A[25]# TCK AV4
    H_A#26 AH4 AW7 XDP_TDI C1034
    H_A#27 A[26]# TDI XDP_TDO U7
    AM4 A[27]# TDO AU1
    H_A#28 XDP_TMS 2
    AP4 A[28]# TMS AW5
    H_A#29 AR5 AV8 XDP_TRST#
    H_A#30 A[29]# TRST# XDP_DBRESET#
    AJ1 A[30]# DBR# J7 XDP_DBRESET# 22 1 VDD SMCLK 8 EC_SMB_CK2 29
    H_A#31 AL1 A[31]# H_PROCHOT# 39
    H_A#32 AM2 H_THERMDA 2 7
    A[32]# +VCCP DP SMDATA EC_SMB_DA2 29
    H_A#33 AU5 A[33]# THERMAL Place Close to U1. C1035
    H_A#34 AP2 1 2 H_THERMDC 3 6 R3051 2 10K_0402_5% +3VS
    H_A#35 A[34]# R22 DN ALERT#
    AR1 A[35]# PROCHOT# D38 1 2 68_0402_5% 2200P_0402_50V7K
    AN5 BB34 H_THERMDA_R R23 1 2 0_0402_5% H_THERMDA THERM# 4 5
    8 H_ADSTB#1 ADSTB[1]# THERMDA THERM# GND
    BD34 H_THERMDC_R R24 1 2 0_0402_5% H_THERMDC
    THERMDC R306
    21 H_A20M# C7 A20M#
    D4 B10 H_THERMTRIP# +3VS 1 2
    21 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 8,21
    ICH

    F10 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8


    21 H_IGNNE# IGNNE#
    H_THERMDA, H_THERMDC routing together,
    21 H_STPCLK# F8 STPCLK# Address:100_1100
    21 H_INTR C9 H CLK Trace width / Spacing = 10 / 10 mil
    LINT0
    21 H_NMI C5 LINT1 BCLK[0] A35 CLK_CPU_BCLK 16
    21 H_SMI# E5 SMI# BCLK[1] C35 CLK_CPU_BCLK# 16
    V2 RSVD01
    Y2 RSVD02
    AG5 RSVD03
    RESERVED

    B B
    AL5 RSVD04
    J9 RSVD05
    F4 H_PROCHOT#
    RSVD06
    0.1U_0402_16V4Z

    H8 RSVD07 1
    C1057 @

    2
    For EMI
    PENRYN SFF_UFCBGA956
    SU2700@

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Penryn(1/4)-AGTL/ITP/XDP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 4 of 43
    5 4 3 2 1
    5 4 3 2 1

    +VCC_CORE +VCC_CORE
    8 H_D#[0..15] H_D#[32..47] 8
    U1B U1C
    H_D#0 F40 AP44 H_D#32 F32 AB28
    H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
    G43 D[1]# D[33]# AR43 G33 VCC[002] VCC[069] AD30
    H_D#2 E43 AH40 H_D#34 H32 AD28
    H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
    J43 D[3]# D[35]# AF40 J33 VCC[004] VCC[071] Y26

    DATA GROUP 0
    D H_D#4 H_D#36 D
    H40 D[4]# D[36]# AJ43 K32 VCC[005] VCC[072] AB26
    H_D#5 H44 AG41 H_D#37 L33 AD26
    H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
    G39 AF44 M32 AF30

    DATA GROUP 2
    H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
    E41 D[7]# D[39]# AH44 N33 VCC[008] VCC[075] AF28
    H_D#8 L41 AM44 H_D#40 P32 AH30
    H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
    K44 D[9]# D[41]# AN43 R33 VCC[010] VCC[077] AH28
    H_D#10 N41 AM40 H_D#42 T32 AF26
    H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
    T40 D[11]# D[43]# AK40 U33 VCC[012] VCC[079] AH26
    H_D#12 M40 AG43 H_D#44 V32 AK30
    H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
    G41 D[13]# D[45]# AP40 W33 VCC[014] VCC[081] AK28
    H_D#14 M44 AN41 H_D#46 Y32 AM30
    H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
    L43 D[15]# D[47]# AL41 AA33 VCC[016] VCC[083] AM28
    H_DSTBN#0 K40 AK44 H_DSTBN#2 AB32 AP30
    8 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 8 VCC[017] VCC[084]
    H_DSTBP#0 J41 AL43 H_DSTBP#2 AC33 AP28
    8 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 8 VCC[018] VCC[085]
    H_DINV#0 P40 AJ41 H_DINV#2 AD32 AK26
    8 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 8 VCC[019] VCC[086]
    8 H_D#[16..31] H_D#[48..63] 8 AE33 VCC[020] VCC[087] AM26
    AF32 VCC[021] VCC[088] AP26
    H_D#16 P44 AV38 H_D#48 AG33 AT30
    H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
    V40 D[17]# D[49]# AT44 AH32 VCC[023] VCC[090] AT28
    H_D#18 V44 AV40 H_D#50 AJ33 AV30
    H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
    AB44 D[19]# D[51]# AU41 AK32 VCC[025] VCC[092] AV28
    H_D#20 R41 AW41 H_D#52 AL33 AY30
    D[20]# D[52]# VCC[026] VCC[093]

    DATA GROUP 1
    H_D#21 W41 AR41 H_D#53 AM32 AY28
    H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
    N43 BA37 AN33 AT26

    DATA GROUP 3
    H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
    U41 D[23]# D[55]# BB38 AP32 VCC[029] VCC[096] AV26
    H_D#24 AA41 AY36 H_D#56 AR33 AY26
    H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
    AB40 D[25]# D[57]# AT40 AT34 VCC[031] VCC[098] BB30
    H_D#26 AD40 BC35 H_D#58 AT32 BB28 +VCCP
    H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099]
    AC41 D[27]# D[59]# BC39 AU33 VCC[033] VCC[100] BD30
    H_D#28 AA43 BA41 H_D#60 AV32
    H_D#29 D[28]# D[60]# H_D#61 VCC[034]
    Y40 D[29]# D[61]# BB40 AY32 VCC[035] VCCP_001 J11 +VCCP_001 R27 1 2 0_0402_5%
    H_D#30 Y44 BA35 H_D#62 BB32 E11 +VCCP_002 R28 1 2 0_0402_5%
    C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP_002 C
    T44 D[31]# D[63]# AU43 BD32 VCC[037] VCCP_003 G11 +VCCP_003 R29 1 2 0_0402_5%
    H_DSTBN#1 U43 AY40 H_DSTBN#3 B28 J37
    8 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 8 VCC[038] VCCP_004
    H_DSTBP#1 W43 AY38 H_DSTBP#3 B30 K38
    8 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 8 VCC[039] VCCP_005
    H_DINV#1 R43 BC37 H_DINV#3 B26 L37
    8 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 8 VCC[040] VCCP_006
    D28 VCC[041] VCCP_007 N37
    V_CPU_GTLREF AW43 AE43 COMP0 D30 P38 1 Change to 330u_R9,
    TEST1 GTLREF COMP[0] COMP1 VCC[042] VCCP_008
    T148 E37 TEST1 MISC COMP[1] AD44 F30 VCC[043] VCCP_009 R37
    casue high
    TEST2 D40 AE1 COMP2 F28 U37 + C5
    T8 TEST2 COMP[2] VCC[044] VCCP_010

    54.9_0402_1%

    27.4_0402_1%

    54.9_0402_1%

    27.4_0402_1%
    C43 TEST3 COMP[3] AF2 COMP3 H30 VCC[045] VCCP_011 V38 330U_D2E_2.5VM_R9 limitation. 12/14

    1 R32

    1 R33
    AE41 TEST4 H28 VCC[046] VCCP_012 W37
    2

    1 R30

    1 R31
    TEST5 AY10 G7 D26 AA37
    T9 TEST5 DPRSTP# H_DPRSTP# 8,21,39 VCC[047] VCCP_013
    TEST6 AC43 B8 F26 AB38
    T10 TEST6 DPSLP# H_DPSLP# 21 VCC[048] VCCP_014
    DPWR# C41 H_DPWR# 8 H26 VCC[049] VCCP_015 AC37
    16 CPU_BSEL0 A37 BSEL[0] PWRGOOD E7 H_PWRGOOD 21 K30 VCC[050] VCCP_016 AE37
    16 CPU_BSEL1 C37 BSEL[1] SLP# D10 H_CPUSLP# 8 K28 VCC[051]
    B38 BD10 H_PSI# M30 B34
    16 CPU_BSEL2 BSEL[2] PSI# T11 VCC[052] VCCA[01] +1.5VS
    M28 D34

    2
    VCC[053] VCCA[02]

    10U_0805_6.3V6M
    Near pin B34
    0.01U_0402_16V7K
    PENRYN SFF_UFCBGA956

    Near pin D34


    K26 VCC[054]
    SU2700@ Cause CPU core power change to M26 BD8
    VCC[055] VID[0] CPU_VID0 39
    P30 BC7 1 1
    1 phase, and not need support P28
    VCC[056] VID[1]
    BB10
    CPU_VID1 39
    VCC[057] VID[2] CPU_VID2 39
    the pin, leave it as TP. 10/02 T30 VCC[058] VID[3] BB8 CPU_VID3 39
    C6 C7
    layout note: Route TEST3 & TEST5 traces on Resistor placed within T28 VCC[059] VID[4] BC5 CPU_VID4 39 2 2
    V30 BB4 CPU_VID5 39
    ground referenced layer to the TPs 0.5" of CPU pin.Trace V28
    VCC[060] VID[5]
    AY4
    VCC[061] VID[6] CPU_VID6 39
    should be at least 25 P26 VCC[062]
    T26
    CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 mils away from any other V26
    VCC[063]
    BD12 VCCSENSE
    VCC[064] VCCSENSE VCCSENSE 39
    toggling signal. Y30 VCC[065]
    COMP[0,2] trace width is Y28 VCC[066]
    AB30 BC13 VSSSENSE VSSSENSE 39
    VCC[067] VSSSENSE
    166 0 1 1 18 mils. COMP[1,3] trace
    B PENRYN SFF_UFCBGA956 B
    width is 4 mils. SU2700@

    200 0 0
    Length match within 25 mils.
    1
    The trace width/space/other is
    20/7/25.
    266 0 0 0

    +VCC_CORE

    R34
    1 2 VCCSENSE
    +VCCP 100_0402_1%

    R35
    1

    1 2 VSSSENSE
    100_0402_1%
    R36
    1K_0402_1%
    2

    V_CPU_GTLREF

    Close to CPU pin


    1

    R37
    within 500mils.
    A 2K_0402_1% A
    2

    Close to CPU pin AW43


    within 500mils. Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Penryn(2/4)-AGTL/PWR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 5 of 43
    5 4 3 2 1
    A
    B
    C
    D

    5
    5

    BD28 VCC_101 VCCP_021 AL37


    BB26 VCC_102 VCCP_022 AN37
    BD26 VCC_103 VCCP_023 AP38
    B22 VCC_104 VCCP_024 B32
    B24 VCC_105 VCCP_025 C33
    D22 VCC_106 VCCP_026 D32
    D24 VCC_107 VCCP_027 E35
    F24 VCC_108 VCCP_028 E33
    F22 VCC_109 VCCP_029 F34
    H24 VCC_110 VCCP_030 G35
    H22 VCC_111 VCCP_031 F36
    K24 VCC_112 VCCP_032 H36
    K22 VCC_113 VCCP_033 J35
    M24 VCC_114 VCCP_034 L35
    M22 VCC_115 VCCP_035 N35
    P24 VCC_116 VCCP_036 K36
    P22 VCC_117 VCCP_037 R35
    T24 VCC_118 VCCP_038 U35
    T22 VCC_119 VCCP_039 P36
    V24 VCC_120 VCCP_040 V36
    V22 VCC_121 VCCP_041 W35
    Y24 VCC_122 VCCP_042 AA35
    Y22 VCC_123 VCCP_043 AC35
    AB24 VCC_124 VCCP_044 AB36
    AB22 VCC_125 VCCP_045 AE35
    AD24 VCC_126 VCCP_046 AG35
    AD22 VCC_127 VCCP_047 AJ35
    AF24 VCC_128 VCCP_048 AF36
    AF22 VCC_129 VCCP_049 AL35
    AH24 VCC_130 VCCP_050 AN35
    AH22 VCC_131 VCCP_051 AK36
    AK24 VCC_132 VCCP_052 AP36
    AK22 VCC_133 VCCP_053 B12
    AM24 B14

    4
    4

    VCC_134 VCCP_054
    AM22 VCC_135 VCCP_055 C13
    AP24 VCC_136 VCCP_056 D12
    AP22 VCC_137 VCCP_057 D14
    AT24 VCC_138 VCCP_058 E13
    AT22 VCC_139 VCCP_059 F14
    AV24 VCC_140 VCCP_060 F12
    AV22 VCC_141 VCCP_061 G13
    AY24 VCC_142 VCCP_062 H14
    AY22 VCC_143 VCCP_063 H12
    BB24 VCC_144 VCCP_064 J13
    BB22 VCC_145 VCCP_065 K14
    BD24 VCC_146 VCCP_066 K12
    BD22 VCC_147 VCCP_067 L13
    B16 VCC_148 VCCP_068 L11
    B18 VCC_149 VCCP_069 M14
    B20 VCC_150 VCCP_070 N13
    D16 VCC_151 VCCP_071 N11
    D18 VCC_152 VCCP_072 K10
    F18 VCC_153 VCCP_073 P14
    F16 VCC_154 VCCP_074 P12
    H18 VCC_155 VCCP_075 R13
    H16 VCC_156 VCCP_076 R11
    D20 VCC_157 VCCP_077 T14
    F20 VCC_158 VCCP_078 U13
    H20 VCC_159 VCCP_079 U11
    K18 VCC_160 VCCP_080 V14
    K16 VCC_161 VCCP_081 V12
    M18 VCC_162 VCCP_082 W13
    M16 VCC_163 VCCP_083 W11
    K20 VCC_164 VCCP_084 P10
    M20 VCC_165 VCCP_085 V10
    P18 VCC_166 VCCP_086 Y14
    P16 AA13

    Issued Date
    VCC_167 VCCP_087
    T18 VCC_168 VCCP_088 AA11

    3
    3

    T16 VCC_169 VCCP_089 AB14


    V18 AB12

    Security Classification
    VCC_170 VCCP_090
    V16 VCC_171 VCCP_091 AC13
    P20 VCC_172 VCCP_092 AC11
    T20 VCC_173 VCCP_093 AD14
    V20 VCC_174 VCCP_094 AB10
    Y18 VCC_175 VCCP_095 AE13
    Y16 VCC_176 VCCP_096 AE11
    AB18 VCC_177 VCCP_097 AF14
    AB16 VCC_178 VCCP_098 AF12
    AD18 VCC_179 VCCP_099 AG13
    AD16 VCC_180 VCCP_100 AG11
    Y20 AH14

    2009/04/01
    VCC_181 VCCP_101
    AB20 VCC_182 VCCP_102 AJ13
    AD20 VCC_183 VCCP_103 AJ11
    AF18 VCC_184 VCCP_104 AF10
    AF16 VCC_185 VCCP_105 AK14
    AH18 VCC_186 VCCP_106 AK12
    AH16 VCC_187 VCCP_107 AL13
    AF20 VCC_188 VCCP_108 AL11
    AH20 VCC_189 VCCP_109 AN13
    AK18 VCC_190 VCCP_110 AN11
    AK16 VCC_191 VCCP_111 AP12
    AM18 VCC_192 VCCP_112 AR13
    AM16 VCC_193 VCCP_113 AR11
    AP18 VCC_194 VCCP_114 AK10
    AP16 VCC_195 VCCP_115 AP10
    AK20 VCC_196 VCCP_116 AU13
    AM20 VCC_197 VCCP_117 AU11

    Compal Secret Data


    AP20 VCC_198 VCCP_118 L9

    Deciphered Date
    AT18 VCC_199 VCCP_119 L7
    AT16 VCC_200 VCCP_120 N9
    AV18 VCC_201 VCCP_121 N7
    AV16 VCC_202 VCCP_122 R9
    AY18 R7

    2
    2

    VCC_203 VCCP_123
    AY16 VCC_204 VCCP_124 U9
    AT20 VCC_205 VCCP_125 U7
    AV20 VCC_206 VCCP_126 W9
    AY20 VCC_207 VCCP_127 W7
    BB18 VCC_208 VCCP_128 AA9
    BB16 AA7
    2010/12/31

    VCC_209 VCCP_129
    BD18 VCC_210 VCCP_130 AC9
    BD16 VCC_211 VCCP_131 AC7
    BB20 VCC_212 VCCP_132 AE9
    BD20 VCC_213 VCCP_133 AE7
    AM14 VCC_214 VCCP_134 AG9
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    AP14 VCC_215 VCCP_135 AG7


    AT14 VCC_216 VCCP_136 AJ9
    AV14 VCC_217 VCCP_137 AJ7
    AY14 VCC_218 VCCP_138 AL9
    BB14 VCC_219 VCCP_139 AL7
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

    BD14 VCC_220 VCCP_140 AN9


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

    AN7
    Title

    Date:

    VCCP_141
    +VCC_CORE

    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom

    AF38 VCCP_017 VCCP_142 AR9


    AG37 VCCP_018 VCCP_143 AR7
    AJ37 VCCP_019 VCCP_144 A33
    AK38 VCCP_020 VCCP_145 A13
    +VCCP
    +VCCP

    U1F

    Size Document Number


    LA-5541P
    SU2700@

    Thursday, September 10, 2009


    Penryn(3/4)-PWR

    1
    1

    PENRYN SFF_UFCBGA956

    Sheet
    6
    of
    Compal Electronics, Inc.

    43
    Rev
    1.0
    A
    B
    C
    D
    5 4 3 2 1

    U1D U1E +VCC_CORE Mid Frequence Decoupling


    B42 VSS[001] VSS[082] AM36 G25 VSS_164 VSS_280 AA15
    F44 VSS[002] VSS[083] AR35 G23 VSS_165 VSS_281 AC15
    D44 VSS[003] VSS[084] AU35 G21 VSS_166 VSS_282 Y10
    D42 VSS[004] VSS[085] AV34 J25 VSS_167 VSS_283 AD10

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    F42 VSS[005] VSS[086] AW35 J23 VSS_168 VSS_284 AH12
    H42 VSS[006] VSS[087] AW33 J21 VSS_169 VSS_285 AE15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    K42 VSS[007] VSS[088] AY34 L25 VSS_170 VSS_286 AG15
    M42 VSS[008] VSS[089] AT36 L23 VSS_171 VSS_287 AJ15

    C8 @

    C9

    C10

    C11

    C12 @

    C13

    C14

    C15

    C16

    C17

    C18

    C19

    C20

    C21

    C22

    C23

    C24

    C25 @

    C26

    C27

    C28

    C29

    C30

    C31
    P42 VSS[009] VSS[090] AV36 L21 VSS_172 VSS_288 AH10
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    T42 VSS[010] VSS[091] BA33 N25 VSS_173 VSS_289 AM12
    V42 VSS[011] VSS[092] BC33 N23 VSS_174 VSS_290 AL15
    Y42 VSS[012] VSS[093] BB36 N21 VSS_175 VSS_291 AN15
    D D
    AB42 VSS[013] VSS[094] BD36 R25 VSS_176 VSS_292 AR15
    AD42 VSS[014] VSS[095] C27 R23 VSS_177 VSS_293 AM10
    AF42 VSS[015] VSS[096] C29 R21 VSS_178 VSS_294 AT12
    AH42 VSS[016] VSS[097] C31 U25 VSS_179 VSS_295 AV12
    AK42 VSS[017] VSS[098] E29 U23 VSS_180 VSS_296 AW13
    AM42 VSS[018] VSS[099] E27 U21 VSS_181 VSS_297 AW11
    AP42 VSS[019] VSS[100] G29 W25 VSS_182 VSS_298 AY12
    AY44 VSS[020] VSS[101] G27 W23 VSS_183 VSS_299 AU15
    AV44 VSS[021] VSS[102] E31 W21 VSS_184 VSS_300 AW15
    AT42 VSS[022] VSS[103] G31 AA25 VSS_185 VSS_301 AT10
    +VCC_CORE
    AV42 VSS[023] VSS[104] J29 AA23 VSS_186 VSS_302 BA13
    AY42 VSS[024] VSS[105] J27 AA21 VSS_187 VSS_303 BA11 High Frequence Decoupling
    BA43 VSS[025] VSS[106] L29 AC25 VSS_188 VSS_304 BB12
    BB42 VSS[026] VSS[107] L27 AC23 VSS_189 VSS_305 BC11
    C39 VSS[027] VSS[108] N29 AC21 VSS_190 VSS_306 BA15

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    E39 VSS[028] VSS[109] N27 AE25 VSS_191 VSS_307 BC15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    G37 VSS[029] VSS[110] J31 AE23 VSS_192 VSS_308 B6
    H38 VSS[030] VSS[111] L31 AE21 VSS_193 VSS_309 D6

    C32

    C33

    C34

    C35

    C36

    C37

    C38

    C39

    C40

    C41

    C42

    C43

    C44

    C45

    C46

    C47

    C48

    C49

    C50

    C51

    C52

    C53

    C54

    C55
    J39 VSS[031] VSS[112] N31 AG25 VSS_194 VSS_310 E9
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    L39 VSS[032] VSS[113] R29 AG23 VSS_195 VSS_311 F6
    M38 VSS[033] VSS[114] R27 AG21 VSS_196 VSS_312 G9
    N39 VSS[034] VSS[115] U29 AJ25 VSS_197 VSS_313 H6
    R39 VSS[035] VSS[116] U27 AJ23 VSS_198 VSS_314 K8
    T38 VSS[036] VSS[117] R31 AJ21 VSS_199 VSS_315 K6
    U39 VSS[037] VSS[118] U31 AL25 VSS_200 VSS_316 M8
    W39 VSS[038] VSS[119] W29 AL23 VSS_201 VSS_317 M6
    Y38 VSS[039] VSS[120] W27 AL21 VSS_202 VSS_318 P8 6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.
    AA39 VSS[040] VSS[121] W31 AN25 VSS_203 VSS_319 P6
    AC39 VSS[041] VSS[122] AA29 AN23 VSS_204 VSS_320 T8
    AD38 VSS[042] VSS[123] AA27 AN21 VSS_205 VSS_321 T6
    AE39 VSS[043] VSS[124] AC29 AR25 VSS_206 VSS_322 V8
    AG39 VSS[044] VSS[125] AC27 AR23 VSS_207 VSS_323 V6
    C C
    AH38 VSS[045] VSS[126] AA31 AR21 VSS_208 VSS_324 U5
    AJ39 VSS[046] VSS[127] AC31 AU25 VSS_209 VSS_325 Y8
    AL39 VSS[047] VSS[128] AE29 AU23 VSS_210 VSS_326 Y6
    AM38 AE27 AU21 AB8
    AN39
    AR39
    VSS[048]
    VSS[049]
    VSS[129]
    VSS[130] AG29
    AG27
    AW25
    AW23
    VSS_211
    VSS_212
    VSS_327
    VSS_328 AB6
    AD8
    ESR <= 1.5m ohm
    VSS[050] VSS[131] VSS_213 VSS_329
    AR37 VSS[051] VSS[132] AJ29 AW21 VSS_214 VSS_330 AD6
    AT38 AJ27 BA25 AF8
    AU39
    VSS[052]
    VSS[053]
    VSS[133]
    VSS[134] AE31 BA23
    VSS_215
    VSS_216
    VSS_331
    VSS_332 AF6
    +VCC_CORE Near CPU CORE regulator
    AU37 VSS[054] VSS[135] AG31 BA21 VSS_217 VSS_333 AH8
    AW39 VSS[055] VSS[136] AJ31 BC25 VSS_218 VSS_334 AH6

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    AW37 VSS[056] VSS[137] AL29 BC23 VSS_219 VSS_335 AK8
    +VCC_CORE
    BA39 VSS[057] VSS[138] AL27 BC21 VSS_220 VSS_336 AK6 1 1 1
    BC41 VSS[058] VSS[139] AN29 C17 VSS_221 VSS_337 AM8
    BD40 VSS[059] VSS[140] AN27 C19 VSS_222 VSS_338 AM6 C1364

    C1365

    C1366
    BD38 VSS[060] VSS[141] AL31 E19 VSS_223 VSS_339 AP8
    2 2 2
    B36 VSS[061] VSS[142] AN31 E17 VSS_224 VSS_340 AP6

    220U_D2_2VK_R9

    220U_D2_2VK_R9

    220U_D2_2VK_R9
    H34 VSS[062] VSS[143] AR29 G19 VSS_225 VSS_341 AT8 1 1 1

    C56

    C57

    C58
    D36 VSS[063] VSS[144] AR27 G17 VSS_226 VSS_342 AT6
    K34 AR31 J19 AU9 + + +
    VSS[064] VSS[145] VSS_227 VSS_343
    M34 VSS[065] VSS[146] AU29 J17 VSS_228 VSS_344 AV6
    M36 VSS[066] VSS[147] AU27 L19 VSS_229 VSS_345 AU7
    2 2 2
    P34 VSS[067] VSS[148] AW29 L17 VSS_230 VSS_346 AW9
    T34 VSS[068] VSS[149] AW27 N19 VSS_231 VSS_347 AY6
    V34 VSS[069] VSS[150] AU31 N17 VSS_232 VSS_348 BA9
    T36 VSS[070] VSS[151] AW31 R19 VSS_233 VSS_349 BB6
    Y34 VSS[071] VSS[152] BA29 R17 VSS_234 VSS_350 BC9
    AB34 VSS[072] VSS[153] BA27 U19 VSS_235 VSS_351 BD6
    AD34 VSS[073] VSS[154] BC29 U17 VSS_236 VSS_352 B4
    Y36 VSS[074] VSS[155] BC27 W19 VSS_237 VSS_353 C3
    AD36 VSS[075] VSS[156] BA31 W17 VSS_238 VSS_354 E3 Del C37 to improve power plan. 6/14
    AF34 VSS[076] VSS[157] BC31 AA19 VSS_239 VSS_355 G3
    B B
    AH34 VSS[077] VSS[158] C21 AA17 VSS_240 VSS_356 J3
    AH36 VSS[078] VSS[159] C23 AC19 VSS_241 VSS_357 L3
    AK34 VSS[079] VSS[160] C25 AC17 VSS_242 VSS_358 N3
    AM34 VSS[080] VSS[161] E25 AE19 VSS_243 VSS_359 R3
    AP34 VSS[081] VSS[162] E23 AE17 VSS_244 VSS_360 U3
    VSS[163] E21 AG19 VSS_245 VSS_361 W3
    AG17 VSS_246 VSS_362 AA3
    AJ19 VSS_247 VSS_363 AC3
    PENRYN SFF_UFCBGA956 AJ17 AE3
    SU2700@ VSS_248 VSS_364
    AL19 VSS_249 VSS_365 AG3
    AL17 VSS_250 VSS_366 AJ3
    AN19 AL3 +VCCP
    VSS_251 VSS_367
    AN17 VSS_252 VSS_368 AN3
    AR19 VSS_253 VSS_369 AR3
    AR17 VSS_254 VSS_370 AU3
    AU19 VSS_255 VSS_371 AW3
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    AU17 VSS_256 VSS_372 BA3 1 1 1 1 1 1 1 1 1 1 1 1
    AW19 VSS_257 VSS_373 BC3
    AW17 VSS_258 VSS_374 D2
    C59

    C60

    C61

    C62

    C63

    C64

    C65

    C66

    C67

    C68

    C69

    C70
    BA19 VSS_259 VSS_375 E1
    2 2 2 2 2 2 2 2 2 2 2 2
    BA17 VSS_260 VSS_376 G1
    BC19 VSS_261 VSS_377 AW1
    BC17 VSS_262 VSS_378 BA1
    C11 VSS_263 VSS_379 BB2
    C15 VSS_264 VSS_380 A41
    E15 VSS_265 VSS_381 A39
    G15 VSS_266 VSS_382 A29
    H10 VSS_267 VSS_383 A27
    M12 VSS_268 VSS_384 A31
    J15 VSS_269 VSS_385 A25
    L15 VSS_270 VSS_386 A23
    N15 VSS_271 VSS_387 A21
    A A
    M10 VSS_272 VSS_388 A19
    T12 VSS_273 VSS_389 A17
    R15 VSS_274 VSS_390 A11
    U15 VSS_275 VSS_391 A15
    W15 VSS_276 VSS_392 A7
    T10 VSS_277 VSS_393 A5
    Y12 VSS_278 VSS_394 A9
    AD12 BD4
    VSS_279 VSS_395 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title
    PENRYN SFF_UFCBGA956
    SU2700@
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Penryn(4/4)-GND/Bypass
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 7 of 43
    5 4 3 2 1
    5 4 3 2 1

    H_A#[3..35] 4 U3B
    5 H_D#[0..63] U3A
    L15 H_A#3 J43
    H_A#_3 T12 RSVD1
    H_D#0 J7 B14 H_A#4 L43 BB32 M_CLK_DDR0 14
    H_D#_0 H_A#_4 T13 RSVD2 SA_CK_0
    H_D#1 H_A#5

    DDR CLK/ CONTROL/COMPENSATION


    H6 H_D#_1 H_A#_5 C15 T14 J41 RSVD3 SA_CK_1 BA25 M_CLK_DDR1 14
    H_D#2 L11 D12 H_A#6 L41 BA33 M_CLK_DDR2 15
    H_D#_2 H_A#_6 T15 RSVD4 SB_CK_0
    H_D#3 J3 F14 H_A#7 AN11 BA23 M_CLK_DDR3 15
    H_D#_3 H_A#_7 T16 RSVD5 SB_CK_1
    H_D#4 H4 G17 H_A#8 AM10
    H_D#_4 H_A#_8 T17 RSVD6
    H_D#5 G3 B12 H_A#9 Add them for Boundary Scan. 10/23 AK10 BA31
    H_D#_5 H_A#_9 T18 RSVD7 SA_CK#_0 M_CLK_DDR#0 14
    H_D#6 K10 J15 H_A#10 AL11 BC25
    H_D#_6 H_A#_10 T19 RSVD8 SA_CK#_1 M_CLK_DDR#1 14
    H_D#7 K12 D16 H_A#11 F12 BC33
    H_D#_7 H_A#_11 T20 RSVD9 SB_CK#_0 M_CLK_DDR#2 15

    RSVD
    H_D#8 L1 C17 H_A#12 R39 1 2 @ 1K_0402_5% TCK AN45 BB24
    H_D#_8 H_A#_12 RSVD10 SB_CK#_1 M_CLK_DDR#3 15
    H_D#9 M10 D14 H_A#13 R38 1 2 @ 4.7K_0402_5% TDI AP44
    H_D#10 H_D#_9 H_A#_13 H_A#14 R40 @ 4.7K_0402_5% TDO RSVD11
    M6 H_D#_10 H_A#_14 K16 1 2 AT44 RSVD12 SA_CKE_0 BC35 DDR_CKE0_DIMMA 14
    H_D#11 N11 F16 H_A#15 +3VS R41 1 2 @ 1K_0402_5% TMS AN47 BE33
    H_D#_11 H_A#_15 RSVD13 SA_CKE_1 DDR_CKE1_DIMMA 14
    H_D#12 L7 B16 H_A#16 C27 BE37
    H_D#_12 H_A#_16 T21 RSVD14 SB_CKE_0 DDR_CKE2_DIMMB 15
    D H_D#13 K6 C21 H_A#17 D30 BC37 D
    H_D#_13 H_A#_17 T22 RSVD15 SB_CKE_1 DDR_CKE3_DIMMB 15
    H_D#14 M4 D18 H_A#18
    H_D#15 H_D#_14 H_A#_18 H_A#19
    K4 H_D#_15 H_A#_19 J19 T23 J9 RSVD17 SA_CS#_0 BK18 DDR_CS0_DIMMA# 14
    H_D#16 P6 J21 H_A#20 BK16
    H_D#_16 H_A#_20 SA_CS#_1 DDR_CS1_DIMMA# 14
    H_D#17 W9 B18 H_A#21 BE23
    H_D#_17 H_A#_21 SB_CS#_0 DDR_CS2_DIMMB# 15
    H_D#18 V6 D22 H_A#22 AW42 BC19
    H_D#_18 H_A#_22 T24 RSVD20 SB_CS#_1 DDR_CS3_DIMMB# 15
    H_D#19 H_A#23

    0.01U_0402_25V7K
    2.2U_0603_6.3V4Z
    V2 H_D#_19 H_A#_23 G19
    H_D#20 P10 J17 H_A#24 BJ17 M_ODT0 14
    H_D#21 H_D#_20 H_A#_24 H_A#25 +1.5V SA_ODT_0
    W7 H_D#_21 H_A#_25 L21 SA_ODT_1 BJ19 M_ODT1 14
    H_D#22 H_A#26 +1.5V
    N9 H_D#_22 H_A#_26 L19 T25 BB20 RSVD22 SB_ODT_0 BC17 M_ODT2 15
    H_D#23 P4 G21 H_A#27 1 1 BE19 BE17 M_ODT3 15
    H_D#_23 H_A#_27 T26 RSVD23 SB_ODT_1

    1
    C71

    C72
    H_D#24 U9 D20 H_A#28 BF20
    H_D#_24 H_A#_28 T27 RSVD24
    H_D#25 V4 K22 H_A#29 BF18 BL25 SMRCOMP R43 1 2 80.6_0402_1%
    H_D#_25 H_A#_29 T28 RSVD25 SM_RCOMP
    H_D#26 U1 F18 H_A#30 R42 BK26 SMRCOMP# R44 1 2 80.6_0402_1%
    H_D#27 H_D#_26 H_A#_30 H_A#31 2 2 1K_0402_1% SM_RCOMP#
    W3 H_D#_27 H_A#_31 K20
    H_D#28 V10 F20 H_A#32 BK32 SMRCOMP_VOH

    2
    H_D#29 H_D#_28 H_A#_32 H_A#33 SMRCOMP_VOH SM_RCOMP_VOH SMRCOMP_VOL
    U7 H_D#_29 H_A#_33 F22 SM_RCOMP_VOL BL31
    H_D#30 W11 B20 H_A#34 R1515 1 2 0_0402_5%
    H_D#_30 H_A#_34 SM_PWROK 38

    1
    H_D#31 U11 A19 H_A#35 BC51 +V_DDR_MCH_REF
    H_D#32 H_D#_31 H_A#_35 R45 SM_VREF SM_PWROK_R R46 @
    AC11 H_D#_32 SM_PWROK AY37 1 2 10K_0402_1%
    H_D#33 AC9 F10 3.01K_0402_1% BH20 SM_REXT R47 1 2 499_0402_1%
    H_D#_33 H_ADS# H_ADS# 4 SM_REXT
    H_D#34 Y4
    HOST A15 BA37 SM_DRAMRST#
    H_D#_34 H_ADSTB#_0 H_ADSTB#0 4 SM_DRAMRST# SM_DRAMRST# 14,15
    H_D#35 Y10 C19 H_ADSTB#1 4

    2
    H_D#36 H_D#_35 H_ADSTB#_1 SMRCOMP_VOL
    AB6 H_D#_36 H_BNR# C9 H_BNR# 4 DPLL_REF_CLK B42 CLK_MCH_DREFCLK 16
    H_D#37 AA9 B8 D42
    H_D#_37 H_BPRI# H_BPRI# 4 DPLL_REF_CLK# CLK_MCH_DREFCLK# 16

    1
    H_D#38

    0.01U_0402_25V7K
    2.2U_0603_6.3V4Z
    AB10 H_D#_38 H_BREQ# C11 H_BR0# 4 DPLL_REF_SSCLK B50 MCH_SSCDREFCLK 16
    H_D#39 AA1 E5 1 1 R48 D50
    H_D#_39 H_DEFER# H_DEFER# 4 DPLL_REF_SSCLK# MCH_SSCDREFCLK# 16
    H_D#40 AC3 D6 1K_0402_1%
    H_D#_40 H_DBSY# H_DBSY# 4

    C73

    C74
    H_D#41 AC7 AH10 R49
    H_D#_41 HPLL_CLK CLK_MCH_BCLK 16 PEG_CLK CLK_MCH_3GPLL 16
    H_D#42 AD12 AJ11 P50
    CLK_MCH_BCLK# 16 CLK_MCH_3GPLL# 16

    2
    H_D#43 H_D#_42 HPLL_CLK# 2 2 PEG_CLK#
    AB4 G11

    CLK
    H_D#_43 H_DPWR# H_DPWR# 5
    H_D#44 Y6 H2
    H_D#_44 H_DRDY# H_DRDY# 4
    H_D#45 AD10 C7
    H_D#_45 H_HIT# H_HIT# 4
    H_D#46 AA11 F8 AG55
    H_D#_46 H_HITM# H_HITM# 4 DMI_RXN_0 DMI_TXN0 22
    H_D#47 AB2 A11 AL49
    C H_D#_47 H_LOCK# H_LOCK# 4 DMI_RXN_1 DMI_TXN1 22 C
    H_D#48 AD4 D8 AH54
    H_D#_48 H_TRDY# H_TRDY# 4 DMI_RXN_2 DMI_TXN2 22
    H_D#49 AE7 AL47
    H_D#_49 DMI_RXN_3 DMI_TXN3 22
    H_D#50 AD2
    H_D#51 H_D#_50
    AD6 H_D#_51 DMI_RXP_0 AG53 DMI_TXP0 22
    H_D#52 AE3 K26 AK50
    H_D#_52 16 MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 22
    H_D#53 AG9 L9 G23 AH52
    H_D#_53 H_DINV#_0 H_DINV#0 5 16 MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 22
    H_D#54 AG7 N7 G25 AL45
    H_D#_54 H_DINV#_1 H_DINV#1 5 16 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 22
    H_D#55 AE11 AA7 J25
    H_D#_55 H_DINV#_2 H_DINV#2 5 T30 CFG_3
    H_D#56 AK6 AG3 L25 AG49
    H_D#_56 H_DINV#_3 H_DINV#3 5 T31 CFG_4 DMI_TXN_0 DMI_RXN0 22
    H_D#57 AF6 L27 AJ49
    H_D#_57 10 CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 22
    H_D#58 AJ9 K2 F24 AJ47
    H_D#_58 H_DSTBN#_0 H_DSTBN#0 5 10 CFG6 CFG_6 DMI_TXN_2 DMI_RXN2 22
    H_D#59 AH6 N3 D24 AG47
    H_D#_59 H_DSTBN#_1 H_DSTBN#1 5 10 CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 22
    H_D#60 AF12 AA3 D26

    DMI
    H_D#_60 H_DSTBN#_2 H_DSTBN#2 5 T32 CFG_8

    CFG
    H_D#61 AH4 AF4 J23 AF50
    H_D#_61 H_DSTBN#_3 H_DSTBN#3 5 10 CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 22
    H_D#62 AJ7 B26 AH50
    H_D#_62 10 CFG10 CFG_10 DMI_TXP_1 DMI_RXP1 22
    H_D#63 AE9 L3 A23 AJ45
    H_D#_63 H_DSTBP#_0 H_DSTBP#0 5 T33 CFG_11 DMI_TXP_2 DMI_RXP2 22
    H_DSTBP#_1 M2 H_DSTBP#1 5 10 CFG12 C23 CFG_12 DMI_TXP_3 AG45 DMI_RXP3 22
    H_DSTBP#_2 Y2 H_DSTBP#2 5 10 CFG13 B24 CFG_13
    H_SWNG B6 AF2 B22
    H_SWING H_DSTBP#_3 H_DSTBP#3 5 T34 CFG_14
    H_RCOMP D4 K24
    H_RCOMP T35 CFG_15
    H_REQ#_0 J13 H_REQ#0 4 10 CFG16 C25 CFG_16

    GRAPHICS VID
    H_REQ#_1 L13 H_REQ#1 4 T36 L23 CFG_17
    H_REQ#_2 C13 H_REQ#2 4 T37 L33 CFG_18
    H_REQ#_3 G13 H_REQ#3 4 10 CFG19 K32 CFG_19
    4 H_RESET# J11 H_CPURST# H_REQ#_4 G15 H_REQ#4 4 10 CFG20 K34 CFG_20 GFX_VID_0 G33
    5 H_CPUSLP# G9 H_CPUSLP# GFX_VID_1 G37
    H_RS#_0 F4 H_RS#0 4 GFX_VID_2 F38
    H_RS#_1 F2 H_RS#1 4 GFX_VID_3 F36
    H_RS#_2 G7 H_RS#2 4 22 PM_BMBUSY# J35 PM_SYNC# GFX_VID_4 G35
    L17 H_AVREF 5,21,39 H_DPRSTP# F6 PM_DPRSTP#
    H_VREF K18 PM_EXTTS#0 J39 Modify in 9/26
    H_DVREF 14 PM_EXTTS#0 PM_EXT_TS#_0

    PM
    PM_EXTTS#1 L39
    15 PM_EXTTS#1 PM_EXT_TS#_1
    Trace < = 500mils CANTIGA GMCH SFF_FCBGA1363 R49 1 2 0_0402_5% AY39 G39
    22,29,39 PM_PWROK PWROK GFX_VR_EN +VCCP
    layout note: R50 1 2 100_0402_1% BB18
    20,25,27,29 PLT_RST# RSTIN#
    B 4,21 H_THERMTRIP# 1 2 K28 THERMTRIP#
    B
    Route H_SCOMP and H_SCOMP# with trace width, 22,39 PM_DPRSLPVR R51 0_0402_5% K36 DPRSLPVR

    1
    spacing and impedance (55 ohm) same as FSB data layout note:
    Add R428 in 9/26

    C75
    AK52 R52
    CL_CLK CL_CLK0 22
    traces Place them close to U3 pin BC51. 1 AK54 1K_0402_1%
    CL_DATA CL_DATA0 22
    A7 NC_1 CL_PWROK AW40 M_PWROK 22

    ME
    A49 AL53 CL_RST# 22

    2
    NC_2 CL_RST# CL_VREF

    @ 0.1U_0402_16V4Z
    Layout Note: 2
    A52 NC_3 CL_VREF AL55
    A54
    H_RCOMP / H_VREF / H_SWNG NC_4

    1
    B54 NC_5 1
    trace width and spacing is 10/20 D55 C76 R53
    NC_6 511_0402_1%
    G55 NC_7 DDPC_CTRLCLK F34 T38
    +V_DDR_MCH_REF +1.5V

    NC
    Layout Note: BE55 F32 0.1U_0402_16V4Z
    NC_8 DDPC_CTRLDATA T39 2
    V_DDR_MCH_REF BH55 B38 HDMICLK 17

    2
    +VCCP NC_9 SDVO_CTRLCLK
    BK55 A37

    MISC
    NC_10 SDVO_CTRLDATA HDMIDAT 17
    1

    +VCCP trace width and BK54 C31


    NC_11 CLKREQ# CLKREQ#_B 16
    spacing is 20/20. R1498 BL54 K42
    NC_12 ICH_SYNC# MCH_ICH_SYNC# 22
    1K_0402_1%

    221_0603_1%

    1K_0402_1% BL52 NC_13


    1

    BL49 NC_14
    R55 R56 BL7 D10 TSATN# R58 1 2 54.9_0402_1% +VCCP
    2

    NC_15 TSATN#
    0.1U_0402_16V7K

    +V_DDR_MCH_REF BL4 NC_16


    BL2 NC_17
    1

    H_DPRSTP# BK2
    2

    H_VREF H_RCOMP H_SWNG R1499 NC_18


    1 BK1 NC_19
    C1056

    C1347 1K_0402_1% BH1 NC_20


    R59

    24.9_0402_1%

    0.1U_0402_16V4Z

    1 BE1 NC_21
    1

    1
    100_0402_1%

    HDA_BITCLK_NB
    0.1U_0402_16V4Z

    1 1 G1 C29 HDA_BITCLK_NB 21
    2

    C78 R60 R61 C79 2 NC_22 HDA_BCLK R313


    HDA_RST# B30 HDA_RST#_NB 21

    HDA
    2K_0402_1%

    HDA_SDIN2_NB
    @ 0.1U_0402_16V4Z

    HDA_SDI D28 1 2 HDA_SDIN2 21


    2
    HDA_SDO A27 HDA_SDOUT_NB 21
    2 2 33_0402_5%
    B28 HDA_SYNC_NB 21
    2

    HDA_SYNC

    @ Near B6 pin +3VS


    A
    within 100 mils from NB
    For ESD CANTIGA GMCH SFF_FCBGA1363 A
    C237 @
    PM_EXTTS#0 R62 1 2 10K_0402_5% R152 @
    For EMI 33P_0402_50V8J
    HDA_BITCLK_NB 1 2 33_0402_1% 1 2
    PM_EXTTS#1 R63 1 2 10K_0402_5%

    Del R48. 9/27


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cantiga(1/6)-AGTL/DDR/DMI
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-5541P
    Date: Thursday, September 10, 2009 Sheet 8 of 43
    5 4 3 2 1
    5 4 3 2 1

    D D

    14 DDR_A_D[0..63] 15 DDR_B_D[0..63]
    U3D U3E
    DDR_A_D0 AP46 BC21 DDR_B_D0 AP54 BJ13
    SA_DQ_0 SA_BS_0 DDR_A_BS0 14 SB_DQ_0 SB_BS_0 DDR_B_BS0 15
    DDR_A_D1 AU47 BJ21 DDR_B_D1 AM52 BK12
    SA_DQ_1 SA_BS_1 DDR_A_BS1 14 SB_DQ_1 SB_BS_1 DDR_B_BS1 15
    DDR_A_D2 AT46 BJ41 DDR_B_D2 AR55 BK38
    SA_DQ_2 SA_BS_2 DDR_A_BS2 14 SB_DQ_2 SB_BS_2 DDR_B_BS2 15
    DDR_A_D3 AU49 DDR_B_D3 AV54
    DDR_A_D4 SA_DQ_3 DDR_B_D4 SB_DQ_3
    AR45 SA_DQ_4 SA_RAS# BH22 DDR_A_RAS# 14 AM54 SB_DQ_4
    DDR_A_D5 AN49 BK20 DDR_B_D5 AN53 BE21
    SA_DQ_5 SA_CAS# DDR_A_CAS# 14 SB_DQ_5 SB_RAS# DDR_B_RAS# 15
    DDR_A_D6 AV50 BL15 DDR_A_WE# 14 DDR_B_D6 AT52 BH14
    SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# 15
    DDR_A_D7 AP50 DDR_B_D7 AU53 BK14 DDR_B_WE# 15
    DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
    AW47 SA_DQ_8 AW53 SB_DQ_8
    DDR_A_D9 BD50 DDR_B_D9 AY52
    DDR_A_D10 SA_DQ_9 DDR_B_D10 SB_DQ_9
    AW49 SA_DQ_10 DDR_A_DM[0..7] 14 BB52 SB_DQ_10
    DDR_A_D11 BA49 AT50 DDR_A_DM0 DDR_B_D11 BC53
    SA_DQ_11 SA_DM_0 SB_DQ_11 DDR_B_DM[0..7] 15
    DDR_A_D12 BC49 BB50 DDR_A_DM1 DDR_B_D12 AV52 AP52 DDR_B_DM0
    DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
    AV46 SA_DQ_13 SA_DM_2 BB46 AW55 SB_DQ_13 SB_DM_1 AY54
    DDR_A_D14 BA47 BE39 DDR_A_DM3 DDR_B_D14 BD52 BJ49 DDR_B_DM2
    DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
    AY50 SA_DQ_15 SA_DM_4 BB12 BC55 SB_DQ_15 SB_DM_3 BJ43

    A
    DDR_A_D16 BF46 BE7 DDR_A_DM5 DDR_B_D16 BF54 BH12 DDR_B_DM4
    DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
    BC47 SA_DQ_17 SA_DM_6 AV10 BE51 SB_DQ_17 SB_DM_5 BD2
    DDR_A_D18 BF50 AR9 DDR_A_DM7 DDR_B_D18 BH48 AY2 DDR_B_DM6

    B
    DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
    BF48 SA_DQ_19 DDR_A_DQS[0..7] 14 BK48 SB_DQ_19 SB_DM_7 AJ3
    DDR_A_D20 BC43 AR47 DDR_A_DQS0 DDR_B_D20 BE53
    SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] 15

    MEMORY
    DDR_A_D21 BE49 BA45 DDR_A_DQS1 DDR_B_D21 BH52 AR53 DDR_B_DQS0
    DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
    BA43 SA_DQ_22 SA_DQS_2 BE45 BK46 SB_DQ_22 SB_DQS_1 BA53
    DDR_A_D23 BE47 BC41 DDR_A_DQS3 DDR_B_D23 BJ47 BH50 DDR_B_DQS2

    MEMORY
    DDR_A_D24 SA_DQ_23 SA_DQS_3 DDR_A_DQS4 DDR_B_D24 SB_DQ_23 SB_DQS_2 DDR_B_DQS3
    BF42 SA_DQ_24 SA_DQS_4 BC13 BL45 SB_DQ_24 SB_DQS_3 BK42
    DDR_A_D25 BC39 BB10 DDR_A_DQS5 DDR_B_D25 BJ45 BH8 DDR_B_DQS4
    DDR_A_D26 SA_DQ_25 SA_DQS_5 DDR_A_DQS6 DDR_B_D26 SB_DQ_25 SB_DQS_4 DDR_B_DQS5
    BF44 SA_DQ_26 SA_DQS_6 BA7 BL41 SB_DQ_26 SB_DQS_5 BB2
    DDR_A_D27 BF40 AN7 DDR_A_DQS7 DDR_B_D27 BH44 AV2 DDR_B_DQS6
    SA_DQ_27 SA_DQS_7 DDR_A_DQS#[0..7] 14 SB_DQ_27 SB_DQS_6
    DDR_A_D28 BB40 AR49 DDR_A_DQS#0 DDR_B_D28 BH46 AM2 DDR_B_DQS7
    C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] 15 C
    DDR_A_D29 BE43 AW45 DDR_A_DQS#1 DDR_B_D29 BK44 AT54 DDR_B_DQS#0
    DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
    BF38 SA_DQ_30 SA_DQS#_2 BC45 BK40 SB_DQ_30 SB_DQS#_1 BB54
    DDR_A_D31 BE41 BA41 DDR_A_DQS#3 DDR_B_D31 BJ39 BJ51 DDR_B_DQS#2
    DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
    BA15 SA_DQ_32 SA_DQS#_4 BA13 BK10 SB_DQ_32 SB_DQS#_3 BH42
    DDR_A_D33 BE11 BA11 DDR_A_DQS#5 DDR_B_D33 BH10 BK8 DDR_B_DQS#4
    SYSTEM

    DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5


    BE15 SA_DQ_34 SA_DQS#_6 BA9 BK6 SB_DQ_34 SB_DQS#_5 BC3
    DDR_A_D35 BF14 AN9 DDR_A_DQS#7 DDR_B_D35 BH6 AW3 DDR_B_DQS#6
    DDR_A_D36 SA_DQ_35 SA_DQS#_7 DDR_B_D36 SB_DQ_35 SB_DQS#_6 DDR_B_DQS#7

    SYSTEM
    BB14 SA_DQ_36 DDR_A_MA[0..14] 14 BJ9 SB_DQ_36 SB_DQS#_7 AN3
    DDR_A_D37 BC15 BC23 DDR_A_MA0 DDR_B_D37 BL11 DDR_B_MA[0..14] 15
    DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
    BE13 SA_DQ_38 SA_MA_1 BF22 BG5 SB_DQ_38 SB_MA_0 BJ15
    DDR_A_D39 BF16 BE31 DDR_A_MA2 DDR_B_D39 BJ5 BJ33 DDR_B_MA1
    DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
    BF10 SA_DQ_40 SA_MA_3 BC31 BG3 SB_DQ_40 SB_MA_2 BH24
    DDR_A_D41 BC11 BH26 DDR_A_MA4 DDR_B_D41 BF4 BA17 DDR_B_MA3
    DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
    BF8 SA_DQ_42 SA_MA_5 BJ35 BD4 SB_DQ_42 SB_MA_4 BF36
    DDR_A_D43 BG7 BB34 DDR_A_MA6 DDR_B_D43 BA3 BH36 DDR_B_MA5
    DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
    BC7 SA_DQ_44 SA_MA_7 BH32 BE5 SB_DQ_44 SB_MA_6 BF34
    DDR_A_D45 BC9 BB26 DDR_A_MA8 DDR_B_D45 BF2 BK34 DDR_B_MA7
    DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
    DDR

    BD6 SA_DQ_46 SA_MA_9 BF32 BB4 SB_DQ_46 SB_MA_8 BJ37


    DDR_A_D47 BF12 BA21 DDR_A_MA10 DDR_B_D47 AY4 BH40 DDR_B_MA9
    DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
    AV6 SA_DQ_48 SA_MA_11 BG25 BA1 SB_DQ_48 SB_MA_10 BH16
    DDR_A_D49 DDR_A_MA12 DDR_B_D49 DDR_B_MA11

    DDR
    BB6 SA_DQ_49 SA_MA_12 BH34 AP2 SB_DQ_49 SB_MA_11 BK36
    DDR_A_D50 AW7 BH18 DDR_A_MA13 DDR_B_D50 AU1 BH38 DDR_B_MA12
    DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
    AY6 SA_DQ_51 SA_MA_14 BE25 AT2 SB_DQ_51 SB_MA_13 BJ11
    DDR_A_D52 AT10 DDR_B_D52 AT4 BL37 DDR_B_MA14
    DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
    AW11 SA_DQ_53 AV4 SB_DQ_53
    DDR_A_D54 AU11 DDR_B_D54 AU3
    DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
    AW9 SA_DQ_55 AR3 SB_DQ_55
    DDR_A_D56 AR11 DDR_B_D56 AN1
    DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
    AT6 SA_DQ_57 AP4 SB_DQ_57
    DDR_A_D58 AP6 DDR_B_D58 AL3
    DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
    AL7 SA_DQ_59 AJ1 SB_DQ_59
    DDR_A_D60 AR7 DDR_B_D60 AK4
    B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
    AT12 SA_DQ_61 AM4 SB_DQ_61
    DDR_A_D62 AM6 DDR_B_D62 AH2
    DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
    AU7 SA_DQ_63 AK2 SB_DQ_63
    CANTIGA GMCH SFF_FCBGA1363 CANTIGA GMCH SFF_FCBGA1363

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cantiga(2/6)-DDR3 Channel A/B
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 9 of 43
    5 4 3 2 1
    5 4 3 2 1

    U3C
    Strap Pin Table
    PEGCOMP trace width +VCC_PEG
    and spacing is 20/25 mils. 000 = FSB 1066MHz
    19,29 BKLT D38 L_BKLT_CTRL CFG[2:0] FSB Freq select
    29 ENBKL C37 U45 PEGCOMP 1 2 010 = FSB 800MHz
    R65 L_BKLT_EN PEG_COMPI
    +3VS 1 2 10K_0402_5% K38 T44 R64 49.9_0402_1%
    L_CTRL_CLK PEG_COMPO 011 = FSB 667MHz
    R66 1 2 10K_0402_5% L37 layout note: Others = Reserved
    L_CTRL_DATA
    19 DDC2_CLK J37 L_DDC_CLK PEG_RX#_0 D52
    19 DDC2_DATA L35 L_DDC_DATA PEG_RX#_1 G49 Place R64 <500mils to U3 pin U45&T44.
    PEG_RX#_2 K54 CFG[4:3] Reserved
    PEG_RX#_3 H50
    19,29 ENAVDD B36 L_VDD_EN PEG_RX#_4 M52 0 = DMI x 2
    1 2 F50 LVDS_IBG PEG_RX#_5 N49 CFG5 (DMI select) 1 = DMI x 4
    D R67
    T42
    2.4K_0402_1%~D H46
    P44
    LVDS_VBG
    LVDS_VREFH
    PEG_RX#_6
    PEG_RX#_7
    P54
    V46
    *
    0 = The iTPM Host Interface is enable
    D

    K46 LVDS_VREFL PEG_RX#_8 Y50 CFG6


    D46 V52 1 = The iTPM Host Interface is disable
    19
    19
    TXCLK_L-
    TXCLK_L+ B46
    LVDSA_CLK#
    LVDSA_CLK
    PEG_RX#_9
    PEG_RX#_10 W49 *

    LVDS
    D44 LVDSB_CLK# PEG_RX#_11 AB54 0 =(TLS)chiper suite with no confidentiality
    10/18 B44 AD46 CFG7 (Intel Management
    LVDSB_CLK PEG_RX#_12
    AC55 1 =(TLS)chiper suite with confidentiality
    19
    19
    TXOUT_L0-
    TXOUT_L1-
    G45
    F46
    LVDSA_DATA#_0
    PEG_RX#_13
    PEG_RX#_14 AE49
    AF54
    Engine Crypto strap)
    *
    LVDSA_DATA#_1 PEG_RX#_15

    GRAPHICS
    19 TXOUT_L2- G41 LVDSA_DATA#_2
    10/19 C45 LVDSA_DATA#_3 PEG_RX_0 E51 CFG8 Reserved
    PEG_RX_1 F48
    19 TXOUT_L0+ F44 LVDSA_DATA_0 PEG_RX_2 J55
    19 TXOUT_L1+ G47 J49 TMDS_B_HPD# CFG9 0 = Reverse Lane,15->0, 14->1
    LVDSA_DATA_1 PEG_RX_3 TMDS_B_HPD# 17
    19 TXOUT_L2+ F40 LVDSA_DATA_2 PEG_RX_4 M54
    A45 M50 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
    10/19
    B40
    LVDSA_DATA_3 PEG_RX_5
    PEG_RX_6 P52
    U47
    *
    LVDSB_DATA#_0 PEG_RX_7
    A41 LVDSB_DATA#_1 PEG_RX_8 AA49 0 = Enable
    F42 LVDSB_DATA#_2 PEG_RX_9 V54 CFG10 (PCIE Lookback enable)

    10/18
    For make layout clearance, del D48 V50 1 = Disable
    TP for channel B. 10/18 D40
    LVDSB_DATA#_3 PEG_RX_10
    PEG_RX_11 AB52
    AC47 CFG11 Reserved
    *
    LVDSB_DATA_0 PEG_RX_12

    PCI-EXPRESS
    C41 LVDSB_DATA_1 PEG_RX_13 AC53
    G43 LVDSB_DATA_2 PEG_RX_14 AD50 CFG[13:12] (XOR/ALLZ) 00 = Reserved
    B48 LVDSB_DATA_3 PEG_RX_15 AF52 01 = XOR Mode Enabled
    10 = All Z Mode Enabled
    For EMI. 9/26 L47 HDMI_C_TX2- C1036 1 2 0.1U_0402_16V4Z 11 = Normal Operation(Default)
    R68 1 2 75_0402_5% J27
    PEG_TX#_0
    PEG_TX#_1 F52 HDMI_C_TX1-
    P46 HDMI_C_TX0-
    C1037 1
    C1038 1
    2
    2
    0.1U_0402_16V4Z
    0.1U_0402_16V4Z
    HDMI_UMA_TX2-
    HDMI_UMA_TX1-
    HDMI_UMA_TX0-
    17
    17
    17 CFG[15:14] Reserved
    *
    TVA_DAC PEG_TX#_2

    TV
    R69 1 2 75_0402_5% E27 H54 HDMI_C_CLK- C1039 1 2 0.1U_0402_16V4Z HDMI_UMA_CLK- 17
    C R70 75_0402_5% TVB_DAC PEG_TX#_3 C
    1 2 G27 TVC_DAC PEG_TX#_4 L55
    PEG_TX#_5 T46 CFG16 (FSB Dynamic ODT) 0 = Disabled
    Del TV_LUMA & CRMA in 10/12. F26 TVA_RTN PEG_TX#_6 R53
    U49 1 = Enabled
    PEG_TX#_7
    PEG_TX#_8 T54
    Y46
    *
    PEG_TX#_9
    B34 TV_DCONSEL_0 PEG_TX#_10 AB46 CFG[18:17] Reserved
    D34 TV_DCONSEL_1 PEG_TX#_11 W53
    PEG_TX#_12 Y54
    AC49 CFG19 (DMI Lane Reversal) 0 = Normal Operation
    Tie to GND. 9/28
    PEG_TX#_13
    PEG_TX#_14 AF46
    AD54 (Lane number in Order)
    *
    PEG_TX#_15

    18 GMCH_CRT_B GMCH_CRT_B J29 J47 HDMI_C_TX2+ C1040 1 2 0.1U_0402_16V4Z HDMI_UMA_TX2+ 17 1 = Reverse Lane
    CRT_BLUE PEG_TX_0
    PEG_TX_1 F54 HDMI_C_TX1+ C1041 1 2 0.1U_0402_16V4Z HDMI_UMA_TX1+ 17
    18 GMCH_CRT_G GMCH_CRT_G G29 N47 HDMI_C_TX0+ C1042 1 2 0.1U_0402_16V4Z HDMI_UMA_TX0+ 17
    CRT_GREEN PEG_TX_2
    H52 HDMI_C_CLK+ C1043 1 2 0.1U_0402_16V4Z CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational.
    18 GMCH_CRT_R GMCH_CRT_R F30 CRT_RED
    PEG_TX_3
    PEG_TX_4 L53
    HDMI_UMA_CLK+ 17
    *

    VGA
    PEG_TX_5 R47 1 = PCIE/SDVO are operating simu.
    E29 CRT_IRTN PEG_TX_6 R55
    PEG_TX_7 T50
    18 GMCH_CRT_CLK D36 CRT_DDC_CLK PEG_TX_8 T52
    18 GMCH_CRT_DATA C35 CRT_DDC_DATA PEG_TX_9 W47
    18 GMCH_CRT_HSYNC R71 1 2 30.1_0402_1% CRT_HSYNC_R J33 AA47
    CRT_HSYNC PEG_TX_10 R72 @ 2.21K_0402_1%
    D32 CRT_TVO_IREF PEG_TX_11 W55 8 CFG5 1 2
    18 GMCH_CRT_VSYNC R73 1 2 30.1_0402_1% CRT_VSYNC_R G31 Y52
    CRT_VSYNC PEG_TX_12 R74 @ 2.21K_0402_1%
    PEG_TX_13 AB50 8 CFG6 1 2
    PEG_TX_14 AE47
    2

    Close to pin D32 and keep AD52 R75 1 2 @ 2.21K_0402_1%


    PEG_TX_15 8 CFG7
    R76
    30mil space to other 1.02K_0402_1% R77 1 2 @ 2.21K_0402_1%
    8 CFG9
    part/trace. CANTIGA GMCH SFF_FCBGA1363
    B R78 @ 2.21K_0402_1% B
    8 CFG10 1 2
    1

    R79 1 2 @ 2.21K_0402_1%
    8 CFG12
    R80 1 2 @ 2.21K_0402_1%
    8 CFG13
    R81 1 2 @ 2.21K_0402_1%
    8 CFG16

    GMCH_CRT_B Remove R84 ~ R86 since


    GMCH_CRT_G already have 75ohm of +3VS
    Del R82, R83. 10/18 page17. 10/27
    GMCH_CRT_R
    R82 1 2 @ 4.02K_0402_1%
    8 CFG19
    R83 1 2 @ 4.02K_0402_1%
    8 CFG20
    1

    1
    150_0402_1%

    150_0402_1%

    150_0402_1%
    R13

    R15

    R16
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cantiga(3/6)-LVDS/TV/CRT
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 10 of 43
    5 4 3 2 1
    5 4 3 2 1

    9/27
    9/27 +1.05VM_DPLLA +VCCP +V1.05VM_AXF 9/27 +VCCP
    R84
    Change to 330u_R9, 1 2 R85 1 2 0_0603_5%
    BLM18PG181SN1D_0603
    casue high +VCCP

    10U_0805_10V4Z~D

    1U_0603_10V4Z
    0.1U_0402_16V4Z
    1

    220U_D2_4VM_R15
    limitation. 12/14

    @
    1 1 1
    U3H +
    +3VS +3VS_DAC_CRT

    C81

    C80

    C82

    C83
    BLM18PG181SN1D_0603 R13
    R86 VTT_1 2 2 2 2

    330U_D2E_2.5VM_R9
    VTT_2 T12

    0.47U_0603_10V7K

    2.2U_0805_16V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z
    2 1 J31 VCCA_CRT_DAC VTT_3 R11 1
    +3VS_DAC_BG VTT_4 T10 1 1 1 1
    +3VS
    0.1U_0402_16V4Z

    10U_0603_6.3V6M

    0.1U_0402_16V4Z

    0.01U_0402_16V7K
    R9 + 9/27
    R87 VTT_5
    1 1 1 1 VTT_6 T8

    C87
    C85

    C86

    C88

    C84
    2 1 L31 R7

    CRT
    BLM18PG181SN1D_0603 VCCA_DAC_BG VTT_7 2 2 2 2 2 +1.05VM_DPLLB +VCCP +1.5V_MEM_SM_CK +1.5V

    0.01U_0402_16V7K
    D M33 VSSA_DAC_BG VTT_8 T6 9/27 D
    C89

    C90

    C91

    C92 @ R88
    R5

    22U_0805_6.3V
    2 2 2 2 VTT_9 R89
    1 1 9/27 VTT_10 T4 1 2 1 2 0_0805_5%
    R3 BLM18PG181SN1D_0603
    VTT_11

    0.1U_0402_16V4Z
    +1.05VM_DPLLA J45 VCCA_DPLLA VTT_12 T2 1

    2
    C93

    C94

    220U_D2_4VM_R15
    @

    0_0603_5%
    R1 1

    VTT
    2 2 VTT_13

    0.1U_0402_16V4Z

    10U_0805_6.3V6M
    L49 +
    +1.05VM_DPLLB VCCA_DPLLB +3VS_TVDAC +3VS
    1 1

    PLL

    C96

    C95

    R90
    install 0.1U & 10U for wavy issue. 7/29 +1.05VM_HPLL AF10 VCCA_HPLL 2 2
    R91

    C97

    C98
    +1.05VM_MPLL AE1 VCCA_MPLL VCCA_TV_DAC K30 1 2
    +1.8V_TXLVDS 2 2

    10U_0805_6.3V6M
    BLM18PG181SN1D_0603

    TV

    0.01U_0402_16V7K

    0.1U_0402_16V4Z
    9/27 1
    change 0.1U to 22U for wavy issue. 5/20 @ R92 0_0402_5% 1 1

    A PEG A LVDS
    +VCC_HDA
    +1.5VS_PEG_BG
    10mA U43 VCCA_LVDS1 +1.05VM_HPLL +VCCP

    C99
    1 U41 A31 1 2

    D TV/CRT HDA
    VCCA_LVDS2 VCC_HDA 2

    C100

    C101
    C102 R93
    1000P_0402_50V7K 2 2
    V44 VSSA_LVDS 1 2
    BLM18PG181SN1D_0603
    2

    0.1U_0402_16V4Z

    4.7U_0805_10V4Z
    VCCD_QDAC N34 +1.5VS_QDAC
    +1.5VS R94 1 2 0_0603_5% AJ43 1 1
    VCCA_PEG_BG
    VCCD_TVDAC N32 +1.5VS_TVDAC
    1 Disable HDMI audio

    C103

    C104
    C105
    2 2
    9/27 +1.05VM_PEGPLL AG43 VCCA_PEG_PLL
    0.1U_0402_16V4Z
    2
    9/27 +VCC_HDA +1.5VS
    9/27
    AW24 VCCA_SM_1
    AU24
    +VCCP +1.05VM_A_SM
    AW22
    AU22
    VCCA_SM_2
    VCCA_SM_3
    VCCA_SM_4
    POWER R321 1 2 0_0603_5%
    +1.05VM_MPLL
    R95
    +VCCP +1.5VS_TVDAC +1.5VS

    AU21 1 1 2 R96
    VCCA_SM_5

    0.1U_0402_16V4Z
    AW20 BLM18PG181SN1D_0603 1 2
    VCCA_SM_6

    C1045

    10U_0805_6.3V6M
    BLM18PG181SN1D_0603

    0.1U_0402_16V4Z
    AU19 VCCA_SM_7

    0.01U_0402_16V7K

    0.1U_0402_16V4Z
    C106

    C107
    R97 1 2 0_0805_5% AW18 Enable HDMI audio 1 1

    A SM
    C VCCA_SM_8 2 C
    AU18 VCCA_SM_9 1 1
    10U_0805_6.3V6M

    4.7U_0805_10V4Z

    1U_0603_10V4Z
    150U_D2_6.3VM

    1 1 1 1 AW16 VCCA_SM_10
    AU16 VCCA_SM_11 2 2

    C108

    C109
    + AT16 VCCA_SM_12 2 2
    C111

    C112

    C113

    AR16 VCCA_SM_13
    2 2 2
    C110

    AU15 VCCA_SM_14
    2 AT15 VCCA_SM_15 9/27
    AR15 VCCA_SM_16
    AW14 VCCA_SM_17 VCC_AXF_1 M25 +V1.05VM_AXF +1.8V_TXLVDS +1.8V
    9/21
    N24

    AXF
    VCC_AXF_2
    AT24 VCCA_SM_NCTF_1 VCC_AXF_3 M23 +VCCP
    AR24 R98 1 2 0_0603_5% +VCC_PEG
    VCCA_SM_NCTF_2

    1000P_0402_50V7K
    AT22 VCCA_SM_NCTF_3
    AR22 VCCA_SM_NCTF_4
    AT21 1 1 R99 1 2 0_0805_5%
    VCCA_SM_NCTF_5 C115
    AR21 VCCA_SM_NCTF_6 VCC_SM_CK_1 BK24 +1.5V_MEM_SM_CK

    4.7U_0805_10V4Z

    10U_0805_6.3V6M

    220U_D2_4VM_R15
    AT19 BL23 @ 10U_0805_6.3V6M 1

    SM CK
    VCCA_SM_NCTF_7 VCC_SM_CK_2

    C114
    AR19 VCCA_SM_NCTF_8 VCC_SM_CK_3 BJ23 1 1
    +1.05VM_A_SM_CK 2 2 +
    AT18 VCCA_SM_NCTF_9 VCC_SM_CK_4 BK22
    AR18 VCCA_SM_NCTF_10 +3VS_HV

    C117

    C118

    C116
    2 2 2
    9/27
    VCC_TX_LVDS T41 80mA +1.8V_TXLVDS
    R100 1 2 0_0603_5% AU27 9/27
    VCCA_SM_CK_4 +1.05VM_PEGPLL +VCCP
    AU28 VCCA_SM_CK_3 VCC_HV_1 C33
    10U_0805_6.3V6M

    0.1U_0402_16V4Z

    AU29 A33 L1 9/21


    VCCA_SM_CK_2 VCC_HV_2
    1 1 AU31 1 2
    HV

    VCCA_SM_CK_1

    0.1U_0402_16V4Z
    AT31 BLM18PG121SN1D_0603
    VCCA_SM_CK_NCTF_1 +1.05VM_DMI

    0.1U_0402_16V4Z

    10U_0805_10V4Z~D
    AR31 1 9/29 +VCCP
    VCCA_SM_CK_NCTF_2
    C119

    C120

    AT29 VCCA_SM_CK_NCTF_3 VCC_PEG_1 AB44 +VCC_PEG 1 1


    2 2 AR29 Y44
    VCCA_SM_CK_NCTF_4 VCC_PEG_2

    C121
    AT28 AC43 R101 1 2 0_0603_5%
    PEG

    VCCA_SM_CK_NCTF_5 VCC_PEG_3 2

    C122

    C123

    0.1U_0402_16V4Z
    AR28 VCCA_SM_CK_NCTF_6 VCC_PEG_4 AA43
    2 2
    AT27 VCCA_SM_CK_NCTF_7 1
    B AR27 VCCA_SM_CK_NCTF_8
    B

    C124
    VCC_DMI_1 AM44 +1.05VM_DMI 2
    VCC_DMI_2 AN43
    AL43 9/29
    DMI

    VCC_DMI_3
    +1.05VM_HPLL AH12 VCCD_HPLL
    0.1U_0402_16V4Z

    +1.05VM_PEGPLL AE43 VCCD_PEG_PLL +VCCP_D


    C125

    1
    +VTTLF1
    0.1U_0402_16V4Z

    9/27 K14
    VTTLF

    VTTLF1
    C126

    1 M46 Y12 +VTTLF2


    VCCD_LVDS_1 VTTLF2
    LVDS

    +1.8V R102 2 1 0_0603_5% 30mA L45 P2 +VTTLF3


    2 VCCD_LVDS_2 VTTLF3 R103 1
    +VCCP 2 1 2 10_0402_5% R104 1 2 0_0402_5% +3VS_HV
    1U_0603_10V4Z

    0.47U_0603_10V7K

    0.47U_0603_10V7K

    0.47U_0603_10V7K

    1 D1 CH751H-40_SC76
    2
    1 1 1 +3VS
    +1.8V_LVDS CANTIGA GMCH SFF_FCBGA1363
    C127

    2
    C128

    C129

    C130

    2 2 2
    +1.5VS_QDAC +1.5VS

    R105
    1 2
    BLM18PG181SN1D_0603

    0.01U_0402_16V7K

    0.1U_0402_16V4Z

    4.7U_0603_6.3V
    1 1 1

    C131

    C132

    C133
    2 2 2

    install 4.7U for wavy issue. 7/29


    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cantiga(4/6)-PWR
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-5541P
    Date: Thursday, September 10, 2009 Sheet 11 of 43
    5 4 3 2 1
    5 4 3 2 1

    U3G

    +VCCP
    3000mA
    Extnal Graphic: 1210.34mA VCC_AXG_NCTF_1 T32
    BB36 U31
    integrated Graphic: 1930.4mA BE35
    VCC_SM_1 VCC_AXG_NCTF_2
    T31
    VCC_SM_2 VCC_AXG_NCTF_3
    +1.5V AW34 VCC_SM_3 VCC_AXG_NCTF_4 R31
    U3F AW32 U29
    VCC_SM_4 VCC_AXG_NCTF_5

    330U_D2E_2.5VM_R9

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    0.01U_0402_16V7K

    0.1U_0402_16V4Z

    0.22U_0402_10V4Z

    4.7U_0805_10V4Z
    9/21 BK30 VCC_SM_5 VCC_AXG_NCTF_6 T29 1 1 1
    1 BH30 VCC_SM_6 VCC_AXG_NCTF_7 R29
    1 1 2 BF30 VCC_SM_7 VCC_AXG_NCTF_8 U28
    +VCCP

    C137

    C138

    C139

    C140
    +

    C134

    C135

    C136
    BD30 VCC_SM_8 VCC_AXG_NCTF_9 U27
    D 2 2 2 D
    BB30 VCC_SM_9 VCC_AXG_NCTF_10 T27
    AW30 VCC_SM_10 VCC_AXG_NCTF_11 R27
    2 2 2 1
    AT41 VCC_1 BL29 VCC_SM_11 VCC_AXG_NCTF_12 U25
    AR41 VCC_2 BJ29 VCC_SM_12 VCC_AXG_NCTF_13 T25
    AN41 VCC_3 BG29 VCC_SM_13 VCC_AXG_NCTF_14 R25
    AJ41 VCC_4 BE29 VCC_SM_14 VCC_AXG_NCTF_15 U24
    AH41 VCC_5 BC29 VCC_SM_15 VCC_AXG_NCTF_16 U22

    POWER
    AD41 VCC_6 BA29 VCC_SM_16 VCC_AXG_NCTF_17 T22
    AC41 VCC_7 AY29 VCC_SM_17 VCC_AXG_NCTF_18 R22
    Y41 VCC_8 BK28 VCC_SM_18 VCC_AXG_NCTF_19 U21
    W41 VCC_9 BH28 VCC_SM_19 VCC_AXG_NCTF_20 T21
    AT40 VCC_10 BF28 VCC_SM_20 VCC_AXG_NCTF_21 R21
    220U_D2_4VM_R15

    0.22U_0402_10V4Z

    0.22U_0402_10V4Z

    0.1U_0402_16V4Z
    AM40 VCC_11 BD28 VCC_SM_21 VCC_AXG_NCTF_22 AM19
    10U_0805_6.3V6M

    1 AL40 VCC_12 BB28 VCC_SM_22 VCC_AXG_NCTF_23 AL19


    1 1 1 1 BL27 VCC_SM_23 VCC_AXG_NCTF_24 AH19
    C141

    C142

    C143

    C144

    C145
    + AJ40 BJ27 AG19
    VCC_13 VCC_SM_24 VCC_AXG_NCTF_25

    VCC CORE
    AH40 VCC_14 BG27 VCC_SM_25 VCC_AXG_NCTF_26 AE19

    VCC SM
    AG40 VCC_15 BE27 VCC_SM_26 VCC_AXG_NCTF_27 AD19
    2 2 2 2 2
    AE40 BC27 AC19

    VCC GFX NCTF


    VCC_16 VCC_SM_27 VCC_AXG_NCTF_28
    AD40 VCC_17 BA27 VCC_SM_28 VCC_AXG_NCTF_29 W19
    AC40 VCC_18 AY27 VCC_SM_29 VCC_AXG_NCTF_30 U19
    AA40 VCC_19 AW26 VCC_SM_30 VCC_AXG_NCTF_31 AM18
    Y40 VCC_20 BF24 VCC_SM_31 VCC_AXG_NCTF_32 AL18
    AN35 VCC_21 BL19 VCC_SM_32 VCC_AXG_NCTF_33 AJ18
    AM35 VCC_22 BB16 VCC_SM_33 VCC_AXG_NCTF_34 AH18
    AJ35 +VCCP AG18
    VCC_23 VCC_AXG_NCTF_35
    AH35 VCC_24 VCC_AXG_NCTF_36 AE18
    AD35 VCC_25 VCC_AXG_NCTF_37 AD18
    AC35 VCC_26 VCC_AXG_NCTF_38 AC18
    W35 VCC_27 W32 VCC_AXG_1 VCC_AXG_NCTF_39 AA18
    AM34 VCC_28 AG31 VCC_AXG_2 VCC_AXG_NCTF_40 Y18

    10U_0805_6.3V

    10U_0805_6.3V

    1U_0603_10V4Z

    0.1U_0402_16V4Z
    AL34 VCC_29 9/21 1 AE31 VCC_AXG_3 VCC_AXG_NCTF_41 W18

    C147

    C148

    C149

    C150
    C C
    AJ34 VCC_30 1 1 1 1 AD31 VCC_AXG_4 VCC_AXG_NCTF_42 U18
    AH34 C146 + AC31 T18
    VCC_31 +VCCP 330U_D2E_2.5VM_R9 VCC_AXG_5 VCC_AXG_NCTF_43
    AG34 VCC_32 AA31 VCC_AXG_6 VCC_AXG_NCTF_44 R18
    AE34 VCC_33 Y31 VCC_AXG_7
    2 2 2 2 2
    POWER
    AD34 VCC_34 W31 VCC_AXG_8
    VCC_NCTF_1 AT38 AH29 VCC_AXG_9
    AC34 VCC_35 VCC_NCTF_2 AR38 AG29 VCC_AXG_10
    AA34 VCC_36 VCC_NCTF_3 AN38 AE29 VCC_AXG_11
    VCC_NCTF_4 AM38 AD29 VCC_AXG_12 VCC_AXG_62 AJ16
    Y34 VCC_37 VCC_NCTF_5 AL38 AC29 VCC_AXG_13 VCC_AXG_63 AH16
    W34 VCC_38 VCC_NCTF_6 AG38 AA29 VCC_AXG_14 VCC_AXG_64 AD16
    AM32 VCC_39 VCC_NCTF_7 AE38 Y29 VCC_AXG_15 VCC_AXG_65 AC16
    AL32 VCC_40 VCC_NCTF_8 AA38 W29 VCC_AXG_16 VCC_AXG_66 AA16
    AJ32 VCC_41 VCC_NCTF_9 Y38 AH28 VCC_AXG_17 VCC_AXG_67 U16
    AH32 VCC_42 VCC_NCTF_10 W38 AG28 VCC_AXG_18 VCC_AXG_68 T16

    VCC GFX
    AE32 VCC_43 VCC_NCTF_11 U38 AE28 VCC_AXG_19 VCC_AXG_69 R16
    AD32 VCC_44 VCC_NCTF_12 T38 AA28 VCC_AXG_20 VCC_AXG_70 AM15
    AA32 VCC_45 VCC_NCTF_13 R38 AH27 VCC_AXG_21 VCC_AXG_71 AL15
    AM31 VCC_46 VCC_NCTF_14 AT37 6326.84mA AG27 VCC_AXG_22 VCC_AXG_72 AJ15
    AL31 VCC_47 VCC_NCTF_15 AR37 AE27 VCC_AXG_23 VCC_AXG_73 AH15
    AJ31 VCC_48 VCC_NCTF_16 AN37 AD27 VCC_AXG_24 VCC_AXG_74 AG15
    AH31 VCC_49 VCC_NCTF_17 AM37 AC27 VCC_AXG_25 VCC_AXG_75 AE15
    AM29 VCC_50 VCC_NCTF_18 AL37 AA27 VCC_AXG_26 VCC_AXG_76 AA15
    AL29 VCC_51 VCC_NCTF_19 AJ37 Y27 VCC_AXG_27 VCC_AXG_77 Y15
    AM28 VCC_52 VCC_NCTF_20 AH37 W27 VCC_AXG_28 VCC_AXG_78 W15
    AL28 VCC_53 VCC_NCTF_21 AG37 AH25 VCC_AXG_29 VCC_AXG_79 U15
    AJ28 VCC_54 VCC_NCTF_22 AE37 AD25 VCC_AXG_30 VCC_AXG_80 T15
    AM27 VCC_55 VCC_NCTF_23 AD37 AC25 VCC_AXG_31
    AL27 VCC_56 VCC_NCTF_24 AC37 W25 VCC_AXG_32
    VCC NCTF

    AM25 VCC_57 VCC_NCTF_25 AA37 AJ24 VCC_AXG_33


    AL25 VCC_58 VCC_NCTF_26 Y37 AH24 VCC_AXG_34
    AJ25 VCC_59 VCC_NCTF_27 W37 AG24 VCC_AXG_35
    B B
    AM24 VCC_60 VCC_NCTF_28 U37 AE24 VCC_AXG_36
    N36 VCC_61 VCC_NCTF_29 T37 AD24 VCC_AXG_37
    VCC_NCTF_30 R37 AC24 VCC_AXG_38
    VCC_NCTF_31 AT35 AA24 VCC_AXG_39
    VCC_NCTF_32 AR35 Y24 VCC_AXG_40
    VCC_NCTF_33 U35 W24 VCC_AXG_41
    VCC_NCTF_34 AT34 AM22 VCC_AXG_42
    VCC_NCTF_35 AR34 AL22 VCC_AXG_43
    VCC_NCTF_36 U34 AJ22 VCC_AXG_44

    VCC GFX
    VCC_NCTF_37 T34 AH22 VCC_AXG_45
    VCC_NCTF_38 R34 AG22 VCC_AXG_46
    AE22 VCC_AXG_47
    AD22 VCC_AXG_48
    AC22 VCC_AXG_49
    AA22 AU45 VCCSM_LF1
    VCC_AXG_50 VCC_SM_LF1

    VCC SM LF
    AM21 BF52 VCCSM_LF2
    VCC_AXG_51 VCC_SM_LF2 VCCSM_LF3
    AL21 VCC_AXG_52 VCC_SM_LF3 BB38
    AJ21 BA19 VCCSM_LF4
    VCC_AXG_53 VCC_SM_LF4 VCCSM_LF5
    AH21 VCC_AXG_54 VCC_SM_LF5 BE9

    C151 0.22U_0603_10V7K

    C152 0.22U_0603_10V7K

    C153 0.47U_0402_6.3V6K

    C154 1U_0603_10V4Z

    C155 1U_0603_10V4Z
    AD21 AU9 VCCSM_LF6 1 1 1 1 1
    VCC_AXG_55 VCC_SM_LF6 VCCSM_LF7
    AC21 VCC_AXG_56 VCC_SM_LF7 AL9

    C156 0.1U_0402_16V4Z

    C157 0.1U_0402_16V4Z
    AA21 VCC_AXG_57 1 1
    Y21 VCC_AXG_58 2 2 2 2 2
    W21 VCC_AXG_59
    AM16 VCC_AXG_60
    CANTIGA GMCH SFF_FCBGA1363 2 2
    AL16 VCC_AXG_61

    PAD T43 AG13 VCC_AXG_SENSE


    PAD T44 AE13 VSS_AXG_SENSE

    A A

    CANTIGA GMCH SFF_FCBGA1363

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cantiga(5/6)-PWR/GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 12 of 43
    5 4 3 2 1
    5 4 3 2 1

    U3I

    BA55 C43 U3J


    VSS_1 VSS_100
    AU55 VSS_2 VSS_101 A43
    AN55 VSS_3 VSS_102 BD42 AN25 VSS_199 VSS_300 AM8
    AJ55 VSS_4 VSS_103 H42 AG25 VSS_200 VSS_301 AK8
    AE55 VSS_5 VSS_104 BG41 AE25 VSS_201 VSS_302 AH8
    AA55 VSS_6 VSS_105 AY41 AA25 VSS_202 VSS_303 AF8
    U55 VSS_7 VSS_106 AU41 Y25 VSS_203 VSS_304 AD8
    N55 VSS_8 VSS_107 AM41 E25 VSS_204 VSS_305 AB8
    BD54 VSS_9 VSS_108 AL41 A25 VSS_205 VSS_306 Y8
    BG53 VSS_10 VSS_109 AG41 BD24 VSS_206 VSS_307 V8
    AJ53 VSS_11 VSS_110 AE41 AN24 VSS_207 VSS_308 P8
    AE53 VSS_12 VSS_111 AA41 AL24 VSS_208 VSS_309 M8
    D D
    AA53 VSS_13 VSS_112 R41 H24 VSS_209 VSS_310 K8
    U53 VSS_14 VSS_113 M41 BG23 VSS_210 VSS_311 H8
    N53 VSS_15 VSS_114 E41 AY23 VSS_211 VSS_312 BJ7
    J53 VSS_16 VSS_115 BD40 E23 VSS_212 VSS_313 E7
    G53 VSS_17 VSS_116 AU40 BD22 VSS_213 VSS_314 BF6
    E53 VSS_18 VSS_117 AR40 BB22 VSS_214 VSS_315 BC5
    K52 VSS_19 VSS_118 AN40 AN22 VSS_215 VSS_316 BA5
    BG51 VSS_20 VSS_119 W40 Y22 VSS_216 VSS_317 AW5
    BA51 VSS_21 VSS_120 U40 W22 VSS_217 VSS_318 AU5
    AW51 VSS_22 VSS_121 T40 H22 VSS_218 VSS_319 AR5
    AU51 VSS_23 VSS_122 R40 BL21 VSS_219 VSS_320 AN5
    AR51 VSS_24 VSS_123 K40 BG21 VSS_220 VSS_321 AL5
    AN51 VSS_25 VSS_124 H40 AY21 VSS_221 VSS_322 AJ5
    AL51 VSS_26 VSS_125 BL39 AN21 VSS_222 VSS_323 AG5
    AJ51 VSS_27 VSS_126 BG39 AG21 VSS_223 VSS_324 AE5
    AG51 VSS_28 VSS_127 BA39 AE21 VSS_224 VSS_325 AC5
    AE51 VSS_29 VSS_128 E39 M21 VSS_225 VSS_326 AA5
    AC51 VSS_30 VSS_129 C39 E21 VSS_226 VSS_327 W5
    AA51 VSS_31 VSS_130 A39 A21 VSS_227 VSS_328 U5
    W51 VSS_32 VSS_131 BD38 BD20 VSS_228 VSS_329 N5
    U51 AU38 H20 L5
    R51
    N51
    VSS_33
    VSS_34
    VSS_35
    VSS VSS_132
    VSS_133
    VSS_134
    H38
    BG37
    BG19
    AY19
    VSS_229
    VSS_230
    VSS_231
    VSS VSS_330
    VSS_331
    VSS_332
    J5
    G5
    L51 VSS_36 VSS_135 AU37 M19 VSS_232 VSS_333 C5
    J51 VSS_37 VSS_136 M37 E19 VSS_233 VSS_334 BH4
    G51 VSS_38 VSS_137 E37 BD18 VSS_234 VSS_335 BE3
    C51 VSS_39 VSS_138 BD36 N18 VSS_235 VSS_336 U3
    BK50 VSS_40 VSS_139 AW36 H18 VSS_236 VSS_337 E3
    AM50 VSS_41 VSS_140 H36 BL17 VSS_237 VSS_338 BC1
    K50 VSS_42 VSS_141 BL35 BG17 VSS_238 VSS_339 AW1
    BG49 VSS_43 VSS_142 BG35 AY17 VSS_239 VSS_340 AR1
    E49 VSS_44 VSS_143 AY35 M17 VSS_240 VSS_341 AL1
    C C
    C49 VSS_45 VSS_144 AU35 E17 VSS_241 VSS_342 AG1
    BD48 VSS_46 VSS_145 AL35 A17 VSS_242 VSS_343 AC1
    BB48 VSS_47 VSS_146 AG35 BD16 VSS_243 VSS_344 W1
    AY48 VSS_48 VSS_147 AE35 AN16 VSS_244 VSS_345 N1
    AV48 VSS_49 VSS_148 AA35 AG16 VSS_245 VSS_346 J1
    AT48 VSS_50 VSS_149 Y35 AE16 VSS_246 VSS_347 AU43
    AP48 VSS_51 VSS_150 M35 Y16 VSS_247 VSS_348 BB42
    AM48 VSS_52 VSS_151 E35 W16 VSS_248 VSS_349 AW38
    AK48 VSS_53 VSS_152 A35 N16 VSS_249 VSS_350 BA35
    AH48 VSS_54 VSS_153 BD34 H16 VSS_250 VSS_351 L29
    AF48 VSS_55 VSS_154 AU34 BG15 VSS_251 VSS_352 N28
    AD48 VSS_56 VSS_155 AN34 AY15 VSS_252 VSS_353 N22
    AB48 VSS_57 VSS_156 H34 AN15 VSS_253 VSS_354 N20
    Y48 VSS_58 VSS_157 BL33 AD15 VSS_254 VSS_355 N14
    V48 VSS_59 VSS_158 BG33 AC15 VSS_255 VSS_356 AL13
    T48 VSS_60 VSS_159 AY33 R15 VSS_256 VSS_357 B10
    P48 VSS_61 VSS_160 E33 M15 VSS_257 VSS_358 AN13
    M48 VSS_62 VSS_161 BD32 E15 VSS_258
    K48 VSS_63 VSS_162 AU32 BD14 VSS_259 VSS_359 N42
    H48 VSS_64 VSS_163 AN32 H14 VSS_260 VSS_360 N40
    BL47 VSS_65 VSS_164 AG32 BL13 VSS_261 VSS_361 N38
    BG47 VSS_66 VSS_165 AC32 BG13 VSS_262 VSS_362 M39
    E47 VSS_67 VSS_166 Y32 AY13 VSS_263
    C47 VSS_68 VSS_167 H32 AU13 VSS_264
    A47 VSS_69 VSS_168 B32 AR13 VSS_265 VSS_NCTF_1 AJ38
    BD46 VSS_70 VSS_169 BJ31 AJ13 VSS_266 VSS_NCTF_2 AH38
    AY46 VSS_71 VSS_170 BG31 AC13 VSS_267 VSS_NCTF_3 AD38
    AM46 VSS_72 VSS_171 AY31 AA13 VSS_268 VSS_NCTF_4 AC38
    AK46 VSS_73 VSS_172 AN31 W13 VSS_269 VSS_NCTF_5 T35
    AH46 M31 U13 R35

    VSS NCTF
    VSS_74 VSS_173 VSS_270 VSS_NCTF_6
    BG45 VSS_75 VSS_174 E31 M13 VSS_271 VSS_NCTF_7 AT32
    AE45 VSS_76 VSS_175 N30 E13 VSS_272 VSS_NCTF_8 AR32
    B B
    AC45 VSS_77 VSS_176 H30 A13 VSS_273 VSS_NCTF_9 U32
    AA45 VSS_78 VSS_177 AN29 BD12 VSS_274 VSS_NCTF_10 R32
    W45 VSS_79 VSS_178 AJ29 AV12 VSS_275 VSS_NCTF_11 T28
    R45 VSS_80 VSS_179 M29 AP12 VSS_276 VSS_NCTF_12 R28
    N45 VSS_81 VSS_180 A29 AM12 VSS_277 VSS_NCTF_13 AT25
    E45 VSS_82 VSS_181 AW28 AK12 VSS_278 VSS_NCTF_14 AR25
    BD44 VSS_83 VSS_182 AN28 AB12 VSS_279 VSS_NCTF_15 T24
    BB44 VSS_84 VSS_183 AD28 V12 VSS_280 VSS_NCTF_16 R24
    AV44 VSS_85 VSS_184 AC28 P12 VSS_281 VSS_NCTF_17 AN19
    AK44 VSS_86 VSS_185 Y28 H12 VSS_282 VSS_NCTF_18 AJ19
    AH44 VSS_87 VSS_186 W28 BG11 VSS_283 VSS_NCTF_19 AA19
    AF44 VSS_88 VSS_187 H28 AG11 VSS_284 VSS_NCTF_20 Y19
    AD44 VSS_89 VSS_188 F28 E11 VSS_285 VSS_NCTF_21 T19
    K44 VSS_90 VSS_189 AN27 BD10 VSS_286 VSS_NCTF_22 R19
    H44 VSS_91 VSS_190 AJ27 AY10 VSS_287 VSS_NCTF_23 AN18
    BL43 VSS_92 VSS_191 M27 AP10 VSS_288
    BG43 VSS_93 VSS_192 BF26 H10 VSS_289
    AY43 VSS_94 VSS_193 BD26 BL9 VSS_290
    AR43 VSS_95 VSS_194 N26 BG9 VSS_291
    W43 VSS_96 VSS_195 H26 E9 VSS_292
    R43 VSS_97 VSS_196 BJ25 A9 VSS_293 VSS_SCB_1 BL55
    M43 AY25 BD8 BL1

    VSS SCB
    VSS_98 VSS_197 VSS_294 VSS_SCB_2
    E43 VSS_99 VSS_198 AU25 BB8 VSS_295 VSS_SCB_3 A55
    AY8 VSS_296 VSS_SCB_4 D1
    AV8 VSS_297 VSS_SCB_5 B55
    CANTIGA GMCH SFF_FCBGA1363 AT8 B2
    VSS_298 VSS_SCB_6
    AP8 VSS_299 VSS_SCB_7 A4

    CANTIGA GMCH SFF_FCBGA1363

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cantiga(6/6)-GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 13 of 43
    5 4 3 2 1
    5 4 3 2 1

    9 DDR_A_DQS#[0..7] +V_DDR_MCH_REF +1.5V +1.5V


    9 DDR_A_D[0..63] JP3
    1 VREF_DQ VSS1 2
    3 4 DDR_A_D4
    9 DDR_A_DM[0..7] +1.5V VSS2 DQ4
    DDR_A_D0 5 6 DDR_A_D5
    DQ0 DQ5

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z
    9 DDR_A_DQS[0..7] DDR_A_D1 7 8
    DQ1 VSS3 DDR_A_DQS#0
    1 1 9 VSS4 DQS#0 10

    C1311

    C1312
    9 DDR_A_MA[0..14] DDR_A_DM0 11 12 DDR_A_DQS0
    DM0 DQS0

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    @ @ 13 14
    DDR_A_D2 VSS5 VSS6 DDR_A_D6
    1 1 15 DQ2 DQ6 16
    2 2

    C1065

    C1066
    DDR_A_D3 17 18 DDR_A_D7
    DQ3 DQ7
    19 VSS7 VSS8 20
    D DDR_A_D8 DDR_A_D12 D
    For EMI 21 DQ8 DQ12 22
    2 2 DDR_A_D9 DDR_A_D13
    23 DQ9 DQ13 24
    25 VSS9 VSS10 26
    DDR_A_DQS#1 27 28 DDR_A_DM1
    DDR_A_DQS1 DQS#1 DM1 SM_DRAMRST#
    Layout Note: 29 DQS1 RESET# 30 SM_DRAMRST# 8,15
    31 VSS11 VSS12 32
    Place near JP3 DDR_A_D10 33 34 DDR_A_D14
    DDR_A_D11 DQ10 DQ14 DDR_A_D15
    35 DQ11 DQ15 36
    37 VSS13 VSS14 38
    DDR_A_D16 39 40 DDR_A_D20
    DDR_A_D17 DQ16 DQ20 DDR_A_D21
    41 DQ17 DQ21 42
    43 VSS15 VSS16 44
    DDR_A_DQS#2 45 46 DDR_A_DM2
    DDR_A_DQS2 DQS#2 DM2
    47 DQS2 VSS17 48
    49 50 DDR_A_D22
    +1.5V DDR_A_D18 VSS18 DQ22 DDR_A_D23
    51 DQ18 DQ23 52
    DDR_A_D19 53 54
    DQ19 VSS19 DDR_A_D28
    55 VSS20 DQ28 56
    DDR_A_D24 57 58 DDR_A_D29
    DQ24 DQ29
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    DDR_A_D25 59 60
    DQ25 VSS21 DDR_A_DQS#3
    2 2 2 2 2 2 1 1 1 1 61 VSS22 DQS#3 62
    C1313

    C1314

    C1315

    C1316

    C1317

    C1318

    C167

    C168

    C169

    C1319
    DDR_A_DM3 63 64 DDR_A_DQS3
    DM3 DQS3
    65 VSS23 VSS24 66
    DDR_A_D26 67 68 DDR_A_D30
    1 1 1 1 1 1 2 2 2 2 DDR_A_D27 DQ26 DQ30 DDR_A_D31
    69 DQ27 DQ31 70
    71 VSS25 VSS26 72

    DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
    8 DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA 8
    75 VDD1 VDD2 76
    77 NC1 A15 78 T147
    C DDR_A_BS2 DDR_A_MA14 C
    9 DDR_A_BS2 79 BA2 A14 80
    81 VDD3 VDD4 82
    DDR_A_MA12 83 84 DDR_A_MA11
    DDR_A_MA9 A12/BC# A11 DDR_A_MA7
    85 A9 A7 86
    87 VDD5 VDD6 88
    DDR_A_MA8 89 90 DDR_A_MA6
    DDR_A_MA5 A8 A6 DDR_A_MA4
    Layout Note: 91 A5 A4 92
    93 94
    Place near JP3.203,204 DDR_A_MA3 95
    VDD7 VDD8
    96 DDR_A_MA2
    DDR_A_MA1 A3 A2 DDR_A_MA0
    97 A1 A0 98
    99 VDD9 VDD10 100
    M_CLK_DDR0 101 102 M_CLK_DDR1
    8 M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 8
    M_CLK_DDR#0 103 104 M_CLK_DDR#1
    8 M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 8
    105 VDD11 VDD12 106
    DDR_A_MA10 107 108 DDR_A_BS1
    A10/AP BA1 DDR_A_BS1 9
    DDR_A_BS0 109 110 DDR_A_RAS#
    9 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 9
    111 VDD13 VDD14 112
    +0.75VS DDR_A_WE# 113 114 DDR_CS0_DIMMA#
    9 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 8
    DDR_A_CAS# 115 116 M_ODT0
    9 DDR_A_CAS# CAS# ODT0 M_ODT0 8
    117 VDD15 VDD16 118
    DDR_A_MA13 119 120 M_ODT1 M_ODT1 8
    DDR_CS1_DIMMA# A13 ODT1
    8 DDR_CS1_DIMMA# 121 S1# NC2 122
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    123 VDD17 VDD18 124


    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    2 2 2 2 2 2 2 125 NCTEST VREF_CA 126 +V_DDR_MCH_REF


    C1320

    C1321

    C1322

    127 VSS27 VSS28 128


    C1323

    C1324

    C1325

    C1326

    DDR_A_D32 129 130 DDR_A_D36


    DQ32 DQ36

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z
    DDR_A_D33 131 132 DDR_A_D37
    1 1 1 1 1 1 1 DQ33 DQ37
    133 VSS29 VSS30 134 1 1

    C1327

    C1328
    DDR_A_DQS#4 135 136 DDR_A_DM4
    DDR_A_DQS4 DQS#4 DM4
    137 DQS4 VSS31 138
    139 140 DDR_A_D38
    DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2
    141 DQ34 DQ39 142
    B DDR_A_D35 B
    143 DQ35 VSS33 144
    145 146 DDR_A_D44
    DDR_A_D40 VSS34 DQ44 DDR_A_D45
    147 DQ40 DQ45 148
    DDR_A_D41 149 150
    DQ41 VSS35 DDR_A_DQS#5
    151 VSS36 DQS#5 152
    DDR_A_DM5 153 154 DDR_A_DQS5
    DM5 DQS5
    155 VSS37 VSS38 156
    DDR_A_D42 157 158 DDR_A_D46
    DDR_A_D43 DQ42 DQ46 DDR_A_D47
    159 DQ43 DQ47 160
    161 VSS39 VSS40 162
    DDR_A_D48 163 164 DDR_A_D52
    DDR_A_D49 DQ48 DQ52 DDR_A_D53
    165 DQ49 DQ53 166
    167 VSS41 VSS42 168
    DDR_A_DQS#6 169 170 DDR_A_DM6
    DDR_A_DQS6 DQS#6 DM6
    171 DQS6 VSS43 172
    173 174 DDR_A_D54
    DDR_A_D50 VSS44 DQ54 DDR_A_D55
    175 DQ50 DQ55 176
    DDR_A_D51 177 178
    DQ51 VSS45 DDR_A_D60
    179 VSS46 DQ60 180
    DDR_A_D56 181 182 DDR_A_D61
    DDR_A_D57 DQ56 DQ61
    183 DQ57 VSS47 184
    185 186 DDR_A_DQS#7
    DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
    187 DM7 DQS7 188
    189 VSS49 VSS50 190
    DDR_A_D58 191 192 DDR_A_D62
    DDR_A_D59 DQ58 DQ62 DDR_A_D63
    193 DQ59 DQ63 194
    195 VSS51 VSS52 196
    1 2 197 198 PM_EXTTS#0
    SA0 EVENT# PM_EXTTS#0 8
    +3VS R1494 10K_0402_5% 199 200 ICH_SMBDATA
    VDDSPD SDA ICH_SMBDATA 15,16,22
    2.2U_0805_16V4Z

    0.1U_0402_16V4Z

    1 2 201 202 ICH_SMBCLK


    SA1 SCL ICH_SMBCLK 15,16,22
    1 1 R1495 10K_0402_5% 203 204 +0.75VS
    VTT1 VTT2
    C1329

    C1330

    A
    +0.75VS A
    205 G1 G2 206
    2 2 FOX_AS0A626-U2RN-7F
    CONN@

    Top side
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR3 SO-DIMM Slot A
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 14 of 43
    5 4 3 2 1
    5 4 3 2 1

    +V_DDR_MCH_REF +1.5V +1.5V


    9 DDR_B_DQS#[0..7]
    JP4
    9 DDR_B_D[0..63] +V_DDR_MCH_REF 1 2
    VREF_DQ VSS DDR_B_D4
    3 VSS DQ4 4
    DDR_B_D0 5 6 DDR_B_D5
    9 DDR_B_DM[0..7] DQ0 DQ5

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z
    DDR_B_D1 7 8
    DQ1 VSS DDR_B_DQS#0
    9 DDR_B_DQS[0..7] 1 1 9 VSS DQS0# 10

    C1331

    C1332
    DDR_B_DM0 11 12 DDR_B_DQS0
    +1.5V DM0 DQS0
    9 DDR_B_MA[0..14] 13 VSS VSS 14
    DDR_B_D2 15 16 DDR_B_D6
    2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
    17 DQ3 DQ7 18
    19 VSS VSS 20

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    @ @ DDR_B_D8 21 22 DDR_B_D12
    DDR_B_D9 DQ8 DQ12 DDR_B_D13
    1 1 23 DQ9 DQ13 24

    C1068

    C1067
    D D
    25 VSS VSS 26
    DDR_B_DQS#1 27 28 DDR_B_DM1
    DDR_B_DQS1 DQS1# DM1 SM_DRAMRST#
    For EMI 29 DQS1 RESET# 30 SM_DRAMRST# 8,14
    2 2
    Layout Note: DDR_B_D10
    31 VSS VSS 32
    DDR_B_D14
    33 DQ10 DQ14 34
    Place near JP4 DDR_B_D11 35 36 DDR_B_D15
    DQ11 DQ15
    37 VSS VSS 38
    DDR_B_D16 39 40 DDR_B_D20
    DDR_B_D17 DQ16 DQ20 DDR_B_D21
    41 DQ17 DQ21 42
    43 VSS VSS 44
    DDR_B_DQS#2 45 46 DDR_B_DM2
    DDR_B_DQS2 DQS2# DM2
    47 DQS2 VSS 48
    49 50 DDR_B_D22
    +1.5V DDR_B_D18 VSS DQ22 DDR_B_D23
    Reserve C524. 9/26 51 DQ18 DQ23 52
    DDR_B_D19 53 54
    DQ19 VSS DDR_B_D28
    55 VSS DQ28 56
    DDR_B_D24 57 58 DDR_B_D29
    330U_D2E_2.5VM_R9

    DQ24 DQ29
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    C187

    1 DDR_B_D25 59 60
    DQ25 VSS DDR_B_DQS#3
    2 2 2 2 2 2 1 1 1 61 VSS DQS3# 62
    C1333

    C1334

    C1335

    C1336

    C1337

    C1338

    C194

    C195

    C196
    + DDR_B_DM3 63 64 DDR_B_DQS3
    1 DM3 DQS3

    C193
    65 VSS VSS 66
    DDR_B_D26 67 68 DDR_B_D30
    2 1 1 1 1 1 1 2 2 2 DDR_B_D27 DQ26 DQ30 DDR_B_D31
    69 DQ27 DQ31 70
    2
    71 VSS VSS 72

    @ DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
    8 DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB 8
    75 VDD VDD 76
    77 78 T146
    DDR_B_BS2 NC A15 DDR_B_MA14 PAD~D
    9 DDR_B_BS2 79 BA2 A14 80
    81 VDD VDD 82
    DDR_B_MA12 83 84 DDR_B_MA11
    C DDR_B_MA9 A12/BC# A11 DDR_B_MA7 C
    85 A9 A7 86
    87 VDD VDD 88
    DDR_B_MA8 89 90 DDR_B_MA6
    DDR_B_MA5 A8 A6 DDR_B_MA4
    91 A5 A4 92
    93 VDD VDD 94
    DDR_B_MA3 95 96 DDR_B_MA2
    DDR_B_MA1 A3 A2 DDR_B_MA0
    Layout Note: 97 A1 A0 98
    99 100
    Place near JP4.203,204 M_CLK_DDR2 101
    VDD VDD
    102 M_CLK_DDR3
    8 M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 8
    M_CLK_DDR#2 103 104 M_CLK_DDR#3
    8 M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 8
    105 VDD VDD 106
    DDR_B_MA10 107 108 DDR_B_BS1
    A10/AP BA1 DDR_B_BS1 9
    DDR_B_BS0 109 110 DDR_B_RAS#
    9 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 9
    111 VDD VDD 112
    DDR_B_WE# 113 114 DDR_CS2_DIMMB#
    9 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 8
    DDR_B_CAS# 115 116 M_ODT2
    +0.75VS 9 DDR_B_CAS# CAS# ODT0 M_ODT2 8
    117 VDD VDD 118
    DDR_B_MA13 119 120 M_ODT3
    A13 ODT1 M_ODT3 8
    DDR_CS3_DIMMB# 121 122
    8 DDR_CS3_DIMMB# S1# NC
    123 VDD VDD 124
    125 TEST VREF_CA 126 +V_DDR_MCH_REF
    127 VSS VSS 128
    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    2 2 2 2 DDR_B_D32 129 130 DDR_B_D36


    DQ32 DQ36

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z
    DDR_B_D33 131 132 DDR_B_D37
    DQ33 DQ37
    C1339

    C1340

    C1341

    C1342

    133 VSS VSS 134 1 1

    C1343

    C1344
    DDR_B_DQS#4 135 136 DDR_B_DM4
    1 1 1 1 DDR_B_DQS4 DQS4# DM4
    137 DQS4 VSS 138
    139 140 DDR_B_D38
    DDR_B_D34 VSS DQ38 DDR_B_D39 2 2
    141 DQ34 DQ39 142
    DDR_B_D35 143 144
    DQ35 VSS DDR_B_D44
    145 VSS DQ44 146
    DDR_B_D40 147 148 DDR_B_D45
    B DDR_B_D41 DQ40 DQ45 B
    149 DQ41 VSS 150
    151 152 DDR_B_DQS#5
    DDR_B_DM5 VSS DQS5# DDR_B_DQS5
    153 DM5 DQS5 154
    155 VSS VSS 156
    DDR_B_D42 157 158 DDR_B_D46
    DDR_B_D43 DQ42 DQ46 DDR_B_D47
    159 DQ43 DQ47 160
    161 VSS VSS 162
    DDR_B_D48 163 164 DDR_B_D52
    DDR_B_D49 DQ48 DQ52 DDR_B_D53
    165 DQ49 DQ53 166
    167 VSS VSS 168
    DDR_B_DQS#6 169 170 DDR_B_DM6
    DDR_B_DQS6 DQS6# DM6
    171 DQS6 VSS 172
    173 174 DDR_B_D54
    DDR_B_D50 VSS DQ54 DDR_B_D55
    175 DQ50 DQ55 176
    DDR_B_D51 177 178
    DQ51 VSS DDR_B_D60
    179 VSS DQ60 180
    DDR_B_D56 181 182 DDR_B_D61
    DDR_B_D57 DQ56 DQ61
    183 DQ57 VSS 184
    185 186 DDR_B_DQS#7
    DDR_B_DM7 VSS DQS7# DDR_B_DQS7
    187 DM7 DQS7 188
    189 VSS VSS 190
    DDR_B_D58 191 192 DDR_B_D62
    DDR_B_D59 DQ58 DQ62 DDR_B_D63
    193 DQ59 DQ63 194
    195 VSS VSS 196
    +3VS 197 198
    SA0 EVENT# PM_EXTTS#1 8 Check PM_EXTTS# spec
    +3VS 199 200 ICH_SMBDATA
    VDDSPD SDA ICH_SMBDATA 14,16,22
    1 2 201 202 ICH_SMBCLK
    SA1 SCL ICH_SMBCLK 14,16,22
    R1496 10K_0402_5% +0.75VS 203 204 +0.75VS
    VTT VTT
    2 10K_0402_5%
    R1497

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z

    1 1 205 GND1 GND2 206


    C1345

    C1346

    A FOX_AS0A626-U8SN-7F A
    1

    CONN@
    2 2

    SO-DIMM B
    Bottom side
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR3 SO-DIMM Slot B
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 15 of 43
    5 4 3 2 1
    5 4 3 2 1

    +3VS +3VM_CK505 +VCCP +1.05VM_CK505


    FSLC FSLB FSLA CPU FSB SRC PCI
    CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz
    1 2 1 2
    R121 0_0805_5% R122 0_0805_5%

    10U_0805_10V4Z~D

    10U_0805_10V4Z~D

    10U_0805_10V4Z~D
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    0 0 0 266 1066 100 33.3 +1.5VS
    1 1 1 1 1 1 1 1 1 1 1 1 1

    0 1 0 200 800 100 33.3 1 @ 2

    C216

    C217

    C218

    C219

    C220

    C221

    C222

    C223

    C224

    C225

    C226

    C227

    C228
    R1535 0_0805_5%
    2 2 2 2 2 2 2 2 2 2 2 2 2
    0 1 1 166 667 100 33.3
    D D

    +VCCP

    2
    R123 R124 1 2 10K_0402_5% +3VS
    @ 56_0402_5% R125 1 2 10K_0402_5% +3VS
    CLKREQ#_B_R R126 2 1 475_0402_1% CLKREQ#_B 8
    CLKREQ_WLAN#_R R128 2 1 475_0402_1%
    CLKREQ_WLAN# 27
    1
    CLKSATAREQ#_R R129 2 1 475_0402_1%
    CLKSATAREQ# 22
    FSA 2 1 1 2 MCH_CLKSEL0 8
    R130 2.2K_0402_5% R131 1K_0402_5% R133 1 2 10K_0402_5% +3VS

    1 2 +3VM_CK505 U4
    5 CPU_BSEL0
    R134 0_0402_5%
    6 VDDREF NC 11
    1

    12 VDDPCI
    9/14 19 VDD48
    R135 +1.05VM_CK505 23
    @ 1K_0402_5% VDD96_IO
    27 VDDPLL3 SCLK 10 ICH_SMBCLK 14,15,22
    55 9 ICH_SMBDATA 14,15,22
    2

    VDDSRC SDATA
    72 VDDCPU
    PCI_STOP# 54 H_STP_PCI# 22
    CPU_STOP# 53 H_STP_CPU# 22

    71
    +VCCP +1.05VM_CK505 CPUT0_LPR_F
    CPUC0_LPR_F 70
    CLK_CPU_BCLK 4
    CLK_CPU_BCLK# 4 SA000020H10 for Compal
    31
    38
    VDDPLL3_IO
    VDDSRC_IO
    CPUT1_LPR_F
    CPUC1_LPR_F
    68
    67
    CLK_MCH_BCLK 8
    CLK_MCH_BCLK# 8 SA00001YJ20 for HP
    2

    C C
    52 VDDSRC_IO
    R136 62 65 CLKREQ#_B_R
    @ 1K_0402_5% VDDSRC_IO CR7#
    66 VDDCPU_IO
    CPUT2_ITP_LPR/SRCT8_LPR 64
    R137 63
    1

    1K_0402_5% CPUC2_ITP_LPR/SRCC8_LPR
    FSB 1 2 61
    MCH_CLKSEL1 8 SRCT7_LPR CLK_MCH_3GPLL 8
    SRCC7_LPR 60 CLK_MCH_3GPLL# 8
    5 CPU_BSEL1 1 2
    R138 CLK_DEBUG_PORT 33_0402_1% 1 2 R1502 PCI_CLK 13 58
    27 CLK_DEBUG_PORT PCI CR#6
    0_0402_5%
    1

    PCI2_TME 14 57
    R141 PCI2/TME SRCT6_LPR
    SRCC6_LPR 56
    @ 0_0402_5% CLK_PCI_EC 33_0402_1% 1 2 R142 PCI_CLK3 15
    29 CLK_PCI_EC PCI3
    49 CLKREQ_WLAN#_R
    CR10#
    2

    SRCT10_LPR 50 CLK_PCIE_MCARD 27
    27_SEL 16 51
    PCI4/27_Select SRCC10_LPR CLK_PCIE_MCARD# 27
    CLK_PCI_ICH 33_0402_1% 1 2 R145 ITP_EN 17 46
    20 CLK_PCI_ICH PCI_F5/ITP_EN CR#11
    9/20
    FSC 2 1 1 2 48
    MCH_CLKSEL2 8 SRCT11_LPR
    R146 10K_0402_5% R147 1K_0402_5% 47
    CLK_XTAL_IN SRCC11_LPR
    5 CPU_BSEL2 1 2 5 X1
    R148 0_0402_5% 43
    CLK_XTAL_OUT CR#9
    4 X2
    1

    SRCT9_LPR 44
    R150 45
    0_0402_5% SRCC9_LPR

    41 CLKREQA_LAN# 25
    2

    CR#4
    Install. 11/06
    14.318MHZ_16PF_X5H01431AFG1H-X

    B B
    SRCT4_LPR 39 CLK_PCIE_LAN 25
    CLK_48M_ICH 33_0402_1% 1 2 R149 FSA 20 40
    22 CLK_48M_ICH USB_48MHz/FSLA SRCC4_LPR CLK_PCIE_LAN# 25
    1 2 R177
    CLK_XTAL_OUT 26 CLK_48M_CR FBMA-11-100505-600T 0402
    CR#3 37
    FSB 2
    CLK_XTAL_IN FSLB/TEST_MODE R_PCIE_ICH RP28 2
    SRCT3_LPR 35 3 0_0404_4P2R_5% CLK_PCIE_ICH 22
    36 R_PCIE_ICH# 1 4
    SRCC3_LPR CLK_PCIE_ICH# 22
    22 CLK_14M_ICH CLK_14M_ICH 33_0402_1% 1 2 R151 FSC 7 FSLC/TEST_SEL/REF0

    Y1 0 = SRC8/SRC8# SRCT2_LPR/SATAT_LPR 32 CLK_PCIE_SATA 21


    ITP_EN SRCC2_LPR/SATAC_LPR 33 CLK_PCIE_SATA# 21
    2 1
    * 10 = ITP/ITP#
    = Enable DOT96 & SRC1(UMA) 24
    9/14 2 2 9/14 27_SEL *1 = Enable SRC0 & 27MHz(DIS) 59
    SRCT0_LPR/DOTT_96_LPR
    SRCC0_LPR/DOTC_96_LPR 25
    CLK_MCH_DREFCLK 8
    CLK_MCH_DREFCLK# 8
    C233 C234 GNDSRC
    27MHz_NonSS/SRCT1_LPR/SE1 28 MCH_SSCDREFCLK 8
    22P_0402_50V8J 22P_0402_50V8J 0 = Overclocking of CPU and SRC Allowed 18 29
    1 1 GNDPCI 27MHz_SS/SRCC1_LPR/SE2 MCH_SSCDREFCLK# 8
    PCI2_TME
    1 = Overclocking of CPU and SRC NOT allowed 22
    * 26
    GND48
    1 CK_PWRGD 22
    +3VS +3VS +3VS GND CK_PWRGD/PD#
    30 GND
    2

    69 21 CLKSATAREQ#_R
    R153 R154 R155 GNDCPU CR#A
    For RF
    @ 10K_0402_5% @10K_0402_5% 10K_0402_5% 34
    CLK_PCI_EC C1304 10P_0402_50V8J GNDSRC
    @ 42 8
    1

    CLK_PCI_ICHC1305 10P_0402_50V8J GNDSRC REF1


    A @ ITP_EN 27_SEL PCI2_TME A
    3 GNDREF T_PAD 73
    CLK_48M_ICHC1306 10P_0402_50V8J
    @ ICS9LPRS397DKLFT MLF 72P
    2

    CLK_48M_CRC1307 10P_0402_50V8J
    @ R156 R157 R158
    CLK_14M_ICHC1308 10P_0402_50V8J @10K_0402_5% 10K_0402_5% @10K_0402_5%

    Security Classification Compal Secret Data Compal Electronics, Inc.


    1

    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Clock Generator CK505
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 16 of 43
    5 4 3 2 1
    5 4 3 2 1

    close to U8 VCC (+3VS) pins (one Pin one Capacitor)


    +3VS +3VS
    +HDMI_5V_OUT
    +5VS Q32
    SI3456BDV-T1-E3 1N TSOP6

    10U_0805_10V4Z~D
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    1 1 1 1 1 1 1 1

    D
    C1253 C1254 C1255 C1256 C1257 C1258 C1259 C1260 F2 W=40mils

    S
    6
    @ @ @ @ 4 5 +HDMI_5V 2 1
    @ 1 2 W=40mils
    2 2 2 2 2 2 2 2 C1348 1.1A_6VDC_FUSE
    1
    1U_0603_10V6K

    G
    3
    B+_BIAS 2
    D +HDMI_5V_OUT D

    2
    R491 R495 R1500

    2
    1
    2.2K_0402_5%

    2.2K_0402_5%
    X76@ 470K_0402_5%
    U8

    1
    EN_HDMI
    +3VS 25 HDMI_DET#

    1
    2
    OE*

    2
    D
    2 2 Q33 R1501
    VCC3V 31,37 SUSP
    11 28 HDMI_SCLK G SSM3K7002FU_SC70-3 1.5M_0402_5%
    VCC3V SCL_SINK
    15 S

    3
    VCC3V HDMI_SDATA
    21 29

    1
    VCC3V SDA_SINK
    26 VCC3V
    33 VCC3V
    +3VS R492 1 X76@ 2 4.7K_0402_5% 40 30 HDMI_DET
    VCC3V HPD_SINK
    46 VCC3V
    R493 1 X76@ 2 4.7K_0402_5% 32 R497 1 2 4.7K_0402_5% +3VS
    +3VS DDC_EN
    R494 1 X76@ 2 4.7K_0402_5% Pin34 Pin35 Equalization Default +VCCP +3VS
    +3VS
    3 34 R498 1 X76@ 2 4.7K_0402_5% +3VS
    R499 1 X76@ 2 4.7K_0402_5% FUNCTION1 FUNCTION3 0 0 12dB
    4 FUCNTION2 FUNCTION4 35
    1

    1
    DP139 R503 = 3.9K R500 1 X76@ 2 4.7K_0402_5%

    1
    R501 R502 0 1 9dB @ @
    2.2K_0402_5% 2.2K_0402_5% 1 X76@ 2 6 R504 1 X76@ 2 4.7K_0402_5% +3VS R1528 R1489
    R503 3.6K_0402_1% ANALOG1(REXT) 1 0 6dB 20K_0402_5%
    10K_0402_5%
    TMDS_B_HPD#_R 7 R505 1 X76@ 2 4.7K_0402_5%
    2

    HPD_SOURCE 1 1 3dB *

    2
    HDMIDAT 8
    8 HDMIDAT SDA_SOURCE
    10 TMDS_B_HPD# 1 2 TMDS_B_HPD#_R
    HDMICLK 9 R549 0_0402_5%
    8 HDMICLK SCL_SOURCE
    +3VS R1527 1 X76@ 2 4.7K_0402_5%

    1
    @
    1 X76@ 2 10 ANALOG2
    R1492
    R507 4.7K_0402_5% 7.5K_0402_1%

    C UMA_DVI_TXC+ 13 48 HDMI_UMA_CLK+ C
    Intel Cantiga TMDS Pin Definition HDMI_UMA_CLK+ 10

    2
    UMA_DVI_TXC- OUT_D4+ IN_D4+ HDMI_UMA_CLK-
    14 OUT_D4- IN_D4- 47 HDMI_UMA_CLK- 10
    UMA_DVI_TXD2+ HDMI_UMA_TX2+
    TMDS_B_CLK PEG_TXP_3 UMA_DVI_TXD2-
    16
    17
    OUT_D3+ IN_D3+ 45
    44 HDMI_UMA_TX2-
    HDMI_UMA_TX2+ 10
    OUT_D3- IN_D3- HDMI_UMA_TX2- 10
    TMDS_B_CLK# PEG_TXN_3 UMA_DVI_TXD1+ 19 42 HDMI_UMA_TX1+ +3VS
    OUT_D2+ IN_D2+ HDMI_UMA_TX1+ 10
    UMA_DVI_TXD1- 20 41 HDMI_UMA_TX1-
    OUT_D2- IN_D2- HDMI_UMA_TX1- 10
    TMDS_B_DATA0 PEG_TXP_2

    2
    UMA_DVI_TXD0+ 22 39 HDMI_UMA_TX0+
    OUT_D1+ IN_D1+ HDMI_UMA_TX0+ 10
    UMA_DVI_TXD0- HDMI_UMA_TX0- R496
    TMDS_B_DATA0# PEG_TXN_2 23 OUT_D1- IN_D1- 38 HDMI_UMA_TX0- 10
    Trace AS Short PASS 49
    2.2K_0402_5%
    THERMAL_GND
    TMDS_B_DATA1 PEG_TXP_1

    1
    1 GND HDMI_DET#
    TMDS_B_DATA1# PEG_TXN_1 5 GND
    12 GND 20071031:
    18 GND Add U1. 49 (THERMAL_GND) to GND Plane

    1
    D
    TMDS_B_DATA2 PEG_TXP_0 24
    27
    GND HDMI_DET 2 Q16
    GND 2N7002_SOT23
    TMDS_B_DATA2# PEG_TXN_0 31
    36
    GND
    G
    S

    3
    GND
    37 GND

    2
    100K_0402_5%

    0.1U_0402_16V4Z
    TMDS_B_HPD# PEG_RXP_3 43 GND 1

    R506

    C1261
    @
    ASM1442T QFN 48P
    2

    1
    UMA_DVI_TXC- 1 2 HDMI_R_CK-
    For Power Saving Application
    R508 0_0402_5%
    DP139 need stuff R492,R494, When Plug-in HDMI
    @ L15 WCM-2012-900T_0805 ,R498 and change R503 value to 3.9K HDMI_HPD=High OE#=Low Enable Level Shift
    4 4 3 3 When Plug-out HDMI
    ASM1442T need stuff R503 value 3.6K HDMI_HPD=Low OE#=High Disable Level Shift
    1 1 2 2
    B +HDMI_5V_OUT B

    UMA_DVI_TXC+ 1 2 HDMI_R_CK+
    R509 0_0402_5% +HDMI_5V_OUT

    (pin 19) plug in 5V


    UMA_DVI_TXD0- 1 2 HDMI_R_D0-

    2
    R510 0_0402_5% R1514 JHDMI1
    HDMI_DET 1 2HDMI_DET_R 19 Q38A
    @ L16 WCM-2012-900T_0805 10K_0402_5% HP_DET HDMI_SDATA HDMI_SDATA_R
    18 +5V 1 6
    4 4 3 3 17 DDC/CEC_GND
    HDMI_SDATA_R 16 2N7002DW-7-F_SOT363-6 Pin 10 Pin 4 Pin 3 Swing Pre-amp Slew-rate Default
    HDMI_SCLK_R SDA
    15 SCL
    1 2 14 0 0 0 450 0 0
    1 2 Reserved
    13 CEC

    5
    HDMI_R_CK- 12 20 0 0 1 420 0 0
    CK- GND Q38B
    11 CK_shield GND 21
    UMA_DVI_TXD0+ 1 2 HDMI_R_CK+ 10 22 HDMI_SCLK 4 3HDMI_SCLK_R 0 1 0 450 0 0
    R511 0_0402_5% HDMI_R_D0- CK+ GND
    9 D0- GND 23
    8 2N7002DW-7-F_SOT363-6 0 1 1 460 0 -4dB *
    HDMI_R_D0+ D0_shield
    7 D0+
    UMA_DVI_TXD1- 1 2 HDMI_R_D1- 6 1 0 0 340 0 0
    R512 0_0402_5% D1-
    5 D1_shield Q38 Please close to JHDMI1
    HDMI_R_D1+ 4 1 0 1 400 2dB 0
    @ L17 WCM-2012-900T_0805 HDMI_R_D2- D1+
    3 D2-
    4 4 1 1 0 400 2dB 0
    3 3 HDMI_R_D2+
    2 D2_shield
    1 D2+ 1 1 1 420 0 0
    1 2 SUYIN_100042MR019S153ZL
    1 2

    CONN@
    UMA_DVI_TXD1+ 1 2
    R513 0_0402_5%

    UMA_DVI_TXD2- 1 2
    A R514 0_0402_5% A

    @ L18 WCM-2012-900T_0805
    4 4 3 3

    1 1 2 2

    UMA_DVI_TXD2+ 1 2
    R515 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDMI Level Shift_AS1442T
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    C 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-5541P
    Date: Thursday, September 10, 2009 Sheet 17 of 43
    5 4 3 2 1
    A B C D E

    BLUE
    GREEN
    RED
    Place close to
    @ D8 @ D11 @ D9 JCRT1

    1
    1 +5VS +RCRT_VCC +CRTVDD 1

    DAN217T146_SC59-3

    DAN217T146_SC59-3

    DAN217T146_SC59-3
    D10 F1
    2 1 1 2 W=40mils
    1
    RB491D_SC59-3 1.1A_6VDC_FUSE

    3
    +CRTVDD
    0.1U_0402_16V4Z
    C1084 2
    JCRT1
    6
    29 MSEN# 11
    RED 1
    7
    12
    GREEN 2
    8
    13
    BLUE 3
    9
    14 16
    4 17
    +5VS +5VS 10
    15
    C1085 C1086 5
    0.1U_0402_16V4Z 0.1U_0402_16V4Z
    1 2 1 2 SUYIN_070546FR015S200ZR Place closed to chipset
    CONN@
    +3VS
    +CRTVDD +CRTVDD +3VS pull-up 10k on AMD M82M MXM side
    5
    1

    U11 pull-up 2.2k on GPU side


    SN74AHCT1G125GW_SOT353-5 R364
    P
    OE#

    1
    1
    2 CRT_HSYNC HSYNC_G_A D_HSYNC 2
    2 A Y 4 1 2 0_0603_5%
    R365 R366 R367 R368
    G

    5
    1

    2.2K_0402_5% 2.2K_0402_5%

    2
    R369 2.2K_0402_5% 2.2K_0402_5%
    P
    OE#
    3

    CRT_VSYNC 2 4 VSYNC_G_A 1 2 0_0603_5% D_VSYNC

    2
    2
    A Y D_DDCDATA CRT_DDC_DATA
    6 1 2 1
    G

    U12 GMCH_CRT_DATA 10
    1 @ 1 @ R370 0_0402_5%
    SN74AHCT1G125GW_SOT353-5 C1087 C1088
    3

    Q1A

    5
    5P_0402_50V8C 5P_0402_50V8C 2N7002DW-7-F_SOT363-6
    2 2 D_DDCCLK CRT_DDC_CLK
    3 4 2 1 GMCH_CRT_CLK 10
    R371 0_0402_5%
    Q1B
    2N7002DW-7-F_SOT363-6

    pull-up 2.2k on GPU side


    pull-up 10k on AMD M82M MXM side

    CRT Termination/EMI Filter


    3 3
    R372 1 2 0_0402_5% CRT_VSYNC
    10 GMCH_CRT_VSYNC
    R373 1 2 0_0402_5% CRT_HSYNC
    10 GMCH_CRT_HSYNC
    MSEN#

    GMCH_CRT_R L6 1 2 RED
    10 GMCH_CRT_R
    HLC0603CSCCR11JT_0603

    GMCH_CRT_G L7 1 2 GREEN
    10 GMCH_CRT_G
    HLC0603CSCCR11JT_0603

    GMCH_CRT_B L8 1 2 BLUE
    10 GMCH_CRT_B

    10P_0402_50V8J
    HLC0603CSCCR11JT_0603
    22P_0402_50V8J

    22P_0402_50V8J

    22P_0402_50V8J

    10P_0402_50V8J

    10P_0402_50V8J

    10P_0402_50V8J
    1

    1
    150_0402_1%

    150_0402_1%

    150_0402_1%

    1 1 1 1 1 1
    R374

    R375

    R376

    2
    2

    2 2 2 2 2 2
    C1130
    @ C1089 @ C1090 @ C1091 C1092 C1093 C1094

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CRT Connector
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 18 of 43
    A B C D E
    5 4 3 2 1

    EMI request.
    +5VS
    C1095
    2 1INV_PWM_R 2 1 INV_PWM
    INV_PWM 29
    D12
    R377 @ 0_0402_5% 4 2 USB20_N4
    @ VIN IO1
    680P_0402_50V7K 2 1 USB20_P4 3 1
    BKLT 10,29 IO2 GND
    R387 0_0402_5%
    PRTR5V0U2X_SOT143-4
    D @ D
    for DPST Function

    +LCDVDD +LCDVDD +3VS


    +5VALW Q13
    SI2301BDS-T1-E3_SOT23-3

    1
    +LCDVDD

    S
    1 3

    4.7U_0805_10V4Z
    R379 1
    R378 47K_0402_5% W=60mils
    100_0805_5% C1097 1

    G
    2
    4.7U_0805_10V4Z

    6 2

    2
    2 C1098
    1 1
    C1099 C1100
    2
    0.1U_0402_16V4Z 0.1U_0402_16V4Z R380
    2 2 0.047U_0402_16V7K
    2 2 1
    220K_0402_1%
    2N7002DW-7-F_SOT363-6 C1101

    1
    Q2A

    3
    +3VS INVPWR_B+ +LCDVDD
    Limited Current < 1A
    C238 @ Q2B
    R190 @
    For EMI 33P_0402_50V8J 1 @ 2 5 2N7002DW-7-F_SOT363-6
    10,29 ENAVDD
    C1102 C1096 C1103 DMIC_CLK 1 2 33_0402_1% 1 2 0_0402_5% R388

    4
    680P_0402_50V7K

    680P_0402_50V7K

    680P_0402_50V7K

    29 LCD_VCC_TEST_EN 1 2
    1 0_0402_5% R386
    1

    1
    C C
    R381
    2

    2 100K_0402_5%

    2
    B+ INVPWR_B+

    Avoid Panel display garbage after


    JLVDS1 power on.
    1 L10 1 2
    1 FBMA-L11-201209-221LMA30T_0805
    2 2
    3 3
    +3VS
    4 4
    INV_PWM_R
    Must close JLVDS1pin 27, 28. +3VS
    5 5
    6 DMIC_DAT DMIC_CLK
    6 BKOFF# 29
    7 7 LCD_CBL_DET# 29
    8 8

    2
    9 9 +5VS 1
    10 R383 R384 @ C1104 1 @ R1521
    10 2.2K_0402_5% 2.2K_0402_5% @ C1105 10K_0402_5%
    11 11 DMIC_DAT 27
    12 220P_0402_25V8J
    12 DMIC_CLK 27 2
    13 220P_0402_25V8J

    1
    13 DDC2_CLK 2
    14 14
    15 DDC2_DATA
    15 USB20_N4 22
    16 BKOFF#
    16 USB20_P4 22
    17 17
    18 INVPWR_B+
    18 INVPWR_B+ BKOFF#
    19 19
    20 INVPWR_B+ EMI request
    20
    21 21 W=60mils

    2
    B 22 22 W=60mils FDS4435: P Channel MOS TXCLK_L+ @ C1106 1 100P_0402_50V8J @ R382 B
    23 23 +3VS 2
    24 Q39 INVPWR_B+ TXCLK_L- @ C1107 1 2 100P_0402_50V8J 10K_0402_5%
    24 B+ FDS4435BZ_SO8~D DDC2_CLK @ C1108 1 100P_0402_50V8J
    25 25 +LCDVDD 2
    26 @ DDC2_DATA @ C1109 1 2 100P_0402_50V8J
    LCD_TST 29

    1
    26
    27 27 DDC2_CLK 10 8
    28 28 DDC2_DATA 10 1 7
    29 29 2 6
    30 30 TXOUT_L0- 10 3 5
    2200P_0402_50V7K~D

    1000P_0402_50V7K~D
    0.1U_0603_50V4Z~D

    31 31 TXOUT_L0+ 10 1
    1

    32 1 1 1 C1359
    32 0.1U_0603_50V4Z~D
    C1360

    C1361

    C1362

    33 TXOUT_L1- 10 R1536
    4

    33 200K_0402_5%~D @
    34 34 TXOUT_L1+ 10 2
    35 35 @
    2 @ 2 @ 2
    41 36 TXOUT_L2- 10 @
    2

    G1 36
    42 G2 37 37 TXOUT_L2+ 10
    43 G3 38 38
    44 39 TXCLK_L- 10 Q40
    G4 39 2N7002W-7-F_SOT323-3~D
    45 G5 40 40 TXCLK_L+ 10
    R1537
    HONDA_LVD-A40SFYG+
    D

    2 1 1 3
    CONN@ @
    100K_0402_5%~D
    G
    2

    29,31,34,36,37 SUSP#

    LVDS CONN & USB Camera +


    A
    Dig Mic A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LCD/Camera/DMIC Connector
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 19 of 43
    5 4 3 2 1
    5 4 3 2 1

    +3VS

    1 2 PCI_DEVSEL#
    R159 8.2K_0402_5%
    1 2 PCI_STOP#
    R160 8.2K_0402_5%
    1 2 PCI_TRDY#
    R161 8.2K_0402_5%
    1 2 PCI_FRAME# U5B
    R162 8.2K_0402_5% A11 G4 PCI_REQ0#
    PCI_PLOCK# AD0 REQ0# PCI_GNT0#
    D
    1
    R163
    2
    8.2K_0402_5%
    B12
    A10
    AD1 PCI GNT0# E1
    A9 PCI_REQ1# D
    PCI_IRDY# AD2 REQ1#/GPIO50
    1 2 C12 AD3 GNT1#/GPIO51 E12
    R164 8.2K_0402_5% A8 B11 PCI_REQ2#
    PCI_SERR# AD4 REQ2#/GPIO52
    1 2 A12 AD5 GNT2#/GPIO53 C10
    R165 8.2K_0402_5% E10 D6 PCI_REQ3#
    PCI_PERR# AD6 REQ3#/GPIO54 PCI_GNT3#
    1 2 C11 AD7 GNT3#/GPIO55 C6
    R166 8.2K_0402_5% B9 AD8
    D8 AD9 C/BE0# D10
    A4 AD10 C/BE1# A5
    E8 AD11 C/BE2# E6
    A3 AD12 C/BE3# C9
    D9 AD13
    C8 C3 PCI_IRDY#
    +3VS AD14 IRDY#
    C2 AD15 PAR B1
    D7 AD16 PCIRST# T3
    B3 A7 PCI_DEVSEL#
    PCI_PIRQA# AD17 DEVSEL# PCI_PERR#
    1 2 D11 AD18 PERR# D4
    R167 8.2K_0402_5% B6 C5 PCI_PLOCK#
    PCI_PIRQB# AD19 PLOCK# PCI_SERR#
    1 2 D5 AD20 SERR# H5
    R168 8.2K_0402_5% D3 A6 PCI_STOP#
    PCI_PIRQC# AD21 STOP# PCI_TRDY#
    1 2 F4 AD22 TRDY# A2
    R169 8.2K_0402_5% E3 B8 PCI_FRAME#
    PCI_PIRQD# AD23 FRAME#
    1 2 E4 AD24
    R170 8.2K_0402_5% B2 A21 PLT_RST#
    AD25 PLTRST# PLT_RST# 8,25,27,29
    1 2 PCI_PIRQE# C4 B5 CLK_PCI_ICH
    AD26 PCICLK CLK_PCI_ICH 16
    R171 8.2K_0402_5% C1 T1 PCI_PME#
    PCI_PIRQF# AD27 PME# R453
    1 2 D1 AD28
    R172 8.2K_0402_5% E2 1 2 +3VALW
    PCI_PIRQG# AD29 10K_0402_5%
    1 2 J4 AD30
    R173 8.2K_0402_5% H2
    PCI_PIRQH# AD31
    2 1
    R174 8.2K_0402_5%
    C
    1 2 PCI_REQ0# PCI_PIRQA# F1
    Interrupt I/F G3 PCI_PIRQE# C
    R175 8.2K_0402_5% PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
    F5 PIRQB# PIRQF#/GPIO3 G1
    1 2 PCI_REQ1# PCI_PIRQC# F2 F3 PCI_PIRQG#
    R176 8.2K_0402_5% PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
    C7 PIRQD# PIRQH#/GPIO5 H4
    1 2 PCI_REQ2#
    R178 8.2K_0402_5% ICH9-M SFF ES_FCBGA569
    1 2 PCI_REQ3#
    R179 8.2K_0402_5%

    A16 swap override Strap Boot BIOS Strap Place closely pin B10
    B B
    Low= A16 swap override Enble CLK_PCI_ICH
    PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location

    1
    @
    R180
    10_0402_5%

    0 1 SPI

    2
    PCI_GNT3# 1
    @
    1 0 PCI C235
    1

    8.2P_0402_50V
    2
    R181
    @ 1K_0402_5% 1 1 LPC *
    2

    +3VALW

    PCI_GNT0#
    1

    R1516
    1

    @ 1K_0402_5%
    R182
    1K_0402_5%
    2

    @ KBC_SPI_CS1#
    2

    22 KBC_SPI_CS1#
    1

    A R183 A

    DEL J3. 9/29 @ 1K_0402_5%


    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ICH9M(1/4)-PCI/INT
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 20 of 43
    5 4 3 2 1
    5 4 3 2 1

    +RTCVCC

    1 2 LAN100_SLP
    R184 330K_0402_1%
    1 2 SM_INTRUDER#
    R185 1M_0402_5%
    1 2 ICH_INTVRMEN
    R186 330K_0402_1%

    0_0402_5%

    0_0402_5%
    R188

    R189
    1 2 ICH_SRTCRST#

    2
    R187 20K_0402_5%
    Change from 180K to 20K C236
    1
    & 0.1u to 1u. 9/29
    1U_0603_10V4Z @ @

    1
    D 2 D

    ICH_RSVD HDA_SDOUT_CODEC Description


    0 0 RV U5A
    LPC_AD[0..3] 27,29
    ICH_RTCX1 F25 H3 LPC_AD0 9/27
    0 1 XOR place under RAM door ICH_RTCX2 G25
    RTCX1
    RTCX2
    FWH0/LAD0
    FWH1/LAD1 J3 LPC_AD1
    R318 K5 LPC_AD2
    1 0 Normal(D) +RTCVCC 1 2 ICH_RTCRST# G24 RTCRST#
    FWH2/LAD2
    FWH3/LAD3 L3 LPC_AD3 Del PU R203~R204 9/27
    20K_0402_5% ICH_SRTCRST# C24
    1 1 PCIE Bit1

    RTC
    LPC
    SM_INTRUDER# C23
    SRTCRST#
    J2
    for H_DPRSTP# &
    INTRUDER# FWH4/LFRAME# LPC_FRAME# 27,29
    XOR CHAIN ENTRANCE STRAP:RSVD 1 H_DPSLP#. +VCCP

    1
    C1044 CLRP1 ICH_INTVRMEN E25 H1
    +3VS SHORT PADS LAN100_SLP INTVRMEN LDRQ0#
    D25 LAN100_SLP LDRQ1#/GPIO23 J1 T46 PAD
    1U_0603_10V4Z

    2
    2 GATEA20
    G22 GLAN_CLK A20GATE N3 GATEA20 29
    1 2 HDA_SDOUT_ICH AB23 R192
    A20M# H_A20M# 4
    R191 @ 1K_0402_5% D14 56_0402_5%
    ICH_RSVD LAN_RSTSYNC H_DPRSTP_R# R194
    1 2 ICH_RSVD 22 DPRSTP# AE23 1 2 0_0402_5% H_DPRSTP# 5,8,39
    R193 @ 1K_0402_5% A14 AE24

    LAN / GLAN
    H_DPSLP# 5

    1
    LAN_RXD0 DPSLP#
    D12 LAN_RXD1
    B14 AD25 H_FERR#_R R195 1 2 56_0402_5% H_FERR#
    LAN_RXD2 FERR# H_FERR# 4
    D13 LAN_TXD0 CPUPWRGD AE22 H_PWRGOOD 5
    C13 LAN_TXD1
    Place Close to U8.
    Add C599 ~ C602 to solve WWAN noise issue. 1/23 A13 AD23 +3VS
    LAN_TXD2 IGNNE# H_IGNNE# 4

    CPU
    PAD T47 D15 GPIO56 INIT# AE21 H_INIT# 4
    AD24 +VCCP GATEA20 R196 1 2 10K_0402_5%
    C INTR H_INTR 4 C
    H22 L1 KB_RST# KB_RST# R197 1 2 10K_0402_5%
    GLAN_COMPI RCIN# KB_RST# 29
    +1.5VS R198 1 2 24.9_0402_1% GLAN_COMP H21 GLAN_COMPO

    1
    Remove R227 & C199 NMI AD21 H_NMI 4
    HDA_BITCLK_ICH AE7 AC21 H_SMI# R201
    HDA_BIT_CLK SMI# H_SMI# 4
    HDA_SYNC_ICH AB7 56_0402_5%
    HDA_SYNC H_STPCLK#
    STPCLK# AC25 H_STPCLK# 4
    HDA_RST#_ICH AA7

    2
    HDA_RST# THRMTRIP_ICH# R206
    THRMTRIP# AC23 1 2 54.9_0402_1% H_THERMTRIP# 4,8
    27 HDA_SDIN0 AB6 HDA_SDIN0
    placed within 2" from
    AE6 HDA_SDIN1 TP11 AC22 T48 PAD ICH9M
    8 HDA_SDIN2 AC6

    IHDA
    HDA_SDIN2
    AA5 HDA_SDIN3
    SATA4RXN AD12
    HDA_SDOUT_ICH AC7 AE12
    HDA_SDOUT SATA4RXP
    SATA4TXN AB12
    AD8 HDA_DOCK_EN#/GPIO33 SATA4TXP AA12
    PAD T49 AB8 HDA_DOCK_RST#/GPIO34
    SATA5RXN AC11
    AC9 SATALED# SATA5RXP AD11
    SATA5TXN AB10
    SATA_RXN0_C AE14 AA10
    24 SATA_RXN0_C SATA0RXN SATA5TXP
    SATA_RXP0_C AD14
    24 SATA_RXP0_C SATA0RXP

    SATA
    SATA_TXN0_CR C1051 1 2 0.01U_0402_16V7K SATA_TXN0_R AC15 AC16 CLK_PCIE_SATA#
    24 SATA_TXN0_CR SATA0TXN SATA_CLKN CLK_PCIE_SATA# 16
    SATA_TXP0_CR C1052 1 2 0.01U_0402_16V7K SATA_TXP0_R AD15 AB16 CLK_PCIE_SATA
    24 SATA_TXP0_CR SATA0TXP SATA_CLKP CLK_PCIE_SATA 16
    SATA_RXN1_C AD13 AD10
    24 SATA_RXN1_C SATA1RXN SATARBIAS#
    SATA_RXP1_C AC13 AE10 R212 1 2 24.9_0402_1%
    24 SATA_RXP1_C SATA1RXP SATARBIAS
    SATA_TXN1_CR C1053 1 2 0.01U_0402_16V7K SATA_TXN1_R AA14
    24 SATA_TXN1_CR SATA1TXN Within 500 mils
    SATA_TXP1_CR C1054 1 2 0.01U_0402_16V7K SATA_TXP1_R AB14
    24 SATA_TXP1_CR SATA1TXP
    ICH9-M SFF ES_FCBGA569

    B ICH_RTCX1 B
    +RTCVCC RTCVREF
    R215
    1 2 ICH_RTCX2 BATT1.1
    D27
    R308 1 2 33_0402_5% HDA_BITCLK_ICH 10M_0402_5% R226 W=20mils 2 W=20mils
    27 HDA_BITCLK
    R307 1 2 33_0402_5% HDA_RST#_ICH 1 2 1 R228
    27 HDA_RST# W=20mils
    R295 1 2 33_0402_5% HDA_SDOUT_ICH 3 1 2
    27 HDA_SDOUT
    R297 1 2 33_0402_5% HDA_SYNC_ICH 0_0402_5% W=20mils
    27 HDA_SYNC
    Y2 1 DAN202U_SC70 1K_0402_5%

    4
    R302 1 2 33_0402_5% HDA_BITCLK_ICH 1 1 C231
    8 HDA_BITCLK_NB

    32.768KHZ_12.5P_1TJS125BJ2A251
    R299 1 2 33_0402_5% HDA_RST#_ICH C247 1

    IN

    OUT
    8 HDA_RST#_NB
    R300 1 2 33_0402_5% HDA_SDOUT_ICH C246 2.2U_0603_6.3V4Z C230
    8 HDA_SDOUT_NB 2
    R301 1 2 33_0402_5% HDA_SYNC_ICH 15P_0402_50V8J 12P_0402_50V8J
    8 HDA_SYNC_NB 2 2 Place near ICH9 0.1U_0402_16V4Z
    2
    10P_0402_50V8J

    10P_0402_50V8J

    NC

    NC
    PV for ESD
    C1354

    C1355

    1 1

    3
    2 2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ICH9M(2/4)-LAN/HDA/SATA/LPC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 21 of 43
    5 4 3 2 1
    5 4 3 2 1
    +3VS
    1 @ 2 GPIO48 +3VALW
    R271 10K_0402_5%
    1 @ 2 GPIO1

    1
    R220 10K_0402_5%
    1 2 SIRQ
    R222 8.2K_0402_5% R223 R224
    1 2 PM_CLKRUN# 2.2K_0402_5% 2.2K_0402_5%
    R225 8.2K_0402_5% U5C

    2
    1 @ 2 THERM_SCI# ICH_SMB_CLK C18 AE19 GPIO21
    R227 8.2K_0402_5% ICH_SMB_DATA SMBCLK SATA0GP/GPIO21 HDD_HALTLED
    C15 SMBDATA SATA1GP/GPIO19 AA18
    1 2 HDD_HALTLED LINKALERT# B21 AE20 NPCI_RST#

    SATA
    LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

    GPIO
    SMB
    R230 8.2K_0402_5% 9/21 ME__EC_CLK1 E18 AA20 GPIO37 PM_PWROK 1 2 M_PWROK
    SMLINK0 SATA5GP/GPIO37
    1 @ 2 GPIO22 ME__EC_DATA1 A24 SMLINK1
    R221 0_0402_5%
    R231 8.2K_0402_5% K1 CLK_14M_ICH
    +3VS CLK14 CLK_14M_ICH 16
    1 2 NPCI_RST# ICH_RI# C20 AB5 CLK_48M_ICH

    Clocks
    D RI# CLK48 CLK_48M_ICH 16 D
    R232 10K_0402_5%
    1 @ 2 GPIO17 T5 R3 ICH_SUSCLK T50 PAD
    R233 8.2K_0402_5% XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK
    4 XDP_DBRESET# C25 SYS_RESET#

    1
    1 2 GPIO21 D18 SLP_S3#
    SLP_S3# SLP_S3# 29
    R234 8.2K_0402_5% R235 R236 PM_BMBUSY# L2 B20 SLP_S4#
    8 PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# 29
    1 2 GPIO37 @ 10K_0402_5% @ 10K_0402_5% D16 SLP_S5#
    SLP_S5# SLP_S5# 29
    R237 8.2K_0402_5% 29 LID_SW# LID_SW# A23 SMBALERT#/GPIO11
    1 @ 2 GPIO18 Add R621 in 12/03. E14 S4_STATE#
    PM_PWROK 8,29,39

    2
    R238 10K_0402_5% H_STP_PCI# R1503 1 S4_STATE#/GPIO26
    16 H_STP_PCI# 2 0_0402_5% H_STP_PCI#_R B15 STP_PCI#/GPIO15
    @ GPIO57 R240 1 2 0_0402_5% R_STP_CPU# R241 1 10K_0402_5%

    SYS GPIO
    1 2 16 H_STP_CPU# A20 STP_CPU#/GPIO25 PWROK D23 2
    R239 10K_0402_5% LAN_RST 2 1
    1 @ 2 EC_SCI# PM_CLKRUN# M5 M1 DPRSLPVR 1 2 10K_0402_5% R273
    CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR 8,39
    R1517 10K_0402_5% R1533 R243 0_0402_5%

    Power MGT
    1 2 WAKE# C21 C16 ICH_LOW_BAT#
    25,27,29 PCIE_WAKE# WAKE# BATLOW#
    0_0402_5% SIRQ L4
    29 SIRQ SERIRQ
    THERM_SCI# AD20 U4
    29 THERM_SCI# THRM# PWRBTN# ON/OFFBTN# 29
    R247 1 2 0_0402_5% VRMPWRGD B24 D22 LAN_RST
    29,39 VGATE VRMPWRGD LAN_RST#
    R248 1 2 100K_0402_5% PM_RSMRST# 1 2
    PAD T51 A19 D19 RSMRST# 1 2 R1522 10K_0402_5%
    TP12 RSMRST# PM_RSMRST# 29
    R251 0_0402_5%
    GPIO1 AE16 U1 CK_PWRGD_R 1 2
    +3VALW GPIO1 CK_PWRGD CK_PWRGD 16
    AE18 R253 0_0402_5%
    GPIO6 M_PWROK
    AD18 GPIO7 CLPWROK T4 M_PWROK 8
    1 2 LINKALERT# 29 EC_SMI#
    EC_SMI# B25 GPIO8
    R244 10K_0402_5% EC_SCI# C14 B23
    29 EC_SCI# GPIO12 SLP_M#
    1 2 WAKE# D20 GPIO13
    R257
    R245 10K_0402_5% GPIO17 AE17 C22 CL_CLK0 3.24K_0402_1%
    GPIO17 CL_CLK0 CL_CLK0 8
    1 2 ICH_RI# GPIO18 K3 GPIO18 CL_CLK1 A18 1 2 +3VS

    0.1U_0402_16V4Z
    R246 10K_0402_5% PAD T52 AC8 GPIO20

    1
    453_0402_1%
    1 2 XDP_DBRESET# GPIO22 AC19 SCLOCK/GPIO22 CL_DATA0 E22 CL_DATA0
    CL_DATA0 8

    Controller Link
    R250 10K_0402_5% D17 B18 1

    GPIO
    PAD T53 GPIO27 CL_DATA1

    R260
    C C
    1 @ 2 S4_STATE# PAD T54 E20 GPIO28
    R252 10K_0402_5% M4 F21 CL_VREF0_ICH
    16 CLKSATAREQ# SATACLKREQ#/GPIO35 CL_VREF0

    C263
    1 2 ICH_LOW_BAT# +3VS 1 @ 2 GPIO38 AB18 A17

    2
    R254 10K_0402_5% R262 8.2K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1 2
    PAD T55 AC18 SDATAOUT0/GPIO39
    1 2 ME__EC_CLK1 GPIO48 AB19 SDATAOUT1/GPIO48 CL_RST0# C17 CL_RST#
    CL_RST# 8
    R259 10K_0402_5% AC20 B17
    PAD T56 GPIO49 CL_RST1#
    1 2 ME__EC_DATA1 GPIO57 A16 GPIO57/CLGPIO5
    R261 10K_0402_5% +3VS R264 1 2 @ 1K_0402_5% A22
    MEM_LED/GPIO24
    1 @ 2 LID_SW# 27 SB_SPKR
    SB_SPKR K4 SPKR GPIO10/SUS_PWR_ACK E16
    R1518 10K_0402_5% MCH_ICH_SYNC# AB20 A15
    8 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
    ICH_RSVD C19 D21
    21 ICH_RSVD TP3 WOL_EN/GPIO9

    MISC
    PAD T57 AB17 TP8
    +3VALW AC17
    PAD T58 TP9
    PAD T59 AD17 TP10
    RP29
    5 4 ICH9-M SFF ES_FCBGA569
    6 3 USB_OC#1 U5D
    7 2 USB_OC#0 T25 PERN1 V25 DMI_RXN0 DMI_RXN0 8
    LID_SW# DMI0RXN DMI_RXP0

    Direct Media Interface


    8 1 T24 PERP1 DMI0RXP V24 DMI_RXP0 8
    R24 PETN1 U24 DMI_TXN0 DMI_TXN0 8
    10K_1206_8P4R_5% DMI0TXN DMI_TXP0
    R23 PETP1 DMI0TXP U23 DMI_TXP0 8
    PCIE_RXN2 P25 W23 DMI_RXN1 DMI_RXN1 8
    27 PCIE_RXN2 PERN2 DMI1RXN
    PCIE_RXP2 P24 W24 DMI_RXP1 DMI_RXP1 8
    27 PCIE_RXP2 PERP2 DMI1RXP
    27 PCIE_TXN2 C265 1 2 0.1U_0402_10V7K PCIE_C_TXN2 P21 WLAN V21 DMI_TXN1 DMI_TXN1 8
    C266 1 0.1U_0402_10V7K PCIE_C_TXP2 PETN2 DMI1TXN DMI_TXP1
    27 PCIE_TXP2 2 P22 PETP2 DMI1TXP V22 DMI_TXP1 8
    Add in 9/14.
    N23 Y24 DMI_RXN2 DMI_RXN2 8
    Add RP15 back. 9/27 +3VS N24
    PERN3 DMI2RXN
    Y25 DMI_RXP2

    PCI-Express
    PERP3 DMI2RXP DMI_RXP2 8
    M21 EXP Y21 DMI_TXN2 DMI_TXN2 8
    PETN3 DMI2TXN DMI_TXP2
    M22 PETP3 DMI2TXP Y22 DMI_TXP2 8
    R275
    1

    B 2.2K_0402_5% DMI_RXN3 B
    M25 PERN4 DMI3RXN AB24 DMI_RXN3 8
    R274 M24 AB25 DMI_RXP3 DMI_RXP3 8
    2.2K_0402_5% Q8 PERP4 DMI3RXP DMI_TXN3
    L24 PETN4 WWAN DMI3TXN AA23 DMI_TXN3 8
    RHU002N06_SOT323 L23 AA24 DMI_TXP3 DMI_TXP3 8
    PETP4 DMI3TXP
    2

    2
    S

    ICH_SMBDATA 3 1 ICH_SMB_DATA K24 T21 CLK_PCIE_ICH#


    14,15,16 ICH_SMBDATA PERN5 DMI_CLKN CLK_PCIE_ICH# 16
    K25 T22 CLK_PCIE_ICH
    PERP5 DMI_CLKP CLK_PCIE_ICH 16
    S

    ICH_SMBCLK 3 1 ICH_SMB_CLK K21


    14,15,16 ICH_SMBCLK PETN5
    Within 500 mils
    G

    K22 AB21
    2

    +3VS Q9 PETP5 DMI_ZCOMP DMI_IRCOMP R276 1


    For / DDR3 / CLKGEN DMI_IRCOMP AB22 2 24.9_0402_1% +1.5VS
    RHU002N06_SOT323 GLAN_RXN
    G

    25 GLAN_RXN H24
    2

    GLAN_RXP PERN6/GLAN_RXN
    25 GLAN_RXP
    C271 1 0.1U_0402_10V7K GLAN_TXN_C
    H25 PERP6/GLAN_RXP USBP0N GLAN AE2 USB20_N0 28
    25 GLAN_TXN 2 J24 PETN6/GLAN_TXN USBP0P AD1 USB20_P0 28
    25 GLAN_TXP C272 1 2 0.1U_0402_10V7K GLAN_TXP_C J23 AD3
    PETP6/GLAN_TXP USBP1N USB20_N1 27
    USBP1P AD4 USB20_P1 27
    E24 SPI_CLK USBP2N AC2 USB20_N2 27
    E23 SPI_CS0# USBP2P AC3 USB20_P2 27
    20 KBC_SPI_CS1# F23 SPI_CS1#/GPIO58/CLGPIO6 USBP3N AC5 USB20_N3 26
    USBP3P AB4 USB20_P3 26
    F22 SPI_MOSI USBP4N AB2 USB20_N4 19 Place closely pin AF3 Place closely pin H1
    SPI

    G23 SPI_MISO USBP4P AB1 USB20_P4 19


    USBP5N AA3 USB20_N5 27
    USB_OC#0 P4 AA2 CLK_48M_ICH CLK_14M_ICH
    28 USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 27
    USB_OC#1 N4 Y1
    27 USB_OC#1 OC1#/GPIO40 USBP6N USB20_N6 27
    N1 OC2#/GPIO41 USB
    USBP6P Y2 USB20_P6 27

    1
    P5 W2 @ @
    OC3#/GPIO42 USBP7N USB20_N7 27
    P1 W3 R283 R284
    OC4#/GPIO43 USBP7P USB20_P7 27
    P2 V1 10_0402_5% 10_0402_5%
    OC5#/GPIO29 USBP8N
    M3 OC6#/GPIO30 USBP8P V2
    M2 Y5

    2
    OC7#/GPIO31 USBP9N
    P3 OC8#/GPIO44 USBP9P Y4
    R1 OC9#/GPIO45 USBP10N U3 1 @ 1 @
    A C273 C274 A
    R4 OC10#/GPIO46 USBP10P U2
    R2 OC11#/GPIO47 USBP11N V4
    V5 4.7P_0402_50V8C 4.7P_0402_50V8C
    USBRBIAS USBP11P 2 2
    AE5 USBRBIAS
    AD5 USBRBIAS#
    1

    Within 500 mils ICH9-M SFF ES_FCBGA569


    R287
    22.6_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title
    2

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ICH9M(3/4)-DMI/USB/GPIO/PCIE
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 22 of 43
    5 4 3 2 1
    5 4 3 2 1

    +RTCVCC +VCCP U5E


    20 mils U5F B4 U5
    VSS[001] VSS[107]
    G17 VCCRTC VCC1_05[01] L11 B7 VSS[002] VSS[108] U10

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    VCC1_05[02] L12 B10 VSS[003] VSS[109] W11

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    1 1 ICH_V5REF_RUN G7 L13 B13 U14
    V5REF VCC1_05[03] VSS[004] VSS[110]

    C275

    C276
    VCC1_05[04] L14 1 1 B16 VSS[005] VSS[111] W16
    ICH_V5REF_SUS U7 L15 B19 U21
    V5REF_SUS VCC1_05[05] VSS[006] VSS[112]
    VCC1_05[06] M11 B22 VSS[007] VSS[113] U22
    2 2

    C277

    C278
    J19 VCC1_5_B[01] VCC1_05[07] M15 D2 VSS[008] VSS[114] U25
    +1.5VS_PCIE_ICH 2 2
    K18 VCC1_5_B[02] VCC1_05[08] N11 D24 VSS[009] VSS[115] V3
    K19 VCC1_5_B[03] VCC1_05[09] N15 E5 VSS[010] VSS[116] V8
    L18 VCC1_5_B[04] VCC1_05[10] P11 E7 VSS[011] VSS[117] V19
    L19 VCC1_5_B[05] VCC1_05[11] P15 E9 VSS[012] VSS[118] V23
    R289 40 mils M18 R11 E11 W1
    VCC1_5_B[06] VCC1_05[12] VSS[013] VSS[119]
    +1.5VS 1 2 M19 VCC1_5_B[07] VCC1_05[13] R12 E13 VSS[014] VSS[120] W4
    D BLM18PG181SN1D_0603 D
    N18 VCC1_5_B[08] VCC1_05[14] R13 E15 VSS[015] VSS[121] W5

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    2.2U_0402_6.3V6M
    1 1 1 N19 VCC1_5_B[09] VCC1_05[15] R14 E17 VSS[016] VSS[122] W7

    220U_D2_4VM_R15
    1 P18 VCC1_5_B[10] VCC1_05[16] R15 E19 VSS[017] VSS[123] W9
    +
    R18 VCC1_5_B[11] 9/29 E21 VSS[018] VSS[124] W15

    C279

    C280

    C281
    T18 R290 F24 W19
    2 2 2 VCC1_5_B[12] VSS[019] VSS[125]
    T19 VCC1_5_B[13] 1 2 +1.5VS G2 VSS[020] VSS[126] W21
    VCC_DMI

    C282

    0.01U_0402_16V7K

    1U_0603_10V4Z
    U18 G5 W22

    CORE
    2 VCC1_5_B[14] VSS[021] VSS[127]
    U19 VCC1_5_B[15] 1 1 MBK1608301YZF 0603 G10 VSS[022] VSS[128] W25

    1U_0603_10V4Z
    G13 VSS[023] VSS[129] Y3
    1 G16 VSS[024] VSS[130] Y23

    C283

    C284
    G19 VSS[025] VSS[131] AA1
    2 2
    G21 VSS[026] VSS[132] AA4

    C285
    H10 VSS[027] VSS[133] AA6
    2
    H12 VSS[028] VSS[134] AA8
    VCCDMIPLL P19 +1.5VS_DMIPLL H18 VSS[029] VSS[135] AA11
    9/29 9/29 +VCCP
    H23 VSS[030] VSS[136] AA13
    T17 R292 J5 AA15
    +5VS +3VS +5VALW +3VALW VCC_DMI[1] VCC_DMI VSS[031] VSS[137]
    VCC_DMI[2] U17 1 2 +VCCP J9 VSS[032] VSS[138] AA16
    (DMI) J10 AA17
    MBK1608301YZF 0603 VSS[033] VSS[139]
    V_CPU_IO[1] V16 J11 VSS[034] VSS[140] AA19
    1

    2 V_CPU_IO[2] U16 J12 VSS[035] VSS[141] AA21

    0.1U_0402_16V4Z

    4.7U_0603_6.3V6K
    R293 D5 R294 D6 J13 AA22
    VSS[036] VSS[142]
    VCC3_3[01] V18 +3VS 1 1 J15 VSS[037] VSS[143] AA25
    100_0402_5% CH751H-40_SC76 100_0402_5% CH751H-40_SC76 J21 AB3
    VSS[038] VSS[144]

    VCCA3GP

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    AE9 J22 AB9
    2

    VCC3_3[02] VSS[039] VSS[145]

    C286
    ICH_V5REF_SUS 1 1 1 J25 AB11
    2 2 VSS[040] VSS[146]

    C287
    ICH_V5REF_RUN 20 mils K2 AB13
    VSS[041] VSS[147]
    20 mils K9 VSS[042] VSS[148] AB15

    C288

    C289

    C290
    1 1 VCC3_3[03] AA9 K10 VSS[043] VSS[149] AC24
    C291 C292 2 2 2
    VCC3_3[04] V14 K11 VSS[044] VSS[150] AC1
    W14 +3VS K12 AC4
    1U_0402_6.3V6K 0.1U_0402_16V4Z VCC3_3[05] VSS[045] VSS[151]
    9/19 2 2
    K13 VSS[046] VSS[152] AC10

    VCCP_CORE
    C C
    K15 VSS[047] VSS[153] AC12

    0.1U_0402_16V4Z
    VCC3_3[06] G8 K17 VSS[048] VSS[154] AC14
    VCC3_3[07] H7 1 K23 VSS[049] VSS[155] AD2
    VCC3_3[08] H8 L5 VSS[050] VSS[156] AD6
    L9 VSS[051] VSS[157] AD9

    C293
    @ R322 1 2 0_0603_5% +3VS L10 AD16
    2 VSS[052] VSS[158]
    L16 VSS[053] VSS[159] AD19
    +1.5VS_VCCSATAPLL R323 1 2 0_0603_5% L17 AD22
    +3.3/1.5VCC_HDA +1.5VS VSS[054] VSS[160]

    PCI
    L21 VSS[055] VSS[161] AE3
    VCCHDA AD7 L22 VSS[056] VSS[162] AE4
    +3.3/1.5VCCSUS_HDA

    0.1U_0402_16V4Z
    R296 R319 180_0402_1% L25 AE11
    VSS[057] VSS[163]
    +1.5VS 1 2 W17 VCCSATAPLL VCCSUSHDA V10 1 2 +3VALW M9 VSS[058] VSS[164] AE13

    150_0402_1%
    0.1U_0402_16V4Z
    MBK1608301YZF 0603 1 M10 AE15
    VSS[059] VSS[165]

    1
    +1.5VS U13 T7 VCCSUS1_05_ICH_1 T60 1 1 2 +3VALW M12 V17
    VCC1_5_A[01] VCCSUS1_05[1] VSS[060] VSS[166]
    10U_0603_6.3V6M

    1U_0603_10V4Z
    1U_0402_6.3V6K

    1 1 V13 VCC1_5_A[02] VCCSUS1_05[2] H15 VCCSUS1_05_ICH_2 T61 @ R324 0_0603_5% M13 VSS[061] VSS[167] AE8

    2 R320

    C294
    1 W13 VCC1_5_A[03] +1.5VALW 2
    M14 VSS[062] VSS[168] V9
    ARX
    C296

    C295
    VCCSUS1_5[1] H16 VCCSUS1_5_ICH_1 T62 M16 VSS[063] VSS[169] J16
    2
    C297

    M17 VSS[064]
    2 2
    C298

    V7 VCCSUS1_5_ICH_2 T63 M23


    2 VCCSUS1_5[2] VSS[065]
    N2 VSS[066]
    N5 VSS[067]
    VCCSUS3_3[01] G14 +3VALW N9 VSS[068]
    U12 VCC1_5_A[04] VCCSUS3_3[02] G15 N10 VSS[069]
    1U_0603_10V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    V12 VCC1_5_A[05] VCCSUS3_3[03] H14 N12 VSS[070]
    VCCPSUS

    1 W12 VCC1_5_A[06] 1 1 N13 VSS[071]


    +3VALW
    ATX

    N14 VSS[072]
    N16 VSS[073]
    C299

    C300

    C301
    W8 If it support 3.3V audio signals N17
    2 VCCSUS3_3[04] 2 2 POP:R322/R324, VSS[074]
    N21 VSS[075]

    4.7U_0603_6.3V6K
    J7 Depop R319/R320/R323 N22
    VCCSUS3_3[05] VSS[076]
    VCCSUS3_3[06] J8 1 N25 VSS[077]
    W10 K7 If it support 1.5V audio signals P9
    B VCC1_5_A[07] VCCSUS3_3[07] VSS[078] B
    0.1U_0402_16V4Z

    K8 POP:R319/R320/R323, P10
    VCCSUS3_3[08] Depop R322/R324 VSS[079]
    1 U15 VCC1_5_A[08] VCCSUS3_3[09] L7 P12 VSS[080]
    2

    C302
    V15 VCC1_5_A[09] VCCSUS3_3[10] L8 P13 VSS[081]
    VCCSUS3_3[11] M7 P14 VSS[082]
    W18 VCC1_5_A[10] VCCSUS3_3[12] M8 P16 VSS[083]
    2
    C303

    VCCSUS3_3[13] N7 P17 VSS[084]


    VCCPUSB

    G9 VCC1_5_A[11] VCCSUS3_3[14] N8 P23 VSS[085]


    H9 VCC1_5_A[12] VCCSUS3_3[15] P7 R5 VSS[086]
    VCCSUS3_3[16] P8 R7 VSS[087]
    +1.5VS_USBPLL V11 R8
    VCC1_5_A[13] VSS[088]
    U11 VCC1_5_A[14] 9/21 R9 VSS[089]
    C304 R10
    R298 0.1U_0402_16V4Z VSS[090]
    R16 VSS[091]
    +1.5VS 1 2 U8 G18 VCCCL1_05_ICH 1 2 R17
    VCCUSBPLL VCCCL1_05 VSS[092]
    R19 VSS[093]
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    MBK1608301YZF 0603 1 1 T9 H17 VCCCV1_5_ICH 1 2 R21 A1


    VCC1_5_A[15] VCCCL1_5 VSS[094] VSS_NCTF[01]
    USB CORE

    U9 C305 1U_0402_6.3V6K R22 A25


    VCC1_5_A[16] VSS[095] VSS_NCTF[02]
    J14 +3VS R25 AE1
    VCCCL3_3[1] 9/21 VSS[096] VSS_NCTF[03]
    C306

    C307

    VCCCL3_3[2] K14 T2 VSS[097] VSS_NCTF[04] AE25


    2 2 C308 T8 VSS[098]
    0.1U_0402_16V4Z T10
    +3VS VCC_LAN1_05_INT_ICH VSS[099]
    2 1 G11 VCCLAN1_05[1] T11 VSS[100]
    H11 VCCLAN1_05[2] T12 VSS[101]
    R303 T13 VSS[102]
    1 2 G12 VCCLAN3_3[1] T14 VSS[103]
    R304 H13 T15
    MBK1608301YZF 0603 MBK1608301YZF 0603 VCCLAN3_3[2] VSS[104]
    T16 VSS[105]
    +1.5VS 1 2 +1.5VS_GLAN J17 T23
    VCCGLANPLL VSS[106]
    0.1U_0402_16V4Z

    1
    GLAN POWER

    H19 ICH9-M SFF ES_FCBGA569


    +1.5VS_PCIE_ICH VCCGLAN1_5[1]
    10U_0603_6.3V6M

    1 J18 VCCGLAN1_5[2]
    C309

    2
    10U_0603_6.3V6M

    A A
    1
    C310

    2
    +3VS K16 VCCGLAN3_3
    C311

    2 ICH9-M SFF ES_FCBGA569

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ICH9M(4/4)-PWR/GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 23 of 43
    5 4 3 2 1
    5 4 3 2 1

    D D

    HDD Connector
    JHDD1
    GND 1
    2 SATA_TXP0_CR
    A+ SATA_TXP0_CR 21
    3 SATA_TXN0_CR
    A- SATA_TXN0_CR 21
    4 0.01U_0402_16V7K
    GND SATA_RXN0
    B- 5 2 1 C1116SATA_RXN0_C SATA_RXN0_C 21
    6 SATA_RXP0 2 1 C1117SATA_RXP0_C
    B+ SATA_RXP0_C 21
    7 0.01U_0402_16V7K
    GND

    8
    Close to JHDD1.
    V33
    V33 9
    10 +5VS Close to JHDD1.
    V33
    GND 11
    GND 12

    10U_0805_10V4Z~D

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    GND 13
    V5 14 1 1 1 1

    C1111
    15 +5VS C1112 C1113 C1114
    C V5 C
    V5 16
    GND 17
    2 2 2 2
    Reserved 18
    GND 19
    V12 20
    V12 21
    V12 22

    OCTEK_SAT-22DJ1G_22P
    CONN@

    DVD-ROM Connector
    JODD1 +5VS

    GND 1
    SATA_TXP1_CR
    Close to JODD1.
    TX+ 2 SATA_TXP1_CR 21
    3 SATA_TXN1_CR
    B TX- SATA_TXN1_CR 21 B
    4 0.01U_0402_16V7K
    GND SATA_RXN1
    RX- 5 2 1 C1120SATA_RXN1_C SATA_RXN1_C 21
    6 SATA_RXP1 2 1 C1121SATA_RXP1_C
    RX+ SATA_RXP1_C 21

    1U_0603_10V4Z

    10U_0805_10V4Z~D

    10U_0805_10V4Z~D
    0.1U_0402_16V4Z
    7 0.01U_0402_16V7K
    GND
    1 1 1 1
    C1122 C1123 C1124 C1125
    8
    Close to JODD1.
    DP
    5V 9
    2 2 2 2
    5V 10 +5VS
    14 GND MD 11
    15 GND GND 12
    GND 13

    SUYIN_127382FB013S266ZR
    CONN@

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDD/ODD Connector
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 24 of 43
    5 4 3 2 1
    5 4 3 2 1

    U14

    22 GLAN_RXP C1144 0.1U_0402_16V7K PCIE_IRX_C_PTX_P6 20 33


    HSOP LED3/EEDO LAN_LED2
    D LED2/EEDI 34 1 2 +3V_LAN D
    22 GLAN_RXN C1143 0.1U_0402_16V7K PCIE_IRX_C_PTX_N6 21 35 LAN_LED1 R523 3.6K_0402_5% W=60mils
    HSON LED1/EESK
    EECS 32
    15 +3VALW
    22 GLAN_TXP HSIP +3V_LAN
    Q34
    22 GLAN_TXN 16 HSIN

    D
    38 LAN_ACTIVITY# 6

    S
    LED0
    1 5 4
    16 CLKREQA_LAN# CLKREQA_LAN# 25 2 LAN_MDI0+ C1349 2 2 2 1 1
    CLKREQB MDIP0 LAN_MDI0- 1U_0402_6.3V6K
    MDIN0 3 1
    17 5 LAN_MDI1+ SI3456BDV-T1-E3 1N TSOP6 C1268 C1269 C1270 C1271

    G
    16 CLK_PCIE_LAN REFCLK_P MDIP1 2
    6 LAN_MDI1- 10U_0805_10V4Z~D 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z

    3
    MDIN1 LAN_MDI2+ B+_BIAS 1 1 2 2
    16 CLK_PCIE_LAN# 18 REFCLK_N NC/MDIP2 8
    9 LAN_MDI2-
    NC/MDIN2 LAN_MDI3+
    8,20,27,29 PLT_RST# 27 PERSTB NC/MDIP3 11

    2
    12 LAN_MDI3-
    NC/MDIN3 R1504
    +LAN_CTRL12A 48 13 +LAN_DVDD12 470K_0402_5%
    VCTRL12A/SROUT12 DVDD12
    DVDD12 30
    +LAN_DVDD12 4 36 Layout Notice : Place as close chip as possible.

    1
    NC/FB12 DVDD12 EN_WOL
    +3V_LAN 43 NC/ENSWREG VDDTX/EVDD12 19 +LAN_EVDD12

    2
    D
    1
    1 2 46 29 +3V_LAN 2 Q35 R1505 C1363
    RSET VDD33 29 EN_WOL#
    R528 2.49K_0402_1% 37 G SSM3K7002FU_SC70-3 1.5M_0402_5% 0.1U_0603_50V_X7R
    VDD33
    S

    3
    2
    22,27,29 PCIE_WAKE# 26 44

    1
    LANWAKEB NC/VDDSR
    ISOLATEB 28 1
    ISOLATEB AVDD33
    NC/AVDD33 40

    LAN_X1 41 10 +LAN_DVDD12
    CKTAL1 DVDD12/AVDD12
    LAN_X2 42 CKTAL2 +LAN_AVDD12 +LAN_EVDD12
    NC/AVDD12 39
    W=60mil L22
    +3V_LAN 45 VCTRL12D/VDDSR
    23 T1 +LAN_CTRL12A 1 2 1 2
    NC/GPO 4.7UH_1098AS-4R7M_1.3A R533 0_0603_1%
    C 7 GND NC 24 C
    14 GND 1 1 1 1
    31 22 C1273
    GND EGND +3V_LAN C1274 C1275 C1276
    47 GND
    W=40mil Close Pin 48 within 200mils 22U_0805_6.3V6M 0.1U_0402_16V4Z 1U_0603_10V4Z 1U_0603_10V4Z
    2 2 2 2

    RTL8111DL-GR_LQFP48_7X7 2 2
    +3VS
    C1279 C1280 Close U14 Pin 19
    0.1U_0402_16V4Z 22U_0805_6.3V6M
    1

    1 1
    R534
    Close L18 within 200mils
    1K_0402_5%
    +LAN_AVDD12 +LAN_DVDD12
    Y6
    2

    29 ISOLATEB ISOLATEB LAN_X1 1 2 LAN_X2


    1 2
    1

    25MHZ_12PF_X5H025000FC1H-H R385 0_0603_1%


    1 1 2 2 2 2 2
    R536 Close Pin 44 within 200mils
    15K_0402_5% C1277 C1278 C1126 C1127 C1128 C1129 C1281
    15P_0402_50V8J 15P_0402_50V8J 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2

    2 2 1 1 1 1 1

    T64 Close U14 Pin 10, 13, 30, 36, 39


    1 2 TCT 1 24 MCT3 1 2 RJ45_GND
    C1285 0.1U_0402_16V4Z LAN_MDI3+ TCT1 MCT1 RJ45_MIDI3+ R539 75_0402_5%
    2 TD1+ MX1+ 23
    LAN_MDI3- 3 22 RJ45_MIDI3- LED1 ,LED0, LED3, LED2
    TD1- MX1-
    2 LEDCFG = 5F 06 ; for NAT20 8111DL LED setting
    1 2 TCT 4 21 MCT2 1 2
    C1283 0.1U_0402_16V4Z LAN_MDI2+ TCT2 MCT2 RJ45_MIDI2+ R540 75_0402_5% C1290 JLAN1
    5 TD2+ MX2+ 20
    LAN_MDI2- 6 19 RJ45_MIDI2- 1000P_1206_2KV7K
    TD2- MX2- 1 RJ45_MIDI3- 8 PR4-
    1 2 TCT 7 18 MCT1 1 2
    B
    C1286 0.1U_0402_16V4Z LAN_MDI1+ TCT3 MCT3 RJ45_MIDI1+ R541 75_0402_5% RJ45_MIDI3+ B
    8 TD3+ MX3+ 17 7 PR4+
    LAN_MDI1- 9 16 RJ45_MIDI1-
    TD3- MX3- RJ45_MIDI1- 6 PR2-
    1 2 TCT 10 15 MCT0 1 2
    C1287 0.1U_0402_16V4Z LAN_MDI0+ TCT4 MCT4 RJ45_MIDI0+ R543 75_0402_5% RJ45_MIDI2-
    11 TD4+ MX4+ 14 5 PR3-
    LAN_MDI0- 12 13 RJ45_MIDI0-
    TD4- MX4- RJ45_MIDI2+ 4 PR3+
    RJ45_MIDI1+ 3
    NS892406 1G ETHERNET PR2+
    RJ45_MIDI0- 2 PR1-
    RJ45_MIDI0+ 1 PR1+

    LAN_LED1 1 2 9
    R1506 330_0402_5% Green LED-
    10 G/O LED+
    LAN_LED2 1 2 11
    R542 330_0402_5% ORANGE LED-

    LAN_LED1 LAN_LED2 +3V_LAN 12 Yellow LED+


    1
    1 C1282 LAN_ACTIVITY# 1 2 13
    @ R538 330_0402_5% Yellow LED-
    1
    @ C1350 15
    C1288 100P_0402_50V8J 0.01U_0402_16V7K 2 SHLD1
    14 Detect
    100P_0402_50V8J 2 LANGND
    1 SHLD2 16
    2 @
    C1284 SANTA_130452-9
    100P_0402_50V8J
    2
    CONN@

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Gigabit LAN_RTL8111DL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    C 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-5541P
    Date: Thursday, September 10, 2009 Sheet 25 of 43
    5 4 3 2 1
    5 4 3 2 1

    +VREG

    10MIL 10MIL
    U19 +VREG
    C1238 0.1U_0402_16V4Z
    2 1 1 AV_PLL
    3 NC0
    +3VS change to +3VS_READER 7 NC1
    +XDPWR_SDPWR_MSPWR 9
    10/20 11
    CARD_3V3
    D D3V3 D
    33 D3V3 VREG 10 1 2
    22 C1239 1U_0402_6.3V4Z
    0_0603_5% MS_D4
    1 1 NC 30
    C1240 +3VS R516 2 1 +CARD_PWR 8
    C1251 0_0603_5% RST# 3V3_IN
    44 RST#
    0.1U_0402_16V4Z +3VALW R517 2 @ 1 MODE_SEL 45 MODE_SEL

    2
    2 2 XDCLE
    47 XTLO XD_CLE_SP19 43

    0.1U_0402_16V4Z
    @ 1 1 XTLI 48 42 XDCE#
    XTLI XD_CE#_SP18

    C1356
    R478 41 XDALE
    100K_0402_5% C1241 USB20_N3 XD_ALE_SP17 SDDAT2_XDRE#
    22 USB20_N3 4 DM SD_DAT2/XD_RE#_SP16 40
    4.7U_0603_6.3V6K 0.1U_0402_16V4Z USB20_P3 5 39 SDDAT3_XDWE#
    22 USB20_P3
    1
    2 2 DP SD_DAT3/XD_WE#_SP15 XD_RDY
    14 GPIO0 XD_RDY_SP14 38
    RST#_L 2 1 RST# 37 SDDAT4_XDWP#_MSD7
    R479 0_0402_5% SD_DAT4/XD_WP#/MS_D7_SP13 SDDAT5_XDD0_MSD6
    SD_DAT5/XD_D0/MS_D6_SP12 35
    SDCLK_XDD1_MSCLK_L SDCLK_XDD1_MSCLK
    Vender suggesttion SD_CLK/XD_D1/MS_CLK_SP11 34
    31 SDDAT6_XDD7_MSD3
    2
    R480
    1
    0_0402_5%
    1 SD_DAT6/XD_D7/MS_D3_SP10
    CLOSE to U19 Pin11 29 MS_INS#
    C1242 MS_INS#_SP9 SDDAT7_XDD2_MSD2
    SD_DAT7/XD_D2/MS_D2_SP8 28
    1U_0402_6.3V4Z 27 SDDAT0_XDD6_MSD0
    2 SD_DAT0/XD_D6/MS_D0_SP7 SDDAT1_XDD3_MSD1
    SD_DAT1/XD_D3/MS_D1_SP6 26
    25 XDD5_MSBS
    XD_D5_SP5 XDD4_SDDAT1
    XD_D4/SD_DAT1_SP4 23
    21 SDCD
    MODE_SEL SD_CD#_SP3 SDWP
    SD_WP_SP2 20
    19 XDCD
    XD_CD#_SP1
    EEDI 18
    1

    1 @ 10MIL
    C1243 R481 AGND_CR_R 2 13 XTAL_CTR 2 1 +CARD_PWR
    @ 0_0402_5% RREF XTAL_CTR R482 0_0603_5%
    MS_D5 24
    47P_0402_50V8J 12 XTAL_CTR
    DGND

    2
    2
    32 15 If Open , use 12MHz. crystal
    2

    R483 DGND EEDO


    EECS 16 If Pull high , use CLKGEN 48MHz.
    C 6.19K_0402_1% AGND_CR C
    6 AGND EESK 17
    46 36 SD_CMD
    AGND SD_CMD

    1
    10MIL
    CLK_48M_CR 1 2 XTLI

    AGND_CR
    16 CLK_48M_CR
    R484 0_0402_5% RTS5159-GR LQFP 48P
    1

    R486
    @ 33_0402_5%
    CKPS 2

    1
    @ C1245
    22P_0402_50V8J
    2

    EMI
    +XDPWR_SDPWR_MSPWR

    JREAD1 +XDPWR_SDPWR_MSPWR

    3 XD-VCC SD-VCC 21
    MS-VCC 28

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    B SDDAT5_XDD0_MSD6 B
    32 XD-D0 1 1

    C1248

    C1357
    SDCLK_XDD1_MSCLK 10 7 IN 1 CONN 20 SDCLK_XDD1_MSCLK
    XD-D1 SD_CLK
    2

    1 SDDAT7_XDD2_MSD2 9 14 SDDAT0_XDD6_MSD0
    SDDAT1_XDD3_MSD1 XD-D2 SD-DAT0 XDD4_SDDAT1
    8 XD-D3 SD-DAT1 12
    R487 C1247 XDD4_SDDAT1 SDDAT2_XDRE# 2 2
    7 XD-D4 SD-DAT2 30
    100K_0402_5% 0.1U_0402_16V4Z XDD5_MSBS 6 29 SDDAT3_XDWE#
    2 SDDAT0_XDD6_MSD0 XD-D5 SD-DAT3 SDDAT4_XDWP#_MSD7
    5 27
    1

    SDDAT6_XDD7_MSD3 XD-D6 SD-DAT4 SDDAT5_XDD0_MSD6


    4 XD-D7 SD-DAT5 23
    18 SDDAT6_XDD7_MSD3
    SDDAT3_XDWE# SD-DAT6 SDDAT7_XDD2_MSD2 CLOSE to U19 Pin9
    34 XD-WE SD-DAT7 16
    SDDAT4_XDWP#_MSD7 33 25 SD_CMD
    XD-WP SD-CMD
    MSCLK and SDCLK ᇠԲሽॴਢቃఎ࿯EMI XDALE
    XDCD
    35
    40
    XD-ALE SD-CD-SW 1 SDCD
    XD-CD
    solutionࠌ‫ش‬, (‫܀‬ᓮᔾ२RTS5158Eೡ). XD_RDY 39 XD-R/B SD-WP-SW 2 SDWP
    SDDAT2_XDRE# 38
    XDCE# XD-RE
    37 XD-CE
    XDCLE 36 26 SDCLK_XDD1_MSCLK
    XD-CLE MS-SCLK SDDAT0_XDD6_MSD0
    MS-DATA0 17
    11 15 SDDAT1_XDD3_MSD1
    R202 @ 33_0402_1% 7IN1 GND MS-DATA1 SDDAT7_XDD2_MSD2
    31 7IN1 GND MS-DATA2 19
    1 2 SDCLK_XDD1_MSCLK 24 SDDAT6_XDD7_MSD3
    MS-DATA3 MS_INS#
    MS-INS 22
    1 13 XDD5_MSBS
    MS-BS
    41 7IN1 GND
    C1249 42
    @ 22P_0402_50V8J 7IN1 GND
    2 TAITW_R015-A10-LM
    CONN@

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Card Reader_RTL5159-GR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 26 of 43
    5 4 3 2 1
    A B C D E

    BTB Conn.
    1 JP20 1

    16 CLKREQ_WLAN# CLKREQ_WLAN# 2 1 PCIE_C_RXN2 0_0402_5% 2 1 R475 PCIE_RXN2 22


    2 1 PCIE_C_RXP2 0_0402_5% 2
    4 4 3 3 1 R476 PCIE_RXP2 22
    CLK_PCIE_MCARD# 6 5 PCIE_TXN2
    16 CLK_PCIE_MCARD# 6 5 PCIE_TXN2 22
    CLK_PCIE_MCARD 8 7 PCIE_TXP2
    16 CLK_PCIE_MCARD 8 7 PCIE_TXP2 22
    R249 1 2 0_0402_5% 10 9
    29 WL_OFF# 10 9
    WLAN_ACT 12 11 EN_WLAN#
    BT_PRI 12 11 LPC_FRAME# EN_WLAN# 29
    14 14 13 13 LPC_FRAME# 21,29
    16 15 LPC_AD3
    16 15 LPC_AD3 21,29
    18 17 LPC_AD2
    22 USB20_N5 18 17 LPC_AD2 21,29
    20 19 LPC_AD1
    22 USB20_P5 20 19 LPC_AD1 21,29
    22 21 LPC_AD0
    22 21 LPC_AD0 21,29
    +1.5VS 24 23 CLK_DEBUG_PORT
    40mil 24 23 CLK_DEBUG_PORT 16
    26 26 25 25 EC_MUTE_R 29
    B+ 28 28 27 27
    R267 1 2 0_0402_5% 30 29 PCIE_WAKE# PCIE_WAKE# 22,25,29
    29 WAN_RADIO_OFF# 30 29 BEEP_R C239 @
    +3VALW
    40mil
    32
    34
    32 31 31
    33 R200 @
    For EMI 33P_0402_50V8J
    34 33 HDA_BITCLK
    28,29 USB_EN# 36 36 35 35 USB20_N6 22 1 2 33_0402_1% 1 2
    29 LID_SW_IN# 38 38 37 37 USB20_P6 22
    8,20,25,29 PLT_RST# 40 40 39 39
    +3VS 42 42 41 41
    44 43 60mil
    C717 1 R519 BEEP_R 44 43
    29 BEEP# 2 1 2 46 46 45 45 +5VS
    1U_0402_6.3V4Z 2800mA 48 47
    560_0402_5% 48 47
    50 50 49 49 HDA_BITCLK 21
    140mil 52 51
    52 51 HDA_SDIN0 21
    54 54 53 53 HDA_RST# 21
    R520 56 56 55 55 HDA_SYNC 21
    C718 1 2 1 2 58 57 HDA_SDOUT 21
    22 SB_SPKR 19 DMIC_DAT 58 57
    1U_0402_6.3V4Z 60 59
    19 DMIC_CLK 60 59
    560_0402_5% 62 61
    2 62 61 2
    22 USB20_N1 64 64 63 63
    66 65 100mil
    22 USB20_P1 66 65 +5VALW
    68 68 67 67
    22 USB20_N2 70 70 69 69 2000mA
    22 USB20_P2 72 72 71 71
    74 74 73 73
    22 USB_OC#1 76 76 75 75
    E51TXD_P80DATA 78 77
    29 E51TXD_P80DATA 78 77
    E51RXD_P80DATA 80 79 EAPD EAPD 29
    29 E51RXD_P80DATA 80 79
    81 81
    82 82
    E-T_1001-F80C-01L
    CONN@

    Blue Tooth Conn.


    3 JBT1 3

    29 BT_DET# BT_DET# 1 2 BT_PRI W=40mils


    WLAN_ACT3 1 2
    3 4 4 +3VS
    5 5 6 6 USB20_P7 22
    29 BT_OFF# 7 7 8 8 USB20_N7 22
    9 9 10 10
    11 11 12 12
    13 13 14 14
    +3VS
    15 GNDGND 16 W=40mils

    HRS_DF12(3.0)-14DP-0.5V(86)~D 1 1
    CONN@ C1176 C1177

    4.7U_0805_10V4Z
    2 2
    0.1U_0402_16V4Z

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    BTB/Blue Tooth Connector
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 27 of 43
    A B C D E
    5 4 3 2 1

    D D

    USB Conn.
    Left side USB Power Switch
    +5VALW R418
    1 2
    0_0402_5%
    W=80mils
    USB_VCCA
    USB_VCCA JUSB1
    U15 L12 1
    USB20_P0 USB20_P0_1 USB20_N0_1 VCC
    1 GND OUT 8 W=80mils 22 USB20_P0 1 1 2 2 2 D-
    2 7 USB20_P0_1 3
    IN OUT D+

    0.1U_0402_16V4Z
    3 IN OUT 6 1 4 GND

    150U_B_6.3VM_R40M
    1 4 5 1 22 USB20_N0 USB20_N0 4 3 USB20_N0_1
    EN# OC# 4 3

    C1181
    +

    C1182
    C1180 5
    APL3510BKI-TRG SOP 8P WCM2012F2S-900T04_0805 @ GND1
    6 GND2
    0.1U_0402_16V7K~D 7
    2 2 2 GND3
    8 GND4
    1 2
    R419 0_0402_5% SUYIN_020173MR004S50DZL
    CONN@
    Change to FB EMI
    C USB_OC#0 22 C
    USB_EN#
    27,29 USB_EN#

    @
    D15

    USB_VCCA 4 2 USB20_N0_1
    VIN IO1
    USB20_P0_1 3 1
    IO2 GND
    PRTR5V0U2X_SOT143-4

    CPU
    B H1 H2 H3 H4 H7 H8 H11 H9 H10 H12 H13 H14 H15 H6 B
    H_4P0 H_4P0 H_4P0 H_4P0 H_2P5N H_1P2N H_6P0N H_3P0 H_3P2 H_3P2 H_3P0 H_3P0 H_3P0 H_1P2N

    @ @ @ @ @ @ @ @ @ @ @ @ @ @
    1

    H17 H18 H19 H20 H21 H26 H22 H23 1H25


    H_3P0 H_3P2 H_3P2 H_3P2 H_3P0 H_3P0 FM1 FM2 FM3 FM4 H_2P7X4P0N H_8P5N H_8P0X6P0N

    @ @ @ @ @ @ @ @ @ @ @ @ @
    1

    H30 H29
    H_3P2 H_1P3N

    @ @
    1

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    USB/Screws
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 28 of 43
    5 4 3 2 1
    Board ID +3VALW
    +3VALW

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K L19

    1
    1 1 1 1 1 2 1 2007-09-19 change Brd ID
    +EC_AVCC +3VALW

    1000P_0402_50V7K~D

    0.1U_0402_16V7K~D
    1 1 R521
    C1190 C1191 C1192 C1193 C1194 +3VALW +EC_AVCC C1264 FBM-11-160808-601-T_0603 100K_0402_5%~D
    C1263
    Ra
    2 2 2 2 2 L20

    2
    0.1U_0402_16V4Z 1000P_0402_50V7K ECAGND2 2
    2 1 AD_BID
    1

    2
    FBM-11-160808-601-T_0603 R522 C1265

    111
    125
    Rb

    22
    33
    96

    67
    100K_0402_5%~D 0.1U_0402_16V7K~D

    9
    U17 2

    VCC
    VCC
    VCC
    VCC
    VCC
    VCC

    AVCC

    1
    GATEA20 1 21 BATT_TEMP
    21 GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F
    21 KB_RST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# 27 1 M/B rev:0.1; 0.2; 0.3; 0.4; 1.0
    SIRQ 3 26
    22 SIRQ SERIRQ# FANPWM1/GPIO12 Voltage:0.0; 0.4; 0.8; 1.2; 1.6
    LPC_FRAME# 4 27 ACOFF C1266
    21,27 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 33,34
    21,27 LPC_AD3 LPC_AD3 5 100P_0402_50V8J~D
    LPC_AD2 LAD3 ECAGND 2
    21,27 LPC_AD2 7 LAD2 PWM Output
    21,27 LPC_AD1 LPC_AD1 8 63 BATT_TEMP
    LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 32
    LPC_AD0 BATT_OVP
    21,27 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
    ADP_I
    BATT_OVP 32
    BATT_OVP
    ADP_I/AD2/GPIO3A 65 ADP_I 34
    CLK_PCI_EC 12 AD Input 66 AD_BID 1
    16 CLK_PCI_EC PCICLK AD3/GPIO3B
    PLT_RST# 13 75
    R437 1 8,20,25,27 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
    +3VALW 2 47K_0402_5% ECRST# 37 ECRST# SELIO2#/AD5/GPIO43 76 BT_DET# 27
    C1267
    1 22 EC_SCI# 20 SCI#/GPIO0E 100P_0402_50V8J~D
    +3VS ECAGND 2
    38 CLKRUN#/GPIO1D
    C1196 68
    10K_0402_5% 1 R461 MSEN# DAC_BRIG/DA0/GPIO3C FAN_SET
    2 0.1U_0402_16V4Z EN_DFAN1/DA1/GPIO3D 70 FAN_SET 30
    2 IREF
    DA Output IREF/DA2/GPIO3E 71 IREF 34
    2.2K_0402_5% 2 1 R432 EC_SMB_DA2 KSI0 55 72 CHGVADJ
    KSI0/GPIO30 DA3/GPIO3F CHGVADJ 34
    2.2K_0402_5% 2 1 R431 EC_SMB_CK2 KSI1 56
    KSI2 KSI1/GPIO31 0_0402_5%
    57 KSI2/GPIO32
    4.7K_0402_5% 2 1 R436 LCD_CBL_DET# KSI3 58 83 EC_MUTE R438 2 1 EC_MUTE_R
    4.7K_0402_5% 2 @ R443 LCD_TST KSI4 KSI3/GPIO33 PSCLK1/GPIO4A LCD_TST EC_MUTE_R 27
    1 59 KSI4/GPIO34 PSDAT1/GPIO4B 84 LCD_TST 19
    +3VALW KSI5 60 85
    KSI6 KSI5/GPIO35 PSCLK2/GPIO4C LCD_CBL_DET#
    61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 LCD_CBL_DET# 19
    KSI7 62 87 TP_CLK
    KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK 30
    39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 30
    4.7K_0402_5% 2 1 R1529 LCD_TST
    10K_0402_5% 1 @ 2 R1508 KSO0 KSO1 40
    30 KSI[0..7] KSO1/GPIO21
    10K_0402_5% 1 @ 2 R1509 KSO3 KSO2 41
    4.7K_0402_5% R550 EC_SMI# KSO3 KSO2/GPIO22 EN_WLAN#
    2 1 42 KSO3/GPIO23 SDICS#/GPXOA00 97 EN_WLAN# 27
    47K_0402_5% 2 1 R489 KSO1 KSO4 43 98 EN_WOL#
    30 KSO[0..16] KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL# 25
    47K_0402_5% R490 KSO2 KSO5
    10K_0402_5%
    2 1
    R1519 LID_SW_IN# KSO6
    44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 BT_OFF# 27
    1 2 45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 VGATE 22,39
    KSO7 46 SPI Device Interface
    2.2K_0402_5% 2 R429 EC_SMB_DA1 KSO8 KSO7/GPIO27
    1 47 KSO8/GPIO28
    2.2K_0402_5% 2 1 R430 EC_SMB_CK1 KSO9 48 119 FRD#
    KSO9/GPIO29 SPIDI/RD# FRD#
    10K_0402_5% @ 1 2 R434 EC_MUTE KSO10 49 120 R448 1 2 15_0402_5% FWR#
    KSO10/GPIO2A SPIDO/WR# FWR#
    10K_0402_5% @ 1 2 R1538 EN_WOL# KSO11 50 SPI Flash ROM 126 R449 1 2 15_0402_5% SPI_CLK
    KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK
    R452 KSO12 51 128 SPICS# 1 2 15_0402_5% FSEL# ACIN
    KSO12/GPIO2C SPICS# FSEL#
    1 2 PCIE_WAKE#_R KSO13 52 KSO13/GPIO2D
    R450
    10K_0402_5% KSO14 53
    @ C1224 1 KSO15 KSO14/GPIO2E WAN_RADIO_OFF#
    2 0.1U_0402_16V4Z 54 KSO15/GPIO2F CIR_RX/GPIO40 73 WAN_RADIO_OFF# 27 1
    KSO16 81 74
    KSO16/GPIO48 CIR_RLC_TX/GPIO41 MSEN# 18
    R518 1 2 82 89 FSTCHG C1358
    30 DIAG_LOOP3 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 34
    0_0402_5% 90 BAT_CHG_LED# 100P_0402_50V8J
    BATT_CHGI_LED#/GPIO52 BAT_CHG_LED# 30 2
    91 CAPS_LED# T71 PAD
    +5VS EC_SMB_CK1 CAPS_LED#/GPIO53 @
    32 EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 1 2 R1524 ISOLATEB 25
    EC_SMB_DA1 78 93 0_0402_5%
    32 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 ENAVDD 10,19
    EC_SMB_CK2 79 SM Bus 95 SYSON
    4 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 31,37,38
    4.7K_0402_5% 2 1 R439 TP_CLK EC_SMB_DA2 80 121 VR_ON
    4 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 39
    4.7K_0402_5% 2 1 R440 TP_DATA 127 ACIN ENBKL
    AC_IN/GPIO59 ACIN 33

    2
    SLP_S3# 6 100 PM_RSMRST#
    22 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 PM_RSMRST# 22
    SLP_S5# 14 101 R455 1 2 R1525
    22 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 LID_SW# 22
    EC_SMI# 15 102 EC_ON 0_0402_5% 100K_0402_1%
    22 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 30
    EMI request for WWAN noise LID_SW_IN#16 103
    27 LID_SW_IN# LID_SW#/GPIO0A EC_SWI#/GPXO06
    17 104 PM_PWROK_R R457 1 2 100_0402_5%

    1
    R1534 @ 0_0402_5% SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# PM_PWROK 8,22,39
    18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# 19
    SPI_CLK 1 2 1 2 PCIE_WAKE#_R 19 GPIO 106
    22,25,27 PCIE_WAKE# EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# 27
    INV_PWM 25 107 LCD_VCC_TEST_EN 19
    19 INV_PWM EC_THERM#/GPIO11 GPXO10
    C1222 FAN_SPEED 28 108
    22P_0402_50V8J 30 FAN_SPEED FAN_SPEED1/FANFB1/GPIO14 GPXO11 PSID_DISABLE# 33
    EAPD 29
    27 EAPD FANFB2/GPIO15
    @ E51TXD_P80DATA 30
    27 E51TXD_P80DATA EC_TX/GPIO16
    E51RXD_P80DATA 31 110 SLP_S4#
    27 E51RXD_P80DATA EC_RX/GPIO17 PM_SLP_S4#/GPXID1 SLP_S4# 22
    ON_OFF 32 112 ENBKL
    30 ON_OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL 10
    ON/OFFBTN_LED# 34 114
    30 ON/OFFBTN_LED# PWR_LED#/GPIO19 GPXID3 USB_EN# 27,28
    SUSP# R442 1 2 8.2K_0402_5% BKLT R1526 1 @ 2 36 GPI 115 THERM_SCI#
    10,19 BKLT NUMLED#/GPIO1A GPXID4 THERM_SCI# 22
    PLT_RST# R1493 100K_0402_5% 0_0402_5% 116 SUSP#
    C1226 GPXID5 ON/OFFBTN# SUSP# 19,31,34,36,37
    GPXID6 117 ON/OFFBTN# 22
    33P_0402_50V DPST FUNCTION 118
    CRY2 GPXID7 PS_ID 33
    1 2 122 XCLK1
    123 124 W=40mil
    XCLK0 V18R +V18R
    CLK_PCI_EC 1
    1

    AGND

    Y4 +3VALW
    GND
    GND
    GND
    GND
    GND

    3 4 @ C1227
    NC OSC
    SPI ROM
    2

    R460 4.7U_0603_6.3V6K
    R433 20M_0402_5% KB926QFD2_LQFP128_14X14 2
    2 1
    11
    24
    35
    94
    113

    69

    NC OSC
    33_0402_5%
    2

    1
    32.768KHZ_12.5PF_9H03200413 1 20mils
    @
    C1185
    1

    2 1 2 CRY1 0.1U_0402_16V4Z R1507 U16


    8 VCC VSS 4
    2
    ECAGND

    C1201 C1228 10K_0402_5%

    2
    15P_0402_50V8J 33P_0402_50V 3
    1 W
    @
    7 HOLD
    R425 @ C1186 FSEL# 1 2 SPI_FSEL# 1
    SPI_FSEL# 2 S
    1 2 1 @ R421 0_0402_5%
    SPI_CLK 6
    33_0402_5% 22P_0402_50V8J C
    FWR# 1 2 SPI_FWR# 5 D SPI_SO 1 2 FRD#
    R423 0_0402_5% Q 2 R424 0_0402_5%
    16M MX25L1605DM2I-12G SOP 8P ROM

    R427 @ C1188
    SPI_FWR# 2 1 2 1 @

    33_0402_5% 22P_0402_50V8J
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EC_KB926/BIOS ROM
    EMI request AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 29 of 43
    A B C D E

    For EMI
    KSO16 C1262 1 2 100P_0402_50V8J

    KSO15 C1195 1
    INT KBD Conn.
    2 100P_0402_50V8J KSI0 C1210 1 2 100P_0402_50V8J

    KSO10 C1197 1 KSO1 JKB1


    2 100P_0402_50V8J C1211 1 2 100P_0402_50V8J

    KSO11 C1198 1 KSO5


    29 DIAG_LOOP3
    DIAG_LOOP3
    KSI7
    1 1
    Power Button
    2 100P_0402_50V8J C1212 1 2 100P_0402_50V8J 2 2
    @
    KSI6 3 R1532
    KSO14 C1199 1 3
    2 100P_0402_50V8J KSI3 C1213 1 2 100P_0402_50V8J KSI4 4 4 1 2
    1 KSI2 1
    5 5
    KSO13 C1200 1 2 100P_0402_50V8J KSI2 C1214 1 2 100P_0402_50V8J KSI5 6 0_0603_5%
    KSI1 6 +3VALW
    7 7
    KSO12 C1203 1 2 100P_0402_50V8J KSO0 C1215 1 2 100P_0402_50V8J KSI3 8
    KSI0 8
    9 9

    100K_0402_5%~D
    KSO3 C1204 1 2 100P_0402_50V8J KSI5 C1216 1 2 100P_0402_50V8J KSO5 10
    KSO4 10
    11 11

    R315
    KSO6 C1205 1 2 100P_0402_50V8J KSI4 C1217 1 2 100P_0402_50V8J KSO7 12
    KSO6 12
    13 13
    KSO8 C1206 1 2 100P_0402_50V8J KSO9 C1218 1 2 100P_0402_50V8J KSO8 14 PWR_ON-OFF_BTN#

    1
    KSO3 14 D18
    15 15
    KSO7 C1207 1 2 100P_0402_50V8J KSI6 C1219 1 2 100P_0402_50V8J KSO1 16 SW1 2
    16 ON_OFF 29

    3
    KSO2 17 3 1 PWR_ON-OFF_BTN# 1
    17

    PESD24VS2UT
    KSO4 C1208 1 2 100P_0402_50V8J KSI7 C1220 1 2 100P_0402_50V8J KSO0 18 3 51ON#
    18 51ON# 33
    KSO12 19 D13 4 2
    KSO2 C1209 1 KSI1 KSO16 19
    2 100P_0402_50V8J C1221 1 2 100P_0402_50V8J 20 20
    CHN202UPT SC-70
    KSO15 21
    KSO13 21 NTC014-BB1G-A100T SPST T-MEC H4.3 4P
    22

    1
    KSO14 22
    23 23
    KSO9 24
    KSO11 24
    25 25
    KSO10 26
    29 KSI[0..7] 26
    27 27
    28 28

    1
    D
    29 KSO[0..16] 29 29 GND 31
    30 32 EC_ON 1 2 2
    30 GND 29 EC_ON
    R291 G Q31

    2
    TYCO_3-2041084-0 0_0402_5%~D S SSM3K7002FU_SC70-3

    3
    CONN@
    R1520
    10K_0402_5%

    1
    2 2

    Fan Control Circuit +5VS Touch Pad Connector


    1
    C1231
    JTP1 0.1U_0402_16V4Z
    +5VS
    2 TP_DATA
    G2 6
    C1232 5 TP_CLK
    +3VS G1
    1 4 4

    2
    2.2U_0603_6.3V4Z 1 3 TP_CLK TP_CLK 29 @
    3 TP_DATA D20
    2 2 TP_DATA 29
    2

    C1234 1 SM05_SOT23
    R465 U18 2 1
    1000P_0402_50V7K~D
    10K_0402_5% 2 ACES_85201-0405N
    8 GND EN 1
    JFAN1 CONN@
    7 2 1 1

    1
    3 GND VIN +5VS_FAN 3
    6 3 1
    1

    GND VOUT FAN_SPEED 1 @ C1233 @ C1235


    5 GND VSET 4 1 2 2
    FAN_SPEED 3 100P_0402_50V8J 100P_0402_50V8J
    29 FAN_SPEED 3 2 2
    APL5607KI-TRG_SO8 C1236
    1 10U_0603_6.3V6M 4 GND
    C1237 2
    5 GND MV-1 For ESD request, close to JTP1
    1000P_0402_50V7K
    2 29 FAN_SET ACES_85205-03001
    CONN@
    place as close as EC

    +5VALW
    LED1
    WHITE

    4 ON/OFFBTN_LED# 4
    29 ON/OFFBTN_LED# 1 2 1 R467 2
    200_0402_5%~D

    BAT_CHG_LED# 3 4 1 R1510 2
    29 BAT_CHG_LED#
    200_0402_5%~D

    YELLOW
    HT-297UY5/BP5_YELLOW-WHITE
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    KB/BTN/FAN/TP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 30 of 43
    A B C D E
    A B C D E

    +5VALW to +5VS +1.5V To +1.5VS


    +5VALW +5VS
    Q20
    1 SI4800BDY-T1-E3_SO8 1
    8 1 B+_BIAS
    7 2 +1.5V +1.5VS

    2
    1 1 6 3 1 1 U20

    1
    5 8 D S 1

    10U_0805_10V4Z~D

    0.1U_0402_16V7K~D
    C1293 C1294 C1295 C1296 R544 R1511 7 2
    10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 1U_0603_10V4Z 470_0603_5% 100K_0402_5%~D D S
    6 3 1 1

    4
    2 2 2 2 D S

    C1351

    C1352
    5 4

    1
    D G

    2
    R1512 AO4478L 1N SO8

    1
    D 2 2
    1 2
    2 SUSP 10K_0402_5% 1

    1
    G D C1353
    B+_BIAS 1 2
    R545 S Q21 SUSP 2

    3
    20K_0402_5% 1 2N7002_SOT23 G Q36 0.1U_0603_50V_X7R

    1
    D 2
    S SSM3K7002FU_SC70-3

    3
    SUSP 2 Q22 C1297
    G 2N7002_SOT23 0.01U_0402_25V7K~D
    S 2
    3

    +3VALW to +3VS
    2 +3VALW +3VS 2
    Q23
    SI4800BDY-T1-E3_SO8
    8 1
    7 2

    2
    1 1 6 3 1 1
    5
    C1298 C1299 C1300 C1301 R546
    10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 1U_0603_10V4Z 470_0603_5%
    4

    2 2 2 2

    1
    1
    D
    2 SUSP
    B+_BIAS 1 2 G
    R547 S Q24

    3
    102K_0402_1% 1 2N7002_SOT23
    1

    D C1302
    SUSP 2 Q25 0.1U_0603_50V_X7R
    G 2N7002_SOT23
    S 2
    3

    3 3
    +5VALW
    1

    +1.5VS +VCCP +1.5V +0.75VS


    R548
    100K_0402_5%

    1
    2

    SUSP R309 R310 R311 R312


    SUSP 17,37
    1

    D 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%


    2 Q26
    19,29,34,36,37 SUSP#

    2
    2N7002DW-7-F_SOT363-6

    2N7002DW-7-F_SOT363-6

    2N7002DW-7-F_SOT363-6

    2N7002DW-7-F_SOT363-6
    G 2N7002_SOT23
    S
    3

    3
    Q29A Q29B Q27A Q27B

    SUSP 2 SUSP 5 SYSON# 2 SUSP 5


    +5VALW
    1

    4
    1

    R1513
    100K_0402_5%
    4 4
    2

    SYSON#
    SYSON# 37
    1

    D
    2 Q37
    29,37,38 SYSON
    G 2N7002_SOT23
    S
    3

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DC/DC Interface
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 31 of 43
    A B C D E
    5 4 3 2 1
    CPU OTP
    PH1 under CPU botten side :

    1
    PD20 PD21
    PESD24VS2UT_SOT23-3 PESD24VS2UT_SOT23-3
    CPU thermal protection at 90 +-3 degree C
    BATT+ Recovery at 50 +-3 degree C
    BATT++

    3
    D PL14 D
    BATT+

    SMB3025500YA_2P VL VS

    1 2 BATT++
    +3VALWP

    100P_0402_50V8J~D
    1

    1
    100P_0402_50V8J~D
    1

    PC196
    PC193

    1
    1000P_0402_50V7K~D
    PC194

    PC195
    2

    2
    0.01U_0402_25V7K~D
    2

    PR212 Place clsoe to EC pin


    47K_0402_5%~D PR39
    1 2 BATT_TEMP 10.7K_0402_1%~D VL

    2
    BATT_TEMP 29 PR40

    1
    PR213 147K_0402_1%~D
    PJPB1 battery connector

    2
    1K_0402_5%~D 1 2
    PC198 PR41
    @ 0.1U_0402_16V7K~D 205K_0402_1%~D

    1
    SMART PJP31

    @
    1 PR217 PR43
    Battery:

    1
    1

    8
    2 61.9K_0402_1%~D
    2 3S/4S# 1K_0402_5%~D OTP_IN OTP_IN+ PD11
    3 1 2 3

    P
    3 3S/4S# 34 +
    4 2 1 1OTP_OUT
    1 2
    1.BAT+
    4 0 MAINPWON 33,35

    100K_0603_1%_TH11-4H104FT
    5 1 2 +3VALWP VL 1 2 OTP_IN- 2
    5 -

    G
    1SS355TE-17_SOD323-2
    2.BAT+ 6 6
    7 PR215 PR45 PU11A

    4
    7

    1
    3.ID 10 GND 8 8 6.49K_0402_1%~D 150K_0402_1%~D LM358ADR_SO8
    11 9
    4.B/I GND 9

    1
    PH1
    1

    1
    5.TS SUYIN_200275MR009G186ZL 1 2 EC_SMB_DA1 29
    C 6.SMD
    PC22 PR47
    C

    2
    PR219 1000P_0402_50V7K~D 150K_0402_1%~D

    2
    7.SMC
    100_0402_5%~D

    2
    PC23
    8.GND 14" change to TOP side
    1U_0603_10V6K~D

    9.GND 1 2 EC_SMB_CK1 29
    PR222
    100_0402_5%~D

    BATT+

    1
    PR223
    453K_0402_1%~D

    VS

    2
    1
    0.01U_0402_25V7K~D
    B COIN RTC Battery PR224
    499K_0402_1%~D B

    PC201
    PR225

    2
    PQ65

    2
    B+ 1 2 3 TP0610K-T1-E3_SOT23-3
    1 B+_BIAS
    PJP32
    470K_0402_5%~D

    100_0805_5%~D 32.8 1 BATT1.1


    1

    8
    0.1U_0805_25V7M~D

    2 2 PR227
    2

    +5VALW
    1SS355TE-17_SOD323-2 PR226

    P
    PC202 +
    GND 3 2 1 7 0

    0.01U_0402_25V7K~D
    4 6
    1

    GND -

    G
    29 BATT_OVP 10K_0402_1%~D
    2

    1
    ACES_88231-02001 PU11B
    1

    1
    220K_0402_5%

    PC203
    LM358ADR_SO8
    2

    PD22 PR229
    PR228

    86.6K_0402_1%~D

    2
    2
    1

    PQ66 D
    2
    0.1U_0603_25V7K~D

    G RHU002N06_SOT323-3
    220K_0402_5%

    S
    3
    2
    1
    PC204

    PR230

    LI-3S :13.5V----BATT-OVP=1.126V
    LI-4S :18V----BATT-OVP=1.5V
    2

    A BATT-OVP=0.08338*BATT+ A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/2/6 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    BATTERY CONN/OTP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    A3 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-5541P
    Date: Thursday, September 10, 2009 Sheet 32 of 43
    A B C D

    PC1 PR1
    Vin Detector 2200P_0402_50V7K~D 56K_0402_5%~D
    PL2
    FBM-L11-160808-601LMT 0603~D
    2 1 DOCK_PSID ADPIN VIN Max. typ. Min. 1 2 1 2

    L-->H 18.234 17.841 17.449 PR2


    PL1
    FBMA-L18-453215-900LMA90T_1812
    H-->L 17.597 17.210 16.813 1M_0402_1%~N
    1 2
    DC_IN_S1 1 2
    PJPDC1 VIN VS VIN

    0.01U_0402_25V7K~D
    SINGAL 5

    1000P_0402_50V7K~D

    1000P_0402_50V7K~D

    1
    100P_0402_50V8J~D

    100P_0402_50V8J~D
    9 1 PR5 PR4
    GND4 DC+_1

    1
    1 1

    PC6
    PR3 10K_0402_5%~D 1K_0402_5%~D

    PC2

    PC3

    PC4

    PC5
    8 2 82.5K_0402_1%~D 1 2ACIN
    GND3 DC+_2 ACIN 29

    2
    7 3 PR6

    2
    GND2 DC-_1

    8
    22K_0402_1%~D
    PU1A
    6 4 N41 1 2 N40 3

    P
    GND1 DC-_2 +
    O 1 PACIN 34

    20.5K_0402_1%~D
    0.1U_0402_16V7K~D
    N35 2 -

    1
    G
    FOX_JPD113E-LB103-7F

    1
    PC8

    PR7
    LM393DR_SO8 PR8

    4
    PC7 PD1 10K_0402_5%~D
    1000P_0402_50V7K~D RLZ4.3B_LL34

    2
    2

    2
    PR10 +5VALW +3VALW
    PR9 10K_0402_5%~D RTCVREF
    1K_1206_5%~D 2 1
    1 2 3.3V

    DA204U_SOT323~D
    PQ1
    PR11 TP0610K-T1-E3_SOT23-3

    2
    PD3

    2.2K_0402_5%~D
    VIN PD2 1K_1206_5%~D @ PR12
    2 1 1 2 3 1
    B+ 1 2

    2
    0_0402_5%~D
    RLS4148_LL34 PR14
    ACIN

    PR13
    1K_1206_5%~D
    PR17
    1 2
    Precharge detector

    1
    100K_0402_5%~D

    100K_0402_5%~D
    33_0402_5%~D

    1
    1

    1
    PR16

    PR18
    PR15 DOCK_PSID
    Min. typ. Max.

    S
    1 3 1 2 PS_ID 29
    1K_1206_5%~D

    2
    2
    PQ2 2
    1 2
    H-->L 14.589V 14.84V 15.243V FDV301N_NL_SOT23-3~D

    G
    2
    15K_0402_1%~D 100K_0402_1%~D
    +5VALW
    L-->H 15.562V 15.97V 16.388V
    2

    2
    +5VALW

    PR19

    DA204U_SOT323~D
    BATT ONLY

    10K_0402_1%~D
    1

    2
    100K_0402_5%~D

    PD5
    Precharge detector

    1
    1

    1
    PR20

    PR21
    C
    PQ3
    Min. typ. Max. 2
    1

    B MMST3904-7-F_SOT323~D @

    2
    PQ4 E
    H-->L 6.138V 6.214V 6.359V

    2
    PR22
    DTC115EUA_SC70-3
    1 2

    1
    @
    L-->H 7.196V 7.349V 7.505V

    1
    29,34 ACOFF 2 PD4 PR23 PSID_DISABLE# 29
    PQ5 SM24_SOT23 1 2

    1
    DTC115EUA_SC70-3
    @ 10K_0402_1%~D
    2
    3

    VIN
    3

    2
    PD6
    RLS4148_LL34-2
    PD7
    RLS4148_LL34-2
    B+

    1
    PR24
    VL 2.2M_0402_5%~D BATT+ 2 1

    1
    2 1
    3
    PR25 PR26 3

    68_1206_5%~D 68_1206_5%~D

    PR28 PQ6

    2
    1

    200_0805_5%~D
    VS PR27 CHGRTCP 1 2 N1 3 1
    VS

    0.22U_1206_25V7K~D
    499K_0402_1%~D
    1

    1
    PR29
    2

    1
    100K_0402_1%~D PR30

    PC9
    100K_0402_5%~D PC10
    32,35 MAINPWON 0.1U_0603_25V7K~D
    2

    2
    8

    PD8 PR31 TP0610K-T1-E3_SOT23-3

    2
    2 5 22K_0402_5%~D
    P

    +
    1 7 O 1 2
    30 51ON#
    191K_0402_1%~D

    0.01U_0402_25V7K~D

    34 ACON 3 - 6
    1

    1
    G

    LM393DR_SO8
    1
    1000P_0402_50V7K~D

    PR32

    PC13

    RB715F_SOT323-3 PU1B PR33


    4
    1

    499K_0402_1%~D
    PC12

    PC11
    2

    0.1U_0603_25V7K~D RTCVREF
    2

    PRG++ 2

    1
    PR34
    200_0805_5%~D
    PU2
    3.3V

    2
    PR35 PQ7 PR36 3 2 N2
    OUT IN
    1

    34K_0402_1%~D D RHU002N06_SOT323-3 47K_0402_5%~D


    2 1 2 2 1 PACIN
    RTCVREF

    1
    G GND
    1

    S PC14 APL5156_SOT89-3 PC15


    3

    PQ8 10U_0805_10V4Z~D 1 1U_0805_25V4Z~D

    2
    4
    DTC115EUA_SC70-3 4

    2 +5VALW
    3

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/2/6 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DCIN & DETECTOR
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 33 of 43
    A B C D
    A B C D

    B+
    PL3
    Iada=0~3.42A(65W) FBMA-L18-453215-900LMA90T_1812

    2200P_0402_25V7K~D
    0.1U_0603_25V7K~D
    1 2

    2200P_0402_25V7K~D

    2200P_0402_25V7K~D

    2200P_0402_25V7K~D

    2200P_0402_25V7K~D

    2200P_0402_25V7K~D

    2200P_0402_25V7K~D
    ADP_I = 19.9*Iadapter*Rsense

    1
    1

    PC72

    PC73
    PQ11 PQ12 PQ13
    P2

    PC74

    PC75

    PC76

    PC77

    PC78

    PC79
    AO4407A_SO8 AO4407A_SO8 PR57 AO4407A_SO8

    2
    P3 0.02_2512_1% CHG_B+

    2
    VIN 8 1 1 8 1 8
    7 2 2 7 1 4 2 7
    6 3 3 6 3 6
    5 5 2 3 CSIN 5
    1 1

    10U_1206_25V6M~D

    10U_1206_25V6M~D

    2200P_0402_25V7K~D
    0.1U_0603_25V7K~D
    CSIP

    4
    PQ14

    1
    TP0610K-T1-E3_SOT23-3

    PC27

    PC28
    PR107
    1

    5600P_0402_25V7K~D

    PC29

    PC30
    10_1206_5%~D PR60

    200K_0402_1%~D
    0.1U_0603_25V7K~D
    PR58 3 1 1 2 DCIN 47K_0402_1%~D

    2
    P3

    2
    PR59
    47K_0402_1%~D 1 2
    VIN

    1
    100K_0402_1%~D
    PC31

    PC32
    PQ15
    2

    1
    PR61
    DTC115EUA_SC70-3 PD14

    2
    1SS355TE-17_SOD323-2
    PD13 PR63 1 2 ACOFF

    2
    3

    PQ16 PR62 2FSTCHG 10K_0402_1%~D

    2
    DTA144EUA_SC70-3 PD15 2 1 21
    1SS355TE-17_SOD323-2 3 SUSP#

    1
    2 1 2 6251VDD 100K_0402_1%~D SUSP# 19,29,31,36,37 PR64

    2.2U_0603_6.3V6K~D
    RB715F_SOT323-3 200K_0402_1%~D

    PC33
    PR65 1 2 VIN

    3
    1
    10K_0402_5%~D

    1
    2 1 PU4 PC35
    29 FSTCHG
    1

    0.1U_0603_25V7K~D
    1

    2
    1 2 1 24 DCIN 2 1 PD16
    VDD DCIN

    100K_0402_1%~D
    6251VDD 1 2 PC34 PQ18 1SS355TE-17_SOD323-2
    0.1U_0402_16V7K~D DTC115EUA_SC70-3 2 1 2

    PR67
    2 PR66 2 23
    PQ17 47K_0402_5%~D PQ19 ACSET ACPRN PR69 PQ20

    1
    DTC115EUA_SC70-3 DTC115EUA_SC70-3 20_0603_5% D RHU002N06_SOT323-3

    5
    6
    7
    8

    1
    0.1U_0603_25V7K~D
    6251_EN 3 22 1 2 CSON 2 PACIN

    3
    EN CSON
    1

    2
    D

    PC36
    2 @ PC37 PC38 PQ22 G
    32 3S/4S#
    3

    2 PR68 680P_0402_50V7K~D 0.047U_0603_16V7K~D AO4710_SO8 S

    3
    G 150K_0402_1%~D CSON 1 2 4 21 1 2 CSOP

    1
    CELLS CSOP
    S PQ21 PR70
    3

    2
    RHU002N06_SOT323-3 PC39 6800P_0402_25V7K~D 20_0603_5% 4 2
    2

    3
    1 2 5 ICOMP CSIN 20 2 1

    2
    PR71 20_0603_5%
    PC41 PR72 10K_0402_1%~D PC40 0.1U_0603_25V7K~D
    1 2 1 2 6 19 1 2 PR75

    3
    2
    1
    PR74 VCOMP CSIP PR73 PL4 0.02_2512_1%
    0.01U_0402_25V7K~D 1
    2 100_0402_1%~D 2.2_0603_5%~D 10UH_PCMB104T-100MS_6A_20% BATT+
    PR76 PC42 1 2 7 18 LX_CHG 1 2 CHG 1 4
    ICM PHASE
    1

    22K_0402_5%~D D 100P_0402_50V8J~D

    4.7_1206_5%~D
    PACIN 1 2 2 PQ23 @ 2 3
    33 PACIN

    1
    G RHU002N06_SOT323-3
    29 ADP_I 6251VREF 8 17 DH_CHG
    VREF UGATE

    5
    6
    7
    8

    PR77
    S PC43 PR78 PC44
    3

    10U_1206_25V6M~D
    PR79 1 2 2.2_0603_5%~D 0.1U_0603_25V7K~D PQ24

    10U_1206_25V6M~D

    10U_1206_25V6M~D
    150K_0402_1%~D 9 16 BST_CHG 1 2 BST_CHGA 2 1 AO4466_SO8
    CHLIM BOOT

    1
    ACON 2 1 0.1U_0402_16V7K~D
    33 ACON

    1 2
    29 IREF

    1
    PC45

    PC46

    PC47
    0.01U_0402_25V7K~D

    PD17
    6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2 4
    ACLIM VDDP
    1

    680P_0402_50V7K~D
    PC49

    2
    1
    PC48

    PQ25 PR80 1 26251VDD

    2
    DTC115EUA_SC70-3 100K_0402_1%~D 11 14 DL_CHG
    VADJ LGATE

    2
    PR81
    2

    3
    2
    1
    ACOFF 2 4.7_0603_5%~D
    29,33 ACOFF
    2

    12 13 PC50

    1
    GND PGND 4.7U_0805_6.3V6K~D

    6251VREF 1 2 ISL6251AHAZ-T_QSOP24
    3

    PR82
    11.5K_0402_1%~D
    PR83
    2.87K_0402_1%~D
    CP mode
    2

    3 3

    Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)
    Vaclim=2.87*((11.5K//152K)/((2.87K//152K)+(11.5K//152K)))
    PR84
    25.5K_0402_1%~D
    1 2
    29 CHGVADJ
    1

    CC=0.22~3.3A PR85
    100K_0402_1%~D
    CHGVADJ CV mode
    IREF=1*Icharge
    2

    IREF=0.22V~3.294V 0V 4V per cell

    1.882V 4.2V per cell

    3.294V 4.45V per cell

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/2/6 Deciphered Date 2010/12/31 Title
    -
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CHARGER
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ULV 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 34 of 43
    A B C D
    5 4 3 2 1

    TPS51427_B+
    TPS51427_B+
    PL7 PR86
    FBMA-L18-453215-900LMA90T_1812 0_0805_5%~D
    1 2 1 2
    B+

    2200P_0402_50V7K~D
    1000P_0402_50V7K~D

    1000P_0402_50V7K~D

    2200P_0402_50V7K~D
    4.7U_0805_25V6-K~D

    4.7U_0805_25V6-K~D

    4.7U_0805_25V6-K~D

    4.7U_0805_25V6-K~D
    0.1U_0603_25V7K~D

    0.1U_0603_25V7K~D
    VL
    1

    8
    7
    6
    5

    5
    6
    7
    8
    PC51

    PC52

    PC54

    PC55

    PC56
    PC199
    D D

    1
    PC53
    PC144

    PC145

    PC197
    PQ26 PQ27
    2

    2
    AO4466_SO8 AO4466_SO8

    4.7U_0805_6.3V6K~D

    2
    2

    1U_0603_10V6K~D
    PC57

    2
    4 0.1U_0603_25V7K~D 4

    1
    PC58
    1

    PC59
    1
    +5VALWP

    2
    1
    2
    3

    3
    2
    1
    PL6

    7
    PL5 PU5 PC60 1 2
    1 2 1U_0603_10V6K~D 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

    LDO
    VIN

    VCC
    +3VALWP

    5
    6
    7
    8
    2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% 33 19 1 2 PQ29
    TP PVCC

    8
    7
    6
    5

    680P_0402_50V7K~D 4.7_1206_5%~D
    1
    PQ28 DH3 26 15 DH5 AO4710_SO8
    UGATE2 UGATE1

    PR91
    PR87 AO4710_SO8 PR88 2.2_0603_5%~D PR89 2.2_0603_5%~D
    4.7_1206_5%~D 2 1 BST3A 24 17 BST5A 2 1
    BOOT2 BOOT1
    1

    2
    2

    61.9K_0402_1%~D
    PR90 4 PC63

    PR92
    330U_D3L_6.3VM_R25M
    0.1U_0402_10V7K~D

    1 0_0402_5%~D PC62 0.1U_0603_25V7K~D

    2
    0.1U_0603_25V7K~D

    1
    1

    1
    +
    PC61

    PC65

    330U_D3L_6.3VM_R25M
    LX3 LX5

    0.1U_0402_10V7K~D
    25 16 1
    2

    3
    2
    1
    PHASE2 PHASE1
    PC200

    PC64

    1
    2
    3

    1
    +

    PC66
    680P_0402_50V7K~D
    2

    2
    2

    PC206
    DL3 23 18 DL5

    1
    LGATE2 LGATE1

    2
    2
    2

    0_0402_5%~D
    C 22 C
    PGND

    2
    FB3 30 OUT2

    PR94
    @ PR93
    10K_0402_1%~D 10
    OUT1
    VL 32
    1

    REFIN2

    1
    11 FB5
    2VREF_TPS51427 FB1
    PC67
    1 2 1 REF
    0.22U_0603_10V7K~D
    BYP 9
    8 LDOREFIN @ PR95 0_0402_5%~D
    SKIP 29 2 1 VL
    PR96 0_0402_5%~D
    1 2
    20 28 @
    PD18 PR97 NC POK2
    RLZ5.1B_LL34-2 100K_0402_1%~D
    1 2 1 2 4 13 POK
    VS EN_LDO POK1 PR99
    2
    200K_0402_1%~D

    267K_0402_1%~D
    2
    PR98

    14 12 ILM1 2 1
    PC68 EN1 ILIM1
    0.22U_0603_10V7K~D
    1

    27 31 ILIM2 2 1

    GND
    TON
    1

    EN2 ILIM2
    1

    B PJP5 B

    NC
    2
    1 2 PR100
    1 2 VL

    0_0402_5%~D
    PD19 @ PR101 TPS51427_QFN32_5X5 169K_0402_1%~D

    21
    PR102
    JUMP_43X118 @ CH355PT_SOD323-2 0_0402_5%~D
    2
    2

    PJP6 PR103
    1

    1
    1U_0603_10V6K~D
    +3VALW 1 2 +3VALWP 806K_0603_1%~D 2VREF_TPS514271
    1 2
    JUMP_43X118 @ PR105 @ PR106 PR104
    1

    2
    PC69
    PJP7 0_0402_5%~D 47K_0402_5%~D 0_0402_5%~D
    1 1 2 2 2 1 1 2 +5VALWP

    2VREF_TPS514272
    1
    JUMP_43X118 @
    .1U_0603_25V7K~D

    PJP8 32,33 MAINPWON


    1

    Thermal Design current=5.8A


    PC70

    +5VALW 1 1 2 2 +5VALWP
    JUMP_43X118 @
    2

    OCP min=10A
    1

    @ PC71
    3

    0.047U_0402_16V7K~D
    2

    Fsw=400KHZ
    +3.3VALWP 2 PQ30
    TP0610K-T1-E3_SOT23-3

    Thermal Design current=4.2A


    A A
    1

    OCP min=7A
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Fsw=300KHZ Issued Date 2009/2/6 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    +5VALWP/+3VALWP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 35 of 43

    5 4 3 2 1
    A B C D

    +VCCPP

    Thermal Design current=11.5A

    OCP min=19.5A

    Fsw=290KHZ
    1 1

    PL9
    FBMA-L18-453215-900LMA90T_1812
    +VCCPP_B+ 1 2 B+

    2200P_0402_50V7K~D

    0.1U_0603_25V7K~D
    2200P_0402_50V7K~D

    1
    PC187
    0.1U_0603_25V7K~D

    @
    10U_1206_25V6M~D

    10U_1206_25V6M~D

    10U_1206_25V6M~D

    PC186
    1

    1
    PC175

    2
    PC174

    PC176

    PC177

    PC185
    2

    2
    +3VALW

    100K_0402_1%~D
    1

    SI7686DP-T1-E3_SO8
    @

    PR204

    PQ47
    PR205 PC178

    D
    2.2_0603_5%~D 0.22U_0603_10V7K~D
    BST_VCCPP 1 2 1 2
    2

    2 2
    2 G
    PR206 PU15
    PG_VCCPP 1 10
    PGOOD VBST

    S
    69.8K_0402_1%~D
    PR207 1 2 TRIP_VCCPP 2 9 UG_VCCPP PL13

    1
    0_0402_5%~D TRIP DRVH 1UH_FDUE1040D-1R0M-P3_21.3A_20%
    1 2 EN_VCCPP 3 8 SW_VCCPP 1 2 +VCCPP
    19,29,31,34,37 SUSP# EN SW
    FB_VCCPP 4 7 V5IN_VCCPP +5VALW
    VFB V5IN
    1

    SI7170DP-T1-GE3-POWERPAK8-5
    @ PC106

    1
    PQ48
    1U_0603_6.3V6M~D

    10U_0805_6.3V6M~D
    0.1U_0402_10V7K~D
    0.1U_0402_16V7K~D RF_VCCPP 5 6 LG_VCCPP 1 1

    D
    RF DRVL

    330U_Y_2.5VM

    330U_Y_2.5VM
    1 1
    2

    1
    PC179

    PR208

    PC181

    PC182

    PC183
    11 + +
    TP
    1

    PC180
    4.7_1206_5%~D
    PR209 TPS51218DSCR_SON10_3X3~D 2

    2
    470K_0402_5%~D 2 G 2 2 2

    1
    S
    2

    PC184
    1
    680P_0402_50V7K~D

    2
    PR210 PR211

    20K_0402_1%~D 10K_0402_1%~D
    1 2 2 1
    3
    @ 3

    PJP29
    JUMP_43X118
    +VCCPP 1 1 2 2 +VCCP

    PJP30
    JUMP_43X118
    1 1 2 2

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/2/5 Deciphered Date 2010/12/31 Title
    +VCCPP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 36 of 43
    A B C D
    A B C D

    +1.5VP

    1
    PJP12

    1
    JUMP_43X79
    1 1

    2
    @

    2
    PU7
    1 VIN VCNTL 6 +3VALW
    2 GND NC 5

    1
    1
    PC91 3 7 PC92
    4.7U_0805_6.3V6K~D PR115 VREF NC

    2
    1K_0402_1%~D 4 8 1U_0603_10V6K~D
    VOUT NC
    9

    2
    TP
    APL5331KAC-TRL_SO8

    0.1U_0402_16V7K~D
    PR116
    +0.75VSP

    1
    10K_0402_1%~D D

    1K_0402_1%~D

    PC93
    17,31 SUSP 1 2 2

    1
    G

    2
    1
    S PQ33 PR117 PC94

    3
    PC95 RHU002N06_SOT323-3 10U_0603_6.3V6M~D

    2
    PR118 0.1U_0402_16V7K~D

    2
    10K_0402_1%~D
    31 SYSON# 1 2

    PJP13
    2 2
    +0.75VSP 2 2 1 1 +0.75VS
    @ JUMP_43X118

    +3VALW
    +5VALW

    1
    PJP14

    1
    JUMP_43X79

    2
    @

    2
    PC96
    1U_0603_10V6K~D

    1
    PC97
    4.7U_0805_6.3V6K~D

    2
    PU8
    6 VCNTL
    5 3
    PR119 9
    VIN
    VIN
    VOUT
    VOUT 4 +1.8VP
    10K_0402_1%~D

    1
    19,29,31,34,36 SUSP# SUSP#

    22U_0805_6.3V4Z~D
    1 2 8 EN

    PC100
    7 2

    GND
    POK FB

    1
    @ PR121

    2
    3 3

    PC98 PR120 1.5K_0402_1%~D


    1U_0603_10V6K~D 47K_0402_5%~D APL5913-KAC-TRL_SO8

    2
    2
    PC99

    1
    0.01U_0402_25V7K~D

    PR122
    @ PR123 1.2K_0402_1%~D
    10K_0402_1%~D

    2
    29,31,38 SYSON SYSON 1 2

    1
    PC101
    1U_0603_10V6K~D

    2
    @
    PJP15
    +1.8VP 2 2 1 1 +1.8V
    @ JUMP_43X118

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/2/5 Deciphered Date 2010/12/31 Title
    +1.8VP / +0.75VP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 37 of 43
    A B C D
    A B C D

    +1.5VSP

    Thermal Design current=11.5A

    OCP min=20A

    Fsw=300KHZ
    1 1

    PL12
    FBMA-L18-453215-900LMA90T_1812
    +1.5VSP_B+ 1 2 B+

    2200P_0402_50V7K~D
    2200P_0402_50V7K~D

    0.1U_0805_50V7M~D

    1
    @
    10U_1206_25V6M~D

    10U_1206_25V6M~D

    10U_1206_25V6M~D
    1

    PC116
    PC102

    PC103

    PC104

    PC105

    PC115

    2
    2

    2
    +1.5VP

    100K_0402_1%~D
    1

    PR124
    2

    SI7686DP-T1-E3_SO8~D
    PQ34
    PR125 PC107

    D
    2.2_0603_5%~D 0.22U_0603_10V7K~D
    8 SM_PWROK BST_1.5VSP 1 2 1 2
    2 2
    2 G
    PR126 PU9
    PG_1.5VSP 1 10
    PGOOD VBST

    S
    71.5K_0402_1%~D
    PR127 1 2 TRIP_1.5VSP 2 9 UG_1.5VSP PL8

    1
    0_0402_5%~D TRIP DRVH 1UH_FDUE1040D-1R0M-P3_21.3A_20%
    1 2 EN_1.5VSP 3 8 SW_1.5VSP 1 2 +1.5VP
    29,31,37 SYSON EN SW
    FB_1.5VSP 4 7 V5IN_1.5VSP +5VALW
    VFB V5IN
    1

    1
    SI7170DP-T1-GE3-POWERPAK8-5~D
    @ PC108

    PQ35
    1U_0603_6.3V6M~D

    10U_0805_6.3V6M~D
    0.1U_0402_10V7K~D
    0.1U_0402_16V7K~D RF_1.5VSP 5 6 LG_1.5VSP 1 1

    D
    RF DRVL PR128

    330U_Y_2.5VM

    330U_Y_2.5VM
    1 1
    2

    1
    4.7_1206_5%

    PC109

    PC111

    PC112

    PC113
    11 + +
    TP
    1

    PC110
    2
    PR129 TPS51218DSCR_SON10_3X3~D 2

    2
    470K_0402_5%~D 2 G 2 2 2

    1
    S
    PC114
    2

    680P_0402_50V7K~D

    2
    PR130 PR131

    10K_0402_1%~D 11.5K_0402_1%~D
    1 2 2 1
    3
    @ 3

    PJP17
    JUMP_43X118
    +1.5VP 1 1 2 2 +1.5V

    PJP18
    JUMP_43X118
    1 1 2 2

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/2/5 Deciphered Date 2010/12/31 Title
    +1.5VSP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 38 of 43
    A B C D
    5 4 3 2 1

    +VCCP
    2

    D D
    PR143 PR144
    68_0402_5%~D 0_0402_5%~D
    8,22 PM_DPRSLPVR 1 2 +5VALW

    5
    CPU_VID25

    5
    CPU_VID6

    CPU_VID5
    CPU_VID4

    CPU_VID3

    CPU_VID1

    CPU_VID0
    1

    PR145 +CPU_B+ PL10

    29
    VR_ON
    0_0402_5%~D HCB2012KF-121T50_0805

    2
    5,8,21 H_DPRSTP# 1 2 1 2 B+
    PR147 0_0402_5%~D PR146

    2200P_0402_50V7K~D

    1000P_0402_50V7K~D

    1000P_0402_50V7K~D
    H_PROCHOT# 1 2 1_0603_5%~D
    CLK_ENABLE#

    1000P_0402_50V7K~D
    0.1U_0603_25V7K~D

    4.7U_0805_25V6-K~D

    4.7U_0805_25V6-K~D

    4.7U_0805_25V6-K~D
    PR148

    1
    0_0402_5%~D

    1
    +3VALW 1 2

    1
    1U_0603_6.3V6M~D

    PC146

    PC147
    1

    1
    0_0402_5%~D

    0_0402_5%~D

    PC205

    PC117

    PC118

    PC119

    PC120

    PC121
    1U_0603_10V6K~D
    0.01U_0402_16V7K~D
    PC122

    2
    1

    2 PR150 1

    PC123

    PC124

    2
    PR171

    SI7686DP-T1-E3_SO8
    PR149

    PQ63
    1.91K_0402_1%~D

    D
    2
    22,29 VGATE 2
    2 G
    @
    1

    41

    40

    39

    38

    37

    36

    35

    34

    33

    32

    31

    S
    PR151 @ PU10
    0_0402_5%~D

    PGOOD
    GND PAD

    CLK_EN

    VR_ON
    3V3

    DPRSTP#

    DPRSLPVR

    VID6

    VID5

    VID4

    VID3
    PC126

    1
    1

    PC125 PL11
    0.22U_0603_10V7K~D
    0.1U_0402_16V7K~D 0.45UH_ETQP4LR45XFC_25A_-25+20%
    2

    1 FDE VID2 30 1 2 1 2 1 2 +VCC_CORE


    2

    @ PR152 40.2K_0402_1%~D
    C 2 PMON 29 PR153 C
    8,22,29 PM_PWROK 1 2 VID1

    1
    PR154 147K_0402_1%~D 2.2_0603_5%~D

    1
    SI7170DP-T1-GE3-POWERPAK8-5
    1 2 3 RBIAS VID0 28
    PR155

    PQ62
    D
    H_PROCHOT# 4 27 4.7_1206_5%~D PR156
    4 H_PROCHOT# VR_TT# VCCP
    @ @ PH2 470K_0402_5%_TSM0B474J4702RE 7.68K_0805_1%~D
    PR157

    2
    1 2 1 2 5 26 LGATE_CPU1
    NTC LGATE

    2 VSUM
    4.22K_0402_1%~D 2 G
    1 2 PC127 6 SOFT VSSP 25

    1
    @ PC148 0.015U_0603_25V7K

    S
    1 2 7 24 PHASE_CPU1 PC128
    OCSET PHASE
    PR158 680P_0402_50V7K~D

    2
    0.1U_0402_10V7K~D 10K_0402_1%~D 8 23 UGATE_CPU1
    VW UGATE
    1 2
    9 22 BOOT_CPU1
    COMP BOOT
    DROOP

    10 FB NC 21
    VDIFF
    2

    VSUM
    VSEN

    VDD
    RTN

    DFB

    VSS
    2

    VIN
    VO

    PR159
    PC129 ISL6261ACRZ-T_QFN40_6X6
    6.81K_0402_1%~D 1000P_0402_50V7K~D
    11

    12

    13

    14

    15

    16

    17

    18

    19

    20
    1
    1

    PC130 PR160 464K_0402_1%~D


    2 1 1 2

    150P_0402_50V8J~D
    1 2 +5VALW
    1 2 PR161
    1

    10_0603_5%~D
    B PC131 47P_0402_50V8J~D PC132 B
    1U_0603_10V6K~D
    2

    PR163 PC133
    330_0402_1%~D 390P_0402_50V7K~D PR162
    1 2 1 2 10_0603_5%~D
    1 2 +CPU_B+
    1

    PR164
    2.21K_0402_1%~D PC134
    1 2 0.22U_0603_25V7K~D
    2

    PC135 1000P_0603_50V7K~D
    5 VCCSENSE 1 2 1 2
    PR165 VSUM
    1

    1
    PC139 0.1U_0402_10V7K~D

    PC140.068U_0402_10V7K~D

    0_0402_5%~D
    4.53K_0402_1%~D

    PC136 PR166
    1

    1000P_0402_50V7K~D 3.57K_0402_1%~D
    2

    1 2
    2 2
    2

    5 VSSSENSE PR168
    0_0402_5%~D PC138 330P_0402_50V7K~D
    2
    1

    1 2 PH3
    1

    PC137
    10KB_0402_5%_ERTJ0ER103J
    330P_0402_50V7K~D 1 2 1 2
    2

    PR167

    PR169 PR170
    1K_0402_1%~D 9.1K_0402_1%~D

    +VCC_CORE

    A A
    2

    PC141
    0.22U_0603_10V7K~D
    1

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/23 Deciphered Date 2010/12/31 Title
    CPU_CORE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 39 of 43
    5 4 3 2 1
    5 4 3 2 1

    Version Change List ( P. I. R. List ) Page 1


    Request
    Item Page# Title Date Owner Issue Description Solution Description Rev.

    1 39 CPU_CORE 09' 09/09 Compal_Will Modify CPU load line PR170 change 6.65K_1%_0402 to 9.1K_1%_0402 0.5
    D D

    C C

    B B

    A A

    Compal Electronics, Inc.


    Title
    PWR-PIR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-5541P
    Date: Thursday, September 10, 2009 Sheet 40 of 43
    5 4 3 2 1
    5 4 3 2 1

    Version Change List ( P. I. R. List ) Page 1/1


    Request
    Item Page# Title Date Owner Issue Description Solution Description Rev.
    1 21, 23 2009/06/05 Compal HDMI NO SOUND ADD R319, R320, R323, R321 DEL R322, R324, R92 0.2
    D 2 D
    29, 30 2009/06/05 Compal Battery LED can't work ADD NET BAT_CHG_LED# 0.2

    3 19 2009/06/05 Compal Change JLVDS connect 0.2

    4 24 2009/06/05 Compal Change JODD1 connect 0.2

    5 17 2009/06/05 Compal Change Level sfift IC to ASMEDIA 0.2

    6 16 2009/06/18 Compal reserve R1535 to using LOW POWER CLK GEN RTM890~397 0.3

    7 26 2009/06/24 Compal
    DEL Y5 C1244, C1246 0.3
    8 19 2009/07/08 Compal
    reserve Q39,Q40,R1536, R1537, C1359, C1360, C1361, C1362 0.3
    9 30 2009/07/08 Compal
    Del C313 D14 0.3
    10 29,30 2009/07/08 Compal
    Add EAPD trace 0.3
    11 25 2009/07/23 Compal
    Add C1363 1.0
    12 30 2009/07/23 Compal
    C
    Change Keyboard footprint 1.0 C
    13

    14

    15

    16

    17

    18

    19

    20

    21

    22

    B 23 B

    24

    25

    26

    27

    28

    29

    30

    31

    32

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EE PIR-1
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5541P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Thursday, September 10, 2009 Sheet 41 of 43
    5 4 3 2 1
    5 4 3 2 1

    U1 U1 U1
    ZZZ1

    D X76 PCB-MB
    PENRYN SFF_UFCBGA956 PENRYN SFF_UFCBGA956 PENRYN SFF_UFCBGA956 D
    723@ SU3500@ SU9400@

    U1 U1

    PENRYN SFF_UFCBGA956 PENRYN SFF_UFCBGA956


    SU4100@ SU7300@

    C C
    U1 U1

    PENRYN SFF_UFCBGA956 PENRYN SFF_UFCBGA956


    U5_R3@ R3_SU3500@ R3_SU9400@

    U1 U1

    U3_R3@ PENRYN SFF_UFCBGA956 PENRYN SFF_UFCBGA956


    R3_SU4100@ R3_SU7300@

    B B

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/04/01 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    BOM structure
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    A MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    A
    Date: Thursday, September 10, 2009 Sheet 42 of 43
    5 4 3 2 1

    +3/5VALW

    ON/OFF#

    ON/OFFBTN#
    D D

    SYSON

    +1.5V

    PM_RSMRST#

    ICH_SUSCLK > 110ms


    SLP_S5#
    programmable

    SLP_S4#

    C C
    30~120us

    SLP_S3#

    SUSP#

    +5VS > +3VS > +1.5VS > +VCCP

    VR_ON

    +CPU_CORE
    B B

    VGATE
    This signal is
    asserted high when
    both SLP_S3# and
    VRMPWRGD are high
    CK_PWRGD
    VGATE to PM_PWROK
    > 5ms
    VCCP to PM_PWROK
    PM_PWROK > 99ms
    PM_PWROK to PLT_RST#
    1.05ms~2.22ms

    PLT_RST#

    H_PWRGOOD

    A A

    H_RESET#

    Title
    <Title>

    Size Document Number Rev


    CustomLA-5541P 1.0

    Date: Thursday, September 10, 2009 Sheet 43 of 43


    5 4 3 2 1

    You might also like