Multimode Controller For SMPS: Features
Multimode Controller For SMPS: Features
Multimode Controller For SMPS: Features
Features
■ Selectable multimode operation: fixed
frequency or quasi-resonant
■ On-board 840 V high voltage startup
■ Advanced light load management
■ Low quiescent current (< 3 mA)
SO16N
■ Adaptive UVLO
■ Line feedforward for constant power capability
■ -600/+800 mA totem pole gate driver with
vs. mains voltage
active pull-down during UVLO
■ Pulse-by-pulse OCP, shutdown on overload
■ SO16N package
(latched or auto-restart)
■ Transformer saturation detection
Applications
■ Programmable frequency modulation for EMI
reduction ■ Industrial SMPS
■ Latched or auto-restart OVP ■ SMPS running off rectified 3-phase input line
■ Brownout protection
Figure 1. Block diagram
10 14 9 15 VCC 6.4V
TIME -
OVPL
1 SOFT-START OUT OVP
LOW CLAMP OFF2 Icharge
HV & & DISABLE
+
FAULT MNGT
LINE VOLTAGE 7.7V
Q
I HV Reference FEEDFORWARD
VOLTAGE CS
voltages
REGULATOR LEB
VCC Internal supply
5 &
1.5 V 7
ADAPTIVE UVLO UVLO
- + - + + -
VCC Vth PWM OCP VCC
UVLO_SHF
400 uA +
6
FMOD
- - Hiccup-mode
OCP logic 14V
+ 5.7V BURST-MODE
OCP2 4
GD
OSC 13
OSCILLATOR R
Q DRIVER
MODE SELECTION S
&
MODE/SC 12 TURN-ON LOGIC
TIME
50 mV ZERO CURRENT
- OUT OVPL
100 mV DETECTOR
ZCD + 4.5V
11 OVP OFF2 -
OVERVOLTAGE
LATCH
PROTECTION
+
DIS
IC_LATCH 8
16
AC_OK - AC_FAIL
DISABLE
15 µA 0.450V
3V + UVLO
0.485V
3
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Zero-current detection and triggering block; oscillator block . . . . . . . . . . 19
5.3 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 22
5.4 Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5 PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6 PWM comparator, PWM latch and voltage feedforward blocks . . . . . . . . 25
5.7 Hiccup-mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.8 Frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9 Latched disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.10 Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 32
5.11 OVP block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.12 Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.13 Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.14 Summary of L6566BH power management functions . . . . . . . . . . . . . . . 39
8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of tables
Table 1. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. L6566BH light load management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. L6566BH protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7. External circuits that determine IC behavior upon OVP and OCP . . . . . . . . . . . . . . . . . . . 44
Table 8. SO16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 9. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Pin connection (through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Multimode operation with QR option active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. High voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5 V) . . . . . . . . . . . . . . 19
Figure 8. VHV rating vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Drain ringing cycle skipping as the load is gradually reduced . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active) . . . . . . . . . . . . . . . . 22
Figure 11. Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Addition of an offset to the current sense lowers the burst-mode operation threshold . . . . 23
Figure 13. Adaptive UVLO block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Possible feedback configurations that can be used with the L6566BH . . . . . . . . . . . . . . . 24
Figure 15. Externally controlled burst-mode operation by driving the COMP pin: timing diagram. . . . 25
Figure 16. Typical power capability change vs. input voltage in QR flyback converters . . . . . . . . . . . 26
Figure 17. Left: overcurrent setpoint vs. VFF voltage; right: line feedforward function block. . . . . . . . 27
Figure 18. Hiccup-mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. Frequency modulation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. Operation after latched disable activation: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21. Soft-start pin operation under different operating conditions and settings . . . . . . . . . . . . . 33
Figure 22. OVP function: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23. OVP function: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 24. Maximum allowed duty cycle vs. switching frequency for correct OVP detection. . . . . . . . 36
Figure 25. Brownout protection: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . . 37
Figure 26. Voltage sensing techniques to implement brownout protection with the L6566BH . . . . . . 38
Figure 27. Slope compensation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 28. Typical low-cost application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 29. Typical full-feature application schematic (QR operation) . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 30. Typical full-feature application schematic (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 31. Frequency foldback at light load (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 32. Latched shutdown upon mains overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 33. SO16N package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 34. Recommended footprint (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
1 Description
Rectified
& Filtered
Mains
Voutdc
Voltage L6566BH
2 Pin settings
2.1 Connections
Figure 3. Pin connection (through top view)
HVS 1 16 AC_OK
N.C. 2 15 VFF
GND 3 14 SS
GD 4 13 OSC
Vcc 5 12 MODE/SC
FMOD 6 11 ZCD
CS 7 10 VREF
DIS 8 9 COMP
AM11479v1
High voltage startup. The pin, able to withstand 840 V, is to be tied directly to the
rectified mains voltage. A 1 mA internal current source charges the capacitor
connected between the Vcc pin (5) and GND pin (3) until the voltage on the Vcc pin
reaches the turn-on threshold, it is then shut down. Normally, the generator is re-
1 HVS enabled when the Vcc voltage falls below 5 V to ensure a low power throughput
during short-circuit. Otherwise, when a latched protection is tripped the generator is
re-enabled 0.5 V below the turn-on threshold, to keep the latch supplied; or, when
the IC is turned off by the COMP pin (9) pulled low, the generator is active just
below the UVLO threshold to allow a faster restart.
Not internally connected. Provision for clearance on the PCB to meet safety
2 N.C.
requirements.
Ground. Current return for both the signal part of the IC and the gate drive. All of
3 GND the ground connections of the bias components should be tied to a track going to
this pin and kept separate from any pulsed current return.
Gate driver output. The totem pole output stage is able to drive Power MOSFETs
4 GD
and IGBTs with a peak current capability of 800 mA source/sink.
Supply voltage of both the signal part of the IC and the gate driver. The internal
high voltage generator charges an electrolytic capacitor connected between this
pin and GND (pin 3) as long as the voltage on the pin is below the turn-on threshold
of the IC, after that it is disabled and the chip is turned on. The IC is disabled as the
5 Vcc
voltage on the pin falls below the UVLO threshold. This threshold is reduced at light
load to counteract the natural reduction of the self-supply voltage. Sometimes a
small bypass capacitor (0.1 µF typ.) to GND might be useful to obtain a clean bias
voltage for the signal part of the IC.
Frequency modulation input. When FF mode operation is selected, a capacitor
connected from this pin to GND (pin 3) is alternately charged and discharged by
internal current sources. As a result, the voltage on the pin is a symmetrical
triangular waveform with the frequency related to the capacitance value. By
6 FMOD
connecting a resistor from this pin to pin 13 (OSC) it is possible to modulate the
current sourced by the OSC pin and then the oscillator frequency. This modulation
is to reduce the peak value of EMI emissions by means of a spread-spectrum
action. If the function is not used, the pin is left open.
Input to the PWM comparator. The current flowing in the MOSFET is sensed
through a resistor, the resulting voltage is applied to this pin and compared with an
internal reference to determine MOSFET turn-off. The pin is equipped with 150 ns
min. blanking time after the gate-drive output goes high for improved noise
7 CS immunity. A second comparison level located at 1.5 V latches the device OFF and
reduces its consumption in the case of transformer saturation or secondary diode
short-circuit. The information is latched until the voltage on the Vcc pin (5) goes
below the UVLO threshold, therefore resulting in intermittent operation. A logic
circuit improves sensitivity to temporary disturbances.
IC latched disable input. Internally, the pin connects a comparator that, when the
voltage on the pin exceeds 4.5 V, latches OFF the IC and brings its consumption to
a lower value. The latch is cleared as the voltage on the Vcc pin (5) goes below the
UVLO threshold, but the HV generator keeps the Vcc voltage high (see pin 1
8 DIS
description). It is then necessary to recycle the input power to restart the IC. For a
quick restart, pull pin 16 (AC_OK) below the disable threshold (see pin 16
description). Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-
up. Ground the pin if the function is not used.
Control input for loop regulation. The pin is driven by the phototransistor (emitter-
grounded) of an optocoupler to modulate its voltage by modulating the current
sunk. A capacitor placed between the pin and GND (3), as close to the IC as
possible to reduce noise pick-up, sets a pole in the output-to-control transfer
9 COMP
function. The dynamics of the pin are in the 2.5 to 5 V range. A voltage below an
internally defined threshold activates burst-mode operation. The voltage at the pin
is bottom-clamped at about 2 V. If the clamp is externally overridden and the
voltage is pulled below 1.4 V, the IC shuts down.
An internal generator furnishes an accurate voltage reference (5 V ± 2%) that can
be used to supply few mA to an external circuit. A small film capacitor (0.1 µF typ.),
connected between this pin and GND (3), is recommended to ensure the stability of
10 VREF
the generator and to prevent noise from affecting the reference. This reference is
internally monitored by a separate auxiliary reference and any failure or drift causes
the IC to latch OFF.
3 Electrical data
4 Electrical characteristics
(TJ = -25 to 125 °C, VCC = 12, CO = 1 nF; MODE/SC = VREF, RT = 20 kΩ from OSC to GND,
unless otherwise specified.)
Supply voltage
Supply current
Reference voltage
(1) T
VREF Output voltage J = 25 °C; IREF = 1 mA 4.95 5 5.05 V
IREF = 1 to 5 mA,
VREF Total variation 4.9 5.1 V
Vcc = 10.6 to 23 V
IREF Short-circuit current VREF = 0 10 30 mA
Internal oscillator
Brownout protection
PWM control
Thermal shutdown
Soft-start
Gate driver
5 Application information
fosc
Input voltage
Valley-skipping
f sw mode
Burst-mode
Quasi-resonant mode
0
0 Pinmax
P in
AM11480v1
If FF operation is selected:
1. FF mode from heavy to light load. The system operates exactly like a standard current
mode control, at a frequency fsw determined by the externally programmable oscillator:
both DCM and CCM transformer operations are possible, depending on whether the
power that it processes is greater or less than:
Equation 1
where Vin is the input voltage to the converter, VR the reflected voltage (i.e. the
regulated output voltage times the primary-to-secondary turn ratio) and Lp the
inductance of the primary winding. PinT is the power level that marks the transition from
continuous to discontinuous operation mode of the transformer.
2. Burst-mode with no or very light load. This kind of operation is activated in the same
way and results in the same behavior as previously described for QR operation.
The L6566BH is specifically designed for applications with no PFC front-end; pin 6 (FMOD)
features an auxiliary oscillator that can modulate the switching frequency (when FF
operation is selected) in order to mitigate EMI emissions by a spread-spectrum action.
HV
1
L6566BH 15 MW
Vcc_OK
HV_EN IHV
5 Vcc
CONTROL
I charge
GND
AM11481v1
With reference to the timing diagram of Figure 6, when power is first applied to the converter
the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is
enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus
the device consumption, charges the bypass capacitor connected from the Vcc pin (5) to
ground and makes its voltage rise almost linearly.
Vin
VHVstart
VccOFF
Vccrestart
t
GD
(pin 4)
t
HV_EN
t
cc_OK
Icharge t
0.85 mA
Normal t
Power-on Power-off
operation
AM11482v1
As the Vcc voltage reaches the turn-on threshold (14 V typ.) the device starts operating and
the HV generator is cut off by the Vcc_OK signal asserted high. The device is powered by
the energy stored in the Vcc capacitor until the self-supply circuit (typically an auxiliary
winding of the transformer and a steering diode) develops a voltage high enough to sustain
the operation. The residual consumption of this circuit is just the one on the 15 MΩ resistor
(≈ 10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared
to a standard startup circuit made with external dropping resistors.
At converter power-down the system loses regulation as soon as the input voltage is so low
that either peak current or maximum duty cycle limitation is tripped. Vcc then drops and
stops IC activity as it falls below the UVLO threshold (10 V typ.). The VCC_OK signal is de-
asserted as the Vcc voltage goes below a threshold VCCrest located at about 5 V. The HV
generator can now restart. However, if Vin < Vinstart, as illustrated in Figure 6, HV_EN is de-
asserted too and the HV generator is disabled. This prevents converter restart attempts and
ensures monotonic output voltage decay at power-down in systems where brownout
protection (see the relevant section) is not used.
The low restart threshold VCCrest ensures that, during short-circuits, the restart attempts of
the device have a very low repetition rate, as shown in the timing diagram of Figure 7, and
that the converter works safely with extremely low power throughput.
Vcc OFF
Vccrestart
Trep
GD t
(pin 4) < 0.03Trep
Vcc_OK
t
Icharge
t
0.85 mA
AM11483v1
1.080
1.060
1.040
VHV(normalized @ 25 C)
1.020
°
1.000
0.980
0.960
0.940
0.920
0.900
-50 -25 0 25 50 75 100 125 150
Tj ( C)
AM11484v1
Equation 2
2 ⋅ 10 3
fosc ≈
RT
(with fosc in kHz and RT in kΩ). As the device is turned on, the oscillator starts immediately;
at the end of the first oscillator cycle, the voltage on the ZCD pin being zero, the MOSFET is
turned on, therefore starting the first switching cycle right at the beginning of the second
oscillator cycle. At any switching cycle, the MOSFET is turned off as the voltage on the
current sense pin (CS, 7) hits an internal reference set by the line feedforward block, and the
transformer starts demagnetization. If this completes (so a negative-going edge appears on
the ZCD pin) after a time exceeding one oscillation period Tosc = 1/fosc from the previous
turn-on, the MOSFET is turned on again – with some delay to ensure minimum voltage at
turn-on – and the oscillator ramp is reset. If, on the other hand, the negative-going edge
appears before Tosc has elapsed, it is ignored and only the first negative-going edge after
Tosc turns on the MOSFET and synchronizes the oscillator. In this way one or more drain
ringing cycles are skipped (“valley-skipping mode”, Figure 9) and the switching frequency is
prevented from exceeding fosc.
t t t
TON TFW TV
Pin = Pin'
(limit condition) Pin = Pin'' < Pin' Pin = Pin''' < P in''
AM11485v1
Note: When the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET
is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Therefore, one or more longer switching
cycles is compensated by one or more shorter cycles and vice versa. However, this
mechanism is absolutely normal and there is no appreciable effect on the performance of
the converter or on its output voltage.
If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is
smaller than the arming threshold for some reason (e.g. a heavy damping of drain
oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used),
MOSFET turn-on cannot be triggered. This is identical to what happens at startup: at the
end of the next oscillator cycle the MOSFET is turned on, and a new switching cycle takes
place after skipping no more than one oscillator cycle.
The operation described so far does not consider the blanking time TBLANK after MOSFET
turn-off, and actually TBLANK does not come into play as long as the following condition is
met:
Equation 3
TBLANK
D ≤ 1−
Tosc
where D is the MOSFET duty cycle. If this condition is not met, there are no substantial
changes: the time during which MOSFET turn-on is inhibited is extended beyond Tosc by a
fraction of TBLANK. As a consequence, the maximum switching frequency is a little lower
than the programmed value fosc and valley-skipping mode may take place slightly earlier
than expected. However this is quite unusual: setting fosc = 150 kHz, the phenomenon can
be observed at duty cycles higher than 60%. See Section 5.11: OVP block for further
implications of TBLANK.
If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an
internal pull-up keeps the ZCD pin close to 2 V during MOSFET OFF-time to prevent noise
from false triggering the detection block. When this pull-up is active, the ZCD pin may not be
able to go below the triggering threshold, which would stop the converter. To allow auto-
restart operation, however ensuring minimum operating frequency in these conditions, the
oscillator frequency that retriggers MOSFET turn-on is that of the external oscillator divided
by 128. Additionally, to prevent malfunction at converter startup, the pull-up is disabled
during the initial soft-start (see the relevant section). However, to ensure a correct startup, at
the end of the soft-start phase the output voltage of the converter must meet the condition:
Equation 4
Ns
Vout > R Z1 I ZCD
Naux
where Ns is the turn number of the secondary winding, Naux the turn number of the
auxiliary winding and IZCD the maximum pull-up current (130 µA).
The operation described so far under different operating conditions for the converter is
illustrated in the timing diagrams of Figure 10.
If the FF option is selected the operation is exactly equal to that of a standard current-mode
PWM controller. It works at a frequency fsw = fosc; both DCM and CCM transformer
operations are possible, depending on the operating conditions (input voltage and output
load) and on the design of the power stage. The MOSFET is turned on at the beginning of
each oscillator cycle and is turned off as the voltage on the current sense pin reaches an
internal reference set by the line feedforward block. The maximum duty cycle is limited to
70% minimum. The signal on the ZCD pin in this case is used only for detecting feedback
loop failures (see Section 5.11: OVP block).
Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active)
armed trigger
GD GD GD
(pin 4) (pin 4) (pin 4)
AM11486v1
COMP
(pin 9)
20 mV
hyster.
VCOMPBM
fosc t
MODE/SC=Open
fsw
MODE/SC=VREF
t
GD
(pin 4)
Valley-skipping Mode
AM11487v1
Figure 12. Addition of an offset to the current sense lowers the burst-mode
operation threshold
Vcso = Vref R
R + Rc
Vref
10
4
L6566BH Rc
R
3 7
Rs
AM11488v1
prevent any malfunction during transients from minimum to maximum load the normal
(higher) UVLO threshold is re-established when the voltage at the COMP pin exceeds
VCOMPL and Vcc has exceeded the normal UVLO threshold (see Figure 13). The normal
UVLO threshold ensures that at full load the MOSFET is driven with a proper gate-to-source
voltage.
VCOMP
(pin 9)
Vcc
VCOMPL
5
VCOMPO
+
Vcc t
COMP
9
-
R (pin 5)
UVLO
S Q +
+
VccOFF1
V COMPL
SW VccOFF2
-
V COMPO
AM11489v1
Figure 14. Possible feedback configurations that can be used with the L6566BH
Vout
5 Vcc
L6566BH
9
L6566BH
Cs
COMP 9
Naux
COMP
TL431
Ideally, the voltage generated by the self-supply winding and the output voltage should be
given by the relation between the Naux/Ns turn ratio only. Actually, numerous non-idealities,
mainly transformer parasites, cause the actual ratio to deviate from the ideal one. Line
regulation is quite good, in the range of ± 2%, whereas load regulation is about ± 5% and
output voltage tolerance is in the range of ± 10%.
The dynamics of the pin are in the 2.5 to 5 V range. The voltage at the pin is clamped
downwards at about 2 V. If the clamp is externally overridden and the voltage on the pin is
pulled below 1.4 V, the L6566BH shuts down. This condition is latched as long as the device
is supplied. While the device is disabled, however, no energy is coming from the self-supply
circuit, therefore the voltage on the Vcc capacitor decays and crosses the UVLO threshold
after some time, which clears the latch and lets the HV generator restart. This function is
intended for an externally controlled burst-mode operation at light load with a reduced
output voltage, a technique typically used in multi-output SMPS, such as those for TVs or
monitors (see the timing diagram Figure 15).
Figure 15. Externally controlled burst-mode operation by driving the COMP pin:
timing diagram
COMP t
(pin 9)
GD t
(pin 4)
Vcc_OK
t
Icharge
t
0.85 mA
Vout t
t
AM11491v1
Equation 5
VVFF k
Vcsx = 1 − = 1 − Vin
3 3
Figure 16. Typical power capability change vs. input voltage in QR flyback
converters
2.5
k=0
2 system not
compensated
k
1.5
1 system optimally
compensated k = kopt
0.5
1 1.5 2 2.5 3 3.5 4
AM11492v1
Note: If the voltage on the pin exceeds 3 V, switching ceases but the soft-start capacitor is not
discharged. The schematic in Figure 17 shows also how the function is included in the
control loop.
With a proper selection of the external divider R1-R2, i.e. of the ratio k = R2 / (R1+R2), it is
possible to achieve the optimum compensation described by the lower curve in the diagram
of Figure 16.
The optimum value of k, kopt, which minimizes the power capability variation over the input
voltage range, is the one that provides equal power capability at the extremes of the range.
The exact calculation is complex, and non-idealities shift the real-world optimum value from
the theoretical one. It is therefore more practical to provide a first cut value, simple to
calculate, and then to fine tune experimentally.
Assuming that the system operates exactly at the boundary between DCM and CCM, and
neglecting propagation delays, the following expression for kopt can be found:
Equation 6
VR
k opt = 3 ⋅
Vin min ⋅ Vin max + (Vin min + Vin max ) ⋅ VR
Experience shows that this value is typically lower than the real one. Once the maximum
peak primary current, IPKpmax, occurring at minimum input voltage Vinmin has been found,
the value of Rs can be determined from (5):
Equation 7
k opt
1− Vin min
Rs = 3
IPKp max
Figure 17. Left: overcurrent setpoint vs. VFF voltage; right: line feedforward function block
0.8
R2 Rs
0.6 VFF CS
15 7
+
0.4 VOLTAGE PWM
COMP FEED -
FORWARD R 4
0.2 9 + Q DRIVER
OCP S GD
-
0 Vcsx Clock/ZCD
0 0.5 1 1.5 2 2.5 3 3.5 +
Hiccup DISABLE
VVFF [V] 1.5 V -
L6566BH
AM11493v1
The converter is then tested on the bench to find the output power level Poutlim where
regulation is lost (because overcurrent is being tripped) both at Vin = Vinmin and
Vin = Vinmax.
If Poutlim @ Vinmax > Poutlim @ Vinmin the system is still undercompensated and k needs to
increase; if Poutlim @ Vinmax < Poutlim @ Vinmin the system is overcompensated and k
needs to decrease. This goes on until the difference between the two values is acceptably
low. Once the true kopt is found in this way, it is possible that Poutlim can turn out slightly
different from the target; to correct this, the sense resistor Rs needs to be adjusted and the
above tuning process is repeated with the new Rs value. Typically, a satisfactory setting is
achieved in no more than a couple of iterations.
In applications where this function is not wanted, e.g. because of a narrow input voltage
range, the VFF pin can be simply grounded, directly or through a resistor, depending on
whether the user wants the OVP function to be auto-restart or latched mode (see
“Section 5.11: OVP block”). The overcurrent setpoint is then fixed at the maximum value of 1
V. If a lower setpoint is desired to reduce the power dissipation on Rs, the pin can be also
biased at a fixed voltage using a divider from VREF (pin 10).
If the FF option is selected the line feedforward function can be still used to compensate for
the total propagation delay Td of the current sense chain (internal propagation delay td(H-L)
plus the turn-off delay of the external MOSFET), which in standard current mode PWM
controllers is done by adding an offset on the current sense pin proportional to the input
voltage. In that case the divider ratio k, which is much smaller as compared to that used with
the QR option selected, can be calculated with the following equation:
Equation 8
Td
k opt = 3
Rs Lp
where Lp is the inductance of the primary winding. In case a constant maximum power
capability vs. the input voltage is not required, the VFF pin can be grounded, directly or
through a resistor (see Section 5.11: OVP block), therefore fixing the overcurrent setpoint at
1 V, or biased at a fixed voltage through a divider from VREF to obtain a lower setpoint.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to ensure
a clean operation of the IC even in a noisy environment.
The pin is internally forced to ground during UVLO, after activating any latched protection
and when the COMP pin is pulled below its low clamp voltage (see Section 5.5: PWM
control block).
Vcc OFF
Vcc restart
VCS 1.5 V t
(pin 7)
GD t
(pin 4)
OCP latch t
Vcc_OK t
AM11494v1
To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the
first time the comparator is tripped the protection circuit enters a “warning state”. If in the
next switching cycle the comparator is not tripped, a temporary disturbance is assumed and
the protection logic is reset in its idle state; if the comparator is again tripped, a real
malfunction is assumed and the L6566BH is stopped. Depending on the time relationship
between the detected event and the oscillator, the device may occasionally stop after the
third detection.
This condition is latched as long as the device is supplied. While it is disabled, however, no
energy comes from the self-supply circuit; hence the voltage on the VCC capacitor decays
and crosses the UVLO threshold after some time, which clears the latch. The internal
startup generator is still off, and the VCC voltage still needs to go below its restart voltage
before the VCC capacitor is charged again and the device restarted. Ultimately, this results in
a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the
power circuit. This special condition is illustrated in the timing diagram of Figure 18.
L6566BH
13 6
1V 1.5 V
OSC FMOD
0V RMOD 0.5 V
RT CMOD
AM11495v1
With reference to Figure 19, the capacitor CMOD is connected from FMOD to ground and is
alternately charged and discharged between 0.5 and 1.5 V by internal current generators
sourcing and sinking the same current (three times the current defined by the resistor RT on
pin OSC). Therefore, the voltage across CMOD is a symmetric triangle, whose frequency fm
is determined by CMOD. By connecting a resistor RMOD from RMOD to OSC, the current
sourced by the OSC pin is modulated according to a triangular profile at a frequency fm. If
RMOD is considerably higher than RT, as is normal, both fm and the symmetry of the triangle
is little affected.
With this arrangement it is possible to set, nearly independently, the frequency deviation
∆fsw and the modulating frequency fm, which define the modulation index:
Equation 9
∆fsw
β=
fm
which is the parameter that the amplitude of the generated side-band harmonics depends
on.
The minimum frequency fsw_min (occurring on the peak of the triangle) and the maximum
frequency fsw_max (occurring on the valley of the triangle) is symmetrically placed around the
centre value fsw, so that:
Equation 10
Then, RT is found from (5) (see Section 5.2: Zero-current detection and triggering block;
oscillator block), while RMOD and CMOD can be calculated as follows:
Equation 11
2 ⋅ 10 3 75
R MOD = C MOD =
∆fsw fm
where ∆fsw and fm (in kHz, with CMOD in nF and RMOD in kΩ) are selected by the user as to
achieve the best compromise between attenuation of peak EMI emissions and clean
converter operation.
DIS
(pin 8)
4.5V
Vccrestart
GD t
HV generator turn-on is disabled here
(pin 4)
VHVstart
AC_OK t
(pin 16)
Vth
AM11496v1
Equation 12
Css Css ⎛ V ⎞
TSS = Vcsx (VVFF ) = ⎜⎜1 − VFF ⎟⎟
I SS1 I SS1 ⎝ 3 ⎠
During the ramp (i.e. until VSS = 2 V) all the functions that monitor the voltage on the COMP
pin are disabled.
The soft-start pin is also invoked whenever the control voltage (COMP) saturates high,
which reveals an open loop condition for the feedback system. This condition very often
occurs at startup, but may be also caused by either a control loop failure or a converter
overload/short-circuit. A control loop failure results in an output overvoltage that is handled
by the OVP function of the L6566BH (see next section). In the case of QR operation, a
short-circuit causes the converter to run at a very low frequency, then with very low power
capability. This makes the self-supply system that powers the device unable to keep it
operating, so that the converter works intermittently, which is very safe. In the case of
overload, the system has a power capability lower than that at nominal load but the output
current may be quite high and can overstress the output rectifier. In the case of FF operation
the capability is almost unchanged and both short-circuit and overload conditions are more
critical to handle.
The L6566BH, regardless of the operating option selected, makes it easier to handle such
conditions: the 2 V clamp on the SS pin is removed and a second internal current generator
ISS2 = ISS1 /4 continues to charge CSS. As the voltage reaches 5 V the device is disabled, if
it is allowed to reach 2 VBE over 5 V, the device is latched off. In the former case the
resulting behavior is identical to that of short-circuit illustrated in Figure 7; in the latter case
the result is identical to that of Figure 20. See Section 5.9: Latched disable function for
additional details.
Figure 21. Soft-start pin operation under different operating conditions and settings
Vcc
(pin 5)
Vcc falls below UVLO UVLO
before latching off
SS 5V+2Vbe t
(pin 14) 5V here the IC
2V here the IC latches off
shuts down
COMP
(pin 9) t
GD
(pin 4) t
t
START-UP NORMAL TEMPORARY NORMAL OVERLOAD SHUTDOWN RESTART
OPERATION OVERLOAD OPERATION LATCHED
AUTORESTART
AM11497v1
A diode, with the anode to the SS pin and the cathode connected to the VREF pin (10), is
the simplest way to select either auto-restart mode or latch-mode behavior upon
overcurrent. If the overload disappears before the Css voltage reaches 5 V, the ISS2
generator is turned off and the voltage gradually brought back down to 2 V. Refer to
Section 6: Application examples and ideas (Table 7) for additional information.
If latch-mode behavior is desired also for converter short-circuit, make sure that the supply
voltage of the device does not fall below the UVLO threshold before activating the latch.
Figure 21 shows soft-start pin behavior under different operating conditions and with
different settings (latch-mode or auto-restart).
Note: Unlike other PWM controllers provided with a soft-start pin, in the L6566BH grounding the
SS pin does not guarantee that the gate driver is disabled.
is allowed to reach 2 Vbe over 5 V, the L6566BH is latched off. See Section 5.9: Latched
disable function for more details on IC behavior under these conditions. If the impedance
externally connected to pin 15 is so low that the 5+2 VBE threshold cannot be reached or if
some means is provided to prevent that, the device is able to restart after the Vcc has
dropped below 5 V. Refer to Section 6: Application examples and ideas (Table 7) for
additional information.
ZCD
to triggering 11
block
40kW
5V
- L6566BH
+
PWM latch 5pF COUT
R Q
OVP 2-bit Fault
Monostable STROBE counter
S Q Monostable
M2
M1 2 µs 0.5 µs
FF Counter
R Q1 reset
AM11498v1
The ZCD pin is connected to the auxiliary winding through a resistor divider RZ1, RZ2 (see
Figure 8). The divider ratio kOVP = RZ2 / (RZ1 + RZ2) is chosen equal to:
Equation 13
5 Ns
k OVP =
Vout OVP Naux
where VoutOVP is the output voltage value that is to activate the protection, Ns the turn
number of the secondary winding, and Naux the turn number of the auxiliary winding.
GD
(pin 4)
Vaux t
0
ZCD
(pin 11)
t
5V
COUT t
STROBE 2 µs 0.5 µs t
t
OVP
COUNTER t
RESET
COUNTER t
STATUS 0 0 0 0 1 1 2 2 0 0 0 1 1 2 2 3 3 4
FAULT t
t
NORMAL OPERATION TEMPORARY DISTURBANCE FEEDBACK LOOP FAILURE
AM11499v1
The value of RZ1 is such that the current sourced by the ZCD pin be within the rated
capability of the internal clamp:
Equation 14
1 Naux
R Z1 ≥ −3
Vin max
3 ⋅ 10 Np
where Vinmax is the maximum DC input voltage and Ns the turn number of the primary
winding. See Section 5.2: Zero-current detection and triggering block; oscillator block for
additional details.
To reduce sensitivity to noise and prevent the latch from being erroneously activated, firstly
the OVP comparator is active only for a small time frame (typically, 0.5 µs) starting 2 µs after
MOSFET turn-off, to reject the voltage spike associated to the positive-going edges of the
voltage across the auxiliary winding Vaux; secondly, to stop the L6566BH, the OVP
comparator must be triggered for four consecutive switching cycles. A counter, which is
reset every time the OVP comparator is not triggered in one switching cycle, is provided for
this purpose.
Figure 22 shows the internal block diagram, while the timing diagrams in Figure 23 illustrate
the operation.
Note: To use the OVP function effectively, i.e. to ensure that the OVP comparator is always
interrogated during MOSFET OFF-time, the duty cycle D under open loop conditions must
fulfill the following inequality:
Equation 15
D + TBLANK2 fsw ≤ 1
where TBLANK2 = 2 µs; this is also illustrated in the diagram of Figure 24.
Figure 24. Maximum allowed duty cycle vs. switching frequency for correct OVP
detection
0.8
0.725
0.7
0.6
Dmax 0.5
0.4
0.3
0.2
4 5 5 5 5 5 5 5
5 .10 1 .10 1.5.10 2 .10 2.5.10 3 .10 3.5.10 4 .10
fsw [Hz]
AM11500v1
Figure 25. Brownout protection: internal block diagram and timing diagram
Sensed voltage
VsenON
VsenOFF
VAC_OK t
0.485V
(pin 16)
0.45V
Sensed
voltage
t
Vcc
AC_FAIL
L6566BH 5
t
IHYS
RH 15 µA
AC_OK
- AC_FAIL
16 t
0.485V Vcc
+ (pin 5)
15 µA 0.45V
RL
t
GD
(pin 4)
t
Vout
AM11501v1
Equation 16
Vsen ON − 0.485 0.485 Vsen OFF − 0.45 0.45
= 15 ⋅ 10 − 6 + =
RH RL RH RL
Equation 17
Vsen ON − 1.078 ⋅ Vsen OFF 0.45
RH = −6
; RL = RH
15 ⋅ 10 Vsen OFF − 0.45
Figure 26. Voltage sensing techniques to implement brownout protection with the
L6566BH
AC mains (N/L) RH
AC_OK
RH 16
AC_OK RH
16 RL1
RL1
L6566BH VFF L6566BH
VFF RL 15
RL RL2
15
RL2
CF
Optional for Optionalfor
OVP settings OVP settings
a) b)
AM11502v1
It is usually convenient to use a single divider to bias both the AC_OK and the VFF pins, as
shown in Figure 26: this is possible because in all practical cases the voltage on the VFF pin
is lower than that on the AC_OK pin. Once RH and RL have been found, as suggested
above, and kopt, either calculated from (6) or (8) or experimentally found, RL is split as:
Equation 18
R L 2 = k opt ( R L + RH ) ; R L1 = R L − R L 2
Circuit a) senses the input voltage bus (across the bulk capacitor, downstream of the bridge
rectifier); in this case, for a proper operation of the brownout function, VsenON must be lower
than the peak voltage at minimum mains and VsenOFF lower than the minimum voltage on
the input bulk capacitor at minimum mains and maximum load considering, if necessary,
holdup requirements during mains missing cycles as well. Brownout level is load-
dependent. In case of latched shutdown, when the input source is removed it is necessary
to wait until the bulk capacitor voltage falls below the start voltage of the HV generator
VHVstart in order for the unit to restart, which may take up to several seconds.
Circuit b) senses the mains voltage directly, upstream of the bridge rectifier. It can be
configured either for half-wave sensing (only the line/neutral wire is sensed) or full-wave
sensing (both neutral and line are sensed); in the first case, assuming CF is large enough,
the sensed voltage is equal to 1/π the peak mains voltage, while in the second case it is
equal to 2/π the peak mains voltage. CF needs to be quite a big capacitor (in the uF) to have
small residual ripple superimposed on the DC level; as a rule-of-thumb, use a time constant
RL ·CF at least 4-5 times the maximum line cycle period in case of half-wave sensing, 2-3
times in case of full-wave sensing. Then fine tune if needed, considering also transient
conditions such as mains missing cycles. Brownout level does not depend on the load.
When the input source is removed, CF is discharged after some ten ms then this circuit is
suitable for a quick restart after a latched shutdown.
The AC_OK pin is a high impedance input connected to high value resistors, therefore it is
prone to pick-up noise, which might alter the OFF threshold when the converter is running or
lead to undesired switch-off of the device during ESD tests. It is possible to bypass the pin to
ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind.
The voltage on the pin is clamped upwards at about 3.15 V; then, if the function is not used,
the pin must be connected to Vcc through a resistor (220 to 680 kΩ).
Internal
oscillator
GD t
(pin 4)
MODE/SC t
(pin 12)
AM11503v1
The compensation is realized by connecting a programming resistor between this pin and
the current sense input (pin 7, CS). The CS pin must be connected to the sense resistor with
another resistor to make a summing node on the pin. Since no ramp is delivered during
MOSFET OFF-time (see Figure 27), no external component other than the programming
resistor is needed to ensure a clean operation at light loads.
Note: The addition of the slope compensation ramp reduces the available dynamics of the current
signal; thereby, the value of the sense resistor must be determined taking this into account.
Note also that the burst-mode threshold (in terms of power) is slightly changed.
If slope compensation is not required with FF operation, the pin is left floating.
Application information
Table 5. L6566BH light load management features
IC VCC_restart Consump. VREF VCOMP OSC
Feature Description Caused by SS FMOD
behavior (V) (Iqdis,mA) (V) (V) (V)
VZCD>VZCDth for 4
Auto Unchanged
5(6)
Doc ID 16610 Rev 2
L6566BH
Table 6. L6566BH protection (continued)
41/51
Application information
Vcc
IC IC Iq VREF VCOMP OSC
Protection Description Caused by restart SS FMOD VFF
behavior (mA) (V) (V) (V)
(V)
Externally settable
overtemperature VDIS>VOTP Latched 13.5 0.33 0 0 0 0 0 0
OTP protection
Auto
Internal shutdown Tj > 160 oC 5 0.33 0 0 0 0 0 0
restart(5)
Shutdown1 Gate driver disable VFF > Voff 5 2.5 5 Unchanged Unchanged 1 Unchanged Unchanged
restart
VCOMP <
Shutdown2 Shutdown by VCOMP low Latched 10 0.33 0 0 0 0 0 0
VCOMPOFF
Vcc < 9.4 V
Shutdown by Vcc going (VCOMP >
Adaptive below Vccoff (lowering of VCOMPL) Auto 0.18m
5V 0 0 0 0 0 0
UVLO Vccoff threshold at light Vcc < 7.2 V restart A
load) (VCOMP >
VCOMPO)
1. Use one external diode from VFF (#15) to AC_OK (#16), cathode to AC_OK.
2. Use one external diode from SS (#14) to VREF (#10), cathode to VREF.
3. If Css and the Vcc capacitor are such that Vcc falls below UVLO before latch tripping (Figure 21).
4. If Css and the Vcc capacitor are such that the latch is tripped before Vcc falls below UVLO (Figure 21).
5. When TJ < 110 oC.
6. Discharged to zero by Vcc going below UVLO.
L6566BH
Application information L6566BH
It is worth remembering that “auto-restart” means that the device works intermittently as
long as the condition that is activating the function is not removed; “Latched” means that the
device is stopped as long as the unit is connected to the input power source and the unit
must be disconnected for some time from the source in order for the device (and the unit) to
restart. Optionally, a restart can be forced by pulling the voltage of pin 16 (AC_OK) below
0.45 V.
4
PHASE RECTIFIER # 2 #
6IN
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2 K 2
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)# $
)#
,"(
#3
:# $ 2
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# 2 # # 4,
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12 OPERATION 2
!-V
4
PHASE RECTIFIER # 2 #
6IN
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6OUT
$
#!"
2
$
2 # .
&- /$ (63 6CC # 9
:# $ 2
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2 62%& -/$%3# /3# 33 #/-0 '.$
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Table 7. External circuits that determine IC behavior upon OVP and OCP
OVP latched OVP auto-restart
OCP latched
OCP auto-restart
R1 R2
MODE/SC Vref
12 10
COMP
9 BC857C
L6566BH
13
OSC
RT
AM11504v1
Vin Vin
Vcc BC857
BC847
5
Vref
8 DIS DIS
L6566BH 10
8 Rq
15 VFF L6566BH 15 VFF
>10 Rq
AM11504v1
A 1.75
A1 0.10 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.80 9.90 10.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27
h 0.25 0.50
L 0.40 1.27
k 0 8°
ccc 0.10
0016020_F
8 Order codes
9 Revision history
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