DESIGN, IMPLEMENTATION, AND EXPERIMENTAL RESULTS OF BI-

DIRECTIONAL FULL-BRIDGE DC/DC CONVERTER WITH UNIFIED SOFT-

SWITCHING SCHEME AND SOFT-STARTING CAPABLLlTY
Kunrong Wang*, Lizhi Zhu, Dayu Qu, Hardus Odendaal, Jason Lai, and Fred C. Lee
Virginia Power Electronics Center
The Bradley Department ofElectrica1 Engineering
Virginia Polytechnic Institute and State University
Blacksburg, VA 24061-01 I 1
Absrruct--The PWM control, design and iniplementation issues used primarily to limit the otherwise high transient voltage on
of the bi-directional dual full-bridge dddc converter with a the current-fed side switches which 1s intrinsic to the isolated
unified soft-switching scheme and soft-start capability, which boost type of converter; zvs for the cun-eni-fed side
was proposd in a companion paper, are presented this part switches 1s another benefit [&7] [ 161, A non-phase-shifting
of the two-paper sequel. Test results on a 5 kW prototype
converter, which is connected between a 12 V battery and a high PWM is used to seamlessly control both the start-up and
voltage bus, and paEeted for aJte-nati,re energv applications, regu1ar boost 'peration in boost Because 'Oft-
validate the serure high reliability and superior switching is realized in operations in both directions, no lossy
eficiency of the proposed converter topology. snubbering component is necessary.
I. INTRODUCTION I
~ %If 7
High power bi-directional dc/dc converters are
expected to h d wider applications in the near future in areas
such as battery chargers/discharger, line-interactive
uniiiten-uptible power systems (UPSs), alternative enerhy
systems. and hybrid electric vehicles (HEVs). The emerging
nature of these areas mainly accounts for the relative
unpopularity of this special class of dc/dc converters [8-15].
Theoretically, replacement of the diode rectifiers in
Fig. 1. Bi-directional full-bridgedc/& conlprtw with a zm@d scrft-
a unidirectional dc,dc converter with a diode and
snitching J chenic.
switch combination naturally leads to the bi-directional
power processing capability, with a few exceptions such as a In this part of the dual paper sequel, the power stage
single-ended forward converter. The issues which are design considerations are briefly discussed in section I1 with
to bidirectional dc/dc converters ,nclude power flow reference to a set of gken design specifications. Section? 111
control, smooth between bi-directiona] operation and IV are devoted to the PWM control implementation and
modes, and, jn the case of isolated topo]ogies, potential hi& issues the buck and boost modes Of operation,
transient voltage on one stde caused by the existence of the respectively. The transition between operation modes is dealt
transformer leakage inductance. with in section V. and finally the test results from the
prototype are presented in section VI.
The bi-directional dual full-bridge dc/dc converter
with a unified soft-switching scheme, which was proposed in 11. POWER STAGE CONSIDEKATIONS
the companion paper [ 131, is redrawn in Fig. 1 . It A. Design SpecYic0tion.y
incorporates an extra flyback winding coupled to the main
A set of design specifications for a prototype bi-
inductor for start-up purposes. In one direction of power
directional dc/dc converter for alternative energy applications
flow. tlie circuit is voltage-fed, or in other words, works in
will be used to illustrate the more general design
buck mode; in the other direction, it is current-fed, or works
considerations and control implementations required for bi-
in boost mode.
directional operation. The prototype converter is supposed to
A clamp branch composed Of an active be placed between a 12 V heavy duty battery and a high
switch and a capacitive energy storage e k " t is voltage bus with nominal voltage of 288 v. At the
incorporated to achieve soft-switching operation, either zero- beginning, the converter needs to power the bus up from
voltage-suitching (ZVS), or zero-current-switching (zcs), energy stored in the battery kvhile recharging the battery once
for Power Processing in both directions. In buck mode of an alternative source is available to support the high voltage
Operation, the Well-knOWn phase-shift PWM Control is used dc bus. The dc bus supplies an inverter-kiven induction
[1-51, and the Converter achieves hybrid zero-voltage and motor. When the motor runs in regeiieratioii mode, the
Zero-Cmmt sM4tching ( z v z c s ) for the voltage-fed side converter is used to absorb the regenerative energy with peak
switches with the brief activation of the auxiliary c h i p charging of the battery at as high as 5 kw. The major
switch. In boost mode of operation, the same clamp branch is specifications ofthe converter are as follows:
* The author is preseritlv nith Celestica. 530 Cblunihia Dr., Johrison City. :VY 13790, USA. E-Mail: kwang@eIestica.com.

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 Battery voltage bi' = 8 - 16 v with nominal voltage tum-on, while the leading leg devices, S7 and Si, are tumed
V,,,, = 13.5 V at room teniperature; off with hard switching, although they tum on with ZVS. For
Bus voltage V, = 255 - 425 V with nominal voltage that reason, at the selected switching frequency of 20 kHz,
V,,,, = 288 V; the current rating of the leading leg switches needs to almost
Maximum discharging power I'd = 1.6 kW; double that of the lagging leg switches if relative slow IGBTs
Nominal charging power P, = 1.6 kW with peak are used.
charging power P',, = 5 kW; The only shortcoming of the selected power stage
Bus capacitance C,, = 2 nlF. configuration is that the sofi-starting process needs to be
B. Selection of Cut-rent-FedSide and Power Switches implemented to boost the bus voltage up during the converter
start-up. The solution to this issue will be discussed later and
For the bi-directional converter in Fig. 1, in
alternative solutions are also presented in [ 151.
principle, the current-fed side and the voltage-fed side can be
exchanged, i.e. the high voltage bus side is cuiTent-fed, while C. Mugtietic Conponetits
the battery side is voltage-fed. Actually. this seems a better The turns ratio, 12, of the transformer, T,, is selected
choice because with the presence of the battery on the with mainly two considerations, i.e. the range for start-up
voltage-fed side, the boost action is secured and no start-up operation in the boost mode, and the voltage matching
problem is incurred. Nevertheless, given the wide input capability in buck mode operation in the full ranges of battery
battery and output bus voltage ranges, the turns ratio of the and output voltage variations. The higher the turns ratio, the
tr'ansfornier needs to be extremely high to boost the bus wider the start-up range. The buck mode operation places an
voltage up to its nominal value. A simple calculation reveals upper limit of n = 15. For the prototype, N = 12 was selected.
that n > 42 (low-voltage side device on-drop of 1 V is
The tums ratio for the coupled flyback choke for
assumed) is a must. Such a high turns ratio leads to a high
start-up operation can be selected to be equal to that for the
voltage of at least 700 V (assume vh = 16 V) in steady state
main transformer to get a buck-like voltage gain in the start-
seen by the devices in the high voltage current-fed bridge. To
up process [ 131.
make the situation even worse, the leakage inductance seen
from the high voltage side is non-trivial with such a high The leakage inductance for both of the magnetic
tums ratio. A.. a result, considerable over-head voltage will coinpoiients needs to be optimized to minimize the voltage
appear on the clamp capacitor. Siniulation reveals that clamp stress on the low-side bridge switches. Liberal use of
capacitor voltage will be above 900 V in the peak cliarging interleaved winding techniques can be adopted to achieve that
case. Together with the inevitable transient voltage in boost purpose.
operation, this mandates that devices with voltage ratings of D. Clump Cupucitor
at least 1200 V be used for high-voltage side switches, which
increases the insulation burden, and deteriorates the circuit With the sum of the leakage inductance of the main
performance. The discontinuous nature of the high pulsating transformer seen from the low-voltage side and the parasitic
charging current on the low-voltage side is another concern. inductance of the layout being about 100 nH, the minimum
capacitance calculated according to the criteria to the
With the above considerations, it turns out that selection of the capacitance of the clamp capacitor C , reached
placement of the current-fed bridge on the battery side, as in [13] is 160 pF. It is clear that the current flowing through
shown in Fig. 1, is more beneficial. First, the high side the clamp capacitor, C,, is pulsating, so a high quality
devices need to sustain only the bus voltage, so that 600 V capacitor with low ESR and high resonant frequency needs to
IGBTs are adequate candidates; instead, the low-voltage side be used. To facilitate the circuit layout, higher density is also
current-fed bridge switches are exposed to overhead voltage preferred. These considerations piactically narrow down the
on the clamp capacitor, and transient voltage. As a rule of selection between multilayer ceramic (MLC) and metalized
thumb. MOSFETs with a voltage rating of three times the polymer capacitors, esp. stacked film capacitors. In reality,
high line input voltage can be adequately used. For example,
MLC capacitors with total capacitance of 162 pF is used, and
in this case 55 V MOSFETs are chosen. Compared with a 35
it results in reasonable circuit waveforms and performance.
V MOSFET. the 55 V device presents less penalty because of
its lower parasitic capacitance, and related driving loss. 111. PwRl COKTROL FOR BUCK MODE
Secondly, placing the high current choke on the low-voltage OPERATION
side helps smooth out the battery current. and reduce bulky A. Control Loop Irnpletrientution
filtering components and related losses. Thirdly, the
The block diagram of PWM control generation in
continuous choke current can be easily sensed to implement
buck mode is shown in Fig. 2. In this mode, also referred to
current mode control, facilitating direct and precise control of
as charging mode, the battery gets charged, and is regulated
the battery current.
at the voltage given by the battery voltage reference signal
As indicated in [ 131, with the ZVZCS operation in V!,-re,, which is compensated with battery temperature. T,,,.
buck niode, the lagging leg devices, Sx and Sh, have almost The amplitude of the charging current reference is limited
no switching loss, thanks to the ZCS tum-off and low-loss

0-7803-5692-6/00/S 10.00 ( C) 2000 IEEE 1059

 to what corresponds to the maximum charging current in the It should be mentioned that by activating the
normal charging operation, which is 120 A in the prototype. MOSFETs on the low-voltage side in the buck mode, the
The rectified inductor current is replated, in the average converter is switched into one with active bi-directional
sense, at the level given by JrC,. power flow capability. Because the battery is always
A phase-shift PWM control chip, UC 2875, is used connected to the converter, it is prone to dumping out enerby,
as the PWM controller denoted as PWM I. The distribution and saturating the isolation transfoiiner if the output bus
logic then decides if its outputs are directed to the power voltage falls below some critical level for retaining buck
stage according to the mode control command. action, which may even result in hazardous situation. For this
reason, the synchronous rectification function is disabled
The normal charging current reference VcI is
once the bus voltage decreases to a certain level, e.g. 255V in
overridden by the regenerative charging current reference VC2
this case, or the charging current approaches zero.
once Reg-EN signal is established. Vc.2 is generated
according to the bus voltage, i.e. it ramps up with the rising IV. PUM CONTROL FOR BOOST MODE
bus voltage when it exceeds 330 V. This tends to stabilize OPERATION
the bus voltage at some reasonable level determined by the A. PU'M Logic Generution
power balance condition, and prevents overloading the bus
IL
It is obvious from the timing analysis in [I31 that the
proposed non-phase-shifting PWM for boost mode operation
mandates two phases of PWM signals, which are phase-
shifted by 180", and have a duty-cycle range from OYOto
almost 100°/o. Unfortunately, no single PWM controller can
fulfill these requirements of fmctionality.
One solution to the problem is presented in the block
diagram for PWM control generation in boost mode in Fig. 3.
In this scheme, a pair of PWM controllers, PWM 2 and PWM
3, are synchsonized with a pair of master clocks, which are
out of phase, to ensure the 180" phase difference. In reality.
such a pair of clocks are readily available from PWM I for
the buck mode operation.
IL

Current Ref.
Generation

Fig. 2. Block diagram of PM'M control iri bzrck mod<..

sc Generalion
B. Design of Tinting.for S,. a Dirttibunon
I
The rising edge of the gate drive signal for the clamp
switch, St.,in buck mode is aligned with the truiling edges of
the leading leg switches [13], so it can be generated easily Modulator2 Modulator3

from the main switch drive signals. The duration of S,. Synchx S.vncliy
should only be long enough to reset the full charging current
in the worst case so as to avoid excessive energy circulation 20 k m , inrcr:zaveu
within the converter. In the prototype design, V,, ramps up to
full charging current of 300 A at the bus voltage of V,, = 400 (UC2875) Generetion

V. So the proper duration Tvcof S, is Tsc = LJ'rp/(nK,:K,nu,.J,

where LL-is the transformer leakage inductance seen from the
high-voltage side. For the prototype design, Lk = 14.4 pH,
PCP= 5 kW, n = 12, Vo2= 400 V, V,,,,,, = 16 V, and the
calculated Ts~: = 0.83 pS. which is only a small portion of a
Fig. 3. Block diugrum of PLVM control in boost mode.
switching cycle. In reality, Tscis adjusted to about 0.8 pS. As shown in Fig. 3, S.j and S7 from PWM 1 are used
to generate a pair of synchronization pulses, synchx and
C. Issues Heluted to 5jwchronou.s Uectifkution synchy. to feed into PWM 2 and PWM 3. respectively.
Synchronous rectification is an effrcient way to Consequently, output "3, from PWM 2 and S, from PWM 3
reduce conduction loss in low-voltage applications. In the bi- are synchronized and opposite in phase. A common average
directional converter under discussion. the low-voltage current regulation loop guarantees that S, and S, have roughly
MOSFETs on the battery side is necessary anyway for the the same duty-cycle. Certainly. the output bus voltage is also
boost mode operation. So they can simply be activated with regulated at the level set by its reference K)-rL,,.
the logic defined in [ 131 to achieve synchronous rectification.

0-7803-5692-C,I00/S10.00(c) 2000 IEEE 1060

 B. Stut-t-upL o ~ ~ c programmable waiting period T,, the normal charging mode
As reached in [13], if the turns ratio for the main is resumed.
transformer and the coupled flyback choke are the same, the
converter assumes a buck-like voltage gain in the start-up
process. The composite voltage gain in boost mode, which is
defined as b<JnVl,,is shown in Fig. 4 with the effective duty-
cycle indicated.
VolnVb

d = Z(TonlTs)-l
0.4
0.2 Fig 6. Transition between djjjierenr operation modes
0 0.2 0.4 0.6 0.8 Once the regenerative chargmg condition is
d detected, the nomial charging control loop is overridden by
Fig.4. Voltage gain in boost mode. the regenerative charging current command, and only the
Perusing the timing diagrams in [ 131 reveals that the charging current is regulated.
timing for S, in the start-up and regular boost modes involves VI. PROTOTYPE IMPLEMEKTATIONAND
a swapping which happens when the duty-cycle reaches 50%, EXPERIMENTAL RESULTS
as also illustrated in Fig. 5(a) and (b). It is evident that a
feature common to the timings of S, in these two cases is that A. Mtrin Prototpe Parumeters
S, is always set by the trailing edges of the main switch A prototype bi-directional full-bridge dc/dc
pulses, while reset by the rising edges of them. This invariant converter with the proposed unified soft-switching scheme is
property greatly simplifies the logic synthesis of the timing designed and built according to the given specifications, and
signal for S, , In the prototype, the edge detection and timing the main power stage components are as follows:
synthesis for S , are realized in a programmable logic chip. SI-S,, S,: IR IR3205 55 V/8 dl MOSFET x 8:
which is also used for mode transition and system control. SS!S-: Toshiba MG100J2YS50, 600 V/100 A half-
si, 52 bridge IGBT module;
S,,ISn: Toshiba MG50J2YS50, 600 VI50 A half-
53,s4 bridge IGBT module;
Cln: United Chemi-Con 747D 123M025AA2A, 25
sc
V/ 12nxF electrolytic capacitor;
(a) In start-up process in boost mode. C,: EFD PM89C, 500 Vi10 pF polyester film
S I , s2 capacitor;
C,: AVX SM035C546KA3360, 50 VI54 pF MLC
53,s4 capacitor x 3;
T,: Philips E65-3F3 core. 2:24 tums;
SC L: Allied Signal AMCC-25 Metglas C-core, 4 pH, 4
(Off N 17
rums copper foil, flyback winding 48 turns, air gap of 1 mm
(h) In reowlar boost mode. on each side:
Fig.5 Timirgjiw S,in start-up und regtrlar h0or.t modes.. D,: Philips BYT230PIV600, 600 V/30 A rectifier
V. CONTROL OF OPERATlON MODE TRANSITION (which is over-designed).
Figure 6 illustrates the transition diagram between The converter is designed to operate at a switching
different operation modes. When the converter control is frequency of 20 kHz, which corresponds to the ripple
tumed on, it automatically enters into the default normal frequency of 40 kHz on the filtering components on both
charging state. Because the high-side bus is not powered yet, sides.
nothing happens to the power stage. B. Test Results in Buck Mode
Once the boost enable signal arrives, the converter The measured circuit waveforms during peak
immediately enters boost mode, or discharging mode in this charging operation at full power of 5 kW are shown in Fig. 7.
particular case. After the external source takes over and It can be seen that the freewheeling current on the high-
powers the bus up, the boost mode is disabled, and afier a

0-7803-5692-6/00/$10.00 (c) 2000 lEEE 1061

 voltage side is reset quickly to zero at the termination of the
on-time ,or “on” duty time, and Sh and S, are turned off with
ZCS just before the onsets of the on-time. It is noticed that
the transient secondary voltage at the rising edge of the on-
time is well controlled, thanks to the voltage clamp effect of
the clamp branch beside achieving ZVZCS. A 464A
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& :k M 5 Oops Chl 395 I4 Jan 1998 Fig.9 Meu3urr.d waveform under-boost mode operution with V,, =
I 3 4 5 52
8 V, 1, = 228 A . V,, = 288 V, PL,= I.S.i M7.
Fig. I. Measured wwefoims under buck mode operution ~ i t Vl,
h = Shown in Fig. 10 are measured efficiencies for
15 1’. 1,= 335.4, I:, = 425 ,’I I“,, = 5 kR’.
operations under different battery (input) voltages. The
Noticeable also is the deviation of the transformer efficiency improves significantly with the increase of battery
secondary current, I,, during the on-time from what is seen in voltage.
regular buck derived converters where an on-slope of the
reflected choke current is always apparent. Actually, the Efficiency
choke current is not modified. It is the extra resonant current,
which replenishes the charges on die clamp capacitor, that is
0 94
superimposed on the reflected choke current and makes the
total transformer current almost flat, especially under heavy
load. 0.92
Because of ZVZCS operation, high efficiencies are
achieved €or operation in both normal and peak charging
operation. Shown in Fig. 8 are efficiencies measured from 0.9
the prototype. Also worthy of notice is that high efficiency is
maintained across a wide range of load conditions, an
apparent benefit of synchronous rectification. 0 88
500 1,000 1,500
Efficiency Pd 0
0.95 Fig 10. A4eusured c$kiencv under boost niode operution
D. Test Results oJ’Start-up Process
0.94
The measured wavefomis during the start-up process
0.93
are shown in Fig. 11. Once the start-up command is given,
the duty-cycle from the PWM chip pair starts to increase
from zero, and the inductor current I, starts to build up.
0.92
Energy is transferred to the output through both the main
transformer and the flyback winding on the choke. As a
0.91
result. h is discontinuous because of the flyback action during
0.gLJ
0
I B I
I
1,000
’
I
2,000
’ ’I
3,000
’
I
I
4,000
’ ’I
5.000
the off time, and is also bi-directional due to the action of the
active clamp branch.
pc ON) Once the duty-cycle of the driving pulses reaches
Fig. 8. Memured &ficiency under buck mode operution. 0.5, the clamp switch drive signal changes its positioning
relative to the main switch drive signals, and the clamp
C. Test Results in Boost Abde capacitor voltage automatically adjusts to the new quasi-
The measured circuit waveforms for steady-state steady-state voltage corresponding to the new equivalent
boost operation under low battery voltage and full-load are duty-cycle in regular boost mode. This accounts for the big

0-7803-5692-6/00/S10.00(c) 2000 IEEE 1062

 resonant current pulse seen in the transformer current. After project, and Prof. Wei Chen, and Mr. Yong Li, both with
that. the flyback winding is blocked by the high output bus VPEC, for their help in the fabrication of the magnetic
voltage, and the inductor current increases quickly. After it components used in the prototype.
reaches its preset limit, the average inductor current control
loop exits from saturation, and starts to function, as is REFERENCES
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