RTu2F-1

A Quadrature Class-G Complex-Domain Doherty

Digital Power Amplifier
Shih-Chang Hung1, Si-Wook Yoo2, and Sang-Min Yoo3
Department of Electrical and Computer Engineering, Michigan State University, USA
1
hungshih@egr.msu.edu, 2 yoosiwoo@egr.msu.edu, 3 syoo@egr.msu.edu

Abstract—An efficient digital quadrature power amplifier is PA PA

presented. It shows a good system efficiency (SE) at back-off, OUT OUT
demonstrating four efficiency peaks with the combination of a
dual-supply Class-G and complex-domain Doherty (CDD) in the
IQ plane. The proposed digital quadrature transmitter in 65-nm
CMOS demonstrates 27.8-dBm peak output power (Pout) with a
Main Peak I Q
peak SE of 32.1%. For an 802.11ax 40-MHz (20-MHz) 1024-
QAM OFDM signal with 13.1-dB (12.4-dB) peak-to-average
power ratio (PAPR), it demonstrates an error vector magnitude
(EVM) of -42.0 dB (-43.3 dB) at an average Pout of 14.7 dBm (15.4
dBm). The average SE measured with a 20-MHz single-carrier
1024-QAM signal with 6.8-dB PAPR at 21-dBm Pout is 18.4%. Main Vector Sum Peak I Vector Sum Q
Keywords— Class-G power amplifier (PA), digital transmitter,
(a) (b)
quadrature transmitter, digital PA (DPA), RFDAC, switched-
capacitor PA (SCPA), Doherty, voltage-mode Doherty (VMD).
PA
Maximum OUT
I. INTRODUCTION
Pout Contour
Modern wireless communication systems require RF Q Q
transceivers with very low power consumption, high linearity,
and wide bandwidth to support the demand for a very high Main Peak
I I
data throughput for mobile subscribers. For example, I/Q I/Q
communication standards such as 802.11ax require high IQ-combined
linearity of <−40-dB error vector magnitude (EVM) and a unit vector unit vector
bandwidth of up to 160 MHz. High linearity and wide Conventional IQ-shared
bandwidth enable a very fast communication speed, while Quadrature Quadrature
increased energy efficiency gives an extended life for battery- Main I/Q Vector Sum Peak I/Q
powered devices. For improved power efficiency and output
(c)
power (Pout), many power amplifier (PA) architectures such as
Doherty [1], Class-G [2][3], power combining [3][4], polar [5], Fig. 1. PA architectures with XFMR power combining: (a) a polar PA in
and digital PA (DPA) [1]–[7] have been investigated. Doherty Doherty configuration, (b) a quadrature PA with dedicated I/Q sub-PAs, and
(c) a quadrature PA in CDD configuration.
architecture demonstrates an improved efficiency with an
additional efficiency peak through load modulation, while
Class-G provides multiple efficiency peaks at power back-off digital computer (CORDIC) and a wideband phase modulator
(PBO) with multiple supply voltages. For DPAs, an enhanced [6]. On the other hand, a quadrature transmitter has a great
Class-G technique demonstrated an improved efficiency and advantage in its wide bandwidth and simple system
linearity associated with the distributed transition of supply architecture. Fig. 1 shows simplified examples of various
voltages over multiple unit cells [2]. power combining configurations. The solid and dashed arrows
A combination of these techniques could lead to better indicate the output vectors of sub-PAs, and the dotted arrow
efficiency. For example, a polar Class-G DPA with Doherty shows the vector sum at the combined PA output. A polar PA
configuration demonstrates a high average efficiency with in Doherty configuration (Fig. 1 (a)) uses output vectors in the
multiple efficiency peaks at the PBO region. A recent work same phase in both main and peak PAs for the output
based on voltage-mode Doherty (VMD) [3] demonstrated an impedance modulation and an extra efficiency peak at the
efficient transformer (XFMR) power combining by utilizing PBO region. However, in this configuration, the phase needs
two XFMR primary windings concurrently even at the deep to be modulated externally with a phase modulator. A
PBO region. quadrature PA configuration (Fig. 1 (b)) combines two
A polar transmitter has a good output power and energy orthogonal in-phase (I) and quadrature (Q) vectors using
efficiency, but it shows a limited bandwidth and requires a XFMR, but its Pout and efficiency are degraded because each
complex system implementation such as a coordinate rotation sub-PA is dedicated to the orthogonal I and Q vectors.

978-1-7281-1701-0/19/$31.00 © 2019 IEEE 291 2019 IEEE Radio Frequency Integrated Circuits Symposium

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:27:27 UTC from IEEE Xplore. Restrictions apply.
 Main
VDD2 Main
VDD2
SCPA
VDD SCPA
VDD
Vss Vss
PA Vout PA 0.75
OUT OUT Vout
Peak
VDD2 Peak
VDD2
SCPA
VDD SCPA
VDD
Vss 0 dB PBO Vss 2.5 dB PBO

Ideal DE Ideal DE
100% 100%

PBO PBO
(dB) (dB)
12 6 2.5 0 12 6 2.5 0

Main
VDD2 Main
VDD2
SCPA
VDD SCPA
VDD
Vss Vss
PA 0.5 PA 0.25
OUT Vout OUT Vout
Peak
VDD2 Peak
VDD2
SCPA
VDD SCPA
VDD
Vss 6 dB PBO Vss 12 dB PBO

Ideal DE Ideal DE
100% 100%

PBO PBO
(dB) (dB)
12 6 2.5 0 12 6 2.5 0

Fig. 2. Operation region vs. I/Q codes for (a) CDD, (b) Class-G, and (c) the Fig. 3. Ideal DE curve for the Class-G CDD DPA for the output vector with
quadrature IQ-cell-shared Class-G CDD DPA. 45, 135, 225, or 315 angle.

II. DESIGN OF THE PROPOSED QUADRATURE IQ-CELL- SHARED power region where only the main PA operates. The Class-G
CLASS-G COMPLEX-DOMAIN DOHERTY DPA operation is also implemented for both main and peak PAs,
which adds two efficiency peaks in addition to the efficiency
A. Theory of Operation peak for Doherty operation. In Fig. 2 (b), the grey area
A quadrature IQ-cell-shared DPA [7] can generate an indicates the region of the Class-G operation with both VDD
output vector in the complex domain as in the conventional and VDD2 (=2VDD) supply voltages, and the white area
quadrature configuration without a phase modulator. The represents the area with only VDD supply voltage. The
maximum Pout and efficiency are significantly improved in combined operation with CDD and dual-supply Class-G in the
comparison to the conventional quadrature configuration (Fig. complex domain is illustrated in Fig. 2 (c). The detailed
1 (b)) because the output vector is not represented by the operation of the proposed DPA in different PBO regions is
orthogonal I and Q vectors generated by the dedicated sub- illustrated in Fig. 3. An ideal drain efficiency (DE) curve for
PAs as shown in Fig. 1(c). Proposed complex-domain Doherty the output vector with the 45, 135, 225, or 315 angle
(CDD) improves the efficiency with additional efficiency demonstrates multiple efficiency peaks at 0-dB, 2.5-dB, 6-dB,
peaks at the PBO region because the peak PA operates only and 12-dB PBO as shown in Fig. 3. The ideal DE shows an
when the main PA generates a maximum Pout. The CDD efficiency peak associated with the Doherty at 6-dB PBO and
provides a load modulation as in the conventional Doherty two additional efficiency peaks associated with the Class-G at
configuration for vector components with the same angle, 2.5-dB and 12-dB PBO. The efficiency curve also shows a
while it expresses the complete complex domain as in the smooth transition between different supply voltage domains
quadrature configuration for orthogonal vector components. and between main/peak PAs due to the continuous changes in
The proposed quadrature DPA based on IQ-cell-shared Class- supply voltages and impedance.
G switched-capacitor (SC) PA (SCPA) operates in the CDD
configuration as described in Fig. 1(c). Each main and peak B. Overall Architecture
quadrature Class-G IQ-cell-shared SCPA delivers the The proposed 12b quadrature DPA, as shown in Fig. 4,
maximum Pout at 45/135/225/315 with IQ-combined unit consists of 11b main and peak DPAs that are integrated with a
vectors [7] as shown in Fig. 1(c). The output vectors with VMD power-combining XFMR for impedance modulation in
different angles in the main and peak Class-G PAs are coupled the complex domain. It operates as a standalone transmitter
with XFMR in VMD configuration to achieve multiple and generates an RF signal from digital I/Q data without a
efficiency peaks in the complex domain. CORDIC or a phase modulator. As described in Fig. 4, a four-
Fig. 2 illustrates the operation region in the complex phase signal generator is used to generate the four IQ-
domain of the proposed DPA with CDD and dual-supply combined unit vectors in the quadrature transmitter. Each
Class-G architecture. In Fig. 2 (a), the area marked with a main and peak PA is a quadrature IQ-cell-shared Class-G
diagonal grid depicts the operation region where both main SCPA. The most significant bits of the I/Q data are assigned to
and peak PAs are turned on, and the white area shows the low- select the main and peak PAs, and the next 5 and 6 bits are

292

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:27:27 UTC from IEEE Xplore. Restrictions apply.
 Peak Power Amplifier

Main Power Amplifier

6b Binary Cells Class-G (1b)

+ Binary AUX Cell 4b Unary Cells

PN PN PN PN PN

T<15>
B<5>
B<0>

T<0>
AUX

PA
DELAY OUT
CONTROL

AUX
LOGIC B2T
Decoder
Q<5:0> 6 6 I<5:0>
I<11:6> 6
Q<11:10> 2 2 I<11:10>
Q<11:6> 6 4

4- Phase Fig. 6. EVM vs. average Pout for an 802.11ax 40-MHz (20-MHz) 1024-QAM
12
12

Signal Generator OFDM signal with 13.1-dB (12.4-dB) PAPR.

I<11:0> Q<11:0> fin < 1024-QAM OFDM fc = 2.2GHz > < 1024 QAM fc = 2.2GHz >
EVM = - 42.0dB Pout = 14.7dBm EVM = - 43.0dB Pout = 21dBm
Fig. 4. Block diagram of the quadrature IQ-cell-shared Class-G CDD DPA.

845 um
1070um

Class-G Complex VMD

(a) (c)
Main SCPA Peak SCPA
< 1024-QAM OFDM >
< fc = 2.2GHz >
EVM = - 42.0dB

Class-G CDD DPA Pout = 14.7dBm

40MHz
Fig. 5. Die photograph. 5dB/div

allocated to the unary and binary cells of each PA,

respectively.
For the linearity in the digital transmitters or DPAs, it is
important to match the unary and binary cells. For a better
matching, two sets of binary cells are allocated to main and
peak PAs even though only one set is required to represent the (b)
complete I/Q domain. In addition, multiple delay cells are Fig. 7. (a) Constellation and (b) spectrum at average Pout of 14.7 dBm (after
utilized to compensate for the unwanted delay mismatch DPD) for an 802.11ax 40-MHz 1024-QAM OFDM signal with 13.1-dB
between the main and peak PAs and between the unary and PAPR. (c) Constellation with a 20-MHz single-carrier 1024-QAM signal at
binary cells. 6.8-dB PBO (after DPD).

III. MEASUREMENT RESULTS a power combining transformer, and pads as shown in the chip
The prototype of the quadrature IQ-cell-shared Class-G micrograph (Fig. 5). The prototype chip is mounted, and wire
CDD DPA, fabricated in a 65-nm RF CMOS process, bonded on PCB.
occupies a chip area of 1.070.845 mm2 including main and Fig. 6 shows the measured EVM of the proposed
peak SCPAs, a four-phase signal generator, a LVDS receiver, quadrature DPA with an 802.11ax 40-MHz (20-MHz) 1024-

293

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:27:27 UTC from IEEE Xplore. Restrictions apply.
 Table 1. Performance comparison with the state-of-the-art
ISSCC JSSC RFIC
This work
2017 [3] 2016 [4] 2018 [7]
Polar Quadrature
Quadrature Quadrature
Architecture Class-G Class-G
Class-G Class-G
VMD CDD
Process 45 nm 65 nm 65 nm 65 nm
Supply 2.4/1.2V 2.4/1.2V 2.5/1.2V 2.55/1.25V
9b 7b 11b 12b
Resolution
(5+4) (6+1) (6+5) (1+5+6)
frequency 3.5GHz 2GHz 2.2GHz 2.2GHz
Peak power 25.3 dBm 20.5 dBm 30.1 dBm 27.8 dBm
Peak PAE 30.4% 20% 37.0% 32.1%
20-MHz 20-MHz
10-MHz LTE
Single- Single-
Modulation 32-Carrier 10-MHz
Carrier Carrier
1024 QAM 64 QAM
256 QAM 1024 QAM
Avg. power 14.8 dBm 14.5 dBm 22.5 dBm 21 dBm
Fig. 8. SE vs. Pout for continuous-wave (CW) signal.
PAPR 10.5 dB 6 dB** 7.6 dB 6.8 dB
QAM OFDM signal with a 13.1-dB (12.4-dB) PAPR at System
18.0%* 12.2% 18.3% 18.4%
efficiency
2.2GHz. The measured EVM is -42.0 dB (-43.3 dB) after
digital predistortion (DPD) at 14.7-dBm (15.4-dBm) average EVM (DPD) -40.3 dB -28.8 dB -40.3 dB -43.0 dB
Pout. The EVM floor is -42.7 dB (-43.5 dB) at an average Pout * Power consumption of PA only excluding CORDIC and phase modulator
** Estimated from the peak/average power.
of 10.3 dBm (11.1 dBm), and the PA achieves EVM of <−40
dB for a more than 10-dB (12-dB) dynamic range after DPD. multiple efficiency peaks, and the linearization techniques for
Fig. 7(a) and (b) depict the measured constellation and unary and binary cells enhance the linearity of the quadrature
spectrum for a 40-MHz 802.11ax signal at 14.7-dBm average DPA.
Pout. The system efficiency (SE) measured with a 20-MHz
single-carrier 1024-QAM signal with 6.8-dB PAPR at 21-dBm ACKNOWLEDGMENT
Pout is 18.4%. The measured constellation is depicted in Fig.
The author would like to thank Integrand Software for
7(c) and demonstrates −43.0-dB EVM. providing an electromagnetics simulation tool (EMX).
Fig. 8 shows the measured SE vs. Pout at 2.2GHz with a
continuous-wave (CW) signal. The SE of the proposed IQ- REFERENCES
cell-shared Class-G CDD DPA clearly demonstrates multiple [1] S. Hu, S. Kousai and H. Wang, "A Broadband CMOS Digital Power
efficiency peaks associated with Doherty and Class-G in Amplifier with," in IEEE ISSCC Dig. Tech. Papers, 2015.
comparison to the ideal efficiency of Class-B PA and other [2] S.-M. Yoo, J. S. Walling, O. Degani, B. Jann, R. Sadhwani, J. C.
operation modes with/without Doherty and/or Class-G Rudell, and D. J. Allstot, “A Class-G switched-capacitor RF power
amplifier,” IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 1212–1224,
operation. The maximum SE is 32.1% at 27.8-dBm Pout. Three May 2013.
additional peaks at 2.5-dB, 6-dB, and 12-dB PBO improve the [3] V. Vorapipat, C. Levy and P. Asbeck, "A Class-G Voltage-Mode
overall efficiency. The SE depicted in this figure reflects the Doherty Power Amplifier," in IEEE ISSCC Dig. Tech. Papers, 2017.
total power consumption in the complete quadrature [4] W. Yuan, V. Aparin, J. Dunworth, L. Seward, and J. S. Walling, “A
quadrature switched capacitor power amplifier,” IEEE J. Solid-State
transmitter chain. It is noted that the prototype quadrature Circuits, vol. 51, no. 5, pp. 1200–1209, May 2016.
DPA demonstrates a large digital power dissipation in logic [5] D. Chowdhury, L. Ye, E. Alon, and A. M. Niknejad, “An efficient
circuits in a 65-nm CMOS process, which degrades the mixed-signal 2.4-GHz polar power amplifier in 65-nm CMOS
efficiency at the PBO region. However, the power dissipation technology,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1796–
1809, Aug. 2011.
in digital circuits scales down significantly in the advanced [6] H. Jin, D. Kim, and B. Kim, “Efficient digital quadrature transmitter
nanometer CMOS technology, and the efficiency based on IQ cell sharing,” IEEE J. Solid-State Circuits, vol. 52, no. 5,
improvement at PBO will be more noticeable in the advanced pp. 1345–1357, May 2017.
CMOS nodes. A comparison to the state-of-the-art PAs is [7] S.-W. Yoo, S.-C. Hung and S.-M. Yoo, "A 1W Quadrature Class-G
Switched-Capacitor Power Amplifier with Merged Cell Switching and
shown in Table 1. Linearization Techniques," in IEEE Radio Frequency Integrated
Circuits (RFIC) Symp. Dig. Papers, 2018.
IV. CONCLUSION
A linear highly efficient transmitter based on a quadrature
CDD SCPA is implemented in a 65-nm CMOS. The
combination of quadrature IQ-cell-shared Class-G and CDD
techniques improves the SE at the PBO region by providing

294

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:27:27 UTC from IEEE Xplore. Restrictions apply.