Disruptive Developments

Disruptive Developments
for Advanced Die Attach

to Tackle the Challenges
of Heterogeneous Integration
Hugo Pristauz & Andreas Mayr, Besi Austria

presented by: Stefan Behler, Besi Switzerland
ECTC 2018 / San Diego

Introduction
Current Integration Architectures
Future Integration Architectures
Demand for High Capabilities
Conclusions & Take-aways

Is the End of Moore‟s Law Coming?
Many predictions of the end of Moore‟s Law

(last prediction by Gordon Moore -> 2025)
May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 3
Enhanced Capabilities Demanded

Introduction

2D-Side-by-Side Packages
Intel‟s Knights LandingTM Shinko‟s i-THOPTM laminate
• Conventional 2D Multi Chip Package architectures, typically FC-BGA,

• Either MR-FC bonding or TC-Bonding
• Interconnection of active side-by-side die is accomplished by either
(wire bonded) wires and/or substrate traces

Organic RDL Based Packages
Infineon‟s eWLB Freescale‟s RCP Deca‟s M-series Amkor‟s SWIFT
ASE‟s FOCoS
TSMC InFO
• Organic RDL based WL/PL-Fan-out packaging technology

• Interconnection of active side-by-side die is accomplished by an organic
redistribution layer (RDL)
Inorganic RDL Based Packages
Intel
2.5D silicon EMIB
interposer
package
CoWoS
Based on inorganic RDL (silicon oxide, silicon nitride)

• a) 2.5D TSV based or TSV-less silicon or glass interposer packaging
• b) embedded silicon bridges (EMIBTM)
• c) CoWoS (Chip on wafer on Substrate): 2.5D Si-interposer on substrate
3D-Stacked IC (3D-SIC)
Hybrid Memory Cube High Bandwidth Memory

(HMC) (HBM)
Stacked DRAM
(3DS)
Amkor‟s PossumTM
(F2F)
• Direct interconnected active die which are 3D arranged

• a) 3D TSV based packaging
• b) 3D Face-to-face packaging

Introduction

3D-SOCs
IMEC
3D-Roadmap
3D-SOC Study for Source: Philipp Absil,

“Overview of the 3D
OpenSPARC T2 Technology Landscape
to be 3D-integrated And Challenges”,
Semicon korea 2016:
into
Logic + Memory

2.5D Chiplet (Dielet) Platforms
DARPA‟s CHIPS Program [1]

• CHIPS = chiplet (dielet) platform
Pitch sweet spot between 2 and 10µm
• Chiplet = functional, verified, for chiplet (dielet) based HI platforms [3]
re-usable IP block,
realized in physical form [2]
Source:
[1] D.S. Green, “DARPA‟s CHIPS Program, and Making Heterogeneous Integration Common”, 3D-ASIP 2017
[2] S. Shumarayev, “Heterogeneous Platform – Innovation with Partners”, 3D ASIP 2017
[3] S. Iyer, “3D-SOCs Through Advanced Packaging”, 3D-ASIP 2016

Transfer Printing
• Example of transfer-print compatible micro devices

• Devices are undercut and anchored using MEMS-processing
technologies
• Throughput proposals beyond 300.000 components/hour
• 1.5µ @ 3σ accuracy required
Source: Kanchan Ghosal / X-Celeprint:

“Mass Transfer of Microscale Devices Using Transfer Printing, 3D ASIP Conference, 2017
Introduction

Drive for Higher Accuracy
comparison of Heterogeneous Integration architectures according

to bump pitch metrics and areal density
areal density = 1 / (bump pitch)2 placement accuracy @ 3σ ≈ (bump pitch) / 10 *)
*) center accuracy for self centering processes, like MR-FC

corner accuracy for non self centering (FO, TC, hybrid bonding)
Enhanced Capabilities Demanded
a)
present
c)
b)
future

Introduction

Advanced Gantry System
Advanced Gantry System

• Decoupled metrology
• Water cooled
Strength
• 2µ@3σ global*)
pick & place accuracy
• Roadmap: 1µ@3σ global*)
pick & place accuracy
*) „global„ means: no local fiducials!

„Van Gogh Alignment‟ Method
To achieve 200nm@3σ placement accuracy (@ 1000 UPH)
European patent
EP 1 802 192 A1
Principle
1. tool reference marks next to the die
2. upward camera determines position of die fiducial
relative to tool reference mark
3. downward camera determines position of substrate fiducial
relative to tool reference mark
4. Calculation of resulting misalignment and correction with ‚Nano Actor„
Enhanced Clean Capability
ISO-3 clean concept for Datacon 8800 platform
1. Use of ISO-3 compatible cables & vacuum hoses

2. Covering all energy chains – exhaust dirty air from inside of covers
3. Introducing horizonal, HEPA filter cleaned laminar flow
4. Loading substrate and diced wafers from FOUPs via EFEMs
Parallel Die Processing
Multi-nozzle bond head concept for Datacon 8800 platform

• Common z-axis for 4 nozzles
• Individual mini-stroke per nozzle to move nozzle into working
or standby position
Throughput Target:
• 20.000+ chips/hour
• ϕ300 or 650x550 mm
1. Sequential picking of dies

2. Concurrent (parallel) transfer of 4 dies
3. Concurrent (parallel) upward vision of 4 dies
4. Sequential bonding of dies

Introduction

Conclusions & Take Aways
• Advanced Die Attach will be in future a key technology for

Heterogeneous Integration.
• Roadmaps are proposing 40->10µ pitch for 2.5D/3D SIC, 10-2µ pitch
for dielet/chiplet 2.5D platforms, and 5->1µ pitch for 3D-SOCs.
• Hybrid bonding is believed to be the killer technology for sub micron
W2W, D2D or D2W 2.5D/3D integration architectures
• hybrid bonding is driving sub-µm placement accuracy with ultra clean
conditions (ISO3->ISO2), while cost down drives throughput beyond
20.000 UPH on GEN-3 panel level (650 x 550 mm)
• 4 disruptive developments for Advanced Die Attach
− Water cooled Advanced Gantry System based on decoupled metrology
− „Van Gogh Alignment‟ method for nanometer scale placement accuracy
− ISO-3 clean concept for 8800 advanced die attach platform
− Quattro-nozzle bond head for parallel die transfer and sequential pick/place

Thank You!

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Disruptive Developments

for Advanced Die Attach

Hugo Pristauz & Andreas Mayr, Besi Austria

ECTC 2018 / San Diego

Current Integration Architectures

Future Integration Architectures

Demand for High Capabilities

Conclusions & Take-aways

Many predictions of the end of Moore‟s Law

May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 4

Current Integration Architectures

Future Integration Architectures

Demand for High Capabilities

Conclusions & Take-aways

Intel‟s Knights LandingTM Shinko‟s i-THOPTM laminate

• Conventional 2D Multi Chip Package architectures, typically FC-BGA,

May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 6

Infineon‟s eWLB Freescale‟s RCP Deca‟s M-series Amkor‟s SWIFT

• Organic RDL based WL/PL-Fan-out packaging technology

Based on inorganic RDL (silicon oxide, silicon nitride)

Hybrid Memory Cube High Bandwidth Memory

• Direct interconnected active die which are 3D arranged

May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 9

Current Integration Architectures

Future Integration Architectures

Demand for High Capabilities

Conclusions & Take-aways

3D-SOC Study for Source: Philipp Absil,

May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 11

DARPA‟s CHIPS Program [1]

May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 12

• Example of transfer-print compatible micro devices

Source: Kanchan Ghosal / X-Celeprint:

Current Integration Architectures

Future Integration Architectures

Demand for High Capabilities

Conclusions & Take-aways

comparison of Heterogeneous Integration architectures according

areal density = 1 / (bump pitch)2 placement accuracy @ 3σ ≈ (bump pitch) / 10 *)

*) center accuracy for self centering processes, like MR-FC

May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 16

Current Integration Architectures

Future Integration Architectures

Demand for High Capabilities

Conclusions & Take-aways

Advanced Gantry System

May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 18

To achieve 200nm@3σ placement accuracy (@ 1000 UPH)

ISO-3 clean concept for Datacon 8800 platform

1. Use of ISO-3 compatible cables & vacuum hoses

Multi-nozzle bond head concept for Datacon 8800 platform

1. Sequential picking of dies

May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 21

Current Integration Architectures

Future Integration Architectures

Demand for High Capabilities

Conclusions & Take-aways

• Advanced Die Attach will be in future a key technology for

May-2018 ECTC 2018 - Disruptive Developments for Advanced Die Attach 23