SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

D Integrated Transient Voltage Suppression

D ESD Protection for Bus Terminals Exceeds: SN65LBC184D (Marked as 6LB184)
SN75LBC184D (Marked as 7LB184)
± 30 kV IEC 61000-4-2, Contact Discharge SN65LBC184P (Marked as 65LBC184)
± 15 kV IEC 61000-4-2, Air-Gap Discharge SN75LBC184P (Marked as 75LBC184)
± 15 kV EIA/JEDEC Human Body Model (TOP VIEW)
D Circuit Damage Protection of 400-W Peak R 1 8 VCC
(Typical) Per IEC 61000-4-5 RE 2 7 B
D Controlled Driver Output-Voltage Slew DE 3 6 A
Rates Allow Longer Cable Stub Lengths D 4 5 GND
D 250-kbps in Electrically Noisy
Environments
D Open-Circuit Fail-Safe Receiver Design functional logic diagram (positive logic)
D 1/4 Unit Load Allows for 128 Devices 3
DE
Connected on Bus 4
D Thermal Shutdown Protection D

D Power-Up/-Down Glitch Protection

D Each Transceiver Meets or Exceeds the
Requirements of TIA/EIA-485 (RS-485) and
ISO/IEC 8482:1993(E) Standards
D Low Disabled Supply Current 300 µA Max
D Pin Compatible With SN75176
D Applications:
− Industrial Networks
− Utility Meters
− Motor Control
2
description RE
6
1 A
The SN75LBC184 and SN65LBC184 are differ- R 7 Bus
B
ential data line transceivers in the trade-standard
footprint of the SN75176 with built-in protection
against high-energy noise transients. This feature
provides a substantial increase in reliability for
better immunity to noise transients coupled to the
V
data cable over most existing devices. Use of
these circuits provides a reliable low-cost ± VP
direct-coupled (with no isolation transformer) data
line interface without requiring any external
± 1/2 VP
components.
The SN75LBC184 and SN65LBC184 can with-
stand overvoltage transients of 400-W peak
1.2 µs t
(typical). The conventional combination wave
50 µs
called out in IEC 61000-4-5 simulates the
overvoltage transient and models a unidirectional
surge caused by overvoltages from switching and Figure 1. Surge Waveform — Combination Wave
secondary lightning transients.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

   !"#$ % &'!!($ #%  )'*+&#$ ,#$(- Copyright  2009, Texas Instruments Incorporated
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2  #++ )#!#"($(!%-

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1






 

 
 



SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

description (continued)
A biexponential function defined by separate rise and fall times for voltage and current simulates the
combination wave. The standard 1.2 µs/50 µs combination waveform is shown in Figure 1 and in the test
description in Figure 15.
The device also includes additional desirable features for party-line data buses in electrically noisy environment
applications including industrial process control. The differential-driver design incorporates slew-rate-controlled
outputs sufficient to transmit data up to 250 kbps. Slew-rate control allows longer unterminated cable runs and
longer stub lengths from the main backbone than possible with uncontrolled and faster voltage transitions. A
unique receiver design provides a fail-safe output of a high level when the inputs are left floating (open circuit).
The SN75LBC184 and SN65LBC184 receiver also includes a high input resistance equivalent to one-fourth unit
load allowing connection of up to 128 similar devices on the bus.
The SN75LBC184 is characterized for operation from 0°C to 70°C. The SN65LBC184 is characterized from
−40°C to 85°C.

schematic of inputs and outputs

VCC

A Port
Only 16 kΩ
12 µA
Nominal
72 kΩ

A or B
I/O

16 kΩ
B Port
Only
12 µA
Nominal

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265






 

 
 



SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

DRIVER FUNCTION TABLE

INPUT ENABLE OUTPUTS
D DE A B
H H H L
L H L H
X L Z Z
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)

RECEIVER FUNCTION TABLE

DIFFERENTIAL INPUTS ENABLE OUTPUT
A−B RE R
VID ≥ 0.2 V L H
−0.2 V < VID < 0.2 V L ?
VID ≤ − 0.2 V L L
X H Z
Open L H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)

AVAILABLE OPTIONS
PACKAGE
TA PLASTIC SMALL-OUTLINE† PLASTIC DUAL-IN-LINE PACKAGE
(JEDEC MS-012) (JEDEC MS-001)
0°C to 70°C SN75LBC184D SN75LBC184P
−40°C to 85°C SN65LBC184D SN65LBC184P
† Add R suffix for taped and reel.

logic symbol†
3
DE EN1
2
RE EN2

6
4 1 A
D 7
1 B

1
R 2

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3






 

 
 



SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

absolute maximum ratings over operating free−air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 15 V
Data input/output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Receiver output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Electrostatic discharge: Contact discharge (IEC61000-4-2) A, B, GND (see Note 2) . . . . . . . . . . . . . . ±30 kV
Air discharge (IEC61000-4-2) A, B, GND (see Note 2) . . . . . . . . . . . . . . ±15 kV
Human body model (see Note 3) A, B, GND (see Note 2) . . . . . . . . . . . . . . ±15 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3 kV
All terminals (Class 3A) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8 kV
All terminals (Class 3B) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 V
Electrical Fast Transient/Burst (IEC 61000−4−4) A, B, GND . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 kV
Continuous total power dissipation (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. GND and bus terminal ESD protection is beyond readily available test equipment capabilities for IEC 61000-4-2, EIA/JEDEC test
method A114-A and MIL-STD-883C method 3015. Ratings listed are limits of test equipment; device performance exceeds these
limits.
3. Tested in accordance with JEDEC Standard 22, Test Method A114-A and IEC 60749−26.
4. The driver shuts down at a junction temperature of approximately 160°C. To operate below this temperature, see the Dissipation
Rating Table.

DISSIPATION RATING TABLE

TA ≤ 25°C
25 C DERATING FACTOR TA = 70
70_C
C TA = 85
85_C
C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW
P 1150 mW 9.2 mW/°C 736 mW 598 mW

recommended operating conditions

MIN‡ TYP MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus terminal (separately or common mode), VI or VIC −7 12 V
High-level input voltage, VIH D, DE, and RE 2 V
Low-level input voltage, VIL D, DE, and RE 0.8 V
Differential input voltage, |VID| 12 V
Driver −60 mA
High-level output current, IOH
Receiver −8 mA
Driver 60
Low-level output current, IOL mA
Receiver 4
SN75LBC184 0 70 °C
Operating free-air temperature, TA
SN65LBC184 −40 85 °C
‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265






 

 
 



SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

DRIVER SECTION

electrical characteristics over recommended operating conditions (unless otherwise noted)

ALTERNATE
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
SYMBOLS
DE = RE = 5 V, No Load 12 25 mA
ICC Supply current NA DE = 0 V, RE = 5 V,
175 300 µA
No Load
IIH High-level input current (D, DE, RE) NA VI = 2.4 V 50 µA
IIL Low-level input current (D, DE, RE) NA VI = 0.4 V −50 µA
VO = −7 V −250 −120
Short-circuit output current
IOS NA VO = VCC 250 mA
(see Note 5)
VO = 12 V 250
IOZ High-impedance output current NA See Receiver II mA
VO Output voltage Voa, Vob IO = 0 0 VCC V
Peak-to-peak change in common-
VOC(PP) mode output voltage during state NA See Figures 5 and 6 0.8 V
transitions
VOC Common-mode output voltage |Vos| See Figure 4 1 3 V
Magnitude of change, common-
|∆VOC(SS)| |Vos − Vos| See Figure 5 0.1 V
mode steady-state output voltage
Magnitude of differential output IO = 0 1.5 6 V
|VOD| Vo
voltage |VA − VB| RL = 54 Ω, See Figure 4 1.5 V
Change in differential voltage mag-
∆|VOD| ||Vt| − |Vt|| RL = 54 Ω 0.1 V
nitude between logic states
† All typical values are measured with TA = 25°C and VCC = 5 V.
NOTE 5: This parameter is measured with only one output being driven at a time.

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(DH) Differential output delay time, low-to-high-level output 1.3 µs
td(DL) Differential-output delay time, high-to-low-level output 1.3 µs
tPLH Propagation delay time, low-to-high-level output 0.5 1.3 µs
RL = 54 Ω, CL = 50 pF,
tPHL Propagation delay time, high-to-low-level output 0.5 1.3 µs
See Figure 5
tsk(p) Pulse skew (| td(DH) − td(DL) |) 75 150 ns
tr Rise time, single ended 0.25 1.2 µs
tf Fall time, single ended 0.25 1.2 µs
tPZH Output enable time to high level RL = 110 Ω, See Figure 2 3.5 µs
tPZL Output enable time to low level RL = 110 Ω, See Figure 3 3.5 µs
tPHZ Output disable time from high level RL = 110 Ω, See Figure 2 2 µs
tPLZ Output disable time from low level RL = 110 Ω, See Figure 3 2 µs

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SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

RECEIVER SECTION

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
DE = RE = 0 V, No Load 3.9 mA
ICC Supply current (total package) RE = 5 V, DE = 0 V,
No Load 300 µA

VI = 12 V 250
VI = 12 V, VCC = 0 250
II Input current Other input = 0 V µA
A
VI = − 7 V −200
VI = − 7 V, VCC = 0 −200
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ± 100 µA
Vhys Input hysteresis voltage 70 mV
VIT + Positive-going input threshold voltage 200 mV
VIT− Negative-going input threshold voltage −200 mV
VOH High-level output voltage IOH = − 8 mA Figure 7 2.8 V
VOL Low-level output voltage IOL = 4 mA Figure 7 0.4 V
† All typical values are at VCC = 5 V, TA = 25°C.

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output 150 ns
CL = 50 pF, See Figure 7
tPHL Propagation delay time, high-to-low-level output 150 ns
tsk(p) Pulse skew (| tpHL − tpLH |) 50 ns
tr Rise time, single ended 20 ns
See Figure 7
tf Fall time, single ended 20 ns
tPZH Output enable time to high level 100 ns
tPZL Output enable time to low level 100 ns
See Figure 8
tPHZ Output disable time from high level 100 ns
tPLZ Output disable time from low level 100 ns

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SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

PARAMETER MEASUREMENT INFORMATION

Output 3V
S1 Input 1.5 V 1.5 V
0 or 3 V 0V
tPZH 0.5 V
CL = 50 pF RL = 110 Ω VOH
Generator (see Note B)
(see Note A) 50 Ω Output 2.3 V
tPHZ Voff ≈ 0 V

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 2. Driver tPZH and tPHZ Test Circuit and Voltage Waveforms

5V
3V
Input 1.5 V 1.5 V
RL = 110 Ω
S1 0V
Output
0 or 3 V tPZL
tPLZ
CL = 50 pF
(see Note B) 5V
Generator
50 Ω 2.3 V 0.5 V
(see Note A) Output
VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 3. Driver tPZL and tPLZ Test Circuit and Voltage Waveforms

A
27 Ω

D VOD
IO(A)
Input
27 Ω VO(A) Output
II B
VOC
IO(B)
VO(B)
CL CL

NOTES: A. Resistance values are in ohms and are 1% tolerance.

B. CL includes probe and jig capacitance.

Figure 4. Driver Test Circuit, Voltage, and Current Definitions

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SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

PARAMETER MEASUREMENT INFORMATION

3V
Input 50% 50%
0V
tPLH tPHL
∼ 3.5 V
90% 90%
VO(A) 50% 50% ∼ 2.3 V
10% 10%
∼1V
tr tf

tPHL tPLH
90% 90% ∼ 3.5 V
VO(B) 50% 50% ∼ 2.3 V
10% 10%
∼1V
tr tf

td(DH) td(DL)
∼ 2.5 V
VOD 0V
∼ −2.5 V

VOC VOC(PP)

∆VOC(SS)

Figure 5. Driver Timing, Voltage and Current Waveforms

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SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

PARAMETER MEASUREMENT INFORMATION

A
27 Ω

D VOD

27 Ω Output
B
Inputs
DE VOC

CL CL

3V
DE
0V
Inputs
3V
D
0V

Output

VOC(PP)
NOTES: A. Resistance values are in ohms and are 1% tolerance.
B. CL includes probe and jig capacitance (± 10%).

Figure 6. Driver VOC(PP) Test Circuit and Waveforms

II
A
IO
R
VID
Input VI B
Output
50 pF VO
1.5 V
RE (see Note A)

3V
Inputs 50% 50% 1.5 V
0V
tPLH tPHL
VOH
90% 90%
Output 50%
10% 10%
VOL
tr tf
NOTE A: This value includes probe and jig capacitance (± 10%).

Figure 7. Receiver tPLH and tPHL Test Circuit and Voltage Waveforms

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SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

PARAMETER MEASUREMENT INFORMATION

5V
A
0 V or 3 V 620 Ω
R

B
1.5 V
50 pF 620 Ω VO
RE (see Note A)
Input

3V
A
0V

3V 3V
Inputs RE 1.5 V
0V 0V
tPHZ tPZH tPLZ tPZL
VOH ∼ 2.5 V
Output 0.5 V 0.5 V
VO 0.5 V 0.5 V
∼ 2.5 V VOL

NOTE A: This value includes probe and jig capacitance (± 10%).

Figure 8. Receiver tPZL, tPLZ, tPZH, and tPHZ Test Circuit and Voltage Waveforms

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265






 

 
 



SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

TYPICAL CHARACTERISTICS

DRIVER DIFFERENTIAL OUTPUT VOLTAGE DRIVER PROPAGATION DELAY TIME

vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
3.0
800
VOD − Driver Differential Output Voltage − V

RL = 54 Ω

tpd − Driver Propagation Delay Time − ns

780

2.5 VCC = 5.25 V

760
VCC = 5 V tPHL
740

2.0
720
VCC = 4.75 V
tPLH
700

1.5
680

660

1.0
−40 −20 0 20 40 60 80 640
−40 −20 0 20 40 60 80
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
Figure 9 Figure 10

DRIVER TRANSITION TIME

DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
OUTPUT CURRENT
900
4.5

4.0
800
VOD − Differential Output Voltage − V
tt − Driver Transition Time − ns

tf 3.5

700
3.0
VCC = 5.5 V
tr
2.5
600
2.0 VCC = 4.5 V

500
1.5
VCC = 5 V
1.0
400
0.5

300
−40 −20 0 20 40 60 80 0.0
0 10 20 30 40 50 60 70 80 90 100
TA − Free-Air Temperature − °C
IO − Output Current − mA

Figure 11 Figure 12

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SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

TYPICAL CHARACTERISTICS

RECEIVER INPUT CURRENT

vs
INPUT VOLTAGE
0.25

0.20
I(I) − Receiver Input Current − mA

0.15

0.10

0.05
A, B (VCC = 0 V)
−0.00

−0.05
B (VCC = 5 V)
−0.10 A (VCC = 5 V)

−0.15

−0.20
−10 −5 0 5 10 15
VI − Input Voltage − V

Figure 13

APPLICATION INFORMATION
SN65LBC184 SN65LBC184
SN75LBC184 SN75LBC184

RT RT

Up to 128
Transceivers

NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.

Figure 14. Typical Application Circuit

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SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

APPLICATION INFORMATION

’LBC184 test description

The ’LBC184 is tested against the IEC 61000−4−5 recommended transient identified as the combination wave.
The combination wave provides a 1.2-/50-µs open-circuit voltage waveform and a 8-/20-µs short-circuit current
waveform shown in Figure 15. The testing is performed with a combination/hybrid pulse generator with an
effective output impedance of 2 Ω. The setup for the overvoltage stress is shown in Figure 16 with all testing
performed with power applied to the ’LBC184 circuit.
NOTE
High voltage transient testing is done on a sampling basis.

VI(peak) II(peak)

0.5 VP 0.5 IP

1.2 µs t 8 µs t
50 µs 20 µs

Figure 15. Short-Circuit Current Waveforms

The ’LBC184 is tested and evaluated for both maximum (single pulse) as well as life test (multiple pulse)
capabilities. The ’LBC184 is evaluated against transients of both positive and negative polarity and all testing
is performed with the worst-case transient polarity. Transient pulses are applied to the bus pins (A & B) across
ground as shown in Figure 16.

IP
High 41.9 Ω 7
Key Tech
B/A
1.2/50 − 8/20
SN75LBC184
Combination Pulse
5
Generator 3Ω VP GND
Impedance Matching
Low and Wave Shaping
2-Ω Internal Impedance

Figure 16. Overvoltage-Stress Test Circuit

An example waveform as seen by the ’LBC184 is shown in Figure 17. The bottom trace is current, the middle
trace shows the clamping voltage of the device and the top trace is power as calculated from the voltage and
current waveforms. This example shows a peak clamping voltage of 33.6 V and peak current of 16 A, thus
yielding an absorbed peak power of 538 W.
NOTE
A circuit reset may be required to ensure normal data communications following a transient noise
pulse of greater than 250 W peak.

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SLLS236G − OCTOBER 1996 − REVISED FEBRUARY 2009

APPLICATION INFORMATION

Power 538 W Peak

0

33.6 V Peak,
Clamping Voltage VI(peak)

16 A Peak,
Input Current
II(peak)

0 20 40 60 80 100 120 140 160 180

t − 20 µs/Div

Figure 17. Typical Surge Waveform Measured At Terminals 5 and 7

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 9-Sep-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN65LBC184D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 6LB184

& no Sb/Br)
SN65LBC184DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 6LB184
& no Sb/Br)
SN65LBC184DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 6LB184
& no Sb/Br)
SN65LBC184DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 6LB184
& no Sb/Br)
SN65LBC184P ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 65LBC184
(RoHS)
SN65LBC184PE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 65LBC184
(RoHS)
SN75LBC184D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7LB184
& no Sb/Br)
SN75LBC184DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7LB184
& no Sb/Br)
SN75LBC184DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7LB184
& no Sb/Br)
SN75LBC184DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7LB184
& no Sb/Br)
SN75LBC184P ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 75LBC184
(RoHS)
SN75LBC184PE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 75LBC184
(RoHS)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 9-Sep-2014

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LBC184DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75LBC184DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2009

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC184DR SOIC D 8 2500 340.5 338.1 20.6
SN75LBC184DR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
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