R. Ludwig and G.

Bogdanov
“RF Circuit Design: Theory and Applications”
2nd edition

Figures for Chapter 4

i1 i1 i2
+ + +
v1 One-port v1 Two-port v2
– Network – Network –
Port 1 Port 2

i1 i2
Port 1 + v v2 + Port 2
– 1 –
i3 i4
Port 3
+ v
Multiport v4 + Port 4
– 3 –
Network
iN – 1 iN
Port N – 1 + vN – 1 vN + Port N
– –

Figure 4-1 Basic voltage and current definitions for single- and multiport network.
 i1 i2
+ ZB +
port 1 v1 ZA ZC v2 port 2

– –

Figure 4-2 Pi-network as a two-port network.

 iC iB rBC iC
C B C
+ +
iB
B vBE iB' rBE i B' rCE vCE

– –
E E E E

Figure 4-3 Common-emitter low-frequency, small-signal transistor model.

 i1 i1' i2' i2
+ +
+ +
v1' [Z'] v2'
– –
v1 v2
i1" i2"
+ +
v1" [Z"] v2"
– – – –

Figure 4-4 Series connection of two two-port networks.

 i1 i'1 Z'A Z'B i'2 i2 i1 i'1 Z'A Z'B i'2 i2
+ + + + + +
+ +
v'1 Z'C v'2 v'1 Z'C v'2
– – – –
v1 Z"B v2 v1 i1" Z"B i"2 v2

+ i"1 i"2 + + +
v"1 Z"C v"2 v"1 Z"C v"2

– – – –
– – – –
1:1
(a) (b)

Figure 4-5 (a) Short circuit in series connection. (b) Transformer to avoid short
circuit.
 i1 i1' i2' i2
+ + + +
v1' [h'] v2'
– –
v1 i"1 v2
i2"
+ +
v" [h"] v2"
– –1 – –

Figure 4-6 Connection of two-port networks suitable for hybrid representation.

 i1 i2

+ + + +
v1' v2'
_ _

v1 N1:1 v2

+ +
v"1 v"2
_ _ _ _
N2:1

Figure 4-7 Series connection of two hybrid networks.

 i1' i2'
+ + + +
v1' [Y'] v2'
– –
port 1 i"1 i"2 port 2
+ +
v"1 [Y" ] v"2
– – – –

Figure 4-8 Parallel connection of two two-port networks.

 i1' i"2
+ i2' i"1 +
v1' + + v"2
v2' v1"
– – – –

i1' i2' i"1 i"2

+ +
A' B' + + A" B"
port 1 v1' v2' v1" v"2 port 2
C' D' – – C" D"
– –

Figure 4-9 Cascading two networks.

 Table 4-1 ABCD-parameters of several two-port circuits
Circuit ABCD Parameters

i1 Z i2 A=1 B=Z

+ +
v1 v2 C=0 D=1
– –

i1 i2 A=1 B=0

+ +
v1 Y v2
– – C=Y D=1

ZA ZA ZB
i1 ZA ZB i2 A = 1 + ------ B = Z A + Z B + -------------
ZC ZC
+ +
v1 ZC v2 1 ZB
C = ------ D = 1 + ------
– – ZC ZC

YB 1
i1 YC i2 A = 1 + ------ B = ------
YC YC
+ +
v1 YA YB v2 YA YB YA
– – C = Y A + Y B + ------------- D = 1 + ------
YC YC

l A = cos ( β l ) B = jZ 0 sin ( β l )
i1 i2
+ +
v1 Z0 , v2 j sin ( β l )
C = -------------------- D = cos ( β l )
– – Z0

i1 N:1 i2 A= N B= 0
+ +
v1 v2 1
– – C= 0 D = ----
N
 Table 4-2 Conversion between different network representations

[Z] [Y] [h] [ABCD]

Z 22 Z 12 ∆Z Z 12 Z 11 ∆Z
-------
- – -------- -------- -------
- -------- --------
[Z] Z 11 Z 12 ∆Z ∆Z Z 22 Z 22 Z 21 Z 21
Z 21 Z 22 Z 21 Z 11 Z 21 1 1 Z 22
– -------- -------- – -------- -------- -------- -------
-
∆Z ∆Z Z 22 Z 22 Z 21 Z 21

Y 22 Y 12 1 Y 12 Y 22 1
-------
- – -------- -------- – -------
- – -------- – --------
[Y] ∆Y ∆Y Y 11 Y 12 Y 11 Y 11 Y 21 Y 21
Y 21 Y 11 Y 21 Y 22 Y 21 ∆Y ∆Y Y 11
– -------- -------
- -------
- -------- – -------- – --------
∆Y ∆Y Y 11 Y 11 Y 21 Y 21

∆h h 12 1 h 12 ∆h h 11
------- ------
- ------- – ------
- – ------- – -------
[h] h 22 h 22 h 11 h 11 h 11 h 12 h 21 h 21
h 21 1 h 21 ∆h h 21 h 22 h 22 1
– ------- ------- ------- ------- – ------- – -------
h 22 h 22 h 11 h 11 h 21 h 21
A- ∆
--- ABCD-
------------------- ---- – ∆
D ABCD-
------------------- B- ∆
--- ABCD-
-------------------
[ABCD] C C B B D D A B
1-
--- D
---- 1 A 1 C- C D
– --- --- – ---- ---
C C B B D D
 R

L L

l, Z 0 C

Figure 4-10 Microwave amplifier circuit diagram.

 Feedback loop
R
Output matching
network
Input matching L L
network

l, Z 0 C

Figure 4-11 Subnetwork representation of the microwave amplifier.

 IB CBC IC
B C

rBE CBE rCE

gmvBE

E E

Figure 4-12 High-frequency hybrid transistor model.

 40
R = 10 kΩ
R = 1 kΩ
Small-signal current gain, dB 35 R = 500 Ω
R = 300 Ω
30 R = 200 Ω

25

20

15

10 4
10 105 106 107 108 109
Frequency, Hz

Figure 4-13 Small-signal current gain of the amplifier versus frequency for different values
of the feedback resistor.
 a1 I1 I2 a2
+ +
V1 [S] V2
– –
b1 b2

Figure 4-14 Convention used to define S-parameters for a two-port network.

 Z0 a1
a2 = 0

VG1 Z0 [S] Z0 ZL

b1 b2

Figure 4-15 Measurement of S11 and S21 by matching the line impedance Z0 at port 2
through a corresponding load impedance ZL = Z0.
 a1 = 0 a2 Z0

ZG Z0 [S] Z0 VG2

b1 b2

Figure 4-16 Measurement of S22 and S12 by matching the line impedance Z0 at port 1
through a corresponding input impedance ZG = Z0.
 R1 R2

Port 1 R3 Port 2

(a)

R1 R2 R1 R2

R3 50 Ω 50 Ω R3

Port 1 Port 2 Port 1 Port 2

(b) (c)

Figure 4-17 S-parameter computation for a T-network.

(a) circuit diagram; (b) circuit for S11 and S21 measurements; (c) circuit for S12 and S22 mea-
surements.
 a 1A a 2A b1B a 2B

port 1 [T]A [T]B port 2

b 1A b 2A a 1B b 2B

Figure 4-18 Cascading of two networks A and B.

 a
a
Z0 ZL ΓL
b

b
(a) (b)

Figure 4-19 Terminated transmission line segment with incident and reflected power wave
description. (a) Conventional form, and (b) Signal flow form.
 a b

(a) Source node a, which launches wave. (b) Sink node b, which receives wave.

a Γ b

(c) Branch connecting source and sink.

Figure 4-20 Generic source node (a), receiver node (b), and the associated
branch connection (c).
 ZG b' a
bS b' 1 a bS b' a
IG ZL
VG Z0 ΓS ΓL ΓS ΓL

a' b a' 1 b b

(a) (b) (c)

Figure 4-21 Terminated transmission line with source. (a) conventional form,
(b) signal flow form, and (c) simplified signal flow form.
 1/(1 – ΓLΓS)
bS b' bS b'

ΓLΓS

Figure 4-22 A self-loop that collapses to a single branch.

 Table 4-3 Signal flowgraph building blocks.

Description Graphical Representation

a a
Nodal Assignment
Z0 Z0
b b

a a
Branch
Z0 ZL ΓL
b b

Series Connection
Sba Scb Sba Scb
a b c a c

S1
Parallel Connection S1 + S2
a S2 b a b

S2 S2 S3
Splitting b S3 b
of Branches c
a c a
S1 S1 S3

b 1/(1 – Γ)
a c a c
Self-Loop

Γ
 bS Γ a1 a2 ΓL
ZS S

VS Z0 [S] Z0 ZL

b1 b2
(a) Circuit representation

bS 1 1 a1 S21 b2 1

ΓS S11 S22 ΓL

1 b1 S12 a2 1
(b) Signal flowgraph

Figure 4-23 Sourced and terminated two-port network.

 bS 1 1 a1 S21 b2 bS 1 1 a1 S21 b2

ΓS S11 S22 ΓL ΓS S11 ΓL

S22 ΓL
b1 S12 a2 b1 S12 a2

Step 1

S21
bS 1 1 a1 1 – S22ΓL b2 bS 1 1 a1
S12S21
ΓS S11 ΓL ΓS S11 Γ
1 – S22ΓL L
b1 S12 a2 b1

Step 2

bS 1 1 a1 bS 1 1 a1
S12S21 S12S21
ΓS S11 Γ ΓS S11 + Γ
1 – S22ΓL L 1 – S22ΓL L
b1 b1

Step 3

bS 1 1 a1 bS 1 1 a1
S12S21
ΓS S11 + Γ
1 – S22ΓL L

b1 S12S21
S11 + Γ Γ
1 – S22ΓL L S

Step 4

bS 1 1 a1
bS a1

1
S12S21 S S
S11 + Γ Γ 1 – S11 + 12 21 ΓL ΓS
1 – S22ΓL L S 1 – S22ΓL

Step 5
Figure 4-24 Step-by-step simplification to determine the ratio a 1 /b S .
 bS a1 a2
ZS

Z 01 Two-port Z 02
VS ZL = Z 02
network
b1 b2
–l1 0 z1 z2 0 –l2

Figure 4-25 Two-port network with finite-length transmission line segments.

 a1 a2
ZG

VG Z0 ZL

b1 b2
l

Figure 4-26 Transmission line attached to a voltage source and terminated by a load im-
pedance.
 bS 1 a1 e–j l
a2

ΓG ΓL
b1 e–j l b2

Figure 4-27 Signal flowgraph diagram for transmission line system in Figure 26.
 RF R A B

50 Ω

Bias tee DUT Bias tee

Dual Directional 50 Ω
Dual Directional
Coupler Coupler
DC Power Supply

Figure 4-28 Measurement system for S 11 and S 21 parameters using a network

analyzer.
 a1 a2

Error Error
DUT
box A box B
b1 b2
Measurement Measurement
Reference Plane Desired Reference Plane Reference Plane
(a)

EX

RFin E21 R S21 F ET B

E22 S11
E11 S22 ER
A
E12 S12
(b)

Figure 4-29 (a) Block diagram of the setup for measurement of S-parameters of a two-port
network; (b) signal flowgraph of the measurement test setup.
 EX

RFin E21 R 1 F ET B
E11 E22 ER
A
E12 1
(a) Through
EX

RFin E21 R F ET B
E11 E22 Γ
ER
A Γ
E12
(b) Reflect
EX

RFin E21 R e–j l F ET B

E11 E22 ER
A
E12 e–j l
(c) Line

Figure 4-30 Signal flow graphs of TRL method: (a) Through, (b) Reflect, (c) Line
configurations.
 R2

Z 01 R1 R3 Z 02

Figure 4-31 Resistive Pi-network attenuator with arbitrary characteristic impedances at the
ports.
Figure 4-32 Pi-network of a 3 dB attenuator with SMA connectors.
Figure 4-33 S11 and S21 recording of the attenuator.