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    System-on-Chip Design: Zynq Soc

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    Bilal Haider Tanoli
    SOX E LECTURE

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    © All Rights Reserved
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    System-on-Chip Design: Zynq Soc

    Uploaded by

    Bilal Haider Tanoli
    81 views17 pages
    SOX E LECTURE

    Original Title

    ZYNQ_SOC

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    © © All Rights Reserved

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    SOX E LECTURE

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    81 views17 pages

    System-on-Chip Design: Zynq Soc

    Uploaded by

    Bilal Haider Tanoli
    SOX E LECTURE

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 17

    System-on-Chip Design

    ZYNQ SoC

    Dr. Syed Azhar Ali Zaidi


    Assistant Professor
    azhar.ali@uettaxila.edu.pk

    https://sites.google.com/site/cmsdrsyedazhar/home/s
    oc-design

    1
    Embedded System
    • A specialized computing system that is optimized
    to carry out a single, or very few, dedicated
    functions.

    Applications of Embedded Systems 2


    General Embedded System Architecture
    Off-load specific tasks to
    Programmed to perform enhance performance
    specific tasks of
    embedded system.
    Co-Processor

    Accelerator

    3
    ZYNQ SoC

    4
    ZYNQ 7000 Family Features

    5
    ZYNQ 7000 Family Features

    6
    Neon 128b SIMD and Floating •Single or Dual processors (upto 1 GHz)
    Point coprocessors per MPcore •Asymmetric and Symmetric MP
    •ARM v7 ISA, Thumb-2, Jazelle
    •Private Timers and Watchdog timers

    •Dual Ported
    •Accessible by CPU, PL
    and central Interconnect
    •Not Cacheable

    Multiplexed I/O
    peripherals
    64-bit AXI Accelerator
    coherency port. Cache-
    coherent access from PL to
    ARM caches.

    7
    Application Processing Unit (APU)

    8
    SIMD (Single Instruction Multiple Data) Processing in the NEON
    Media Processing Engine (MPE)

    • Operates on multiple sets of input vectors upon which same operation is performed
    simultaneously.
    • Cater well for applications like image/video processing, FIR Filters, FFTs etc.
    • NEON supports a variety of data types including signed and unsigned integers, single
    precision floating point, and half-precision floating point.

    Source: The Zynq Book 9


    Snoop Control Unit
    • Maintains coherency between the processors
    L1 data caches and the shared L2 cache.
    • Initiates and control access to level 2 cache,
    arbitrating requests between processor cores.
    • The SCU additionally manages transactions
    that take place between the PS and PL via the
    Accelerator Coherency Port (ACP).

    10
    Cache-Coherence Problem

    Many Protocols are used to solve the cache-coherence problem such as


    1. Write-through
    2. Write-back
    3. Snoopy Protocol
    etc. 11
    Programmable Logic

    12
    PS-PL Interfaces
    • PS and PL are tightly integrated through a set of AXI interconnects
    and interfaces and some other interconnections in particular EMIO.
    • AXI stands for Advanced eXtensible Interface, and the current
    version is AXI4, which is part of the ARM AMBA® 3.0 open standard
    for On-chip communication.
    • AXI4 has three flavors, each of which represents a different bus
    protocol.
    – AXI4 — For memory-mapped links, and providing the highest
    performance: an address is supplied followed by a data burst transfer
    of up to 256 data words (or ‘data beats’).
    – AXI4-Lite — A simplified link supporting only one data transfer per
    connection (no bursts). AXI4-Lite is also memory-mapped: in this case
    an address and single data word are transferred.
    – AXI4-Stream — For high-speed streaming data, supporting burst
    transfers of unrestricted size. There is no address mechanism; this bus
    type is best suited to direct data flow between source and destination
    (non memory mapped).

    13
    PS-PL Interfaces
    • Nine AXI interfaces between the PL and PS.

    Interface —
    A point-to-
    Interconnect – Switches that manages and point
    direct traffic between the AXI interfaces connection
    for passing
    data,
    addresses,
    and hand-
    shaking
    signals
    between
    master and
    slave clients
    within the
    system.

    14
    PS-PL Interfaces

    15
    EMIO Interface
    • Several connections from the PS can be routed through the
    PL to external interfaces, and this is referred to as Extended
    MIO, or EMIO. Provide additional 64 inputs and 64 outputs
    with output enables.
    • Another option is to use EMIO to interface the PS with a
    peripheral block in the PL.

    16
    17

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