Electrostatic Discharge Analysis of Multi Layer

Ceramic Capacitors
Cyrous Rostamzadeh #1, Hamidreza Dadgostar*2, Flavio Canavero $3
#
Robert Bosch LLC, Plymouth. MI, USA
1
Cyrous.Rostamzadeh@us.bosch.com
*
University of Stuttgart, Germany
2
hdadgostar@stud.uni-stuttgart.de
$
Politecnico di Torino, Italy
3
flavio.canavero@polito.it

Abstract—A rigorous analysis of Electrostatic Discharge current-limiting resistor (or ambient air condition) to transfer
susceptibility of Multi Layer Ceramic (MLC) capacitors is the energy pulse to the target.
carried out. The impact of ESD stress applied at the connector In order to meet the module level ESD tests, various
pins of an electronic control module, protected by utilizing 0603 methods and techniques on printed circuit boards have been
package MLC capacitors is evaluated. Effectiveness of MLC
implemented and investigated. One effective technique is to
capacitors for protection of integrated circuits cannot be
underestimated, nor should it be assumed as an effective ESD add discrete noise-decoupling components or filters into
robust solution. Meanwhile, any degradation, or physical damage complex CMOS based IC products to decouple, bypass, or
to MLC capacitors should not be ignored. This analysis absorb the electrical transient voltage (energy) under system-
concentrates on the permanent physical degradation to the ESD level ESD test [3]. Various types of noise filter networks can
capacitors employed for the protection of active components for be employed to improve system-level ESD stress tests,
an automotive control module. However, this does not limit its including capacitor filters, ferrite bead, transient voltage
scope to specialized automotive applications. In general, the samesuppressor (TVS), metal oxide varistor (MOV), and 2nd order
principles are applicable to all electronic products employing
LC filter or 3rd order π-section filters.
MLC capacitors as per ESD protection and filter mechanism.
Multi layer ceramic capacitors (MLCC) are employed as an
I. INTRODUCTION ESD bypass mechanism at the connector pins of electronic
control modules. An automotive control module may require
Electrostatic Discharge (ESD) is one of the most important
the use of a single high-density connector with pin density in
reliability problems in the electronic circuit industry.
excess of 200. In a typical application, a connector may
Typically in integrated circuits (ICs) industry, one-third to
present the designer with a matrix of 4 x 50 (4 rows of 50 pins
one-half of all field failures (customer returns) are due to ESD.
at each row) in a tightly congested PCB real estate. To
As ESD damage has become more prevalent in newer
accommodate for the ESD protection for each and every I/O
technologies due to the higher susceptibility of smaller circuit
pin at the connector of a highly congested PCB real estate,
components, there has been a corresponding increase in
design engineers recommend the use of 0603 style MLC
efforts to understand ESD failures through modeling and
capacitors. In most applications, MLC capacitors used for
analysis. Manufacturers of integrated circuits provide ESD
ESD protection are rated for 100 V stress level. However,
test information. However, the ESD data on IC level standards,
post-ESD characteristics of MLCC’s are often ignored or
Human Body Model (HBM), Charged Device Model (CDM),
misunderstood. In reality, MLCC’s exposed to ESD stress
Machine Model (MM) and latch up to the system level testing
exhibit dramatic shift in characteristic impedance behavior.
is often confusing.
Careful examination of MLCC’s reveals a permanent
Design of robust ESD circuits remains challenging because
structural damage resulting in excessive low frequency
ESD failure mechanisms become more acute as critical circuit
leakage. Post-ESD behavior of MLCC’s results in a functional
dimensions continue to shrink. Circuit board designers are
deviation for a control module and it is fundamentally unsafe
further constrained by the ability to design highly congested
to use the product for its intended application. It is suggested
printed circuit boards (PCB) and meet ESD requirements.
that the low profile 0603 capacitors should not be used for
HBM provides much insight into device behavior during an
ESD protection as reported in this paper. Alternative solutions
ESD event [1,2] .
can be met by the use of low profile transient voltage
An ESD event is the transfer of energy between two bodies
suppressors (TVS) or fast metal oxide varistors (MOV).
at different electrostatic potentials, either through contact or
However, 0805 style MLCC’s with high value capacitance
via an ionized ambient discharge (a spark). This transfer has
(larger than 47 nF) provide a good solution and are safe to be
been modeled in various standard circuit models for testing
used as an ESD bypass element.
the compliance of device targets. The models typically use a
MLCC’s as a protective device or mechanism should
capacitor charged to a given voltage, and then some form of
consider the voltage, peak power and energy as the key

978-1-4244-4267-6/09/$25.00 ©2009 IEEE 35

components of an ESD threat. It is thus necessary to fully determined to exceed the maximum value of 39 nF available
characterize the amplitude and timing of ESD components. in 0603 package.
Therefore, protection structure should reduce the voltage,
peak power, and energy threats by shunting the stress currents
away from fragile portions of the microcontrollers and other
ICs [9].
To solve ESD problems, MLC capacitors employed as ESD
bypass or filter component on PCB’s, must shunt the ESD
transient current safely to ground. It is important that MLC
capacitor employed as bypass component, absorbs the ESD
voltage and current safely and protects the device under test
with no degradation. In addition, MLC capacitor must remain
within its parametric tolerance if it could be considered as a
reliable protection mechanism.

II. MLC CAPACITOR AS AN AUTOMOTIVE ESD PROTECTION

DEVICE
Multi layer ceramic capacitors are designed for use where a
small physical size with comparatively large electrical
capacitance and high insulation resistance is required. General
purpose 0603 (1.6 mm x 0.5 mm) class II, type X7R (-55oC ->
Fig. 2. ‘Standard’ vs. ‘ESD-Enhanced’ 0603 MLCC
+125 oC) is a popular choice for automotive electronic control
module design. Therefore it is a common practice to apply
X7R MLCC’s as ESD protection component at all I/O pins. Figure 2 illustrates two different styles of MLCC
technology with respect to the design of conductive plates.
Style A capacitor is a standard MLCC design where the
capacitor plates from opposing terminals do not overlap in the
upper and lower edges as indicated. A closer examination of
post-ESD damage consistently revealed a physical structural
damage (crack, bubble or void) in the upper or lower terminal
region of MLCC. Capacitor manufacturers recognize the over-
voltage stress concern and have provided an ESD-enhanced
MLCC product. Fig. 2 demonstrates the style B as an ESD
enhanced design. A close examination of Figure 2 (Style B)
geometry indicates a design topology, where manufacturers
have overlapped the opposing electrodes in the four corners of
MLCC terminals. Figure 3 illustrates a horizontal grind of an
‘ESD-enhanced’ MLCC on a scale of X 100 magnifications.

Fig. 1. Standard 0603 MLCC (X 100 Magnification)

Figure 1 illustrates a horizontal grind of 0603 MLCC

(magnification X 100) with plates spaced at 21 μm apart for a
10 nF, X7R type II capacitor. It is important to note that in the
indicated region, capacitor plates from opposing edge
terminals do not overlap. A higher value capacitor is designed
with increased number of plates. This will result in a narrow
dielectric thickness, a possible drawback for high voltage
transients. At the present time (January 2009), capacitor
values for a type II X7R 0603 (100 V) range between 180 pF
to a maximum value of 39 nF. However, the capacitor value
range for the same technology, but larger physical size (0805),
varies from 220 pF to a maximum value of 120 nF. This can
be an important factor if ESD protection capacitor value is Fig. 3. ESD-Enhanced’ 0603 MLCC

36
Comparison with Fig. 1 demonstrates the differences in plate However, simple RLC model fails to provide additional
geometry design. As indicated, plates from opposing technical insight required for the analysis of MLCC’s exposed
electrodes do overlap in four corners of MLCC terminals. to ESD pulse. The modified model presented in Fig. 4 has
Printed circuit board designers with fundamental EMC additional elements to describe the behavior of MLC
trainings, are required to ascertain the optimum mounting capacitors exposed to ESD stress. In fact, the model described
strategy for ESD capacitors. EMC engineers verify a “Y- here is an accurate electrical description, necessary to account
Connection” topology for all of the ESD capacitors, at every for the various physical attributes found within a capacitor.
I/O pin of the connector. MLCC must be placed in close 1. L1 is the series parasitic inductance associated with
proximity of the I/O pin (< 1 cm) with a short trace (< 1 cm) plate connections.
to the PCB return plane. In this manner, added PCB parasitic 2. L2 is the equivalent series inductance. It is also
trace inductance and its degradation effect on the effectiveness known as LESL.
of ESD bypass capacitor is minimized. The general concern is 3. R1 is the equivalent series resistance (also known as
to limit the added inductance due to PCB mounting RESR) and represents the actual Ohmic resistance of
inductance, and thus provide a low-impedance path for ESD the plates. This value is typically very low. It causes
current flow to return plane. a power loss of I2R1. Its contribution to the total
Another limitation would be to use the lowest value dissipation factor is D1 = ωR1C1.
capacitor available, where it is most effective at higher 4. C1 is the nominal capacitance.
frequencies. ESD would result into an RF current with a 5. R2 is the dielectric loss: A parallel resistance arising
bandwidth in excess of 330 MHz. The choice between a 1 nF from two phenomena; molecular polarization and
and 680 pF would easily be reduced to the latter one. However, interfacial polarization (dielectric absorption).
ESD HBM consists of a 150 pF capacitance, thus a higher Dielectric loss is a complex phenomenon that can
value MLC capacitor is preferred. A voltage divider network change with frequency in most any manner that is not
is established by the combination of HBM capacitor and abrupt. Its contribution to the total dissipation factor
MLCC. The voltage developed across a larger value MLCC, can be approximated by D3 ~ 1/(ωR2C2).
would lower the voltage developed across an integrated circuit: 6. C2 is the parallel dielectric absorption capacitor.
C HBM 7. R3 is the leakage resistance, or insulation resistance:
VMLCC = VESD (1) A parallel resistance due to leakage current in the
C HBM + C MLCC capacitor. This value is typically very high. It causes
Therefore for VMLCC << VESD, it is required that CMLCC >> a power loss of V2/R3. Its contribution to the total
CHBM. dissipation factor is D2 = 1/(ωR3C1).
The impedance characteristics of type II (package 0603,
III. MLC CAPACITOR ELECTRICAL MODEL X7R MLC) capacitors for a 680 pF and 10 nF are illustrated in
Several electrical models of capacitors are available in text books and Fig. 5.
RF publications used by EMC/RF community to describe the
electrical behavior of MLC capacitors. A simple series RLC network
is commonly used to provide an accurate behavior for most
applications.

Fig. 5. Pre-ESD Impedance Characteristics

ESD is a high frequency pulse with a rise time of less

than 1 ns, resulting in spectral content in excess of 330 MHz.
Hence, the choice of ESD capacitor is reduced to a smaller
value MLCC, as seen in Fig. 5. Closer examination of Fig. 5
reveals a lower impedance for a 680 pF (1.71 Ω, at f = 330
MHz) compared with a 10 nF (3.97 Ω, at f = 330 MHz).
Another consideration may be due to capacitive loading of
certain I/O signals, i.e., CAN bus, where a limited capacitance
Fig. 4. Improved Electrical Model of MLC Capacitors can be added to the communication bus.

37
 TABLE I accumulated on the 150 pF discharge network capacitor
MLCC 0603 CAPACITOR MODEL COMPONENTS (charged to 25 kV) would amount to 3.75 μC. ESD is a high-
frequency, high-voltage and high current event that can
NOMINAL 680 pF 10 nF deposit 46.875 mJ of energy in the protection device in a
VALUES @ 1 kHz relatively short time duration.
L1 49 pH 91 pH HBM provides much insight into device behavior during
an ESD event. Although the HBM stress is characterized by a
L2 931 pH 1.730 nH
certain charging voltage, VHBM, the 2 kΩ series resistor of the
C1 680 pF 10 nF circuit is usually much larger than the impedance of the device
C2 4.10 pF 4.10 pF under test, so we think of HBM tester as current sources, with
the peak HBM current equal to 12.5 A. (VHBM = 25 kV, air-
R1 5.15 kΩ 0.329 kΩ discharge).
R2 753.73 Ω 34.57 Ω
12
R3 1.471 x 10 Ω 0.1 x 1012 Ω V. PRE-ESD AND POST-ESD MEASUREMENTS
In order to evaluate the impact of ESD stress on 0603
MLCC’s two different types of tests were performed. Since a
The requirements of a lower value ESD capacitor as in the populated electronic control module is the intention of a
previous paragraph, may suggest the use of the lowest value realistic test, it is important to evaluate the impact of ESD
MLCC available in industry. In addition, there is a third factor stress as per OEM ESD test techniques. In an another method,
that is outlined in Table I, R3 (insulation resistance) that may an 0603 MLCC network was prepared as shown in Fig. 6 with
add additional incentive for the use of the lowest value two short wires (< 1 cm) at each end. Terminal one was
MLCC. However, further insight is required to distinguish the connected to a ground plane where an ESD gun return wire
apparent easy choice. would normally be connected. ESD discharge tip was slowly
In Table I, all nominal and parasitic elements for both approached to the floating terminal until an air discharge was
capacitors are listed as per MLCC supplier A. achieved.
It is important to note that the insulation resistor, R3, is an Pre-ESD and post-ESD characteristics of the 0603
order of magnitude higher in value for smaller value capacitor capacitor were recorded using an Agilent 4294A impedance
(Table I). As more plates are stacked up to accommodate for analyzer (40 Hz – 110 MHz) with the help of Agilent 16034G
higher value capacitance in the same physical volume of 0603 test fixture.
style package, the dielectric thickness is reduced by a factor of Capacitors were removed from test PCB, or ESD network
14.7. Therefore, as a consequence of thinner dielectric wires and mounted inside the 16034G test fixture for
material between the capacitor plates, the insulation resistor impedance characterization.
for higher value capacitor is reduced by the same ratio, It was decided to apply ESD pulse to a fully populated
(capacitor ratio: 10 nF / 680 pF = 14.7, insulation resistor automotive electronic control module as designed with
ratio: 0.1 x 1012 Ω / 14.7 x 1012 Ω = 1/147). It is clear that a rigorous EMC guidelines. OEM ESD requirements provides
higher value capacitor will sustain a dielectric breakdown in guidelines [6,7,8] for remote I/O access ESD stress tests. A
lower ESD voltages. It appears by this argument, for ESD HBM model with discharge network as outlined in section IV
applications, only to consider lower-value capacitors with was calibrated and ESD voltage levels from +/- 4 kV up to +/-
higher insulation resistance in order to protect for dielectric 25 kV was applied in successive order. After each discharge,
breakdown, i.e., 680 pF vs. 10 nF. Further investigation was MLCC was removed and analyzed on impedance analyzer as
required to answer the accuracy of aforementioned statement. per previous method.
If a smaller capacitor presents a higher insulation resistance
as shown above, it is important to examine the behavior of the
insulation resistance after ESD tests. It is important to
evaluate the impact of ESD stress on 680 pF and 10 nF
capacitors by characteristic impedance of post-ESD capacitors
for further insight.

IV. HUMAN BODY ESD TEST

ESD tests for automotive applications are derived and
based on HBM specified by original equipment manufacturers
(OEM) [4,5,6,7,8].
A typical HBM discharge network consists of a 150 pF
capacitor with a 2 kΩ resistor. HBM capacitor can be charged
up to 25 kV for air-discharge test. The static charge
Fig. 6. ESD air-discharge to 0603 MLCC

38
 In Fig. 10, a modified electrical model represented as per
Figure 7 illustrates the impact of ESD pulse at +/-15kV Fig. 4, was used for post-ESD effects for both capacitors. In
level for 680 pF capacitor. Figure 8 illustrates the impact of electrical model per Table I, R3 was replaced with a 500 Ω
ESD pulse at +/-15kV level for 10 nF capacitor. resistor in place of a nominal pre-ESD value provided by
MLCC manufactures in Table I (14.7 x 1012 Ω).

Fig. 7. Measured Pre-ESD and Post-ESD ( MLCC 680 pF) Fig. 10. Simulated Post-ESD Impedance Characteristics, R3 = 500 Ω

It is important to note that 10 nF capacitor has developed a

severe leakage from 40 Hz up to 20 kHz, and for 680 pF, the
upper frequency is approximately 200 kHz. The impedance of
both capacitors registers a 500 Ω resistive value in the
aforementioned frequency range. It is thus concluded that
ESD has caused a non-recoverable, permanent damage to
MLCC’s. Post-ESD behavior suggests physical damage to
dielectric material due to metallization of capacitor plates. In
reference to Fig. 4, it is clear that R3 has shifted from its pre-
ESD nominal value as per Table I (for 680 pF, R3 = 1.471 x
1012 Ω or for a 10 nF, R3 = 0.1 x 1012 Ω to an extremely low
value of 500 Ω.
In order to understand why 680 pF MLCC has a 500 Ω
Fig. 8. Measured Pre-ESD and Post-ESD ( MLCC 10 nF) leakage up to 200 kHz, whereas 10 nF shows the ill-effect
only up to 20 kHz can be explained as follows: the circuit of
Fig. 4 simplifies to the parallel of C1 and R3, at low
frequencies, and the knee of the impedance curve appears at a
frequency f ~ 1/2πR3C1. For post-ESD, the 680 pF MLCC, is
dominated by R3 from DC to ~ 300 kHz, whereas, R3
contributes only up to 20 kHz for the 10 nF capacitor.

Fig. 9. Dielectric damage for Post-ESD MLCC

Fig. 11. Measured Post-ESD for 4.7 nF 0805 Capacitor

Post-ESD capacitor dielectric damage is illustrated in Fig.
9 (horizontal grind) on a magnification scale of 100.

39
 It is clear that smaller size MLCC will suffer extreme However, I/O pin ESD capacitors in the range of 1 nF to
leakage to much higher frequency range. It is recommended to 100 nF are often utilized as an input RF filter at the connector
use higher value MLCC’s in contradiction to previous pins. The ESD capacitors provide a bypass element for the
recommendations. induced RF currents on the module harness due to impinging
As an extension to the exposure of 0603 MLC capacitors to electromagnetic fields. Low value TVS capacitance is
ESD stress, additional ESD tests were performed on modules insufficient to provide the required filter across the 1 MHz –
populated with larger footprints 0805 MLC capacitors. Figure 200 MHz frequency bandwidth. It is recommended to use a
11 illustrates the impact of +/- 25 kV HBM ESD stress on a TVS in parallel with a 0603 capacitor (10 nF – 39 nF rated for
4.7 nF capacitor. It is clear that a 4.7nF, 0805 capacitor would 50 V) where permissible.
fail the ESD requirements. However, extending the capacitor
size (value) to 10 nF in an 0805 package, results in ESD
compliance.
REFERENCES
[1] Y. Fukuda, et al., “ESD Protection Network Evaluation by
VI. CONCLUSION HBM and CDM (Charge packaged Method)”, EOS/ESD
This study is an examination of the physical damage to the Symposium Proceedings, pp. 193 – 199, 1986
[2] Warren Boxleitner, Peter Richman, Geoff Well,
0603 MLC capacitors exposed to ESD transients. It is shown
“Characterizing the Stress applied to ICs by different ESD
that permanent damage to dielectric material is resulted for Testers”, EOS/ESD Symposium Proceedings, 1990.
ESD voltages in excess of 15 kV. The use of 0603 MLC [3] Ming-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih, “On-Chip
capacitors for I/O connector pins, as an ESD bypass Transient Detection Circuit for System-Level ESD Protection
mechanism, is not recommended and should be avoided. in CMOS Integrated Circuits to Meet Electromagnetic
However, in larger footprints, 0805 MLCC’s will meet the Compatibility Regulation”, IEEE Transactions on
ESD stress for 25 kV requirements, provided that capacitor Electromagnetic Compatibility, February 2008, Vol. 50, No. 1
size exceeds 10 nF, and rated for 100 V applications. pp. 13 – 21
Throughout this article, it was stressed that lower value [4] ISO10605:2008 Road Vehicles Test Method for Electrical
Disturbances from Electrostatic Discharge.
MLCC’s are preferred with respect to their impedance
[5] IEC61000-4-2, “Electromagnetic Compatibility (EMC) – part
behavior at higher frequencies. It is clear that one cannot 4-2: Testing and Measurement Techniques – Electrostatic
utilize lower values MLCC at will, such as 680 pF due to Discharge Immunity Test”, EN 61000-4-2:1995, Amendment
dielectric degradation, as illustrated in Fig. 7 and Fig. 9. 1:1998, Amendment 2:200
Higher value capacitors exhibit self-resonance phenomena at [6] Ford Motor Company (ES-XW7T-1A278-AC, October 2003).
lower frequencies. Therefore it is also recommended not to [7] General Motors Corporation (GMW3097 Rev. 5, May 2006).
exceed the MLCC value indiscriminately. A preferred ESD [8] Chrysler Corporation (DC-11224 and DC-11225, May 2007).
bypass solution would use a low capacitance transient voltage [9] Warren Boxleitner, “ESD Stress on PCB Mounted ICs Caused
suppressor (TVS, CTVS < 100 pF) or a fast metal oxide varistor by Charged Boards and Personnel”, EOS/ESD Symposium
Proceedings, 1990.
(MOV).

40