Yamaha HTR5790 AV Receiver - Service Manual PDF
Yamaha HTR5790 AV Receiver - Service Manual PDF
Yamaha HTR5790 AV Receiver - Service Manual PDF
IMPORTANT NOTICE
This manual has been provided for the use of authorized YAMAHA Retailers and their service personnel.
It has been assumed that basic service procedures inherent to the industry, and more specifically YAMAHA Products, are already
known and understood by the users, and have therefore not been restated.
WARNING: Failure to follow appropriate service and safety procedures when servicing this product may result in personal
injury, destruction of expensive components, and failure of the product to perform as specified. For these reasons,
we advise all YAMAHA product owners that any service required should be performed by an authorized
YAMAHA Retailer or the appointed service representative.
IMPORTANT: The presentation or sale of this manual to any individual or firm does not constitute authorization, certification or
recognition of any applicable technical capabilities, or establish a principle-agent relationship of any form.
The data provided is believed to be accurate and applicable to the unit(s) indicated on the cover. The research, engineering, and
service departments of YAMAHA are continually striving to improve YAMAHA products. Modifications are, therefore, inevitable
and specifications are subject to change without notice or obligation to retrofit. Should any discrepancy appear to exist, please
contact the distributor's Service Division.
WARNING: Static discharges can destroy expensive components. Discharge any static electricity your body may have
accumulated by grounding yourself to the ground buss in the unit (heavy gauge black wires connect to this buss).
IMPORTANT: Turn the unit OFF during disassembly and part replacement. Recheck all work before you apply power to the unit.
■ CONTENTS
TO SERVICE PERSONNEL .......................................... 2 DISPLAY DATA ........................................................... 34
FRONT PANEL .............................................................. 3 IC DATA ................................................................. 35~41
REMOTE CONTROL PANEL ........................................ 3 BLOCK DIAGRAM ................................................. 42~43
REAR PANELS .............................................................. 4 PRINTED CIRCUIT BOARD .................................. 44~60
SPECIFICATIONS ...................................................... 5~7 PIN CONNECTION DIAGRAM .............................. 61~62
INTERNAL VIEW ........................................................... 8 SCHEMATIC DIAGRAM ........................................ 63~71
DISASSEMBLY PROCEDURES ............................. 9~12 PARTS LIST ........................................................... 73~90
UPDATING FIRMWARE .............................................. 13 REMOTE CONTROL .............................................. 91~92
SELF DIAGNOSIS FUNCTION (DIAG) ................. 14~32 Parts List for Carbon Resistors ................................ 93
AMP ADJUSTMENT .................................................... 33
HTR-5790
100890
P.O.Box 1, Hamamatsu, Japan
HTR-5790
“CAUTION”
“F1, F2: FOR CONTINUED PROTECTION AGAINST RISK OF FIRE, REPLACE ONLY WITH SAME TYPE 10A,
125V FUSE.”
CAUTION
F1, F2: REPLACE WITH SAME TYPE 10A, 125V FUSE.
ATTENTION
F1, F2: UTILISER UN FUSIBLE DE RECHANGE DE MEME TYPE DE 10A, 125V.
DO NOT PLACE SOLDER, ELECTRICAL/ELECTRONIC OR PLASTIC COMPONENTS IN YOUR MOUTH FOR ANY REA-
SON WHATSOEVER!
Avoid prolonged, unprotected contact between solder and your skin! When soldering, do not inhale solder fumes or expose
eyes to solder/flux vapor!
If you come in contact with solder or components located inside the enclosure of this product, wash your hands before
handling food.
2
HTR-5790
■ FRONT PANEL
HTR-5790
3
HTR-5790
■ REAR PANELS
U, C models
A model
HTR-5790
4
HTR-5790
■ SPECIFICATIONS
■ Audio Section ■ Video Section * Specifications are subject to change without notice due to product • DIMENSIONS
improvements.
(7/8")
Minimum RMS Output Power (Power Amp. Section) Video Signal Type
22
(20 Hz to 20 kHz, 0.04% THD, 8 ohms) U, C models ......................................................................... NTSC U .......... U.S.A. model C ...... Canadian model
FRONT L/R .......................................................... 110 W + 110 W A model ................................................................................... PAL A .......... Australian model
CENTER .............................................................................. 110 W Composite Video Signal Level
SURROUND L/R .................................................. 110 W + 110 W ............................................................................ 1 Vp-p / 75 ohms
SURROUND BACK L/R ........................................ 110 W + 110 W S-Video Signal Level
Y ......................................................................... 1 Vp-p / 75 ohms
Maximum Power C .................................................................. 0.286 Vp-p / 75 ohms
(EIAJ, 1kHz, 10% THD, 8 ohms) Component Video Signal Level Manufactured under license from Dolby Laboratories.
FRONT L/R .......................................................... 165 W + 165 W Y ......................................................................... 1 Vp-p / 75 ohms “Dolby”, “Pro Logic”, “Surround EX”, and the double-D symbol are
(3/4")
(1kHz 100w / 8ohms, Multi CH IN) Tuning Range
18
U, C models ..................................................... 87.5 to 107.9 MHz
PHONO (MM) ................................................. 3.5 mV / 47 k-ohms
A model ........................................................ 87.50 to 108.00 MHz
CD, etc. ......................................................... 200 mV / 47 k-ohms
50dB Quieting Sensitivity (IHF) THX and the THX logo are registered trademarks of THX Ltd.
MULTI CH INPUT
(1kHz, 100% Mod.) Surround EX is a jointly developed technology of THX and Dolby
150 (5-7/8")
171 (6-3/4")
FRONT L/R, CENTER, SURROUND L/R, SUB WOOFER
Mono .................................................................. 2.0 µV (17.3 dBf) Laboratories, Inc. and is a trademark of Dolby Laboratories, Inc. All
.................................................................. 200 mV / 47 k-ohms
Stereo .................................................................. 25 µV (39.2 dBf) rights reserved. Used under authorization.
Maximum Input Signal Level Usable Sensitivity (IHF)
PHONO (MM) (1 kHz, 0.1% THD) ....................... 100 mV or more Mono .................................................................. 1.0 µV (11.2 dBf)
CD, etc. (1 kHz, 0.5% THD) .................................... 2.4 V or more Selectivity
Output Level / Output Impedance at 400 kHz ............................................................................ 70 dB
Signal to Noise Ratio (IHF) 435 (17-1/8")
(13/16")
21
REC OUT ..................................................... 200 mV / 1.2 k-ohms Mono .................................................................................... 76 dB
PRE OUT (FRONT L/R, CENTER, SURROUND L/R, SURROUND Stereo .................................................................................. 70 dB
BACK L/R) .......................................................... 1.0 V / 500 ohms Harmonic Distortion Unit : mm (inch)
SUB WOOFER(20Hz) ........................................ 2.0 V / 500 ohms (1 kHz)
ZONE 2 OUT .................................................... 1.0 V / 1.2 k-ohms Mono ..................................................................................... 0.2 %
ZONE 3 OUT ................................................ 200 mV / 1.2 k-ohms Stereo .................................................................................... 0.3 % • The variable range of the parameter (Min/Max/Step)
Frequency Response Stereo Separation Parameter name Pro Logic Pro Logic II Pro Logic II Neo:6 2ch DD/dts/AAC 6.1/ES Unit
CD, etc. to FRONT L/R (10 Hz to 100 kHz) ............... +0 / -3.0 dB 1 kHz .................................................................................... 42 dB
Frequency Response Movie/Game Music
RIAA Equalization Deviation 20 Hz to 15 kHz .......................................................... +0.5 / -2 dB DSP LEVEL - - - - -6/3/1 -6/3/1 -6/3/1 dB
20 Hz to 20 kHz, PHONO (MM) ..................................... 0±0.5 dB Antenna Input
(P.) INIT. DLY - - - - 1/99/1 1/99/1 1/99/1 ms
Headphone Jack Rated Output / Impedance ...................................................................... 75 ohms unbalanced
(P.) ROOM SIZE - - - - 0.1/2.0/0.1 0.1/2.0/0.1 0.1/2.0/0.1 -
CD, etc. (1 kHz, 40 mV, 8 ohms) ................... 150 mV / 100 ohms
■ AM Section (P.) LIVENESS - - - - 0/10/1 0/10/1 0/10/1 -
Total Harmonic Distortion (20 Hz to 20 kHz)
PHONO (MM) to REC OUT (1V) ............................ 0.02 % or less Tuning Range S. DELAY 10/25/1 10/25/1 0/15/1 0/30/1 0/49/1 0/49/1 0/49/1 ms
CD, etc. (STEREO) to FRONT L/R SP OUT (60W, 8 ohms) ... 0.04 % or less U, C models ....................................................... 530 to 1,710 kHz S. INIT. DLY - - - - - 1/49/1 1/49/1 ms
A model .............................................................. 531 to 1,611 kHz
Signal to Noise Ratio (IHF-A Network) Usable Sensitivity S. ROOM. SIZE - - - - 0.1/2.0/0.1 0.1/2.0/0.1 0.1/2.0/0.1 -
PHONO (MM) (Input shorted) to SP OUT (5mV) ........................................................................................ 300 µV/m S. LIVENESS - - - - 0/10/1 0/10/1 0/10/1 -
U, C models ............................................................ 86 dB or more Antenna
A model ................................................................... 81 dB or more SB. INT.DLY - - - - - - 1/49/1 ms
................................................................................. Loop Antenna
CD, etc. (Input shorted, STEREO) to SP OUT SB. ROOM, SIZE - - - - - - 0.1/2.0/0.1 -
(250mV) .............................................................. 100 dB or more ■ General SB. LIVENESS - - - - - - 0/10/1 -
Residual Noise (IHF-A Network) Power Supply REV. TIME - - - - 1.0/5.0/0.1 1.0/5.0/0.1 1.0/5.0/0.1 s
FRONT L/R SP OUT .............................................. 150 µV or less U, C models ........................................................ AC 120 V, 60 Hz REV. DELAY - - - - 0/250/1 0/250/1 0/250/1 ms
Channel Separation (STEREO) A model ............................................................... AC 240 V, 50 Hz
Power Consumption REV. LEVEL - - - - 0/100/1 0/100/1 0/100/1 %
PHONO (Input shorted, 1 kHz/10 kHz) ......... 60 dB or more / 55 dB or more U, C models ......................................................... 500 W / 630 VA Panorama - OFF OFF/ON - - - - -
CD, etc. (Input 5.1 k-ohms shorted, 1 kHz/10 kHz) A model ............................................................................... 500 W
...................................................... 60 dB or more / 45 dB or more Dimension - 0 (STD) -3/+3/1 - - - - -
Standby Power Consumption (Reference Data)
Tone Control Characteristics .................................................................................. 0.5 W or less C Width - 0 0/7/1 - - - - -
BASS AC Outlets C Image - - - 0/0.5/0.1 - - - -
Boost/Cut ............................................................ ±6 dB (50 Hz) 2 switched outlets
U, C models ......................... 100 W max. total / 0.8 A max. total DIALG. LIFT - - - - 0/5/1 0/5/1 0/5/1 -
Turnover Frequency ...................................................... 350 Hz
1 switched outlet PLⅡ/PLⅡx - PLⅡ/PLⅡx PLⅡ/PLⅡx - - - - -
TREBLE
A model .................................................................... 100 W max.
Boost/Cut .......................................................... ±6 dB (20 kHz)
Dimensions
Turnover Frequency ..................................................... 3.5 kHz
........................ 435 x 171 x 421 mm (17-1/8" x 6-3/4" x 16-9/16")
Filter Characteristics Weight
FRONT, CENTER, SURROUND, SURROUND BACK SP Small ....................................................................... 15 kg (33 lbs. 1 oz.) 7ch Stereo Parameter Unit
(H.P.F.) Finish
CT. LEVEL 0/100/1 %
................... fc=40/60/80/90/100/110/120/160/200Hz / 12 dB oct. .................................................................. Black color, Silver color
SUBWOOFER (L.P.F.) Accessories / 付属品 SL. LEVEL 0/100/1 %
................... fc=40/60/80/90/100/110/120/160/200Hz / 24 dB oct. Remote Control x 1, Batteries (Manganese Dry) x 4, Power Cable SR. LEVEL 0/100/1 %
(U, C models) x 1, Indoor FM Antenna x 1, AM Loop Antenna x 1,
Optimizer Microphone x1, Speaker Terminal Wrench x 1 SB. LEVEL 0/100/1 %
RL. LEVEL 0/100/1 %
RR. LEVEL 0/100/1 %
5
6
• Set Menu Table
Main category Sub-category No. Main Menu Sub Menu Initial Value Setting Ranges
HTR-5790
7
HTR-5790
HTR-5790
■ INTERNAL VIEW
8
HTR-5790
■ DISASSEMBLY PROCEDURES
(Remove parts in the order as numbered.)
Disconnect the power cable from the AC outlet.
3
1
2
Top Cover
Fig. 1
CB509
CB505
CB512
CB25 CB861
HTR-5790
CB863 CB862
Fig. 2
9
HTR-5790
Fig. 3
DSP P.C.B.
5 Support
6 6
7
6
6
Bracket
Fig. 4
8 0
HTR-5790
0 Fig. 5
10
HTR-5790
Tuner
CONVERSION P.C.B.
DSP P.C.B.
Fig. 6 HTR-5790
11
HTR-5790
A
A
B
Duct
Fan
CB32
Cover
C E
D
F
F
Amp Unit
Cloth
HTR-5790
Fig. 8
12
HTR-5790
■ UPDATING FIRMWARE
After replacing the IC512 on the FUNCTION P.C.B. with 2. After executing the firmware loading program, select
the service part (X4678A00), update the firmware the program type and port settings as follows:
according to the following procedure.
Program Type Select
Equipment required
Program Type: Vx400
• PC with RS-232C serial port (OS: Windows98/Me/
2000/XP) COM > SETTING Menu
• Firmware loading program (Z9Boot.exe)
Port Setting Dialog
• Firmware (Vx400_xxxxx.mot)
Port: Select proper port #
• RS-232C cross cable "D-Sub 9-pin Female".
Bits per second: 9600
Pin No.2 RxD Pin No.2 RxD
Data bits: 8
Pin No.3 TxD Pin No.3 TxD
Parity: None
Pin No.5 GND Pin No.5 GND
Stop bits: 1
Pin No.7 RTS Pin No.7 RTS
Flow control: Hardware
Pin No.8 CTS Pin No.8 CTS
• RS-232C Conversion Adapter (Part #: AAX24910)
3. Turn on the power to the unit.
Preparations
Download the firmware loading program and firmware 4. To connect the line, click the CONNECT button or the
from the specified download sources to the same directory COM menu, then click the CONNECT.
of the PC for updating the firmware.
COM > CONNECT Menu
Firmware updating procedure
1. With the power turned off, connect the RS-232C cross After connecting, the "Connected" message is
cable and RS-232C conversion adapter between the displayed in the status bar.
PC and the RS-232C port of the unit as shown below.
5. Click the File Change button and then select the file to
be loaded.
To start loading, click the Program Macro button.
<CAUTION>
Never disconnect the power cable of the unit while
loading the firmware, or the flash ROM data may be
destroyed.
13
HTR-5790
14
HTR-5790
15
HTR-5790
CAUTION!
Using this product with the protection function disabled
may cause damage to itself. Use special care for this point When there is a history of protection function:
when using this mode.
When there is a history of protection
function due to excess current Version (1 alphabet)
• Canceling DIAG
[1] Before canceling DIAG, execute setting for PRESET of
DIAG menu No.11 (Memory initialization inhibited or
Memory initialized).
* In order to keep the user memory stored, be sure to Cause: An excessive current flowed through the power
select PRESET INHIBIT (Memory initialization amplifier.
inhibited). Any protection history will remain in Turning on the power without correcting the abnormality
memory. will cause the protection function to work immediately and
[2] Turn off the power by pressing the “STANDBY/ON” the power supply will instantly be shut off.
key of the main unit or the “STANDBY” key of the
remote controller. Note)
• Applying the power to a unit without correcting the
abnormality can be dangerous and cause additional
circuit damage.
• The output transistors in each amplifier channel
should be checked for damage before applying any
power.
• Amplifier current should be monitored by measuring
across the emitter resistors for each channel.
HTR-5790
16
HTR-5790
Voltage display in %
Reverse Forward
17
HTR-5790
1. DA601-YSS930
This function is for YSS930 only. Main DSP of YSS930
is selected for FRONT output.
Using the sub-menu, it is possible to select 0dB output
level or full-bit output.
YSS 0dB
• The signal is output including the head margin.
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
18
HTR-5790
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
DA601-YSS930 4Mbit
DRAM
(ANALOG)
DIR L/R
SWL/ SWL/SWR
SWR
DIR POST POST PL/PR
DECODE PL/PR
PROCESSING PROCESSING
DSP DSP DSP
ReL/
ReR
2. BYPASS
ANALOG BYPASS
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
19
HTR-5790
DSP BYPASS
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
DIR L/R
SWL/ SWL/SWR
SWR
DIR POST POST PL/PR
DECODE PL/PR
PROCESSING PROCESSING
DSP DSP DSP
ReL/
ReR
DSP BYPASS
4Mbit
(DIGITAL) DRAM
DIR L/R
SWL/ SWL/SWR
SWR
DIR POST POST PL/PR
DECODE PL/PR
PROCESSING PROCESSING
DSP DSP DSP
ReL/
ReR
20
HTR-5790
3. RAM THROUGH
Using the sub-menu, it is possible to select the full-bit
output at 0dB output level.
RAM 0dB
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
MAIN ATT
• MAIN -9dB
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
RAM THROUGH
(ANALOG)
4Mbit
DRAM
DIR L/R
SWL/ SWL/SWR
SWR
DIR POST POST PL/PR
DECODE PL/PR
PROCESSING PROCESSING
DSP DSP DSP
ReL/
ReR
21
HTR-5790
PRO LOGIC I
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
SPEAKER OUTPUT SUBWOOFER
Input level Volume
FRONT L/R CENTER SURROUND L/R SURROUND BACK OUTPUT
Each ch, -20 dBm +6.5 dB +13.5 dBm -∞ -∞ -∞ -∞
Both ch, -20 dBm +6.5 dB -∞ +16.5 dBm -∞ -∞ -∞
PRO LOGIC II
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
SPEAKER OUTPUT SUBWOOFER
Input level Volume
FRONT L/R CENTER SURROUND L/R SURROUND BACK OUTPUT
Each ch, -20 dBm +6.5 dB +13.5 dBm -∞ -∞ -∞ -∞
Both ch, -20 dBm +6.5 dB -∞ +16.5 dBm -∞ -∞ -∞
Neo:6
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
PRO LOGIC/NEO:6
(ANALOG) 4Mbit
DRAM
DIR L/R
SWL/ SWL/SWR
SWR
DIR POST POST PL/PR
DECODE PL/PR
PROCESSING PROCESSING
DSP DSP DSP
ReL/
ReR
HTR-5790
22
HTR-5790
5. SPEAKERS SET
The input signal is automatically identified in the order
of dts → DOLBY DIGITAL → AAC→ PCM → Analog.
There are seven sub-menu items as follows. The
signals output from the DSP block are the same as 1.
DA601-YSS930: YSS 0dB.
LARGE: This mode is used with a speaker with high NONE: This mode is used with no center speaker.
bass reproduction performance (a large The center content is reduced by 3dB and
unit). Full bandwidth signals are output. distributed to FRONT L/R.
SMALL: This mode is used with a speaker with low
bass reproduction performance (a small
unit). The signals of 90Hz or less are mixed
into the channel specified by LFE/BASS.
Reference data
INPUT: DVD ANALOG
SUBWOOFER: 50Hz, Others: 1kHz
SPEAKER OUTPUT SUBWOOFER
Sub-menu Input level Volume
FRONT L/R CENTER SURROUND L/R SURROUND BACK OUTPUT
1 FRONT: SMALL 0dB 1 kHz Both ch, -20 dBm +6.5 dB +13.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm -17.0 dBm
2 CENTER: NONE 1 kHz Both ch, -20 dBm +6.5 dB +10.5 dBm -∞ +13.5 dBm +13.5 dBm -22.0 dBm
3 LFE/BASS: FRONT 1 kHz Both ch, -20 dBm +6.5 dB -∞ +13.5 dBm +13.5 dBm +13.5 dBm -∞
50 Hz Both ch, -20 dBm +6.5 dB +24.0 dBm +4.5 dBm +4.5 dBm +4.5 dBm -7.0 dBm
4 PRESS MIX: 5CH 1 kHz Both ch, -20 dBm +6.5 dB +13.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm -7.0 dBm
5 SURROUND BACK: MUTE 1 kHz Both ch, -20 dBm +6.5 dB +13.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm -7.0 dBm
HTR-5790
6 SURROUND: MUTE 1 kHz Both ch, -20 dBm +6.5 dB +13.5 dBm +13.5 dBm -∞ +13.5 dBm -7.0 dBm
7 SURROUND: NONE 1 kHz Both ch, -20 dBm +6.5 dB +13.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm -7.0 dBm
23
HTR-5790
6. EXTERNAL INPUT
It is possible to select the 6ch/8ch input and 6_/8_ by
using the SUB menu.
6CH_INPUT_6OHMS
6CH_INPUT_8OHMS
8CH_INPUT_6OHMS
8CH_INPUT_8OHMS
Reference data
INPUT: MULTI CH INPUT
SUBWOOFER: 50Hz, Others: 1kHz
SPEAKER OUTPUT SUBWOOFER
Sub-menu Input level Volume
FRONT L/R CENTER SURROUND L/R SURROUND BACK OUTPUT
1 6CH_INPUT_6ohms Both ch, -20 dBm +6.5 dB +13.5 dBm +13.5 dBm +13.5 dBm -∞ -1.0 dBm
2 6CH_INPUT_8ohms Both ch, -20 dBm +6.5 dB +13.5 dBm +13.5 dBm +13.5 dBm -∞ -1.0 dBm
3 6CH_INPUT_6ohms Both ch, -20 dBm +6.5 dB -∞ +13.5 dBm +13.5 dBm +13.5 dBm -1.0 dBm
4 6CH_INPUT_8ohms Both ch, -20 dBm +6.5 dB -∞ +13.5 dBm +13.5 dBm +13.5 dBm -1.0 dBm
7. MIC CHECK
The signals inputted through the microphone are output
via A/D - D/A.
HTR-5790
24
HTR-5790
Short Normal
HTR-5790
25
HTR-5790
9. MANUAL TEST
The noise generator with a built-in DSP outputs the test
noise through the channels specified by the sub-menu.
The noise frequency for LFE is 35 to 250 Hz. Other than
that, the center frequency is 800Hz.
Noise is output from all channels. Noise is output from the FRONT L channel. Noise is output from the CENTER
channel.
Noise is output from the FRONT R channel. Noise is output from the SURROUND R Noise is output from the SURROUND
channel. B channel.
Noise is output from the SURROUND L Noise is output from the PRESENCE L Noise is output from the PRESENCE R
channel. channel. channel.
TEST LFE
10. RS-232C
Not applied to this model.
CAUTION: Before setting to the PRESET RESERVED, write down the existing preset memory content of the Tuner in a
HTR-5790
table as shown next page. (This is because setting to the PRESET RESERVED will cause the user memory
content to be erased.)
26
HTR-5790
Preset group P1 P2 P3 P4 P5 P6 P7 P8
• PRESET STATIONS
STATION FM FACTORY PRESET DATA (MHz) STATION AM FACTORY PRESET DATA (kHz)
PAGE NO. U, C A PAGE NO. U, C A
1 87.5 87.50 1 630 630
2 90.1 90.10 2 1080 1080
3 95.1 95.10 3 1440 1440
4 98.1 98.10 4 530 531
A/C/E B/D
5 107.9 108.00 5 1710 1611
6 88.1 88.10 6 900 900
7 106.1 106.10 7 1350 1350
8 107.9 108.00 8 1400 1404
12. AD DATA CHECK / FAN TEST THM/FAN OUT (temperature detection/fan drive level)
This menu is used to display the A/D conversion value THM: 500% display of the voltage based on the
of the main CPU which detects panel keys of the main temperature detected value.
unit and protection functions in % using the sub-menu. Reference voltage: 5V=500% (Normal value: 10 to
During signal processing, the condition before 139)
execution is maintained. Fan: Current fan drive level on the left and the past fan
When K0/K1 menu is selected, keys become non- drive history on the right.
operable due to detection of the values of all keys.
However, it is possible to advance to the next sub-
menu by turning the VOLUME of the main unit. When
using this function, note that turning the VOLUME
Display H M L
more than 1 click would cause the volume value to fan drive level HIGH MID LOW
change.
27
HTR-5790
Speaker impedance setting During normal operation When limiter is operating Value for starting limiter operation Value for canceling limiter operation
7CH STEREO
LC1=L LC1=H
or 184 157
LC2=H LC2=H
6 ohms EXT8CH_INPUT
Other than those LC1=L LC1=H
184 157
on the above LC2=H LC2=L
7CH STEREO
LC1=L LC1=H
or 163 157
LC2=L LC2=L
8 ohms EXT8CH_INPUT
Other than those LC1=L LC1=L
163 157
on the above LC2=L LC2=H
K0/K1 (Panel key of main unit) [Remote control code: –] FAN DRIVE TEST (For models so equipped)
A/D of the key fails to function properly when the standard HIGH
value is deviated by ±4%. In this case, check the constant
of partial pressure resistor, solder condition, etc. Refer to
table below.
(Reference voltage: 5V=100%)
FAN DRIVE TEST (For models so equipped)
MID
Display K0 K1
00+2 PRESET/TUNING – FAN DRIVE TEST (For models so equipped)
10±2 PRESET/TUNING SPEAKERS A LOW
20±2 PRESET/TUNING SPEAKERS B
30±2 FM/AM INPUT MODE
40±2 MEMORY A/B/C/D/E
50±2 TUNING MODE TONE CONTROL
60±2 – STRAIGHT/EFFECT
100 KEY OFF KEY OFF
HTR-5790
28
HTR-5790
HTR-5790
29
HTR-5790
<3rd byte> A u d i o c o d e m o d e i n f o r m a t i o n o f
reproduction signal
Display 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D
Audio Code MULTI MONO 1+1 1/0 2/0 3/0 2/1 3/1 2/2 3/2 2/3 3/3 OVER 6.1 MULTI PCE Unknown
TI1-2:
HTR-5790
30
HTR-5790
SW MODE
Display Description PCB or SOFT can be selected.
WAIT Bus is being checked.
NoEr No error detected.
DATA Data bus shorted or open.
RSCS /RAS or /CAS shorted, or open.
MODEL SETTING
ADDR Address bus shorted or open.
V1400 (HTR-5790) or V2400 can be selected.
As there is no model to replace with, this mode is used the
SECOND DECODER (DA601) BUS CHECK check for the V1400 (HTR-5790).
TUNER DESTINATION
Display Description J, UC, ALG or R can be selected.
Booting of DA601 being executed (When booting
In this model, it is possible to select UC or A.
is continued, possibility is that there is a defective
Boot
part or poor connection of the microprocessor
DA601 SDRAM.)
NoEr Booting of DA601 has been completed properly.
TUNER EXIST
NOT or EXIST can be selected.
RDS EXIST
16. PROTECTION SET
NOT or EXIST can be selected.
Not applied to this model.
ZONE 2 EXIST
NOT or EXIST can be selected.
VIDEO FORMAT
NTSC or PAL can be selected.
HTR-5790
31
HTR-5790
Version
Release 1 figure / Main 2 figures / DSP 2 figures / Communication 1 figure / Boot
manufacturer 1 figure / Boot 232C 1 figure
Checksum
A : All area P : Program area
Checksum
2 : Boot 232C M : Boot manufacturer
*2 (Tuner mode)
Tuner mode 0 Tuner mode 1 Tuner frequency
0 0 AM: 531-1611kHz/9kHz FM: 76.0-90.0MHz/100kHz
0 1 AM: 531-1611kHz/9kHz FM: 87.5-108.0MHz/50kHz
1 0 AM: 530-1710kHz/10kHz FM: 87.5-107.9MHz/200kHz
R destination, Port6: LOW AM: 530-1710kHz/10kHz FM: 87.5-108.0MHz/100kHz
1 1 HIGH AM: 531-1611kHz/9kHz FM: 87.5-108.0MHz/50kHz
HTR-5790
32
HTR-5790
■ AMP ADJUSTMENT
Confirmation of Idling Current of Amp Unit
• Right after power is turned on, confirm that the voltage Attention
MAIN (2) P. C. B.
across the terminals of R319 (Front Lch), R320 (Front If the idle current exceeds 10.0mV after an amplifier
Rch), R325 (Center), R326 (SURROUND Lch), R327 repair, first check for a defective component before
(SURROUND Rch), R321 (SURROUND BACK Lch), cutting the bias resistor. MAIN (3) P. C. B.
R322 (SURROUND BACK Rch) are between 0.1mV R292
• Confirm that the voltage is 0.2 mV ~ 15.0 mV after 60 R319
and 10.0mV. R291
minutes. R321 R322
• If it exceeds 10.0mV, open (cutoff) R291 (Front Lch),
R292 (Front Rch), R295 (Center), R296 (Surround R320
Lch), R297 (Surround Rch), R293 (Surround Back
R294
Lch), R294 (Surround Back Rch) and reconfirm the
voltage.
R293
Cut off
R296
R295
R297
MAIN (4) P. C. B.
33
HTR-5790
■ DISPLAY DATA
● V901 : 16-BT-112GNK (WB585800) ● ANODE CONNECTION
y 1
16G 15G 14G 13G~2G 1G
P1 S1 S2 1-1 1-1 1-1
P2 S4 S11 2-1 2-1 2-1
PATTERN AREA
P3 S5 S12 3-1 3-1 3-1
P4 S6 S13 4-1 4-1 4-1
P5 S7 S14 5-1 5-1 5-1
P6 S8 1-2 1-2 1-2
● PIN CONNECTION P7 S9 2-2 2-2 2-2
Connection F2 NX NP NP P38 P37 P36 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P9 4-2 4-2 4-2
P10 S3 5-2 5-2 5-2
Pin No. 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P11 S15 1-3 1-3 1-3
Connection P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 NC NC NC 16G 15G 14G 13G 12G 11G 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G NP NP NX F1 P12 S16 2-3 2-3 2-3
Note : 1) F1, F2 ..... Filament 2) NP ..... No pin 3) NC ..... No connection 4) NX ..... No extened 5) 1G ~ 16G ..... Grid 6) P1 ~ 38 ..... Anode P13 S17 3-3 3-3 3-3
P14 S18 4-3 4-3 4-3
P15 5-3 5-3 5-3
● GRID ASSIGNMENT
P16 1-4 1-4 1-4
16G 15G
P17 2-4 2-4 2-4
P18 B1 3-4 3-4 3-4
P19 B2 4-4 4-4 4-4
P20 B3 5-4 5-4 5-4
P21 B4 1-5 1-5 1-5
S19 1G 2G 3G 4G 5G 6G 7G 8G 9G 10G 11G 12G 13G 14G
P22 B5 2-5 2-5 2-5
P23 B6 3-5 3-5 3-5
(16G, 15G)
S1 S2 P24 B7 4-5 4-5 4-5
P25 B8 5-5 5-5 5-5
S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14
P26 B9 1-6 1-6 1-6
P27 B10 2-6 2-6 2-6
(1G~14G) (15G) (16G)
1-1 2-1 3-1 4-1 5-1 P28 3-6 3-6 3-6
B10
B9
1-2 2-2 3-2 4-2 5-2 B8 S15 P29 4-6 4-6 4-6
B7
B6
1-3 2-3 3-3 4-3 5-3 B4
B5 S16 P30 5-6 5-6 5-6
B3
B2 S18 S18 P31 S20 1-7 1-7 1-7
1-4 2-4 3-4 4-4 5-4
S17 P32 2-7 2-7 2-7
1-5 2-5 3-5 4-5 5-5
B1 P33 3-7 3-7 3-7
S20
1-6 2-6 3-6 4-6 5-6
P34 4-7 4-7 4-7
1-7 2-7 3-7 4-7 5-7
P35 5-7 5-7 5-7
P36 – S19
P37 –
P38 S21 – –
S21
34
HTR-5790
EMPHA/UO
3 RX1 I Coaxial-compatible digital data input pin with built-in amplifier
AUDIO/VO
4 RX2 Is TTL-compatible digital data input pin
DGND
DGND
XMCK
RERR
XOUT
DVDD
DVDD
CKST
XIN
INT
5 RX3 Is TTL-compatible digital data input pin
6 DGND Digital GND
36
35
34
33
32
31
30
29
28
27
26
25
DO 37 24 SDIN 7 DVDD Digital power supply
DI 38 23 SLRCK 8 RX4 Is TTL-compatible digital data input pin
CE 39 22 SBCK
CL 40 21 RDATA 9 RX5/VI Is TTL-compatible digital data / Validity flag input pin for modulation
XMODE 41 20 RLRCK 10 RX6/UI Is TTL-compatible digital data / User data input pin for modulation
DGND 42 19 DVDD
11 DVDD PLL digital power supply
DVDD 43 LC89057W-VF4-E 18 DGND
TMCK/PIO0 44 17 RBCK 12 DGND PLL digital GND
TBCK/PIO1 45 16 RMCK 13 LPF O PLL loop filter connection pin
TLRCK/PIO2 46 15 AGND
TDATA/PIO3 47 14 AVDD 14 ACDD PLL analog power supply
TXO/PIOEN 48 13 LPF 15 AGND PLL analog GND
10
11
12
1
2
3
4
5
6
7
8
9
16 RMCK O R system clock output pin (256fs, 512fs, XIN, VCO)
*: Pull-down resistor internal 17 RBCK O/I R bit clock input/output pin
RXOUT
*RX0
RX1
RX2
RX3
DGND
DVDD
*RX4
RX5/VI
*RX6/UI
DVDD
DGND
18 DGND Digital GND
19 DVDD Digital power supply
20 RLRCK O/I R LR clock input/output pin (fs)
EMPHA/UO
XMODE
23 SLRCK O S LR clock output pin (fs/s, fs, 2fs)
INT
CE
CL
CI
24 SDIN Is Serial audio data input pin (Unconnected)
32 33 35 40 39 38 41
25 DGND Digital GND
RXOUT 1 26 DVDD Digital power supply
27 XMCK O Oscillation amplifier output pin
RX0 2 Microcontroller
Cbit, Ubit 37 DO 28 XOUT O Crystal resonator connection output pin (Unconnected)
RX1 3 I/F
29 XIN I Crystal resonator connection, external supply clock input pin (24.576 MHz or 12.288 MHz)
RX2 4 36 RERR
Input 30 DVDD Digital power supply
RX3 5 Selector
RX4 8
Demodulation Data 31 DGND Digital GND
& 21 RDATA
RX5/VI Selector 32 EMPHA/UO I/O Emphasis information / U data output / Chip address setting pin
9 Lock Detect
RX6/UI 10 33 AUDIO/VO I/O Non-PCM output / V flag output / Chip address setting pin
24 SDIN 34 CKST I/O Clock switch transition period signal / Demodulation master or slave function switch pin
16 RMCK 35 INT I/O Microcontroller interrupt output / Modulation or general-purpose I/O switch pin
LPF 13 PLL
17 RBCK 36 RERR O PLL clock error, data error flag output
Clock 20 RLRCK 37 DO O Microcontroller I/F read data output pin (3-state)
TMCK/PIO0 44 Selector 22 SBCK
TBCK/PIO1 45 Modulation 1/N 38 DI Is Microcontroller I/F write data input pin
& 23 SLRCK
TLRCK/PIO2 46
Parallel Port 39 CE Is Microcontroller I/F chip enable input pin
TDATA/PIO3 47 40 CL Is Microcontroller I/F clock input pin
41 XMODE Is System reset input pin
TXO/PIOEN 48
42 DGND Digital GND
29 28 27 34
43 DVDD Digital power supply
XIN
XOUT
XMCK
CKST
44 TMCK/PIO0 I/O Modulation 256fs system clock input / General-purpose I/O input/output pin
45 TMCK/PIO1 I/O Modulation 64fs bit clock input / General-purpose I/O input/output pin
46 TLRCK/PIO2 I/O Modulation fs clock input / General-purpose I/O input/output pin
47 TLRCK/PIO3 I/O Modulation serial audio data input / General-purpose I/O input/output pin
48 TXO/PIOEN O/I Modulation data output / General-purpose I/O enable input pin
35
HTR-5790
I2C1 Enhanced
L2 Instruction Decode Logic 46 CVDD S 1.2V power supply
Memory
DMA Data Path A Data Path B Test
I2C0
Controller DA610:
47 DVDD S 3.3V power supply
(16 channel) A Register File B Register File In-Circuit
192K Bytes
Emulation 48 VSS GND Ground
Timer 1 DA601:
64K Bytes .L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t Interrupt
Control
49 VSS GND Ground
Timer 0
50 CVDD S 1.2V power supply
GP1
L1D Cache
51 CVDD S 1.2V power supply
2-Way Set
GP0 R2 ROM Associative 52 VSS GND Ground
512K 4K Bytes Total
HPI16 Bytes
Total
53 CVDD S 1.2V power supply
Clock Generator, 54 VSS GND Ground
Oscillator and PLL Power-Down
x4 through x25 Multipliers Logic
/1 through /32 Dividers 55 DVDD S 3.3v power supply
56 ARDY I Asynchronous RAM Ready input
57 /CE3 O/Z For external memory area, Enable 3 (Unconnected)
58 DVDD S 3.3V power supply
No. Name I/O Function 59 VSS GND Ground
1 GP0[4]/(EXT_INT4) IOZ General purpose I/O0 port 4 60 CVDD S 1.2V power supply
2 GP0[6]/(EXT_INT6) IOZ General purpose I/O0 port 6 (Unconnected) 61 /CE2 O/Z For external memory area, Enable 2 (Unconnected)
3 CVDD S 1.2V power supply 62 EA2 O/Z For external memory, Address 2
4 VSS GND Ground 63 EA3 O/Z For external memory, Address 3
5 DVDD S 3.3V power supply 64 EA4 O/Z For external memory, Address 4
6 GP0[5]/(EXT_INT5) IOZ General purpose I/O0 port 5 (Unconnected) 65 DVDD S 3.3V power supply
7 GP0[7]/(EXT_INT7) IOZ General purpose I/O0 port 7 (Unconnected) 66 VSS GND Ground
8 CLKS1 I McBSP1 external clock source (Unconnected) 67 CVDD S 1.2v power supply
9 DVDD S 3.3V power supply 68 EA5 O/Z For external memory, Address 5
10 VSS GND Ground 69 EA6 O/Z For external memory, Address 6
11 CVDD S 1.2V power supply 70 EA7 O/Z For external memory, Address 7
12 TINP1/AHCLKX0 I Timer 1 Input (Unconnected) 71 EA8 O/Z For external memory, Address 8
13 TOUT1/AXRO[4]/AXR1[11] O Timer 1 Output (Unconnected) 72 DVDD S 3.3V power supply
14 CVDD S 1.2V power supply 73 VSS GND Ground
15 VSS GND Ground 74 EA9 O/Z For external memory, Address 9
16 CLKX0/ACLKX0 IOZ McASP0 Transmission BCLK (Unconnected) 75 /SDRAS O/Z Asynchronous RAM OE / SDRAM RAS / SBS RAM OE
17 TINP0/AXRO[3]/AXR1[12] I Timer 0 Input (Unconnected) 76 EA10 O/Z For external memory, Address 10
18 TOUT0/AXRO[2]/AXR1[13] O Timer 0 Output (Unconnected) 77 ECLKOUT O/Z Clock output for EMIF
19 ACLKR0 IOZ McASP0 Reception BCLK 78 ECLKIN I Clock input for EMIF (Unconnected)
20 AXRO[1] IOZ McASP0 Transmission/reception data 1 79 /SDCAS O/Z Asynchronous RAM RE / SDRAM CAS / SBSRAM ADS
21 AFSX0 IOZ McASP0 Transmission LRCLK (Unconnected) 80 CVDD S 1.2V power supply
22 CVDD S 1.2V power supply 81 VSS GND Ground
23 VSS GND Ground 82 CLKOUT2/GP0[2] O/Z Half clock output of device Speed (Unconnected)
24 AFSR0 IOZ McASP0 Reception LRCLK 83 /SDWE O/Z Asynchronous RAM WE / SDRAM WE / SBSRAM WE
25 DVDD S 3.3V power supply 84 DVDD S 3.3V power supply
26 VSS GND Ground 85 VSS GND Ground
27 AXRO[0] IOZ McASP0 Transmission/reception data 0 86 EA11 O/Z For external memory, Address 11
28 AHCLKR0 I McASP0 Reception MCLK (Unconnected) 87 DVDD S 3.3V power supply
29 CVDD S 1.2V power supply 88 VSS GND Ground
30 VSS GND Ground 89 CVDD S 1.2V power supply
31 FSX1 IOZ McBSP1 Transmission Frame Sync (Input in SPI slave state) 90 EA14 O/Z For external memory, Address 14 (Unconnected)
32 DX1 O/Z McBSP1 Transmission data 91 EA13 O/Z For external memory, Address 13
33 CLKX1 IOZ McBSP1 Transmission clock (Input in SPI slave state) 92 EA16 O/Z For external memory, Address 16 (Unconnected)
34 VSS GND Ground 93 EA12 O/Z For external memory, Address 12
35 CVDD S 1.2V power supply 94 EA15 O/Z For external memory, Address 15 (Unconnected)
36 CLKR1 IOZ McBSP1 Reception clock (Unconnected) 95 EA18 O/Z For external memory, Address 18 (Unconnected)
37 DR1 I McBSP1 Reception data 96 CVDD S 1.2V power supply
38 FSR1 IOZ McBSP1 Reception Frame Sync (Unconnected) 97 VSS GND Ground
39 VSS GND Ground 98 DVDD S 3.3V power supply
40 CVDD S 1.2V power supply
36
HTR-5790
37
HTR-5790
IC516, 518: YSS930 (DSP P.C.B.) IC516, 518: YSS930 (DSP P.C.B.)
DSP DSP
RAMWEN
RAMOEN
RAMD15
RAMD14
RAMD13
RAMD12
RAMD11
RAMD10
RAMA10
RAMA9
RAMA3
RAMA4
RAMA2
RAMA5
RAMA1
RAMA6
RAMA0
RAMA7
RAMA8
No. Name I/O Function IC516 IC518
RASN
CASN
VDD2
VDD1
VDD1
VSS
1 VSS - Digital ground terminal
2 XO O Terminal for connecting crystal oscillator x x
3 XI I Terminal for connecting crystal oscillator (12.288Å`15.0MHz)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS 76 50 VDD2 4 IOPORT0 I+/O General purpose input/output terminal, SDO0 Lch zero-flag output terminal, input/output terminal for branching program conditions x
RAMA11 77 49 RAMD9
RAMA12 78 48 RAMD8 5 IOPORT1 I+/O General purpose input/output terminal, SDO0 Rch zero-flag output terminal, input/output terminal for branching program conditions x
RAMA13 79 47 RAMD7 6 IOPORT2 I+/O General purpose input/output terminal, SDO1 Lch zero-flag output terminal, input/output terminal for branching program conditions x
RAMA14 80 46 RAMD6
RAMA15 81 45 RAMD5 7 IOPORT3 I+/O General purpose input/output terminal, SDO1 Rch zero-flag output terminal, input/output terminal for branching program conditions x
RAMA16 82 44 RAMD4 8 IOPORT4 I+/O General purpose input/output terminal, SDO2 Lch zero-flag output terminal, input/output terminal for branching program conditions x
RAMA17 83 43 RAMD3
VDD1 84 42 RAMD2 9 IOPORT5 I+/O General purpose input/output terminal, SDO2 Rch zero-flag output terminal, input/output terminal for branching program conditions x
/CS 85 41 RAMD1 10 IOPORT6 I+/O General purpose input/output terminal, SDO3 Lch zero-flag output terminal, input/output terminal for branching program conditions x
SO 86 40 RAMD0 11 IOPORT7 I+/O General purpose input/output terminal, SDO3 Rch zero-flag output terminal, input/output terminal for branching program conditions x
SI 87 39 VDD1
SCK 88 38 IOPORT19 12 AVSS - Analog ground terminal (for PLL)
/IC 89 37 IOPORT18 13 CPO A Terminal for connecting PLL filter
SDWCK 90 36 IOPORT17
SDBCK 91 35 IOPORT16 14 AVDD - +2.5V digital power supply (for PLL)
SDI7 92 34 SDO7 15 VDD1 - +3.3V digital power supply (for input/output terminal)
SDI6 93 33 SDO6
SDI5 94 32 SDO5 16 (NC) - x x
SDI4 95 31 SDO4 17 IOPORT8 I+/O General purpose input/output terminal, SD04 Lch zero-flag output terminal
SDI3 96 30 SDO3 18 IOPORT9 I+/O General purpose input/output terminal, SD04 Rch zero-flag output terminal
SDI2 97 29 SDO2
SDI1 98 28 SDO1 19 IOPORT10 I+/O General purpose input/output terminal, SD05 Lch zero-flag output terminal
SDI0 99 27 SDO0 20 IOPORT11 I+/O General purpose input/output terminal, SD05 Rch zero-flag output terminal
VDD2 100 26 VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
21 IOPORT12 I+/O General purpose input/output terminal, SD06 Lch zero-flag output terminal, input terminal 0 for chip address setting
1
2
3
4
5
6
7
8
9
22 IOPORT13 I+/O General purpose input/output terminal, SD06 Rch zero-flag output terminal, input terminal 1 for chip address setting
VSS
XO
XI
IOPORT0
IOPORT1
IOPORT2
IOPORT3
IOPORT4
IOPORT5
IOPORT6
IOPORT7
AVSS
CPO
AVDD
VDD1
(NC)
IOPORT8
IOPORT9
IOPORT10
IOPORT11
IOPORT12
IOPORT13
IOPORT14
IOPORT15
VDD2
23 IOPORT14 I+/O General purpose input/output terminal, SD07 Lch zero-flag output terminal, input terminal 2 for chip address setting
24 IOPORT15 I+/O General purpose input/output terminal, SD07 Rch zero-flag output terminal, input terminal 3 for chip address setting
25 VDD2 - +2.5V digital power supply (for internal circuit)
26 VSS - Digital ground terminal
27 SDO0 O PCM output terminal
IOPORT19~0
SO
SDWCKO
CONTROL REGISTER 50 bit *1024 word 16 bit *1024 word 17 bit *256 word
37 IOPORT18 I+/O General purpose input/output terminal, 64fs clock output terminal x
MPLOAD
CONTROL
38 IOPORT19 I+/O General purpose input/output terminal, fs clock output terminal x
SIGNALS 39 VDD1 - +3.3V digital power supply (for input/output terminal)
SDBCK
40 RAMD0 I+/O Data input/output terminal 0 for external memory x
SDWCK
41 RAMD1 I+/O Data input/output terminal 1 for external memory x
42 RAMD2 I+/O Data input/output terminal 2 for external memory x
OVF
END
ZEROF7R-0L
SDI0 SDO0 43 RAMD3 I+/O Data input/output terminal 3 for external memory x
SDO INTERFACE
SDI1
SDI INTERFACE
SDO1
32 bit *1024 word
SDI2 SDO2 44 RAMD4 I+/O Data input/output terminal 4 for external memory x
DATA RAM
SDI3 SDO3 45 RAMD5 I+/O Data input/output terminal 5 for external memory x
32 bit DSP Core
SDI4 SDO4
SDI5 SDO5 46 RAMD6 I+/O Data input/output terminal 6 for external memory x
SDI6 SDO6 47 RAMD7 I+/O Data input/output terminal 7 for external memory x
SDI7 SDO7
48 RAMD8 I+/O Data input/output terminal 8 for external memory x
49 RAMD9 I+/O Data input/output terminal 9 for external memory x
DSP INTERNAL 50 VDD2 - +2.5V digital power supply (for internal circuit)
OPERATING CLOCK
CK (30.72~40.96MHz) EXTERNAL RAM 51 VSS - Digital ground terminal
INTERFACE
52 RAMD10 I+/O Data input/output terminal 10 for external memory x
PLL
53 RAMD11 I+/O Data input/output terminal 11 for external memory x
54 RAMD12 I+/O Data input/output terminal 12 for external memory x
XO
XI
CPO
RAMD15~0
CASN
RASN
RAMWEN
RAMOEN
RAMA17~0
38
HTR-5790
P15/D13/INT3
P16/D14/INT4
P17/D15/INT5
No. Name I/O Function IC516 IC518
P12/D10
P13/D11
P14/D12
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
P40/A16
P41/A17
P42/A18
P43/A19
P11/D9
P20/A0
P21/A1
P22/A2
P23/A3
P24/A4
P25/A5
P26/A6
P27/A7
P30/A8
P31/A9
57 RAMD14 I+/O Data input/output terminal 14 for external memory x
P120
P121
P122
P123
P124
Vss
Vcc
Vss
Vcc
58 RAMD15 I+/O Data input/output terminal 15 for external memory x
59 CASN O Column address strobe output terminal for external DRAM x
60 RAMWEN O Write enable output terminal for external memory x
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
108
107
106
105
104
103
102
101
100
61 RAMOEN O Output enable output terminal for external memory x P10/D8 109 72 P44/CS3/A20
P07/D7 110 71 P45/CS2/A21
62 RASN O Low address strobe output terminal for external DRAM x P06/D6 111 70 P46/CS1/A22
63 RAMA8 O Address output terminal 8 for external memory x P05/D5 112 69 P47/CS0/A23
P04/D4 113 68 P125
64 RAMA7 O Address output terminal 7 for external memory x P114 114 67 P126
P113 115 66 P127
65 RAMA0 O Address output terminal 0 for external memory x
P112 116 65 P50/WRL/WR/CASL
66 RAMA6 O Address output terminal 6 for external memory x P111 117 64 P51/WRH/BHE/CASH
P110 118 63 P52/RD/DW
67 RAMA1 O Address output terminal 1 for external memory x P03/D3 119 62 P53/BCLK/ALE/CLKout
68 VDD1 - +3.3V digital power supply (for input/output terminal) P02/D2 120 61 P130
P01/D1 121 60 P131
69 RAMA5 O Address output terminal 5 for external memory x P00/D0 122 59 Vcc
70 RAMA2 O Address output terminal 2 for external memory x P157 123 58 P132
P156 124 57 Vss
71 RAMA4 O Address output terminal 4 for external memory x P155 125 56 P133
72
73
RAMA3
RAMA9
O
O
Address output terminal 3 for external memory
Address output terminal 9 for external memory x
x
x
P154
P153
P152
126
127
128
M30805SGP 55
54
53
P54/HLDA/ALE
P55/HOLD
P56/ALE/RAS
P151 129 52 P57/RDY
74 RAMA10 O Address output terminal 10 for external memory x x Vss 130 51 P134
75 VDD2 - +2.5V digital power supply (for internal circuit) P150 131 50 P135
Vcc 132 49 P136
76 VSS - Digital ground terminal P107/AN7/KI3 133 48 P137
77 RAMA11 O Address output terminal 11 for external memory x x P106/AN6/KI2 134 47 P60/CTS0/RTS0
P105/AN5/KI1 135 46 P61/CLK0
78 RAMA12 O Address output terminal 12 for external memory x x P104/AN4/KI0 136 45 P62/RXD0
P103/AN3 137 44 P63/TXD0
79 RAMA13 O Address output terminal 13 for external memory x x
P102/AN2 138 43 P64/CTS1/RTS1/CTS0/CLKS1
80 RAMA14 O Address output terminal 14 for external memory x x P101/AN1 139 42 P65/CLK1
Avss 140 41 Vss
81 RAMA15 O Address output terminal 15 for external memory x x P100/AN0 141 40 P66/RXD1
82 RAMA16 O Address output terminal 16 for external memory x x Vref 142 39 Vcc
Avcc 143 38 P67/TXD1
83 RAMA17 O Address output terminal 17 for external memory x x P97/Adtrg/RxD4/SCL4/STxD4 144 37 P70/TXD2/SDA/TA0out
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
85 /CS Is Microprocessor interface chip select input terminal
86 SO Ot Microprocessor interface data output terminal
P96/ANEX1/TxD4/SDA4
P95/ANEX0/CLK4
P94/DA1/TB4in/CTS4/RTS4/SS4
P93/DA0/TB3in/CTS3/RTS3/SS3
P92/TB2in/TxD3/SDA3/STxD3
P91/TB1in/RxD3/SCL3
P90/TB0in/CLK3
P146
P145
P144
P143
P142
P141
P140
BYTE
CNVss
P87/Xcin
P86/Xcout
RESET
Xout
Vss
Xin
Vcc
P85/NMI
P84/INT2
P83/INT1
P82/INT0
P81/TA4in/U
P80/TA4out/U
P77/TA3in
P76/TA3out
P75/TA2in/W
P74/TA2out/W
P73/CTS2/RTS2/TA1in/V
P72/CLK2/TA1out/V
P71/RXD2/SCL/TA0in/TB5in
87 SI Is Microprocessor interface data input terminal
88 SCK Is Microprocessor interface clock input terminal
89 /IC Is Initial clear input terminal
90 SDWCK I Word clock (fs) input terminal for SDI/SDO interface
91 SDBCK Is Bit clock (64fs) input terminal for SDI/SDO interface
92 SDI7 I PCM input terminal
93 SDI6 I PCM input terminal
94 SDI5 I PCM input terminal 8 8 8 8 8 8 8
Port P7
Timer TA0 (16 bits)
Timer TA1 (16 bits) XCIN - XCOUT
99 SDI0 I PCM input terminal UART/ Clock Synchronous
8
Timer TA2 (16 bits) SI/O (8 bits x 5 channels)
Timer TA3 (16 bits)
100 VDD2 - +2.5V digital power supply (for internal circuit) Timer TA4 (16 bits) X-Y Converter Memory
Port P8
Timer TB0 (16 bits) (16 bits x 16 bits)
Timer TB1 (16 bits) RAM
7
Timer TB2 (16 bits) CRC arithmetic Circuit (CCITT) 24K
Is: Schmidt trigger input terminal Timer TB3 (16 bits) (Polynomial: X16+X12+X5+1)
Timer TB4 (16 bits)
Port P85
I+: Input terminal with pull-up resistor Timer TB5 (16 bits)
M16C/80 Series 16-bit CPU core
O: Digital output terminal
Watchdog Timer Registers DRAM
Ot: 3-state digital output terminal (15 bits) R0H
FLG Controller
R0H R0LR0L
Port P9
INTB
A: Analog terminal R1H
R1H R1LR1L
D-A Converter ISP
x : Unconnected R2 DRAM
8
(8 bits x 2 channels) R2 USP
R3 Controller
R3 PC
Port P10
SVP
A0
VCT Multiplier
A1 SVF
8
SVP
FB SVP
VCT
SB VCT
Port P15 Port P14 Port P13 Port P12 Port P11
8 7 8 8 5
39
HTR-5790
40
HTR-5790
41