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    74 HC 42

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    Kiran Paru
    The document describes a BCD to decimal decoder integrated circuit. It decodes 4-bit binary-coded decimal (BCD) inputs into 10 mutually exclusive outputs, with only one output active at a time corresponding to the decimal value of the BCD inputs. It provides high-speed operation and compatibility with TTL logic standards. The document provides detailed specifications, pin descriptions, logic diagrams and truth tables for the IC.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    74 HC 42

    Uploaded by

    Kiran Paru
    64 views6 pages
    The document describes a BCD to decimal decoder integrated circuit. It decodes 4-bit binary-coded decimal (BCD) inputs into 10 mutually exclusive outputs, with only one output active at a time corresponding to the decimal value of the BCD inputs. It provides high-speed operation and compatibility with TTL logic standards. The document provides detailed specifications, pin descriptions, logic diagrams and truth tables for the IC.

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    74hc42

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    The document describes a BCD to decimal decoder integrated circuit. It decodes 4-bit binary-coded decimal (BCD) inputs into 10 mutually exclusive outputs, with only one output active at a time corresponding to the decimal value of the BCD inputs. It provides high-speed operation and compatibility with TTL logic standards. The document provides detailed specifications, pin descriptions, logic diagrams and truth tables for the IC.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    64 views6 pages

    74 HC 42

    Uploaded by

    Kiran Paru
    The document describes a BCD to decimal decoder integrated circuit. It decodes 4-bit binary-coded decimal (BCD) inputs into 10 mutually exclusive outputs, with only one output active at a time corresponding to the decimal value of the BCD inputs. It provides high-speed operation and compatibility with TTL logic standards. The document provides detailed specifications, pin descriptions, logic diagrams and truth tables for the IC.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 6

    INTEGRATED CIRCUITS

    DATA SHEET
    For a complete data sheet, please also download:

    • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications


    • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
    • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

    74HC/HCT42
    BCD to decimal decoder (1-of-10)
    Product specification December 1990
    File under Integrated Circuits, IC06
    Philips Semiconductors Product specification

    BCD to decimal decoder (1-of-10) 74HC/HCT42

    FEATURES The 74HC/HCT42 decoders accept four active HIGH BCD


    inputs and provide 10 mutually exclusive active LOW
    • Mutually exclusive outputs
    outputs. The active LOW outputs facilitate addressing
    • 1-of-8 demultiplexing capability other MSI circuits with active LOW input enables.
    • Outputs disabled for input codes above nine The logic design of the “42” ensures that all outputs are
    • Output capability: standard HIGH when binary codes greater than nine are applied to
    • ICC category: MSI the inputs.
    The most significant input (A3) produces an useful inhibit
    GENERAL DESCRIPTION function when the “42” is used as a 1-of-8 decoder. The A3
    input can also be used as the data input in an 8-output
    The 74HC/HCT42 are high-speed Si-gate CMOS devices demultiplexer application.
    and are pin compatible with low power Schottky TTL
    (LSTTL). They are specified in compliance with JEDEC
    standard no. 7A.

    QUICK REFERENCE DATA


    GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

    TYPICAL
    SYMBOL PARAMETER CONDITIONS UNIT
    HC HCT
    tPHL/ tPLH propagation delay An to Yn CL = 15 pF; VCC = 5 V 14 17 ns
    CI input capacitance 3.5 3.5 pF
    CPD power dissipation capacitance per package notes 1 and 2 37 37 pF

    Notes
    1. CPD is used to determine the dynamic power dissipation (PD in µW):
    PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
    fi = input frequency in MHz
    fo = output frequency in MHz
    ∑ (CL × VCC2 × fo) = sum of outputs
    CL = output load capacitance in pF
    VCC = supply voltage in V
    2. For HC the condition is VI = GND to VCC
    For HCT the condition is VI = GND to VCC − 1.5 V

    ORDERING INFORMATION
    See “74HC/HCT/HCU/HCMOS Logic Package Information”.

    December 1990 2
    Philips Semiconductors Product specification

    BCD to decimal decoder (1-of-10) 74HC/HCT42

    PIN DESCRIPTION

    PIN NO. SYMBOL NAME AND FUNCTION


    1, 2, 3, 4, 5, 6, 7, 9, 10, 11 Y0 to Y9 multiplexer outputs
    8 GND ground (0 V)
    15, 14, 13, 12 A0 to A3 data inputs
    16 VCC positive supply voltage

    Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

    December 1990 3
    Philips Semiconductors Product specification

    BCD to decimal decoder (1-of-10) 74HC/HCT42

    FUNCTION TABLE

    INPUTS OUTPUTS
    A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
    L L L L L H H H H H H H H H
    L L L H H L H H H H H H H H
    L L H L H H L H H H H H H H
    L L H H H H H L H H H H H H
    L H L L H H H H L H H H H H
    L H L H H H H H H L H H H H
    L H H L H H H H H H L H H H
    L H H H H H H H H H H L H H
    H L L L H H H H H H H H L H
    H L L H H H H H H H H H H L
    H L H L H H H H H H H H H H
    H L H H H H H H H H H H H H
    H H L L H H H H H H H H H H
    H H L H H H H H H H H H H H
    H H H L H H H H H H H H H H
    H H H H H H H H H H H H H H
    Fig.4 Functional diagram.
    Note
    1. H = HIGH voltage level
    L = LOW voltage level

    Fig.5 Logic diagram.

    December 1990 4
    Philips Semiconductors Product specification

    BCD to decimal decoder (1-of-10) 74HC/HCT42

    DC CHARACTERISTICS FOR 74HC


    For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
    Output capability: standard
    ICC category: MSI

    AC CHARACTERISTICS FOR 74HC


    GND = 0 V; tr = tf = 6 ns; CL = 50 pF

    Tamb (°C) TEST CONDITIONS


    74HC
    SYMBOL PARAMETER UNIT VCC WAVEFORMS
    +25 −40 to +85 −40 to +125
    (V)
    min. typ. max. min. max. min. max.
    tPHL/ tPLH propagation delay 47 150 190 225 ns 2.0 Fig.6
    An to Yn 17 30 38 45 4.5
    14 26 33 38 6.0
    tTHL/ tTLH output transition time 19 75 95 110 ns 2.0 Fig.6
    7 15 19 22 4.5
    6 13 16 19 6.0

    DC CHARACTERISTICS FOR 74HCT


    For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
    Output capability: standard
    ICC category: MSI

    Note to HCT types


    The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
    To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

    INPUT UNIT LOAD COEFFICIENT


    An 1.0

    AC CHARACTERISTICS FOR 74HCT


    GND = 0 V; tr = tf = 6 ns; CL = 50 pF

    Tamb (°C) TEST CONDITIONS


    74HCT
    SYMBOL PARAMETER UNIT VCC WAVEFORMS
    +25 −40 to +85 −40 to +125
    (V)
    min. typ. max. min. max. min. max.
    tPHL/ tPLH propagation delay 20 35 44 53 ns 4.5 Fig.6
    An to Yn
    tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6

    December 1990 5
    Philips Semiconductors Product specification

    BCD to decimal decoder (1-of-10) 74HC/HCT42

    AC WAVEFORMS

    (1) HC : VM = 50%; VI = GND to VCC.


    HCT: VM = 1.3 V; VI = GND to 3 V.

    Fig.6 Waveforms showing the input (An) to output (Yn) propagation delays and the output transition times.

    PACKAGE OUTLINES
    See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

    December 1990 6

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