Sequential Logic Basics

Unlike Combinational Logic circuits that change state depending upon the actual signals being applied to
their inputs at that time, Sequential Logic circuits have some form of inherent “Memory” built in to them as
they are able to take into account their previous input state as well as those actually present, a sort
of ”before” and “after” effect is involved with sequential logic circuits.

In other words, the output state of a “sequential logic circuit” is a function of the following three states, the
“present input”, the “past input” and/or the “past output”. Sequential Logic circuits remember these conditions
and stay fixed in their current state until the next clock signal changes one of the states, giving sequential logic
circuits “Memory”.
Sequential logic circuits are generally termed as two state or Bistable devices which can have their output or
outputs set in one of two basic states, a logic level “1” or a logic level “0” and will remain “latched” (hence the
name latch) indefinitely in this current state or condition until some other input trigger pulse or signal is
applied which will cause the bistable to change its state once again.

Sequential Logic Representation

The word “Sequential” means that things happen in a “sequence”, one after another and in Sequential Logic
circuits, the actual clock signal determines when things will happen next. Simple sequential logic circuits can be
constructed from standard Bistable circuits such as: Flip-flops, Latches and Counters and which themselves can
be made by simply connecting together universal NAND Gates and/or NOR Gates in a particular combinational
way to produce the required sequential circuit.

Classification of Sequential Logic

As standard logic gates are the building blocks of combinational circuits, bistable latches and flip-flops are the
basic building blocks of Sequential Logic Circuits
Sequential logic circuits can be constructed to produce either simple edge-triggered flip-flops or more complex
sequential circuits such as storage registers, shift registers, memory devices or counters. Either way sequential
logic circuits can be divided into the following three main categories:
1. Event Driven – asynchronous circuits that change state immediately when enabled.
2. Clock Driven – synchronous circuits that are synchronised to a specific clock signal.
3. Pulse Driven – which is a combination of the two that responds to triggering pulses.
As well as the two logic states mentioned above logic level “1” and logic level “0”, a third element is introduced
that separates sequential logic circuits from their combinational logic counterparts, namely TIME. Sequential
logic circuits return back to their original steady state once reset and sequential circuits with loops or feedback
paths are said to be “cyclic” in nature.
We now know that in sequential circuits changes occur only on the application of a clock signal making it
synchronous, otherwise the circuit is asynchronous and depends upon an external input. To retain their current
state, sequential circuits rely on feedback and this occurs when a fraction of the output is fed back to the input
and this is demonstrated as:

Sequential Feedback Loop

The two inverters or NOT gates are connected in series with the output at Q fed back to the input.
Unfortunately, this configuration never changes state because the output will always be the same, either a “1”
or a “0”, it is permanently set. However, we can see how feedback works by examining the most basic
sequential logic components, called the SR flip-flop.

SR Flip-Flop
The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic sequential logic circuit
possible. This simple flip-flop is basically a one-bit memory bistable device that has two inputs, one which will
“SET” the device (meaning the output = “1”), and is labelled S and another which will “RESET” the device
(meaning the output = “0”), labelled R.
Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop back to its original state with
an output Q that will be either at a logic level “1” or logic “0” depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its opposing inputs
and is commonly used in memory circuits to store a single data bit. Then the SR flip-flop actually has three
inputs, Set, Reset and its current output Q relating to it’s current state or history. The term “Flip-flop” relates to
the actual operation of the device, as it can be “flipped” into one logic Set state or “flopped” back into the
opposing logic Reset state.
The NAND Gate SR Flip-Flop
The simplest way to make any basic single bit set-reset SR flip-flop is to connect together a pair of cross-
coupled 2-input NAND gates as shown, to form a Set-Reset Bistable also known as an active LOW SR NAND
Gate Latch, so that there is feedback from each output to one of the other NAND gate inputs. This device
consists of two inputs, one called the Set, S and the other called the Reset, R with two corresponding outputs Q
and its inverse or complement Q (not-Q) as shown below.

The Basic SR Flip-flop

The Set State

Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and input S is at logic level “1” (S = 1),
the NAND gate Y has at least one of its inputs at logic “0” therefore, its output Q must be at a logic level “1”
(NAND Gate principles). Output Q is also fed back to input “A” and so both inputs to NAND gate X are at logic
level “1”, and therefore its output Q must be at logic level “0”.
Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic “1” with S remaining
HIGH also at logic level “1”, NAND gate Y inputs are now R = “1” and B = “0”. Since one of its inputs is still at
logic level “0” the output at Q still remains HIGH at logic level “1” and there is no change of state. Therefore,
the flip-flop circuit is said to be “Latched” or “Set” with Q = “1” and Q = “0”.

Reset State
In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output at Q is at logic level “1”, (Q =
“1”), and is given by R = “1” and S = “0”. As gate X has one of its inputs at logic “0” its output Q must equal logic
level “1” (again NAND gate principles). Output Q is fed back to input “B”, so both inputs to NAND gate Y are at
logic “1”, therefore, Q = “0”.
If the set input, S now changes state to logic “1” with input R remaining at logic “1”, output Q still remains LOW
at logic level “0” and there is no change of state. Therefore, the flip-flop circuits “Reset” state has also been
latched and we can define this “set/reset” action in the following truth table.

Truth Table for this Set-Reset Function

State S R Q Q Description

1 0 0 1 Set Q » 1
Set
1 1 0 1 no change

0 1 1 0 Reset Q » 0
Reset
1 1 1 0 no change

Invalid 0 0 1 1 Invalid Condition

It can be seen that when both inputs S = “1” and R = “1” the outputs Q and Q can be at either logic level “1” or
“0”, depending upon the state of the inputs S or R BEFORE this input condition existed. Therefore the condition
of S = R = “1” does not change the state of the outputs Q and Q.
However, the input state of S = “0” and R = “0” is an undesirable or invalid condition and must be avoided. The
condition of S = R = “0” causes both outputs Q and Q to be HIGH together at logic level “1” when we would
normally want Q to be the inverse of Q. The result is that the flip-flop looses control of Q and Q, and if the two
inputs are now switched “HIGH” again after this condition to logic “1”, the flip-flop becomes unstable and
switches to an unknown data state based upon the unbalance as shown in the following switching diagram.

S-R Flip-flop Switching Diagram

This unbalance can cause one of the outputs to switch faster than the other resulting in the flip-flop switching
to one state or the other which may not be the required state and data corruption will exist. This unstable
condition is generally known as its Meta-stable state.
Then, a bistable SR flip-flop or SR latch is activated or set by a logic “1” applied to its S input and deactivated or
reset by a logic “1” applied to its R. The SR flip-flop is said to be in an “invalid” condition (Meta-stable) if both
the set and reset inputs are activated simultaneously.
As we have seen above, the basic NAND gate SR flip-flop requires logic “0” inputs to flip or change state from Q
to Q and vice versa. We can however, change this basic flip-flop circuit to one that changes state by the
application of positive going input signals with the addition of two extra NAND gates connected as inverters to
the S and R inputs as shown.

Positive NAND Gate SR Flip-flop

As well as using NAND gates, it is also possible to construct simple one-bit SR Flip-flops using two cross-coupled
NOR gates connected in the same configuration. The circuit will work in a similar way to the NAND gate circuit
above, except that the inputs are active HIGH and the invalid condition exists when both its inputs are at logic
level “1”, and this is shown below.
The NOR Gate SR Flip-flop

Switch Debounce Circuits

Edge-triggered flip-flops require a nice clean signal transition, and one practical use of this type of set-reset
circuit is as a latch used to help eliminate mechanical switch “bounce”. As its name implies, switch bounce
occurs when the contacts of any mechanically operated switch, push-button or keypad are operated and the
internal switch contacts do not fully close cleanly, but bounce together first before closing (or opening) when
the switch is pressed.
This gives rise to a series of individual pulses which can be as long as tens of milliseconds that an electronic
system or circuit such as a digital counter may see as a series of logic pulses instead of one long single pulse
and behave incorrectly. For example, during this bounce period the output voltage can fluctuate wildly and
may register multiple input counts instead of one single count. Then set-reset SR Flip-flops or Bistable Latch
circuits can be used to eliminate this kind of problem and this is demonstrated below.

SR Flip Flop Switch Debounce Circuit

Depending upon the current state of the output, if the set or reset buttons are depressed the output will
change over in the manner described above and any additional unwanted inputs (bounces) from the
mechanical action of the switch will have no effect on the output at Q.
When the other button is pressed, the very first contact will cause the latch to change state, but any additional
mechanical switch bounces will also have no effect. The SR flip-flop can then be RESET automatically after a
short period of time, for example 0.5 seconds, so as to register any additional and intentional repeat inputs
from the same switch contacts, such as multiple inputs from a keyboards “RETURN” key.
Commonly available IC’s specifically made to overcome the problem of switch bounce are the MAX6816, single
input, MAX6817, dual input and the MAX6818 octal input switch debouncer IC’s. These chips contain the
necessary flip-flop circuitry to provide clean interfacing of mechanical switches to digital systems.
Set-Reset bistable latches can also be used as Monostable (one-shot) pulse generators to generate a single
output pulse, either high or low, of some specified width or time period for timing or control purposes. The
74LS279 is a Quad SR Bistable Latch IC, which contains four individual NAND type bistable’s within a single chip
enabling switch debounce or monostable/astable clock circuits to be easily constructed.

Quad SR Bistable Latch 74LS279

Gated or Clocked SR Flip-Flop

It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop that only changes state when
certain conditions are met regardless of the condition of either the Set or the Reset inputs. By connecting a 2-
input AND gate in series with each input terminal of the SR Flip-flop a Gated SR Flip-flop can be created. This
extra conditional input is called an “Enable” input and is given the prefix of “EN“. The addition of this input
means that the output at Q only changes state when it is HIGH and can therefore be used as a clock (CLK) input
making it level-sensitive as shown below.

Gated SR Flip-flop

When the Enable input “EN” is at logic level “0”, the outputs of the two AND gates are also at logic level “0”,
(AND Gate principles) regardless of the condition of the two inputs S and R, latching the two outputs Q and Q
into their last known state. When the enable input “EN” changes to logic level “1” the circuit responds as a
normal SR bistable flip-flop with the two AND gates becoming transparent to the Set and Reset signals.
This additional enable input can also be connected to a clock timing signal (CLK) adding clock synchronisation to
the flip-flop creating what is sometimes called a “Clocked SR Flip-flop“. So a Gated Bistable SR Flip-flop
operates as a standard bistable latch but the outputs are only activated when a logic “1” is applied to its EN
input and deactivated by a logic “0”.
In the next tutorial about Sequential Logic Circuits, we will look at another type of simple edge-triggered flip-
flop which is very similar to the RS flip-flop called a JK Flip-flop named after its inventor, Jack Kilby. The JK flip-
flop is the most widely used of all the flip-flop designs as it is considered to be a universal device.

The D-type Flip Flop

One of the main disadvantages of the basic SR NAND Gate bistable circuit is that the indeterminate input
condition of “SET” = logic “0” and “RESET” = logic “0” is forbidden. This state will force both outputs to be at
logic “1”, over-riding the feedback latching action and whichever input goes to logic level “1” first will lose
control, while the other input still at logic “0” controls the resulting state of the latch.

But in order to prevent this from happening an inverter can be connected between the “SET” and the “RESET”
inputs to produce another type of flip flop circuit known as a Data Latch, Delay flip flop, D-type Bistable, D-type
Flip Flop or just simply a D Flip Flop as it is more generally called.
The D Flip Flop is by far the most important of the Clocked Flip-flops as it ensures that ensures that inputs S and
R are never equal to one at the same time. The D-type flip flop are constructed from a gated SR flip-flop with an
inverter added between the S and the R inputs to allow for a single D (data) input.
Then this single data input, labelled D, is used in place of the “set” signal, and the inverter is used to generate
the complementary “reset” input thereby making a level-sensitive D-type flip-flop from a level-sensitive RS-
latch as now S = D and R = not D as shown.

D-type Flip-Flop Circuit

We remember that a simple SR flip-flop requires two inputs, one to “SET” the output and one to “RESET” the
output. By connecting an inverter (NOT gate) to the SR flip-flop we can “SET” and “RESET” the flip-flop using
just one input as now the two input signals are complements of each other. This complement avoids the
ambiguity inherent in the SR latch when both inputs are LOW, since that state is no longer possible.

Thus this single input is called the “DATA” input. If this data input is held HIGH the flip flop would be “SET” and
when it is LOW the flip flop would change and become “RESET”. However, this would be rather pointless since
the output of the flip flop would always change on every pulse applied to this data input.

To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate the data input from
the flip flop’s latching circuitry after the desired data has been stored. The effect is that D input condition is
only copied to the output Q when the clock input is active. This then forms the basis of another sequential
device called a D Flip Flop.

The “D flip flop” will store and output whatever logic level is applied to its data terminal so long as the clock
input is HIGH. Once the clock input goes LOW the “set” and “reset” inputs of the flip-flop are both held at logic
level “1” so it will not change state and store whatever data was present on its output before the clock
transition occurred. In other words the output is “latched” at either logic “0” or logic “1”.
Truth Table for the D-type Flip Flop

Clk D Q Q Description

Memory
↓»0 X Q Q
no change

↑»1 0 0 1 Reset Q » 0

↑»1 1 1 0 Set Q » 1
Note that: ↓ and ↑ indicates direction of clock pulse as it is assumed D-type flip flops are edge triggered

The Master-Slave D Flip Flop

The basic D-type flip flop can be improved further by adding a second SR flip-flop to its output that is activated
on the complementary clock signal to produce a “Master-Slave D-type flip flop”. On the leading edge of the
clock signal (LOW-to-HIGH) the first stage, the “master” latches the input condition at D, while the output stage
is deactivated.

On the trailing edge of the clock signal (HIGH-to-LOW) the second “slave” stage is now activated, latching on to
the output from the first master circuit. Then the output stage appears to be triggered on the negative edge of
the clock pulse. “Master-Slave D-type flip flops” can be constructed by the cascading together of two latches
with opposite clock phases as shown.

The Master-Slave D Flip Flop Circuit

We can see from above that on the leading edge of the clock pulse the master flip-flop will be loading data
from the data D input, therefore the master is “ON”. With the trailing edge of the clock pulse the slave flip-flop
is loading data, i.e. the slave is “ON”. Then there will always be one flip-flop “ON” and the other “OFF” but
never both the master and slave “ON” at the same time. Therefore, the output Q acquires the value of D, only
when one complete pulse, ie, 0-1-0 is applied to the clock input.

There are many different D flip-flop IC’s available in both TTL and CMOS packages with the more common
being the 74LS74 which is a Dual D flip-flop IC, which contains two individual D type bistable’s within a single
chip enabling single or master-slave toggle flip-flops to be made. Other D flip-flop IC’s include the 74LS174 HEX
D flip-flop with direct clear input, the 74LS175 Quad D flip-flop with complementary outputs and the 74LS273
Octal D-type flip flop containing eight D-type flip flops with a clear input in one single package.
74LS74 Dual D-type Flip Flop

Other Popular D-type flip-flop ICs

Device Number Subfamily Device Description

74LS74 LS TTL Dual D-type Flip Flops with Preset and Clear

74LS175 LS TTL Quad D-type Flip Flops with Clear

74LS273 LS TTL Octal D-type Flip Flops with Clear

4013B Standard CMOS Dual type D Flip Flop

40174B Standard CMOS Hex D-type Flip Flop with Master Reset

Using The D-type Flip Flop For Frequency Division

One main use of a D-type flip flop is as a Frequency Divider. If the Q output on a D-type flip-flop is connected
directly to the D input giving the device closed loop “feedback”, successive clock pulses will make the bistable
“toggle” once every two clock cycles.

In the counters tutorials we saw how the Data Latch can be used as a “Binary Divider”, or a “Frequency Divider”
to produce a “divide-by-2″ counter circuit, that is, the output has half the frequency of the clock pulses. By
placing a feedback loop around the D-type flip flop another type of flip-flop circuit can be constructed called a
T-type flip-flop or more commonly a T-type bistable, that can be used as a divide-by-two circuit in binary
counters as shown below.

Divide-by-2 Counter
It can be seen from the frequency waveforms above, that by “feeding back” the output from Q to the input
terminal D, the output pulses at Q have a frequency that are exactly one half ( ƒ/2 ) that of the input clock
frequency, ( ƒIN ). In other words the circuit produces frequency division as it now divides the input frequency
by a factor of two (an octave) as Q = 1 once every two clock cycles.

D Flip Flops as Data Latches

As well as frequency division, another useful application of the D flip flop is as a Data Latch. A data latch can be
used as a device to hold or remember the data present on its data input, thereby acting a bit like a single bit
memory device and IC’s such as the TTL 74LS74 or the CMOS 4042 are available in Quad format exactly for this
purpose. By connecting together four, 1-bit data latches so that all their clock inputs are connected together
and are “clocked” at the same time, a simple “4-bit” Data latch can be made as shown below.

4-bit Data Latch

Transparent Data Latch

The Data Latch is a very useful device in electronic and computer circuits. They can be designed to have very
high output impedance at both outputs Q and its inverse or complement output Q to reduce the impedance
effect on the connecting circuit when used as a buffer, I/O port, bi-directional bus driver or even a display
driver.

But a single “1-bit” data latch is not very practical to use on its own and instead commercially available IC’s
incorporate 4, 8, 10, 16 or even 32 individual data latches into one single IC package, and one such IC device is
the 74LS373 Octal D-type transparent latch.
The eight individual data latches or bistables of the 74LS373 are “transparent” D-type flip-flops, meaning that
when the clock (CLK) input is HIGH at logic level “1”, (but can also be active low) the outputs at Q follows the
data D inputs.
In this configuration the latch is said to be “open” and the path from D input to Q output appears to be
“transparent” as the data flows through it unimpeded, hence the name transparent latch.
When the clock signal is LOW at logic level “0”, the latch “closes” and the output at Q is latched at the last
value of the data that was present before the clock signal changed and no longer changes in response to D.
8-bit Data Latch

Functional diagram of the 74LS373 Octal Transparent Latch

The D-type Flip Flop Summary

The data or D-type Flip Flop can be built using a pair of back-to-back SR latches and connecting an inverter
(NOT Gate) between the S and the R inputs to allow for a single D (data) input. The basic D flip flop circuit can
be improved further by adding a second SR flip-flop to its output that is activated on the complementary clock
signal to produce a “Master-Slave D flip-flop” device.
The difference between a D-type latch and a D-type flip-flop is that a latch does not have a clock signal to
change state whereas a flip-flop always does. The D flip-flop is an edge triggered device which transfers input
data to Q on clock rising or falling edge. Data Latches are level sensitive devices such as the data latch and the
transparent latch.
In the next tutorial about Sequential Logic Circuits, we will look at connecting together data latches to produce
another type of sequential logic circuit called a Shift Register that are used to convert parallel data into serial
data and vice versa.

The JK Flip Flop

From the previous tutorial we now know that the basic gated SR NAND flip flop suffers from two basic
problems: number one, the S = 0 and R = 0 condition (S = R = 0) must always be avoided, and number two, if S
or R change state while the enable input is high the correct latching action may not occur. Then to overcome
these two fundamental design problems with the SR flip-flop design, the JK flip Flop was developed.
This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a universal
flip-flop circuit. The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop
with the same “Set” and “Reset” inputs. The difference this time is that the “JK flip flop” has no invalid or
forbidden input states of the SR Latch even when S and R are both at logic “1”.
The JK flip flop is basically a gated with the addition of a clock input circuitry that prevents the illegal or invalid
output condition that can occur when both inputs S and R are equal to logic level “1”. Due to this additional
clocked input, a JK flip-flop has four possible input combinations, “logic 1″, “logic 0″, “no change” and “toggle”.
The symbol for a JK flip flop is similar to that of an SR Bistable Latch as seen in the previous tutorial except for
the addition of a clock input.

The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called the J and K
inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input NAND gates with
the third input of each gate connected to the outputs at Q and Q. This cross coupling of the SR flip-flop allows
the previously invalid condition of S = “1” and R = “1” state to be used to produce a “toggle action” as the two
inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the lower NAND gate. If the
circuit is “RESET” the K input is inhibited by the “0” status of Q through the upper NAND gate. As Q and Q are
always different we can use them to control the input. When both inputs J and K are equal to logic “1”, the JK
flip flop toggles as shown in the following truth table.

The Truth Table for the JK Function

Input Output
Description
J K Q Q

0 0 0 0 Memory
same as
0 0 0 1 no change
for the
SR Latch 0 1 1 0
Reset Q » 0
0 1 0 1

1 0 0 1
Set Q » 1
1 0 1 0

toggle 1 1 0 1
Toggle
action 1 1 1 0

Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its two input terminals,
either SET or RESET to be active at any one time thereby eliminating the invalid condition seen previously in the
SR flip flop circuit. Also when both the J and the K inputs are at logic level “1” at the same time, and the clock
input is pulsed either “HIGH”, the circuit will “toggle” from its SET state to a RESET state, or visa-versa. This
results in the JK flip flop acting more like a T-type toggle flip-flop when both terminals are “HIGH”.
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing problems called
“race” if the output Q changes state before the timing pulse of the clock input has time to go “OFF”. To avoid
this the timing pulse period ( T ) must be kept as short as possible (high frequency). As this is sometimes not
possible with modern TTL IC’s the much improved Master-Slave JK Flip-flop was developed.
The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops connected together in a
series configuration. One flip-flop acts as the “Master” circuit, which triggers on the leading edge of the clock
pulse while the other acts as the “Slave” circuit, which triggers on the falling edge of the clock pulse. This
results in the two sections, the master section and the slave section being enabled during opposite half-cycles
of the clock signal.
The TTL 74LS73 is a Dual JK flip-flop IC, which contains two individual JK type bistable’s within a single chip
enabling single or master-slave toggle flip-flops to be made. Other JK flip flop IC’s include the 74LS107 Dual JK
flip-flop with clear, the 74LS109 Dual positive-edge triggered JK flip flop and the 74LS112 Dual negative-edge
triggered flip-flop with both preset and clear inputs.

Dual JK Flip-flop 74LS73

Other Popular JK Flip-flop ICs

Device Number Subfamily Device Description

74LS73 LS TTL Dual JK-type Flip Flops with Clear

74LS76 LS TTL Dual JK-type Flip Flops with Preset and Clear

74LS107 LS TTL Dual JK-type Flip Flops with Clear

4027B Standard CMOS Dual JK-type Flip Flop

The Master-Slave JK Flip-flop

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with
the slave having an inverted clock pulse. The outputs from Q and Q from the “Slave” flip-flop are fed back to
the inputs of the “Master” with the outputs of the “Master” flip flop being connected to the two inputs of the
“Slave” flip flop. This feedback configuration from the slave’s output to the master’s input gives the
characteristic toggle of the JK flip flop as shown below.

The Master-Slave JK Flip Flop

The input signals J and K are connected to the gated “master” SR flip flop which “locks” the input condition
while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of the “slave” flip flop is the inverse
(complement) of the “master” clock input, the “slave” SR flip flop does not toggle. The outputs from the
“master” flip flop are only “seen” by the gated “slave” flip flop when the clock input goes “LOW” to logic level
“0”.
When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional changes to its
inputs are ignored. The gated “slave” flip flop now responds to the state of its inputs passed over by the
“master” section.
Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are fed through to
the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the same inputs are reflected on
the output of the “slave” making this type of flip flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on the
falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only
passes data with the timing of the clock signal.
In the next tutorial about Sequential Logic Circuits, we will look at Multivibrators that are used as waveform
generators to produce the clock signals to switch sequential circuits.

The Shift Register

The Shift Register is another type of sequential logic circuit that can be used for the storage or the transfer of
data in the form of binary numbers. This sequential device loads the data present on its inputs and then moves
or “shifts” it to its output once every clock cycle, hence the name “shift register”.
A shift register basically consists of several single bit “D-Type Data Latches”, one for each data bit, either a logic
“0” or a “1”, connected together in a serial type daisy-chain arrangement so that the output from one data
latch becomes the input of the next latch and so on.
Data bits may be fed in or out of a shift register serially, that is one after the other from either the left or the
right direction, or all together at the same time in a parallel configuration.
The number of individual data latches required to make up a single Shift Register device is usually determined
by the number of bits to be stored with the most common being 8-bits (one byte) wide constructed from eight
individual data latches.
Shift Registers are used for data storage or for the movement of data and are therefore commonly used inside
calculators or computers to store data such as two binary numbers before they are added together, or to
convert the data from either a serial to parallel or parallel to serial format. The individual data latches that
make up a single shift register are all driven by a common clock ( Clk ) signal making them synchronous devices.
Shift register IC’s are generally provided with a clear or reset connection so that they can be “SET” or “RESET”
as required. Generally, shift registers operate in one of four different modes with the basic movement of data
through a shift register being:
• Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the stored data
being available at the output in parallel form.
• Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register, one bit at a time in
either a left or right direction under clock control.
• Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously and is shifted out
of the register serially one bit at a time under clock control.
• Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the register, and transferred
together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can be presented graphically as:

Also, the directional movement of the data through a shift register can be either to the left, (left shifting) to the
right, (right shifting) left-in but right-out, (rotation) or both left and right shifting within the same register
thereby making it bidirectional. In this tutorial it is assumed that all the data shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been RESET ( CLEAR
input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and
therefore the resulting QA will be set HIGH to logic “1” with all the other outputs still remaining LOW at logic
“0”. Assume now that the DATA input pin of FFA has returned LOW again to logic “0” giving us one data pulse
or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output of FFB and QB HIGH to logic
“1” as its input D has the logic “1” level on it from QA. The logic “1” has now moved or been “shifted” one place
along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so on until the
arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level “0” because the
input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is
shown in the following table until the complete data value of 0-0-0-1 is stored in the register. This data value
can now be read directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output. The truth table and
following waveforms show the propagation of the logic “1” through the register from left to right as follows.

Basic Data Movement Through A Shift Register

Clock Pulse No QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the register and will
remain there provided clocking of the register has stopped. In practice the input data to the register may
consist of various combinations of logic “1” and “0”. Commonly available SIPO IC’s include the standard 8-bit
74LS164 or the 74LS594.

Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was read directly in a parallel
form from the outputs QA to QD, this time the data is allowed to flow straight through the register and out of
the other end. Since there is only one output, the DATA leaves the shift register one bit at a time in a serial
pattern, hence the name Serial-in to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three connections, the
serial input (SI) which determines what enters the left hand flip-flop, the serial output (SO) which is taken from
the output of the right hand flip-flop and the sequencing clock signal (Clk). The logic circuit diagram below
shows a generalized serial-in serial-out shift register.

4-bit Serial-in to Serial-out Shift Register

You may think what’s the point of a SISO shift register if the output data is exactly the same as the input data.
Well this type of Shift Register also acts as a temporary storage device or as a time delay device for the data,
with the amount of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by
varying the application of the clock pulses. Commonly available IC’s include the 74HC595 8-bit Serial-in to
Serial-out Shift Register all with 3-state outputs.

Parallel-in to Serial-out (PISO) Shift Register

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one above. The
data is loaded into the register in a parallel format in which all the data bits enter their inputs simultaneously,
to the parallel input pins PA to PD of the register. The data is then read out sequentially in the normal shift-
right mode from the register at Q representing the data present at PA to PD.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important to note that with
this type of data register a clock pulse is not required to parallel load the register as it is already present, but
four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial format, it can be used
to multiplex many different input lines into a single serial DATA stream which can be sent directly to a
computer or transmitted over a communications line. Commonly available IC’s include the 74HC166 8-bit
Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift register also acts as
a temporary storage device or as a time delay device similar to the SISO configuration above. The data is
presented in a parallel format to the parallel input pins PA to PD and then transferred together directly to their
respective output pins QA to QA by the same clock pulse. Then one clock pulse loads and unloads the register.
This arrangement for parallel loading and unloading is shown below.
4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three connections, the parallel
input (PI) which determines what enters the flip-flop, the parallel output (PO) and the sequencing clock signal
(Clk).
Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary storage device or
as a time delay device, with the amount of time delay being varied by the frequency of the clock pulses. Also, in
this type of register there are no interconnections between the individual flip-flops since no serial shifting of
the data is required.

Universal Shift Register

Today, there are many high speed bi-directional “universal” type Shift Registers available such as the TTL
74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-function devices that can be used in
either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial, or as a parallel-to-parallel
multifunction data register, hence the name “Universal”.
These universal shift registers can perform any combination of parallel and serial input to output operations
but require additional inputs to specify desired function and to pre-load and reset the device. A commonly
used universal shift register is the TTL 74LS194 as shown below.

4-bit Universal Shift Register 74LS194

Universal shift registers are very useful digital devices. They can be configured to respond to operations that
require some form of temporary memory storage or for the delay of information such as the SISO or PIPO
configuration modes or transfer data from one point to another in either a serial or parallel format. Universal
shift registers are frequently used in arithmetic operations to shift data to the left or right for multiplication or
division.
Shift Register Tutorial Summary
Then to summarise a little about Shift Registers
• A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data bit.
• The output from each flip-Flop is connected to the D input of the flip-flop at its right.
• Shift registers hold the data in their memory which is moved or “shifted” to their required positions on
each clock pulse.
• Each clock pulse shifts the contents of the register one bit position to either the left or the right.
• The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded
simultaneously in a parallel configuration (PI).
• Data may be removed from the register one bit at a time for a series output (SO) or removed all at the
same time from a parallel output (PO).
• One application of shift registers is in the conversion of data between serial and parallel, or parallel to
serial.
• Shift registers are identified individually as SIPO, SISO, PISO, PIPO, or as a Universal Shift Register with
all the functions combined within a single device.

The example of sequential logic design:

Counter with non-binary sequence with JK type Flip-Flop:
000 → 001 → 010 → 100 → 101 → 110 and back to 000

Truth Table for JK type Flip-Flop

J K Qt+1
0 0 Qt

1 0 1

0 1 0

1 1 Qt

We derive JK inputs by truth table above:

Present Next
state state Flip-flop inputs
A B C A+ B+ C+ JA KA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X

Now we will minimize functions for JA, JB, JC, KA, KB, KC by using Karnaugh Map.
 B
JA: A → JA = B

0 X X 1

C 0 X X X

B
JB: A → JB = C

0 0 X X

C 1 1 X X

B
JC: A → JC = B\ (NON B)

1 1 0 0

C X X X X

B
A → KA = B
KA:

X 0 1 X

C X 0 X X

B
A
KB: → KB = 1

X X 1 1

C X X X X

B
A
KC: → KC = 1

X X X X

C 1 1 X X

The resulting connection and its behavior is shown below.

CP

t
C

B t

A t

ABC ABC ABC ABC ABC ABC ABC t

000 001 010 100 101 110 000