RNS INSTITUTE OF TECHNOLOGY

Dr. VISHNUVARDHAN ROAD, CHANNASANDRA, BENGALURU - 560 098

Department of Electronics &

Communication Engineering

VLSI LABORATORY MANUAL

VII Semester
15ECL77

Faculty-in-charge
Mrs. Sangeetha B G
Mrs. Ibrar Jahan

RNS INSTITUTE OF TECHNOLOGY

Dr. VISHNUVARDHAN ROAD, CHANNASANDRA, BENGALURU -560 098
 Department of Electronics and Communication
Engineering

VISION of the College

Building RNSIT into a World - Class Institution

MISSION of the College

To impart high quality education in Engineering, Technology and Management with a

difference, enabling students to excel in their career by

1. Attracting quality Students and preparing them with a strong foundation in fundamentals
so as to achieve distinctions in various walks of life leading to outstanding contributions.
2. Imparting value based, need based, and choice based and skill based professional
education to the aspiring youth and carving them into disciplined, World class
Professionals with social responsibility.
3. Promoting excellence in Teaching, Research and Consultancy that galvanizes academic
consciousness among Faculty and Students.
4. Exposing Students to emerging frontiers of knowledge in various domains and make them
suitable for Industry, Entrepreneurship, Higher studies, and Research & Development.
5. Providing freedom of action and choice for all the Stake holders with better visibility.

VISION of the Department

Conquering technical frontiers in the field of Electronics and Communications

MISSION of the Department

1. To achieve and foster excellence in core Electronics and Communication engineering

with focus on the hardware, simulation and design.
2. To pursue Research, development and consultancy to achieve self sustenance.
3. To create benchmark standards in electronics and communication engineering by active
involvement of all stakeholders.
 PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

ISE Graduates within three-four years of graduation will have

• PEO1: Acquired the fundamentals of computers and applied knowledge of
Information Science & Engineering and continue to develop their technical
competencies by problem solving using programming.
• PEO2: Ability to formulate problems attained the Proficiency to develop
system/application software in a scalable and robust manner with various platforms,
tools and frameworks to provide cost effective solutions.
• PEO3: Obtained the capacity to investigate the necessities of the software Product,
adapt to technological advancement, promote collaboration and interdisciplinary
activities, Protecting Environment and developing Comprehensive leadership.
• PEO4: Enabled to be employed and provide innovative solutions to real-world
problems across different domains.
• PEO5: Possessed communication skills, ability to work in teams, professional ethics,
social responsibility, entrepreneur and management, to achieve higher career goals,
and pursue higher studies.

PROGRAM OUTCOMES (POs)

Engineering Graduates will be able to:

 PO1: Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization for the solution of
complex engineering problems
 PO2: Problem analysis: Identify, formulate, research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences and engineering sciences.
 PO3: Design/development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs
with appropriate consideration for public health and safety, and cultural, societal, and
environmental considerations.
 PO4: Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid conclusions.
 PO5: Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools, including prediction and modeling
to complex engineering activities, with an understanding of the limitations.
 PO6: The engineer and society: Apply reasoning informed by the contextual
knowledge to assess Societal, health, safety, legal and cultural issues and the
 consequent responsibilities relevant to the professional engineering practice.
 PO7: Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
 PO8: Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
 PO9: Individual and team work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
 PO10: Communication: Communicate effectively on complex engineering
activities with the engineering community and with the society at large, such as,
being able to comprehend and write effective reports and design documentation,
make effective presentations, and give and receive clear instructions.
 PO11: Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these to
one’s own work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.
 PO12: Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest context of
technological change.

PROGRAM SPECIFIC OUTCOMES (PSOs)

ECE Graduates will have

 PSO1: Apply fundamental knowledge of Electronics, Communications, Signal
processing, VLSI, Embedded and Control systems etc., in the analysis, design, and
development of various types of real-time integrated electronic systems and to
synthesize and interpret the experimental data leading to valid conclusions.
 PSO2: Demonstrate competence in using Modern hardware languages and IT tools
for the design and analysis of complex electronic systems as per industry standards
along with analytical and managerial skills to arrive at appropriate solutions, either
independently or in team.
 RNS INSTITUTE OF TECHNOLOGY
Dr. VISHNUVARDHAN ROAD, CHANNASANDRA, BENGALURU -560 098

Department of Electronics and Communication

Engineering
VLSI Laboratory
Subject Code: 15ECL77 Total Hours: 40
Hours/Week: 01I + 2P Exam Hours: 03
Subject Code 15ECL77
I.A. Marks 20
Exam Marks 80
Course objectives:
This course will enable students to:
 Explore the CAD tool and understand the flow of the Full Custom IC design
cycle.
 Learn DRC, LVS and Parasitic Extraction of the various designs.
 Design and simulate the various basic CMOS analog circuits and use them in
higher circuits like data converters using design abstraction concepts.
 Design and simulate the various basic CMOS digital circuits and use them in
higher.

Course Outcomes
After studying this course, students will be able to:
CO1 Write test bench to simulate various digital circuits.
CO2 Realize shift registers and adders to meet desired parameters using basic gates.
CO3 Understand the flow of the Full Custom IC design cycle by exploring the CAD tool.
CO4 Interpret concepts of DC Analysis, AC Analysis and Transient Analysis in analog circuits.
Simulate basic CMOS circuits like inverter, common source amplifier and differential
CO5
amplifiers.
Functional verification of operational amplifier and analog/digital converters to meet desired
CO6
parameters using basic amplifiers.

CO mapping to PO/PSOs
CO /
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
PO & PSO
15ECL77.1 1 2 1 2 2
15ECL77.2 1 1 1 2 1 2 2
15ECL77.3 1 1 2 1 2 3
15ECL77.4 1 2 1 2 3
15ECL77.5 1 1 2 1 1 3
15ECL77.6 1 2 1 1 3
 VLSI Laboratory
Subject Code: 15ECL77 Total Hours: 40
Hours/Week: 01I + 2P Exam Hours: 03
Subject Code 15CSL38
I.A. Marks 20
Exam Marks 80

List of Programs
Sl. No Name of Experiment CO
PART - A
ASIC-DIGITAL DESIGN
1 Write Verilog Code for the following circuits and their Test
Bench for verification, observe the waveform and synthesize
the code with technological library with given constraints*.
Do the initial timing verification with gate level simulation.
i. An inverter
ii. A Buffer CO1
iii. Transmission Gate
iv. Basic/universal gates
v. Flip flop -RS, D, JK, MS, T
vi. Serial & Parallel adder
vii. 4-bit counter [Synchronous and Asynchronous counter]
viii. Successive approximation register [SAR]
PART - A
ASIC-ANALOG DESIGN
1 Design an Inverter with given specifications**, completing
the design flow
mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) Transient Analysis CO1
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the
Design
e. Verify & Optimize for Time, Power and Area to the given
constraint*
2 Design the (i) Common source and Common Drain amplifier
and (ii) A Single
Stage differential amplifier, with given specifications**,
completing the
design flow mentioned below: CO2
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
 c. Check for LVS
d. Extract RC and back annotate the same and verify the
Design.
3 Design an op-amp with given specification** using given
differential amplifier Common source and Common Drain
amplifier in library*** and completing the design flow
mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis CO4
ii). AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the
Design.
4 Design a 4 bit R-2R based DAC for the given specification
and completing the design flow mentioned using given op-
amp in the library***.
a. Draw the schematic and verify the following CO4
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
5 For the SAR based ADC mentioned in the figure below draw
the mixed signal schematic and verify the functionality by
completing ASIC Design FLOW.
[Specifications to GDS-II]

CO2
 VLSI Laboratory
Evaluation Rubrics

Subject Code: 15ECL77 I.A. Marks : 20

Hours/Week: 01I+2P Exam Hours: 03
Total Hours: 40 Exam Marks: 80

Lab Write-up and Execution Rubrics (Max: 10 marks)

Above Average Average Below Average

Understanding of
Able to analyze the Able to analyze the
design and Poor understanding
given design and design and moderate
a. approach to of design or tool.
efficiently implement understanding of tool.
solve. (1-0)
using Cadence tool. (4) (3-2)
(4 Marks)
Design executed for
Design has errors
specified inputs with Design is executed
Execution and or no Execution
valid results and able to for some inputs and
b. Viva (5 questions) and not answered
answer all five able to answer three-
(2 Marks) any questions.
questions two questions. (1)
(0)
appropriately. (2)
Obtained results for Obtained results for No Proper results
Results and
respective design are respective design is and poor
c. Documentation
legibly written / acceptably documentation.
(4 Marks)
documented. (4) documented. (3-2) (1-0)

LAB Internal Assessment rubrics (Max: 10 marks)

Above Average Average Below Average

Able to write the Able to write the
Write-up Unable to write.
a. complete design. design with few
(3 Marks) (1-0)
(3) errors. (2-1)
Executed
successfully for Obtained partially Program has compilation
Execution
b. all the correct results. errors or No Execution.
(5 Marks)
specification (3-2) (1-0)
given. (5)
Able to answer all
Viva (5 questions) Able to answer three-
c. five questions Not answered any. (0)
(2 Marks) two questions. (1)
correctly. (2)
 PART -A

Getting Started
Cadence can be run only on Unix terminals or PCs loaded with Linux (or UnixTerminal
emulators) and X Windows servers like Exceed, X-Win32, or Xfree (Linux). BeforeStarting
the Cadence, there are a few configuration files that are needed in the home Working
directory. These files determine the environment in which Cadence runs, what libraries are to
be included in the current session, etc. These files are in "cshrc" file in the user directory of
"cadence". A work directory has been created for each user when cadence is to be used, so that
all the files generated by Cadence user will be creating their directory locally. Ex.: (you’re
U.S.N. No.)". This will store the Cadence work Environment and files for the present user
only. To For sourcing the script file, c-shell is used.
 csh
 source /cad/cshrc
 cd Cadence_digital_labs
 mkdir USN_no [Create folder for storing your digital experiments]
 cd USN_no
 vi inv.v [Create a verilog files in vi editor]
 vi inv_test.v [Create a verilog testbench files in vi editor]
 ncvlog inv_test.v –mess
 ncvlog inv_test.v –mess [To compile your verilog and textbench code]
 ncelab inv_test-access +rwc –mess [To elaborate your testbench code]
 ncsim inv_test –gui [To simulate your testbench code]

Close console window

 rc –gui –logfile inv.log [To synthesis your verilog code]

After this command you will get two windows:

1. Command Window 2. Graphical Window

Command Window
 Graphical Window
Note: You have to work in command window

 set_attr hdl_search_path {../rnsit}

 set_attr lib_search_path {../rnsit}
 set_attr library slow_highvt.lib
 read_hdl inv.v
 elaborate
 synthesize –to_mapped –effort high
 report power
 report timing
 report area
 gui _show
 EXPERIMENT 1: INVERTER
Aim: To write the verilog code for CMOS Inverter and write the test bench for the same to
verify and observe the waveform.

Circuit Diagram:

//Verilog code //Test bench

module inverter(vout,vin); module invertertest;

input vin; reg vin;
output vout; wire vout;
supply1 vdd; inverter i1(vout,vin);
supply0 gnd; initial
pmos p1(vout,vdd,vin); begin
nmos n1(vout,gnd,vin); vin=1'b0;
endmodule #10 vin=1'b1;
#10 vin=1'b0;
#10 vin=1'b1;
#10;
end
endmodule
Output Waveform:
 EXPERIMENT 2: BUFFER
Aim: To write the verilog code for buffer and write the test bench for the same to verify and
observe the waveform.

Circuit Diagram:

//Verilog code //Test bench

module buffer(y,a); module buffertest;

input a; reg a;
output y; wire y;
wire w; buffer b1(y,a);
supply1 vdd; initial
supply0 gnd; begin
pmos p1(w,vdd,a); a=1'b1;
nmos n1(w,gnd,a); #10 a=1'b0;
pmos p2(y,vdd,w); #10 a=1'b1;
nmos n2(y,gnd,w); #10 a=1'b0;
endmodule #10;
end
endmodule

With Inverter Instantiation

//Verilog code //Test bench

module buffer(y,a); module buffertest;

input a; reg a;
output y; wire y;
wire w1; buffer b1(y,a);
inverter i1(w1,a); initial
inverter i2(y,w1); begin
endmodule a=1'b0;
#10 a=1'b1;
#10 a=1'b0;
#10 a=1'b1;
#10;
end
endmodule
Output Waveform:
 EXPERIMENT 3: TRANSMISSION GATE
Aim: To write the verilog code for transmission gate and write the test bench for the same to
verify and observe the waveform.

Circuit Diagram:

//Verilog code //Test bench

module tg(in,out,s,sbar); module tgtest;

input in,s,sbar; reg in,s,sbar;
output out; wire out;
pmos p1(out,in,sbar); tg t1(in,out,s,sbar);
nmos n1(out,in,s); initial
endmodule begin
s=1'b1;
sbar=1'b0;
in=1'b0;
#10in=1'b1;
#10in=1'b0;
#10s=1'b0;
sbar=1'b1;
in=1'b1;
#10in=1'b0;
#10;
end
endmodule
Output Waveform:
 EXPERIMENT 4: LOGIC GATES
Aim: To write the verilog code for logic gates and write the test bench for the same to verify
and observe the waveform and synthesize the code.

Circuit Diagram:

Black Box Boolean Expression Logic Circuit

//Verilog code //Test bench

module logic(a,b,f1,f2,f3,f4,f5,f6); module logictest;

input a,b; reg a,b;
output f1,f2,f3,f4,f5,f6; wire f1,f2,f3,f4,f5,f6;
assign f1=a&b; logic l1(a,b,f1,f2,f3,f4,f5,f6);
assign f2=a|b; initial
assign f3=~a; begin
assign f4=~(a|b); a=1'b0;
assign f5=~(a&b); b=1'b0;
assign f6=a^b; #10 b=1'b1;
endmodule #10 a=1'b1;
b=1'b0;
#10 b=1'b1;
#10;
end
endmodule
Output Waveform:
 EXPERIMENT 5: FLIP-FLOPS
Aim: To write the verilog code for flip-flops and write the test bench for the same to verify
and observe the waveform and synthesize the code.

1. SR FLIP-FLOP
Circuit Diagram:

Black Box Truth Table Circuit Diagram

//Verilog code //Test bench

module srff(s,r,clk,q,qb); module srfftest;

input s,r,clk; reg clk,s,r;
output q,qb; wire q,qb;
reg [1:0] sr; srff s1(s,r,clk,q,qb);
reg q,qb; initial
always @(posedge clk) begin
begin clk=1'b0;
sr={s,r}; end
case(sr) always
2'b00:q=q; #5 clk=~clk;
2'b01:q=1'b0; initial
2'b10:q=1'b1; begin
2'b11:q=1'bx; #10 s=1'b0;
endcase r=1'b1;
qb=~q; #10 s=1'b1;
end r=1'b0;
endmodule #15 s=1'b0;
r=1'b0;
#20 s=1'b1;
r=1'b1;
#20;
end
endmodule
Output Waveform:

2. D FLIP-FLOP

Black Box Truth Table

//Verilog code //Test bench

module dff(d,clk,q,qb); module dfftest;

input d,clk; reg clk,d;
output q,qb; wire q,qb;
reg q,qb; dff d1(d,clk,q,qb);
always@(posedge clk) initial
begin begin
q=d; clk = 1'b0;
qb=~d; end
end always
endmodule #5clk=~clk;
initial
begin
d=1'b0;
 #10d=1'b1;
#20d=1'b1;
#20d=1'b0;
#20;
end
endmodule

Output Waveform:

3. JK FLIP-FLOP
Black Box Truth Table
//Verilog code //Test bench

module jkff(j,k,clk,q,qb); module jkfftest;

input j,k,clk; reg j,k,clk;
output q,qb; wire q,qb;
reg[1:0] jk; jkff jk1(j,k,clk,q,qb);
reg q=0,qb=1; initial
always@(posedge clk) begin
begin clk=1'b0;
jk={j,k}; end
case (jk) always
2'b00:q=q; #5 clk=~clk;
2'b01:q=1'b0; initial
2'b10:q=1'b1; begin
2'b11:q=~q; j=1'b0;
endcase k=1'b0;
qb=~q; #5 j=1'b0;
end #10 k=1'b1;
endmodule #5 j=1'b1;
#5 k=1'b0;
#5 j=1'b1;
#5 k=1'b1;
#20;
end
endmodule

Output Waveform:
 4. T FLIP-FLOP
Black Box Truth Table

//Verilog code //Test bench

module tff(clk,t,q,qb); module tfftest;

input clk,t; reg clk,t;
output q,qb; wire q,qb;
reg q=0,qb=1; tff t1(clk,t,q,qb);
always @(posedge clk) initial
begin begin
clk=1'b0;
if (t==0) end
q=q; always
else #5 clk=~clk;
q=~q; initial
qb=~q; begin
end t=1'b0;
endmodule #10 t=1'b1;
#20 t=1'b1;
#20 t=1'b0;
#20;
end
endmodule

Output Waveform:
 EXPERIMENT 6: ADDERS
Aim: To write the verilog code for serial and parallel adder write the test bench for the same
to verify and observe the waveform and synthesize the code.

1. PARALLEL ADDER

Circuit Diagram:

//Verilog code //Test bench

// Full Adder module patest;

reg [3:0]a,b;
module fa(a,b,cin,sum,cout); reg cin=1'b0;
input a,b,cin; wire cout;
output sum; wire [3:0]s;
pa p1(a,b,cin,s,cout);
output cout;
initial
assign sum=(a^b)^cin; begin
assign cout=((a&b)|(b&cin)|(cin&a)); a=4'b0;
endmodule b=4'b0;
#10 a=4'd1;
// Parallel Adder b=4'd2;
#20 a=4'd9;
module pa(a,b,cin,s,cout); b=4'd3;
input [3:0]a,b; #10 a=4'd9;
input cin; b=4'd7;
output [3:0]s; #10;
output cout; end
wire [2:0]c; endmodule
fa f1(a[0],b[0],cin,s[0],c[0]);
fa f2(a[1],b[1],c[0],s[1],c[1]);
fa f3(a[2],b[2],c[1],s[2],c[2]);
fa f4(a[3],b[3],c[2],s[3],cout);
endmodule
Output Waveform:

2. SERIAL ADDER

Circuit Diagram:

//Verilog code //Test bench

module serial (clk,reset,paload,pbload, module serialtest;

pout,adata,bdata,enable); reg clk,reset,paload,pbload,enable;
input clk,reset; reg[7:0] adata,bdata;
input paload,pbload,enable; wire[7:0] pout;
input[7:0] adata,bdata; serial
output[7:0] pout; s1(clk,reset,paload,pbload,pout,adata,bdata,enable);
wire sum,carry; initial
reg hcarry; begin
reg[7:0] shifta,shiftb,shiftc=8'b0; clk=1'b0;
reg shiftalsb,shiftblsb; end
always@(posedge clk) always
begin #5 clk=~clk;
if(paload) initial
shifta=adata; begin
else if(enable) reset=1'b1;
begin #5 reset=1'b0;
shiftalsb=shifta[0]; paload=1'b1;
shifta=shifta>>1; pbload=1'b1;
shifta[7]=shiftalsb; #5 adata=8'b10001001;
end bdata=8'b10001001;
 #10 paload=1'b0;
if(pbload) pbload=1'b0;
shiftb=bdata; enable=1'b1;
else if(enable) #80 enable=1'b0;
begin end
shiftblsb=shiftb[0]; endmodule
shiftb=shiftb>>1;
shiftb[7]=shiftblsb;
end

if(enable)
begin
shiftc=shiftc>>1;
if(sum)
shiftc[7]=sum;
else shiftc[7]=1'b0;
end
end

assign pout=shiftc;
fa f1
(shifta[0],shiftb[0],hcarry,sum,cout);

always@(posedge clk)
begin
if(reset)
hcarry=1'b0;
else if(enable)
hcarry=cout;
else
hcarry=hcarry;
end
endmodule
Output Waveform:
EXPERIMENT 7: COUNTERS
Aim: To write the verilog code for synchronous and asynchronous counter write the test
bench for the same to verify and observe the waveform and synthesize the code.

1. ASYNCHRONOUS COUNTER

//Verilog code //Test bench

module async(clk,q); module asynctest;

input clk; reg clk;
output q; wire [3:0]q;
reg [3:0]q; async a1(clk,q);
initial initial
q=4'b1111; begin
always @(negedge clk) clk=1'b0;
q[0]=~q[0]; end
always @(negedge q[0]) always
q[1]=~q[1]; #5 clk=~clk;
always @(negedge q[1]) endmodule
q[2]=~q[2];
always @(negedge q[2])
q[3]=~q[3];
endmodule

Output Waveform:
 2. SYNCHRONOUS COUNTER

//Verilog code //Test bench

module sync(clk,reset,q); module synctest;

input clk,reset; reg clk,reset;
output [3:0]q; wire [3:0]q;
reg [3:0]q; sync sc1(clk,reset,q);
always @(negedge clk) initial
if(reset) begin
q=4'b0; clk=1'b0;
else end
q=q+1; always
endmodule #5 clk=~clk;
initial
begin
reset=1'b1;
#10 reset=1'b0;
end
endmodule

Output Waveform:
Successive Approximation Register (SAR)
Verilog Code Testbench
module sar (R,L,E,W,clk,q); module sar_test;
parameter n=8; reg[7:0] r;
input [n-1:0] r; reg l,e,w,clk;
input L,E,W, clk; wire [7:0]q;
output [n-1:0] q; sar bb (R(r), L(l), E(e), W(w), clk(clk), q(q));
reg [n-1:0]; initial
integer k; begin
l=1’b1;
always @(posedge(clk)) e=1’b0;
begin r=8’b11110000;
if (L) clk = 1’b0;
q=R; #10 w=1’b1;
else if(R) l=1’b0;
begin e=1’b1;
for (k=n-1; k>0;k=k+1) #10 w= 1’b0;
q[k-1]<=q[k]; end
q[n-1] <=W; always @ clk = ~clk;
end endmodule
end
endmodule
 PART-B

INTRODUCTION TO VLSI LAB

VLSI lab allows the theoretical concepts studied as part of subjects CMOS VLSI
Design, Microelectronics Circuits and HDL, to experience in practical with the help of Cadence
tool framework. The lab introduces the complete custom IC design flow, ASIC design flow and
AMS (Analog and Mixed Signal) flow for Analog circuits, Digital circuits and Analog and
mixed signal circuits design respectively.

The analog design involves schematic (standard cell), test schematic capture and
symbolic representation of circuit topologies using Virtuoso schematic editor/ Composer.
Simulation of the test circuit to perform various analyses such as transient, DC and AC is
facilitated by Multimode Simulator/Spectre. Once the simulation results are obtained as per the
specifications the physical design is carried out using Virtuoso Layout suite followed by the
physical verification using Assura DRC (Design Rule Check), LVS (Layout Versus Schematic)
and Parasitic RC extraction. The floor planning, Power planning, placement and routing can be
performed later using Encounter.

The digital design involves the realization of various digital circuit components using
Register Transfer Logic (RTL) code, Compilation of the same using Native Compiler,
elaboration using elaborator and simulation using Incisive. The synthesis of the verified RTL
code to obtain the gate level netlist is performed thereon.

The AMS circuit design is performed by importing the digital modules as configuration
files into the analog environment, followed by the steps of the analog design and simulating the
same using AMS simulator instead of Spectre.

Introduction to Cadence Design Systems

Cadence is an Electronic Design Automation (EDA) environment which allows
different applications and tools to integrate into a single framework thus allowing supporting
all the stages of IC design and verification from a single environment. These tools are
completely general, supporting different fabrication technologies. When a particular
technology is selected, a set of configuration and technology-related files are employed for
customizing the cadence environment. This set of files is commonly referred to as a design
kit. The Cadence Development System consists of a bundle of software packages such as
schematic editors, simulators, and layout editors. This software manages the development
process for analog, digital, and mixed-mode circuits. In this lab, we will strictly use the tools
associated with analog circuit design and digital design. All the Cadence design tools are
managed by a software package called the Design Framework II. This program supervises a
common database which holds all circuit information including schematics, layouts, and
simulation data.

LINUX Operating System

Using the LINUX operating system is similar to using other operating systems such as DOS.
LINUX commands are issued to the system by typing them in a “shell”. LINUX commands
are case sensitive so be careful when issuing a command, usually they are given in lower-
case.

The following list summarizes all the basic commands required to manage the data
files you will be creating in this lab course. All LINUX commands are entered from the shell
window (Terminal window).

Caution: Do not use LINUX commands for modifying, deleting, or moving any Cadence
data files.
Table 1 Common LINUX commands
Commands Description
ls [-la] Lists files in the current directory. ”l” lists with properties and
“a” also lists hidden files (ones beginning with a “.”)
cd XXXX Changes the current directory to XXXX.
cd.. Changes the current directory back to one level.
cp XXXX YYYY Copies the file XXXX to YYYY
mv XXXX YYYY Moves file XXXX to YYYY. Also used for rename
rm XXXX Deletes the file XXXX
mkdir XXXX Creates the directory XXXX.
lp -dXXXX YYYY Prints the textfile or postscript file YYYY to the printer named
XXXX, where XXXX can be either “ipszac” or “hpszac”
Note: The command “&” tells LINUX to execute the command and return the prompt to the active shell.
 ANALOG DESIGN
Custom IC Design Flow

Specification/
Requirement
F
R
O Schematic
N
T
Symbol
E
N
D Back
Back Test Circuit Annotation
Annotation

Simulation

Layout Design
B
A
DRC
C
K
LVS E
N
D
RCX

GDS

Fig.1 Flow Diagram of Analog Design flow

Procedure for analog design

1. Login to your workstation using the username and password. The home directory has
a csh file with paths to the cadence installation.

2. In a terminal window, type csh at the command prompt to invoke C shell.

> csh
>source /cad /cshrc
>ls
In the terminal window, enter:
>virtuoso &
 The virtuoso or Command Interpreter Window (CIW) appears at the bottom of the
screen.

3. If the “What’s New…” window appears, close it with the File-Close command.
4. Keep opened CIW window for the labs.

Creating a new Library:

1. In the CIW window click on Tools-Library manager. The library manager

window will be opened.
2. Click File-New-Library. Specify the name for the new library. Click ok.
3. In the next “Technology File for New Library” form, select option Attach an
existing technology file and click ok.
4. In the “Attach Design Library to technology file” form, select gpdk180 from the
cyclic field and click ok
5. After creating a new library you can verify it from the Library manager.

Creating a Schematic Cellview:

1. In the CIW or Library manager, select the library created and execute File-New-
Cellview.
2. Setup the new file form.
3. Click ok. A blank schematic window for the design appears.

Adding Components to Schematics:

1. In the design window, click the create instance, fix menu icon to display add
instance form.
2. Click on the browse button. This opens up a library browser from which you can
select the components (gpdk180) and the symbol view (library created you).
3. After you complete the add instance form, move your cursor to the schematic
window and click left to place a component. If you place a component with wrong
parameter values, use the Edit-Properties-Objects command to change the
parameter. Use Edit-Move command if you place components in the wrong
location. You can rotate components using Edit-Rotate command.
4. After entering components, click cancel in the Add instance form or
press Esc.

Adding Pins to Schematic:

1.Click the Pin fixed menu icon in the schematic window

2.Make sure that the direction field is set to input/output/inout when placing the pins
respectively.
3.Select cancel from the Add-Pin form after placing the pins.
 Adding Wires to a Schematic:

1.Click the wire (narrow) icon in the schematic window.

2.In the schematic window, click on a pin of one of your components as the first point
for your wiring. A diamond shape appears over the starting point of this wire.
3.Follow the prompts at the bottom of the design window and click left on the
destination point for your wire. A wire is routed between the source and destination
points.
4.Complete the wiring as shown in figure and when done wiring press ESC key in the
schematic window to cancel wiring.
5.Click the Check and Save icon in the Schematic editor window.
6.Observe the CIW output area for any errors.

Symbol Creation:

1.In the schematic window, execute

Create -Cellview -From Cellview.
The Cellview form appears. With the Edit options function active, you can control
the appearance of the symbol to generate.
2.Verify that the From View Name field is set to schematic, and the To View Name
field is set to symbol, with the Tool/Data Type set as Schematic symbol. Click ok.
3.Modify the pin specification.
4.Click ok.

Editing a Symbol:

1. Move the cursor over the automatically generated symbol, until the green rectangle is
highlighted, click left to select it.
2. Click Delete icon in the symbol window, similarly select the red rectangle and delete
that.
3. Execute Create-Shape-Polygon.
4. After creating the shape press ESC key.
5. You can move the pin names according to the location.
6. Execute Create-Selection Box. In the Add Selection Box form, click Automatic. A
new red selection box is automatically added.
7. After creating symbol, click on the save icon in the symbol editor window to save the
symbol. In the symbol editor, execute File-Close to close the symbol view window.

Simulation with Spectre:

1. In the schematic window, execute Launch-ADE L

2. In Analog Design Environment (ADEL) window, Click the Choose- Analysis icon.
3. To setup for transient analysis select tran icon, click at the moderate or enabled
button at the bottom, click Apply.
4. To setup for DC analysis select dc, turn on Save DC Operating Point.
 Turn on the Component Parameter. Click the select Component, which takes you
to the schematic window. Select input signal, Vpulse or DC analysis.
Select start and stop voltages. Click Apply and ok.

Selecting outputs for plotting:

1. In Analog Design Environment (ADEL) window,

2. Execute Outputs- To be plotted- Select input and output line on Schematic in the
simulation window.
3. Follow the prompt at the bottom of the schematic window, click on the output net,
input net of the design. Press ESC with the cursor in the schematic after selecting
it.
4. Execute Simulation-Netlist and Run to start the simulation.

Saving and Loading Simulator State:

1. In the simulation window, execute Session- Save State. Set the Save as field and
click ok.
2. In the simulation window execute Session- Load State, set the state name and
click ok.

Creating a Layout View:

1. From the schematic window menu execute Launch- Layout XL. A startup Option
form appears.
2. Select Create New option.
3. Check the cell name, View name. Click ok.

Adding Components to Layout:

1. Execute Connectivity-Generate-All from Source. Generate Layout form appears.

Click ok, which imports the schematic components into the layout window
automatically.
2. Rearrange the components within PR boundary.
3. To rotate a component, select the component and execute Edit-Properties. Now
select the degree of rotation.
4. To move a component, select the component and execute Edit-Move command.

Making Interconnection:

1. Execute Connectivity-Nets-Show/Hide Selected incomplete nets.

2. Move the mouse pointer over the device and click LMB to get the connectivity
information, which shows the guidelines for the interconnections of the
components.
3. From the layout window execute Create-Shape-Path or Create-Shape-Rectangle
and select the appropriate layers from the LSW window and Vias for making
interconnections.

Creating Contacts/Vias:

1. Execute Create-Via to place different contacts as given in the table below.

Connection Contact
Type
For Metal1- Metal1-
Poly Poly
For Metal1- P Metal1-
substrate Psub
For Metal1- N Metal1-
Well Nwell
2.Save the design by selecting File-Save.

Running DRC:

1. Select Assura-Run DRC from Layout window. The DRC form appears. The
Library and cell name are taken from the current design window, but rule file may
be missing. Select the technology as gpdk180. This automatically loads the rule
file.
2. Click ok to start DRC. A progress form will appear. You can click on the watch
clock file to see the Log file.
3. When DRC finishes, a dialog box appears, Click Yes to view the results.
4. If there are any DRC error exits in the design View Layer Window (VLW) and
Error Layer Window (ELW) appears. Also the errors highlight in the design
itself.
5. Click View- Summary in the ELW to find the details of errors.
6. You can refer to rule file also for more information, correct all DRC errors and Re
– run the DRC.
7. If there are no errors in the layout then a dialog box appears with No DRC errors
found written in it, Click on close to terminate the DRC run.

ASSURA LVS:

1. Select Assura-Run LVS from the layout window. The Assura Run LVS form
appears, it will automatically load both the schematic and layout view of the cell.
2. Click OK. The LVS begins and a progress form appears.
3. If the schematic and layout matches completely, you will get the form displaying
Schematic and Layout Match.
4. If the schematic and Layout do not matches, a form informs that the LS completed
successfully and results form will appear, click YES in the form.
 5. In the LVS debug form, find the details of mismatches and correct all those
mismatches and Re-Run the LVS.

ASSURA RCX:

1. From the layout window execute Assura-Run RCX.

2. Change the Assura Parasitic Extraction form, select Output Type under Setup
tab of the form.
3. In the Extraction tab of the form, choose Extraction type (RC), Cap coupled
mode (coupled) and specify the reference node for extraction.
4. In the filtering tab of the form, Enter Power Nets as Vdd!, Vss! and Enter
Ground Nets as gnd!
5. Click ok. The RCX progress form appears, in the progress form click Watch log
file to see the output log file.
6. When RCX completes, a dialog box appears, shows Assura RCX Run completed
successfully.
7. Open the av_extracted view from the Library manager and view the parasitic.

Configuration View:

1. In the CIW or Library manager, execute File-New-Cell view.

2. Click ok in Create New File form. The Hierarchy editor form opens and a New
Configuration form opens in front of it.
3. Click Use template at the bottom of the New Configuration form and select
Spectre in the cyclic field and click ok.
4. Change the Top Cell view to schematic and remove the default entry from the
Library List field.
5. Click ok. The Hierarchy editor displays the Hierarchy for the design using table
format.
6. Click the Tree View tab. The Design hierarchy changes to Tree format. Save the
current configuration.
7. Close the Hierarchy window, execute File-Close window.

To run the circuit without parasitics:

1. From the Library manager open cell config view.

2. In the form, turn on the both cyclic buttons to Yes and click ok.
3. Execute Launch-ADE L from the schematic window.
4. Follow the same procedure for running the simulation. Execute Session-Load
state.
5. Click Netlist and Run icon to start the simulation.
6. In the CIW, note the netlisting statistics in the circuit inventory section. This list
includes all nets, design devices, source and loads. There are no parasitic
components.

Measuring the Propagation Delay without parasitics:

1. In the waveform window execute Tools-Calculator.

 2. From the functions select delay, this will open the delay data panel.
3. Place the cursor in the text box for signal1, select the wave button and select the
input waveform from the waveform window.
4. Repeat the same for signal2, select the output form.
5. Set the Threshold value1 (vdd/2) and Threshold value2 (vdd/2).
6. Execute ok and observe the expression created in the calculator.
7. Click on Evaluate the Buffer icon to perform the calculation. Close calculator
window.

To run the circuit with parasitics:

1. From the Library manager open cell config view.

2. In the form, turn on the both cyclic buttons to Yes and click ok.
3. Click the Tree View tab. The Design hierarchy changes to Tree format.
4. Right click on Io, set instance view, select av_extracted, and Click Recompute
the hierarchy and Save the current configuration.
5. Close the Hierarchy window, execute File-Close window.
6. Execute Launch-ADE L from the schematic window.
7. Follow the same procedure for running the simulation. Execute Session-Load
state.
8. Click Netlist and Run icon to start the simulation.
9. In the CIW, note the netlisting statistics in the circuit inventory section. This list
includes all nets, design devices, source and loads. There are parasitic components.

Measuring the Propagation Delay with parasitics:

1. In the waveform window execute Tools-Calculator.

2. From the functions select delay, this will open the delay data panel.
3. Place the cursor in the text box for signal1, select the wave button and select the input
waveform from the waveform window.
4. Repeat the same for signal2, select the output form.
5. Set the Threshold value1 (vdd/2) and Threshold value2 (vdd/2).
6. Execute ok and observe the expression created in the calculator.
7. Click on Evaluate the Buffer icon to perform the calculation. Close calculator
window.

Calculating the Power:

1. In ADEL window, select outputs, from the tab select save all.
2. In pop-up window, select all block for first and second line. Apply ok.
3. Run the simulation once again.
4. In the waveform window, choose browser from classic panel, double click on
tran, click on :pwr.
5. Power waveform appears on waveform window.
6. Execute Tools-Calculator.
 7. Select the wave button on calculator and select the power waveform from the
waveform window.
8. This will display getdata on calculator window.
9. From the functions select average, this will open the data panel.
10. Click on Evaluate and observe the expression created in the calculator.

Calculating the Gain:

1. Go to ADEL window.
2. Run simulation
3. In the waveform window, open a new sub window.
4. From the ADEL window go to Results -> Direct Plot ->Select AC Gain and
Phase, and select Vo and Vin from test circuit.
5. Gain waveform appears on the simulation window.
 Experiment – 1
Objectives:
1. Design an Inverter with given specification, completing the design flow mentioned below
a. Draw the schematic and verify the following
i) DC Analysis
ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the design
e. Verify & Optimize for Time, Power and Area to the given constraint.

Schematic Symbol

Library Cell Name Properties/comments

Name
gpdk180 nmos Model Name= nmos1 (NM0);
W= 2u; L=180n
gpdk180 pmos Model Name = pmos1 (PM0);
W= 2u; L=180n
 Test Circuit

Library Cell Name Properties/comments

Name
USN Inv symbol
analoglib Vpulse V1 = 0V, V2 =1.8V, Delay = 0s, Rise time=1ns;
fall time=1ns; Pulse Width = 10ns, Period = 20n s
analoglib Vdc, gnd DC Voltage=1.8V

Simulation Waveform (Transient, DC):

Analysis Start time Stop time

Transient - 200ns
Dc 0 1.8V
Layout:
 EXPERIMENT – 2
Objective:

1. Design the following circuits with given specification, completing the design flow
mentioned below
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the design
i) A Single Stage Differential Amplifier.
ii) Common Source and Common Drain Amplifier.

Schematic

Library Name Cell Name Properties / Comments

gpdk180 nmos Model Name = nmos1 (NM0, NM1); W= 3u; L = 1u
gpdk180 nmos Model Name = nmos1 (NM2, NM3); W= 4.5u; L = 1u
gpdk180 pmos Model Name = nmos1 (PM0, PM1); W= 15u; L = 1u
 Symbol Test Circuit

Symbol Library Cell Properties / Comments

Parameters Name Name
USN Diff_Amp Symbol
Vin analogLib vsin Define specification as
AC Magnitude = 1; Amplitude = 5m;Frequency = 1K
Vb analogLib vdc -2.5
Vss analogLib vdc -2.5
vnonb analogLib gnd
idc analogLib Idc DC current = 30u

Simulation Waveform (Transient, AC, DC):

Layout
 EXPERIMENT – 3

Objectives
1. Design the following circuits with given specification, completing the design flow
Mentioned below
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the design of Common Source
Amplifier.

Schematic Symbol

Library Name Cell Name Properties / Comments

gpdk180 nmos Model Name = nmos1 (NM0);
W= 10u; L = 1u
gpdk180 pmos Model Name = nmos1 ( PM0);
W= 50u; L = 1u
 Test Circuit:

Library Symbol Cell Name Properties / Comments

Name Parameters
USN cs_amplifier Symbol
analogLib Vin vsin Define specification as
AC Magnitude = 1; Amplitude = 5m;
Frequency = 1K
analogLib vdd, vbias vdc 2.5
analogLib vss vdc -2.5

Simulation Waveform (Transient, AC, DC):

Layout:
 EXPERIMENT – 4
Objective:
1. Design the following circuits with given specification, completing the design flow
Mentioned below
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the design for Common Drain
Amplifier.

Schematic Symbol

Library Name Cell Name Properties / Comments

gpdk180 nmos Model Name = nmos1 (NM1);
W= 10u; L = 1u
gpdk180 nmos Model Name = nmos1 (NM0);
W= 50u; L = 1u
 Test Circuit:

Library Symbol Cell Name Properties / Comments

Name Parameters
USN cd_amplifier
Symbol
analogLib vin vsin Define specification as
AC Magnitude = 1;Amplitude = 5m;
Frequency = 1K
analogLib vbias, vdd vdc 2.5
analogLib vss gnd -2.5
Simulation Waveform (Transient, AC, DC):
Layout:
 EXPERIMENT – 5
Objective:

1. Design the Op-Amp circuits with given specification, using given Differential amplifier
and Common source amplifier in library and completing the design flow mentioned below.
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS

Schematic

Library Name Cell Name Properties / Comments

USN diff_amp symbol
USN cs_amplifier symbol

Symbol
 Test Circuit:

Symbol Library Cell Properties / Comments

Parameters Name Name
USN Op_amp Symbol
Vin analogLib vsin Define specification as
AC Magnitude = 1; Amplitude = 5m;Frequency = 1K
Vb analogLib vdc -2.5
Vss analogLib vdc -2.5
vnonb analogLib gnd
idc analogLib Idc DC current = 30u

Simulation Waveform (Transient, AC, DC):

Layout:
 EXPERIMENT – 5
Objective:

1. Design the R-2R DAC circuits with given specification, using given operational amplifier
in library and completing the design flow mentioned below.
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis

Schematic

Library Name Cell Name Properties / Comments

gpdk180 polyres R=2k
gpdk180 polyres R=1k
USN Op-amp symbol
analogLib Idc,gnd Idc=30u

Symbol
Test Circuit:

Library Name Cell Name Properties / Comments

USN R-2RDAC Symbol
analogLib vpulse For V0: v1=0 v2=2 Ton=5n T=10n
For V1: v1=0 v2=2 Ton=10n T=20n
For V2: v1=0 v2=2 Ton=20n T=40n
For V3: v1=0 v2=2 Ton=40n T=80n
analogLib vdc, gnd Vdd = 2; Vss = -2

Simulation Waveform (Transient): Tran: 250ns

VII Semester 15ECL77– VLSI Laboratory

Department of ECE, RNSIT 1