EC231 ELECTRONICS DEVICES AND CIRCUITS LAB

COLLEGE OF ENGINEERING CHENGANNUR

(Approved by AICTE & Affiliated to APJ Abdul Kalam Technological University)
Chengannur P.O. Alappuzha District Kerala
Website: www.ceconline.edu

DEPARTMENT OF ELECTRONICS & COMMUNICATION

EC231 ELECTRONICS DEVICES AND CIRCUITS LAB
SEMESTER-III of ACADEMIC YEAR 2018-‘19

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TABLE OF CONTENTS

Exp No TITLE Page No

VI CHARACTERISTICS OF RECTIFIER AND ZENER

1 03-08
DIODES
RC INTEGRATING AND DIFFERENTIATING
2 CIRCUITS (TRANSIENT ANALYSIS WITH DIFFERENT 09-12
INPUTS AND FREQUENCY RESPONSE)

FULLWAVE RECTIFIER -WITH AND WITHOUT

3 13-17
FILTER- RIPPLE FACTOR AND REGULATION

CLIPPING AND CLAMPING CIRCUITS (TRANSIENTS

4 18-27
AND TRANSFER CHARACTERISTICS)
CHARACTERISTICS OF BJT IN CE CONFIGURATION
5 28-31
AND EVALUATION OF PARAMETERS
. RC COUPLED CE AMPLIFIER - FREQUENCY
6 32-35
RESPONSE CHARACTERISTICS
SIMPLE ZENER VOLTAGE REGULATOR (LOAD AND
7 36-38
LINE REGULATION)
. FEEDBACK AMPLIFIERS (CURRENT

SERIES, VOLTAGE SERIES) - GAIN AND

8 39-43
FREQUENCY RESPONSE

9 LOW FREQUENCY OSCILLATORS –RC PHASESHIFT, 44-45

POWER AMPLIFIERS (TRANSFORMER LESS) - CLASS

10 46-48
B AND CLASS AB

. MULTIVIBRATORS -ASTABLE
11 49-51

12 BOOTSTRAP SWEEP CIRCUIT 52-54

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EXPERIMENT NO.1

V I CHARACTERISTICS OF RECTIFIER AND ZENER

DIODE
A)V I characteristics of silicon and germanium diode.

AIM: To plot Volt-Ampere Characteristics of Germanium and Silicon P-N Junction Diode.

2. To find cut-in Voltage for Germanium and Silicon P-N Junction diode.

3. To find static and dynamic resistances in both forward and reverse biased conditions of Germanium
and Silicon (only forward bias) P-N Junction diode.

APPARATUS:

1 Diodes IN 4007 ( Si), OA79(Ge), Resistors 1KΩ, 100Ω , Regulated Power Supply (0-30)V DC ,
Bread Board ,Digital Ammeter (0-200)μA/(0-200)mA ,Digital Voltmeter (0-20)V DC ,Connecting
Wires As Required

THEORY:- A p-n junction diode conducts only in one direction. The V-I characteristics of the diode
are curve between voltage across the diode and current through the diode. When external voltage is
zero, circuit is open and the potential barrier does not allow the current to flow. Therefore, the circuit
current is zero. When P-type (Anode is connected to +ve terminal and n- type (cathode) is connected to
–ve terminal of the supply voltage, is known as forward bias. The potential barrier is reduced when
diode is in the forward biased condition. At some forward voltage, the potential barrier altogether
eliminated and current starts flowing through the diode and also in the circuit. The diode is said to be
in ON state. The current increases with increasing forward voltage. When N-type (cathode) is connected
to +ve terminal and P-type (Anode) is connected to –ve terminal of the supply voltage is known as
reverse bias and the potential barrier across the junction increases. Therefore, the junction resistance
becomes very high and a very small current (reverse saturation current) flows in the circuit. The diode
is said to be in OFF state. The reverse bias current due to minority charge carriers

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CIRCUIT DIAGRAM

FORWARD BIAS

REVERSE BIAS

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PROCEDURE: (i) FORWARD BIAS (For ‘Ge’ and ‘Si’ Diode):

1. Connections are made as per the circuit diagram.

2. For forward bias, the RPS +ve is connected to the anode of the diode and RPS –ve is connected to
the cathode of the diode,

3. Switch ON the power supply and increases the input voltage (supply voltage) in Steps

4. Note down the corresponding current flowing through the diode and voltage across the diode for
each and every step of the input voltage

5. The readings of voltage and current are tabulated. 6. Graph is plotted between voltage on x-axis and
current on y-axis.

OBSERVATIONS:

IN4001(Silicon) OA79(Germanium)

V (volts) I(mA) V (VOLTS) I (mA)

(ii) REVERSE BIAS (For ‘Ge’ Diode):

1. Connections are made as per the circuit diagram.

2. For reverse bias, the RPS +ve is connected to the cathode of the diode and RPS –ve is connected to
the anode of the diode.

3. Switch ON the power supply and increase the input voltage (supply voltage) in Steps.

4. Note down the corresponding current flowing through the diode and voltage across the diode for each
and every step of the input voltage.

5. The readings of voltage and current are tabulated.

6. The Graph is plotted between voltage on x-axis and current on y-axis.

V (volts) I (micro ampere)

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Calculations

RESULT: The Forward and Reverse Bias characteristics for a p-n diode are observed. The cutin
voltage, static and dynamic resistances in both forward and reverse biased conditions for Germanium
and Silicon P-N Junction diode are found.

i) The Cut-in voltage of ‘Ge’ Diode is____________________

ii) The Cut-in voltage of ‘Si’ Diode is____________________
iii) The Static forward resistance of ‘Ge’ Diode is___________________
iv) The Dynamic forward resistance of ‘Ge’ Diode is_________________
v) The Static reverse resistance of ‘Ge’ Diode is___________________
vi) The Dynamic reverse resistance of ‘Ge’ Diode is_________________
vii) The Static forward resistance of ‘Si’ Diode is____________________
viii) The Dynamic forward resistance of ‘Si’ Diode is_________________

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B)V I CHARACTERISTICS OF ZENER DIODE

AIM: 1. To observe and draw the V-I characteristics and Regulation characteristics of a Zener diode.
2. To find the Zener Break down voltage in reverse biased condition.

3. To find the Static and Dynamic resistances of Zener diode in both forward and reverse biased
conditions.

APPARATUS:

1 Zener Diode,,Resistors 1KΩ, 10KΩ ,Regulated Power Supply (0-30)V ,Bread Board , Ammeter (0-
200)mA ,Digital Voltmeter (0-20)V DC ,Connecting Wires As Required

THEORY: A zener diode is heavily doped p-n junction diode, specially made to operate in the break
down region. A p-n junction diode normally does not conduct when reverse biased. But if the reverse
bias is increased, at a particular voltage it starts conducting heavily. This voltage is called Break down
Voltage. High current through the diode can permanently damage the device .To avoid high current,
we connect a resistor in series with zener diode. Once the diode starts conducting it maintains almost
constant voltage across the terminals what ever may be the current through it, i.e., it has very low
dynamic resistance. It is used in voltage regulators.

CIRCUIT DIAGRAM

REVERSE BIAS

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. The Regulated power supply voltage is increased in steps.

3. The zener current (lz), and the zener voltage (Vz.) are observed and then noted in the tabular form.
4. A graph is plotted between zener current (Iz) on y-axis and zener voltage (Vz) on x-axis.

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OBSERVATIONS:

V(volts) I(mA)

V-I CHARACTERISTICS:

RESULT:

The V-I characteristics and Regulation characteristics of a zener diode are observed. The Zener Break
down voltage in reverse biased condition, Static and Dynamic resistances of Zener diode in both
forward and reverse biased conditions are calculated.

i) The Zener Break down voltage is_____________________

ii) The Static forward resistance of Zener Diode is___________________
iii) The Dynamic forward resistance of Zener Diode is_________________
iv) The Static reverse resistance of Zener Diode is___________________
v) The Dynamic reverse resistance of Zener Diode is_________________

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EXPERIMENT NO.2

RC INTEGRATOR AND RC DIFFERENTIATOR

A)RC INTEGRATOR

Aim: Design and set up an RC integrator and study its response to pulse and square waves

Components and equipment’s required: Diodes, Resistors, signal generator, dc sources,

bread board and CRO

Theory: The RC integrator is a series connected RC network that produces an output signal
which corresponds to the mathematical process of integration. A passive RC network is nothing
more than a resistor in series with a capacitor, that is a fixed resistance in series with a capacitor
that has a frequency dependant reactance which decreases as the frequency across its plates
increases. Thus at low frequencies the reactance, Xc of the capacitor is high while at high
frequencies its reactance is low due to the standard capacitive reactance formula of Xc =
1/(2πƒC). For an RC integrator circuit, the input signal is applied to the resistance with the
output taken across the capacitor, then V OUT equals VC. As the capacitor is a frequency
dependant element, the amount of charge that is established across the plates is equal to the
time domain integral of the current. That is it takes a certain amount of time for the capacitor
to fully charge as the capacitor can not charge instantaneously only charge exponentially.

The current is Vin/ R since almost all vin is appearing across R.

Output voltage across C is V0 is = ( 1/RC)∫ 𝑉𝑖𝑛 𝑑𝑡

The output is proportional to the integral of the input. voltage drop across C increase as time
passes.

A pulse waveform is a kind of voltage that rises to a high voltage level abruptly and remains at
the level for a period of time and falls quickly to zero and remains at that level for another
period of time.

A square waveform has positive and negative excursions with respect to its reference zero. If
the input is a square wave , capacitor charges and discharges from negative voltage to the
positive voltage and back.

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Circuit Diagram

Design

Let the input be a pulse train of 1kHz. Then T =1ms.

For an integrator RC>=16T

To avoid loading , select R= Ten times the output impedance of the signal generator. i.e., output
impedance of signal generator is 600ohm then R=6000ohm . Use 5.6K std

Therefore we get, c=2.857𝑢𝐹 . Use 3.3uF std.

Procedure:

1. Switch on the function generator and set it for 10Vpp, 1kHz square wave

2. Note down the output waveforms for the following conditions using a potentiometer. (i)
RC=T, (ii) RC<<T (iii) RC>>T

3.Repeat the above steps steps for a 5Vpp, 1kHz pulse wave input

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B)RC DIFFERENTIATOR

Aim: Design and set up an RC differentiator and study its response to pulse and square waves

Components and equipments required: Diodes, Resistors, signal generator, dc sources,

bread board and CRO

Theory:

The passive RC differentiator is a series connected RC network that produces an output signal
which corresponds to the mathematical process of differentiation. For an RC differentiator
circuit, the input signal is applied to one side of the capacitor with the output taken across the
resistor, then VOUT equals VR. As the capacitor is a frequency dependant element, the amount
of charge that is established across the plates is equal to the time domain integral of the current.
That is it takes a certain amount of time for the capacitor to fully charge as the capacitor can
not charge instantaneously only charge exponentially. the voltage across the capacitor can not
change instantly but depends on the value of the capacitance, C as it tries to store an electrical
charge, Q across its plates. Then the current flowing into the capacitor, that is it depends on the
rate of change of the charge across its plates. Thus the capacitor current is not proportional to
the voltage but to its time variation giving: i = dQ/dt. As VOUT equals VR where VR according
to ohms law is equal too: iR x R. The current that flows through the capacitor must also flow
through the resistance as they are both connected together in series.

Vout= RC dv/dt

Circuit Diagram

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Design

Let the input be a pulse train of 1kHz. Then T =1ms.

For an integrator RC=<0.0016T

To avoid loading , select R= Ten times the output impedance of the signal generator. i.e., output
impedance of signal generator is 600ohm then R=6000ohm . Use 5.6K std

Therefore we get, c=2857𝑝𝐹 . Use 220pF std.

Procedure:

1. Switch on the function generator and set it for 10Vpp, 1kHz square wave

2. Note down the output waveforms for the following conditions using a potentiometer. (i)
RC=T, (ii) RC<<T (iii) RC>>T

3.Repeat the above steps steps for a 5Vpp, 1kHz pulse wave input

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EXPERIMENT NO:3

FULL WAVE RECTIFIERS (WITHOUT AND WITH C-

FILTER)
AIM: 1. To obtain the load regulation and ripple factor of a full-wave rectifier by using

(a). without Filter (b). with Filter

2. To observe the input and output waveforms of a full-wave rectifier.

APPARATUS:

Diodes IN 4007 (Si) , Resistance 1KΩ 1,Step down Transformer ,Capacitor 470µF, Bread Board
,CRO, Connecting Wires As Required

THEORY:

Center-tapped full wave rectifier :The circuit of a center-tapped full wave rectifier uses two diodes
D1&D2. During positive half cycle of secondary voltage (input voltage), the diode D1 is forward biased
and D2is reverse biased. The diode D1 conducts and current flows through load resistor RL. During
negative half cycle, diode D2 becomes forward biased and D1 reverse biased. Now, D2 conducts and
current flows through the load resistor RL in the same direction. There is a continuous current flow
through the load resistor RL, during both the half cycles and will get unidirectional current as show in
the model graph. The difference between full wave and half wave rectification is that a full wave
rectifier allows unidirectional (one way) current to the load during the entire 360 degrees of the input
signal and half-wave rectifier allows this only during one half cycle (180 degree).

Bridge rectifier: During the positive half cycles of the secondary voltage diode D2 and D4 are
conducting and diode D1 and D3 are not conducting. Therefore current flows through the secondary
winding diode D2 and load resistor and diode D4 .During the negative half cycles D1 and D3 are
conducting and D2 and D4 are not conducting. Therefore, current flows through the secondary winding
diode D3 and load resistor and D1.in both cases the current flows through the load resistor in the same
direction.

The theoretical value of ripple factor of bridge and full wave rectifier is

r =1/(4√3 f RLC)

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CIRCUIT DIAGRAM:

Observations :

A)without filter

FWR Vm Vrms=Vm/√2 Vdc=2Vm/ π r=

√(𝑉𝑟𝑚𝑠/𝑉𝑑𝑐)2 − 1

BR Vm Vrms=Vm/√2 Vdc=2Vm/ π r=
√(𝑉𝑟𝑚𝑠/𝑉𝑑𝑐)2 − 1

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B)with filter

Type Vm Vrpp Vr,rms= Vdc=Vm- r= Vr,rms/ Vdc

Vrpp/2√3 Vrpp/2
FWR
BR

BRIDGE RECTIFIER WITHOUT FILTER

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BRIDGE RECTIFIER WITH FILTER

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Connect the primary side of the transformer to ac mains and the secondary side to the rectifier
input.

3. Switch on the main supply .observe the transformer secondary voltage waveform and output voltage
waveform across the load resistor ,simultaneously on the CRO screen note the peak values

4 .calculate ripple factor using expression

5.connect the capacitor filter and observe the waveform .note down Vm ,Vrpp and calculate the ripple
factor using expression

6.repeat the above step for bridge rectifiers.

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Waveforms

RESULT:

The Ripple factor and the % regulation for the Full-Wave Rectifier with and without filters are
calculated.

1. The Ripple factor of Full-Wave Rectifier without filter is _

a)centre tapped full wave rectifier
b)bridge rectifier

2. The Ripple factor of Full-Wave Rectifier with filter is

a)centre tapped full wave rectifier

b)bridge rectifier

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EXPERIMENT NO.4

CLIPPING AND CLAMPING CIRCUITS

A)CLIPPING CIRCUITS

Aim: To design, set up and study various clipping circuits using diodes.

Components and equipments required: Diodes, Resistors, signal generator, dc sources,

bread board and CRO

Theory Clipping circuits are non-Linear wave shaping circuits. They are useful to clip off the
positive or negative portions of an input waveform. It can also be used to slice off an input
waveform between two voltage levels. Using a double clipper , a moderate quality square
waveform can be generated from the sine wave. The property of a diode as a switching device
is utilised in clipping circuits. Diode clippers are of two types series and shunt clippers.. In the
shunt clippers, output is taken parallel (shunt) with the diode and in series clippers, output is
taken in series with the diode. A resistance is used to limit the current through the diode. The
value of the resistance used in the clipping circuits is given by the expression R=√(Rf x Rr) ,
where Rf = forward resistance of the diode and Rr = reverse resistance of the diode

Positive Diode Clipping Circuit: In this diode clipping circuit, the diode is forward biased
(anode more positive than cathode) during the positive half cycle of the sinusoidal input
waveform. For the diode to become forward biased, it must have the input voltage magnitude
greater than +0.7 volts (0.3 volts for a germanium diode).

When this happens the diodes begins to conduct and holds the voltage across itself constant at
0.7V until the sinusoidal waveform falls below this value. Thus the output voltage which is
taken across the diode can never exceed 0.7 volts during the positive half cycle.

During the negative half cycle, the diode is reverse biased (cathode more positive than anode)
blocking current flow through itself and as a result has no effect on the negative half of the
sinusoidal voltage which passes to the load unaltered. Thus the diode limits the positive half of
the input waveform and is known as a positive clipper circuit.

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Negative Diode Clipping Circuits: The diode is forward biased during the negative half cycle
of the sinusoidal waveform and limits or clips it to –0.7 volts while allowing the positive half
cycle to pass unaltered when reverse biased. As the diode limits the negative half cycle of the
input voltage it is therefore called a negative clipper circuit.

Clipping of Both Half Cycles : If we connected two diodes in inverse parallel, then both the
positive and negative half cycles would be clipped as diode D1 clips the positive half cycle of
the sinusoidal input waveform while diode D2 clips the negative half cycle. Then diode clipping
circuits can be used to clip the positive half cycle, the negative half cycle or both.

For ideal diodes the output waveform above would be zero. However, due to the forward bias
voltage drop across the diodes the actual clipping point occurs at +0.7 volts and –0.7 volts
respectively. But we can increase this ±0.7V threshold to any value we want up to the maximum
value, (VPEAK) of the sinusoidal waveform either by connecting together more diodes in series
creating multiples of 0.7 volts, or by adding a voltage bias to the diodes.

Biased Diode Clipping Circuits: To produce diode clipping circuits for voltage waveforms at
different levels, a bias voltage, VBIAS is added in series with the diode to produce a combination
clipper as shown. The voltage across the series combination must be greater
than VBIAS + 0.7V before the diode becomes sufficiently forward biased to conduct. For
example, if the VBIAS level is set at 4.0 volts, then the sinusoidal voltage at the diode’s anode
terminal must be greater than 4.0 + 0.7 = 4.7 volts for it to become forward biased. Any anode
voltage levels above this bias point are clipped off.

Positive Bias Diode Clipping: Likewise, by reversing the diode and the battery bias voltage,
when a diode conducts the negative half cycle of the output waveform is held to a level –
VBIAS – 0.7V as shown.

Negative Bias Diode Clipping: A variable diode clipping or diode limiting level can be
achieved by varying the bias voltage of the diodes. If both the positive and the negative half
cycles are to be clipped, then two biased clipping diodes are used. But for both positive and
negative diode clipping, the bias voltage need not be the same

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Circuit diagrams and Waveforms

1.positive clipper clipping at 0V

2.Negative clipper clipping at 0V

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3.positive clipper clipping at +3V

4.Negative clipper clipping at -3V

5.Double clipper clipping at +3 and -3V

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6.positive series clipper

7.Reverse biased positive series clipper

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Design:

Select IN4007 or BY 126 diodes.

The series resistance used for current limiting R

Typical values of R f =30 ohm and Rr =300 k , we get R = 3 K. Use 3.3K

Procedure:

1. Check the components using multimeter

2. Setup the first circuit

3. Apply the sine wave input to the circuit.

4. Simultaneously observe the input and output on CRO.

5. Repeat the above steps for all circuits

6. Plot the waveforms

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B)CLAMPING CIRCUITS

Aim: To design, set up and study various clamping circuits using diodes.

Components and equipments required: Diodes, Resistors, signal generator, dc sources,

bread board and CRO

Theory: A clamping circuit is simply a level shifter. It shifts the level of an input waveform
to a predesigned level. Now consider a positive clamper circuit. During the negative half cycle,
the diode is forward biased and hence voltage at output is the forward voltage drop of diode.
So capacitor charges. During the positive half cycle of ac voltage, diode is reverse biased .So
applied voltage comes at output .Also the capacitor discharges and the discharging voltage is
adding to the input voltage. So the output voltage is the sum of the input voltage and the
capacitor discharge voltage. Then by properly biasing the diode clamping at various voltage
levels can be obtained.

1. Positive clamper clamping at 0V

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2.Negative clamper clamping at 0V

3.Positive clamper clamping at -3 V

4. Positive clamper clamping at +3 V

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5)Negative clamper clamping at +3 V

6) Negative clamper clamping at -3 V

Design:

Select IN4007 or BY 126 diodes.

The series resistance used for current limiting R

Typical values of R f =30 ohm and Rr =300 k , we get R = 3 K. Use 3.3K

Procedure:

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1. Check the components using multimeter

2. Setup the first circuit

3. Apply the sine wave input to the circuit.

4. Simultaneously observe the input and output on CRO.

5. Repeat the above steps for all circuits

6. Plot the waveforms

Result:

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EXPERIMENT NO:5

BJT CHARACTERISTICS (CE CONFIGURATION)

AIM: 1. To draw the input and output characteristics of transistor connected in CE
Configuration

2. To find Input Resistance (Ri), Output Resistance (Ro) and Current amplification Factor (β) of
the given transistor.

APPARATUS: Transistor (BC-107) , Resistors 1KΩ, 470Ω , Regulated Power Supply (0-30)V DC ,
Bread Board ,Ammeters (0-200)μA/(0-200)mA , Voltmeters (0-20)V DC , Connecting Wires As
Required

THEORY: A transistor is a three terminal device. The terminals are emitter, base, collector.
In common emitter configuration, input voltage is applied between base and emitter terminals and out
put is taken across the collector and emitter terminals. Therefore the emitter terminal is common to both
input and output. The input characteristics resemble that of a forward biased diode curve. This
is expected since the Base-Emitter junction of the transistor is forward biased. As compared to CB
arrangement IB increases less rapidly with VBE. Therefore input resistance of CE circuit is higher than
that of CB circuit. The output characteristics are drawn between Ic and VCE at constant IB.
the collector current varies with VCE unto few volts only. After this the collector current becomes
almost constant, and independent of VCE. The value of VCE up to which the collector current changes
with V CE is known as Knee voltage. The transistor always operated in the region above Knee voltage,
IC is always constant and is approximately equal to IB. The current amplification factor of CE
configuration is given by β = ΔIC/ΔIB

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Circuit diagram

BC107 transistor details .it is a silicon low frequency transistor

Maximum ratings VCB=50V, VCE=45 V, VEB= 6 V ,IC= 100 mA

Nominal rating VCe=5V,IC=2mA, hFE=100 to 500

PROCEDURE:

(i) INPUT CHARACTERSTICS:

1. Connect the circuit as per the circuit diagram.

2. For plotting the input characteristics the output voltage VCE is kept constant at 1V and for different
values of VBE, note down the values of IB.

3. Repeat the above step by keeping VCE at 2V and 3V.

4. Tabulate all the readings.

5. Plot the graph between VBE on x-axis and IB on y-axis for constant VCE.

(ii) OUTPUT CHARACTERSTICS:

1. Connect the circuit as per the circuit diagram.

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2. For plotting the output characteristics the input current IB is kept constant at 50μA and for different
values of VCE, note down the values of IC.

3. Repeat the above step by keeping IB at 75μA and 100μA.

4. Tabulate the all the readings.

5. Plot the graph between VCE on x-axis and IC on y-axis for constant IB.

OBSERVATIONS: (i) INPUT CHARACTERISTICS:

VCE =0V VCE=3 V VCE=6V

IB(µA) VBE(V) IB(µA) VBE(V) IB(µA) VBE(V)

OBSERVATIONS: (i) OUTPUT CHARACTERISTICS:

IB=60µA IB=80µA IB=100µA

IC(mA) VCE (V) IC(mA) VCE (V) IC(mA) VCE (V)

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Graph

Input characteristics Output characteristics

Result

Dynamic input resistance=------------------------------ Ω

Dynamic output resistance=------------------------------ Ω

Common emitter current gain =-----------------------------β

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EXPERIMENT NO:6

RC-COUPLED AMPLIFIER
Aim

To design and set up an RC-coupled CE amplifier using bipolar junction transistor and to plot its
frequency response. Components and equipments required Transistor, dc source, capacitors, resistors,
bread board, signal generator, multimeter and CRO.

Theory

RC-coupled CE amplifier is widely used in audio frequency applications in radio and TV receivers. It
provides current, voltage and power gains. Base current controls the collector current of a common
emitter amplifier. A small increase in base current results in a relatively large increase in collector
current. Similarly, a small decrease in base current causes large decrease in collector current. The
emitter-base junction must be forward biased and the collector base junction must be reverse biased for
the proper functioning of an amplifier. In the circuit diagram, an NPN transistor is connected as a
common emitter ac amplifier. R1 and R2 are employed for the voltage divider bias of the transistor.
Voltage divider bias provides good stabilisation independent of the variations of β. The input signal Vin
is coupled through CC1 to the base and output voltage is coupled from collector through the capacitor
CC2. The input impedance of the amplifier is expressed as Zin = R1||R2||(1 +hF Ere) and output
impedance as Zout = RC||RL where re is the internal emitter resistance of the transistor given by the
expression = 25 mV/IE, where 25 mV is temperature equivalent voltage at room temperature.

Selection of transistor Transistor is selected according to the frequency of operation, and power
requirements. The hF E of the transistor is another aspect we should be careful about. Low frequency
gain of a BJT amplifier is given by the expression. Voltage gain Av = −hF E RL Ri . In the worst case
with RL = Ri , AV = −hF E. hF E of any transistor will vary in large ranges. For example, the hF E of
SL100 (a general purpose transistor) varies from 40 to 300. hF E of BC107 (an AF driver) varies from
100 to 500. Therefore a transistor must be selected such that its minimum guaranteed hF E is greater
than or equal to AV required.

Selection of supply voltage VCC For a distortionless output from an audio amplifier, the operating
point must be kept at the middle of the load line selecting VCEQ = 50% VCC(= 0.5VCC). This means
that the output voltage swing in either positive or negative direction is half of VCC. However, VCC is
selected 20% more than the required voltage swing. For example, if the required output swing is 10 V,
VCC is selected 12 V.

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Selection of collector current IC The nominal value of IC can be selected fromthe data sheet. Usually
it will be given corresponding to hF E bias. It is the bias current at which hF E is measured. For BC107
it is 2 mA, for SL100 it is 150 mA, and for power transistor 2N3055 it is 4 A

Design of emitter resistor RE

Current series feedback is used in this circuit using RE. It stabilizes the operating point against
temperature variation. Voltage across RE must be as high as possible. But, higher drop across RE will
reduce the output voltage swing. So, as a rule of thumb, 10% of VCC is fixed across RE. RE = VRE IE
= VRE IC since IE ≈ IC, RE = 0.1 VCC IC

Design of RC Value of RC can be obtained from the relation RC = 0.4VCC/IC since remaining 40%
of VCC is dropped across RC.

Design of potential divider R1 and R2 Value of IB is obtained by using the expression IB = IC/hF E
min. At least 10IB should be allowed to flow through R1 and R2 for the better stability of bias voltages.
If the current through R1 and R2 is near to IB, slight variation in IB will affect the voltage across R1
and R2. In other words, the base current will load the voltage divider. When IB gets branched into the
base of transistor, 9IB flows through R2. Values of R1 and R2 can be calculated from the dc potentials
created by the respective currents.

Design of bypass capacitor CE The purpose of the bypass capacitor is to bypass signal current to
ground. To bypass the frequency of interest, reactance of the capacitor XCE computed at that frequency
should be much less than the emitter resistance. As a rule of thumb, it is taken XCE ≤ RE/10.

Design of coupling capacitor CC The purpose of the coupling capacitor is to couple the ac signal to
the input of the amplifier and block dc. It also determines the lowest frequency that to be amplified.
Value of the coupling capacitor CC is obtained such that its reactance XC at the lowest frequency (say
100 Hz or so for an audio amplifier), should be less than the input impedance of the amplifier. That
means XC must be ≤ Rin/10. Here Rin = R1||R2||(1 + hF Ere) where re is the internal emitter resistance
of the transistor given by the expression = 25 mV/IE at room temperature.

Procedure

1. Test all the components using a multimeter. Set up the circuit and verify dc bias conditions. To check
dc bias conditions, remove input signal and capacitors in the circuit.

2. Connect the capacitors in the circuit. Apply a 100 mV peak to peak sinusoidal signal from the function
generator to the circuit input. Observe the input and output waveforms on the CRO screen
simultaneously.

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3. Keep the input voltage constant at 100 mV, vary the frequency of the input signal from 0 to 1 MHz
or highest frequency available in the generator. Measure the output amplitude corresponding to different
frequencies and enter it in tabular column.

4. Plot the frequency response characteristics on a graph sheet with gain in dB on y-axis and logf on x-
axis. Mark log fL and log fH corresponding to 3 dB points. (If a semi-log graph sheet is used instead of
ordinary graph sheet, mark f along x-axis instead of logf).

5. Calculate the bandwidth of the amplifier using the expression BW= fH − fL.

6. Remove the emitter bypass capacitor CE from the circuit and repeat the steps 3 to 5 and observe that
the bandwidth increases and gain decreases in the absence of CE.

Circuit diagram

Design Output requirements: Mid-band voltage gain of the amplifier = 50 and required output voltage
swing = 10 V.

Selection of transistor Select transistor BC107 since its minimum guaranteed hF E(= 100) is more
than the required gain (=50) of the amplifier.

Quick Reference data of BC107 Type: NPN-Silicon, Application: In audio frequency

Maximum rating: VCB = 50 V, VCE = 45 V, VEB = 6 V, IC = 100 mA.

Nominal rating: VCE = 5 V, IC = 2 mA, hF E = 100 to 500.

DC biasing conditions VCC is taken as 20% more than required ouput swing. Hence VCC = 12 V. IC
= 2 mA, because hF E is guaranteed 100 at that current as per data sheet. In order to make the operating
point at the middle of the load line, assume the dc conditions VRC = 40% of VCC = 4.8 V, VRE = 10%
of VCC = 1.2 V and VCE = 50% of VCC = 6 V

Design of RC VRC = IC × RC = 4.8 V. From this, we get RC = 2.4 k. Use 2.2 k.

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Design of RE VRE = IE × RE = 1.2 V. From this, we get RE = 600 Ω because IE ≈ IC. Use 680 Ω std.

Design of voltage divider R1 and R2 Assume the current through R1 = 10IB and that through R2 =
9IB for a stable voltage across R1 and R2 independent of the variations of the base current. VR2 =
Voltage drop across R2 = VBE + VRE. i.e., VR2 = VBE + VRE = 0.6 + 1.2 = 1.8 V. Also, VR2 =
9IBR2 = 1.8 V But IB = IC/hF E = 2 mA/100 = 20 µA. Then R2 = 1.8 9×20×10−6 = 10.6 k. Use 10 k.
VR1 = voltage across R1 = VCC − VR2 = 12 V − 1.8 V = 10.2 V Also, VR1 = 10IBR1 = 10.1 V. Then
R1 = 10.2 10×20×10−6 = 50 k. Select 47 k std.

Design of RL: Gain of the common emitter amplifier is given by the expression AV = −(rc/re). Where
rc = RC||RL and re = 25 mV /IE = 25 mV /2 mA = 12.5 Ω. Since the required gain = 50, substituting it
in the expression we get, RL = 845 Ω. Use 820 Ω std.

Design of coupling capacitors CC1 and CC2 XC1 should be less than the input impedance of the
transistor. Here, Rin is the series impedance. Then XC1 ≤= Rin/10. Here Rin = R1||R2||(1 + hF Ere)
because is RE bypassed. We get Rin = 1.1 k. Then XC1 ≤ 110 Ω. So, CC1 ≥ 1/2πfL × 110 = 14 µF.

Use 15 µF std. Similarly, XC2 ≤ Rout/10, where Rout = RC. Then XCE ≤ 240 Ω. So, CC2 ≥ 1/2π ×
240 = 6.6 µF. Use 10 µF std.

Design of bypass capacitors CE To bypass the lowest frequency (say 100Hz), XCE should be less
than or equal to the resistance RE. i.e., XCE ≤ RE/10 Then, CE ≥ 1/(2π × 100 × 68) = 23 µF. Use 22
µF

Result Mid-band gain of the amplifier =. . . . . .

Bandwidth of the amplifier =. . . . . . Hz

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EXPERIMENT :7

ZENER DIODE VOLTAGE REGULATOR

Aim: To set up and study a zener diode shunt regulator and to plot its line and load regulation
characteristics

Components required

Zener,resistor,rheostat,voltmeter,ammeter,DC source and bread board

Theory:

A zener diode functions as ordinary diode when it sis forward biased. The Zener diode is operated in
the breakdown or zener region, the voltage across it is substantially constant for a large current of
current through it. This characteristic permits it to be used as a voltage regulator. As the load Current
increases, the Zener current decrease so that current through resistance Rs is constant.The current
through Rs is given by the expression ,Is=Iz+IL Where IL is the current through the current through the
RL resistor.The value of RS must be selected to fulfill the following worst condition requirement.

When the input voltage increases IL remains same ,Is and Iz increases ,similarly if the input voltage
decreases IL remains same ,Is and Iz decreases. Bt if Iz falls lower than the minimum zener current enough
to keep the zener in minimum break down region ,the region will cease the output voltage decreases. A
low input voltage can cause regulator fail to regulate.athe series resistance should be selected between
Rsmin and Rsmax

Rsmin=[vi(min)-vz]/Is

Rsmax=[vi(max)-vz]/Is

PROCEDURE:

(a)Connect the circuit as per the circuit diagram

(b)Keep load resistance constant (take maximum value of load resistance)

(c)Vary input voltage from 7V to 10 V and note down output voltage,calculate percentage of line
regulation using the expression Δvo/ Δvi

(d)Now keep input voltage constant(say 10V) and vary load resistance and note down corresponding
ammeter reading, and volt meter reading

(e)Plot the respective graph and calculate percentage of load regulation VR= (VNL-VFL)/ VNL

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Circuit diagram

Design output requirements

Vo= 5.6 V,IL= 5 mA when the input voltage is in the range 10±3V

Selection of zener select 5.6 V zener

Design of RL

We know RL = Vo/ IL

Vo =Vz then RL =5.6/5mA=1.12 k Ω ,use 1.2 K pot

Design of Rs

The series resistance Rs selected in a way a that

Rsmax> Rs > Rsmin

Rsmin=[vi(min)-vz]/Is =(7-5.6)/5mA=280 Ω

Rsmax=[vi(max)-vz]/Is =(13-5.6)/5mA=1.48k Ω

Select Rs =1 K Ω

Observation

IL= 10 mA

Vin Vo(volts)
(volts)

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Line regulation

Vin= 10 V

IL (mA) Vo(volts) Load regulation

GRAPH

RESULT

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EXPERIMENT 8

FEED BACK AMPLIFIER

A) CURRENT-SERIES FEEDBACK AMPLIFIER
Aim: To design and test the current-series feedback amplifier and to calculate the following
parameters with and without feedback.
1. Mid band gain.
2. Bandwidth and cut-off frequencies.

Components and equipment required :Transistors ,resistors capacitors ,signal generator,dc power
supply,breadboard,CRO

THEORY: Theory: The current series feedback amplifier is characterized by having shunt sampling
and series mixing. In amplifiers, there is a sampling network, which samples the output and gives to the
feedback network. The feedback signal is mixed with input signal by either shunt or series mixing
technique. Due to shunt sampling the output resistance increases by a factor of ‘D’ and the input
resistance is also increased by the same factor due to series mixing. This is basically trans conductance
amplifier. Its input is voltage which is amplified as current.

CIRCUIT DIAGRAM

DESIGN

Design Output requirements: Mid-band voltage gain of the amplifier = 50 and required output voltage
swing = 10 V.

Selection of transistor Select transistor BC107 since its minimum guaranteed hF E(= 100) is more
than the required gain (=50) of the amplifier.

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Quick Reference data of BC107 Type: NPN-Silicon, Application: In audio frequency

Maximum rating: VCB = 50 V, VCE = 45 V, VEB = 6 V, IC = 100 mA.

Nominal rating: VCE = 5 V, IC = 2 mA, hF E = 100 to 500.

DC biasing conditions VCC is taken as 20% more than required ouput swing. Hence VCC = 12 V. IC
= 2 mA, because hF E is guaranteed 100 at that current as per data sheet. In order to make the operating
point at the middle of the load line, assume the dc conditions VRC = 40% of VCC = 4.8 V, VRE = 10%
of VCC = 1.2 V and VCE = 50% of VCC = 6 V

Design of RC VRC = IC × RC = 4.8 V. From this, we get RC = 2.4 k. Use 2.2 k.

Design of RE VRE = IE × RE = 1.2 V. From this, we get RE = 600 Ω because IE ≈ IC. Use 680 Ω std.

Design of voltage divider R1 and R2 Assume the current through R1 = 10IB and that through R2 =
9IB for a stable voltage across R1 and R2 independent of the variations of the base current. VR2 =
Voltage drop across R2 = VBE + VRE. i.e., VR2 = VBE + VRE = 0.6 + 1.2 = 1.8 V. Also, VR2 =
9IBR2 = 1.8 V But IB = IC/hF E = 2 mA/100 = 20 µA. Then R2 = 1.8 9×20×10−6 = 10.6 k. Use 10 k.
VR1 = voltage across R1 = VCC − VR2 = 12 V − 1.8 V = 10.2 V Also, VR1 = 10IBR1 = 10.1 V. Then
R1 = 10.2 10×20×10−6 = 50 k. Select 47 k std.

Design of RL: Gain of the common emitter amplifier is given by the expression AV = −(rc/re). Where
rc = RC||RL and re = 25 mV /IE = 25 mV /2 mA = 12.5 Ω. Since the required gain = 50, substituting it
in the expression we get, RL = 845 Ω. Use 820 Ω std.

Feedback factor,  = -RE

Gm = -hfe / (hie + RE)

Desensitivity factor, D = 1 +  Gm

Transconductance with feedback, Gmf = Gm / D

Input impedance with feedback, Zif = Zi D

Output impedance with feedback, Z0f = Z0 D

Procedure: 1. Connect the circuit as per the circuit diagram.

2. Keeping the input voltage constant, vary the frequency from 50Hz to 3MHz in regular steps and note
down the corresponding output voltage.

3. Plot the graph: Gain (dB) Vs Frequency

4. Calculate the bandwidth from the graph

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Result: Thus the current series feedback amplifier is designed and constructed and its gain and
bandwidth are calculated.

1)Gain (midband)-------------------------------------

2) Bandwidth-------------------------------------------------

B)VOLTAGE SHUNT FEEDBACK AMPLIFIER

Aim: To design and test the voltage-shunt feedback amplifier and to calculate the following parameters
with and without feedback. 1. Mid band gain. 2. Bandwidth and cut-off frequencies.

Components and equipment required :Transistors ,resistors capacitors ,signal generator,dc power
supply,breadboard,CRO

Theory: In voltage shunt feedback amplifier, the feedback signal voltage is given to the base of the
transistor in shunt through the base resistor RB. This shunt connection tends to decrease the input
resistance and the voltage feedback tends to decrease the output resistance. In the circuit RB appears
directly across the input base terminal and output collector terminal. A part of output is feedback to
input through RB and increase in IC decreases IB. Thus negative feedback exists in the circuit. So this
circuit is also called voltage feedback bias circuit. This feedback amplifier is known an transresistance

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amplifier. It amplifies the input current to required voltage levels. The feedback path consists of a
resistor and a capacitor.

Circuit diagram

DESIGN

With feedback: RO = RC || Rf = Ri =

(RB || hie ) Rf =

Rm = -(hfe (RB || Rf) (RC || Rf)) / ((RB || Rf) + hie) =

Desensitivity factor, D = 1 +  Rm

Rif = Ri / D =

Rof = Ro / D =

Rmf = Rm / D =

XCi = Rif /10 =

Ci = 1 / (2f XCi) =

Xco = Rof /10 =

Co = 1 / (2f XCo) =

RE ’ = RE || ((RB + hie) / (1+hfe))

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XCE = RE ’ /10 =

CE = 1 / (2f XCE) =

XCf = Rf/10

Cf = 1 / (2f XCf) =

Procedure:

1. Connect the circuit as per the circuit diagram.

2. Keeping the input voltage constant, vary the frequency from 50Hz to 3MHz in regular steps and note
down the corresponding output voltage.

3. Plot the graph: Gain (dB) Vs Frequency

4. Calculate the bandwidth from the graph.

Result: Thus the current series feedback amplifier is designed and constructed and its gain and
bandwidth are calculated.

1)Gain (midband)-------------------------------------

2) Bandwidth-------------------------------------------------

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EXPERIMENTT :9

LOW FREQUENCY OSCILLATORS (RC PHASE SHIFT

OSCILLATOR)

Aim To design and set up an RC phase shift oscillator using BJT and to observe the sinusoidal output
waveform.

Components and equipments required Transistor, dc source, capacitors, resistors, potentiometer,

breadboard and CRO.

Theory An oscillator is an electronic circuit for generating an ac signal voltage with a dc supply as the
only input requirement. The frequency of the generated signal is decided by the circuit elements. An
oscillator requires an amplifier, a frequency selective network, and a positive feedback from the output
to the input. The Barkhausen criterion for sustained oscillation is Aβ = 1 where A is the gain of the
amplifier and β is the feedback factor. The unity gain means signal is in phase. (If the signal is 180◦ out
of phase, gain will be −1.)

If a common emitter amplifier is used, with a resistive collector load, there is a 180◦ phase shift between
the voltages at the base and the collector. Feedback network between the collector and the base must
introduce an additional 180◦ phase shift at a particular frequency. In the figure shown, three sections of
phase shift networks are used so that each section introduces approximately 60◦ phase shift at resonant
frequency. By analysis, resonant frequency f can be expressed by the equation,

The three section RC network offers a β of

1/29. Hence the gain of the amplifier should be 29. For this, the requirement on the hF E of the transistor
is found to be hF E ≥ 23 + 29(R/RC) + 4(RC/R). The phase shift oscillator is particularly useful in the
audio frequency range.

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Design Output requirements Sine wave with amplitude 10 VP P and frequency 1 kHz.

Design of the amplifier Select transistor BC107. It can provide a gain more than 29 because its
minimum hF E is 100.

DC biasing conditions VCC = 12 V, IC = 2 mA,VRC = 40% of VCC = 4.8 V, VRE = 10% of VCC =
1.2 V and VCE = 50% of VCC = 6 V.

Result Amplitude and frequency of sine wave = · · · · · · V, · · · · · · Hz respectively

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EXPERIMENT :10

POWER AMPLIFIER
Aim: to set up and study complementary symmetry class B and class AB push pull power amplifier

Components required: transistor ,diode ,potentiometer, DC source ,capacitor,resistor,bread board

,signal generators .

Theory : Class B operation means that the Q point Is located at the cut off and collector current flows
for 1800 of input cycle. A complimentary symmetry circuit uses two transistor NPN and PNP with
identical characteristics. Both transistors are connected as emitter follower with emitters connected
together. The name push pull comes from the fact that one transistor drive current through the load in
one direction while other transistor drives current in the opposite direction

During the positive half cycle of the input ,base of NPN transistor T2 is driven positive relative to its
emitter. This makes the transistor ON. At the same time ,other transistor is in off state .A current
determined by the supply voltage and load resistor gets established in the output circuit. During the
negative half cycle of the input , transistor T1 is becomes ON and T2 becomes OFF. Now output current
flows in opposite direction. Voltage developed across RL is same as the input voltage.

In class B power amplifier transistor will start conducting only after the input voltage reaches 0.6 This
causes output voltage to distort near the zero crossing. This distortion is called cross over distortion. To
avoid this slight base bias is applied so that as soon as the input is applied conduction begins and an
undistorted output can be obtained.

This circuit does not use transformer for phase splitting, Thus the cost and bulkiness of the circuit is
reduced.it has high efficiency.

Procedure:

1.Set up class B power amplifier circuit as shown in figure after testing all components ,observe the
cross over distortion on CRO screen

2. Set the frequency of input signal at 1KHZ and load impedance at 8Ω in power meter .Taking the
reading on the power meter of different values of load impedance. Plot load impedance versus output
power. Note the impedance for which output power is maximum. This is the value of optimum load

3.Repeat the above steps for class AB power amplifier circuit.

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CIRCUIT DIAGRAM

Class B power amplifier

Class AB power amplifier

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Design of class-AB power Design of RL and CCis same as that of class-B amplifier. Design of R and
RB The bias current through the compensating diodes ID is same as the ICQ in order to match the diode
curves and VBE curves of the transistor. ICQ should be 1 to 5 percent of collector saturation current
ICsat. Average current ICsat = VCEQ/πRL = 3/πRL = 43 mA ICQ = ID = ICsat × 5% = 2.15 mA
Applying KVL in the diode bias network, 6 V = ID × 2R + 1.2 V + ID × RB ID × RB should be about
2 V to drive into class-AB. ID × RB = 2 V . From this RB = 930 Ω. Use 1 k

Waveform

Class B power amplifier

Class AB power amplifier

Observation

Resistance Ω Power(mW)

Result :Waveforms of class A and class AB power amplifier is observed on CR

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EXPERIMENT 11

ASTABLE MUTIVIBRATOR
Aim:To design and set up an astable multivibrators using transistors ,study its performance and observe
the waveforms.

Apparatus required: Transistors, Resistors ,Capacitor ,Regulated dc Power Supply ,bread board

Theory :. An Astable Multivibrator has two quasi stable states and it keeps on switching between these
two states by itself . No external triggering signal is needed . The astable multivibrator cannot remain
indefinitely in any one of the two states .The two amplifier stages of an astable multivibrator are
regenerative across coupled by capacitors. The astable multivibrator may be to generate a square wave
of period,T=Ton +Toff

T1=0.69R1C1.

T1=0.69R2C2.

Suppose transistor Q1 is OFF and Q2 is ON,Then capacitor C2 whose left hand side was at potential --
Ic2RC2 starts charging towards Vcc through R2 and Q2.when the potential at left side of capacitor
becomes the cut in voltage Q1 starts conducting .Sudden surge of base current into Q1 create a
momentary rise in base voltage .But soon it settle at 0.7 volt.When Q1 conduct Q2 goes to OFF state
due to degenerative action is given by the expression ,T2=0.69R2C2.

Sudden conduction of Q1 causes a potential drop of Ic1RC1 at the collector of Q1 .this sudden chage get
transferred to the base of Q2,Because capacitor act as a short circuit for sudden changes.This create a
potential drop of 0.7v- Ic1RC1 at the right side of capacitor C1.Now 1 starts charge toward Vcc through
R1 and Q1.When the potential at the right side of he capacitor C1 reaches cut in voltage Q2 starts
conducting.resulted sudden voltage drop of Ic2RC2 transferrs from collector of Q2 to Q1,The base
potential of Q1 is then 0.7- Ic2RC2 This cycle repeats. Time duration for Q1 remains ON T2=0.69R1C1.

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CIRCUIT DIAGRAM

Procedure :

1. Calculate the theoratical frequency of oscillations of the circuit

2. Connect the circuit as per the circuit diagram.
3. Observe the voltage wave forms at both collectors of two transistors simultaneously.
4. Observe the voltage wave forms at each base simultaneously with corresponding collector
voltage.
5. Note down the values of wave forms carefully. 6. Compare the theoratical and practical values.
Wave forms

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Output waveforms

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Experiment 12

Bootstrap sweep circuit

Aim:To set up and study a bootstrap sweep circuit

Equipment and components required:

Transistors,diode,resistors,capacitors,signal generators, Bread board, dc supply.

THEORY: The input to Q1 is the gating waveform. Before the application of the gating waveform, at
t = 0, transistor Q1 is in saturation. The voltage across the capacitor C and at the base of Q2 is VCE(sat).
To ensure Q1 to be in saturation for t = 0, it is necessary that its current be at least equal to iCE / hFE
so that Rb < hfeR. With the application of the gating waveform at t = 0, Q1 is driven OFF. The current
iC1 now flow into C and assuming units gain in the emitter follower RC V t V CC 0 = . When the sweep
starts, the diode is reverse biased, as already explained above, the current through R is supplied by C1.
The current VCC / R through C and R now flows from base to emitter of Q2.if the output V0 reaches
the voltage VCC in a time TS / Tg, then from above we have TS = RC. If the sweep amplitude is less
than VCC, then the maximum ramp voltage is given by

DESIGN

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CIRCUIT DIAGRAM

WAVEFORMS

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PROCEDURE:

1. Connect the circuit as per the circuit diagram

2. Generate a control square wave amplitude vc of 5v pp at 1khz Frequency and apply into the circuit.
3. Observe the out put wave forms

RESULT:

TS = -------------------

TG= -----------------------

TR =----------------------

Bootstrap sweep circuit is designed and studied

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