A

Project Report On
Electronic voting machine
Submitted in partial fulfilment of the requirements for award of the
degree of
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By
B.Pradeep(16E31A0465)
E.Vamshi Pranay (16E31A0476)
Sushma Reddy (16E31A0497)
A.SriVarsha (16E31A0460)
Gopireddy ManiChandana (16E31A0480)
C. Premalatha(16E31A0474)
A.Saichitra(16E31A0457)
Under the guidance of
Mr. SRIDHARA SHETTY
AGM, CED
Of
ECIL-ECIT
ELECTRONICS CORPORATION OF INDIA LIMITED(A
Government of India Enterprise)
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING

JNTUHCEJ
(Recognised by UGC under section 2(F)&12(B) of UGC
Act 1956)
 DECLARATION

We hereby declare that the project entitled Electronic

voting machine submitted in partial fulfilment of the requirements for
the award of degree of Bachelor of Technology in Electronics and
Communication Engineering. This dissertation is our original work
and the project has not formed the basis for the award of any degree,
associate ship, fellowship or any other similar titles and no part of it
has been published or sent for the publication at the time of
submission.

B.Pradeep(16E31A0465)
E.Vamshi Pranay (16E31A0476)
Sushma Reddy (16E31A0497)
A.SriVarsha (16E31A0460)
Gopireddy ManiChandana (16E31A0480)
C. Premalatha(16E31A0474)
A.Saichitra(16E31A0457)
 ACKNOWLEDGEMENT

We wish to take this opportunity to express our deep gratitude to

all those who helped, encouraged, motivated and have extended their
cooperation in various ways during our project work. It is our
pleasure to acknowledgement the help of all those individuals who
was responsible for foreseeing the successful completion of our
project.
We would like to thank Mr. SRIDHARA SHETTY (AGM, CED)
and express our gratitude with great admiration and respect to our
project guide Mr. T. Naveen Kumar Reddy and Ms.
K.RAMALAKSHMI for their valuable advice and help throughout
the development of this project by providing us with required
information without whose guidance, cooperation and
encouragement, this project couldn’t have been materialized.
Last but not the least; we would like to thank the entire
respondents for extending their help in all circumstances.
B.Pradeep(16E31A0465)
E.Vamshi Pranay (16E31A0476)
Sushma Reddy (16E31A0497)
A.SriVarsha (16E31A0460)
Gopireddy ManiChandana (16E31A0480)
C. Premalatha(16E31A0474)
A.Saichitra(16E31A0457)
 ORGANIZATION PROFILE

ECIL was setup under the department of Atomic Energy in the

year 1967 with a view to generate a strong indigenous capability in
the field of professional grade electronic. The initial accent was on
self-reliance and ECIL was engaged in the Design Development
Manufacture and Marketing of several products emphasis on three
technology lines viz. Computers, control systems and
communications. ECIL thus evolved as a multi-product company
serving multiple sectors of Indian economy with emphasis on import
of country substitution and development of products and services that
are of economic and strategic significance to the country.
Electronics Corporation of India Limited (ECIL) entered into
collaboration with OSI Systems Inc. (www.osi-systems.com) and set
up a joint venture "ECIL_RAPSICAN LIMITED". This Joint Venture
manufacture the equipment’s manufactured by RAPSICAN, U.K,
U.S.A with the same state of art Technology, Requisite Technology is
supplied by RAPSICAN and the final product is manufactured at
ECIL facility.
Recognizing the need for generating quality IT professionals
and to meet the growing demand of IT industry, a separate division
namely CED has been established to impart quality and professional
IT training under the brand name of ECIT. ECIT, the prestigious
offshoot of ECIL is an emerging winner and is at the fore front of IT
education in the country.
Mission
ECIL’s mission is to consolidate its status as a valued national
asset in the area of strategic electronics with specific focus on Atomic
Energy, Defence, Security and such critical sectors of strategic
national importance.
Objectives
 To continue services to the country’s needs for the peaceful uses
Atomic Energy. Special and Strategic requirements of Defence
 and Space, Electronics Security System and Support for Civil
aviation sector.
 To establish newer Technology products such as Container
Scanning Systems and Explosive Detectors.
 To re-engineer the company to become nationally and
internationally competitive by paying particular attention to
delivery, cost and quality in all its activities.
 To explore new avenues of business and work for growth in
strategic sectors in addition to working realizing technological
solutions for the benefit of society in areas like Agriculture,
Education, Health, Power, Transportation, Food, Disaster
Management etc.
Divisions
The Company is organized into divisions serving various
sectors, national and Commercial Importance. They are Divisions
serving nuclear sector like Control & Automation Division (CAD),
Instruments & Systems Division (ISD), Divisions Serving defence
sector like Communications Division (CND), Antenna Products
Division (APD), Servo Systems Division (SSD) etc., Divisions
handling Commercial Products are Telecom Division (TCD),
Customer Support Division (CSD), Computer Education Division
(CED).
Exports
ECIL is currently operating in major business EXPORT
segments like Instruments and systems design, Industrial/Nuclear,
Servo Systems, Antenna Products, Communication, Control and
Automation and several other components.
Services
The company played a very significant role in the training and
growth of high calibre technical and managerial manpower especially
in the fields of Computers and Information Technology. Though the
initial thrust was on meeting the Control & Instrumentation
requirements of the Nuclear Power Program, the expanded scope of
self-reliance pursued by ECIL enabled the company to develop
various products to cater to the needs of Defence, Civil Aviation,
Information & Broadcasting, Tele communications, etc.
 CONTENTS

 VLSI INTRODUCTION

 PROJECT DESCRIPTION

 XILINX PROCEDURE

 RTL SCHEMATIC

 WAVEFORMS

 APPLICATIONS

 REFERENCES
 VLSI INTRODUCTION
Very-large-scale integration (VLSI) is the process of creating
an integrated circuit (IC) by combining thousands
of transistors into a single chip. VLSI began in the 1970s when
complex semiconductor and communication technologies were
being developed. The microprocessor is a VLSI device.
Before the introduction of VLSI technology, most ICs had a limited
set of functions they could perform. An electronic circuit might
consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC
designers add all of these into one chip.
The electronics industry has achieved a phenomenal growth over the
last few decades, mainly due to the rapid advances in large scale
integration technologies and system design applications. With the
advent of very large scale integration (VLSI) designs, the number of
applications of integrated circuits (ICs) in high-performance
computing, controls, telecommunications, image and video
processing, and consumer electronics has been rising at a very fast
pace.
The current cutting-edge technologies such as high resolution and
low bit-rate video and cellular communications provide the end-users
a marvellous amount of applications, processing power and
portability. This trend is expected to grow rapidly, with very
important implications on VLSI design and systems design.

VLSI Design Flow

The VLSI IC circuits design flow is shown in the figure below. The
various levels of design are numbered and the blocks show processes
in the design flow.
Specifications comes first, they describe abstractly, the functionality,
interface, and the architecture of the digital IC circuit to be designed.
Behavioral description is then created to analyze the design in terms
of functionality, performance, compliance to given standards, and
other specifications.
RTL description is done using HDLs. This RTL description is
simulated to test functionality. From here onwards we need the help
of EDA tools.
RTL description is then converted to a gate-level netlist using logic
synthesis tools. A gatelevel netlist is a description of the circuit in
terms of gates and connections between them, which are made in
such a way that they meet the timing, power and area specifications.
Finally, a physical layout is made, which will be verified and then
sent to fabrication.
DEVELOPMENT
The first semiconductor chips held two transistors each. Subsequent
advances added more transistors, and as a consequence, more
individual functions or systems were integrated over time. The first
integrated circuits held only a few devices, perhaps as many as
ten diodes transistors, resistors and capacitors, making it possible to
fabricate one or more logic gates on a single device. Now known
retrospectively as small scale integration (SSI), improvements in
technique led to devices with hundreds of logic gates, known
as medium scale integration (MSI). Further improvements led
to large scale integration (LSI), i.e. systems with at least a thousand
logic gates. Current technology has moved far past this mark and
today's microprocessors have many millions of gates and billions of
individual transistors.
At one time, there was an effort to name and calibrate various levels
of large-scale integration above VLSI. Terms like ultra-large-scale
integration (ULSI) were used. But the huge number of gates and
transistors available on common devices has rendered such fine
distinctions moot. Terms suggesting greater than VLSI levels of
integration are no longer in widespread use.
In 2008, billion-transistor processors became commercially available.
This became more commonplace as semiconductor fabrication
advanced from the then-current generation of 65 nm processes.
Current designs, unlike the earliest devices, use extensive design
automation and automated logic synthesis to lay out the transistors,
enabling higher levels of complexity in the resulting logic
functionality. Certain high-performance logic blocks like the SRAM
(static random-access memory) cell, are still designed by hand to
ensure the highest efficiency.
FPGA Design Flow Overview

The ISE® design flow comprises the following steps: design entry,
design synthesis, design implementation, and Xilinx® device
programming. Design verification, which includes both functional
verification and timing verification, takes places at different points
during the design flow. This section describes what to do during each
step. For additional details on each design step, click on a link below
the following figure.
 Design Entry

Create an ISE® project as follows:

1. Create a project.
2. Create files and add them to your project, including a user
constraints (UCF) file.
3. Add any existing files to your project.
4. Edit the design files to specify design functionality.
5. Optionally, use the Language Templates to assist in coding of
the design.
6. Edit the design test bench or waveform files to drive stimulus
for testing the design files. Optionally, do the following:
o Use the Test Bench Waveform Editor to specify stimulus
for the design.
 o Use the Language Templates to assist in coding of the test
bench.
7. Assign constraints, such as timing constraints, pin assignments,
and area constraints.

Functional Verification
You can verify the functionality of your design at different points in
the design flow as follows:

 Before synthesis, run behavioral simulation (also known as

RTL simulation).
 After Translate, run functional simulation (also known as gate-
level simulation), using the SIMPRIM library.
 After device programming, run in-circuit verification.

Design Synthesis and Verification

Click on a link below the following figure for additional details.

Design Synthesis

1. Before synthesis, run behavioral simulation (also known as

RTL simulation).
2. If you do not want to use the default settings, set the synthesis
properties.
3. Check your syntax.
4. Run the Synthesize process.
 5. Optionally, you can view your synthesized design as schematics
as follows:
o Register transfer level (RTL) schematic, which shows the
design in terms of generic symbols, such as AND and OR
gates.
o Technology schematic, which shows the design in terms
of logic elements optimized to the targeted Xilinx®
device, such as LUTs and carry logic.
6. View the Synthesis Report.

Design Implementation
Implement your design as follows:

1. Implement your design, which includes the following steps:

o Translate
o Map
o Place and Route
2. Review reports generated by the Implement Design process,
such as the Map Report or Place & Route Report, and change
any of the following to improve your design:
o Process properties
o Constraints
o Source files
3. Synthesize and implement your design again until design
requirements are met.

Design Implementation and Verification

Click on a link below the following figure for additional details.
Design Implementation
Implement your top module as follows:

1. If you do not want to use the default settings, set the

implementation properties.
2. Translate your design.
3. Optionally, run post-Translate functional simulation.
4. Map your design. Optionally, do the following:
o Run static timing analysis (for a partial timing analysis of
logic delays without routing).
o Run post-Map partial timing simulation (for a partial
simulation of logic delays without routing).
5. Place and Route your design. Optionally, do the following:
o Run static timing analysis.
o Run back annotation for the following:
 Timing information
 Pin locations
6. Review reports generated by the implementation process, such
as the Map Report or the Place and Route Report, and change
any of the following to improve your design:
o Process properties
o Constraints
o Source files
7. Optionally, consider the following advanced implementation
strategies to improve design performance:
o Manually place logic at any of the following points in the
design flow:
 Before Map
 After Map but before Place and Route
 After Place and Route
o Set the Perform Timing Driven Packing and Placement
map property
o Use Xplorer.
o Set multiple place and route passes for your design.
 8. Modify the design as necessary, simulate, synthesize, and
implement your design, as appropriate, until design
requirements are met.
9. Run timing simulation to verify end functionality and timing of
the design.

Timing Verification
You can verify the timing of your design at different points in the
design flow as follows:

 Run static timing analysis at the following points in the design

flow:
o After Place & Route
 Run timing simulation at the following points in the design
flow:
o After Map (for a partial timing analysis of CLB and IOB
delays)
 After Place and Route (for full timing analysis of block and net
delays)
Electronic voting machine
Electronic Voting Machine (EVM) is a simple electronic device used
to record votes in place of ballot papers and boxes which were used
earlier in conventional voting system. Fundamental right to vote or
simply voting in elections forms the basis of democracy. All earlier
elections be it state elections or centre elections a voter used to cast
his/her favourite candidate by putting the stamp against his/her name
and then folding the ballot paper as per a prescribed method before
putting it in the Ballot Box. This is a long, time-consuming process
and very much prone to errors. This situation continued till election
scene was completely changed by electronic voting machine. No
more ballot paper, ballot boxes, stamping, etc. all this condensed into
a simple box called ballot unit of the electronic voting machine.
Because biometric identifiers cannot be easily misplaced, forged, or
shared, they are considered more reliable for person recognition than
traditional token or knowledge based methods. So the Electronic
voting system has to be improved based on the current technologies
viz., biometric system. This article discusses complete review about
voting devices, Issues and comparison among the voting methods and
biometric EVM. In order to cast your vote, you must present
your Voter ID and your name should appear in the Electoral
Rolls. The officer in charge will then press a button that enables
you to vote. You can then enter the polling booth and cast your
vote. Once you have pressed a button to vote, your vote is
recorded. Pressing the button again, how many times you want,
will not record another vote. The machine will be locked till the
officer in charge sends in the next voter and enables him to
vote. This ensures one person equals one vote.
Once the last voter has cast their vote, the officer in charge will
press a button labelled “Close”. The EVM will not accept any
votes after this. The Balloting unit will be disconnected from the
Controlling unit and both units will be kept separately.
After the polls are closed, the presiding officer will give each
polling agent the accounts of the recorded votes. After counting
votes, the account of voters registered will be tallied against the
votes counted. Any discrepancies can be pointed out by the
counting agents. After the counting, the Results button can be
pressed to display the result.
There is also a safety measure provided to prevent the result
button from being pressed before the counting of votes begins.
The button cannot be pressed till the “Close” button is pressed.
The button is also sealed and hidden inside. This can be
accessed only at the counting center in the presence of an
officer designated to this task. With these measures and
features, the EVMs can be sealed and the votes can be
counted on a later date even weeks or months after collecting
the polls.
EVMs also have added security such as CCTV coverage,
storage in strong rooms, transport under armed guards, and
24/7 armed police guard.
Design and technology

Ballot Unit (left), control unit (right)

An EVM consists of two units, a control unit, and the balloting
unit.[32] The two units are joined by a five-meter cable. Balloting unit
facilitates voting by a voter via labeled buttons while the control unit
controls the ballot units, stores voting counts and displays the results
on 7 segment LED displays. The controller used in EVMs has its
operating program etched permanently in silicon at the time of
manufacturing by the manufacturer. No one (including the
manufacturer) can change the program once the controller is
manufactured. The control unit is operated by one of the polling booth
officers, while the balloting unit is operated by the voter in privacy.
The officer confirms the voter's identification then electronically
activates the ballot unit to accept a new vote. Once the voter enters
the vote, the balloting unit displays the vote to the voter, records it in
its memory. A "close" command issued from the control unit by the
polling booth officer registers the vote, relocks the unit to prevent
multiple votes. The process is repeated when the next voter with a
new voter ID arrives before the polling booth officer.[32]
EVMs are powered by an ordinary 6 volt alkaline
battery[33] manufactured by Bharat Electronics
Limited, Bangalore and Electronics Corporation of India
Limited, Hyderabad. This design enables the use of EVMs throughout
the country without interruptions because several parts of India do not
have the power supply and/or erratic power supply. The two units
cannot work without the other. After a poll closes on a particular
election day, the units are separated and the control units moved and
stored separately in locked and guarded premises.
Both units have numerous tamper-proof protocols. Their hardware, by
design, can only be programmed once at the time of their manufacture
and they cannot be reprogrammed. They do not have any wireless
communication components inside, nor any internet interface and
related hardware. The balloting unit has an internal real-time clock
and a protocol by which it records every input-output event with a
time stamp whenever they are connected to a battery pack. The
designers intentionally opted for battery power, to prevent the
possibility that the power cables might be used to interfere with the
reliable functioning of an EVM.
An EVM can record a maximum of 3840 (now 2000) votes and can
cater to a maximum of 64 candidates. There is provision for 16
candidates in a single balloting unit and up to a maximum of 4
balloting units with 64 candidate names and the respective party
symbols can be connected in parallel to the control unit.[32] If there are
more than 64 candidates, the conventional ballot paper/box method of
polling is deployed by the Election Commission.[32] After a 2013
upgrade, an Indian EVM can cater to a maximum of 384 candidates
plus "None Of The Above" option (NOTA).[6]
The current electronic voting machines in India are the M3 version
with VVPAT capability, the older versions being M1 and M2. They
are built and encoded with once-write software (read-only masked
memory) at the state-owned and high-security premises of the Bharat
Electronics Limited and the Electronics Corporation of India
Limited.[6][35] The inventory of election EVMs is securely tracked by
the Election Commission of India on a real-time basis with EVM
Tracking Software (ETS). This system tracks their digital verification
identity and physical presence. The M3 EVMs has embedded
hardware and software that enables only a particular control unit to
work with a particular voting unit issued by the Election Commission,
as another layer of tamper-proofing. Additional means of tamper
proofing the machines include several layers of seals. Indian EVMs
are stand-alone non-networked machines.[36][37]
Procedure to use
The control unit is with the presiding officer or a polling officer and
the balloting Unit is placed inside the voting compartment. The
balloting unit presents the voter with blue buttons (momentary switch)
horizontally labeled with corresponding party symbol and candidate
names. The Control Unit, on the other hand, provides the officer-in-
charge with a "Ballot" marked button to proceed to the next voter,
instead of issuing a ballot paper to them. This activates the ballot unit
for a single vote from the next voter in the queue. The voter has to
cast his vote by once pressing the blue button on the balloting unit
against the candidate and symbol of his choice.
As soon as the last voter has voted, the Polling Officer-in-charge of
the Control Unit will press the 'Close' Button. Thereafter, the EVM
will not accept any votes. Further, after the close of the poll, the
Balloting Unit is disconnected from the Control Unit and kept
separately. Votes can be recorded only through the Balloting Unit.
Again the Presiding officer, at the close of the poll, will hand over to
each polling agent present an account of votes recorded. At the time
of counting of votes, the total will be tallied with this account and if
there is any discrepancy, this will be pointed out by the Counting
Agents. During the counting of votes, the results are displayed by
pressing the 'Result' button. There are two safeguards to prevent the
'Result' button from being pressed before the counting of votes
officially begins. (a) This button cannot be pressed till the 'Close'
button is pressed by the Polling Officer-in-charge at the end of the
voting process in the polling booth. (b) This button is hidden and
sealed; this can be broken only at the counting center in the presence
of designated office.
 Xilinx procedure:

Getting Started You first need to install Xilinx ISE WebPACK on

your PC or laptop. The latest version of the software is currently 11.1,
which is what we use in this tutorial. It is available as a free download
from www.xilinx.com. This tutorial uses the project example1-
Verilog, from another Digilent tutorial on the Xilinx ISE WebPACK
tools. This project is available as a free download from
www.digilentinc.com.
Starting Sample Project
First, open Project Navigator by selecting Start > Programs > Xilinx
ISE Design Suite 11 > ISE > Project Navigator. Once the application
opens, specify an ISE project file by selecting File > Open Project and
navigate to the appropriate directory to choose your project. In this
tutorial, we use example1-Verilog.xise Once the project is open, add a
Verilog Test Fixture source file to your project. In this source file,
you are able to define circuit inputs over time so the simulator knows
how to drive the outputs. To add the source file, right-click on the
device in the Sources window and choose the New Source option. In
the New Source wizard, choose VHDL test fixture for the source type
and enter a meaningful name for the file. We call ours
“example1_test_verilog”.
After clicking Next, the following dialog box asks you to select the
source file you want to associate with the given test fixture file. This
dictates which source file you actually run the simulation on. In this
tutorial, we run the simulation on the top-level module of the
example1- VHDL design (circuit2.v).

Complete the new source file creation by clicking Next and Finish. To
view and edit the Verilog test fixture, you first need to change the
selected option in the sources drop-down menu from Implementation
to Behavioral Simulation as follows:
 Once this option is selected, the sources panel changes slightly so
that example1_test_verilog.v is the first source file under the device.
The options under the processes panel change so that the only

option is the ISim Simulator (sic).

Verilog Test Fixture
Open the Verilog test fixture in the HDL editor by double-clicking it
in the Sources window. If you examine the contents of the new source
file you will see that, like a standard VHDL source file, the Xilinx
tools automatically generate lines of code in the file to get you started
with circuit input definition. This generated code includes: • a
Comment block template for documentation • a Module statement • a
UUT instantiation • input initialization Scroll down to the end of the
test fixture file to see the “initial begin” and “end” statements of the
module
The simplest way of defining input stimulus in a Verilog test fixture is
to use timing controls and delay, denoted by the pound symbol (#).
For example, the statement #100 present in example1_test_verilog.v
tells the simulator to delay for 100 ns. Therefore, any statement made
after this timescale statement will occur after the 100 ns delay time.
It’s important to note that the timescale for the delay is defined by the
`timescale statement at the beginning of the file. By default, the
Xilinx tools define the timescale as 1ns/1ps, which indicates that the
units are in nanoseconds while calculated time precision is 1
picoseconds. To add further input stimulus, we will add the several
more statements until the completed verilog test fixture looks like
this:
Note that the assignment statements take place in the simulation after
each delay. The inputs then stay at their respective states until
assigned otherwise. Now, save the test fixture and select it in the
sources window. Go to the processes window, expand the ISim
Simulator (sic), and double-click Simulate Behavioral Model.
ISE Simulator
Running the Simulate Behavioral Model process causes the ISim
window to appear.

Some features of this window include: 1. a Source Files panel where

source files to be viewed can be selected 2. an Objects panel where
different signals can be added to the simulation 3. a simulation panel
where the state of signals can be observed 4. a Console panel We first
use the Zoom to Full View tool to see the full view of the simulation,
which is located to the right of the magnifying glasses on the
simulation panel toolbar.
This displays the useful part of the simulation. Use the magnifying
glass with the plus sign to zoom in further, as follows

On the left side of the simulation panel there are columns labeled
Name and Value:

For a given item on these columns, you can right-click and choose
options to delete, rename, or change the color of the signal color.
You may also use the scroll bars to see the simulation at different
times as well as observe more signals if you have a larger design. The
simulation control option on the top right side of the ISim toolbar
contains the following features:

1. Restart simulation by stopping it and setting time back to 0

2. Run simulation until all events are executed.
3. Run simulation for a specified time indicated by the Value box.
4. Amount of time and unit simulation is to run for.
5. Run simulation for one executable HDL instruction at a time.
6. Pause simulation.
7. Stop simulation.
Rtl schematic
Wave forms
 APPLICATIONS

This could be used for voting purpose at any required place

REFERENCES
[1].http://www.xilinx.com/itp/xilinx10/books/docs/qst/qst.pdf
[2].Digital System Design Using V.H.D.L by Charles H. Roth, JrChapter.2, Chapter 3
[3]. Digital System Design Using V.H.D.L by Charles H. Roth, Jr
Appendix A (VHDL Language Summary)
[4]. www.xilinx.com ISE Tutorial in Depth Chapter 2, Chapter 3
[5]. www.xilinx.com ISE Tutorial in Depth Chapter 4,Chapter 5,Chapter 6
[6]. Benjamin B., Bederson, Bongshin Lee., Robert M. Sherman., Paul S., Herrnson, Richard G. Niemi., "Electronic Voting System Usability
Issues", In Proceedings of the SIGCHI conference on Human factors in computing systems, 2003.
[7].Rubin A.D. "Security considerations for remote electronic voting", ACM, 5(12):39-44, Dec.2002.