Course Handbook EEE344 DSD - FA19
Course Handbook EEE344 DSD - FA19
Course Handbook EEE344 DSD - FA19
Reference Books
1. Digital Electronics and Design with VHDL by Volnei A. Pedroni
Theory CLOs:
• CLO 1: Analyze and Design the working of advanced combinational and sequential logic-based
systems using the classical principals of digital logic design. (PLO3-C5)
• CLO 2: Design of digital systems in a hierarchical and top-down manner using register-transfer
logic (RTL) approach. (PLO3-C5)
Lab CLOs:
• CLO3: To design the digital systems based on HDL modelling techniques using VHDL. (PLO3-C5)
• CLO4: Reproduce the response of the designed digital systems using the software tool and hardware
platform (PLO5-P3)
• CLO5: To explain and write effective lab reports of experiments performed during lab (PLO10-A3)
16 Marks Breakup
Theory
Quizzes (minimum 4) 15%
Homework assignments (minimum 4) 10%
S-I 0.5*(S-I Exam result) + 0.5* (average of lab evaluation of Lab 1-4)
S-II 0.5*(S-II Exam result) + 0.5*[ (average of lab evaluation of Lab 5-8) * 1.5]
Terminal 0.5*(Terminal Exam result) +0.25*[(average of lab evaluation of Lab 9-12) *5] + 0.10*[(average of lab
evaluation of Lab 5-8)*5] + 0.15*[(average of lab evaluation of Lab 1-4)*5]
LAB CLO2
LAB CLO3
LABCLO1
CLO 1
CLO2
Activity
A1
A2
A3
A4
A5
C1
C2
C3
C4
C5
C6
P1
P2
P3
P4
P5
P6
P7
Quiz 1 X X
Quiz 2 X X
Quiz 3 X X X
Quiz 4 X X
Assignment 1 X X
Assignment 2 X X
Assignment 3 X X
Assignment 4 X X X
S-I X X
S-II X X X
Lab S-I X X X X
Lab S-II X X X X
Terminal X X X
Lab Terminal X X X
Lab Assignments/ Lab Reports/
X X X X X X
Lab Performance
PLO10
PLO11
PLO12
PLO1
PLO2
PLO3
PLO4
PLO5
PLO6
PLO7
PLO8
PLO9
A1
A2
A3
A4
A5
C1
C2
C3
C4
C5
C6
P7
P1
P2
P3
P4
P5
P6
CLOs
CLO1 X X X X X X
CLO2 X X X X X X
CLO3 X X X X X X
CLO4 X X X X
CLO5 X X X X
PLO 1, 4, 6 , 7 , 8, 9, 11, 12: These PLOs are not directly addressed in this course.
Introduction to VHDL and Altera Quartus with the design of Full Adder
OBJECTIVES
• Familiarize students with VHDL (VHSIC Hardware Description Language) and
1 Quartus.
To design the combinational and sequential circuit components using VHDL and show
output on the FPGA board
OBJECTIVES
• To understand the simulation of combinational logic problems using VHDL.
2 • Quartus shall be used for the compilation and functional verification of VHDL
design files.
To design the counter and sequence detector using VHDL and reproduce the sequence on
the FPGA board.
OBJECTIVES
To design the complex counter and vending machine using VHDL and show the results on
the FPGA board
OBJECTIVES
5 • To design a complex design i-e complex counter and vending machine in VHDL
with the help of Finite State Machines
To design the array and binary multiplier using VHDL and reproduce the output on the
FPGA board
OBJECTIVES
• To design an array multiplier (combinational logic) in VHDL and Binary
6
Multiplier (shift and add approach)
To design the signed binary multiplier using Booth’s algorithm in VHDL and show the
results on FPGA board
OBJECTIVES
• To design and test signed binary number multiplier using Booth’s algorithm
7
To design the binary and signed binary divider using VHDL and reproduce output on
FPGA board
OBJECTIVES
• To design binary divider a signed binary number divider using VHDL
To design the memories (RAM and ROM) using VHDL and reproduce output on FPGA
board
OBJECTIVES
• To design and test RAM and ROM using VHDL
10
To design the keypad scanner using VHDL and show the output on the FPGA board
OBJECTIVES
11 • To design a scanner for a telephone keypad using VHDL
To design the finite impulse response (FIR) filter using VHDL and reproduce output on
FPGA board
OBJECTIVES
• To design and test different architectures of Finite Impulse Response (FIR) filter
12
To design the fast fourier transform (FFT) processor using VHDL and show the output on
the FPGA board
OBJECTIVES
• To design and test a 16-point Radix-2 FFT processor
13
To design the video graphics array (VGA) controller using VHDL and reproduce output
on FPGA board
OBJECTIVES
• To design and implement a VGA controller to display a certain pattern on a VGA
14 monitor interfaced with an FPGA.