Semeconductor
Semeconductor
Semeconductor
w
-y fits concise introduction to semiconductor fabrication technology covers everything
' professionals need to know, from crystal growth to integrated devices and circuits.
Fill
Throughout, the authors address both theory and the practical aspects of each major
fabrication step, including crystal growth, silicon oxidation, photolithography, etching,
diffusion, ion implantation,
v ^
Fundamentals of
Semiconductor Fabrication
Fundamentals of
Semiconductor Fabrication
GARY S. MAY
Motorola Foundation Professor
School of Electrical and Computer Engfncemrj,
Georgia Institute of Techiwlogy
Atlanta. Georgia
SIMON M. SZE
( MC Chair Professor
Sational Chiao Tung Cnii^rsittj
National Xano Device laboratories
Hsinchu, Taiwan
WILEY
JOHN WILEY & SONS, INC.
Preface
under-
da-m-
»calengineering, and materials science. The book
can be used conveniently in a
semester-length course on integrated circuit
fabrication. Such a course am or may not
lieaccompanied by a ^requisite laboratory. Tl.e
text can also serve as a reference for
practicing engineers and scientists in the
semiconductor Industry.
Chapter l gives a brief historical overview of major
semiconductor devices and ke%
technology- developments, as well
as an introduction to basic fabrication steps.
Cliapte'r
2 deals with crystal growth techniques. Tl.e next several chapters are
organized accord-
ing to a typical fabrication sequence. Chapter
3 presents silicon oxidation. HiotoUdiographv
and etching are discussed in Chapters 4 and
5. respectively Chapters 6 and 7 pr.-sent
the primary techniques for the introduction of
dopants: diffusion and ion implantation
he final Chapter on individual process steps.
Chapter 8. covers various methods ofthm
film deposition. The final three chapters
focus on broad, summ.itise topic*. Chapter 9
ties the individual process steps
together by presenting the process flows for critical
pro-
cess technologies integrated devices,
and mieroelectrical mechanical systems M E MS
Chapter 10 introduces high-level integrated circuit
manufac turing issues, including elec-
trical testing packaging, process
control, and yield. Finallv. Chapter 1 1 <!,v usses
the future
outlook and challenges for the semiconductor
industry.
Each chapter begins with an introduction and a list of learning goals and concludes
With a summary ofimportant concepts. Solved example problems
are pn.v .
I,,
out. and suggested homework problems appear at
the end of the chapter The con !
Silicon Oxidation 41
5.1.2 Silicon Dioxide Etching 87
5.1.3 Silicon Nitride and Poh'sihcon
3. 1 Thermal Oxid ation Process 42 Etching S8
3.1.1 Kinetics of Growth 42 5.1.4 Aluminum Etching SS
3.1.2 Thin Oxide Growth 49 5.1.5 Gallium Arsenide Etching SS
si
sdi > Contents
53 pi) Etching 89
CHAPTER 8 9.5 MEMS Technology* 212 APPENDIX A
Ski Plasma Fundamentals 90 Film Deposition 144 9.5.1 Bulk Micromachining 215 List of Symbols 265
5.2.2 Etch Mechanism, Plasma 9.5.2 Surface Micromachining 215
8.1 Epitaxial Growth Techniques 144
Diagnostics, and End-Point
8.1.1 Chemical Vapor Deposition 145 9 5.3 UGA Process 215 APPENDIX B
Control 91 9.6 Process Simulation 218 International System
8.1.2 Molecular Beam Epitaxy 148 of Units (SI Units) 267
5.2.3 Reactive Plasma Etching 9.7 Summary 223
8.2 Structures and Defects in Epitaxial
Techniques and
Layers 152
References 223 APPENDIX C
Equipment 93 Problems 224 Unit Prefixes 269
8.2.1 Lattice-Matched and Strained-
5.2. 1 Reactive Plasma Etching
Layer Epitaxy 152
Applications 97 CHAPTER 10 APPENDIX D
8.2.2 Defects in Epitaxial Layers 153
5s3 Etch Simulation 101 IC Manufacturing 226 Greek Alphabet 271
8.3 Dielectric Deposition 155
5.4 Summary 102
8.3.1 Silk-on Dioxide 156 10. Electrical testing 227
References 103
8.3.2 Silicon Nitride 160
1
APPENDIX E
10.1.1 Test Structures 227
Problems 103 Physical Constants 273
8.3.3 Low-Dielectric-Constant 10.1.2 Final Test 228
Materials 162 10.2 Packaging 228
CHAPTER 6 APPENDIX F
8.3.4 High-Dielectrie-Constanf 10.2.1 Die Separation 230
Diffusion 105
Materials 164
Properties of Si and GaAs at 300 K 275
10.2.2 Package Types 230
6.1 Basic Diffusion Process 106 8.4 Polysilicou Deposition 165 10.2.3 Attachment
APPENDIX G
6.1.1 Diffusion Equation 107 8.5 Metallization 167 Methodologies 232
Some Properties of the Error Function 277
6.1.2 Diffusion Profiles 109 8.5.1 Physical Vapor Deposition 167 10.3 Statishe.il Process Control 237
6. 1 .3 Evaluation of Diffused 8.5.2 Chemical Vapor Deposition 168 10.3.1 Control Charts for
APPENDIX H
Layers 113 8.5.3 Aluminum Metallization 169 Attributes 237
Basic Kinetic Theory of Gases 2S1
6.2 114
Extrinsic Diffusion 8.5.4 Copper Metallization 173 10.3.2 ( tatad ( fcaitS for Variables 239
6.2.1 Concentration-Dependent 8.5.5 Silicide 175 III Statistical Experimental Design 242
1
APPENDIX I
Diffu.sivitv 115 8.6 Deposition Simulation 177 10.4.1 Comparing Distributions MS SUPREM Commands 283
6.2.2 Diffusion Profiles 117 8.7 Summary 177 10.4.2 Analysis ofVariance 243
6.3 Literal Diffusion 118 References 179 10.4 3 Factorial Designs 246 APPENDIX J
BA Diffusion Simulation 120 Problems 180 10.5 Yield 250
Running PROLITH 287
6.5 Summary 121 10.5 1 Functional Yield 250
References 122 CHAPTER 9 10.5.2 Parametric Yield 254
APPENDIX K
Problems 122 Process Integration 182 10.0 Computer-Integrated
Percentage Points of the t Distribution 2S9
Manufacturing 256
9.1 Passive Components 184
CHAPTER 7 10.7 Summai) 257 APPENDIX L
9.1.1 The Integrated Circuit
Ion Implantation 124 References 257 f Distribution 291
Resistor 184 Percentage Points of the
Problems 258
7 .1 Range of Implanted Ions 125 9. 1 .2 The Integrated Circuit
7.1.1 Ion Distribution 125 Capacitor 185 Index 297
CHAPTER 11
7.1.2 Ion Stopping 127 9. 1 .3 The Integrated Circuit
Future Trends and Challenges 259
7.1.3 [on Channeling 130 Inductor 187
7.2 Implant Damage and Annealing 131 9.2 Bfpolar Technology 188 11. 1 Challenges for Integration 259
7.2.1 Implant Damage 131 9.2.1 The Basic Fabrication U.I.] Ultrashallow Junction
7.2.2 Annealing 134 Process 189 Formation 261
7.3 Implantation-Related Processes 136 9.2.2 Dielectric isolation 192 11.1.2 Ultimthin Osfde 261
7.3.1 Multiple Implantation and 9.2.3 Self-Aligned Double-PoH/silicon 11.1.3 Silicide Formation 261
Masking 136 Bipolar Structures 193 11.1.4 New Materials for
7.3.2 Tilt-Anglr Ion Implantation 138 9.3 MOSFET Technology 196 Interconnection 261
7.3.3 lligli-Energ> and High-Current 9.3.1 The Basic Fabrication U.1.5 Power [imitations 261
implantation 139 Process 196 ll L.6 sol Integration 262
7. 1 Ion Implantation Simulation 140 9.3.2 Memory Devices 100 1 1 2 System-on-a-Chlp 262
7J5 Summary mi 9.3.3 CMOS Technology
203 11.3 Summarj 264
References142 9.3.4 BiCMOS Technology 210 References 2<>i
Problems 142 9.4 MESFET Technology 212 Problems 264
4 Chapter 1. Introduction
1.3 Semiconductor Process Technology < 5
The most important device for adv anced integrated circuits is the M<
)SKKT (metal-
One important micrmyave devices were invented
OOdde-semiconductOr field-effect transistor), which wax reported In Idling and Alalia" «mm***W*m*m
The
m lOW. Figure 1.3 shows the lust device using a thermal!) ovidi/ed silicon substrate.
thickness of 100 nui ( 1 am = 10" em).
' »>
1 > M '
I ED is used extensively in suc h millimeter-wave apphcalioiU
device has a gate length ..120 urn and a gate oxide
The two keyholes arc the source and drain contacts, and the top elongated area is the .
I
tTZv^T rr"
IMlAHdrnde
til s«. M-
a,,,,rwk A
1
mitrowave
i
a. 11) „uaslus,ol se.e
™ The
|hv j uh , t(l „e.al.'"i„ 1965.
^ 23IMPATT
BS
dev. .:
fCW power h*
been scaled down tothedeep^bmicron regime, the choice of silicon and he n nail v grown t
nuenc^ at milKmeter.wws
siluon dioxide used in the first MOSFET remains the most important comhination of
materials The MOSFET and related integrated circuits now constitute about 009; of the
O^*™., l-N ESFET(n 1 etal-s ( m.iconduc,orfi<.l<hefie ( ,tr.,nsi,or).S
oy Mead m 1 JW,. It Is a key device for monolithic
microwave integrated circuits M MIC)
semiconductor device market. An ultrasmall MOSFET with a channel length of 15 nm An important semic-onductor memory device was invented l.v I
its stored
one
I
'
first achieved lasing in semiconductors. In 1963. Kroemer and tional MOSI- FT. the major difference is the
17
addition of a "(loath which semiper-
All.-rov and K.t/arinov proposed the heteixistructure laser. These proposals laid the foun-
manent charge storage is possible. Because of its attributes
of nonvolatility. high device
dation tor modem laser diodes, which can be operated continuously at room tempera- density, low power consumption, and electrical rewritabilitv
i.e.. the stored charge can
ture. Laser diodes are the ke\ components for a wide range of applications, including be removed by applying voltage to the control gate the N YSM has
become the domi- ,
digital video disks, optical-fiber communication, laser printing, and atmospheric pollu- nant memory lor portable electronic systems such as the cellular
phone, notebook com-
tion monitoring. puter, digital camera, and smart card.
A limiting case of the floating-gate nonvolatile memon is the single-electron mem-
ory cell (SEMC). which obtained by reducing the length of the floating gate to ultra-
is
Small dimensions (e.g.. 10 nm). At this dimension, when an electron moves into the floating
gate, the potential of the gate will be altered so that it will pre-. , „t the entrance of another
electron. The SEMC is the ultimate floating-gate memory cell, since we need only one
electron lor information storage. The operation of a SEMC at room temperature Was first
demonstrated by YanO et al* in 1994. The SEMC can serve as the lusis for the most
advanced semiconductor memories, which can contain over one trillion bits.
The charge-coupled device (CCD) was invented by Boyle and Smith in 1970. CCD
is used extensively in video cameras and in optical sensing applications. The resonant tun-
neling diode(RTD) was first studied by Chang et al." in 1974. RTD is the basis for most
quantum-effect devices, which offer extremely high density, ultrahigh speed, and enhanced
functionality, because it permits a greatly reduced number of devices to perform B given
circuit function. In 19S0. MODFET (modulation-doped field-
Minima et al."' developed the
elTect transistor). With the proper selection of heterojmiction materials, the MODFET is
Many important semiconductor technologies haw been derived from processes invented
furnace w as pioneered by
centuries ago. For example, the growth of metallic crystals in a
Africans living on the western shores of Lake Victoria
more than 2000 years ago.-' This
preheated forced-draft furnaces. Another
process was used to produce carbon steel in
Figure U The first „„ (..Uud, -semiconductor fifld-effeet
.
transistor. I
Photograph
r courtesv of example is the lithographv process, which was invented in 1798.
In this original process,
Bell Laboratories.) ° ' 1
This section considers
stone plate
the pattern, Or image, was transferred from a
(fttno).
1.3 Semiconductor Procoss Technology « 7
6 » Cn»pt«r 1 Introduction
was developed by Bndgmair in 1925. form a thin layer of semiconductor materials on surface oi a crystal that
^Jers an- produced \nother growth technique
tin- lias a latti< e
has l»een used extensively lor the growth of gallium arsenide structure identical to that of the crystal. This method is important lor the Improvement
71 „• BriArman technique
tin- semiconductor properties of device performance and the creation of novel device structures. In 1959, a rudimen-
ud related compound semiconductor crystals. Although
studied sua,- early 1940. the study of senneonductor com- tary integrated circuit was made bj Kilby. It contained one bipolar transistor, three resis-
of silicon have been widely
long time. In 1952. Welker* noted that gallium arsenide and tors, ami one capacitor, all made in germanium and connected by wire bonding a hybrid
pounds uas neglected for a
(dated Ul-V compounds were semiconductors. He was able to predict their characteiv circuit. Also in 1959. Noyi e proposed the monolithic IC li\ fabricating all devices in a
by Fick" 1S55. The idea of using diffusion orated aluminum layer over the entire oxide surface using the lithographic technique. These
ing. Basic diffusion theory was considered
in
conductivity silicon was disclosed in a patent in 1952 inventions laid the foundation for the rapid growth ol the microelectronics industry.
techniques to alter the type of in
process w-as applied to semiconductor device The Hoemi in 1960. In this process, an oxide layer
planar process was dev loped by
e
'
by Pfana u -
1957, the ancient lithography
Heiisedjjbotosensttrve^etch-iesistanl polymers (photoresist) for is formed on semiconductor surface. With the help of a lithography process, portions
a
fabrication b\ Andrus
industry. The con- of the oxide can be removed and windows cut in the oxide. Impurity atoms will dilluse
pattern transfer. Lithography is a key technology for die semiconductor
only through the exposed semiconductor surface, and p-n junctions will form in the oxide
tinued growth of the industry has been the direct result of improved
lithographic tech-
representing over 3-5% window areas.
nology. Lithography is also a significant economic factor, currently
of IC manufacturing costs.
V* the compVutv «'l «!'« K increased, technology has moved from NMOS ui-channel
MOSFK1 MOSKKT). which einplovN both
tot MOS-cnmpIeincntarv
NMOS ami P.MOS
i^duuuH-l Ml >SFI form the logic elements. The CMOS concept was proposed by
I to
VI mtasandSah' in 1963. The adv antage of CMOS technology is that logic elements draw
to another ie.g.. from 0 to 1
ugnificant current only during the transition from one state
and draw vm
little current k-rween transitions. allowing
power consumption to be min-
Imueil CMOS
technology is die dominant technology for advanced ICs.
In 1%7 an important two-element circuit, the dynamic random access memory
DRAM was invented by Dennard." The memor\ -evil contains one MOSFETand one
i Lu _. -st.the M< )SFKT serves as a switch to charge or discharge the capac-
,r.«ge r.ipu iter
itor Uthough is volatile and consumes relatively high power, we expect that
a DRAM
DRAMs will coutinue to be the first choice among various semiconductor memories for
nonportable electronic- sv>.teiiis in the foreseeable future.
To improve device performance, the polysilicon self-aligned gate process was pro-
posed b\ Kerwin et aL* in 1969. This process not only improved device reliability but
n-din ed p,ir.isitic capacitances. Also in 1969. the iiietaloruanic- c hemic al vapor depo-
1
sition i MQCVD) method was developed by Manasevit and Simpson. '
Tliis is a very impor-
tant epitaxial growth technique lor compound semiconductors such as CaAs.
As the device dimensions were reduced, the dry etching technique was developed
to replace wet chemical etching for high-fidelity pattern transfer. This technique vv.is ini-
tiatedby Irving etal." in 1971 using a CF/O, gas mixture toetch silicon wafers. Another
5
important technique developed in the same year by Clio* was molecular beam epitaxy.
This t.-c lnuqiie has the advantage of near-perfect vertical control of composition and dop-
ing clown to atomic- dimensions. It is responsible for the creation of numerous photonic
devices and quantum-effect devices.
In 1971. the firstmicroprocessor was made by Hoff et al..'*' who put the entire cen-
tral processing unit (CPU) of a simple computer on one chip. It was a four-bit micro-
processor (Intel 4004 in Figure 1.5. with a chip size of 3 mm by 4 mm. and it
1. shown
contained 2300 MOSFETs.
was fabricated by a p-channcl porysilicon gate process using
It
an S-jim design rule. This microprocessor performed as well as those in $300,000 IBM
—
computers of die earl)- 1960s each of which needed a CPU the size of a large desk. This
Figure 1.5 The first mkroprocessor* (Photograph courtesy of Intel Corp.)
was a major breakthrough for the semiconductor industry. Currently, microprocessors
constitute die largest segment of the industry.
Since the early 1980s, many new technologies have been developed to meet the At that rate, the minimum feature length will shrink to about 50 nm in the year 2010.
requirements of ever-shrinking minimum feature lengdis. Three kev technologies are Device miniaturization results in reduced unit cost per circuit function. For example, the
trench isolation, chemical mechanical polishing, and copper interconnect. Trench isola- a )st of memory chips has halved even- 2 years for successive generations of DRAM
pe r bit
tion technology was introduced by Rung et al.'~ in 19S2 to isolate devices. This CMOS circuits. As device dimensions decrease, the intrinsic- switching time
decreases. Device
approach eventually replaced all other isolation methods. In 19S9. the chemical mechan- speed has improved by four orders of magnitude since 1959. Higher speeds lead to
*s
func tional throughput rates. In the future, digital ICs will be able to
ical polisliing methcxl was developed by Davari et for global planarization of the inter- per-
al expanded [G
layer dielectrics. This is a key process for multilevel metallization. At submicron dimensions, form data processing and numerical computation at terabit-per-seeond rates. As devices
a widely known failure mechanism is electromigration, which is the transport of metal becomes smaller, they consume less power. Therefore, device miniaturization also reduces
dissipate d per logic gate has
ions through a conductor due to the passage of an electrical current. Although aluminum the energy used for each svvitching operation. The energy
has been used since die early 1960s as interconnect material, it suffers from decreased bv over one million times since 1959.
electromi-
gration at high electrical current. Copper interconnect was introduced in 1993 by Figure 1.6 shows the exponential increase of the actual DRAM densit) versus the year
faatnre length of an integrated circuit has l>een reduced at a rate of about will reach 100 C1P (billion instruc
tions per second) in the vear 2010.
|
13% per year." continue-, we
1.4 Basic Fabrication Steps < II
-
IV
Figure 1.6 Exponential increase of dynamic random access memory density versus year based
on the Semiconductor Industry .-Vssociation madmap.'"
1950 1970 1990 2010 2030
Year
11
Figure l.S illustrates the growth curves for different technology drivers. At the lxrgin-
ning of the modem electronic era (1950-1970). the bipolar transistor was the technol-
ogy driver. From 1970 to 1990. the DRAM and the microprocessor based on MOS devices
were the technology drivers because of the rapid growth of personal computers arid
advanced electronic systems. Since 1990. nonvolatile semiconductor memory has been
the technology driver, mainly because of the rapid growth of portable electronic systems.
1.4.1 Oxidation
The development of a high-quality silicon dioxide (SiO.) has helped to establish the dom-
functions as an insulator
inance of Si in the production of commercial ICs. Generally. SiO.
IS Ckapter I. lntroducl)On
Basic Fabrication Steps
1.4 « 13
Dopant SB
or
accelerated impurity loin
1231
n -SI
(b)
n-Si
Metal
(0
Figure 1.10 wafer after the development, (b) Tin- wafer ifter SiO. removal (e) the
[a) Tin-
complete lithographic process <l A p-n junction is formed in the dffiustao
final result after a
or implantation process. (»') The wafer after metallization, if) A p-fl Junction after the complete
processes.
Figure 1.9 a) A bare n-rype Si wafer, (b) An oxidized Si wafer by drv or wet oxidation.
.-
1
Application tif resist d Resist exposure through the mask.
Another technology, called photolithography, is used to define the geometry of the p-n
in a number of device structures or as a barrier to diffusion or implantation during device junction. After the formation of Si0 2 . the wafer is coated with an ultraviolet (UV)
fabrication. In the fabrication of ap-n junction (Fig. 1.9). the SiO, film is used to define light-sensitive material called a photoresist, which is spun on the wafer surface by a high-
the junction area. the w afer baked at aboul S0°C to 100°C to drive
speed spinner. Afterward (Fig. 1.9r). is
There are two SiO, growth methods, dry and wet oxidation, depending on whether the solvent out of the resist and to harden the resist for improved adhesion.
dry (SygeQ or water vapor is used. Dry oxidation is usually used to form thin oxides in shows the next step, which is to expose the wafer through a patterned
Figure 1.9rf
I fa ice structure because of its good Si-Si0 interface characteristics, whereas wet oxi- IV light source. The exposed region of the photoresist-coated wafer under-
2 mask using a
dation used for thicket layers because of its higher growth rate. Figure 1.9a shows a
is
goes a chemical reaction depending on the type of resist. The area
exposed to light becomes
section of a bare Si wafer reach- for oxidation. After the oxidation process, a SiO, layer is The polymerized region remains whet,
polymerized and difficult to remove in an etchant.
formed all over the wafer surface. For simplicity. Figure 1.9b shows only the upper sur-
the wafer is placed in a developer, whereas the unexposed region (under the opaque area)
face of an oxidized wafer. More details on oxidation may be found in Chapter 3. dissolv es and washes away.
14 » Chapter I Introduction
References < 15
Figure LQa shows the wafer after the development. Tin- wafer is again baked to
l
•"•'" MX- **ls with . key R fabric*
ia)°C to 160°C for 20 minutes to enhance the adhesion and improve tin- resist. iikv to
1 proce* *ep |
w ,,,.,„.,„,.
thf subsequent etching process. Then, an etch using buffered hydrofluoric acid (HF)
„f
'nth.'
on «! H
original
s
'
literature. I owever, a few
• '
M
important paper, are
presented in a dear and coherent I.lsI
i ii
listed
EXiJKS
„ the end ofe
remows the unprotected SiO, surface (Fig. 1.10b). Lastly, the resist is stripped awaj b) chapter for reference and for further reading.
„
a chemical solution or an oxygen plasma system Figure 1. 10c shows the final result of a
region without oxide (a window) after the lithography process. The wafer is now ready
tor fanning the p-fl junction b) a diffusion or ion implantation process. Photolithography
.•Uhing are described more thoroughly in Chapters 4 and 5, respectively, REFERENCES
1 2000 Electronic Market Data Book. Electron Ind. Assoc.. Washington. DC. 2000.
1.4.3 Diffusion and Ion Implantation 2 2000 Semiconductor Industnj Report, Ind. Technol, Res Inst.. Ihinchu. Taiwan. 2000.
3 Most of the classic device papers are collect^ in M.
In the diffusion method, die semiconductor surface not protected by the oxide is exposed S. S,e. Kd.. Semiconductor fat*. PUmrerin*
H
Paper,. World Sci.. Singapore. 1991.
to a source with a high cone -cut ration oj opposite-type impurity. The impurity moves into
4. K K Xg. Complete Guide to Semiconductor Devices. McCraw.HiU.
the semiconductor «. rvst.il !>v solid-state diffusion. In ion implantation, the intended in:pu- Now York. 1995.
5. F. Braun. "liber die Stro.nlcitung .lurch SchsvefclmctauV."
ntv is mtr. iduced into t lie semiconductor by accelerating the impurity ions to a high energy Ann W,„, Chem . 153. 556 ( 1874).
led and then implanting the ions in the semiconductor. The SiO, layer serves as a bar- II J.
Hound. "A Note on Carborundum." Electron World.
19,309(1907).
rier to impurity diffusion or ion implantation. After the diffusion or implantation pro- : J B.ml. ,1, and W H. Brattain. The Transistor. Semi. OoductOl IrfcdV /•/,.,.. Hex.. 71. 230 (1948).
cess the ;>-n junction is formed, as shown in Figure 1.1 Or/. Due to lateral diffusion of
8 W Sliocklry. The Tbeorj oi Semkondu.lorx and
p-fl function to ;>-. Junction Transistor* • Bell Sutt
impurities or lateral straggle of implanted ions, the width of the p- region y
is slightly wider Tech. /.28,435(1949). '
than the window opening. Diffusion and ion implantation are discussed in Chapters 6 9 Eberx. "Four Terminal p-u-p-t, Transistors." Proe IHE.
J. 40. 1361 (1952).
and 7. respectively.
10.D. M chapiii. c s Fuller, and <:
.
I. P. anon, "A New Silicon p-n Junction Photocell for Converting
SoLr Radiation into Electrical Power, 25. id.
/ Appl /'/.•/. IT>I
1.4.4 Metallization 11. H. Kroemer, Theory oft Wide-Cap EmHtei for Transistors." Proe IHE, 45. 1535(1957).
12. L. Esaki. 'New Phenomenon in Harrow Germanium p-n Junction*,' Plan Rn 109, 603 (1958).
After diffusion or ion implantation, a metallization process used to form ohmic contacts
is
.
and interconnections (Fig. 1.10c). Metal films can be formed by physical vapor deposition 13. D. ICahngand M M Alalia, "Silicon -Silicon Dioxide SmU. D.-su-c." m IHE Device Research
Conference, Pittsburgh, 1960. (The paper can Ik- found in Ref 3.)
or chemical vapor deposition. The photolithography process is again used to define the
front contact, which is shown in Figure 1.10/ A similar metallization step is performed on 14. B Yii. ,-t at, "15 nm Gate Length Planar CMOS Transistor.' IEEE WDM Technical Digest, Washington.
DC. p. 937 (2001).
the back contact without using a lithograph)' process. Normally, a low-temperature (<, 500°C)
anneal would also be performed to promote low-resistance contacts between the metal 15. F N Hall. < t al . "Coherent Ught Emission from C.i\s Junctions, /%« Rev hit.. 9, 366 (1962).
17. I. Alferov and R. F. Ka/arinov. *SemiCOnductOr Laser with Electrical Pumping I s s It Patent I8l.
737(1963).
1.5 SUMMARY IS
J
li Cunii. Microwave Oscillations of Current in lll-V Sen, lOOdducton, Solid SMl I'ouimtin.. 1,88
Semiconductor devices have an enormous impact on our society and the global economy (1963).
because they serve as the foundation of the largest industry in the world— the electron- 19. R. L Johnston, B C DcLoach. Jr . and B. C Cohen, "A Silicon Diode Microwave < Kdlator." Bell Sijxt
This introductory chapter has presented a historical review of major semiconductor 20. C. A. Mead. "Scbottky Barrier Gate Field Effect Transistor." Pn U I E M, 307 (1966).
devices, from the first study of the metal-semiconductor contact in 1874 to the fabrication 21. D. KahngandS. M. Sze. "A Floating Gate and Its Application to Memory Devices "
Bell Stj-t IfeCfl
/
of an ukrasmall 15-nm MOSFET in 2001. Of particular importance are the invention of 46. 1283(1967).
the bipolar transistor in 1947, which ushered in the modern electronics era; die devel- 22. K. Yauo. <-t al "Room Temperature Single- Electron Memoi) IEEE Tram Electron i>,-i u, ... 41. it>2*>
opment of the MOSFET in 1960. which is the most important device for integrated cir- (1994).
cuits and die invention of the nonvolatile semiconductor
memory in 1967, which has 23. W S. Bovlc and C E Smith. "Charge Coupled Semiconductor Devices." Bell Syal Tn l,
J. 49. 587
been the technology driver of the electronics industry since 1990. (1970).
This chapter also described key semiconductor technologies. The origins of these 24. L. L. Cliaiig. L. Esaki. and R. Tsu. "Resonant Tunneling in Semiconductor Double Barriers." Aiipl.
technologies can be traced back as far as two millennia. Of particular Phus. Ixtt.. 24, 593 197-1
importance are the ( 1.
development of the lithographic photoresist in 1957. w hich established die basic pattern 25. T. Mimura. et al.. "A New Field-Effect Transistor with Selectively Dop,-d GaAs/n-Al.Cii, , as
tvwj largest segments of the semiconductor industry. 27 M H. pher. The Photoasist Story."./. Photo Set 12. 181 1 1964V
Ctaptvr 1. Introducfoon
* J.
CaocWsh. Kin neues Verfahren air Mcssung der KristallisaUonspschwtndJgkcit
der Metallc."
-
34 C | Frosch and L Derrick. "Surface Protection and Selective Masking during Diffusion in Silicon.
44 S M Irving. K E Lemons, and C. E Bobos. 'Cas Plasma Vapor Etching Process." U.S. Patent
3.615.956 M971).
Si CaAs
45. A. Y. Cho. "Film Deposition by Molecular Beam Technique."/ Vac. Sci. Techno!.. 8, S31 (1971).
sio2 <:., \v
46 The inventors of the microprocessor are M. E. Hoff. F. Faggin. S. Ma/or. and M. Shima. For a profile <>l
material
It E Hoff. see Portraitt In Silicon by R. Slater, p. 175. MIT Press. Cambridge. 1987.
Distillation Synthesis
47 R Bung. H. Momose. and Y Nanakubo. "Deep Trench Ivl.ite.l CMOS Devices." 7< <7i Dig IEEE hit and
Electron Devices Meet 237 ( 1982) reduction
, p.
48 B. Davari. et al . "A New Planarization Technique. Using a Combination of RIE and Chemical
Polycrystalliiic
Mechanical Polish (CMP)." Tech. Dig IEEE Int. Electron Devices Meet . p. 61 (1989). semiconductor
n | I'.ir.iv/x-zak. et aL. "High Perfomum • Die!, dries and Processes for ULSI Interconnection
Technologies.- Tech Dig IEEE Int Electron Devices Meet., p. 261 (1993).
Crystal growth
Crystal growth
50. 77w International Technology Roadmap for Semiconductor. Semiconductor Ind. Assoc.. San Jose. 1999.
51 F Masuoka. "Flash Memorv Technology." Proc Int Electron Devices Mater Symp.. 83. Hsinchu.
Single crystal
Taiwan (1996),
to polished wafei
Figure 2.1 Process flow Gton starting material
17
18 Chtpttf 2. Crystal Growth 2.1 Silicon Crystal Growth from the Moll < 19
The starting material for silicon is a relatively pure form of sand (SiO,) called quartette.
This is placed a furnace with various forms of carbon (coal. coke, and wood chips).
in
Although a number of reactions take place in the furnace, the overall reaction is
This process produces metallurgical-grade silicon with a purity of about 98%. Next, the
C
silicon is pulverized and treated with hydrogen chloride (HC1) at 300 C to form trichlorosi-
bne SiHGI .
The trichlorosilane is a liquid at room temperature (it has a boiling point of 32°C).
Fractional distillation of the liquid removes the unwanted impurities. The purified SiHCl,
is then used in a hydrogen Reduction reaction to prepare the electronic-grade silicon (ECS):
This reaction takes place in a reactor containing a resistance-heated silicon rod. which serves
as the nucleation [joint for the deposition of silicon. EGS. a polycrystalline material of high
purity is the raw material used to prepare device-quality, single-crystal silicon. Pure EGS
1
The Czochralski technique uses an apparatus called a crystal puller. A simplified version
of this device is shown in Figure 2.2. The puller has three main components: (a) a furnace,
which includes a fused-silicon (SiO,) crucible, a graplute susceptor. a rotation mechanism
(clockwise as shown), a heating element, and a power supply; (b) a crystal-pulling mech- 2.1.3 Distribution of Dopant
anism, which includes a seed holder and a rotation mechanism (counterclockwise); and
(c) an ambient control, which includes a gas source (such as argon), a flow control, and an In crystal growth, a known amount of dopant is added to the melt to obtain tin- desired
exhaust system. In addition, the puller has an overall microprocessor-based control system doping concentration in the grown crystal. For silicon, boron and phosphorus are the most
to control process parameters such as temperature, crystal diameter, pull rate, and rota- common dopants for p- and n-type materials, respectively.
tion speeds, as well as to permit programmed process steps. Various sensors and feedback As a from the melt, the doping concentration incorporated Into
crystal is pulled
tin-
loops allow the control system to respond automatically, reducing operator intervention. crystal (solid) usually different from the doping concentration of tin- melt (liquid) it
is
In the crystal-growing process, polycrystalline silicon (EGS) is placed in the crucible, the interface. The ratio of these two concentrations is defined as the equilibrium Wjgr*
and the furnace is heated abov e the melting temperature of silicon. A suitably oriented gation coefficient, k 0 :
seed crystal (e.g.. <111>) is suspended over the crucible in a seed holder. The seed is
inserted into the melt. Part of it melts, but the tip of the remaining seed crystal still touches
the liquid surface. It is then slowly withdrawn. Progressive freezing at the solid-liquid
the dopant (o the
interface vields a large, single crystal. A typical pull rate is a few millimeters per minute. where C, and C, are. respcctivelv, the equilibrium concentrations of
For large-diameter and 'liquid near the interface/Table 2. 1 lists values of k, for the commonly used dopants
silicon ingots, an external magnetic field is applied to the basic solid
which means during growth the dopants
silicon. Note that most values are below
that
Czochralski puller. The purpose of the
external magnetic field is to control the concen- for 1.
SitU SSJl^fft
li<l"i(! -weight), C,. is
^
given In
,s A/ "- M "'«' ... Oh
Given the initial weight of the dopant. C:„\/ we can integrate K<,. 7:
</5
-/
,J,y =i »Jiv^
f f
«•>
Figure 2.4 illustrates the doping distribution as a function of the fraction solidified <.\//A/„)
lor several segregation coefficients. 1
Consider a Crystal being grown from a melt having an initial The total number of boron atoms in the melt is
weight A/„ with an ini-
tialdoping concentration C„ in the melt (i.e.. the
U a given point of growth when a mM.,1 of weight
weigfat of the dopant per 1 g of melt) 1.25x10'* atoms/cm' x 2.37 xlOW = 2.96x10* boron atoms
has been grown, the amount ofM
dopant remaining in the melt by weight is S. For an incremental so that
I
amount of the crvstal
with weight tIM. the corresponding reduction
of the dopant I-y/S) from the melt isCdM !o
2.96xl0 atoms x 10.8 g/mol ... ,_„, fl c ,.
where C, is the doping concentration in the cr>stal (by weight): ^ = 5.31x10 eofboron
6 = 5.31 nig of boron
6.02x10" atoms/mol *
-dS*Ct dM (5) Note the small amount of boron needed to dope such a Urge load of silicon
Mefetl Crystal Growth 2.1 Silicon Crystal Growth from the Melt < 23
? Solid - Liquid -
cko)
V Cur)
^ (*o<»
c,
0 6
i
| *t Growth direction
0= v£ + D £
where D is the dopant diffusion coefficient in the melt, vis the crystal grown velocity,
and C is the doping concentration in the melt.
The solution of Eq. 11 is
C = A e-"° + A
l 2 (12)
where /\, and A, are constants to be determined by the boundary conditions. The first
boundary condition is that C = C, (0) at x = 0. The second boundary condition is the con-
servation of the total number of dopants: that is. the sum of the dopant fluxes at the inter-
face must be zero. By considering the diffusion of dopant atoms in the melt (neglecting
diffusion in the solid), we have
Substituting these boundary conditions into Eq. 12 and noting that C = C, at x = £ gives
2.1.4 Effective Segregation Coefficient
^° = ^'" C '
(H)
While the crystal is growing, dopants are constantly being rejected into die melt (for k„> 1). C,(0)-C.
If die rejection rate is higher than the rate at which the dopant can be transported away Therefore,
by diffusion or stirring, then a concentration gradient will develop at the interface, as illus-
trated in Figure 2.5. The segregation coefficient (given in Section 2.1.3) is fc„ = C,/C,(0). (15)
We can define an effective segregation coefficient k, . which is die ratio of C4 and the impu- «-"t% + (i-V~
nt\ o >ncentration far away from the interface:
the crj stal is given by the same expression as in Eq. 9. except
The doping distribution in
that A„ is replaced byValues of it, are larger than those of *„ and can approac h 1 for
it..
(10) large values of die growth parameter vS/D. Uniform doping distribution (kt
-* I) in the
<>'
crystal can be obtained by employing a high pull rate and a low rotation speed (since
Consider a small, virtually stagnant laser of melt with width 8 in which the only flow isinversely proportional to the rotation speech. Another approac h to achieve uniform dop-
is tint re quired to replace the crystal being withdrawn from the melt. Outside this stag- ing is to add ultrapure polycrystalline silicon continuously to the melt so
that the initial
nant layer, the doping concentration has a constant value C,. Inside the layer, die dop- doping concentration is maintained.
ing concentration can be described by the steady-state continuity equation:
ipt* 2. Crystal Growth
2 2 Silicon Float-Zone Process « 25
so that
2.2 SILICON FLOAT-ZONE PROCESS
TV float-u process can be used to grow silicon that has lower contamination than that
>tu-
dS
nonrulh obtained from the Czochralski technique. A schematic setup of the float-zone
process is shown in Figure 2.6a. A high-purity p<>lycrystalline roil with a seed crystal at
thr lx>ttom is he-Id tn ft vertical position .incl rotated. The rod is enclosed in u quartz enve-
lope witliin atmosphere (argon) is maintained, During the operation, a small
which .ui inert
heater, whic h is moved from the seed upward so that this /?« wring ZOM traverses tin- length
of the rod. The molten silicon is retained by surface tension between the melting and "l L J" C0 p,A-{ K S/L) n
growing As the flouting zone moves upward, single-erystal silicon freezes
solid -silicon faces. or
at the zone's re rc.it inn end and grows .is .in extension of the seed crystal. Materials with
t
liiglit resistivities can be obtained from the float-zone process than Iroin the Czochralski
i
more Furthermore,
5= S^[ . 1 (l .^ r (w
process because the former can be used to purify the crystal easily. ,J
since no crucible is used in the float-zone process, diere is no contamination from the C<,nCe " tra,i0n ,he **** at the
crucible (as with Czixhralski growth 1
. At the present time, float-zone crystals are used k^pltlh^ end) is given by C, =
mainly for high-power, high-voltage deuces, where high-resistivity materials are required.
To evaluate the doping distribution of a float-zone process, consider a simplified mixiel.
^.=4-1(1-*,)-^]
.isshown in Figure 2.6/j. The initial uniform doping concentration in the rod is C 0 (by .
(18)
M eight). L is the length of the molten zone at a distance X along the rod. A is the cross- Sh0m COnCentration versus the soli(,ir,ed length for various
s< < tional area of the rod. p,, is amount of dopant
the specific density of silicon, and S is the
vaberoX*
present in the molten zone. As the zone traverses a distance dx, the amount of dopant These two crystal growth techniques can also be used
to remove impuritie s. A com-
.hIUA at its advancing end is
parison of Figure 2.7 with Figure 2.4 shows
to it p..\ tlx. whereas the amount of dopant removed from
(.' that a single pass in the float-zone
process
the retreating end k S dx/L). whe re the effective segregation coefficient. Thus.
does not produce as much purification as a single
it at Ls I k, is Czochralski growth. For example, for
fc„ = A„ - 0.1. C,/C„ is smaller over
most of the solidified ingot made bv the i/nchralski (
50 =5cxp^J (19)
Therefore, XkjJL is small. C, Will remain nearK constant with distance except at (he-
Ftourt U FW-zone process, (a) Schematic setup, (b) Simple model for doping evaluation. Si * + neutron -> Si JJ + yray->P, { +0ray
,
(21)
/ 2.3 GaAs Crystal Growth Techmques 2i
p 1
After 1 zone
1
to-'
io- ;
1(T*
/
[0
*r = 0.1
5 l
io- 1
10
Figure 2.8 Relative impurity concentration versus zone length for a Dumber of passes. L
denotes the zone length.*
Figure 2.7 Curves for the float-zone process showing doping concentration in the solid as a Figure 2.10 shows the phase diagram of the gallium-arsenic system. The absdsss
function of solidified zone lengths.' represents various compositions of the two components in terms of atomic percent (lower
67
scale) or weight percent (upper scale). Consider a melt that is initially of composition
x 85 atomic percent arsenic, as
(e.g.. shown in Fig. 2.10). When the temperature is low-
Hie half-life of the intermediate lenient Si
1
is 2.62 hours Because the penetration depth until the liquidus line readied. At die point T \\
ered, its composition will remain fixed is
.
,
} i
nt neutrons bo silicon is abotil 100 cm, doping is very uniform throughout the slice. gallium arsenide) will begin to solidify.
material of .50 atomic percent arsenic (i.e..
Figure 2.!) compares the lateral resistivity distributions in conventionally doped silk-on and
in Silicon doped by neutron irradiation.' Note that the resistivity variations for the neu-
tron-irradiated silicon are much smaller than those for the conventionally doped silicon.
EXAMPLE 2
2 31 Starting Materials
SOLUTION the weight of the liquid M, is me weight of
At T, . &?, is
the solid [I e., GaAs), ind<
and c of dopant In the liquid and the solid respectively. Therefore, the
are the concentrations
The starting materials for the synthesis
of polycrystallinc gallium arsenide are the ele- rcspcctivvly Because the total arsenic
weights of arsenic in the liquid and solid are .\/,C, and M,C,.
iin lit i! < hemii
pure gallium and arsenic. Because gallium arsenide is a combination
allv
weight is (M, * MJC.,. we have
of two materials, its behavior is different from that of a single material such as silicon.
Hie behavior of a combination can be described by a phase diagram. A phase is a state
2.3 GaAs Crystal Growth Techniques « 29
or
1 1 . -J i i I
40 mm :30 20 10 20 30 40
Radius Radius
(b)
Figure 2.9 a Typical lateral resistivity distribution in a conventionally doped silicon, (h) Silicon
0 10 X) 100
Mo
10 20 30 40 50 60 70 80 90 100
Atomic 1 arsenic
ud(b) toprevent decomposition of the gallium arsenide while it is being formed in the
furnace. When the melt cools, a high-purity polycrystalline gallium arsenide results.
This
7
Serves as the raw material to grow single-crystal gallium arsenide.
There are two techniques for GaAs crystal growth: the Czochralski technique and the
Direction of heater travel fc-
Bridgman technique. Most gallium arsenide is grown by the Bridgman technique. However,
Figure 2.12 Bridgman technique for growing single-crystal gallium arsenide, and temperature
the Czochralski technique is more popular for the growth of larger-diameter GaAs ingots.
a
pre. file of the furnace.
For Czochralski growth of gallium arsenide, the basic puller is identical to that for
silicon. However, to prevent decomposition of die melt during crystal growth, a liquid encap-
sulation method is employ ed. The liquid encapsulant is a molten boron trioxide (B 2 0.,) layer Figure 2.12 shows a Bridgman system in which a two-zone furnace is used for grow-
about 1 cm thick. Molten lx>ron trioxide is inert to the gallium arsenide surface and serves ing single-crystal gallium arsenide. The left-hand zone is held at a temperature (approx-
as a cap to cov er the melt. This cap prevents decomposition of the gallium arsenide as long imately 610°C) to maintain the required oveqjressure of arsenic, whereas the right-hand
as the pressure on its surface is higher than 1 atm (760 Torr). Because boron trioxide can
zone is held just above the melting point of gallium arsenide ( 1240°C). The sealed tube
dissolve silicon dioxide, the fused-siliea crucible is replaced with a graplute crucible. made of quartz, and the boat made of graphite.
is is In operation, the boat is loaded with
To obtain the desired doping concentration in the grown crystal of GaAs, cadmium a charge of poryciystalline gallium arsenide, with the arsenic kept at the other end of
and zinc are commonly used forp-type materials, whereas selenium, silicon, and tellurium the tube.
are used for n-type materials. For semiinsulating GaAs, the material is undoped. The equi- As the furnace is moved toward the right, the melt cools at one end. Usually, there is
librium segregation coefficients for dopants in GaAs are listed in Table 2.2. Similar to a seed placed at the left end of the boat to establish a specific crystal orientation. The grad-
those in Si, most of the segregation coefficients are less than L The expressions derived ual freezing (solidification) of the melt allows a single crystal to propagate at the liquid-solid
previous!) for Si (Eqs. 4 to 15) are equally applicable to GaAs. interface. Eventually, a single crystal of gallium arsenide is grown. The impurity distribu-
tion can be described essentially by Eqs. 9 and 15, where the growth rate is given by the
Dopant Type
2.4 MATERIAL CHARACTERIZATION
Be 3 P
Mg 0.1
P 2.4.1 Wafer Shaping
Zn 4 x ltr 1
P After a crystal is grown, the first shaping operation is to remove the seed and the other
C 0.8 nip
The next operation to grind the surface so
1
10-'
end of the ingot, which is last to solidify. is
Si 1.85 x nip
Uiat the diameter of the material is defined. After that, one or more flat regions are ground
Ge 2.8 x 10 J
nip
along the length of the ingot. These regions, or flats, mark the specific crystal orienta-
S 05 n
tion of the ingot and the conductivity type of the material. The largest flat, the primary
Se 5.0 x 10- 1 n
: flat, allows amechanical locator in automatic processing equipment to position the wafer
Sn 5.2 x 10' n
10" 1
and to orient the devices relative to the crystal. Other smaller Hats. caScdsecondaryflats.
Te 6.8 x n crystal, as shown in
are ground to identify the orientation and conductivity type of the
Cr 1.03 xlO" 4 Semiinsulating mm.
Figure 2.13. For crystals with diameters equal to or larger than 200 00 fiats are ground
Fe 1.0 x 10
1
Semiinsulating
Instead, a small groove is ground along the length of the ingot.
32 * Chapter 2. Crystal Growth 2.4 Material Characterization « 33
Figure 2.14 200-mm (8 in.) and 400-mm (16 in.) polished silicon wafers in cassettes.
(Photo courtesy of Shin-Etsu Handotai Co.. Tokyo.
and contaminated regions can be renio\ ed by chemical etching (see Chapter 5). The final
step of wafer shaping is polishing. Its purpose is to provide a smooth, specular surface
2.4.2 Crystal Characterization
where device features can be defined by photolithographic processes (see Chapter 4).
Figure 2.14 shows 200-mm (8 in.) and 400- mm (16 in.) polished silk-on wafers in cas- Crystal Defects
settes. Table 2.3 shows the specifications for 125-. 150-. 200-. and 300-mm diameter pol- A from die ideal crystal in important Ways It
real crystal (such as a silicon wafer) differs
ished silicon wafers from the Semiconductor Equipment and Materials Institute (SEMI). is finite; atoms are incompletely bonded. Furthermore, it has defects, which
thus, surface
As mentioned previously, lor lan»e crystals >> 200 mm diameter', no Hats are ground: instead, strongly influence the electrical, mechanical, and optical properties of the semiconduc-
made on tor. There are four categories of defects: point defects, line
delects, area defed* and vol-
a groove is the edge of the wafer for positioning and orientation purposes.
Gallium arseniBe is a more fragile material than silicon. Although the basic shaping time delects.
operation of gallium arsenide is essentially the same as that for silicon, greater care must Figure 2.15 shows several forms of point defeds.
1
'
Any foreign atom incorporated
be exercised in gallium arsenide wafer preparation. The state of gallium arsenide technol- into the lattice at either a substitutional site (i.e.. at a regular lattice site (Kg 2,15a)]
compared with However, the technology of group between regular lattice sites Fig. 2.1.5/.)] is a point defect \
ogy is icI.itneK primitive that of silicon. Or an interstitial site [i.e.. |
compounds has advanced missing atom in the lattice creates a vacancy, also considered a point delect (Fig 2.15c
II1-V partly because of die advances in silicon technology.
Chapter 2. Crystal Growth 2.4 Material Characterization ^ 35
ooooooo ooooooo
ooooooo ooooooo
ooooooo ooooooo
000Q000 ooooooo
ooooooo ooooooo
ooooooo ooooooo
ooooooo ooooooo
(.) (b)
ooooooo ooooooo
ooooooo ooooooo
ooooooo ooooooo
ooo ooo O ^CTOOOO
ooooooo ooooooo
ooooooo ooooooo
ooooooo ooooooo
(c) (d)
Figure 2.15 Point defects, (a) Subs! impurity, (b) Interstitial Impurity (c) Lattice
vacancy. (</> Frenkel-type defect."
A host atom that is situated between regular lattice sites and adjacent to a vacancy is
called a Frenkel defect (Fig. 2.15V/). Point defects are particularly important subjects in
the kinetics of oxidation and diffusion processes. These topics are considered in Chapters
3 and 6. respectively
The next class of defects is the line defect, also called a dislocation.
1
"
There are two
types of dislocations: the edge and screw types. Figure 2.16a is a schematic represen-
tation of an edge dislocation in a cubic lattice. An extra plane of atoms AB is inserted into Precipitates of impurities or dopant atoms make Up the fourth class of defects: vol-
the lattice. The line of the dislocation would be perpendicular to the plane of the page. ume defects. These defects arise because of the inherent solubility of the imparity in the
The screw dislocation may be considered as being produced by cutting the crystal part- host lattice. There is a specific concentration of impurity that the host lattice can accept
way through and pushing the upper part one lattice spacing over, as shown in Figure 2. 16b. in a solid solution of itself and the impurity. Figure 2.1S shows solubility versus temper-
decreases
Line defects in devices are undesirable because they act as precipitation sites for metal- ature for a variety of elements in silicon." The solubility of most impurities
licimpurities, which may degrade device performance. with decreasing temperature. Thus, if an impurity is introduced to the maximum con-
Area defects represent a large-area discontinuity in the lattice. Typical defects are twins centration allowed by its solubility at a given temperature, ami the crystal is then cooled
and grain boundaries. Twinning represents a change in the crystal orientation across a to a lower temperature, the crystal can only achieve an equilibrium
state by precipitat-
plane. A grain boundary is a transition between crystals having no particular orientational ing the impurity atoms in excess of the solubility level Howev er, the volume mismatch
In Figure 2.17 the sequence of atoms in the stack is ABCABC .... If a part of layer C is Material Properties
lor integrated circuit tech-
missing, the defect is called an intrinsic stacking fault (Fig. 2.17a). If an extra plane A is
Table 2.4 compares silicon characteristics and the requirements
7 as ultralargc-scalc inte-
Inserted between layers B and C. it is an extrinsic stacking fault (Fig. 2.17i>). Such defects nology having more than 10 components, which is referred to
- 11 properties listed in Table 2.4 cm be
may appear during crystal growth. Crystals having these area defects are not usable for gration (ULSI).
1
The semiconductor materia]
The measured by the four-point pwlx- method,"
integrated circuit manufacture and are discarded. measured by various methods. resistivity is
2.4 Material Characteri/at.on « 37
TABLE 2.4 Comparison of Silicon Material Characteristics and Requirements tor ULSI
< lliiiructrrittits
ppma. parts per million atoms; ppba. parts per billion atoms.
IT ls
it aids the format ion
of defects. Typical oxygen concentrations range from 10 to 10
5
atoms/cm Oxygen, however, has both deleterious and beneficial effects. It can act as a
.
donor, distorting the resistivity of the crystal caused by intentional doping. On the other
hand, oxygen in an interstitial lattice site can inc rease the yield strength of silicon.
In addition, the precipitates of oxygen due to the solubility effect can !>e used for
gettering. Gettering meaning a process that removes harmful impuri-
is a general term
ties or defects from the region in a wafer where devices are fabricated. When the wafer
the surface. This lowers the oxygen content near the surface. The treatment creates a
defect-free (ox denuded) zone for device fabrication, as shown in the inset of Figure 2. 19.'
Additional thermal cycles can be used to promote the formation of oxygen precipitates
in the interior of the wafer for gettering of impurities. The depth of the defec t-free zone
depends on the time and temperature of the thermal cycle and on the diffusisity of oxy -
gen in silicon. Measured results for the denuded zone are shown in Figure 2.19.' It is
Figure 2.18 So&d solubilities of impurity dements in silicon."
possible to obtain Czochralski crystals of silicon that are virtually free of dislocations.
Commercial melt-grown materials of gallium arsenide are heavily contaminated In
the crucible. I Iowever. for photonic applications, most requirements call for heavily doped
and lO'^cin" ). For integrated circuits or for discrete MESFET
5 IT
.uul trac v impurities suc h as owg« to .tiid carbon in silicon can be analyzed by the secondary materials (between 10
loo mass spectroscopic SIMS' tec Imique described in Chapter 6. Note that although cur- devices, undoped gallium arsenide can be used as the starting material with a resistivity
rent capabilities can meet most of the wafer specifications listed in Table 2.3, many improve* of 10'' Q-cm. Oxygen is an undesirable impurity in GaAs because it cSD form a deep donor
m.nts are needed to satisfy- the stringent requirements for ULSI technology.
13 level, which contributes to a trapping charge in the bulk of the substrate and increases
The oxygen and carbon concentrations are substantially higher in Czochralski crys- its resistivity. Oxygen contamination can be minimized by using graphite crucibles for
tals than in float-zone crystals because of the dissolution of oxygen from the silica cru- melt growth. The dislocation content for Czochralski-grown gallium arsenide cry stals is
l iN. .uul transport of carbon to the melt from the grapliite susceptor during crystal growth. about two orders of magnitude higher than that for silicon. For Bridgman CaAs c n stals,
Typical carbon concentrations range from 10'" to about 10 1T atoms/cm \ and carbon atoms the dislocation density is about an order of magnitude lower than that for Czochralski-
in silicon occupy substitutional lattice sites. Hie presence of carbon Ls undesirable l>ecause grown GaAs crystals.
IS Chta«*i Crystal Growth Problems « 39
A real crystal lias defects tli.it influence the electrical. 1necLu11e.1l Hid rjptt || prop-
erties of the semiconductor. Tl.es,- defe< ts are jx >n it defects, line defects, .ire.. <!. f
and volume delects. This chapter also discussed me., us to immiui/c such dele. Is I",,,
the more demanding ULSI applications, the dislocation density must be less than 1 per
square centimeter, Other Important requirements ..re listed in Table 2.1
REFERENCES
I. C. W. Peareo. "Crystal Growth end w.uVr Preparation' end "Epiuxy." in S. M. Ste, E<1 VLSI
T.-chtuJogy. McGraw-Hill. New York. 1983.
.-» !•. \V Mass and M S ScluioUer. 'Phosphorus Doping of Silium bv Means ,,i \Yutr,,ii Irradiation." /EEE
Trans. Electron Devices. ED-23, 803 (1976).
5 J
R Arthur. 'Vapor Pressures ami Phase Equilibria in the GaAs System.'/ Wiyi . ( hem Mltls. 2H, 225~
(1967).
,.t di, «1. i,tit!.-<I /,.i:<- ..ii-l getteniig sites in .1 water cross section
1
39. 205 (I960); R. Hull. Properties of Crystalline Silicon. INSPEC. London. 1999.
12 V. Matsushita Trend of Silicon Substrate Technologies for 0.25 Urn Devices." Pn« VLSI Teehnol
Workshop Honolulu (1996).
2.5 SUMMARY 13. The International Technology Roodmap for Semiconductors. Semiconductor Industry Association. San
For silk-on crystals, sand (SiO : is used to produce poK-crN^stalline silicon, wliich then serves
)
1 I W F Beadle, J
C. C. Tsai. and R. D. Pluinmcr. Eds.. Quick Reference Manual for Engineer,. W.l, •%.
New York. 1985.
as die raw material in a Czochralski puller. A seed crystal with the desired orientation is
used to grow a large ingot from the melt. Over 90% of silicon crystals are prepared by
this technique. During crystal growth, the dopant in the crystal will redistribute. A key PROBLEMS
parameter is the segregation coefficient, that is. the ratio of the dopant concentration in
the solid to that in the melt. Since most of die coefficients are less th;m 1. die melt becomes SECTION 2.1: SILICON CRYSTAL GROWTH FROM THE MELT
progressively enriched with the dopant as the Crystal gTOWS. 1. |»|«,t the doping distribution of arsenic at distances of 10. 2<>. 40 and 45 cm from the
seed in a silicon ingot 50 cm long that has been pulled from .1 melt with an initial doping
toother growth technique for silicon Is the float-zone process. It offers lower con-
tamination than that normally obtained from the Czochralski technique. Float-zone crys- concentration of 10" cnf*.
the
tals are used mainly for high -power, high-voltage devices where high-resistivitv materials 2. In silicon, the lattice constant is 5.43 A. Assume a hard-sphere model (a) Calculate
are required. radius of a silicon atom, (b) Determine the density of silicon atoms in atoms/cm', (c) Use
To make GaAs. chemically pure gallium and arsenic are used as the starting mate- the Avogadro constant to find the density of silicon.
After a crystal is grown, it usual])' goes through wafer-shaping operations to give an formlv distributed in substitutional sites. Find (a) die boron concentration in atoms/cm
end product of highly polished wafers with a specified diameter, thickness, and (in the average distance between Ixiron atoms.
and surface
orientation. For example. 200-mm silicon wafers for a MOSFET fabrication line should 5. The seed crVStal used in the Czochralski process is usually necked down to a small diaine-
have a diameter of 200 ± 1 mm. a thickness of 0.725 ± 0.01 mm. and a surface orienta- strength of
ter (5.5 mm) as a means to initiate dislocation-free growth. If die crlt»cal->ield
tion of ( 100) ± 1°. Wafers with diameters larger than 200 are being manufactured mm silicon is 2 x Iff gW. calculate the maximum length of a silicon ingot 200
diame- mm U
for future integrated circuits. Their specifications are listed in Table 2.3. ter diat can be supported by such a seed.
Cnaottr 2. Crystal Growth
3
6. Hot the curve of the C/C„ value for
7. A Cznchralski-gruwii crystal is doped with boron. Why is tho boron concentration larger
10. From Eq. IS find the C/C„ value at xJL » 1 and 2 with k r » 0.3.
1 1. If p+ ii abrupt-junction diodes are fabricated using the silk-on materials shown in Figure
29. find the peavntage change of breakdown voltages for the conventionally doped sili-
Mail) different kinds of thin films are used to fabricate
discrete devices and integrated
con and the neutron-irradiated silicon.
':" " ,s ["eluding thermal oxides, dielectric layers, noncrystalline
-
silicon, and metal films.
Figure 3.1 shows a schematic view of a conventional
SECTION 2.3: CAAS CRYSTAL GROWTH TECHNIQUES silicon n-channel MOSFKT that
uses all lour groups of films. The first important
thin film from the thermal oxide group
12. From Figure 2.10. if C. is 2091. what fraction of the liquid will remain at T,?
is the gate oxide layer, under which a conducting
channel can be formed between the
13. From Figure 2 11 explain why the GtAf liquid always becomes gallium rich. source and the drain. A related layer is the field oxide, which
provides isolation Iron, other
devices. Both gate and field oxides generally are grown by a thermal oxidation process
SECTION 2.4: MATERIAL CILVRACTERIZATION because only thermal oxidation can provide the highest-quality oxides
having the lowest
14. The equilibrium densitv < >f \ acancy n, is given by .V exp( -EJk T>. w hen- .V is the density of interface trap densities.
semiconductor atoms and E, is the energy of formation. Calculate n, in silicon at 27°C. This chapter covers the following topics:
900°C. and 1200°C .Assume £, » 2.3 eV
• The thermal oxidation process used to form silicon dioxide (SiO,)
15. Assume the energy of formation iE,« of a Frenkel-type defect to be 1.1 eVand estimate
• Impurity redistribution during oxidation
the defect density at 27°C and 900°C. The equilibrium density of Frcnkel-type defects is
gist-n by • Material properties and thickness measurement techniques for SiO, films
n, = VawV*' 1 "
16. How many c hips of area 100 mm" can be placed on a wafer 300 mm in diameter? Explain
your assumptions regarding the chip shape and unused wafer perimeter.
Dielcetnc SIN)
MOSFET
Figure 3.1 Schematic cross section of a meUl<Kfde-semiconductor field -effect transistor
(MOSFET).
42 * Cuapttf 3. S*co« Oxidation 3.1 Thermal Oxidation Process < 43
The silicon-silicon dioxide interface moves into the silicon during the oxidation process.
3.1 THERMAL OXIDATION PROCESS This creates a fresh interlace region, with surface contamination on the original
be oxidized by various method^
These include thernuJ option, silicon
SemkOftdu tors can ending up on the «dde surface. The densities and molecular weights of silicon
and sili-
and plasma-eimanced chemical vapor depos.bon (PECVD
.^ctrodvernicalanodization con dioxide are used in the following example to show that growing an oxide of
most nnportant thick-
sre Chapter s Among these
methods, thermal oxidation .s by far the ness x consumes a layer of silicon 0.44* thick (Fig. 3.3).
modem silicon integrated circuit technology. For
lor silicon deuces. It is key pr.Kv.vs in
.,
matic insertion and removal of silicon wafers, to ramp the temperature up (i.e.. to increase
Since 1 mol of silicon is converted to 1 mol «if silicon dioxide.
tlu- furnace temperature linearly) from a low temperature to die oxidation temperature
so that the wafers will not w arp due to sudden temperature change, to maintain the oxi- Thickness of Si x area Volume of 1 mol of Si
dation temperature to witliin ±1°C, and to ramp the temperature down when oxidation Thickness of SiO, x area Volume of 1 mol of SiO,
is completed. Thickness of Si 12.06
= 0.44
Thickness of SiO, 27.18
3.1.1 Kinetics of Growth Thickness of silicon - 0.4-1 (thickness of SiO,). For example, to grow a silicon dioxide layer of 100 mn,
: a layer of 44 nm of silicon is consumed. ^
The following chemical reactions describe Uie thermal oxidation of silicon in oxygen (
RrcuUnce heater
To vent
End cap (quartz)
Exhaust
At the silicon surface, the oxidizing species reacts chemically with silicon. Assuming
the rate of reac tion is proportional to the concentration of the species
at the silicon sur-
(c)
face, the flux P, is given by
Figure 3.4 ia) Basic structural unit of silicon dioxide, (b) Two-dimensional representation of a
ijiurtv crvstal lattice r) Two-dimensional representation <>t die UDOiphouS Structure ol mIkou F=kC, (4)
dioxide'
u lere v is the surface reaction rate constant
] for oxidation. At the steady state. F, = F, = F.
Combining Eqs. 3 and 4 gives
F=
DC
The kisic difference between the and amorphous structures is that the for-
crystalline [5)
x + (Dk)
mer iv .1 periodic structure. extending over main molecules, whereas the latter has no peri-
all. Rgure 3.4b is a two-dimensional schematic diagram of a quartz crystalline
odic Structure at The reaction of the oxidizing species with silicon forms silicon dioxide. Let C, be
made up of ring! with six silicon atoms. Figure 3.4c is a two-dimensional schematic
Structure the number of molecules of the oxidizing species in a unit volume of the oxide. There
diagram of an amorphous structure shown for comparison. In the amorphous structure, are 2.2 x UH silic on dioxide molecules/cm in the oxide, and we add one oxygen molecule
'
there is still a tendency to form characteristic rings with six silicon atoms. Note that the (0 2 to each silicon dioxide molecule, whereas we add tw o water molecules (H 20) to each
)
amorphous structure iii Figure 3.4c open because only 43* of the spec is oceu-
is quite SiO| molecule. Therefore. C, for oxidation in dry oxygen is 2.2 x 102 cm
-'
'.
and for oxi-
plei 1 by tiltoon dioxide molecules. The relatively open structure accounts for the lower den- dation in water vapor it is twice this number (4.4 x 10^ cm >. Thus, the growth rate of
and allows a ariety of impurities (such as the oxide layer diickness is given by
Sftj v sodium) to enter and chfluse readily through
the silicon dioxide layer.
dx _ F _ OC0 /C,
The kinetics Of thermal ovulation of silicon can
be studied based on a simple model (6)
For small values of t. Eq. S reduces to TABLE 32 Rate Constants for Dry Oxidation of Silicon
Panlvilir- Uitf
.v = ^(r + r) (9)
Oxidation
1 .11 .11 n /111
( .onstant
n.llt Line at Kate
1 flllVIIt'lf
1000
/i
0.165
0.027
0.0117
0.30
0.071
0.076
0 37
920 0.235 0.0049 0.0208 1.40
During the earK stages of oxide growth, when surface reaction is the rate-limiting factor, 800 0.370 0.0011 0.0030 9.0
the oxide thickne.w varies linearly with time. As the oxide layer becomes thicker, the oxi- 700 0.00026 81.0
dant must diffuse thrOUgjb the Oxide layer to react at the silicon-silicon dioxide interface,
and the reaction becomes diffusion limited. The oxide growth then becomes proportional
to the square root of the oxidizing time, w hich results in a parabolic growth rate.
.t=*(/ + r) (12,
for the parabolic region. For tlus reason, the term B/A is referred to as the linear rate
constant, and B is the parabolic rate constant. Experimentally measured results agree
with the predictions of this model over a wide range of oxidation conditions. For wet oxi-
dation, the initial oxide thickness r/„ is very small, or r = 0. However, for dry oxidation,
the extrapolated value off/,, at! »0 is about 25
mn, Tims, the use of Eq. 1 1 for dry oxi-
dation on bare silicon requires a value for rthat can be generated using this initial thick-
ness. Table 3. 1 lists the values of the rate constants for w et oxidation of silicon, and Table
3.2 lists the values for dry oxidation.
The temperature dependence of the B/A is shown in Figure
linear rate constant
3.6 for both dry and wet oxidation and for and ( 100,-oriented silicon wafers."' The
( 1 1 1 )-
linear rate constant varies as exp(-EJkT), where the activation energy E t is about 2 eV
for both dry and wet oxidation. This closely agrees with the energy required to break
silicon-silicon bonds, 1.S3 eV/molecule. Under a given oxidation condition, the linear
rate constant depends on crystal orientation. This is because the rate constant is related to the rate of incorporation of oxygen atoms into the silicon. The rate depends on the sur-
face bond structure of silicon atoms, making it orientation dependent. Because the den-
sity of available Ixmds on the 1) plane is higher than that on the (100) plane, the linear
1
1 1
TABLE 3.1 Rate Constants for Wet Oxidation of Silicon rate constant for (111) silicon is larger.
Figure 3.7 shows die temperature dependence of the parabolic rate constant B. which
Parabolic Rate Linear Rate
Oxidation
can also be described by exp(-EJkT). The activation energy E 4 is 1.24 eV for dry oxida-
Constant Constant
tion. The comparable activation energy for oxygen diffusion in fused silica is
lis V The ,
1100 0.11 0.510 4.64 0 independent of crystal orientation. This independence Ls expected because it is
stant is
rcci
1000 $00 700 600
looo/rtK-')
2
figure 3.7 Parabolic rate constant versus temperature.
Although oxides grown in dry oxygen have the best electrical properties, consider-
ably more time is required to grow the same oxide thickness at a given temperature in
dry oxygen than in water vapor. For relatively dun oxides such as die gate oxide in a MOS-
FET (typically £ 20 nm), dry oxidation is used. However, for thicker oxides such as field
oxides 20 nm in MOS integrated circuits, and for bipolar devices, oxidation in water
)
vapor (or steam) is used to provide both adequate isolation and passivation.
Figure 3.8 shows the experimental results of silicon dioxide thickness as a function
of reaction time and temperature for two substrate orientations.' Under a given oxida-
tion condition, the oxide thickness grown on a (111) substrate is larger than that grown Since (/„ = 0.196 Um from the first step, we have
on a (100) substrate because of the larger linear rate constant of the (111) orientation.
Note that for a given temperature and time, die oxide film obtained using wet oxidation r s (d\ + 20* /k)C, /2DC„ = = 0.067 h
is about 5 to 10 times thicker than that using dry oxidation.
U.n = 0.296 um. Using these parameters in Ec, 11. we
The final desired thickness is x = J„ 0. 1
grown? (b) Flow much additional time is required to grow 0.1 Um more oxide in wet O, at 1200°C?
SOLUTION (a) From Table 3.2, the values of the rate constants for dry O, at 1200°C are 3.1.2 Thin Oxide Growth
A = 0.04 Um B - 0.045 umMi Relatively slow growth rates must be used to reproducer/ grow thin oxide films of pre-
to achieve such slow growth rates have been
report**
cise thickness. Various approaches
and t = 0.027 h. Using these parameters in Eq. 11. we obtain an oxide thickness of and lower temperatures (S00 C to
including growth in dry 0, at atmospheric pressure
pressure: growth in reduced partial
r - 0.196 um 900°C)- growth at pressures lower than atinospheric
diluent inert gas. such as N, Ar. or lie, together with the gas
pressures of ()- bv ..sine a
fb) From Table the values of the rate constants for wet Q 1200°C are ofcoitiposRe oxide (Urns, with the gate oxide
containing the oxidizing specfes; and the use
3.1. 2
at
films consisting of a layer of thermally grown SiOj and an overlaver 0J S.O. grown by
A = 0.05 Um B = 0.72 umWi
50 Chapter 3 Silicon Oxidation
3.3 Masking Properties of Silicon Dioxide + 51
|
•• ( \D
However, the mainstream approach for gate oxides 10
vaptir *K
tO 15 am thick is to grow the oxide film at atmospheric pressure and lower temperatures
(800*C toQOO'C). With this approach, processing using modem Vertical oxidation fur-
u i. . > i .in gnnv reproducible, high-qualit) 10-003 oxides to within 0 I 001 across the wafer.
It was noted earlier that for dry oxidation, there is an apparently rapid oxidation that
m- (0 .ui Initial OXide thickness </,. Of about -l> OJO. Therefore, the simple model
presented in Section 3 1.1 i- ""t wild for dry oxidation With an oxide thickness less than
or equal to20nm. For VLSI, the ability to grow thin —5-20 urn), uniform, high-quality
reproducible gate oxides ins become increasingly important This section bricflv considers
the growth mechanisms of such thin oxides.
In the earl) Stage of growth in dry oxidation, there is a large- compressiye stress in
the oxide layer that reduces the Oxygen diffusion coefficient in the oxide As the oxide
becomes thicker, the Stress is reduced because of the viscous flow of silica, and the dif-
fusion coefficient will approach its stress-free value. Tlierefore. for thin oxides, the value
til P k iii.n Ih- sufficiently small that we can neglect the term At in Eq. 11 and obtain
r-dJ^Bt (14)
— sio 2 -•—SIO,
u here <l is e<ju.d to V2DC„r/ C, which . is the initial oxide thickness when time is ext rap- Si
l 0 1.0
Okted to aero, and li is the parabolic rate constant defined previously We therefore expect *>1
the growth in dry oxidation to follow a paralwlic form. StawdifTusant in
initial
SiO, (eg P)
/ Fdst difTuiant in
.
/ SlOj (e.g.. Ca)
10
together, an impurity in one solid will redistribute between the two solids until it reaches x(ura) x(mto)
equilibrium. This is similar to the previous discussion in Chapter 2 on impurity redistri-
(c) (d)
bution in crystal growth from the melt. The ratio of the equilibrium concentration of the
impurity in the silicon to that in the silicon dioxide Figure 3.9 Four different cases of impurity redistribution in silicon due to thermal nidation
'
increases Uie amount of depletion: an example is boron -doped silicon heated in a hydro-
^ _ Equilibrium concentration of impurity in silicon
Equilibrium concentration of impurity gen ambient, because hydrogen in silicon dioxide enhances the diffusivity of boron. In
in SiO,
group 2. k is greater than unity, so the oxide rejects the impurity. If diffusion of the impu-
A second factor that influences impurity distribution is that the impurity may diffuse rity through the silicon dioxide is relatively slow, the impurity piles up near the silicon
rapidlv through the Silicon dioxide and escape to the gaseous ambient. If the diffusivity surface: an example is phosphorus, with k approximately equal to 10. When diffusion
of the impurity in silicon dioxide is large, tins fac tor will Ih- important. A third factor in through die silicon dioxide is rapid, so much impurity may escape from the solid to the
the redistribution process is that the oxide growing, and thus die boundary between
is gaseous ambient that the overall effect will be a depletion of the impurity: an example
the silicon and the oxide is advancing into the silicon as a function of time. The relative is gallium, with k approximately equal to 20.
rate ol thisadvance compared with the diffusion rate of the impurity through the oxide The redistributed dopant impurities in silicon dioxide are seldom electrical!) active
is Important in determining the extent of the redistribution. Note that
even if the segre- 1[owever, redistribution in silicon has an important effect on processing and device per-
gation coefficient of an impurity equals unity, some redistribution of the impurity in the
formance. For example, nonuniform dopant distribution will modify the interpretation
silicon WiD still take place As mdu ated in Figure 3.3. the oxide layer will be about twice of the measurements of interface trap properties, and the change of the surface con-
.i> thick a> the Silicon Uer it replaced Therefore, the same amount of impuritx will now centration will modify die threshold voltage and device Contact resistance
Ih- distributed m a larger volume, resulting in depletion of the impurity from the silicon.
Four possible redistribution processes are illustrated in Figure 3.9. 4 These processes
can into two groups. In one group, the oxide takes up the impurity (Figs. 3.9a
Ih- classified
3.3 MASKING PROPERTIES OF SILICON DIOXIDE
and b for k < 1 ). and in the other the oxide rejects die impuritx (Fig. 3.9r and r/ for k > 1). A silicon dioxide laver can also prov ide a selec tiv e mask against the diffusion of dopants
In each case, what happens depends on how rapidly the impurity can ated temperatures, a very useful property in IC fabrication. Predeposition of dopants
diffuse through the at elev
oxide. In group 1. the silicon surface is depleted of impurities: an example is boron, with Chapter 6). whether it be by ion implantation, chemical diffusion,
or spin-on tech-
(see
I approximate^ equal to 0 .3. Rapid diffusion of the impurity through the silicon dioxide niques, typically results m a dopant source at or near the surface of the oxide. During a
2 * Chapter 3. Silicon Oxidation
3.4 Oxide Quality •« 53
Subsequent high-temperature drive-in step. diffusion in oxide-masked regions must be OXIDE QUALITY
3.4
slow enough With respect to diffusion in the silicon to prevent dopants from diffusing
through the oxide mask to the silicon surface. The required thickness may be determined Oxides used for masking are usually grown by
wet oxidation A typical growth cyc le con-
experimentally by measuring the oxide thic kness necessary to prevent the inversion of a ^ofasequencetf
lightly doped silicon substrate of opposite conductivity at a particular temperature and m the wet phase s.nce the SiO,
growth rate is much higher when water is used
time. Typically, oxides used for masking common impurities are 0.5 to 1.0 fim thick. oxidant. Diyox.dat.on however, results in
the „
a higher-quality oxide that is denser
and has
The depend on the z
values of diffusion constants for various dopants in SiO_, a Mgber breakdown voltage (5-10 MV/cm).
It is for these reasons
that the thin gate oxides
contration. properties, and Structure of the oxide. Table 3.3 lists diffusion constants ft m MOS devices are usually formed using
dry oxidation.
various common dopants, and Figure 3.10 gives the oxide thickness required to mask lx>ron MOS devices are also affected by charges in the oxide and traps at the
SiO,-Si inter-
and phosphorus as a function oi diffusion time and temperature. Note that SiCX is much race. The baric classification of these traps and charges
is shown in Figure 3.1 1
They
more effective for masking boron than phosphorus. Nevertheless, the diffusivities of P, are the interface trapped charge, fixed oxide charge,
oxide trapped charge, and mobile
ionic- charge." °
Sb. As. and B in SiO, arc all orders of magnitude less than their corresponding values in
silicon, so they are all compatible with oxide masking. This is not true, however, for Ga Interface trapped charges (0„) are due to the
SiO,-Si interface properties and are
or Al. Silicon nitride isused as an alternative masking material for these elements dependent on the chemical composition of this interface. The
traps are located at the
S.O a-Si interface, with energy states in the silicon forbidden
bandgap. The interface trap
density (i.e.. number of interface traps per unit area
and per eV Is orientation depen-
TABLE 3.3 Diffusion Constants in SiO,
dent. In silicon with a <100> crystal orientation, the
interface trap density is about ,„
Dopants Diffusion Constants 100°C (crnVs) order of magnitude smaller than that in the <1 1 1> orientation.
at 1
Present-day MOS dev Ices
with thermally grown silicon dioxide on silicon have most of the
B 3.4 x nr" to 2.0 x 10" interface trapped charges
passivated by low-temperature (450°C) hydrogen annealing
Ga 5.3 x 10"" (see Chapter 7). The value
U of 0„ for <100>-oriented silicon can be as low as 10'" cm :
w hic h amounts to about one-
P 2.9 x 10" 1
to 2.0 x 1(T .
Sb 9.9 x 10
The fixed charge (O,) is located within approximately 3 nm of the SiO.-Si interface.
This charge is fixed and very difficult to charge or discharge. Generally, Q, is positive and
depends on oxidation and annealing conditions and on silicon orientation. It has l>ecn
suggested that when the oxidation is stopped, some ionic silicon is left near die
Inter-
face. These ions, along with uncompleted silicon bonds (e.g.. Si-Si or Si-0 bonds .
; ,l the
surface, may result in the positive interface charge. O, can be regarded as a charge sheet
Metal
Oxide trapped
ch "* B
<W Fixed oxide SiO,
V + + charge (O f )
E 0 0 0 0 l/
7
Interface trapped
charge (0„>
Figure 3.10 Thickness of silicon dioxide needed to mask boron and phosphorus diffusions
as a
func tion of diffusion time and temperature
Figure 3.11 Terminology for the charges associated with thermally oxidized silicon.
i
located at tin- SiO.-Si interface. Tvpical lived oxide- charge densities for a carefully treated TABLE 3.4 Color Chart for Thermally Grown SiO, Films Observed Perpendicularly under Daylight
mo M Interface system an about 10" cm 1
for* <1Q0> surface and about 5x 10'" cm"* Fluorescent Lighting
1 1 Klll> surface. Because of the lower values of Q and (),. the <100> orientation is
iy
Film Film
preferred lor silicon MOSFETs. Thickness Thickness
Kide trapped charge-s ,(,)
1
are associated with delec t-, in the silicon dioxide. These Color and Comments
(
(Um) (Um) Color ami Comments
charge -s can be created, for example, bj v -\.w radiation or high-energy electron bom-
0.05 Tan OAS
banlment. Tin- traps are distributed inside the oxide layer Most process-related can omiimi not Olue hill Ixmlerlllie
i
operations Irnce ooanvnination by alkali metal ions may cause stability prop?
I
electric field
II. 1 / AU
\1. wlllK
iIIk- ti\ 1
tOWTN i .
UgiM
li.rl.t 0.72 Blue green to green (quite hroud)
deuces operated under high-bias and high-temperature condfe
| ins in seinicondiictoi
Yellow green 0.77 "Yellmvisif
Hons Under these conditions mobile ionic charges can move bac k and forth through the
n -in l.i^lit ^old tir vellow; 0.80 Orange (rather broad for orange)
oxich- layer and cans.- threshold voltage shiftSi Th.-refon-. Special attention must be paid
» 1
1 t^i i i y MK'I'lllic
ii iv %€Uiiv
0.82 Salmon
to the elimination of mobile ions in device fabrication. For example, the effects of sodium
0.22 ( ;<>|"*
( l wiili
» 111 slight
'U^IU1
0.85 Dull, light red violet
contamination can be reduced by adding c hlorine during oxidation. Chlorine immobi-
0.86
yeDow orange Violet
lizes the sodium ions. A small amount (6% or less) of anhydrous HQ in the oxidizing gas 0.25 1 >r;tngr to melon 0.87 Blue violet
< an m coinplish this but the presence of chlorine during tin, oxidation incre;ises both the
0.27 Red 0.89 Blue
Violet
linear and parabolic rate- constants, leading to a higher growth rate.
0.30 Blue to violet blue- 0.92 Blur green
0.31 Blue 0.95 Dull vellosv green
3.5 OXIDE THICKNESS CHARACTERIZATION 0.32 Blue- to blue green 0.97 YeUow t<> Yellowish"
r
of the wafer corresponds to that wavelength. For example, a wafer with a 500-nm sili- 0.42 (
' (million nitik 1.10 Green
con dioxide layer will appear blue green. 111 Ye llow green
0 44 » l red
Violet i vi1 i
MOW
I . ,< i ('ii
* 11
1.28 Yellemisl.
indicates die step height. This information is then displayed on a chart recorder or CRT \Pll t II \l HOW 1.32 Sky blue to green blue
Screen Films of thicknesses of less than HX) nm to greater than 5 pm can be measured Vf-Urm/ In "Vi'lli iwidi" (not Vellow hilt 1.40 Orange
with this instrument. It in the rwcition where Yellow is to 1.45 Violet
Ellipwnuiry is another wide ly used measurement technique that is based on the polar- be e xpe-c te-el: at times appears to he 1.46 Blue- violet
ization changes that OCCUTWhen light is reflected from or transmitted through a medium. liglit creamy gray or metallic 1 1.50 Blue
Changes in polarization are a function of the optical properties of the material (i.e.. its 0.58 Light orange or yellow to pink 154 Dull yellow green
complex refractive indices its thic kness, and the wavelength and angle of incidence of 0.60 Carnation pink
the light beam relative to the surface normal These differences in polarization are mea- 0.63 Violet red
sured by an ellipsometer. and the oxide thickness can then lie calculated.
Senirrr Copyright 1064 hy lnie ni.iti.m:d Bustnws M* u Gorponttop reprinted with pnrttttafan fiooi
EXAMPLE 3
Suppose we want to perform a dry-wet-dry oxidation sequence on a <1(K)> silicon wafer at 1 100*C
foi S miDUtes In dry 0*2 hours in Wat 0..and finally, fur 5 more minutes indrvO It' the silium
sul.str.it.- is doped with phosphorus at
a level of use
10''"
cm\ SUPREM
to determine (he final
oxidation thickness and the phosphorus doping profile in the oxide and silicon
layers.
boundary, impurity segregation during growth, and other physical phenomena. In addi- STOP End oxidation example
tion. SUPREM can predict the results of die \-arious deposition, diffusion, epitaxial growth,
We assume the furnace has an idle temperature of 900 C when the wafer is inserted, so we use .i
and ion implantation processes discussed in subsequent chapters.
l(l-minuteramp up at 20 C C 'minute to KXFC at the U-gmrdngoTpTOCeaing and a 10-minute ranip
I
SI PREM performs oxidation simulations lux-don the kinetic growth model described
down at -20°C/minute hack to 900°C at the end The ramp up and ramp down .ire performed in
in Section 3. 1.1. The package incorporates Arrhenius functions to describe the linear and a nitrogen ambient.
parabolic rate coefficients for wet and dry oxidation, as well as a rudimentary model for
Alter oxidation is complete, we print and plot the phosphorus concentration as a function ofdepth
chlorinated oxidation. Oxidation is simulated using the command DIFFUSION.
With either into the silicon substrate. The results are Shown in Figure 3.13, which indicates a final oxide thick-
*ET02 or DRY02 included ;is parameters indicating wet or dry oxidation, respectively."
the oxide btvei
ness of 0.909 pin and depicts the phosphorus incorporation in
SUPREM also requires the specification of process conditions such as times, tempera-
ture profiles, and so forth. In the thin oxide regime. SUPREM uses an empirical model
of the form
3.7 SUMMARY
dx B _
+Cf mM a high-quality insulator that can l>c thermally grown on silicon wafers.
*=ir^ <
I6) Silicon dioxide
It
is
can also serve as a barrier layer during impurity diffusion or Implantation, and it is a
where B and .\ are the oxidation rate coefficients, and C and L are empirical constants. v component of MOS devices and circuits. These factors have contributed
si-uiiflcantK
la
To run SUPREM. an input deck must be provided. This file contains a series of state- dominant semiconductor material in us,- lock)
to silicon's current status as the
presented
ments nid comments. \ description of a few common!) used statements is given in This chapter described the mechanism bf thermal oxidation of silicon and
Vppendix I TV dci k U-gmswuh ..TITLE statement which is merel) a comment repeated a kinetic model of oxide growth. This model accurateb predicts oxide growth rate for a
and
01 r.M I, page ol theprogram output The next command. INITIALIZE is ., control state- wide range of process conditions. The chapter idso discussed dopant redistribution
and oxide quality were
ment that sets the substrate type, orientation, and doping. This command can also be the masking properties of oxides. Oxide characterization methods
* 59
U •* CMptav 1 SAcon Oxidation
Problems
PROBLEMS
Asterisks denote difficult problems
1. A ;'-t\]H- <l00>-<ihente<l silicon walci with .1 resistivity <>l 111 tlcm is pliutd in .1 wi t dm
dation system to grow a field oxide of 0 45 |im at UYHrC. Determine the tune required to
grmv the oxide.
*2. Alter the lirM oxidation as given in Problem I. a window is ojiened in the oxide to grow .1
gate oxide at 1000°C for 20 minutes in dry oxidation. Find the thicknesses of the nte
ovule and the total field oxide.
3. Show that Ecj. 1 1 reduces to x 1 = Bt for long times and to 1 = B/Ati * r) for short times.
4. Determine the difhiMon coefficient I) for dry oxidation of <100>-oriented silicon samples
6. Assume that the Cu concentration in the SiO, layer is 5 x 10 n atoms/cm' after vapor
phase deposition and is measured with atomic ahsorption spectrometry. The Cu concen-
tration in the Si layer is 3 x 10" atoms/cm' after HF/II.() : dissolution (Calculate the seg-
regation coefficient of Cu in SiO/Si layers.
•7. A bare and undoped <100> silicon sample is oxidized for 1 hour at 1 100°C in dry O.. It Is
then coven d and has the oxide removed over half the wafer Next, it is re-oxidized in wet
0, at 1000°C for 30 minutes. Use SUPREM to determine the thickness in the txvo
regions How high are the step on the surface and the step in the substrate?
Figure 3.13 Plot of phosphorus concentration as .1 function of depth into the silken s.:i>strate,
describee! as well Finally, the process simulation software package SUPREM wis intro-
duced. Hie use of SUPREM. however, is not limited to oxidation, and it willbe revis-
REFERENCES
I K II N.collninandJ R. Brrws. MOS PhunCi and Technology. Wiles. New York. 1982.
1 B. E. Deal and A. S Crosr. "General Rrlahonship for the Thermal Oxidation of Silicon "/ Appl Pliyt .
3770(1965!
A I D Mrindl. et A. -Silicon Epitaxy and Oxidation.* in F. Van de Wide. W. U EngL and P O. Jcspers.
Eds trVOm ami Device SU-.Minc.fur Inteeratrd Circuit Design. NoorhofT. Leydcn. 19i ..
.
4 A. S Crow. Phytic* and Technology of Semiconductor Device*. Wiles . New York. 1967.
7 S Wolf and R Tauher. Silicon Procaine, for the VLSI Era. Lattice Press. Sunset Beach. CA. 2000.
9 H Massoud. C Ho. and J Pluminer. in J Plummer. Ed.. Computrr Aided Design of Integrated Circuit
Fahncation Prorates for VLSI Deiice*. Stanford Urusroity TechnK-al Report. Stanford. CA. I9S2.
4.1 Optical Lithography < 61
4
Photolithography
final device, but onlv replicas of circuit features To produtv circuit features these resist
Figure 4.1 Various W*yi in which dust particles can interfere with photomask
patterns must be transferred once more into the underbuy Livers comprising the device. p.,tt, rm
Pattern transfer is accomplished b\ an etching process that selectively removes umn;isked
portions of a layer see Chapter 5).*
( A brief description of pattern transfer was given in
A pinhole in the underlying Liver. Particle 2 Is located near a pattern edge and may cause
Section 1 .4.2 The present chapter covers the following topics:
OOnsbtction of current flow in a metal runner. Particle 3 can lead to a short circuit between
..
• The importance of a clean room for lithography the two conducting regions and render the circuit useless.
• The most widely used bthographic method —optical lithography—and its resolu-
In a clean room, the total nimiher of dust particles per unit volume must
controlled, along With the temperature and humidity. Figure 1.2 shows the particle-si/e
Ik- tightly
taken from the maximum allowable number of particles thai are 0,5 |im and larger per
cubic loot of air. In the metric system, the class is taken from the logarithm (base I" of
4.1 OPTICAL LITHOGRAPHY
the maximum allowable number of particles thai are 0.5 um and largei per mine meter
The vast majority of lidiographic equipment for IC fabrication is optical equipment using For example, a class KM) clean room Knglish system) has ..dust count of KM) particles
i
it
ultraviolet light (wavelength or X = 0.2-0.4 Jim). This section considers the exposure tools, With particle diameters of 0.5 pin and larger, whereas a class M 3 5 clean tOOm metric
masks, resists, and resolution enhancement techniques used for optical lithography. It system) has a dust count of K) ''. or about t><mi particles m '
with particle diameters oi
also considers the pattern transfer process, which serves as a basis for other lithographic 0 5 um or larger. Since 100 particles/fl - 3500 particles fa . a class 100 in the English
gent control of the dean room environment is required when the minimum feature lengths
oflCs are reduced to the deep subrnicron range. For most IC fabrication areas, a diss
4.1.1 The Clean Room
KM) clean room is required; that is. the dust count must be about (bur orders oi magni-
tude lower than that of ordinary room .or. However, lor the lithograph) area B class
111
An IC fabrication facility requires a clean processing room, especially in the area used
for photolithography. The need for such a clean room arises because dust particles in the clean room or one with a lower dust count is required
air can settle on semiconductor wafers and lithographic masks and can cause defects in
the devices, which result in circuit failure. For example, a dust particle on a semicon- EXAMPLE 1
ductoi mii f t. c can disrupt tin- single-crystal growth of an epitaxial film, causing the for-
minute an am under laminar-flow condition at 3»
It we e\jx)se a 2(KI-iiun wafer for 1 to ail str. .1
mation of dislocations. A dust particle incorporated into the gate oxide can result in
m/min, how many dust particles will land 00 die wafer m a c lass 10 clean rOOTO?
enhanced conductivity and cause device failure due to low breakdown voltage. The situ-
ation is even more critical in the lithographic area When dust particles adhere to the sur- Um and large per uhu-
SOLUTION For a dad 10 clean room, there an- 350 particles (0.5 r t. r
,
face of a photomask, they behave as opaque patterns on the mask, and these patterns will The air volume that goes over the wafer in minute is I
be transferred to the underlying layer along with the circuit patterns on the mask. Figure
4 1
5
shows three dust particles on a photomask. Particle 1 may result in the formation of (30m/mto)x«{Ha] *j .nin.He * 0.942 m'
'
Chapter 4. Photolithography
4.1 Optical Lithography « 63
in optical diffraction at feature edges on the photomask: thai is when lighl passes by the
edges ol an opaque mask feature, fringes are formed and some light
penetrates Into the
shadow region. As a result, the resolution is degraded to the 2 to 5-um range.
In shadow printing, the minimum linewidth [or critical dimension (CD)] that can
Ik- printed is roughly
CD = VAi (1)
where >. ts tike wavelength of the exposure radiation and g is the gap between the mask
and the wafer and includes the thickness of the resist. For X = 0.4 Jim and g = 50 um.
the CD is 4.5 Jim. If we reduce X to 0.2-5 um (a wavelength range of 0.2 to 0.3 um is in
the deep 0V spectral region) and g to 15 Mm. the CD Ix-comes 2 um. Thus, then- is an
advantage in reducing both X and g. However, for a given distance
g. any dust particle
with a diameter larger than potentially can ause mask damage.
g c
—1—1 . L_i To avoid the mask damage problem associated with shadow printing, projection
0.01 0.1 1 10
printing exposure tools have been developed to project an image of the mask patterns
Particlru/r iu.in)
onto a resist-coated wafer many centimeters away from the mask To increase resolution,
Figure 4.2 Particle-\i/e cJistriimtion curve for English (- - - 1 and metric (—J cfasteS of onl\ a small portion of the mask is exposed at a time. The small image area is scanned or
clean room stepped over the w aler to cover the entire wafer surface. Figure 4.4a shows a 1:1 wafer
scan projection system." A narrow, arc-shaped image field approximately ] mm in width
serially transfers the slit image of (he mask on(o (he wafer. The image size on the wafer
The tiuiiiIxt of ilust particles (0.5 urn and larger* contained in the air volume is 350 x 0.942 = 330
is the same- as that on the mask.
particles.
Therefore, if there are 400 IC chips on the wafer, the particle count amounts to one particle on
i m li el s2' «>t il:< i hips Fortunate!} onK ., fraction ol the putt lei that land adhere to the wafer
surface, and of those only a fraction an? at a circuit location critical enough to cause a failure. I lowwer. Contact Proumity
the calculation indicati-s the importance of the clean room. <
The pattern transfer process is accomplished by using a lithographic exposure tool. The
performance of an exposure tool is determined by three parameters: resolution,
(ration, and throughput. Resolution is (he minimum feadire dimension that can be I
fcrred with high fidelity to a resist film on a semiconductor wafer. Registration is a measure
of how accurately patterns on successive masks can be aligned (or overlaid) with respec(
to previously defined patterns on the wafer. Throughput is (he number of wafers that
cm be exposed per hour for a given mask level.
There are basic-all) two optical exposure methods: shadow printing and projection
printing.* " Shadow printing may have the mask and wafer in direct contact with one another
(.) (b)
(as in contact printing) or in close proximity (as in proximity printing). Figure 4 .3a shows
a basic setup for contact printing, in which a resist-coated wafer is brought into physical Figure 4.3 Schematic of optic al shadow printing techniques a) Contact printing
contact with a mask, and the resist is exposed by a nearly collimated beam of uhraviolel (h) Proximity printing.
64 W C^*p<«r 4 Photolithography
4.1 Optical Lrthoflraphy « 65
NA = /isin0 (3)
tanfl 7 (
sint? '(NA) '
asshown in Figure 4.6. The terms G-tine, //-/me. and /-/me refer to the peaks
at 436 nm.
405 nm. and 365 nm. respectively, [-line lithography with 5:1 step-and-repeat projection
can offer a resolution of 0.3 \Ua With resolution enhancement techniques see Section
(c) (d)
4.1.6). Advanced exposure tools such as the
248-nm lithographic system using a KrF
Figure 4.4 Image partitioning techniques lor projection printing, (a) Annual-field wafer scan. exdmer laser, the 193-nm lithographic system using an ArF exdmer loser, and the 157-
i/>) 1:1 stcp-and- repeat, (c) M l atluction step-and repeat. id) M:l reduction step-and-scan* 7
lithographic system using a F, excimer laser have been developed for mass produc-
11111
tion with a resolution of 0.18 urn (180 nm). 0.10 urn (100 nm), and
0.07 Mm (70 nm).
respectively.
The small image field can also be stepped over the surface of the wafer by two-
4.1.3 Masks
dimensional translations of the wafer only, while the mark remains stationary. After
the
exposure of one chip site, the wafer is moved to the next chip site and the process Masks used for IC manufacturing are usually reduction reticles. The first step in mask
is
repeated Figures 4.4/> and A.Ac show the partitioning of the wafer image bv stq>-and- making is to use a computer-aided design (CAD) system in whic h designers c an completely
repeat projection Willi a ratio of 1:1 or at a demagnification ratio
of A/:l (e.g., 10:1 for a
describe the circuit patterns electrically. The digital data produced by the CAD system
10 times reduction on the wafer), respectively. The demagnification then drives a pattern generator, which is an electron beam lithographic system .see Section
ratio is an impor-
tant factor in our ability to produce both the lens and the mask from which we wish to 4.2.1) that transfers the patterns directly to electron-sensitized mask. The mask consists
print. The 1:1 optical Systems are easier to design and fabricate than 10:1 or 5:1 reduc- of a fused -silica substrate covered with a chromium layer. The circuit pattern is first trans-
tion Systems, but it is much more difficult to produce defect-free masks at 1:1 than it is ferred to the electron-sensitized layer (electron resist), which is transferred once more
at a 10:1 or a 5:1 demagnification ratio.
Reduction projection lithography can also print larger wafers without
redesigning
the stepper lens, as long as the field size (i.e.. the exposure area onto the wafer) of the
lens is large enough 10 contain one or more IC
chips. When the chip size exceeds the
field size of the lens, further partitioning of the image
on the reticle is necessary. Figure In
4.4a, the image field on the
can be a narrow arc shape for AM step-and-scan pro-
reticle
jection lithography. The step-and-scan system yields two-dimensional
translations of the
wafer with speed V. and one-dimensional translation of the mask
with a speed times M
that of the wafer speed.
The resolution of a projection system is given by
* Chapter 4 Photolithography
41 Optical Lithography <* 67
1000 Mask as seen by nak. ,1 ,-%<•
Device feature
mask on which patterns of geometric shapes have Ixsen fonned. A few secondary chip sites,
duced during the manufacture of the mask 01 during subsequent lithographic processes.
Even a small mask-defect density has a profound effect on the final [C yield. Yield is
defined as the ratio of good chips per wafer to the total number of chips per wafer [see
Chapter 10). Asa first-order approximation, the yield V for a given masking level can be
expressed as
200 300 400
Wavelength (nm)
Y= e^ (5)
Figure 4.6 Typical lni;li-pie\Mirc ineicurx -.ire lamp spectrum. where D„ is the average number of "fatal" defects per unit area, and A is the detect -
r=rVIM (6)
into the underlying chromium layer for the finished mask, The details of pattern Figure 4.S shows the mask limit yield for a 10-level lithographic process as .i function
1
fer are considered in Section 4.1.5. of chip size for various values of defect densities. For example, forZ? 0.25 defect/cm ,
The patterns on a mask represent one level of an IC design. The composite layout die yield is 10% for a chip size of 90 mn r and it drops to abot it.
G «r d lip size of 180 nun W 1
1
1
is broken into mask levels that correspond to the IC process sequence, such as the iso- Therefore, inspection and cleaning of masks are Important to achieve high yields on large
lation region on one level, tin- gate region on another, ami so on. Tvpically. 15 to 20 chips. Of course, an ultracle.m processing area i*> mandatory for lithographic processing
become more soluble and are thus more easily removed in the development process. The
high transmission at shorter wavelengths, and its mechanical strength. Figure 4.7 shows a
: . '
hv
hv
Figure 4.8 Yield tor I 10-mask lithographic prows* with various defect densities per level.
Figure 4.9 Exposure response curve and cross section of the resist Image after development 1
lame at thOM OO the mask. For neg/attve resist*, the exposed regions become less solu-
ble, and the patterns formed in the negative resist are the reverse of the mask patterns.
where Ej is the energy obtained by drawing the tangent at £, to reach 100* resist thick-
in the developer solution After exposure, the photosensitive compound absorbs radia- The image cross section in Figure 4.9fl illustrates the relationship between theedges
of a photomask image and the corresponding edges of the resist images after develop-
tion in the exposed pattern areas, changes its chemical structure, and Incomes soluble
ment. Theedges of the resist image arc- generally not at the vertically projected positions
in the developer solution. After development, the exposed areas are removed.
of the mask edges because of diffraction. The edge of the re sist image corresponds to
Negative photoresists are polymers combined with a photosensitive compound. After
compound absorbs the optical energv and converts into the position where the total absorbed optical energv e.jiuls the threshold energy £r
expOSUfO! the photosensitive it
Figure \Mh shows the exposure lesixin.se curve and image ross sec tion for a nega-
chemical energy to polymer cross-linking reaction. This reaction causes cross
initiate a c
linking ol the polymer molecules. The cross-linked polymer has a higher molecular weight
tive- resist. The negative- resist remains couipletelv soluble in the developer solution for
exposure energies lower than £,. Alx>ve £,, more of the resist film remains after devel-
and Ik-coiiics insoluble in the developer solution. After development, the unexposed areas
are remov ed One major drawback of a negative photoresist is that in the development opment. At exposure energies twice the threshold energy, the resist film becomes essen-
tially insoluble in the devclojxT. The sensitivity of a negative resist is defined as the energv
process* the whole resist mass swells by absorbing developer solvent. This swelling
required to retain of the original resist film thickness in the exposed region. The
limits the re solution of negative photoresists.
Figure -1.9a shows a typical exposure response curse and image- cross section for parameter y is defined similarly to y in Eq. 7. except that £, and £, are interchanged
positive resist.
1
In addition to £T . a paramete r y. the contrast ratio, is defined to characterize the SOLUTION For thepositiye resist, E,- 90 mj/cm* and £, .45mjfcn. so
'
70 Chapter 4. Photolithography
4.1 Optical Lithography * 71
E, = ' OjfcW and E,
1
For the MQtfM resist. => 12 mj/cm*. SO
For deep UV lithographv (e.g.. 24S and 193 inn), we cannot use conventional photoresists because
tlu-M resists require deep I V which will ause ns damage und lower
high dose exposure in i l<
throughput Ch, miail-<iinphfn ,l nsist ('AH has Ihcm developed tor the deep UV process. CAR
•
consists of I photo-acid generator, a resin polymer, and a toivent ( JAR Is very sensitive to deep
FY i .uh.ition. and the exposed and unexposed regions dillcr greatly in their solubility in the devel-
oper solution.
Figure 4.10 illustrates the steps to transfer 1C patterns from a mask to a silicon wafer
that Ills an insulating SiO. layer Conned on its surface." The wafer is placed in a clean
room, which typically is Illuminated with yellow light, since photoresists are not sensi-
tive to xvavelengtlis greater than 0.5 win. To ensure satisfactory adhesion of the resist,
the surface must l>e changed from hydrophilic to hydrophobic. This change can be made
After the spinning step, the wafer is "soft baked" (typically at 90-120°C for 60-120
seconds) to remove the solvent from the photoresist film and to increase resist adhesion
to the wafer. The wafer is aligned with respect to the mask in an optical lithographic sys-
tem, and the resist is exposed to UV light, as shown in Figure 4.10/;. If a positive pho-
toresist is used, the exposed resist is dissolved in the developer, as shown on the left si
of Figure 4.10c. Photoresist development is usually done by flooding the w afer with
developer solution. The wafer then rinsed and dried. After development, "post bak-
is
ing' at approximately 100°C 180°C may be required to increase the adhesion of the
to
resist to the substrate. The wafer is then put in an ambient that etches the exposed insu-
lation layer but does not attack the resist, as shown in Figure 4.10r7. Finally, the resist
stripped (e.g., using solvents or plasma oxidation), leaving behind an insulator image ("
pattern) that is the same as the opaque image on the mask (left side of Fig. 4.10c).
For negative photoresist, the procedures described are also applicable, except that
the unexposed areas are removed. The final insulator image (right side of Figure 4.1! Figure 4.10 Details of the optica! lithographic pattern transfer process.*
is the reverse of the opaque image on the mask.
The image Can !>< used as a mask for subsequent processing. For example.
insulator
ion implantation (see Chapter 7) can l>e done to dope the exposed semiconductor region, The film (e.g., aluminum) is deposited over the resist and the substrate (Fig I I Ic The
film thickness must be smaller than that of the resist. Those portions of the film on the
but not the area covered by the insulator. The dopant pattern is a duplicate of the design
pattern on the photomask for a negative photoresist or is its complementary pattern for resist are removed bv selectively dissolving the resist laser in an appropriate liquid etchant
so that the overlying film is lifted off and removed Rg. 4. 1 W). The liftoff technique Ls
a positixe photoresist. The complete circuit Ls fabricated by aligning the next mask in
I
Figure 4.12 The principle of phase-shift technology (a) Conventional technology! lb) Phase-shift
technology*
4.1.6 Resolution Enhancement Techniques However, due to deep-submicron IC process requirements, optical lithograph) has
some limitations that have not yet been solved. Although we can use PSM or OPC to
been continuously challenged to provide better resolution, greater
Optic.il lithography has
been met by extend its useful span, the complexity of mask production and mask inspection cannot
DO F. and wider exposure latitude in IC processing. These challenges have
tools and developing new resists. In addition, be easily resolved. In addition, the cost of masks is very high. Therefore, we need t<> find
reducing the wavelength of the exposure
developed to extend the capability alternatives to optical lithography to process deep-submicron or nanometer ICs.
many resolution enhancement techniques have been
Various t\pcs of next-generation lithographic methods for IC fabrication are discussed
of optical lithography to even smaller feature lengths. lithography, extreme UV lithography, x-ray lithography,
(PSM). in this section. Electron beam
An important resolution enhancement technique is the phase-shifting mask among these methods.
4. 1 2a). die elec- and ion be am lithography are considered, as are the differences
The basic concept is shown in Figure 4.12." For a conventional mask (Fig.
Diffraction and the limited
tric Held has the same phase at even- aperture (clear area).
wafer, as shown by the dot-
resolution of the optical system spread the electric field at the 4.2.1 Electron Beam Lithography
waves by die adjacent apertures enliances the field
ted lines. Interference between diffracted
photomasks. Relatively
proportional to the square of the electric field,
Electron beam (ore-beam) lithography is primarily used to produce
between them. Because the intensity (/> is
by a focused electron beam with-
tools are dedicated to direct exposure of the
resist
few
it becomes difficult to separate the
two images that are projected close to one another. an electron beam lithograph) system. he I
cap*
used to position the substrate to be pattern* d
shapes of adjacent subresolution geometry to improve imaging
Which uses modified diameter a precision mechanical stage is
square contact hole with dimensions near the resolution limit will the genera,, ,1 subuueron
bility. For example, a electron beam lithography include
additional geometry at The advantages8 of depth
print arK as a circle. Modifying the contact-hole pattern with and prec isely controlled operation, greater
,,sist geometries highly automated
...
minium
Ekxiron £un illinium
uwinuiw
minium
minium
Alignment coil ^nMfHiUiMl
it
ii mil
iiinmim IIIIIU
in iiiim ii
niniiiiiimim ii
Kicn! mini, iim-i iiiimniiiiiim mini
mmimmmii 1 1 1 1 1 1
IcilS iiiiiiiniimim
mmiiuiimm mini
Raster wall mini
Hlaiiking plal«-s iiiim
liiiniiiiiiiiiiiiiiiiiiiiiiim in.
S<n>lhloi)ll<li UN. :
k-itf
limiting aperture
SuUtrate
Mechanical stage has higher throughput than the conventional Gaussian spot beam. It is also possible to
* pattern a complex geometric shape in one exposure with an electron beam system; this
Figure 4.13 9cbei>utK- .»t an electron beam lithography machine.
is called cdl projection, as shown ,„ ihe far right of Figure 4. 1-k The cell projection tech-
11
nique is particularly suitable for highly repetitive designs, as in MOS memory cells, since
of focus than that available from optical lithography, and direct patterning on a semi- several memory cell patterns can !><• exposed at once < Jell protection lias not vet achieved
conductor wafer without using a mask. The disadvantage is that electron beam lithog- the throughput ol optical exposure tools.
raph) iii.k bines have low throughput —
approximately 10 wafers per hour at less than
0.25 Urn resolution This throughput is adequate for the production of photomasks, for Electron Resist
situations that require smallnumbers of custom circuits, and for design verification. Electron resists are polymers. The behavior of an electron beam resist is similar to that
However, for maskless direct writing, the machine must have the highest possible of a photoresist; that is. a chemical or physical change is induced in the resist by irradi-
throughput, and therefore the largest beam diameter possible consistent with the min- ation. This change allows the resist to be patterned. For a positive electron resist, the
imum device dimensions. pot) uifi -electron interaction anises chemical bonds to In- broken chain scission) to form
1
There are basically two wavs to scan the focused electron beam: raster scan and vec- shorter molecular fragments, as shown in Figure 4. 15a.
'
As a result, the molecular weight
u M an " In a raster.scan system, resist patterns are written by a vertically oriented beam is reduced in the irradiated area, which can be dissolved subsequently in a developer solu-
ii
thatmines tli rough a regular mode, as shown in Figure 4.1-Wj. The beam scans sequen- tion that attacks the low-molecular-weight material. Common positive electron resists
tial ovei even possible location on the mask and is blanked (turned off' where no expo- include poly-methyl rnethacrylate (PMMAJ and pory-butene-1 sulfone (PBS). Positive
sure is required. All patterns on the area to be written must be subdivided into individual electron resists can acliieve resolution of 0.1 um or better.
addresses. and a given pattern must have a minimum incremental interval that is evenly For a negative electron resist, the irradiation causes radiation-induced polymer link-
divisible by the beam address size. ing, as shown in Figure 4.15b. The cross linking creates a complex three-dimensional struc-
nonirradiated pohuier. The
In a t error MM system, shown in Figure 4.14/;. the beam is directed only to the ture with a molecular weight higher than that of the
can be dissolved in a developer solution that does not attack me higfr-
requested pattern features and jumps from feature to feature, rather than scanning I
nonirradiated resist
molecular-weight material. Poly-glycidyl inethacr\late-co-ethvl-acr\ late (COP) is a com-
whole chip, as in raster scan. For mam chips, the average exposed region is only 20%
mon negative electron resist. COP. like most negative photoresists, also swells during
the chip area, so time is saved using a vector scan system.
development, so resolution is limited to about 1 um.
Figure 4. I k shows several tvpes of electron
beams employed for e-beam lithogra-
phv the Gaussian spot beam (round beam), die variable-shaped beam, and cell projec-
tion In the variable-shaped beam system, the patterning beam has a rectangular cross The Proximity Effect
in optical btbooaphy, the resolution is limited In diilractioi, of light, in electron beam lithog-
•-• . ti. m . >t variable si/e and aspect ratio It offers the advantage of exposing several address
not limited by diffraction (because the wavelengths associated
units simultaneously. Therefore, the vector scan method using a variable-shaped raphy the resolution is
«
76 * Chapter 4. Photolithography
(«)
Crosslink
(b)
n
4.15 Schematic of positive- and negative resists used in electron beam lithography.
with electrons of a few keV and higher energies are less than 0.1 nm) but by electron
substrate, they undergo
scattering. When electrons penetrate the resist film and underlying
trons spread out as they travel through the material until either all of their energy is
the xz plane. This figure shows qualitatively that the electrons are distributed in an oblong
pear-shaped volume with a diameter on the same order of magnitude as the electron pen-
etration depth (-3.5 |im). Also, many electrons undergo lwckscattering collisions and travel
backward from the silicon substrate into the PMMA
resist film and leave the material.
trons effectively can irradiate several micrometers away from the center of the expos
beam. Since the dose of a resist Is given by the sum of the irradiations from all surroum
areas, electron lx?am irradiation at one location will affect the irradiation in neighboring
locations. This phenomenon is called the proximity effect. The proximity effect places a
limit on the minimum spacings between pattern features. To correct for the proximity effect,
patterns are divided into smaller segments. The incident electron dose in each seg
is adjusted so that the integrated dose from all its neighlxmng segments is the correct <
sure dose. This approach further decreases the throughput of the electron beam system
because of the additional computer time required to expose the subdivided resist patterns.
78 D..pc.r4 Ptvotolrthography
4.2 Next-Generation Lithographic Methods <* 79
* schematic diagram of ail EUV lithograph) system. A laser-produced pliisnia or syn- * ,r,M s 00 ,1 < " r
"
material and most materials have
chrotron radiation can serve as the source of EUV having a wavelength of 10 to 14 nm. '!
;
.,</.,! "m,..lu. nasksul,s. at,-mus.l,,. ll 11IMll(
lowtranspetetiei
produced by patterning an absorber mate-
1
I
m | ini , |
.
2 ,,„, tin, k made o| lou , l ,
FA A mask
>
mask movement to reprtxhiee the image belt! on all chip sites on the wafer surface. A 25% to ay.* of the incident flux and must therefore be cooled. An x-ra\ rests! Urn
fllicl
required to perform the chip-site alignment and to control the wafer
1
precision system is will absorb about 10% of the incident flux. There
are no reflections Iron, the substrate
and mask stage movements and the exposure dose during the scanning process. to create standing waves, so antireflection coatings are
uunc.-ssarv
EUV lithographv is capable of printing 50-nin features with PMMA resist using 13-nm
We can use electron beam resists as x-ray resists because when .... x-ray is absorbed
radiation 1 low. \. r the production of EUV exposure tools has a number of challenges. bv an atom, theatom goes tOan excite,! state with the emission of an
elcCtTOa The excited
Since EUV is strongly absorbed in ;dl materials, the lithography process must be per- atom returns to its ground state by emitting an x-ray hav ing different wavelength
than .,
formed vacuum. The camera must use reflective lens elements, and the mirrors must
in a the mcident x-ray. This x-ray is absorbed by another atom and the process repeal's. Sin< ,-
In- coated with multilaver coatings that produce distributed quarter-wave Bragg reflec- all the processes result the emission of electrons, a resist film under x-ray irradiation
in
tors. In addition, the mask blank must also be multilayer coated to maximize its reflec- equivalent to one
is being irradiated by a large number of seccnclaiy electrons iron, an)
tivity at X of 10 to 14 nm. of the other processes. Once the resist film is irradiated, chain cross linking or chain ids-
sion will occur, depending on 1 1
1<
- type of resist.
X-rav lithography
1 ' 1
fabrication of integrated circuits at 100 nm. The synchrotron storage ring is the choice Ion beam lithography can achieve higher resolution than optical, It-ray, or electron beam
of x-ray source for high-volume manufacturing. It can provide a large amount of colli- hniques because ions have a higher mass and therefore scatter less than
litho graphic tec
mated flux and can easily accommodate 10 to 20 exposure tools. electrons. The most important application is the repair oi masks lor optical lithographs,
XRL uses a shallow printing method similar to optical proximity printing. Figure 4.18 k tor which commercial systems are available.
shows a schematic XRL system. The x-ray wavelength is about nm, and the printing is 1 Figure 4.19 shows the computer-simulated trajectories of 50 H' ions implanted at
through a lx mask in close proximity (10-40 urn) to the wafer. Since x-ray absorption 60 keY into PMMA and various substrates.
1
depth of 0.4 pin is only 0.1 pin in all cases (compare with Fig. 4.16Vi for electrons).
Backscattering is completely absent for the silicon substrate, and then- is only a small
,r
Figure 4.18 Schematic representation of a proximity x-ray lithography system.
. I
amount of backscatteriiiu lor the gold substrate. HoWW, ion beJUD lithography may suf- .... even moreimr^rtant key driver for the semiconductor industn beceuseofme
reotdre-
hi from random m stochastic! s|xiee-chargc effects, causing bre>adening of (he ion l*>am. nets o. snialle, feature si,e and
BtwS
tem .md
There arc
a mask-lx-am
t\M> rvprs ot'iou
%\Mi-in
beam lithograph)
The fanner system
systems: a scanning focused-beam sys-
is similar to the electron
H\ The
system is similar to
beam machine ST ( -'' n
;'
,
''«ly
H itW
\t
tl"-t<vhiH,l«,g) clevelopme
tighter overlay tolerant. In
*?*
addition,
«*" ,(;
^»&ng
tool
Lis its own limitations, the diffraction effect in optical lithography, the proximity ef 'ROLITIl is a Windows-! used program that uses a jx)sitive/i«n;ati\c
photoresist opti-
m electron 1h .uu lithographs, mask fabrication complexities in x-ray lithography, calbthography model originally developed by Chris Mack. PROUTI simulates the
com-
1 ''
1
cult) m mask blank production for EUV lithography, and stochastic space charge in ion plete one- and two-dimensional optical lithography process from
aerial Image formation
Ihmiii lithography through resist exposure and dev elopment. The output of the program is an at curate pre-
For IC fabrication, man) mask levels are involved However, it is not necessary to diction of the final resist profile, which is presented In a wide variet) of images, plots,
use the vame lithographic method for all levels. A mlx-and-niatch approach can take advan- graphs, and calculations. In particular. PROLITH is able to simulate the following:
tage 1 if the uniipie features of each lithographic process to improve resolution and to miw-
Formation of an image of a mask feature by an optic al projection system
imize throughput For example, a 4:1 EUV method can In- used for the most critic;d
levels 5sl optical System can be used for the rest.
whereas 4:1 «>r
l '.\|M)sure of photoresist by this image
entttOd around 2010." With each new technology generation, lithography has
PROLITH accepts lithography information in the form of data files and input param-
eters and uses this information to simulate standard and adv anced lithography processes.
To run PROLITH. the user simply clicks on the PROLITH icon from the Windows Start
TABLE 4.1 Comparison of Various Lithographic Technologies menu. After a successful license search, the Imaging Tool parameters window appears
AA Beam see Fig.
1.2(1 As the user makes choices from the View menu. PROLITH displays win-
1.
( Optical SCALPEL 1 X-ray Ion
24V 193 nm which parameters may be entered in order to view simulation results. These can
d< rw S in
be observed from the Graphs menu. These ideas are illustrated in Example 3.
Kxpmirr Toot
Source I.iM-r Filament Laser plasma Synchrotron Multicusp
EXAMPLE 3
Diffraction limited Yes No Yes Yes No
Refractive Refractive Refractive No optics Full Held l se PROLITH to view the resist profile fin the cylindrical mask feature in Figure 4 SOtfta expo-
Optfca
refractive sure and development Assume the following process conditions
200- mm wafers/hr
Pre-bake time = 60 seconds
Staxk
Numerical aperture of the lens = 0.5
IX-ii Signification 4x 4x 4x lx 4x
Optical prmimitv Yes No Yes No Exposure wavelength = 365 nm
Yes
1
correction Exposure energy = 150 mj/cm
BeAifen path Trammivsion Transmission Reflection Transmission Stencil Post-exposure hake temperature = 1 10°C
K«uf Post-exposure bake time = 60 seconds
Singlr or multilayer Singh- Single Surface Single Single Development timer - 60 seconds
imaging SIFT 245/501
Developer .
4.4 SUMMARY
) *0 »l» Hft jTg ^fc»»4-» - ill HI T I t I
totranslr, s,n
, g,„„,h a] , he ^conductor tadustr, b b dired resull ... the ,
a
1,-r and s,„alfer circuit pattern* on..,
s.-un. onduc-.or waf,, v (
ium-n.lv .hi-
«sl majority <>l lithographic
equipmenl is optica] systems This chapter
conaideredvar.
.oms expos,,,,- lewis, masks, photoresists,
and the clean room for optical Mrcapln
Th,
primary factor limiting resolution ... optical
of axlvamv.n.n.s
lithography is diffraction, i U we^bei •
REFERENCES
For a more detailed discussion on lithography, sot- (a K. Nakamura. "Urography."
1
in Y. Chang and I
G
S M Sze l-M* ' LSI Technology, McGrm -Hill. New York. 1996. <b) I* rW-Cboudbu*. Handbook of
Figure 4.20 Tin Imaging 1'ools window in PROLTTH. MicnJithography. Micronwchining. and Sficrofabricatlon. Vol 1. SPIE. Washington.
DC. 1997. (c) D A.
McCillis. -Urography." in S. M. Sw». Ed.. VLSI Technology. McGraw-Hill. New York. 1983.
2. For a more detailed discussion on etching. sec Y. T. Utl, "Etching * in C. Y. Chang ;md S. M. S«-. Eds
J.
ULSI T.rWogy. McC raw- Hill. New York, 1996.
3. J M. Duffalo and J R. Monkowski. -Particulate Contamination and IVsice Performance.- Solid Stair
Technol 27,3. 109(1984).
4 I! P Tseng and R Jansen. "Clcanroom Technology." in C. Y. Chang and S. M. Sw. Eds.. VLSI
Technology- HcGltW-IOD. New York. 1996.
6.
J.
H Bruning. "A Tutorial on Optical Uthography." in D. A. Doanc. et al.. Eds.. Semiconductor
Technology. Electrochemical Soc.. Pcnningston. 1982
7. R. K. Watts and J
H. Bruning. "A Review of Fine-Urn- Lithographic Techniques: Present and Future."
Solid State Technol . 24, 5. 99 ( 1981 ).
8. W. C. Till and J T. Luxon. Integrated Circuits. Materials. Dct ices. and Fabrication. Prentice-Hall.
Englewwd Chffs. NJ. 1982.
10. D. P. Kern, ct at, "Practical Aspects of MicrofabricaUon in the 100-nm Region." Solid State Technol .
27. 2. 127(1984).
11.
J.
A Reynolds. "An Overview of e-Beam Mask-Making." Solid State Technol . 22. S. 87 (1979).
12. Y. Somcda. et al.. "Electron-Beam Oil Projection Lithograph}-: Its Aecur.ny and Its Throughput."
13. W L Brown. T Vcnkat.vm. and A Wagner. 'Ion Beam UtlKniraphy." Solid State Technol . 24. S. 60 I9S1
14 D. S. KsM-r .md N W
Viswanatlun. "Monte Carlo Simulation of Spacully Distributed Beams in
16. P. Silverman. "Proximity X-Ray Lithography." White Paper. Sematecli Ne.\l Generation Ijtliography
J
\V,.rk«h. vO.!..r.i.l..Spnin;x. Dei 7-10. IJ»N
1
17. L Karajiipens. < ! .! . "Ion Beam Exposure Profiles in PMMA-Computer Simulation.";. Vac. Sci.
2001.
s rhr international IbehtukM Riwhiuip for Semiconductors, Semiconductor Ind. Assoc., San Jose, CA.
Etching
19 PBOUTHf2 l Vr'» Manual. F1NI.E Technologies. Austin. TX, 1998.
PROBLEMS
As discussed in the previous chapter, lithography is the process of transferring patterns
SECTION 4.1: OPTICAL LITHOGRAPHY to photoresist covering the surface ofa semiconductor wafer. To produce c ircuit features,
1. For a daS3 100 clean room, find the iiimi!>er of dust particles per cubic meter with parti- these resist patterns must be transferred into the underlying layers comprising the de\ke.
cle sizes a Ivtween 0 5 and 1 Urn. lb) between 1 and 2 Um, and (c) above 2 Jim. The pattern transfer is accomplished by an etching process that selectively removes
2. Find the final yield for a nine- mask-level proevss in which the av erage tat J defect density per unmasked portions ofa layer.! A brief description of etching was given in Section 1.4.2.
enr is 0.1 for four lewis, 0.25 for four levels. and 1.0 for one level. The chip area is 50 mm 2
. The present chapter covers the following topics:
4. (a)For an ArF cuimei laser 193-nm optical lithographic system with NA 0.65, k, = 0.60,
5. The plots in Figure 4.9 are called nsjHmse Curves in microlithography. (a) What are the conductor wafers sliced from an ingot (Chapter 2). chemical etchants are used for lap-
advantages and disadvantages of using resists with high y values? (b) Conventional resists ping and polishing to give an optically Hat. damage-free surface. Trior to thermal oxidation
cannot lx- used for 248-nra or 193-nm lithography. Why not? (Chapter 3) or epitaxial growth (Chapter 8), semiconductor wafers are chemically cleaned
to remove contamination that results from handling and storing. Wet chemical et< King
SECTION 4.2: NEXT-GENERATION LITHOGRAPHIC METHODS is especially suitable for blanket etches (i.e.. over the whole wafer surface) of poly-silicon,
e-beam lithography, (b) How can alignment Ik- performed for e-beam lithography? Why The mechanisms for wet chemical etching invoke three essential steps, .is illustrated
is alignment in x-ray lithography so difficult? (c) What are the potential advantages of in Figure 5.1: The rcactants are transported by diffusion to the reacting surface, chem-
vr.i\ lithography over e-beam lithography? ical reactions occur at the surface, and the products from the surface are removed by
7. Why has the operating mode (if optical lithographic systems evolved from proximity print- diffusion. Both agitation and the temperature of the etehant solution influence the etch
ing to 1:1 projection printing and finally to 5:1 projection step-and-repeat? (b) Is it possi- rate, which is the amount of film removed by etching per unit time. In IC processing,
ble to build a step-and-scan x-ray lithographic system? Why or why not? most wet chemical etches proceed by immersing the wafers in a chemical solution or by
spraying the wafers with the etehant solution. For immersion etching, the wafer Is immersed
SECTION 4.3: PHOTOLITHOGRAPHY SIMULATION in the etch solution, and mechanical agitation is usually required to ensure etch unifor-
mity and a consistent etch Spray etching has gradually replaced immersion etching
rate.
8. Repeat Example 3 with the following revised process conditions:
because it greatly increases the etch rate- and uniformity by constantly supplying Ires!,
Pre-bake temperature = 100°C etehant to the wafer surface.
Prc-bake time = 5 minutes For semiconductor production lines, highly uniform etch rates are important Etch
Exposure energy = 50 inj/cm* rates must be uniform across a wafer, from wafer to wafer, from run to run, and lor any
variations in feature sizes and pattern densities. Etch rate uniformity is given by
the fol-
Post-exposure bake temperature = 120°C
Post-exposure bake time = 15 minutes lowing equation:
Development time = 60 seconds etch rate-.\1 ininium etch rate)
(Maximum
Developer = MF319 Etch rate uniformity (ft)
. .
=
(M;Lximmnetchrate + NIiniimini etch rate)
^ '
W...
s.->
S6 * Chapter 5. Etching
L;;!,
1,1 " Uer -
-
^^^^^^
or
W(,
= \V„-2/cot.54.7°
wju-re u; fc the width of the window .... the wafer surface .,,..1 / b the etched depth „
i
5.1 Basic mechanisms in wet cheniie.ll etching
Calculate the Al average etdl rate and etch rate uniformity on a 200-inm diameter silicon wafer, The wet etching of silicon dioxide is commonly
achieved in a dilute solution of if with
assuming the etch rates at the t enter, left, right, top. and bottom of the wafer are 7"ll. M2. 765] I
SOLUTION
For semiconductor materials, wet chemical etching usually proceeds by oxidation, fol-
lowed by the dissolution of the oxide by a chemical reaction. For silicon, the most com-
inonb used etchants are mixtures of nitric acid (UNO,) and hydrofluoric acid (HF) in (a)
'
water or acetic acid (CI I COOH). Nitric acid oxidizes silicon to form a SiO, layer.
2 '
oxidation reaction is
the etch rate is expected to be slower for the (111) plane. A commonly Figure 52 Orientation-dependent etching.' (a) Through window patterns on <100> -oriented
used orientation-
dependent etch for silicon consists of a mixture of KOH in water and isopropyl alcohol. silicon, (b) Through window patterns on <110> -oriented silicon.
5.2 Dry Etching « 89
ol.m-d t,. tx
, .ihufUml III solution (B1IF\ also called huff. -red oxuh rich I
BOE). The TABLE 5.1 Etchants lor Insulators and Conductors
.'...!,!, \ || r ti> 111" « nl mis the pi I value -uul leplenishes tin depletion of tin- (1,
Material Etchant Composition
ciridr ions, thus maintaining stable etching performance. Tin* overall reaction for Etch Rate tnmAnhi)
• :< lung is the same .is tli.it it Kij 3 The etch rate of Si(). etching dcj>ends on et<
i SK>( 28 ml HP
solution etchant concentration, agitation, anil temperature. In addition density. |x>ros- 170 ml IIF Buffered HF 100
it\ iiiicrostnicturc. and the presence ol impurities in the oxide influence the etch rate. H3gNH«F
For example, a high concentration ol phosphorus in the oxide results in a rapid increase
15 ml HF
m tlw etch rate, and a looscK structured oxide formed b\ chemical vaj*>r deposition (CM))
10 ml iino Petefa 12
or sputtering exliihits a faster etch rate than thermally grown oxide.
300 ml no
Silicon dioxide can also be etched in varx>r-ph.isc I IF Vapor-phase I IF oxide etch
Si,N 4 Buffered HF
te< hnology has a potential for submicron feature etching liecause the process can l>e well
05
controlled. A] II,P0 4 III
4 ml UNO,
5 13 Silicon Nitride and Polysilicon Etching
3 5 ml CI I COOII 30
73.nl II I'O,
Silicon nitnde films are ctchaMc at room temperature in concentrated HF or buffered 19.5 ml Hfi
IIF and in a boiling II I'O, solution Selective etching of nitride to oxide is done with An 4gKI LOOO
S5% 11,1*0, at 180°C because this solution attacks silicon dioxide ven slowly. The etch
rate is rypic.il l\ li> urn mm for silicon nitride, but less than 1 nm/min for silicon dioxide.
However, photoresist adhesion problems are encountered when etching nitride with boil- 111 ml n o
N!" 5 ml I'M .500
ing H P0 solution. Better patterning can Ik- achieved by depositing a thin oxide layer
: 4
II
on top of the nitride film before resist coating. The resist pattern is transferred to the 2 ml UNO,
•1 ml ( II COOII
oxide layer, which then acts as a mask tor subsequent nitride etching.
Etching
150 ml HjO
[v.)|\ silicon is similar to etching single-crxstal silicon. However, the etch rate
is considerably faster because of the gram boundaries. The etch solution is usually I ml UNO
ified to ensure
does not attack the underlying gate oxide. Dopant concentn
tliat it Pt 7 ml I ICl 50
and temperature may affect the etch rate of polysilicon. 8ml no
34gKIIjP0 4
5.1.4 Aluminum Etching
w 13 4 g KOI 1 160
33 K K,Fe(CN)6
Aluminum and aluminum etched in heated solutions of phos-
alloy films arc generally 11. 0 to make 1 liter
phoric acid. Bltlfc acid, acetic acid, and D) water. The typical etchant is a solution of 73%
1
1
I'O,. 4<* UNO,. 3.5% CH ,COOH. and 19.5% DI water at 30°C to SO°C. The wet etch-
ing of aluminum proceeds as follows: UNO ,
oxidizes aluminum, and H.PO, then dis-
solves the oxidized aluminum. The etch rate depends on etchant concentration,
an etchant with an S: 1 : 1 volume ratio of H ;
SO,:II () H O. the etch rate is 0 S Uin/min
temperature, agitation of the wafers, and impurities or alloys in the aluminum film. For
for the Ca face and 1.5 Uin/min for all Other faces. For an etchant with
<1 ll> a 3:1:50
example, the etc h rate is reduced when copper is added to the aluminum.
volume ratio of H^PO, O bVetch rate is 0.4 uin/min for the <1 1> Ca
! I 1 1 ( ). 1 Dice and
Wet etching of insulating and metal films is usually done with similar c hemicals that
0.8 fim for all other feces,
dissohe these materials in bulk form and involve their conversion into soluble salts or
complexes. Generally, film materials will !>e etched more rapidly than their bulk coun-
terparts. Also, the etch rates are higher for films that have a poor microstructure. built- 5.2 DRY ETCHING
in stress, or departure from stoichiometry. or that have been irradiated. Some useful In pattern transfer operations, a resist pattern is defined b) a
lithographic process to serve
ctc hants lor insulating and metal films are listed in Table 5.1. as a mask foretchingofitsun(leiKin-U. r Fig.5.3fl)."Mostofthr layei materials e.g (
are etc hed in a wet chemical etchant, the etch rat.- is general!) isotropic (le., the lateral
515 Gallium Arsenide Etching
Figure 5.3&. If ft, is the thickness
and vertical etch rates are the same), as Illustrated in
A wide variety the lateral distance etched underneath the resist mask, we can
ol etc hes have been investigated for gallium arsenide; however, few of them of tin- layer material and /
are truly Isotropic' This is because the surface activities of the 1 1 1 Ca and (1 1 1 As
( > ) define the degree <>i anisotropy- by
faces are very different. Most etches give a polished surface on the arsenic face, but the
gallium face tends to show crystallographic defects and etches more slowlv. The most
commonly used etch.mts are the H SO.-H.O.-H.Oand H^O.-H.O^-HjO systems. For
90 > Chapter 5. Etching
5.2 Dry Etching + 91
EXAMPLE 2
Hie electron densities in HIE and HDP systems range from 10* to 10" cm 'and 10" to lO^cm '.
respectively. Assuming the RIE chamber pressure is 200 mTorr and HDP chamber pressure is
5 mTorr. calculate the ionization efficiency in RIE reactors and HDP reactors at room tempera-
ture. The ionization efficiency is the ratio of the electron density to the density of molecules.
SOLUTION
PV = nRT
where P is the pressure in atm 1 .it in - 760 000 mTorr*. V is the volume in liters. R is the Miiri-
Iht of moles. R is the gas constant (0.082 liter-atm/mol-K). and T is die absolute temperature in
(O K. respectively.
Figure 5.3 Comparison of wet chainlet] etching and dry etching for pattern transfer.' For the RIE system
The major disadvantage of wet chemical etching in pattern transfer is the undercu Ionization efficiency . (
10" - 10")/(6 38 x 10°)
of the layer underneath the mask, resulting in a loss of resolution in the etched pattern. . 156x10-1.36x10-
In practic e, for isotropic etching, the film thickness should be about one-third or less (it
the resolution required. If patterns are required with resolutions much smaller than the For the HDP system.
film thickness, anisotropic etching (i.e., 5 A, > 0) must be used. In practice, the value
1
nA' - P/RT - (5r760.O00M0.OS2 x 300) « 2.66 x 10": (mol/Uter)
of A, is chosen to be close to unity. Figure 5.3c shows the limiting case where A, 1,
- 2.66 x 10
'
x 6 02 x UP 1000
responding to / = 0 (or /{, = 0).
= 1.6x10" (cm *>
To achieve fl high-fidelity transfer Of the resist patterns required for ultralarge-scale
integration processing, dry etching methods have been developed. Dry etching is syn* Ionization efficiency - (10" - 10"VU.6 x 10")
onymous with plasma-assisted etching, which denotes several techniques thai use plasms 4
* 6.25 xlO" - 6.25 xlV
in the form of low-pressure discharges. Dry etch methods include plasma etching, reac -
5.2.1 Plasma Fundamentals 5.2.2 Etch Mechanism. Plasma Diagnostics, and End-Point Control
With
A plasma is a fully or partially ionized gas composed of equal numbers of positive and Plasma etching is a process in which a solid Bin is removed b) I chemical reaction
Ls often enhanced or induced
negative charges and a different number of unionized molec ules. A plasma is produced ground-state or excited-state neutral species, Plasma etching
1 Chapter 5 Etching 5.2 Dry Etching < 93
the material surface to form volatile products. Chemical and physical etch mechanisms liave off a thin film surface oscillates. This oscillation occurs because of the phase interler-
different characteristics. Chemical etching exhibits a high etch rate and gcod selectivity (i.e.. en< e between the light reflected from the outer and inner interfaces of the etching layer
the ratio of etch rates for different materials) and produces low ion
bombaahncnt-induced Tins !a\er must therefore Ik- optically transparent or semitransparem" to observe the OA Il-
damage, but \ields Isotropic etching can yield anisotropic profiles, but is
profiles. Physical Figure 5.5 shows a typical signal from a silicidc/polvcrystalline
lation. Si gate etch The
asm K/iati-d with low etch selectivity and high bombardment-induced damage. ( a.mbinaoons period of the oscillation is related to the change in film thickness by
of chemical and physical etching give anisotropic etch profiles, reasonably good selec-
Ar/ = A/2n (6)
ti\ih.aiHlinotl«-rat<-i>oinlKirdinent-inducedcLuuage. An example is the RIE process, which
uses a phv sic.d method to assist chemical etching or creates reactive ions to participate w here Stl is light. X is the wave-
the change in film thickness for one period of reflected
in chemical etching. length of the laser and n is the refractive index of the layer being etched. For exam-
light,
ple, Ar/ for polysilicon is 80 nm. measured by using a helium-neon laser source for which
X = (532.8 nm.
Siliride/pol«ilicon etch
experimental curve
Stagnant gas layer
(4) Reaction
(5) Desorptioii and diffusion
into bulk
(3) Adsorption
Mechanisms and Pressure Ranges of Plasma Reactors by choosing the proper etch chemistry; lor
TABLE 52 Etch example, 1a nolyrnerfaing the silicon mrtace
configuration HiK etch, as shown in Rgure 5.7, can separate plasma generation from Ion
Chcmicul 0.1-10 transport, lonenerg)
Barrel Hefting is controlled through a separate bias o„ the u-afer
electrode thereby
Chemical 0.1-10 minimizing the
Downstream plasma etching loss ol selectivity and the ion l>o...bard.ne.>t-u.ducvd damage observed m
Chemical and physical 0.01-1
RMKdW ion etching (RIE) most traditional R1E systems.
Chemical ami physical 0.01-1
Magnetic enhanced HIE
Chemical and physical 0.001-0.1
Magnetic confinement trunk- HIE Electron Cyclotron Resonance Plasma Etching
Chemic.il and phytical 0.001-0.1
Elect nm cyclotron resonance Most parallel-plate plasma etchers, except triode HIE. do not provide the
ability to con-
plasma etch trol plasma parameters such as electron energy,
chemical .mil physical 0.001-0.1 plasma density, .md reactanl density Inde-
Inductively coupled plasma or
pendently. As a result, ion bombardment-induced damage becomes a serious problem.
transformer-coupled plasma
Chemical and physical 0.001 -It.l Theefecfrwi cyclotron resonance (ECR) reactor combines microwave povvei with a static
Stirf.«<-<- wav e coupled plasma
etching
magnetic field to force electrons to circulate around the magnetic Held lines at all angu-
or helicon plasn i
lar In .juency. When tins frequency equals the applied microwave frequency, a resonance
coupling occurs between the electron energy and the applied electric Held that results
A comparison of pres- in a high degree of dissociation and ionization (10'-' for ECR compared with 10'" for RIE).
in the*pes of etching equipment that "re conrnjercially available.
reactors is shown in Figure Figure 5.S shows an ECR reaction chamber configuration. Microwave power is coupled
sure operating ranges and ion energies for different types of
combination of pressure, through a microwave window into the ECR source region. The magnetic field is sup-
(i Kadi etch tool is designed empirically and uses a particular
and source frequency to control tin- two primary etch
plied from the magnetic coils. ECR plasma systems can also be* used in thin film depo-
electrode configuration and type,
sition. High efficiency in exciting the reactants in ECR plasmas allows the deposition of
mechanisms—chemical and physical Higher etch rates and tool automation
.re required
films at room temperature without the need for thermal activation.
for most .-tellers used in manufacturing.
subjected a heavy bombardment of energetic been developed. These etchers have high plasma density (10"-10' cm" and low prO- )
Wafer
j i i i
1 10 100 1000
Pressure (mTorr) .-actor. ion The energy is separately con.
Figure 5.7 Schematic of a trhxk- reactive too etch
Figure 5J Comparison of ion energy and operating pressure ranges for different types of trolled by a bias voltage on the bottom electrode, rf. radio frequency.
plasma reactor*.
96 > Chapter 5. Etching 5.2 Dry Etching •< 97
Mtaow*rs(2 45Gll7> dielectric plate on the top of the reactor. The wafer is betted awaj from the coil, so it
is not affected b) the electromagnetic field generated by
the coil. There is little plasma
density loss because plasma is generated only a few mean free paths RWS) from the Wafel
surface. Therefore, a higli-densit) plasma and high etch rates are achieved
Plasma etching has rapidly evolved from simple batch resist stripping to large and single-
wafer processing. Etching systems continue to be improved, from the conventional RIE
tool to the high-density plasma tool for pattern transfer of deep-submk ran devices. Vside
from the etching tool, etch chemistry also plays a critical role in the performance ol the
i ''eh process. Table 5.3 some etch chemistries for different etch pun esses. Developing
lists
Figure 5.8 Schematic of an electron cyclotron resonance reactor. an etch process usuallv means optimizing etch rate, selectivity, profile control, critical dimen-
sion, damage, and so forth by adjusting a large iiuiuIkt of process parameters.
pressure plasma is generated by a flat spiral coil that is separated from the plasma by a
Vacuum load-lock
chamber
00 :
Cassette loatl'unload
chamber
multilayer metal (TWAlCu/TAN ) mtetcenned
Figure 5.10 Cluster reactive <0b etch too. for
1
etching.
Figure 5.9 Schematic of a transformer-coupled plasma reactor.
9S > Chapter 5. Etching
5.2 Dry Etching •« 99
TABLE 53 Etch Chemistries of Different Etch Processes
gate oxide ape the most m ipo * ailt recrements lor gate etebb^ For i&ati* the selec-
Etching Chemistry 1G dkani b more
Mate-rid Being Etched tlvit)
.mos, ,o,,-e„ha„c,d
etchtag prOC
tropy a, the
, Tl^eforft mul.is.ep process,,,,
JSSm
Shallow Si trench HBr/ClyO. ,s
Poh Si
HBr/O t BCl/Cl,. SF
IIBr/Cl/Oj.
BCl,CLSiCl/Cl 4 "Br/CI. .
. f.
used. .n which Afferent etch steps
selectivity (
On
the process are optimized lor etch
in
die Other hand, the trend in plasma technology
anisotropj
for anisotropic etching
L
and
Al
l„gh m- Wlmly ,s to utilize a low-pressure, high-densitv
AlSiCu BCVCVNj plasma using a relatively low power.
Most chlonue-l.ased and Immune-based chemistries
W SF,,only. NF/Cl. an be used .
for gate etching to aehu-ve
the required etch anisotropy and
TiW SF6 only selectivity.
Chlorine-based and bromine-based chemistries have a high silicon etch rate and I
I lowever. the HDP generates high-temperature electrons and subsequent!) gener-
degree of dissociation of ions and
etch selectivity to the silicon dioxide mask. The combination of HBr NF, * SFh + O, ates a high radicals. It generates far more active radicals
gas mixtures is used to form a trench capacitor with a depth of approximately 7 Jim. This .md ions than HIE or MERIE plasmas. In particular, a high F concentration worsens the
> iectivity to silicon. V arious methods have been enhance the
combination is alsoused for shallow trench Isolation etching. Asj)eci ratio-dependent etch- tried to selectivities in the
ing i.e.. variation in etch rate with aspect ratio) is often observed in deep silicon trench li -J
>
-density plasma. First, a parent gas with a high C/F ratio, suc h .is C,F ( :,F or C,F
V K ,
•'. .s attempted. Other methods to scavenge radicals have also Ix-en developed
etching, caused by limited ion and neutral transport within the trench. Figure 5.11 shows
I"
"
the dependence of average silicon trench etch rate on aspect ratio. Trenches with
more slowly than trenches with small aspect ratios. Interconnect Metal Etching
aspect ratios are etched
Etching of a metallization layer is a very important step in IC fabrication. Aluminum,
copper. ;uid tungsten are the most popular materials used for interconnection. These mate-
Polysilicon and Polycide Gate Etching
usually used rials usually require anisotropic etching. The reaction of aluminum with fluorine results
Polysilicon or polycide (i.e., low- resistance metal silicides over polysilicon) is
has a very high chemical etch rate with aluminum and tends to produce an undercut dur-
_ 0.6 to form HCl, which corrodes aluminum. An in situ exposure of the wafer to a CF, dis-
charge to exchange Cl with F and then to an oxygen discharge to remove the resist, fol-
lowed In immediate immersion in deionized water, can eliminate aluminum
corrosion.
at ambi-
Figure 5.12 shows 0.35-um TiNVAl/Ti lines and spaces on a wafer maintained
even prolonged exposure to the ambient.
1 OA ent for 72 hours. No corrosion is present after
02 -
etching at room temperature is diffic ult. Process temperatures higher than 200 ( are
damascene process is used to form < -u inter-
required to etch copper films. Therefore, the
TiN lurriei U, r
SiOj
s,o
AlC,
Brian Wet&badi
Aft. i H'. tdilm, I
Figure 5 14 Formation of tungsten plu in a
K contact hoi, I, dcpoMtin, blanket
low-p^Mirc
clnm.eal vapor deposition W
and tlien usin< reaction ion etching
etchhack
'
-pre sure CY D LPCVD) tungsten <W) has been widely used for filling contact
<
-mhos, lp^ I ., t ;i ll 1 p,t,,nl,,. t , us < .. ri«,, x< ..lU. Ilt
t
d.position«>„f0 rI nah,htv H„ l, t
lu« nne- ami chlonne-based clicimstncs etc ;
i
h
;
W and form volatile etch products. An impor-
.... nuN. n e-ch process is the blanket W ctchback to form a W plug The b3d
LPC\ I") \\ ,s deposed o„ top of a Ti\ harrier laver. as shov,,, j„ K^m- ., I t \ , wo .
rOCess ,s usuallv ..seel First. 909; of the W is etched at a high etch rate and then
u
Figure 5.12 " Wum TiN Al Ti\ lme% .mil spaces on wafer maintained .it amlm-nt lor 72 1
, l
'
rate b rtdufied to remove the remaining W with an etehant that has , bieh
W-to-TiN selectivity.
after a microwave strip .in- not corroded.
in addition to the trench. After filling, the metal and dielectric arc planarized byi 5.3 ETCH SIMULATION
i, ill mccluinicul /m/in/h/i^ (MP. mv Chapter Si. Tin- .u!% ant.i^- of damascene pr
si I'KKM inn)be used to simulate the etching process. However, etch simulation using
ingis tliat it eliminates the need for metal etch. This is ;m important concern as the
RlOva from aluminum to copper interconnections.
i
SI PREM is rodhtientaryat best. Simulation results may lie achieved using the ETCH com-
mand which allows the user to etc h all or part of any given layei ..I die top of the CUT-
rent Structure. If the material at the top of the structure is not the material -j>- eilie.l
lU-wf then no etching take, place. If the amount to In- etched is not specified, then the entire
removed.
3
layer is
EXAMPLE 3
Bteb itpphyei
Suppose W8 Want to simulate the etching of 0.3 um of the oxide grown after the dry-wet -dry ve.juenc\-
in Fxample 3 of ( Ihaptei 3.
As processmg evolves from 200-mm to 300-mm and even larger diameter wJers. con-
tuu.ed improvements are rc.pmed lor etch
uniformity across (he wafer New g. Ls
che„nstnes,uustbed,-velo H,lt,,pr.,vide.he,,np osedsei,,
I
necessarv I t mK for advanced
REFERENCES
""'''-".'V,"'
B * l,wurt/
"Chemical Etching of Silicon
1
II. the System UK. UNO . H.Oarul
HC.H.O,. 7 Uectwchem. Soc. 107. 10S (1960)
3 K E. Bean. -Anisotropic Etching in Silicon." IEEE Tram. Electron Dtxicn. ED-25, 1185 (1978).
8 la iSl i
' ' *" VnCtkai °f M ^ W>ricaUon ln 100-nm Region." Solid Stat, Techno! . 27.
5 S. lida and K llo. "Sek-ctivc Etching of Gallium Arsenide Crvsial ». II SO II <>..|| o .Svm, ,,,
9 C. O. Jung, et al.. "Advanced Plasma Technology in Mkroelc-c-troi.iw." 77nn Solid Filmy 341, 12 1999)
Distance along lln« 1 1
Figure 5.15 Plot of phosphorus concentration .is a function of depth into the silk-on substrate,
using SITKEM
PROBLEMS
ETCH Asterisks denote difficult problems.
Oxide Thickness - 0.3
PRINT Layers Chemical Concentration Phosphor
PLOT Active Net Onin-lel4 SECTION 5.1: WET CHEMICAL ETCHING
STOP End etching example 1. If the mask and the substrate cannot be etched by a particular etc -haul, sketch the edge
profile of an isotropically etched feature in a film of thickness h, for (a) etching just l<>
ness of 0.609 Urn and depicts the phosphorus incorporation in the oxide layer. ^ window defined in silicon dioxide. The etch rate normal to 100) planes is 0.6 uin'mln. (
The etch rate ratios are 100:16:1 for the ( 100):(1 10):{ 1 1 1) planes. Show tin- etc hed pn>file
5.4 SUMMARY after 20 seconds. 40 seconds, and 60 seconds.
3. Repeal the previous problem with a <110>-oriented silicon etched with i thin sio mask
The two major processes to transfer patterns in IC fabrication are photolithography and in KOI I solution. Show the etched pattern profiles on <110> Si.
etching. W et chemical etching is used extensively in semiconductor processing. It is par-
ticularly suitable for blanket etching. Tin's
4. A <100>-oriented silicon wafe r 150 mm in diameter is 625 Uin thick The wafer has 1000
chapter discussed wet chemical etching pro-
Urn x 1000 urn ICs on it The IC chips are to lx- separated by oricnlatioii-dcp. indent etch-
cesses for silicon and gallium arsenide, insulators, and metal interconnections. Wet chemical
ing. Describe two methods for doing this and calculate the fraction of the suit... t an-.,
etching was used for pattern transfer. However, undercutting of the layer underneath the
that is lost in these processes.
OUtfk resulted in loss of resolution in the etched pattern.
Dry etching methods are used to achieve high-fidelity pattern transfer. Dry etching SECTION 5.2: DRY ETCHING
issynonymous with plasma-assisted etching. This chapter considered plasma fundamentals *5. The average distance by particles between collisions is called the mean free path
trave led
and various dry etching systems, which have grown from relatively simple, parallel -plate is pressure in Tore In typical plasmas of Interest, the
m
(X). k = 5 x 10*VF (c ). where P
configurations to complex chambers with multiple frequency generators and a variety of ol gal
chamber pressure ranges from 1 Pa to 150 Pa. What are the- corresponding denstl)
process-control sensors. molecules (cm and the mean free path?
>
The challenges for future etching technology are high etch selectivity, better dimen-
a rate given by
6. Fluorine ( F) atoms etch Si at
sioned control, low .ispect ratio-dependent etching, and low plasma-induced damage.
x 10"
:
Etch rate (nm/min) = 2.86 n, x J* vxpi-E,/RT)
Low-pressure, high-density plasma reactors are necessary to meet these requirements;
104 •> Otp»riEtch«ig
!** vxp{-E,/RT)
Etch rate (nm/min) - 0.614 X Iff" n r x
hBVe * b 3 M U»:
'
cn and £. is 3.76 kcul/mol Calculate the etch rate of SiO, and Diffusion
OK h selectivity of SiO, over Si at room temperature.
etching a polysilicon gate with thin gate oxide.
8. A multiple-step etch process is required for
Hons do you design an etch process that has no micromasking. has an anisotropic etch
profile, and is selective to thin gate oxide?
xxith chlorine-
13. Describe far to eliminate the corrosion issues in Al lines after etching
Mask
based plasma.
(•)
1 1 velocity
dopant
ions
M ivk
(b)
103
106 0«Ktr6 0.«u«>n
6.1 Basic Diffusion Process * 107
ar ^
Hits dupter focuses on tin- diffusion piixvss. Ion implantation is covered in Chapter 7. allo\-s and ZnAs. for the sealed-ampule approach or ZnA-Stn r, .i
t
Sp.xnfu .illv. this chapter COS ers
• The simulation of diffusion using Sl'PRFM hash- atomic diffusion models in a solid.'
T ^^^X^^.
solid dots represent
„„,,„„,,
.
*• *~* *brate around u7e^uibrium lattta rite v
BASIC DIFFUSION PROCESS
£
6.1
for silicon and 60O'C and 1000°C for guftjun arsenide. The number of dopant atoms that
6.3W. the mechanism
|
three elements are highh soluble in silicon: they haw solubilities above 5 x lO^cnT'in
the diffusion temperature range. These dopants con Ik- introduced in several ways, includ-
ing solid sources (e.g.. BN for lx>ron. As.O, for arsenic, and P,0, for phosphorus), liq-
where the proportionality constant is the diffusion D
coeffkieni or diffusivity. Note that
uid sources (BBr v AsCl,, and POCl 3 ). and gaseous sources (B li A AsH v and PHj). .
thel >sicdriving force of the diffusion process is the cone .•titration
gradient dClth. The
However, liquid sourees are mast commonly used. A schematic diagram ol the furnace (lux Is proportional to the concentration gradient, and the dopant atoms will
move (dif-
and gas flow arrangement for a liquid source is shown in Figure 6.2. This arrangement fuse) away from a high-concentration region toward a lower-concentration region.
iv mii hi, to that used lor thermal oxidation. An example of the chemical reaction for phos-
i;
If we substitute Eq. 3 into the one-dimensional continuity equation under the c on-
phorus diffusion using a liquid source is
dition that no materials are formed or consumed in the host semiconduc tor, we obtain
4POC1, t 30, -> 2P.O, + 6CL, T (1)
The P,0, forms a glass-on-silicon wafer and is then reduced to phosphorus by silicon,
oooo oooo
Electric furnace
OOOO O OJp o
Quartz turx-
62
r
Schematic diagram of a typical
Electric furnace
where P is the diffusion ct)efllcient in curVs extrapolated to infinite temperature, and The Aflurion profile of the dopant atoms is dependent
on the Initial and boundary con-
E, is the activation energy in eV. d,t.om..Tins subsection considers two
important cases, namely constanl surface
energies r.-.piiit-cl to move dopant con-
k the intcrstiti.il diltusion model E, fa related to the
Fl centiation diffusion and enstant total dopant
diffusion In the first case,
of"/-; are found to be between 0.5
impurity atoms
tioms from one Interstitial die to another, The values are transported Iron, a vapor source onto the
semiconductor surface and diffused into
md J e\ in botch silicon and gaDium arsenide. For thevacanc) diffusion mod. is related
],
/-.'
the sennconductor wafers. The vapor source
maintains a constant level o! surface con.
to both the energies of motion and the energies of fonnation of vacancies. Thus. £ 4 for centnmo»«.,m
vacaiu v dtfruston is larger than thai for interstitial diffusion, usually between 3 and 5 eV. is deposited onto tlie semiconductor surface and is subsequently < li II used into the w at. i
-
C(x.O)
(7)
which states that the dopant concentration in the host semiconductor is initially zero The
boundary conditions are
C((U) = C, (8a)
and
CK t ) = 0
{Bb)
w here C, is the surface concentration (at x = 0). which
is independent of time. The
sec-
ond boundary condition states that at large distances from the
surface there are tioimou-
1
rify atoms.
The solution of Ficks diffusion equation that
satisfies the initial and boundary con-
ditions is given by"
«M-«Sf^ (9)
when erfc iscomplementary error function and Voi is the diffusion length. The
the
definition ol erfcand some properties of the function are summarized in Table 6.1.
The
diffusion profileTor the constant siirHicc concentration condition is shown
i„ Figure 6.5a,
w inch plots, on both linear (upper' and logarithmic (lower) scales,
thenormalized con-
centration as a function of depth for three values of the diffusion
length corresponding
to three consecutive diffusion times and a fixed
D
for a given diffusion temperature Note
that as time progresses, the dopant penetrates deeper into the semiconductor.
The total number of dopant atoms per unit area of the semiconductor is given by
lxl(r
S - constant
(CtmstMl
crfc<.t)«l-crf(.i)
0.1 uni
erf(0) =0
erf(~)«l ,0.5 pm
erf(jr)s-£-« forJt«l
//> = 1 0 pm
sit
erfe(x)3-i'- — for.i»l
10' -
"V^fslOuin
- 10
1
10*
1 0.1pm
10'
12
1
3 4
imated In triangles with height C, and base iVoi. This leads to Diffusion dcplh x (pm)
Q(t'< = C.VDf. which Diffusion depth x turn)
is close to the evict result obtained from Eq. 11. (.) (b)
A related quantity is the gradient of the diffusion profile dC/dx. The gradient can be Figure 6.5 Diffusion profiles, (a) Normalized compleincntaiy ernn I'unctiun versus distance for
obtained by differentiating Eq. 9: successive diffusion times, (b) Normalized Gaussian (unction versus distance.
^j^T j
.v,
For a boron diffusion in silicon at lOOO'C. the surface concentration is maintained at 111" cm
and the diffusion time is 1 hour. Find Q(t and the gradient ) at x = 0 and at a location when- the = -- = -3.5x10" cm-
1 s nlh
dopant concentration reaches lO" cm .
SOLUTION Tbfl diffusion Coeffidenl of bonm at 1000°C. as obtained from Figure 6.4, is about
2 X 10" cmVs. so the diffusion length is
dC C. -10"
-r±r = -r = -6.7 x 10" cm" JC(.U) = S U3a)
dx \nDr V^x8.48xl0*
.
This expression Is the Gaussian distribution. Since the dopant will move into the semi- x^jRi-b'-jRl-a* (17)
conductor as time increases, in order to keep the total dopant S constant, the surface where a and b are indicated in the figure. In addition, if fl,, is much larger than a and
concentration must decrease This is indeed the case, since the surface concentration is
then
go en b) Bq. 14
with j>0:
: :
a -h
The junction depth x jt as illustrated in Figure 6 6o. is the position where the dopant
Figure 6.5/> sIkavs the dopant profile foraUmssian distrihulion in which the normalized concentration equals the substrate concentration C„. or
concentration (C/S) is plotted as a function of the distance for three increasing diffusion
Note the reduction of the surface concentration as the diffusion time increases. C(x,) = C„ (19)
lengths
The gradient of the diffusion profile is obtained by differentiating Eq 14 and is Thus, if the junction depth and CH are known, the surface concentration C and the impu-
rity distribution can be calculated, provided the diffusion profile follows one or the other
dxl.j 2v//r(D/f-
"
VT-~C(
2Di
X J) (16) simple equation derived in Section 6.1.2.
sion length VDf for the predeposition diffusion is much smaller than the diffusion length
for the drive-in diffusion. Therefore, the predeposition profile can be considered a delta where CF is known as the correction factor. The correction factor depends on the ratio
function the surface, and the extent of the penetration of the predeposition profile can
at of d/s. where 8 is the prolx- spacing. When d/s > 20. the correction lac tor approaches 4 54.
be regarded to be negligibly small compared with that of the final profile that results from
the drive-in step
EXAMPLE 2
Arsenic was pit-deposited by arsine gas. and the resulting total amount of dopant per unit area was
1 X 10" atoms /cm*. How long would it take to dnvr the arsenic in to a junction depth of 1 Jim?
B
tanne background doping of C„ = 1 x 10 atoms/cm and a drive-in temperature of 1200°C
1
,
SOLUTION
° ,wnt
>"Y,
<
7 c,
-
' s u "' "" r
;
semicondactoi SS2
1
difTusn.K
fusion profiles
among
;
are
,
, omesconcen,ra.
dependent.' 'In the extrinsic dub,
more complicated, and
the sequential or simultaneous
.here are mterac.ions and
diffusions,
cooped
'
^£ .
simple diffusion
Cv =C,exp{^)
fusion profile. Design curves relating C, and p have been calculated for (23)
profiles, such as the eric or Gaussian distribution." To use these curves correct 1)-. we must
where C, is the intrinsic vacancy density. /J, is the Fermi level, and E
Ix- sure that the diffusion profiles agree with the assumed profiles. For low concentra- is the intrinsic Fermi
level.
tionand deep diffusions, the diffusion profiles generally can be represented by the afore-
'i the dopant diffusion is dominated by the vacancy mechanism, the diffusion COef-
mentioned simple (unctions. However, as discussed in the next section, for
fideir is expected to lie proportional to the vacancy density. At low doping concent rat ...us
concentration and shallow diffusions, the diffusion profiles cannot be represented by'
simple functions.
Hie diffusion profile can In- measured using a capacit;uicc -\ oltage technique. The major-
100
ity carder profile (n >, which is equal to the impurity profile if impurities are fully ionized,
can be determined by measuring the reverse-bias capacitance of a p-u junction or a
barrier diode as B function of the applied voltage. This is due to the relationship'
-1
:
d(\ C' ) d\'
capacitance per unit area of the sample, and V is the applied voltage.
A more elaborate method is the secondary ion mass spectroscopic (SIMS)
which measures the total impurity profile. In the SIMS technique, an ion beam
material off the surface of a semiconductor, and the ion component is detected and mass
analyzed. This technique has high sensitivity to many elements, such as boron and
and is an ideal tool for providing the precision needed for profile measurements
concentration or shallow -junction chffusions. 10
files occur when the doping concentration Is lower than the intrinsic carrier conce and extrinsic diffusion
-
-I Diffusion in Silicon
where C, is the surface concent nition, D is the dillusion coefficient at the surface, and 1 < ™'« ri " i
"" - abrupt, as dep
t
I
a .,,,,
He diffusion ol
platmum
pn.hles have the concave shape show,,
phosphorus
cliffusion in silicon, /is
in silicon
i„ curve d
Cose
ol
U
Figure 6 9
] „„.„. ,,,„.
Figure 6.9 shows the solutions' for constant surface concent ration diffusion with dif- ,s associated w,lh the doubh charged accep-
tor i acancy andthe diffusion coefficient at high
ferent v alues of y For y = 0. we have the ease of constant diffusivity, and the profile is \
_
.
concentrator^ as tf We wouH
the same as that shown in Figure 6.5fl. For y> 0. the diffusi\it\ decreases .is the con-
centration decreases, ami increasingly steep and boxlike concentration profiles result for
• Igun- 6.9. ™J I
,l,l,,, si,,
» P"» ni< ' " r Pl-phorus resembles that shown
1
lowcver. because of a <l,ssociatio„ effect,
the diffusion profile exhibits
in erne 6 of
lous l>ehavior.
IncreesJng y There-fore, highly abrupt junctions are formed when diffusions are made
Figure 6.10 shows phosphorus diffusion profiles
into a background of an opposite impurity type. The abruptness of the doping profile for various surface concentrations
after diffusion into silicon for hour at lOOTC." When the surface con
results in a junction depth virtually independent of the background concentration. Note 1
entrarJoo U low
corn spun, ling to the intrinsic diffusion region, the diffusion profile
that the junction depth (see Fig. 6.91 is given by is given In an eric
Ccurve As the concentration Increases, the profile begins to
a).
deviate from the simple
expression (curves b and r). At very high concentration (cum-
d), the profile near the
surface is indeed Similar to that shown in curvet
of Figure 6.9. However, at con., „(,.,-
Hon n, a kink occurs and is followed by a rapid diffusion in the tail region.
1.0 The concern
08 jratoon n corresponds to a Fermi level 0.1 1 eV tie conduction band. At this enem Wow
06 (d) level,the coupled impurity -vacancy pair (/"V 2 ") dissociates to /' V
ami an electron .
D-V 1
Thus, the dissociation generates a large number of singly charged
acceptor vacancies V .
04 winch in turn enhances the diffusion in the tail region of the profile The
diffusivity in
the tail region is over 10" 12 cm'Vs. which is about two orders
of magnitude largei than the
intrinsic diffusivity at 1000°C. because of its high diffusivity. phosphorus
is monl) ,
0.04 (b) because both p- and n-type impurities must ultimately reside in lattice sites However
O-r 1
D - (
the charge states of the vacancies have not been established.
y Zinc is the most extensively Studied difrusanl In gallium arsenide. Its diffusion coef-
0O2 ficient isfound to vary as C : Therefore, the diffusion profiles are steep. as shown in Figure
6.11, and resemble curve/; of Figure 6.9. Note that even for the case ol the lowest sur-
face concent nition. the dillusion is in the extrinsic diffusion region, because PI tor ( ia \s
\ than l0W Cm
001 j i I l I
1(KM)°C
' 1 l 1 l l I
at is less As seen til Figure 6. 1 1, the surface concentration has
0 04 08 1.2 1.6 2.0 2.4 2A 3.2 3.6 4.0
profound effect on the junction depth. The diffusivity varies linearly with the partial pres-
sure of the zinc vapor, and the surfacv concentration is proportional to the square root
Figure 6.9 Normalized diffusion profiles for extrinsic diffusion where the diffusion of the partial pressure. Therefore, rom Eq. 2-5. the junction depth linearly propor-
f is
l*i in - s conceiitratkm dependent. ' 1
<
tional to the surface concentration
US » Ch»pttr 6 Drftusion
6.3 Lateral Diffusion «• 1 19
Figure 6.11 I HffuskH profile*" of zinc in GaAs after annealing at 1000 e C for 2.7 hours.
The
dill. «. surface concentrations are obtained by maintaining the
.;!
Zn souk .-at temiM-MtunMhl
the range 600°C to 800°C.
penetration In the vertical direction for concentrations three or more orders of magni-
tude Mow the surface concentration. Similar results are obtained for a constant
total
LP dopant diffusion condition. The ratio of lateral to vertical penetration is about 7")%. For
Dcptil (um) concentration-dependent diflusivitics. the ratio is found to be reduced slightly to alwut
65% to 70%.
Figure 6.10 Phosphorus diffusion profiles 1
for various surface concentration-, ifter diffusion
into silicon for i hour at 1000°C.
Diffusion mask
Figure 6. 12 shows the contours of constant doping concentration for a constant sur-
face concentration diffusion condition, assuming that the diffusi\ity is independent of
centration.'* At the far right of the figure, the variation of the dopant concentration
0.5 C, to 10~* C, (where C, is the surface concentration) corresponds to the erfc
bution given by Eq. 9. The contours are in effect a map of the location of die jui
created by diffusing into various background concentrations. For example, at C/C,
m the background doping is 10' times lower than the surface concentration), we see -20 -1.0 0 1.0
.
from y/2VD7
this constant concentration curve that the vertical penetration is alwut 2.8 um.
whereas the lateral penetration is about 2.3 um (i.e.. the penetration along the diffusion Figure 6.12 Diffusion contours at the edge of an oxide window, where r die radius of
"
mask-semiconductor interface). Therefore, the lateral penetration is about 80% of curvature."
120 »• 0«pt»r6 Obtusion
Summary
6.5 «•
121
Note thai surface concentration of die boron is set to ll..- solid solubility
limit l»v the Solidsol
6.4 DIFFUSION SIMULATION parameter hi the DIFFUSION command After predeposition is
complete, «, print an.l plot the
OWJeOtrattOU as function ot depth into the silicon substrate The results
are shown in rVuit
The various complications that arise la the computation of diflusion profik s such as con-
fi H !iKlMn lieatesaj.incti( |,.l« ptl,of().0r>r>5u.n.
ham
l )
M
a tntntka>dependenl difiustvit) tend to preclude the use of analytical r^culatioos
t..r .til bul the simplest evuuples. Fortunately, the SUPREM software p.ieka ;e introduced
inChaotei 3 aba includes complete models for diffusion. SUPREM can simulate one- or
two-dimensional diffusion profiles, this is accomplished using the diffusion command. 6.5 SUMMARY
The output of the program b typical]) the chemical, earner, and vacan entrationl
as functions of depth into the semiconductor substrate. Diffusion is a key method of impurity- doping. This chapter first considered the basic dif-
All diffusion process simulators. Including SUPREM. are based upon three basic equa- fusion equation for constant diffusivity. The complementary error function (erfc)and the
tions.
1 '
The first equation is Ibr the Qui which bl one dimension is given by (. e s;.,n function were obtained for the constant surface concentration case and con-
The results of a diffusion process can be evaluated
stant total dopant cases, respectively.
(26) by measurements of the junction depth, the sheet resistance, and the dopant profile.
ax
when- X is tin- charge stat.-. jti is the mobility of the Impurity, and E is the electric field.
The subscript i indicates the SUPREM grid location. The second relationship is the con-
tinuity equation, which is given by
where (.* is the ^neration/recoiubination rate of the impurity. The final key relationship
is Poi.sson's equation which in one dimension is given by
(28)
where E is tile permittivity, and p are the electron and hole concentrations, and Sd
;i
and .\\ are the concentrations of ionized donors and acceptors, respectively. SUPREM
solves Eos. 26 to 2-S simultaneously over a one-dimensional grid specified by the user.
The dilTus.MtN values used b\ SUPREM are based on the vacancy model of Fair." The
fames of f, and D„ for B. Sb. and As are included in a look-up table. Empirical models
are used to account for field-aided, oxidation-enhanced,
and oxidation-retarded diffusion.
EXAMPLE 3
• we want to simulate the predeposition ofbOTOTl into an n-tvpe <100> wafer at S50*C
silicon
to
*
detennine the
-mIii^ii substrate i% (l.)jx-il«iaipj,«»p»,„nis at a'lesrl of 10'W use SUPREM
horn doping profile and the Junctioa depth
silicon substrate, using
Figure 6.13 Plot of boron concentration as a function of depth into the
SOLUTION The SUPREM Input fating b as follows: SUPREM.
122 >• Chapter 6. Diffusion
Problems + 123
When higher than the intrinsic c arrier concentration n, at
the doping concentration is
[fusion temperature-, the diffusMty becomes concentration dependent. This depen- .. .i. HusMtj d . 23 > 10 c m, fs IVe measured surface concenta
n is I H 10
ilc-ucv h is profound effed on tin- resulting doping profile-. For example, arsenic and
.1
boron difiusivity in silicon vary linearly with the impurity concentration. Their doping X 10 ( Jgleulate the diffusion time and the
1
MaJ dopant in the diffused laser.
profiles pre much more abrupt than the eric profile. Phosphorus difliisivity in silicon varies
•4. To avoid wafer warp due to
..n
phosphorus
the square of concentration. This
ilitliiMvitv th.it is 1(K)
dependence and
times larger than its
,t dissociation effect give rise to a
intrinsic difiusivity
rion
trve diffusion
We is
time
sudden reduction in temperature, the
.,
I. S. M. Sw. Ed.. VLSI Technology. 2nd Ed . McGraw-Hill. New York. 1988. Ch. 7. 8.
2.SK Chamlhi. VIJl FalmcatUm Principles. 2nd Ed.. Wiley. Now York. 1994. Ch. 4. fi. SI < l iON 6.2: EXTRINSIC DIFFUSION
3. \V. R. Runyan and K. E. Bean. Semiconductor Integrated Circuit Processing Technology. Addison-Wesley. 7. I
!"
arvnk-
diffused into a thick slice of silicon doped with 10"
is
boron atoms/cm' at a
Boston. 1990. Ch. 8. '
mperature ofOOO*C for 3 hours, what is the foal distribution of arsenic
if the surface
ls
Ci Casey and C. L Pearson. "DilTusion in Semiconductors."
4. II. in
J.
H. Crawford and L. M Slifldn. Eds.. concentration is held fixed at 4 x 10 atoms/cm ? What is the junction
depth? Assume
Pomt Dr/Kfcui Solids. Vol. 2. Plenum. New York. I975. the following:
5 J
P Job. "Metallic Contamination of Silicon Wafers." Microelectron Eng 40. 285
. (1998).
D„ = 45.8 cmVs E. = 4.05 eV x, = l&VBt
6. A. S. Crow, Physics and Techtiology of Semiconductor Devices. Wiley. New York. 1967.
8. Explain the meaning of intrinsic diffusion and extrinsic diffusion.
7. ASTNt Method F374-88, "fell Method for Sheet Resistance of Silicon Epitaxial. Diffused, and Ion-
Implanted Layers Using a Collinear Four- Probe Array." VIO. 249 (1993).
SECTION 6.4: DIFFUSION SIMULATION
8.
J.
C. Irvin. "Evaluation of Diffused Layers in Silicon." Bell Syst. Tech. J..
41, 2 ( 1962).
9. Use SUPREM to perform a drive-in step for 6 hours at 1175*C following the predeposi-
9. S. M. Sat, Semiconductor Devices Physics and Technology. 2nd Ed.. Wiley. New York. 2002. Ch. 7.
OOO described Example
in 3. Plot the boron profile and give the now junction depth
10. ASTM Method E1438-9I. "Standard Cuide for Measuring Wiilth of Interfaces u. Sputter Depth
*10. Aftei the boron drive-in step in Problem 9. suppose phosphorus is subsequently prede?
Profiling Using SIMS." VIO. 578 (1993).
posited and driven in. The phosphorus prcdeposition occurs at S50'C for 30 minutes. ..ml
II R. B. Fair. "Concentration Profiles of Diffused Dopants." in F. F. Y. Wang. Ed.. Impurity Doping the drive-in occurs at 1000"C for 30 minutes. Use SUPREM to plot the phosphorus and
Pixicessrs in Silicoti. North-Holland. Amsterdam, 1981.
boron impurity profiles, and determine the junction depth(s).
12. L. R Wtilber0 and J.
Blanc. "Diffusion with Interstitial-Substitutional Equilibrium. Zinc in GaAs."
Pitys. ftm, 131. 1548(1963).
13. F A Gunnel] ami C. ft Cooch. "Diffusion of Zinc in Gallium Arsenide."/ Phys Chem Solid. 15. 127
(1960).
14. D P Kennedy and R. R O'Brien. "Analysis of the Impurity Atom Distribution Near the Diffusion Mask
for a Planar p-n Junction." IBM J firs Dev . 9, 179 (1965).
15. S. A. Campbell. The Science and Engineering of Microelectronic Fabrication. 2nd Ed.. Oxford University
Press. New York. 2001. Ch. 3.
: PROBLEMS
Asterisks denote difficult problems.
™
2. II the sample in Problem 1 is subjected to a neutral drive-in at 1050°C for 60 mini
calculate the diffusion profile and the junction depth.
h
Ion Implantation
bntmns with average depths ranging
onvcm
-dating
from 10
f„ r d.resholcl voltage
layers. Note „ lat L
ad
dose •
to
o,
"
ss^l
^^ ^
^ &^"23 *
7 '°"
""^
7 '" '""
,llS,n -
^ «>
U
*' S ""'"
1 c-m of th- semiconductor surf,,
, T ? ''"P 1 1
oMBE gS * * ^ ^ ^
, ,
a,J;:;;^ »*.
As discussed in Chapter and Ion implantation are the two key methods of
6. diffusion
impuritv doping Since the earl) L9705, mans doping operations have been performed
As- An fflrtraction voltai, ( . lroumI ^ 1
" Ul
'
""«>^-g,-d ,o„s -iv or
In ion implantation, as shown in Figure 7. 1. In this process the dopant ions are implanted
into tbfl Semiconductor In means of an ion lu-ain. The doping concentration has a peak
io
0
s
-
pa to
1,tam is vt' n c
tl:r
minimis* on
as they move from high
ma,ed
;
voltage to ground Apertures
scattering f
by gas molecules. v* ~ &*tt\2S
The
in
ion beam is then scanned over
• The process and advantages of ion implantation
t^*S£" electros,alic ddWlion
pto n*« S IS
•
•
[on distributions in the crystal lattice
by ion implantation
and how to remove
"
"
subsv rate
sub.
'
'
,,
and
T'-i-"
n
,K i0nS ,0SC
finally come
^
to rest at
throU h
g
some depth within the
electrons and nuclei in the
lattice. The aver. depth
high-eu rren t i 11 plan t ation h) mo„ tonng
1
the ton current during implantation.
The principle side effect is disrup-
• The simulation of ion implantation using Sl'PKF.M ts o
,au,age of tl,e semiconductor lattice due to ion
collisions. Therefore a sul
ment
annealing treatment is needed to remove this 1
damage.
Ca.«of
dorunt Mklll 7.1.1 Ion Distribution
l80KN
l 'rT1 Equfcrnew \,. nlr.j bean Crsp
Beam ir.iji and Ventral
gate plate »nd beam
path gated
>--«is" \\'.,f,. f ui
scanner w^,. r pnxrs*
(b) chamber
V«raunt
Ion br-un
t ftp
r
J
f 2)
Figure 7.36 shows the ion distribution. Along the axis of incidence, the imj
2 -
p +Mtfx
(4)
*(,) = cxp
where S the ion dose per unit area. This equation is similar to Eq. 14 in Chapter 6
is
' '
t, ,i 1
i< "Concentration is reduced In l<r; from its p.-ak \alueat o -11
±o r .
by one decade at ±2op by two decades at ±3op and by five decades ±4.8c
. , at .
p
.\longtheaxisperrxii(licu] lt rtotheaxisofincidencf. the
distribution is also a Gaussian
function Oi the form exp -yVtol). Because of this
distribution, there will l>e some lat-
eral implantation.' However, the lateral
penetration from the mask edge (on the order
considerably smaller than that from the thermal
diffusion process discussed
Section 6.3.
Figure 7.4 ( .'ollision of hard spheres.
£
IM - Chapter 7 Ion Implantation
W Range of Implanted Ions •« 129
M same order of magnitude as A/,, a large amount of energy
Since b USlttBy of the
am be transferred in u nuelear stopping process.
Detailed calculations show that the nuclear stopping power increases linearly with
i-i»^:^::^r^^^-a
^ww»i^ZSB
energv at low energies (similar to Eq. 4). and S„(E) reaches a maximum at some inter- , i r „,„K„
medute energv At high energies. S,(E) beeomes smaller because fast particles may not
have sufficient interaction time with the target atoms to achieve effective energy tran S .
Hm calculated values of S„(E) for arsenic, phosphorus, and boron in silicon at
i
*
w here the superscript Indicates die
Rr
ous merges are shown in Figure 7.5 (solid lines,
l+(A/,/3M,) (6 >
weight Note th.it heavier atoms, such as arsenic, have a larger nuclear stopping
tliat is, larger energy loss per unit distance.
Hie electronic stopping power is found to l>e proportional to the v elocity of the
The value otk is approximately 10" (eV) /cm for silicon and 3 x 10' (cV) */cm for projected range and s.ragg.es
1
1
incr-aJ" wi
.ncrgv F„r gwen element at a specific incident energy.
a
I
limn arsenide. The electronic stopping power in silicon is plotted in Figure 7.5 (dotted O and a are con,,,,,
line Also shown in the figure are the crossover energies, at which S.(E) = S,\E). For
- -.ally v.thm ± 0', Figure 7 6,, shows the
.
corresponding vines fo.
fiteTZ
,
E
i.
boron, which has a relatively low ion mass compared with the target silicon atom, the compare Figures
crossover energv
range of 1 keV to
is
1
only 10 keY. This means that over most of the implantation energy
MeV the main energy loss mechanism is due to electronic stopping. JJatfSM *
On the other hand, for arsenic, with its relatively high ion mass, the crossover energy is
7(H) keV. Thus, nuc lear stopping dominates over most of die energy range For phosphorus.
l.VXl
-'-Si-
Nuclear
Bfectronlc
I (XX)
I
i
706 keV
EXAMPLE 1
\ Ion .< A 'lwit.ui implants mi .i 2lHi-min silicon water .it a dose nl "> x III 'loiivtiir C Jcntatf
the peak concentration .mil tin- rt'«|iiirx>cl ion Ihmiii current for 1 minute of implantation.
SOLUTION Prom Figure 7 6a vn obtain 0 31 and 0.07 urn foj tin- projected range and projected
straggle n speitiwlv
From Kij I
n(x).
2na 2a\
Jn S 2lx-R
0\p =0
2a: 2a„
,k ,:
10
— = 4.19x10
1 1
1.6x10
= tqQ = —x 1.57x10"
I
.
l
y A = 0.42mA 0 0.2 0.4
Depth liitn)
0.6 0.8
Figure 7.7 Impurity profile obtained m a purpose!} inisoriented targel Ion bean is Inddenl 7
from me < 1> axis *
1 1
ductors, provided the ion In-am is inisoriented from the low-index ervstallographic direction nels Pig 7.9bW ith this method, most implantation machines tilt the wafei l>\ 7 and
(e.g.. clll>) In this situation, then apply a 22 twist from the Hat to prevent channeling. I're-damaging the wafer surface
:
tion Ions implanted i„ the < 1 10> direction will follow trajectories that will not bring then, of nuclear and electronic collisions and finally come to rest. The electronic energ) loss
don enough to a target atom to lose significant amounts
of energy in nuclear collisions, can lx- accounted foi in terms of elec tronic excitations to higher energy levels or m terms
rims, for channeled ions, the only energs loss mechanism
is electronic stopping, and the of the generation of electron-hole lowever, electronic collisions do not displace semi
pairs. I
m.pl.mls and heaV) ions. energy to the atoms are displaced, resulting in implant damage (also
lattice so that host
Channeling can be minimized
In several techniques: a blocking amorphous surface Called lattice disorder). These displaced atoms nja) possess large fractions ol the incident
Uer misorientation ol the w.der, and creation a
damaged layer in the wafer surface. The energx, and they in turn cms.- cascades of secondary displacements ol nearb) atoms to
•sua bloc king amorphous lavcr is s.mpK .,
t| llu ilVl r u f grown si | jf ,,„ dioxide (Fig. 7.9fl). |
.
form a tree of disorder along the ion path. When the displaced atoms per unit \olutne
The layer randomizes tl.e direction of the ion beam so that approach the atomic densjt) of the semiconductor, the material becomes amorphous
the ions enter the wafer at
132 * Chapter 7. Ion Implantation
7.2 Implant Damage and Annealing h 133
HUJ HI U 1UU
c
displaced Le., 1500 A/2.5 A). If each displaced atom moves roughly 25 A from its orig-
inal position,
1
oooooooo oooooooo Crystal For heavy ions, die energy loss is primarily due to nuclear collisions: therefore, we expect
OOOOOOOO
Crystal
oooooooo ,
sul istantial damage. Consider a 100-keV arsenic ion with a projected range of 0.06
Jim, or
Crystal
b<> mn. The average nuc lear energy loss oxer the entire energy range is about 13211 eWmn
(.) (b) (c) 1 :g 7.5). This means that the arsenic ion loses about 330 eV for each lattice plane on the
average. Most of the energy is given to one primary silicon atom Each primary atom will
Figure 7.9 Minimizing channeling. <o) Implantation through an amorphous oxide layer.
subsequently cause 22 displaced target atoms (i.e.. 330 eV/15 eV). The total number of dis-
(b) MLsorientation of the beam direction to all crystal axes, (c) Pre-damage on
the crystal surface.
placed atoms is 52S0. Assuming a range of 2 5 11111 lor the displaced atoms, the damage vol-
:s
ume is V0 B M2JS nm) 1 (60 mn) = 10 cm'. The damage density is then 52-S0 V,
r
>
•
The tree of disorder for light ions is quite different from that for heavy ions. Much of 1" cm . or about KKJ of the total number of atoms in V„ As a result of the beavy-ion
the energy loss for light ions (e.g.. "B* in silicon) is due to electronic collisions (see Fig. 7.5), implantation, the material becomes essentially amorphous. Figure 7. H)/; illustrates the sit-
winch do not cause lattice damage. The ions lose their energies as the)- penetrate deeper uation in which the damage forms a disordered cluster over the entire projected range
into the substrate. Eventually, the ion energy is reduced below the crossover
energy (10 To estimate the dose required to convert a crystalline material to an amorphous form,
kcV for boron) nuclear stopping becomes dominant. Therefore, most of the
where lat- we can use the criterion that the cnergx density is of the same order of magnitude as
3 :I
This illustrated in Figure 7.10a. that needed for melting the material (Le., 1<> teV/cm ). For 100-keV arsenic ions, the
tice disorder occurs near the final ion position. is
100-keV boron ion. Its projected range dose required to make amorphous silicon is then
We can estimate the damage by considering a
and nuclear energy loss is only 3 eV/A (Fig. 7.5). Since the
is 0.31 Jim (Fig. 6o). its initial ;|
(10 keY'/cm')/?. r
means that the boron ion '—L = 6x10'
sparing between lattice planes in silicon is about 2.5 A. this
S= ± ions/cm- (8)
The energy required
wil] lose 7.5 eV at each lattice plane because of nuclear stopping.
,
7.2 Implant Damage and Annealing < 135
134 Chapter 7 ,on Implantation
because for boron implanted ions are activated by a 30-minute anneahng in a conventional annealing
dose required is 3 x 10« tojterf J
nis fur-
For 100-keV bomn ions, the nace For boron implantation, higher annealing temperatures are needed for
arsenic. . 1, .wev er. in
practice, higher doses (> 10 ,ons/cnr) are
ire bigger doses.
es u*-r than for
fi « For phosphorus at lower doses, the annealing behavior is rimfiai to that for boron. I iowever
when the dose is greater than 10' cm the annealing temperature drops to about 600 S C.
.
cessing times vising RTA. trade-offs must be made in temperature and process unifor-
1000
ms temperature measurement and control, and wafer stress and diroughput. In addition,
there are concerns about the introduction of electrically active wafer defects during
the
l = 30 mill
t
T.-25'C
Reflector I .amps
Boron^/ f s
/ \
E
1
\
X^Qudrtz window ^\
t.ni
n
TV"
000
i
-
VX) 1
optically heated
Rapid thermal annealing system that is
*
Figure 7.12
Figure 7.1 1 Annealing temperature versus dose for 90* activation of boron and phosphorus
136 - Owpttf? lonlmplsntat.on
TABU
TABLf M
7.1 Technology
IILIII
Comparison
|| •«»
Conventional Furnace Rapid Thermal Annealtog
Drlrnniiunt
Single-wafer
Batch
(old-wall
Hot -wall
Fumacr
Low High
Heating rate
l.'\clr tunc OA
HO
*
LOW
Furnace
Wafer
Temperature BJCBMOf
LOW
.
Tnt-nrul
i i v ..,i
....
OaagK w$A
Minimal
Yes
Particle faction
1 X l\V
l iufoni.lt> and repeaUhility
Low
In manv doping profiles other than the simple Gaussian distribution are
applications,
is the preimplantation of silk-on
One such case with an men .on to make the
required.
allows close control of tl ie doping pro-
silicon surface region amorphous. This technique
low temperatures, as liiscussed previ-
fde and permits m ark HM)% dopant activation at
ouslv. In such a case, a deep amorphous region may be required. To obtain this type of
region, we must make a series of implants at varying ion energies and closes.
7 V Hen-,
I four boron implants into silicon are used to provide a composite doping pro-
process, a large variety of the masking materiaLs can be used. The minimum thickness
of the masking material required to stop a given percentage of incident ions can be
esti-
profile of
mated the ram.- parameters for ions. The inset of Figure 7.14 shows a
fan
an implant in a ma>kiu<: material. The dost- implanted in the region beyond a depth a
(shown shaded) is given by integration of Eq. 1 as
138 Chapter 7 Ion Implantation .3 Implantation-Related Processes < 139
fiOkcVAc Si
(9)
= ^erfc(.r) (10)
Once t is given, we can obtain the mask thickness c7 from Eq. 1 1 for any given R p and a .
p
Tin- \alues of d to stop 99.99% of the incident ions (T =
\0~*) are shown in Figure
7.14 for SiO . Si N,. and photoresist as masking materials.' Mask thicknesses given in
this figure are for boron, phosphorus, and arsenic implanted into silicon. These mask thick-
Depth (nm)
n esses also can I*- imiI .is guidelines for impurity masking in
gallium arsenide. The dopants
are shown m the [\irentheses, Since both H and O. vary appradmateh/lmeariy with energy,
Figure 7.15 60-keV arsenic implanted into silicon as ,i function of beam tilt angjta Inset shows
the shadow area for tilt-angle ion implantation.
the minimum thickness of the masking material also increases linearis with energy. In
ators that can provide an amorphous surface layer to the incident ion beam to minimize
Consider the shadow effect (inset in Fig. 7.15) for the patterned water. A lower tilt angle
the channeling effect.
leads to a small shadow area. For example, if the height of the patterned mask is 0.5 uan
with vertical sidewall, a 7° incident ion beam will induce a 61-nm shadow. This shadow
EXAMPLE 2
effec t may introduce an unexpected series resistance in the device.
When boron ions are implanted at 200 keY what thickness of SiO. will lx- required to mask 99.996S
long diffusion times at high temperatures. High-energy implantors can also be used to
produc e low-resistivity buried layers. For example a buried layer 1.5 to 3 pm below the
where the parameter u is given by (rf - fy/V2o. For T = 10~\ we solve the above equation to
surface for a CMOS device can be achieved by high-energy implantation.
range, are rou-
obtain u = 2.8. Tims. High-current implantors (10-20 mA), operating in the 25- to 30-keV
tinely used forthepiedepositionstepin diffusion technology because the
amountol total
</ = *.+ 3.960-,, = 0.53 + 3.96 x 0.093 = 0.898 fim « be driven
dopant c an be ex. nt rolled precisely. After predepositiou. the dopant impurities can
in b) a high-temperature diffusion step at the same time that implant damage a! the sui
-
ing dopant activation and subsequent processing steps. Modem device structures, such in silicon and silkx.n oxide arc- comparable, if
we choose a suitable incident eiu-ruy. the
thicker Held oxide The thresboldvolt-
U the lightly doped drain LDD MOSFET. require precise control of dopant distribu- ions w ill penetrate just the thin gate ox.de. not the
with the implanted dose. After ^^plantetton,
tions vertically and laterally. age will vary approriniatel) linearly
form the gate elec trode o! the MOSFE I
It Ls the Eon velocity perpendicular to the surface that determines the projected range polvsilicon can be deposited and patterned to
of an implanted ion distribution. If the wafer is tilted at a large angle to the ion beam, TtetbJncwdeainouiio^to^
arsenic- tmplantahon.
then the effective ion energy is greatly reduced. Figure 7.15 illustrates thus for 60-keV are formed, as Figure 7.1*. In another high-dose
shown in
150- to200-kej range
arsenic ions as a function of the tilt angle, showing that it is possible to achieve extremely High-current implantors with energies in the
form high-quahty sd.con hlms. winch are
able. A major use for these machines
is to
shallow distributions using a high tilt angle (86°). In tilt-angle ion implantation, we should
140 > Chapter 7. Ion Implantation
7.5 Summary * 141
PoK-silicon Ait.
Acttkntod borop ions t
the rinraJatfon is ooomtae wt nrint tnd ni„» a. u.
arc
" "'
1
"~" r
' which todkatai
of 0.4454 urn •
fraction depth
I I I J I
Gair txadr
7.5 SUMMARY
Ion i.uplantation is a key method for nupurity doping The kevoarnn,.,^ ft
f'>r .on unplan-
i
tatiou are the projected ranee .« ' '
Thick oxide
I and it, „, I 1 .
p-txpr«tli«*/
(«) < b)
•
7.4 ION IMPLANTATION SIMULATION
Sl'PRKM mav be used to simulate ion implantation profiles. Simulated profiles can be
implanted and activated using the IMPLANT command, and subsequently driven in using
Boron (/c«3)
the DIFFUSION command. SUPREM contains the implant parameters lor most common Phosphorus (/cm3)
dopants, but also allows the user to input range and straggle data for unusual implanted Het Doping (/cra3)
materials. SL'PREM can also simulate implants through multiple layers.
EXAMPLE 3
R-typfl cl00> silicon wafer The implant is then followed by a drive-in at 950°C for 60 minutes I
Ion Implantation
142 Chapttf 7 Problems < U3
materials Ami thickness to stop a given
percentage of incident ions *rx>in reaching the sub- 7. Estimate the implant dose recp.fred to reduce
a ,,cha„nel threshold wolup
b] V
gate oMde b4 nm
^ ,h.'
I
\Z \*™
1 '"
u. Silicon In
I k A Pidur. "Ion linpLuitatx.n
10. With referencv to Example 2. what thickness of SiO, required to mask 99.999* of the
Prew. New York. 1975 is
implanted ions?
6 U Pauling and R Havward. Iftr ArWimrrurr of Molecules. Freeman. San Francisco. 1964
implanted with boron The implant energy is 30 ke\' with a close of 10° cm"1 Use .
9 D H I and J
W Mayer, -lon lnipJanted Semiconductor Desiees." Proc IEEE. 62. 1241 1 1974).
SI PREM to plot the boron profile \Mni1 «l. pth .,f tl„ speak ol the in, planted
10. C. Deamaley. et at , Ion Implantation. North-Holland. Amsterdam. 1973 profile, (b) the boron concentration at the peak depth, and (c) the junction depth?
I I W C Ol.lham. Ha» Fabrication of Microelectronic Circuit." in Mtcroelectnmky Freeman, San "12. I >e SUPREM to design m Implantation step that gives the same doping profile as the
FrancMcn. 1977 diffusion Example 3 in Chapter 6.
PROBLEMS
.Artrrufcs denote difficult problems.
2. A silicon p-n junction is formed by implanting boron ions at SO keV through a window
:
an oxide. If the boron dose is 2x io'"
1
3. A threshold voltage adjustment implantation is made through a 25-nm gate oxide. The
substrate <100> -oriented p-type silicon with a resistivity of 10 Q-cin It the incremen-
is a
tal threshold \oltage due to a 40-keV boron implantation Ls 1 V. what is the total
implanted dose per unit area 2 Estimate the location of the peak boron concentration.
M. For die substrate in Problem 3. what percentage of the total dose is in the silicon?
15 eV the range is 25 nm. and the spacing between silicon lattice planes is 0.25 nm.
"
6. Explain why high -temperature RTA is preferable to low-temperature RTA for defect
shallow-junction formation.
81 Eprtax,al Growth Techniques « 145
8 ,1.1
30% to 50%
sition
The common techniques for emtaxi.d
lower.
«2VD) and moLadarln-am q>ilaxi/ i.MHE).
( , n ^ , J.
tors
«, ,
^J
We ran classil\ thin films into five groups, thermal oxides. d.e!e< trie lasers, epi-
films the „...
fo he^eh.u.iMnoK.-Vn.nu.K,,,, ,,, ,„ „„.„.„
|wlu rystalline silicon, and metal films. The growth of thermal oxides was sl ,, )v ,
reaction chamber.
conductor substrate. The word epiitoxy is derived from the Greek words <•/>/ fj
"on") and taxis (meaning "arrangement"). The epitaxial layer and the substrata CVD for Silicon
.ils mav be the same, giving rise to homoejntaxy. For
example, an n-type silicon can be
ources have been used for VPE growth The) are siBoon tetrachloride Sid
grown epitaxially on an n'- silicon substrate. On the other hand, if the epitaxial layer and Slll(
)
1
:l
trichlon.silaneisilicl „„| sil.„„-
die substrate are chemically and often crystallographically different, we have hcterocpl-
... ; Sii i SiU< - n tetrai Itlorfde
has been studied the most and has the widest industrial
use. The typical reaction temperature
taxy. such as die epitaxial growth of Al,Ca,^As on CaAs.
( )lh.-r silk-on sources are used because of lower react..,,, temperatures.
'
Dielectric layers such as silicon dioxide and silicon nitride are ured for insulation
'
The
between conducting layers, for diffusion and ion implantation masks, for capping doped
films to prevent the loss of dopants, and for passivation. Polycrystalline silicon, usual!)'
•
Characteristics of these tlun films and their compatibility with integrated
processing
V
8.1 EPITAXIAL GROWTH TECHNIQUES
In an epitaxial process, the substrate wafer acts as the seed crystal. Epitaxial processes (b>
are differentiated from die melt-growth processes described in Chapter 2 in that the epi- Figure 8.1 Three common susceptors for chemical vaj*ir deposition a horizontal ft pancake,
taxial layer can be grown at a temperature substantially below and Iwm'l susceptors.
the melting point, typically (c)
146 - Chapter 8. film Opposition
silicon layers
chloride that results in the growth of
ta
(gas)
SiCl, (gas) + Si (solid) «-» 2SiCl 2 (2)
port in the vapor phase is not possible. One approach is the use of As, for the arsenic
component and gallium chloride iCaCl | for the gallium component. The overall reac-
As, + 4GaCl 1
611, -» 4GaAs 12HC1 (3)
The n tauts are introduced into a reac tor with a earriei gas e.g..
....
The gallium arsenide 1 1
'
wafers are txpicalK held within the (v)() C to Sol) C temperature range There must be
Sufficient arsenic overpressure to prevent thermal
decomposition of the- substrate and
Metalorganie CVD
VPE process based on pyrolxtic reactions. Unlike
Metalorganic CVD (MOCVD i is also a
chemical nature ol the precursor.
conventional CVD. MOCVD is distinguished b) th«-
by introducing dopants in vapor form. Diethyl Figure 8.5 shows a schematic ol an MBE system
Dunn* eritaxy the GaAs is doped or gallium arsenide and related
dopants, and silane (SiH 1 ll-V
ZnfSkj and dit-tln fcadrnhim [Cd(QH 5 ) 2 are typioalp-type
•
1
] 4 ) compounds, such as Al Ga, ,As. The system represents
,1k- ultimate i„ ffl,,, deposition
X' compounds. The hydrides
of sulfur and selenium or tetra- control, cleanlinessand in situ chemical characterization capability.
is a n-type dopant for
1 1 I
Separate elision
methvltin are also used for it-type dopants,
and chromyl chloride is used to dope- chromium ovens made of pyrolytic boron nitride are used for Ga. As.
and d)e dopants. All the effu-
layers. Since- these- compounds arc highly poisonous ovens are housed in an ultrahigh-vacuum chamber
into GaAs to form senuinsulating sion (-KT Pa). The temperature of
spontaneously inllammahle in .dr. rigorous safety precautions an- necessary in each ..ven adjusted to give the desired evaporation rat,-. The
is
and often substrate holder rotates
the MOCVD process. continuously to achieve uniform epitaxial layers (e.g.. ± 1 in doping variations % and ±0.5%
Figure S,l shows a schematic of an MOCVD
reactor.' Pypic.llv. the metalorganic in thickness variations).
hydrogen carrier gas. where it
compound is transported to the quartz reaction vessel by To grow GaAs, an overpressure of As is maintained, since- the stickmg coefficient of
of GaAs growth. The chemical reaction is induced by heat- Ga GaAs is unity, whereas thai for As is zero, unless
is mixed with AsH , in the case to there is a previously deposited
600°C to 800°C above a substrate placed on a graphite susceptor using ( la layer. For a silicon MBE system, an electron gun used to evaporate
ing the ibises to is silicon. One or
radio frequence heating A pvrohtic reaction
forms the GaAs layer The advantages of more effusion ovens are used for die dopants. Effusion ovens behave like small-area sources
using metalorganics are that they are volatile .it
moderately low temperatures and that and exhibit a cosfl emission, where 6 is the angle between the direction of the source
then are no troublesome liquid Ga or In sources in the reactor. and the normal to the substrate surface.
MBE uses an evaporation method in a vacuum system. An important parameter for
vacuum technology is the molecular impingement how many molecules
rate; that is.
8.1.2 Molecular Beam Epitaxy
impinge on a unit area of the substrate per unit time. The impingement rate (01 is a func-
MBE an epitaxial process involving the reaction of one or more thermal beams of atoms
is tion of the molecular weight, temperature, and pressure. The rate is derived in Appendix H
(-10'* Pa)/
or molecules with a crystalline surface under ultrahigh-vacuum conditions and can be expressed as*
0 = P(2nn,kT)-
m
(5)
Mass flow controllers.
EA nut
Vacuum
0 = 2.64x10*1-4=] molecules/ cm -s
(5,,)
fora«rmolecuJes(e^ir^
EXAMPLE 1
at a system pressure of 10 v
Pa, A would be 660 km.
At 300 K. the moltnnilar diameter of ovvgen is 3.64 A. ;uid the number of molecules per unit area .V
is 7.54 x I()
'
< in
J
. Find the time required to form a monolayer of oxygen at pressures of 1. lfr\ and EXAMPLE 2
10-* Pa.
Assume ;m ell-Mon oven geometry of urea A - 5 en. and a distance /. I.e.ween the top of the oven
and the gallium arsenide substrate of
SOLUTION The time required to form a monolayer (assuming 100ft sticking) is obtained from
10 cm. Calculate the MBE growth rate for the effusion ov n
ailed with gallium arsenide at 90O"C. The surface density of gaU atoi 6 x in'
1
,,„ .,,,1
the impingement rate: the average thickness of a monolayer is 2.S A
N, N,jMT
4> 2.64 xlO"/* SOLUTION On heating gallium arsenide, the volatile arsenic
vaporizes first, leaving a gallium- rich
solution, i berefore, only the pressures
marked "Gcttfch" in Figure 2.1 are of interest The 1
pres.
Therefore. sure at 900°C is 5.5x10- Pa for gallium and 11 Pa for arsenic (As.
Tlie arrival rate can be o
1 from the impingemenl rate (Eq. 5a) by multiplying it byA/xL1
f = 2.8 x lO" - 0.28 ms at 1 Pa -.
= 2.8s at 10-* Pa
Arrival rate = 2.64 xl0»(-^|-A. molecules / cm -s
= 7.7 hr at (04 Pa j
To avoid contamination of the epitaxial layer, it is of paramount importance to maintain ultrahjgh- The molecular weight (Afl is 89.72 for Ga and 74.92 x 2 for As,. Substituting values d P M and
MBE T (1173 K) into the above equation gives
vacuum conditions (-10^ Pa) for the process. ^
Arrival rate = 8.2 x 10" / cm*-* for Ga
During molecular motion, molecules will collide with one another. The average distance
traversed by all the molecules tatween successive collisions with each other is defined
= UxlO'Vcm'-sforAr
a> the menu free path. It can be derived from a simple collision theory. A molecule hav- The growth rate of gallium arsenide is governed by the arrival rate of gallium. The growth rate is
ing a diameter d and a velocity v will move a distance vdt in the time 5t. The molecule
suffers a collision with another molecule if its center is anywhere within the distance d ——
8.2x10" x2.8
3.8 A /s = 23 nm/mm , .
^ = ^(2d)
4
v& = 2
7td
2
v& (6) There are two ways to clean a surface in situ for MBE. High-temperature baking
can decompose the native oxide and remove other adsorbed species In evaporation or
3
Since there are ;i molecules/cm , thevolume associated with one molecule is on the aver- dil fusion into the wafer. Another approach is to use a low-energy ion beam of an inert
3
age Vn cm When . the volume 5V equal to Un. it must contain on the average one
is gas to sputter-clean the surface, followed by a low-temperature annealing t" reorder the
other moleCule. Thus, a collision would have occurred. Setting r = 6/ as the average time surface lattice structure.
between collisions. MBE can use a wide variety of dopants (compared with CVD and MOCYD), and
the doping profde can be exactly controlled. However, the doping process is similar to
- = TUi'vT the vapor-phase growth process: A flux of ev aporated dopant atoms arrives at a favorable
(7)
lattice site and is incorporated along the growing interface. Fine control <»l the doping
Tin- ti.e.m free path profile is achieved by adjusting the dopant flux relative to the flux ot silicon atoms foi
('/.* is then
silicon epitaxial films) or gallium atoms ifor gallium arsenide epitaxial films). It is also
X = vr=-
1 * possible to dope the epitaxial film using a low-current, low-energy ion beam to implant
2
rend nPd- the dopant (see Chapter 7).
152 • Chapter 8 Film Deposition
8.2 Structures and Defects in Epitaxial Layers < 153
Tin- Substrate temperatures for MBE
range from 400°C to 900°C. and the growth
Strafed
rates range from 0.001 to 0.3 um/min. Because of low-temperature processing and the I-tUlCv matches!
uvtr.iiiied
low growth rate. many unique doping profiles and alloy compositions not obtainable from I
con\-entional
using MBE. These
effect transistors.
\
CVD can Ik* produced in MBE. Many novel structures have been
include the supcrlattice. which
.Jternating ultrathin layers with a period less than the electron mean free path (e.g.,
GaAs/Al,Ga,_,As. with each layer 10 inn or less in thickness), and heterojunction field-
< • • < *
»>»>»
• • •
be Optimized For example, an n-type silicon layer with a relatively low doping concen- he critical layer thicknesses for two material systems are shown in Figure 8.7. 7 The
1
tration can Ik? grown epitaxial!)' on an n' silicon substrate. This structure substantially Upper CUJVe is for the strained-layer epitaxy of a Ge Si. layer on a silicon substrate, and
reduces the series resistance associated with the substrate. the lower cum- is for a Ga, ,In As layer on a GaAs substrate. For example, for Ge Si
For heteroepitaxy. the epitaxial layer and the substrate are tw< .liferent semicon- on silicon the maximum epitaxial thickness is about 70 nm. For thicker films, edge dis-
ductors, and the epitaxial layer must be grown in such a way that an idealized interfacial locations will occur.
structure is maintained. This implies that atomic bonding across the ir Vrface must be A related heteroepitaxial structure is the Strained-layer supcrlattice (SLS). A super-
continuous. There! ore. the two semiconductors must either have the same lattice spac- lattice is an one-dimensional periodic structure constituted In different mate-
artificial
ing or be able to deform to adopt a common spacing. These two cases are referred rials v. ith a period of about 10 nm. Figure 8.8 shows' an SLS iun ing two semiconductors
to as
lattice-matched epitaxy ;md strained-layer epitaxy, respectively. with different equilibrium lattice constants a, > rr. grown in a stnicture with a common
Figure S.fvj shows a lattice-matched epitaxy where the substrate and the inplane lattice constant b. where 0, > b > at For sufficiently thin layers, the lattice mis-
film have
the same An important example is the
lattice constant. epitaxial growth of Al,Ga,^As on match is accommodated bv uniform strains in the layers. Under these conditions, no mis-
a GaAs substrate where for any I between 0 and I, the lit dislocations arc- generated at the interfaces, so high-quakty crystalline materials can
lattice constant of Al.Ga,.^ dif-
fers from that of GaAs by less than 0.13%. be obtained. These- artificially structured materials can be grown by MBE. These mate-
For the latrice-mismatcin ?d case, if the epitaxial layer has a larger lattice constant rials provide a new area in Semiconductor researc h and permit new solid-state devices
and is flexible, it will be compressed in the plane of growth to conform to the substrate especially lor high-speed and photonic- applications.
spacing. Elastic forces then compel it to dilate in a direction perpendicular to the inter-
face. This type of stnicture is called strained-layer epitaxy and illustrated in Figure 8.66.'
is 8.2.2 Defects in Epitaxial Layers
On the other hand, if the epitaxial layer has a smaller lattice constant, it will be dilated
in the plane of growth and compressed in a direction Defects in epitaxial lay ers will degrade device properties. For example, defects can result
perpendicular to the interface. In
the above strained-layer epitaxy, as the strained-layer thickness increases, in reduc ed mobility or increased leakage current The delec ts in epitaxial layers can be
the total num-
ber of atoms under strain of the distorted atomic bonds grows, categorized into five groups:
mis- and at some point,
fit dislocations are nucleated to relieve the homogeneous strain energy. This tliickness is
I. Defects from the substrates. These defects may propagate from the substrate
referred to as the critical layer thickness for the system. Figure S.fi? shows defects, dislocation-free semiconductor
the case in into the epitaxial layer. To avoid these
which there are edge dislocations at the interface.'
substrates are required.
154 * Ch.pter 8. Film Deposition
8.3 Dielectric Deposition -4 153
I- «i
Sii|*-rlattkf. mismatch
accommodated fay strain
Graded layer
Figure 8.7 Experimentally determined critical layer thickness for defect-free rtrained-layer
epitaxy of Ce.St,., on Si. and Ca,.,In,As on GaAs."
strate must be thoroughly cleaned In addition, an in situ etchback maybe and integrated There are three commonly used deposition methods: atmospheric-
circuits.
5. Edge dislocations These are formed in the heteroepitaxy of two lattice- except that different gases are used at the gas inlet. In a hot-wall, reduced-pressure reac-
mismatched semiconductors. If both lattices are rigid, they will retain their tor like the one shown in Figure 8.9o. the quartz-tube is heated by a three-zone furna e,
fundamental lattice spacings. and the interface will contain rows of mis- and gas is introduced at one end and pumped out at the Opposite end The seniiconductot
bonded atoms described as misfit or edge dislocations. The edge dislocations wafers ,,re held vertical!) in a slotted quartz boat.* The quartz-tube wall is hot focaUM
the horizontal epi-
can also form in a strained layer when the layer thickness becomes larger than it is adjacent to the furnace. In contrast to a cold-wall reactor such as
the critical layer thickness. taxial reactor that uses radio frequency (rf) heating.
156 Chapters .Film Deposition
8 3 Dielectric Deposition * 157
— Pump
SiH 4 -fO : -i^-»SiO :+ 2H, (,,,
The deposition process can Ik? performed either at atmospheric pressure in a CVD reac-
La*! Gh tor or at reduced pressure in an LPCVD reactor (Fig, Ma). The lew deposition tem-
i!<«ir inlet
perature of the sdane-oxygen reaction makes a suitable process
it
when films must In-
w deposited over a layer of aluminum.
For mteniiediate-teiii->eratiire deposition ,-|MI SI III O, silicon dioxide can I*- formed
lnuiliit(xl rf input Wafers bj decompo^gtetiaethybrthosAcate, SI oc n in an U'< reactor Hie compound
>
. VD
abbreviated TEOS. is vaporized from a liquid source. The TE( )S ompound da omp ises
^
J Class
cyfadef as follows:
(
Aluminum Si(OC,H,)
4
—S^SiO, + by-products (13)
clectnxles
forming both SiO, and a mixture of organic and organosilicon by-prodm ts. Although the
t I
higher temperature required lor the reaction prevents its use over aluminum, is suit- it
Cm I urn])
Gas ii polysilicon gates requiring a uniform insulating laver with good step coverage.
inlet
lata
Hr-at.-d
The good step coverage is a result of enhanced surface mobiHt) at higher temperatures
The oxides an be doped In adding small amounts of the dopant hydrides phosphines,
c
doping compounds are present. The dependence ol the deposition rate on TEOS par-
sure is proportional to (l-e^' where /' is the TEOS partial pressure and /' is
>.
allel aluminum elec trodes. An rf voltage is applied to the upper electrode, whereas
the
rated with adsorbed TEOS. and the deposition rate becomes essentia]]) Independent of
lower electrode is grounded. The rf \-oltage causes a plasma discharge between the elec- TEOS pressure.
trodes.Wafers are placed on the lower electrode, which is heated between 100°C and Recently, atmospheric-pressure and low^mperotuxeCVD processes using TEOS and
400°C by resistance heaters. The reaction gases flow through the discharge from outlets ozone have been proposed."' as shown in Figure S.10. This CVD technology produces
( )
located along the circumference of the lower electrode. The main advantage of this reac- oxide films with high coniormalitv and low visoosttj under low deposition temperature.
tor low deposition temperature. However, its capacity is limited, especially for large-
is its The shrinkage of oxide film during annealing is also a function of ozone concentration, as
diameter wafers, and the wafers may become contaminated if loosely adhering deposits shown Figure 8.11. Because of their porosity; 0 -TEOS CVD oxides are often accom-
in
plement thermal oxides. A layer of undoped silicon dioxide is used to insulate multilevel lating lasers over polysilicon.
metallization, to
mask ion implantation and diffusion, and to increase the thickness of
thermally grown field oxides. Phosphorus-doped silicon
dioxide is used both as an insu- Properties of Silicon Dioxide
lator between metal layers and as a final passivation layer over devices. Oxides doped with Table S.l lists deposition methods and
properties of silicon dioxide BlmS W general
phosphorus, arsenic, or boron are used occasionally as diffusion sources. there is a direct correlation between deposition temperature and film quality. At higher
HJ Dielectric Deposition <* 155)
g/cm
| linil „
^u ^^ ^^ ^ ^ ^£
"J*.n
r indtt of silicon dioxide
<
•! 1 \
i i
is 1 .46 at a wavelength of'o.6328
1
Urn. Oxides with lowt-i
*5"
a
rk
rclractne uidex r^r-n
o| , ,., ,
11
'
oxi<l
"
;Hir(ms
r " s,,,,i,,,-;
„,„„
fr ° -
.
r
^ I S
°" "'I* ""'P' '-'"'^. annealing l.isl«»r>. ami dopant concentration. Usually higher '
OaseAni jPhvphqrui Bona TEOS ( |ualit> oxides are etched at lower rates.
mm sourer
Figure 8.10 Expt ri.nental apparatus for the O.-TEOS chemical vapor de-position system Step Cos e rage
Step Coverage relate* the surface topography of a deposited film to the sanous steps on
the M -nuconducto, substrate In the illustration of ideal, or cmfonml. step coverage
shown
10 in Figure 8.12fl, film thickness
uniform along all surfaces ol the step The uniformity
is
IVpoMtion t. mper.ilurv HKV'i:
of the film thickness, regardless of topographs is due to the rapid migration
of rcact.u.ts .
2 4 6
1 8.11 Dependence of the shrinkage of the 0,-TEOS CVD film on ozone concentration
using annealing Courtesx. of SAMCO Company. Japan.'
(.)
158
160 Chjpw 8 Mm Deposition 8.3 D.etectr.c Deposrt.on -« 161
O^arctany (i
5)
ing siLne-owgen deposition, no surfacv migration takes place, and the step coverage is
,!,.., ,, : :! „ .1 In r h< ..rrn.il angle Most evaporated or sputtered materials have a stepcov.
crage similar to that in Figure S.12/>.
P-Class Flow
A smooth topography is usually required for the deposited silicon dioxide used as an insu-
lator l>erween metal lavers. If the oxide used to cover the lower metal layer is concave,
circuit failure may result from an opening that may occur in the upper metal layer dur-
me deposition He, ..use phosphorus-doped silicon dioxide P-glass dej ovited at lowtem-
peratures becomes soft and flows upon heating, it provides a smooth surface and is often
used to insulate adjacent metal Liv ers. This process is called P-glass flow.
Figure S.13 shows four cross sections of scanning electron microscope photographs
of P-glass covering a polysilicon step. All samples are heated in steam at 1 100°C for 20
1
''
minutes. Figure & 13a shows a sample of glass that contains a negligibly small amount of
phosphorus and does not Note the concavity of the film and that the correspond-
flow.
ing angle (0) is 8.13fc. c, and d show samples of P-glass with pro-
about 120°. Figures
gressivelv higher phosphorus contents, up to 7.2 wt^fc (weight perceni l:i these samples,
die decreasing step angles of die P-glass layer indicate how flow increases w ith phosphorus
concentration. P-glass flow depends on annealing time, temperature, phosphorus con-
10
centration,and the annealing ambient.
The angle 0as a function of weight percent of phosphorus as shown in Figure 8.13 Blmscan
;
l«Ml(-|X)sitedbyaiiinteniu'(liat(--teuiix-ratur,sT5() (: LP(:\'n >n-
,
I
. ssn, alow-
can be approximated by
temperature (300°C) plasma-assisted CVI) process I'll. LHA n films are stoi- of
chiometric composition (Si ,N 4 ) with liigh density (2.9-3. 1 g/cm '). These films can be used
>,l20-f
10
-^* to passivato devices because they serve as good barriers to the diffusion
of w ater and
) silicon l>ecause
The films also can be used as masks for the selectiv e oxidation of
If we want an angle smaller than 45°. we require a phosphorus concentration larger
6 wt%. However, at concentrations above 8 wt%. the metal film (e.g.. aluminum) may
: sodium.
Silicon nitride oxidizes
films deposited by
erv slowly and prevents the underlying silicon from
v
lower densjt)
be corroded by the acid products fonned during the reaction between the phosphorus (2.4-2.8 g/cm
3
). Because of the low deposition
temperature, silicon nitride films can be
Plasma-deposited
in the oxide and atmospheric moisture. Therefore, the P-glass flow process uses phos- deposited over fabricated devices and serve as their final passivation.
phorus concentrations of 6 to 8 wt*. protection, serves as a moisture barrier, and prevent!
nitride provides excellent scratc h
sodium diffusion.
In the LPCVD process, dichlorosilane and ammonia react at reduced pressure to
8.3.2 Silicon Nitride
de,x,sit silicon nitride at temperatures between 700°C and S00«C. Tlie reaction is
It is difficult to grow silicon nitride by thermal nitridation (e.g.. with ammonia, NHJ
!•.... us,- ol ,rs sluw growth rate ami high growth temperatun Hmvever silicon nitride 3SiCl : H :+ 4NH : -^^Si^ + 6HCl + 6H :
H
Itt fr Cluplara Film Deposition
— . 1
8 3 Dielectric Deposition * 163
processed per hour) are achan- 45
Good film umlom.itv and high W«faf AwiMgbjpo; 0 Gate, Way
reduced-pressure process, As in the case of oxide deposition, silicon nitride
laces of the * Sum atddayv Al and SiO
pressure, and reactant concentration. Theactj. ;
dei>.Mt,..n .v controlled bs temperature, 40 • Sum at <k-Uv Cu and low Jt
deposition is about 1.8 eV. The deposition rat.- increases with increas. Interconnect delay. Al and
sation energv for SM I '/
partial pressure and decreases with an increasing A Intt- rctMimxi dday, Cu
oad low't ll
„, s total pressure <»r dichlonxsilane 35
1
ainiiioiiia-to-dichlorosilanc ratio. '
1
an amorphous dielectric containing up t„
LPCVD is 1
SiHcon nitride deposttefl' b) 30 1 1
hvdroge... The etch rate in buffered III is less than 1 nm/,„i n 1 /
S atomic [x-rcent at'J »
.
_ 25
thicker than 200 urn may crack because of T~
Id times that olTKOS-deposited SiO.. Films
'
J
Cilr. Al. S O, /' 1
silicon nitride at room temperature is about lO^Q-cn,.
the verv liigh stress. The resistivity ol
T
• t /
is 10 Wcm.
Itsdielectric COnstanl is 7. and its dielectric strength -
* /
/
In the plasma-assisted ( VD process, silicon nitride is formed either by reacting suane
15
and ammonia in an argon plasma or by reacting silane in a nitrogen discharge. The re.,c-
_ t c.t. .<:..
J
4-
Tlie products depend strongly on deposition conditions. The radial-flow, parallel-plate
'
i
Large concentrations of hydrogen are contained in plasma-deposited films. Tlie 8.14 Calculated gate and interconnect delay versus cln.nl. .gy
i
t.
BBDenoon The diet trt -
6 x 10* Wcm ility, high capability for gap filling, low deposition temperature, simplicity of pro-
:< I ease of integration. A substantial number of low-it materials have lx-en synthesized
for the intermetal dielectric in ULSI circuits. Some of the promising low-* materials are
8.3.3 Low-Dielectric-Constant Materials shi vTJ in Table S.2. Tliese materials can be either inorgmic or organic and cm Ik- deposited
\s ,!,m« « M/i-s . . ii!inuetoshrinl( down tothedeepsubmii ran regjoi I
. require a In either ( A l) or spin-on techniques.
1 '
tilevel intern mnection architecture to minimize the time delay due to parasitic- resistanei
(10 and oapadtance (C). The gain in device speed at the gate 1( »et bj th.-prop-
TABLE 8.2 Low-* Materials
ition deLiv at the metal interconnects because ol the increased RC lime constant, as
shown in Figure 8. 14. For example, in de\ u a W< ith gate length of 250 nm or less, up to Determinant Materials Dielectric ( xinsUnt
50% of the time d. lav is due to the RC delay of long interconnections. Therefore, the
Vapor-pliase deposition polymers rinorosilicate glass (FSG) 3.5-4.0
devii e totercocnection aetworii becomes a limiting factor in determining chip performance
Parylene N 2.6
metrics such as device speed, cross talk, and power consumption of ULSI circuits.
2 4-2.5
I'arylene I"
(Minute the intrinsic RC value of two parallel Al wires OS Um x 0.5 um "> cross section,
1
mni A )H.\M
I ( ..!>.,> (.., lias (l 1( .r(> || ().Alnv,
in length, and separated by a polyimide (A - 2.7) dielectric layer that is 05 Mm thick The n^.
nuts -I Al is2 7nfl-cm.
for silicon dioxide
equivalent ceD area of the eapadtor?
If we replace Sin Ll, ^S'^^SfSiS,
" chan9
' "*
l
"
thickne ». *
3.9
the
SOLUTION
Resistance
SOLUTION L the CTOSS -sectional rfimeasion of the wires s equal top/djvjj^
i
: I In-
d
^ "
(^/; )
X
(
C-
Spacing width )
so
3.9x1.28 25xA
d d
Therefore, the equivalent cell size is
value ofcapacitance for proper operation (e.g., 40 fF). For a given capacitance, a mini, 8.4 POLYSIUCON DEPOSITION
mum d is usually selected to meet the conditions of the maximum allowed leakage cur-
and ininiiniim required breakdown voltage. The area of the capacitor can Using pol>-silicon as the gate electrode in MOS devices
rent tin- be is a significant development in
Increased l>\ using stacked or trench structures. These structures are considered MOS technology. One important reason is that polysilicon surpasses aluminum for elec-
in
men trode reliability. Figure 8.15 shows the maximum time to
Chapter 9. However, for a planar structure, area is reduced with ising DRAM den- breakdown for capacitors with
Therefore, the dielectric constant of he film must be increased.
both polysilicon and aluminum electrodes u Polysilicon is clearlv
sity. I superior, especially for
Several materials have been proposed, such as barium strontium titanate BSTl
hitdi-fc (
md lead urcouium titanate PZT>. These materials are shown in Table S.3. In addition
tit. mates doped with one or more acceptors, such as alkaline earth
10* -
there are metals, or
PohtOkoa electro*
doped with one or more donors, such as rare earth elements. Tantalum oxide (Ta.O.)has
a dielectric constant in the range of 20 to 30. As a reference, the dielec tric constant ol
10'-
- \ is in tin- range of 6 to 7. and that for SiO, is 3.9. A Ta,(), film can be deposited by
a CVD process using gaseous TuCl. and (), as the- starting materials.
w /ox =5MV/cm
r = 300°C
electrode
*A 10'
T
Si \ , ?
Paraelcctric per«»vskite SrTiOj (STO) 140
(Ba^.SrJTiO^BST) .300-500 111'
PbMg^Nb^cyPMN) 1000-2000
I-Vrroel.-ctrk- pcrovsldte Pb'/r.T, Figure 8.15 Maximum time to breakdown versus oxide thickness lm a polysilicon electrode and
() r/T- >1000
an aluminum electrode.
*
^
to
to create shallow junctions
rs also used as a diffusion sourer °T\ « pr-Kessmute,,,,,.,,,,,,,.
viTsl ,!
lude the manufacture of conductors and res.stance „, S^gte^ s.licon , :
tact to erxstalhne silicon.
Additional uses inc l,i
R},. an,. „, 500-nm polyrftam dope,. w,,h u
^T^^^ ^ ^
, 1
AlM^mKUn reactor (Fig. S.ito) opemtcd between 600°C and 650°C Ls used to
"
deposit pdysiheon In pxroN/ing silane
according to the reaction si,,,,
1 ''t
„ Mst
I Mst.,„, eI'"'
'|
„i ...ip Uted ^ryaiheon Carrier traps at the grain
huh bc^dariea .use
verj resfatenee in .he Utt imp] d polysilicon. As FigSre s
< ..
SiH 4 -^-Si + 2H, (l9) tonce -hops rapidly, a^roadrfng thai oi ^planted
Zti*es res,.
stogje-oystal ilHcon, as the carrier
traps lx-come saturated with dopants.
Of tlie tw> mast low-pressure processes, one operates at a pressure of 25 to
common
I.VI Pa using l<N>'« silane, whereas the
other Involves a diluted mixture of 20«X to 30%
silane m nitrogen at the same total pressure. Both pnxvsses can deposit polysilicon oq 8.5 METALLIZATION
waie.s run with gcnxl unifonnity (i.e.. thicknesses within ±5%).
hundreds of per
8.5.1 Physical Vapor Deposition
Figure B ,M-shows tl.i.l.|)ositioii rate at four deposition temperatures. At low silane
jxirti.il press.... the d«-positioii rate- is pniportional to the silane pressure." At higher silanc The most common methods ,,| physical vapor deposition
(PVD) of metals are evapora-
concentrations, saturation of the deposition rate occurs. Deposition at reduced pressure tion,e-beam evaporation, plasma spray deposition, and sputtering Metals
and metal com-
ISMQerap) Hotted to temperatures between 600°C and 650°C. In this temperature range. pounds such asTi. Al. Cu. TiN. and TaN can be deposited by PVD
Evaporation occun
the deposition rate vines ;u, cxp(-E/A7>. where E t
is I" eV. which Ls essentially inde- when a source material is heated above its melting point in evacuated bsmber. The <
pendent of the total pressure in the reactor. At higher temperatures, gas-phase reactions e\ aporated atoms then travel at high velocity in straight-line trajectories.
The source an i
occurs, causing poor uniformity At temperatures much lower than 600°C, the deposi- and e-beam evaporation were used extensively in earlier generations of integrated
ctr-
tion rate is too slow to be practical. ClritS, bul they haw been replaced by sputtering for ULSI c ircuits.
Process parameters that affect the polysilicon structure are deposition temperature, In Ion beam sputtering, a source of ions is accelerated toward the target •"•<! impinges
dopants, and the heat cy cle applied following the deposition step. A columnar structure on its surface. Figure 8.1Sfl shows a standard sputtering system. The sputtered material
results when jx>!\ silicon Ls deposited at a temperature of 600°C to 650°C. This structure de-posits on a wafer that
placed facing the target. The ion current and energy c an be
is
consists of pohvrystalline grains ranging in size from 0.03 to 0.3 um at a preferred ori- independently adjusted. Since the target and water are placed in a chamber that has lower
entation of i
l K)l. When phosphorus is diffused at 950°C. the structure changes to crys- pressure, more target material and less contamination are transferred to the wafer.
tallite,and grain size increases to a size between 0.5 and l.O um. When temperature is One method to increase the ion density and. heme the sputter-deposition rate is to
Increased to 1050*0 during oxidation, the grains reach a final size ol to3 um. Although I
use a third electrode that provides more electrons for ionization. Another method is to use
the initially deposited film appears amorphous w hi n deposition occurs below 600°C.
growth characteristics similar to the polvcrxstalline-gr.un columnar structure are
observed after doping and heating. \0't
loged poiyafflcoii
II."
l
\
\
s i
lb"
rv - i
\
i
*d v
*
l.ct>n
i
-\
\
\ N
io«
Bugle >
^ '
-«.
X
N
10>
Ion (cm-! )
«» k-V
Figure 8.17 Sheet resistance versus ion dose into500-nn. [x-K-dic,.., ,t
)
| |
Collimator WP, 311, -> W 6HF (hydrogen reduction)
(2o )
|
ZWF, 3Si -> ZW 3SiF 4 (silicon reduction)
(2 l
2\VFn * 3Sill 4 2W 3SiF, 6H, (silane reduction) (22)
On
a Si contact, the selective process Marts
tn.m a silicon reduction process
Thi,
Long-throw sputtering. U Sputtering with a collimator.
process provides a nucleation layer of w
grown on s, but not on SiO,. The hv.L,,,
redu*
RflWt Ul (a , Standard .sputtering. (/») )
don process can deposit W rapidly on the nucleation forming the plug The hvdro-
layer,
gen reduction process provides excellent confonnal
coverage of the topographs This '
working pressures of less than 0.1 Pa. At these pressur, s gas scattering
for sputtering at
is important and the target-to-substrate distance can be greatl) increased. From a
less
6TiCl 4 + 8N H, -> 6 TiN + 24HC1 + N, (23)
simple geometrical argument, this allows the angular distribution to be greatly narrowed 2T.C1, + N, 4H ; -> 2TiN + 8HC1 (24)
which permits more deposition at die bottom of liigh-aspect features such :* contact holes. 2TiCL, + 2NH, * H, -> 2 TiN 8HC1 (25)
Cent* t holes with large aspect ratio are difficult to fill with material, mainly because
scattering events cause the top opening of the hole to seal before appreciable material has The is about 400°C to 700°C for NH, reduction and is higher
deposition temperature
jectorv is more than 5° from normal are deposited on the inner surface of the collimators.
8.5.3 Aluminum Metallization
Aluminum and its alloys are used extensively for metallization in integrated circuits. The
5.2 Chemical Vapor Deposition Al film can be deposited by PVD or CVD. Since aluminum and its allovs have low resis-
tivities (2.7 Ufl-cm for Al and up to 3.5 uft-cm for its alloys), these metals satisfy the low -
CV'D is attractive for metallization localise it otters coatings that are con formal, has good
Aluminum also adheres well to silicon dioxide. However tin-
step coverage, and can coat a large nuinlwr of wafers at a time. The basic CVD setup is resistance requirements.
problems, such
the same as that used for deposition of dielectrics and polvsilicon (see Fig. S.9fl). Low- use of aluminum in integrated circuits with shallow junctions often creates
as spiking and electromigration. Tins section considers the problems of aluminum met-
pressure CA'D is capable of producing confonnal step coverage over a wide range of topo-
graphical profiles, often with lower electrical resistivity than that from PVD. allization and their solutions.
One of the major new applic ations of CVD metal deposition for integrated circuit
pnxluction is in the area of refractor)- metal deposition. For example, tungsten s low elec- Junction Spiking
The phase diagram
trical resistivity (5.3 uli-cm) and refractor) nature make it a desirable metal for use in Figure 8.19 shows the phase diagram of the Al-Si system at 1 arm™
relates these two components as a function of temperature.
The Al-Si system exhibits
integrated circuit fabrication.
m Deposition
8 5 Metallization 4 171
where pK and pSi are the densities of aluminum and silicon, respectively, and S is the sol-
ubility of silicon in aluminum at the annealing temperature* If the
consumption takes
place uniformly over the contact area A (where A = ZL for uniform dissolution), the depth
to which silicon would be consumed is
EXAMPLE 5
S00°G, t = 30 min. ZL = 16 urn"'. Z = 5 urn, and H - 1 urn. Find the depth b, assuming
uniform dissolution.
eutectic characteristics; that is. the addition of either component lowers the* wstem's melt-
ing point below tluit of either metal. Here, the minimum melting temperature, called
SOLUTION The diffusion coefficient of silicon in aluminum at 500 : C is about 2 x 10 * em '/s; thus.
eutectic temperature, is 5TTC, corresponding to a 11.3%
and 88.7% Al composition. Si
VDf is 60 urn.The density ratio is 2.7/2.33 - 1.16. At 500'C. S is 0.8 wt«*. From Eq, 27. we httt
Hie melting points of pure aluminum and pure silicon are 660°C and 1412°C. respec-
tively. Because of the eutectic characteristics, during aluminum
deposition the temper- b = 2x6fj(^jo.8%xl. 16 = 0.35 Urn
ature on the silicon substrate must be limited to less than 577°C.
The inset of Figure 8. 19 shows the solid solubility of silicon in aluminum. For exam-
Aluminum will fill a depth ofh = 0.35 Urn from which silicon is consumed. If at the contact point
ple, die solubility of silicon in aluminum is 0.23 wt% at 400°C. 0.5 wi% at 450°C. and then is a shallow junction whose depth in less than h. the diffusion of silicon into aluminum CM
u s ur ->ihm; Therefore, when-vei aluminuiu
; ,,i
contacts silicon the silicon will dis- short-circuit the junction. ^
solve into the aluminum during annealing. The amount
of silicon dissolved will depend
not only on the solubility at the annealing temperature, but also on the volume of alu-
In a practical situation, the dissolution of silicon does not take place imihu mly. but rathe!
minum to be saturated with silicon. Consider a long aluminum metal line in contact with The effective area in Eq. 27 is less than the actual contact an a: hence,
at .
mly a few points.
an area Z/, of silicon, as shown in Figure 8.20. After an annealing p-n junction area
illustrates the actual situation in the
••!
time t. the silicon will b is much larger. Figure 8.21
!,,}
'
,,!SI -»'" ' "I approximate!) \ Dt along the aluminum line from the edge of the
aluminum penetrating the silicon at only the few points where spikes are formed. One
contact, w here D is the diffusion coefficient given by 4 x 10 - exp(-0.92/jtT) for silicon
way to minimize aluminum spiking is to add silicon to the aluminum by co-evaporation
172 » Chapter 8 .Rim Deposrtion
8 5 Metellization < 173
Figure 821 Schematic view of aluminum films eoiitactinvi silicon. Noli- the aluminum spiking j,
the silicon
until tho amount <•! silicon contained by the alloy satisfies the solubility requirement.
rial A I
in 0LS1 circuits has d^awbacb such Z '
, S^T^
«
"
Another to iiitr.xliuv a barrier metal layer between the aluminum and die sil- pnS^go«de s,u, artoAlp on
i<x)ii
in. iIhkI is
substrate 1
Fix;, s 22V Tins lurner uu-tal laser must meet the following requirements: and low-* polymers. "I
as S,() :
Al and its poor adneCEESoSSS 1
I ,-,ion d.scusses
2
copper metallic
It must fonn low eontai resistance with silicon, it must not react with aluminum, and
t
he Brsf method
1
TU7 T
I 77 Is
ra,,ri(a, "
, conventional
m '" ,mil,il, - V< - 1 (:
method
"
pattern the metal tin*
...
E u,l
als such .is titanium nitride (Ti.\ have Ixvn evaluated and found to be stable for con-
follow,,!
to pattern the dlewSE
by cfemfcd
Z
kJS J.
I
,
damascene sequence
ions in some regions will pile up. and voids will form in other regions. This pileup can for an advanced Cu interconnection structure. For a typical
damascene structure benches
short-circuit adjacent conductors, whereas the voids can result in an open circuit. lor metal hues are defined and etched in the intcrlavcr dielectric (ILD>. followed by
The mean time to failure MTF) of a conductor due to electromigration can be met J
i
EXAMPLE 6
If we replace Al with Cu wire associated with some lovv-A dielectric k 2 <> m st, allot ., Si( ) lasvr.
what percentage of reduction bo the RC time constant will be achieved? The resfsttvit) of AJ bsS 7
Uf2-cm. and the resistivity of Cu is 1.7 pil-cm.
SOLUTION
J
«r„
are three .nam parts o, the process:
„ ,
the key ,,„, Bum "wbtogtfc of mechanical action to '
(.)
EXAMPLE 7
ViU
Si,N 4
The
time
oxide removal
arelrand0.1r.„
is
s
and the removal rate of a layer
rate-
>
,
^
(called a stop layer)
*> '
rcmOMj
Did |
DiokvtrK SOLUTION
Si,N 4
(b)
lr O.lr
HA r = 0.2nm/min
Dfalectrfe trench
^
Dielectric
8.5.5 Silicide
(0 Silicon forms many stable metallic and semiconducting compounds with metals. Several
metal silicides show low resisivity and high thermal stability, making them suitable for
Dfefactrfc Dielectric ULSI application. Silicides such as TiSi, and CoSi. have reasonably low resistivities and
]|
are generally compatible with integrated circuit processing. Silicides become important
i)., fab* meta ll ization materials ;is devices become smaller. One important application of silicide
Si
3
X4 is for the MOSFET gate electrode, either alone or with doped polvMiicc.n poKeide ;<!xne •
the gate oxide. Table S.5 shows a comparison of titanium silicide and cobalt silicide
TaX
(d)
Metal silicides have- been used to reduce the contact resistance of the source and
dr;tii 'he gate electrodes, and interconnections. Self-aligned metal silicide technologv
1 823 Process sequence (Med to fabricate a Cii line-stud structure using dual damascene.
a Resist stencil applied. (/>) Reactive ion etching dielectric and resist patterning, (c) Trench and
via definition, (d) Cu depositions followed by chemical mechanical polishing.
Polishing slurry
tiiat allows glolxil penalization (i.e., makes a flat surface across the whole wafer). It offers
Slurry supply
many advantages over other types of technologies, including better global planarization
. >\ er large or small structures, reduced defect density, and the avoidance of plasma dam-
age. Three CMP approaches are summarized III Table S.4.
Tin- CMP process consists of moving the sample surface against i pad that carries
slurp, between the sample surface and the pad. Abrasive particles in the slurry cause Rotating platen
mechanic-id damage on the sample surface, loosening the material for enhanced chemi-
cal attac k or fracturing off the pieces of surface into a slum- where thrv dissolve Figure 8.24 Schematic of a CMP polisher.
swept away. Tin- process is tailored to provide an enhanced material removal rate
high points on surfaces, thus affecting the planarization because most chemical a
TABLE 8.5 A Comparison of TiSi, and CoSi, Films
are isotropic. Mechanical grinding alone may theoretically achiev e the desired plai
Properties TiSi. CoSi,
TABLE 8.4 Three Methods of Chemical Mechanical Polishing (CMP) 13-16 22-2S
Resistivity
2.37 3.56
Silicidc/metal ratio
Method Wafer Facing Platen Movement Slurry Feeding 0.97
Silicide/Si ratio 1.04
Rotary CMP Down Rotary against rotating wafer carrier Dripping to pad surface Reactive to native oxide Yes No
Orfiital CMP Down Orbital against rotating wafer earner S00-S50 550-900
Through the pad surface Silicidation temperature (°C)
w
Linear CMP Down 1.5 x 1010 1.2 x 10
Linear against rotating wafer carrier Dripping to pad surface Film stress (dvne/cm2)
g
considered Chapter 7). Tins process can minimize the overlap of these
um implantation, in
.lectrodes .,nd thus reduce parasitic capacitances. SOLUTION The reafsttvity Is equal .,, the product oi the mod
Figure s 25 shows the potyeide and salidde processes
A typical polycide formation rerirttoce and the film tfekfcne*
sequence is shown In RgUW j> 25^/. For sputter deposition, a high-temperature, high, p = R,xi
purirj compound target used to ensure the qualit) of the silicide. The most commonly
Is
Then
used sffiddes for the polycide process are vvsi TaS., and MoSi,. They are all refrac-
,
ing Silicide is formed, principle, onlv where the metal is in contact with Si. A wet chem-
m SUPREM may he used to simulate the deposition process. Like etch simulation, depo-
ical wash then rinses off the nnreacted metal,
leaving only the silicide. This technique modeling is very straightforward. Simulation is executed using the DEPOSITION com-
sition
eliminates the need to pattern the composite jx>Kcide gate structure and adds silicide to mand, which deposits a given amount of user-specified material on top of the current
the source/drain area to reduce the contact resistance. Structure. The material deposited may be either undoped or uniformly doped. If singfe-
Suicides an- promising materials for ULSI circuits because of their low resistivity crystal silicon deposited, then the crystal orientation must also be specified If poly-sil-
is
and excellent thermal stahility Cobalt silicide has been widely investigated l>ecause of icon is deposited, the temperature must be specified for SUPREM to determine the proper
its b« resistivity and high-temperature thermal stahility. However, cohalt is sensitive to polysilicon grain size.
native oxides as well as an oxygen-containing environment, and a large amount of silicon
is consumed during silicidation. EXAMPLE 9
Suppose we want to simulate the deposition of SOOA CVD silicon nitride on top of a drv ovule lav.r
gppn odmatefy 400A thick. If the p-type Silicon substrate is doped with boron at a level of 10" cm
ns<- SI I'll KM to determine the final oxide and nitride layer thicknesses, as well as the boron dop-
Sul. w.,11 ing profile in the oxide and nitride layers.
is complete-, the results are shown in Figure 8.26. which indicates final
ovule and
After simulation
in the
nitride- layer thicknesses of 379 and SOOA. respectively, and depicts the l)oron incorporation
oxide layer.
8.7 SUMMARY
Figure825 l'«-K, .<!,• u>d salfc ide pro «m a Polydde structure: I
i i
gate oxide, (ii) polysilicbB
films. In the epitaxial
..ii.l silicide deposition, ijjjl pattern polycide and (iv) lightly doped drain (LDD) implant, Sid* Modem semiconductor device fabrication requires the use of thin
single-c rystal films can be
wall formation, and source/drain implant. lh> Salkide
tfn* ture (i) gat.- patterning (rx>lysilicon growth process, the substrate wafer is the seed. High-quality,
the melting point. The common technique fl
onh 1.1)1) s.d. wall, and source/drain implant: (ii) metal (Ti. Co)
deposition; (Ui) anneal to grown at a temperature 30% to50% lower than
form salkide: and (iv) selective (wet) etch to remove nnreacted metal. foepftesldgrc^ffleek^^
. i
Tomiruim/etheKctimedeU duetopaiaiitfc^
theaflwde
process for ojunfc contacts copper metallization for intorconnects,
constant materials for Interlayet films are extensrveh used b
and bw^iele. m
the requirement, ol *
the multilevel interconnect structures oi ULSIi Ircuits. In addition,
rlfc chapter di* used
high-diele, tnc -< onst.u.t materials to Improve the gate insulator
performance and to inc rease
the capacitancv per unit area lor DRAM.
REFERENCES
I. A S. Crovc. Physics and Technology of Semiconductor De\icr.\. Wiley, S,-* York 1887
2 R K< il T I K.m.mv and Is C
Samwat. *A Model for Dopant IsxarporatkM fatn Cmu**. saw .
i R D Dupuis, MMaloijanic Chemical Vapoi Deposition ol iii-vv„„u m .l...u>rv - w,rr 226 «2.3
0864).
6. M OhdlBg, The Materiah Science of Ttiin Films. Acade mic Pr.-s». Sew York. 1992
7 J
C Bean. The Growth ol '
Novel Silicon Mat.-ri.Jv" Phyurs Today. 39. in Vi l<)V<
8 For a ditcussion on film deposition, sec. for example. A. C. Adanu. "Dielectric and
I) »,..„ in S \l S/r. Ed VLSI Technology. NKCraw-Hill. York 19S3 . W Polwdi<t,ii Kiln.
'J K Eiijmo ••..! loped Silicon Oxide Deposition by Atinosph.-m.' Pr.-ss.ire ;ind \jr*t Tin. [*r. .tun-
I
ed Vapor D.p..s,!„„, Wxug Tetraethoxyvdane and Owme."/. EUctmchnn Sot, L38, 3010 ISM
Figure8.26 PloC ofboroo bacoiporatkM into the csddebyw using SUPR1 M in U: Vl-.ms and C D Capio. 'Planari/ation of Phmphonis-Dop. d Sil.o.n Dioude ~j Fleet .
T Yamamoto,
II. "An Advanced 2.5nm OxHtted Nitride Gale
- ( ..I Dielectric f..r Hgdj ReMaUeOSS m»>
lUrge-Sak Integrat.il Ciront MuHilevd Interconaects,' Mater Sa. Eng. 23. 243(1998).
It is done h\ the evarx>ration of a species in an iiltrahigh-vacuuin { In
deposition process sys-
tem. Because it is a low^emperature process that lias a low growth rate. MBE can grow 14. li \ Y.i. <-r .11 nm MOSFETVLSI Teehnolog>-. Part 1 — An Overview,' IEEE Tran* Electron
A R Otterloo. and A Monlree. "Kiii.-ln.il .\s[)<A.ts of tin- I.I'CYl) ,,i TlUBium NUfiOW
strained layer structures. For strain. d-l..\er .-pit.cw. there is a c ritical lavvi thickness above 16 M |
Is.i.tmu II.
SM
.
|
Aside from epitaxial layers, there are four other important tyjx-s of films: thennal 20. D. Pramamk and A N Smm "VLSI Met..ll./..t..m t\..m Al.m.mmr. .....I lis Alloys, 5 U Rati /••'".
oxidi s dielec tric Livers |x>Iu r\ st.dline silicon, and metal films. The major issues related 26(1). 127 (1983); 26(3). 131 (1983).
Cht* 52
to film formation arc low-temperature processing, step coverage, selective deposition, 21. C. L Hu and J. M. E. Harper. "Copper Interconnections and Rrlialnl.tv. Meter. F*JH
uniformity, film quality planarization. throughput, and large wafer capacity. (1998).
193rd Mrrt
Thermal oxidation offers the lx-st quality for the Si-Si()
;
interface and has the low- 22. P. C. Andricacos. ct al.. -Dairuncene Copper Ek-clr. V latin K for Chip Interconnect*.-
est iteriacv t rap density see Chapter 3). Therefore, it is used to fonn gate and field oxides.
EUetmhtm. Sac . p. 3 (1998).
W
1
1 <
LPCYD oi dielectrics >nd poiysihcoa offers cuiifonnal step coverage. In contnist. PVD 23. j M StdSjerwald, «« al. tfemtal kUOmkd Plancri^ of Microelectronic Materiuly NVdev H*
uh! itmosphen. -pressun ( \ I ' genentlK result in noncouifonnal st. pmverage. CMP offers York. 1997.
I*
Metal CMP."
and Practicd Aspc<ts of Dioldric and
.
tion are also required for precise pattern transfer at p 141 (1995).
the decp-subinicron lithography level.
Problems * 181
ISO * Cnapttr 8. Film Deposition
unit area. \„ needed to form a monolayer under close- nesses are 30 nm.
•3. Find the number of atoms per
in contact with its six neighboring atoms), assuming
Mddng condition (i.e.. each atom is 18. Compare the advantages and disadvantages ol TiSi and CoSi. lor salicide applications
(assuming tin atoms are fully incorporated in the " pft-cui. and the dielectric
try 6 ifed .1. the doping 00BCattmtfc» tivity of I is organic polymer with dielectric constant 2 S
weight for tin is
gallium arsenide grown at the aforementioned rate). The molecular (c) Compare the results in (a) and (b). How much can we decrease the RC time delaj ?
18.69. and the pressure at 700°C for tin is 2.66 x 10** Pa.
1
20. Repeat Problems 19 (a) and (b) if the fringing factor for the capacitors is 3. The fringing
EPITAXIAL LAYERS factor is due to die spreading of the electric-field lines beyond die length and the width ol
SECTION S.2: STRUCTURES AND DEFECTS IN the metal lines.
In the x value for Ca,In, As) film grown on CaAs
5. Fmd the maximum percentage of
(i.e.. ,
6.
substrate and the lihi r« spectively Find
„ / are the unstrained lattice constants of the thick there, find the total resistance of the runner if the resistivity is 3 x 10 h cm Find '
the/values for InAs-GaAs imd Ce-Si systems. the maximum voltage that can be applied across the runner.
*22. To use Cu for wiring, one must overcome several obstacles: the diffusion of Cu dirough
SECTION 8.3: DIELECTRIC DEPOSITION
SiOj, adhesion of and corrosion of Cu. One way to overcome these obstacles
Cu to SiO,.
a plasma-deposited silicon nitride that contains 20 at* hydrogen and has a silicon-
is to use a cladding/adhesion layer (e.g.. Ta or UN) to protect the Cu wires. Consul, r
7. (a) In
to-nitrogen ratio (Si'N) of 1.2. find t and ij in the empirical formula of SiN.IL. (b) If the dadded Cu wire with a square cross section of 0.5 pm x 0.5 pm and compare it with a
given by 5 x 10* exp(-33.3y) for 2 > y> ered TiN/Al/TuN wire of the same size, with the top and bottom TIN layers 40 nm and
0.8.
variation of film resistivity with Si/N ratio is
wfaere vis the ratio, find the resistivity of the film in (a).
GO nm thick, respectively. What is the maximum thickness of the cladding layer it the
8. The dielectric constants of SiO,. Si A N„ and Ta.O, are about 3.9. 7.6, and 25, respectively. 1 1 s,stances of the dadded Cu wire and the TiN/Al/TiN wire are the same?
What Is the capacitance ratio for the capacitors with the Ta.< ami i.\i<:< n:t ride/oxide >
9. In Problem S. if BST with a dielectric constant of 500 is chosen to replace Ta.O v calcu-
late tlie area reduction ratio to maintain the same capacitance if the two films have the
same thickness.
10. In Problem S. calculate the equivalent thickness of the Ta.O, in terms of SiO. thickness if
both have the same capacitance. Assume the actual thickness of Ta,O s is 3pm.
12. The P-gfcs flow process requires temperatures above lOOO'C. As device dimensions
become smaller in ULSI. we must use lower temperatures. Suggest methods to obtain a
smooth topography at < 900°C for deposited silicon dioxide that c an lx- used as an insula-
14. Explain why the deposition temperature for polvsilicon films is moderately low. usually
between 600°C and 650°C.
t
9
Process Integration
Impurity
doping
Mien »wav e. photonic, and power applications generally employ discrete devices. For exam-
ple,an IMPATT diode is used as a microwave generator, an injection laser as an optical
Eta king
source,and a tl.vTistorasalugh-rxwerswitch. However, most elec tronic systems are built
on the intcgratal divtiit. which is an ensemble of both active le g., transistor) and pas-
I
mw e u resistor, capacitor, and inductor devices formed on and within single-crystal
.
.t
1
semiconductor substrate and interconnected by a metallization pattern. ICs have enor-
devices connected by wire bonding. The advantages include
mous advantages ov er discrete Wafer
reduction of the interconnection parasities. because an 1C with multilev el metalliza- out
(a)
tion can substantially reduce the overall wiring length: (b) full utilization of a semicon-
ductor wafers area, because devices can l>e closely packed within an IC cliip: and (c) drastic Figure 9.1 Schematic flow diagram of integrated circuit fabrication.
ous chapters to fabricate active and passive components in an IC. Because the key ele- isgenerally followed by etching (Chapter 5). which in turn is often followed by another
ment of an IC is the transistor, specific processing sequences are developed to optimize impurity doping or film formation. The final IC is made by sequentially transferring the
its performance. The chapter considers three major IC technologies associated with the patterns from eac h mask, level by level, onto the surface of the semiconductor wafer.
MOSFET. Alter processing, each wafer contains hundreds of identical rectangular chips (or dice).
three transistor families: the bipolar transistor, the and the MESFET. In addi-
tion, it discusses the fabrication of microelectromechanical systems by microniacluning
t\
;
all) between l and 20 mm on each side, as shown in Figure 9.2a. The chips are sep-
techniques. Specifically, it covers the following topics: arated b) sawing or laser cutting; Figure 9:2b shows a separated chip. Schematic top views
of a single MOSFET and a single bipolar transistor are shown in Figure 9.2r to give some
• The design and fabrication of IC resistors, capacitors, and inductors pe v c tive of the relative size of a component in an IC chip. Prior to chip separation,
• The processing sequence for standard bipolar transistor and adv anced bipolar each chip is electrically tested (see Chapter 10). Defective c hips are usually marked with
devices
• The processing sequence lor MOSFETs. with special emphasis on CMOS and
Gate
memory devices
Source Dr.iin
• The processing sequence for high-performance MESFETs and monolithic -50 to 1000 chips
»AMIM * Good
mal electrical.
-i
ai.il
P^^^KnT?^
mteramnecl.on environment
chip, are selected
tronu app lor ele .cations. ^ „l
Go«aA*tfc*be*^^
the p-type materia] that is of thickness ,l x parallel to the surface and at a d- ml. i
^
(n
has grown exp<me,,,ally We
. state-of-the-art IG Chip us*
, , mhe, „l COmp<»en(
S^«fc ,„
as its level of mtegraton
I refer 0 the «.mplexitx of an 1C
100 Components pet Chip,
/m</mm-.sr,;/e murium (MSI) to „p ,„ where W is the width ofthe bar. /. is the length of the bar (we
SSI rtfcn UP 10 aegect the end conoid
areas for the time being). ^ is the mobility of a hole, and pi v [s the doping
ner chta
SSmbraMoA
W famo* .-..h-grat™ (VLSI) to
tains over 2 billion components. where v is the junction depth. If the value of (which is a function of the hole con-
centration), and the distribute f/>!vl are known, the total conduc t;, n< can he i-..ilu-
s,< >;
where l/g usually is defined by the s\inlx>l R and is called the sheet resistance. The sheet
resistance lias units of ohms but is conventionally specified in units of ohms per square (ft/O).
'•i.mv resistors in an integrated circuit are fabricated simultaneously by defining dif-
ferent geometric patterns in the mask, such as those shown in Figure 9.3. Since the- same
processing evele is used for all these resistors, it is convenient to separate the resistance
into two parts: the sheet resistance H determined by the implantation (or diffusion pro-
.
i
cess: and the ratio LAV. determined by the pattern dimensions. Once the value of R is
known, the resistance is given by the ratio LAV. or the number of squares (each square
has an area of W
x \V) in the resistor pattern. The end contact areas will introduce addi-
tional resistance to the IC resistors. For the type shown in Figure 9.3, eac h end contac t
corresponds to approximately 0.65 Squares. For the meander-shape resistor the elect nc-
field lines at the bends are not spaced uniformly across the width of the resistor but are
crowded toward the inside corner. A square at the bend does not contribute exactly 1
square, but rather 0.65 squares.
EXAMPLE 1
90 urn long and LO urn wide such is the bawhaped resistor in Btguns
Find the value of a resistor
SOLUTION
« m cutter region) as one plate, the top ^J^'J^U*
and n-^od a MOS car**.
metal electrode as the
kyer a thermA
o*i<fe (a) 2 - fi. X-4X-^
Swn Figure form a
litlu.graphicallx ,W.n and etched i„
a
SSntfe. Next.
a s.luon
window is 1
5V
region m he xxinclow area.
:,
(5) lb) Changing die dielectric constant Iron. 3.9 to 25 and the thickness from LO am to 5 run we
obtain O, - 8.85 x 10 u C. and number of electrons = 8.85 x io
1
( , 553 x 10*.
'
<
u)u .
r( .
, h ^ (lu .,ee. rie pcrmiUix.tx ofsiBCOI. dioxide (the
dielectric M^tftli The Integrated Circuit Inductor
luriher. insulator* w,t, 9.1.3
:i >, 2d 3 fa
lb Increase the cyacitancv
the -vide thk*
lusher
d ed.s Kl,asSi> a ul Ia: O v winch have diclectnc COD, ic inductors have been wider) used ... Hl-V-based monolithic microwave Integrated
,, llM , Ilt ,arel>e nus
I
l
(ll
(i] ,. UlIK(
1
1 1
;
lower plate of the capacitor is made oi heavuy doped mate,
voltage, bec ause the
tilevelinterconnec tion technology. IC inductors have started to receive more and more
series resistance. attention in silicon-based radio frequencx and high-frcqueucv applications Manx kinds
rial This also reduces the asociated
used as a c apacitor in an integrated Circuit. he top and I
of inductors can be fabricated using IC processes. The most popular method is the
\ p-fl junction is so.uetin.es
capacitor are shown in Figure 9.4b. The detailed thin-film spiral inductor. Figures 9.5a and /; show the top view and the cross section ol
cross-sc, fonal s lew S ofan n -}> junction
because tins structure forms part of a
fabrication process is considered
... Section 9.2. a silicon-based, two-level-metal spiral inductor. To form a spiral induc tor, a thick oxide
device is usually reverse biased; that .s. thep region is thermally grown or deposited on a silicon substrate. The fust metal is tln n deposited
tool U transistor As a capacitor, the
to the n region. The capacitance is
not aconstant. but varies and defined as one end ol the induc tor. Next, another dielec tric is deposited onto metal
is reverse b.ascd with resjx-ct
1
is considerably higher
He than that of a capaci. MOS the via hole The spiral pattern can be defined and etched on metal 2 as the
til( .
hm Son series resistance is filled.
EXAMPLE 2 is defined as Lco/R, where L. ft. and Ware the inductance, resistance, and (requeue)
respectively. The higher the Q value, the lower the loss from resistance, and hence the
What » the stored charge and the number of electrons on a MOS capacitor with an area of 4 urn* model an IC induc-
better the performance. Figure 9.5c- shows the equivalent circuit for
thick SiO : and (b) 5-nm thick Tkflf The
applied voltage is 5 V for
tor I d.clectric of (a) 10-nm
R is
tor. the inherent resistixity of the metal, C and C are the coupling capacitances
both cases
between the metal lines and the substrate, and /< and ft are the resistances of the
silicon substrate associated with the metal lines, respectively. The o value increases lin-
eal .
with frequency initially and then drops at higher frequencies because of parasitic
resistances and capacitances
Some approaches e xist for improving the p value. The- first is to use low-dielectric-
metals (eg., Cu, All to replace Al> to reduce ft,. The third approach USeS an
resistivit)
l|U , t l K ,
o, resistance
calculate- integrated capacitance
to calculate the integrated inductance- than to
to estimate the square planar spiral inductor is given .is
However. simple equation ..
L= /i
0
/rr= 1.2 xlO-VV (6)
( ' -I num-
where 0, is the ^rmeability in vacuum (An X 10* H/m>. L is in henries, n is the
(a) (b)
the radius of the spiral in meters.
ber of turns, and r is
Figure 9.4 « Integrated MOS capacitor, lb) Integrated V -n junction capacitoi
188 Chapter 9 Process Integration 9.2 B.polar Technology •« 189
located on the top surface of the IC wafer, and each transistor must be elec trically iso-
lated to prevent interactions between devices. Prior to 1970. both the lateral and verti-
cil :
- ilitions were provided byp-n junctions (Fig. 9.6V). and the lateral p isolation region
was alvi r. s reverse bi.iscd with respect to the n-typc collector. In 1971. thermal oxide
w.i'- i:s, d for lateral isolation, resulting in a substantial reduction in device size (Fig. 9.66)
'
the base and collector contacts abut the isolation region. In the mid-1970s, the
ciuitle: e xtended to the walls of the oxide, resulting in an additional reduction in area
and emitter stripe widths have dimensions in the submicron region (Fig. 9.6V/).
(c)
formance than can be obtained with p-n-p types. Figure 9.7 shows a perspective view
EXAMPLE 3 of an n-p-n bipolar transistor, in which lateral isolation is provided b) oxide walls and ver-
provided by the n -p junction. The lateral ovule isolation approach reduces
tical isolation is
For an integrated inductor with an inductance of 10 what the required radius if the num- dielec-
not only the device size, but also the parasitic capacitance because of the smaller
nil, is
10x10
r = 2.08x10 '
m = 20.8 jiu. are formed inside the semiconductor, the choice of Crystal orientation is not as critical
1.2x10^x20
is to form a buried layer, The main
as for MOS devices (see Section 9.3). The first step
A thick oxide
purpose of this laver is to minimise the series resistance of the collector.
9.2 BIPOLAR TECHNOLOGY and window is then opened m the oxule^
(0 .5-1 urn)
is grown on the
thermally wafer, a
For IC applications, especially for VLSI and ULSI, the size of bipolar transistors must
A rnvuM lv controlled .miount of lov^^ cm"-) is implanted
the surface topography. This oxide isolation process is called bed oxidation "/silicon
Arsenic inipl.uit (LOCOS). Figure 9.9a shows the cross section of the isolation oxide after the removal
of the nitride layer. Because of segregation effects, most of the implanted boron ions arc-
pushed underneath the Isolation oxide to form a /)' layer. This is called the p' channel
stop lor chanstop) because the high concentration ofp-typc semiconductor will present
-Si02
cli.nistop
(»)
-Si0 2
p-hase
Figure 9.8 CrOSS-sectfonal views of bipolar transistor fabric-ation. (o) Buricd-laycr Arsenic implant
The second Step is to deposit ap n-type epitaxial layer. The oxide is removed and the
Wafer is plaeed in an epitaxial reactor for epitaxial growth. The thickness and the doping
concentration of the epit.ixi.il Lver are determined by the ultimate use of the device. Analog
circuits (with their higher voltages for amplification) require thicker layers (-10|im)and
fabrication. <a< Ovule isolation h liav
lowci dopings -5 < 1" whereas digital circ uits (with their lower voltages for switch- Figure 9.9 Cross-sectional views of bipolar transistor
implant
ing) require thinner layers ( -3 urn) and higher dopings (~2 x 10 cm Figure 9.8b shows implant, (c) Removal of thin oxide, (d) Emitter and CoUectW
ftodMlnKJ'WiO" 9 2 Bipolar Technolofly * 193
192 CMewJ
Mrf « in „.I «m mi * * *** SN*« <"*» (or **n,lel,) """«"«*• ipproacb ailed did* trie Udahon, is used to form tnsulating tuba t"
< •
isolate i aumbei
of pockets ol tingle-crystal semiconductors hi this approach, the device is isolated from
bom its common substr.it. and its surrounding neighbors b* .> dielectric layer
•
is formed inside I00>-orientod n-type riheon substrate using high-energy oxvgen ion
.1 *
is called
isolated on an ovule Inamelv, a silicon-on-
SIMOX (separation bj Implanted oxygen 1
Since the top Silicon is so thin, the isolation region easily formed by the LOCOS
SSSSSfflSSS X. ™ * «- fan*.
is pro-
miBttoncn]
9
i
oP-oons, s « UO,^ cess illustrated in Figure 9.8c or In etching a trench (Fig ff.lli and refilling it Withoxtde
» M1 four etching operations
bach operation must be Fig 9.1 Id). The other processes ale almost the same as those 111 Figures Q Be through
9.9 to form the p-type base, n' emitter, and n collector.
WM'
lh , J,
TIhmI .p.t"
i«
pro! W the completed
^r«n,i!,,s l
l,nn,tlH-eause(.lthea,ncvntrati(»n- 1
ddTusion. lhe Elector doping ,s given hv the emtaxtal doping Self-Aligned Double-Polysilicon Bipolar Structures
9.2.3
;ver. a larger&p^
representat witchmg transistor H
, 7x10 CH. I
fa. .
outd.fTus.on from the buned layer. The process shown in Figure 9.9r needs another lithographic step to define an oxide region
concentrate, inc ases because of
,h, eoll^or doping and emitter contact regions. This gives rise to a large Inactive device
to separate the base
area within the isolated boundary, which increases n<>t only the parasitic capacitances,
9.2.2 Dielectric Isolation but also the resistance that degrades transistor performance. The most effective way to
these effects by using a self-ali^iu structure
for the bipolar transistor, the device redw
is iso- '• is il
8911
Figure
1
Pre* M»«^^^J^
jO^*******
n
tueoce for dielectric isolation ^mT^ a
Voltage applJon -
:;=;:;.;;;;::;;;...„,!., *J--N >
KVI1 c-dled
) (
drv .-tel. proo- ,s used to pnxh.ee an opening in the oxide and poly l CVD
m( | ,
thermal oxide is then grown over the etched structure and a^ relatively
(Fi . 9 v. \ l
M , yl.i Because boron diffuses laterally as well as vertu ally, the extrinsic
the intrinsic base region that «s formed next,
I^m- region u.ll be able to make contact with
under the emitter contact.
Following the oxide growth step, the intrinsic base region is formed using ion implan-
tation ..I Ik . .n Pit; V Tins serv es to self-align the Intrinsic and extrinsic base regions.
l-V/ '.
\ft, r the intact is cleaned to remove anv oxide layer, die second poK-silicon layer is
m.planfd with or The n* polysilicon (called poly 2 is used as a solid-
dep. .s.ted and ;\s P.
pliase diffusion sount- to form the emitter n-gion and die emitter electrode. A shallow emit-
d.en formed through dopant outdiffusion from poly 2. A
rapid thermal anneal
ter r.-^ion Ls
the original volume of polysilicon. Thus, an opening 0.8 Urn wide will shrink to about
0.4 um if sid.-wall oxide 0.2 um thick is grown on each side.
BE C
Poly
Figure 9.12 Cross section of a self-aligned doubk--poU's«licon bipolar transistor with advanced
trtMKTi tsounon
196 » Chapter 9. Process Integration
M m vvluch
.
both n-channel
M< *FET) comptementarj tedmcjctf. jad
SttR 1-
£ < >s
coUed^OSandPMOS.resp*^^
| devices
because has the lowest pow*
CMOSSS - ULSI P-rttoOar attractive for
circuits ,t
r
-"-;::!;:::;
9.3.1 The Basic Fabrication Process MOSFET is not as complicated as that in a bipolar transistor, and control of the dopant
distribution is also less critical. This section now considers the major process steps that
n-channel MOSFET prior to final metallic
Figure 9 15 shows a Mispecttveview of an are used to fabricate the device in Figure 9.15.
>s a rjhospharus-doped silicon
cUoxide (P-glass) that .s used as an insu-
rjon The top layer
ami also as a gettenng layer
To process an n-channel MOSFET (NMOS). the starting material is a p-type, lightly
gate and the gate metalliA.tion
,«,, U-twern tin- jx)K^ilkx.n
]
doped (-10" cm"8), <1 00 > -oriented, polished silicon wafer. The < 1(K)> orientation is pre-
.....pare Figure 9.15 with Figure 9.7
for the bipolar transistor and note
| or nu.b.l.. i„ns t
ferred over <111> be< ause il has an interface trap density that is about one-tenth tliat
in its basic structure. Although both devices use
t|, ,| a MOSFET is considerabK simpler
of < 1 1 1 >. The first step is to form the oxide isolation region using LOCOS technology.
The process sequence for this step is similar to that for the bipolar transistor. A thin pad
oxide (-35 nm) is thermally grown, followed by a silicon nitride (-150 nun deposition
(Area = 6000 unr) 7
(Fig. 9.16V/). The active device area is defined by a photoresist mask and a Ixiron chanstop
l.iver and is then implanted through the composite nitride-oxide layer (Fig. 9.16{>). The
nitride laser not covered by the photoresist mask is subsequently removed by etching.
Ail. r stripping the photoresist, the wafer is placed in an oxidation furnace to grow an
i »\i.le called the field oxide), where the nitride layer is removed, and to drive in the boron
CEP
i
2
(10 urn )
devices MlydeUKa contt^
-05x05um the sheet resistance to about I QJD.
can be used as the gate material to reduce
drain. After the gate ,s patterned .g. m 1-
serves as a
it
Figure 9.14 Reduction in the an-.. of the MOSFET as the length minimum feature
than the gate-channel capac.tame
-
reduced
be much s.naller
length) is
lr.tegrat.on
19S Ch»p»«r9 Process
PMorv»i»t
M
Boiun diaiim-l implant
Field uxid.-
Srlf-uliKiK-d
Call OXldc
(c)
Pain-nunl pol)-»ilKx»n
flowed In heating the wafer to give a smooth surface topography digital information (or data) in termsoj bta fata
the entire wafer and is
Memories are devices that can store
windows are defined and etched in the P-glass. A metal layer, such and fabrit ated using \M< >S technol-
k„, y i:/, ( i
oMt.tit v .rious memorv chips have been designed
II,
i
,
EXAMPLE 4
MOSFETs. The depletion-mode M0S1 ETs«n» I
Ulut is the maximum gate-to-sourcv voltage that a MOSFET with a 5-nm gate oxide can with- deoletion-rnodfi
stand? Assume that the odde breaks down at 8 MV/cm and that the substrate voltage is zero.
SOLUTION
\ =,,
e
xJ = 8xlO*x5xlO =4V
s^xtsaaKSSS i
200 Chapter 9. Process Integration
Stor.it;.
1
To meet the requirements ol high-dositv DRAMs, the DRAM structure
.
has been
extended to the third dimension With stacked or trench capacitors. Figure 9.19/, sh.
1
a Simple trench cell structure. The advantage of the trend, tvpe is that the capa, itanre
Gbhan !>»«•
of the can be Increased by increasing the depth of the trench without increasing the
cell
surface a,.-., of silicon occupied by the cell The main difficulties ol making trench-type
Oiftajad
evil plat.
1
Cells are the etc hing Of the deep trench, which needs a rounded bottom comer, and the
oohnna baa
growth of a uniform thin dielectric Rim on trench walls. Figure 919b shows a stacked
1 Mccad cell structure. The storage capacitance increases as a result of stat king the storage can ,c-
x roar I"" 1
itor on top of the an ess transistor. The dielectric is formed Using the thermal oxidation
Capacitor or C AD nitride methods between the two polysilieon plates feni I
<• the stacked cell pro-
cess is easier than the trench-type process.
Figure 9 2o shows a l-Gb DRAM chip. This memory chip nsesO.lS-um design rules
Accra Trench c apacitors and its peripheral circuits are in CMOS, which is discussed in Section
transistor 9.3.3. The memory chip has an area of 390
1
mm
11.3 mm x 27.3 mm) that contains over
1
2 billion components and operates at 2.5 V. This l-Gb DKAM is mounted in an 88-pin
(b)
ceramic package, which can provide adequate heat dissipation.
y— Storage gate Both and DRAM are volatile memories: that is. they lose their stored data
SRAM
Tomtit gate
i Ki.l. when power is switched off. Nonvolatile memories, on the other hand, can retain their
data Figure 9.21a shows a floating-gate nonvolatile memory, which is basically a con-
ventional MOSFET that has a modified gate electrode. The composite gate has a regu-
Drain
|
1 u control) gate and a floating gate that is surrounded by insulators. When a large positive
Inversion region*
voltage is applied to the control gate, charge will be injected from the channel region
thru igh the gate oxide into the floating gate, when the- applied voltage is removed the
(c)
c-.u. be stored in tlu- storage capacitor. The voltage level on the capat itor determines the
stat,- of the cell. For example, * IJS V may be defined as logic 1 and 0 V defined as logic
sponding cross section through A-A\ The storage capacitor uses the channel region as
sitic capacitance C the product of which is the RC delay. The column line is formed
by rT diffusion the internal drain region of the serves as a conductive link MOSFET
layers under the storage gate and the transfer gate. The drain region
between the inversion
Figure 9.18d. capacitor cell.
can be eliminated using the double-level polysilicon approach shown in
93 MOSFET Technology « 203
i
ire 9.23a shows a CM< >s inverter. The gate of the upper E>M< )S device is connected
to the gate of the lower NMOS device. Both devices are enhancement-mode MOSFETs
Figure 922 An IC card The data stored in the NVSM can In.- accessed through the bus of the
re.Hlsvritc
central processing unit (CPl'i There an- several metal pads connecting to tin-
needed to make the p-channc] MOSF I-T. the number ol steps to make a MOS drCUil <
is essentially double that to make anNMOS circuit. Thus, there a trade-ofl between is
in p-type substrate, as shown in Figure 9.24«. In this ease, the n-tvpe dopant
concen-
(ration must be high enough to overcompensate for the background
doping)! thep sub-
strate i.e.. \„ > .\\). In both thep-tuh and the n-tuh approach, the
channel mobility
will lx- degraded because mobility is determined by the total dopant
tion is needed m eithei ol the twin tubs, higher c hannel mobility can be- obtained.
All CMOS c irc uits have- the potential lor a trouble-some problem < ailed latchup that
is associated with parasitic bipolar transistors. These parasitic devic es consist of the
rj-p-fl
transistor formed by the NMOS
source/drain regions,/) tub. and ri-type substrate, .is well
as the p-n-p transistor formed In the PMOS source/dram regions, n-type substrate, and
/) tub. Under appropriate conditSons, die collector of die p-n-p device supplies base cur-
tent to the n-p-n. and vice versa in a positive feedback arrangement This late Imp cur-
rent < an have serious negative repercussions in a ( :MOS circuit
\u effec tive processing technique to eliminate the latchup problem is to use deep-
trench isolation, as shown in Figure 9.24c." In technique, a trench with a depth deeper
this
than the well is formed in the silicon by anisotropic reactive sputter etching. An oxide
lay er is thermally grow n on the- bottom and walls of the trenc h, which is then refilled bv
(O deposited polysilicon or silicon dioxide-. This technique can eliminate latchup Ix-cause
the n -channel and /'-channel devices are physically isolated bv the refilled trenc h. The
Ownple.nentarv M< CMOS inverter. (fl» Circuit digram Circuit layout
Figured >S
detailed steps for trench isolation and some related < IMOS processes are discussed next
Cross section along dotted A-A' line of (b).
If)
H-ftitimfi p<hwnd
with the threshold voltage V, less than zero lor the PMOS device and V, greater than
zero for the NMOS device typically the threshold voltage is aboul 1
'4 V DD When
). the
the gate-to-grouod potential of PMOS is -Vm , whic h is more negative than Vr and
J,
the NMOS device is off. Hence, the output voltage (VJ is ver> close to VDD (logic 1).
W hen the input is at V,,,,. the PMOS (with = <»: is turned off. and the NMOS is turned
The CMOS inverter has a unique feature: In either logic state, one device in the
series path from V,,,, to ground is nonconduc tiv e. The current thai flows in either steady
State I s a small leakage current, and only when both devices are on during switching doei
tion is small, on the order of nanowatts. As the number of compon ts per clup increases, i
v-epitaxy
power dissipation becomes a major limiting factor. Low power consumption is the most
N*-<ubftrato
attractive feature of the CMOS circuit.
Figure 9.23/; shows a layout of the CMOS Inverter, and Figure 9.23c shows the device
(b)
cross section along the A-A' tub (also called a p well) is first
line. In the processing, a />
implanted and subsequent!) driven into the n substrate. The /'-type dopant concentra-
tion must Ik- high enough to overcompensate the background doping of the n substrate.
The subsequent processes for the n -c hannel MOSFETin the /; tub are identical to those
described previously. For thep-channel MOSFET, B or BV ions are implanted
into the n substrate to form the source and drain regions. A channel implant of "As* ions
(0
may be used to adjust the threshold voltage, and an m" chanstop is formed underneath 11
Refilled trench
Figure 9.24 VW6nsCMOSstnK*nres.(fl)n tub (fc)Twintub e
the field oxide an >und the ^-channel de\ice. Because of thep tub and the additional steps
i
.
,,
t;
,,,a,ion
active region
reduced Ix-causc of the lateral
.
illv ,M,ron for
is
oxidation
NMos » «««• >
— • ,
:
,dl
Tori t utv ,he pnxvss temperature
|
I
.
|
© ,,1
implanting the ton to the field oxide grown in wider spacings.
energy. «v can design the well depth with dif.
,
Implanted p-wvll
OoMentjtaaafly
Affined p-wefi
400 nn
n
I'oKmIhiiii
n ut p
tub
ljul.ly.lop.il
( l...ll-t.<l' Boron implant
.lr.un vtru.iure
tinned cluilllM'l
L0D1
n* poly Si fftM
p MOS n-MOS
bulled channel turfaee channel
\ \ STI
(b)
and the oxide layer can be removed by H ,P0 and HF. Figure 9.28 («) A conventional long-dunnd ( Nios stnictuie with i sfogk potyriheoc gate n
rKe polishing die nitride layer
step is helpful for the subsequent polysilicon pat- (/>) Advanced CMOS structures with dual poh/sflkefi gates
respective^ This initial rjlanarization
toning anil planarizations of the multilevel interconnection processes.
I'M' « buried type, as shown in Figure 9.2S<*. The buri. <l-type PMOS suffers
Offi* a
device size shrinks below 0.25
th,- n Hie most notice-
serious short-channel effects as
.,1,1,. phenomena lor short-channel
effects are the V T
roll-off. drain -induced l>..rner low-
leakage current at the off state, so tli even with the gate
ering (DIBL). and the large
'
urn and less, dual-gate structures are required: />' pol>-siucon gate for PMOS. and n* polysil-
icon for NMOS (Fig. 9.286). A comparison of\' r for the surface channel and tlie buried
channel is shown in Figure 9.29. Note that the VT of the surface c hannel rolls off more
slowly in the deep-submicron regime than in the buried-channel de\ice. This makes
the
operation.
surface-channel device with p' polysilicon suitable for deep-submic rou device
implantation of BFJ commonly used. However,
To form the p' pol\*ilicon gate, ion is
substrate
boron penetrates easik from the polysilicon through the oxide into the silicon
at high temperatures, resulting in a VT shift. This penetration is enhanced in the pres-
The v
-
200
( M(
K
Ffcurt
»
an area of
fabricated us.ng0.l8.,* ,„shAMu, llllls
(I |><'(1
ment
t..r ir.insr.'iu-r.
M , „, „,
VtRepresent
amph
b,(
BiCMOS technology has been suceecriulry devet
andosdDatoi
mos
I >,
processes ,,,
appoeatkaubwirele3S<
,MS ,. (1 on tli( (;N ()S .
,
,
^W
Xequ£
BiCMOS Technology pie F Ig. 9.32) is lor a high-performance BiCMOS process based on
9.3.4 the tvrinS Mi >s
combine* both CMOS ami bipolar
device structures
RiCMos is
I
, lecfandkMO that
, „ toccTbine these two Afferent technologies is to create an [<
^ in
to
The
reduce
initial material is a p-typj silicon substrate,
m lector resistance. The buried p layer Is
fa n buried
<
marn^n analog circmtstl CMOS, a kmvr power dissipatmn ^higher the collector deep n' the base p mask, and the poly-emitter mask In other
...ask,
pro-
Figure H •> compares a 1
* CMOS lope- cessing steps, thep' region for base contad can be formed with the,,
i m pl.,.it
C^porJ denrit) than hi,>olar.
C„ source/drain implantation of the PMOS, and
in the
:MOS inverter, the cunent to drive for to char-.-' the nexj load, is the the n" emitter Can be formed with the
For . (
a un of the bipolar transistor and l Us isthe base current of the b.polar transistor ami b Compared with a standard CMOS are the main drawbacks of BiCMOS. The additional
the CMOS. Since fc„ is much cost should be justified
larger than 1. the speed
equal to the drain curreni pi M m l>\ the enhanced performance
Oft - 5V
() (b)
Figure 9.31 (a) CMOS logic gate. (/>) Bipol.u CMOS i Hit :mos lu-u gov
nptt bipolar
pulyMlicon emitter
MjUtratr
n'ccmUrtbrw
5S T
th silicon Mid ,
,
I
I. t S .
mobility, vvnich
results in
^
lower scries resistance for a
nt nrU1 wliuh imimn| , (I , Auv
gi v, n
c
.
( ]t
inn x
devxv pyuK-tn iirIk r Pbotocaan
-
w )x
.
X I
,r
•
i
U , ,
.
MM
.
t |
each MESFET A relative!) lighi channel implant is used for the enhancement-mode • till and gate
evaporation
Switching device, and a heavier implant used for the depletion-mode load device. A is
gate recess is usually not used for such digital IC fabrication because the uniformity of
control, leading to unacceptable variation in the threshold volt-
each depth Ls chflicu'lt to
age. This process sequence can also be used for a monolithic
micnm aw integrated dr-
at,! iMMIC! Note that gallium arsenide MESFET processing tech- <-log\ is similar to
use the same design rules However substantial improvements m < r\ .1.. qualit) and pro-
I I \.iU'Ni..|imu-contact
cessing technology are needed before gallium arsenide can seriously challenge the pre-
eminent position of silicon in ULSI applications. Figure 9.33 Fabrication sequence of GeAi MESFET."
technologies of silicon integrated Circuits. This approach has enabled MEMS products to machining, and the UGA process.
' j
9 51
Bulk Micromachining
photoresist
mum — /
SiOX
In bulk micromachining, the device (e.g.. a sensor or an actuator)
large single-crystal substrate. Hie films are patterned
and transducer (unctions. hiertation-d^rjendent wet chemical
isolation (
is shaped by etching a
Load implant device USes two-sided processing creating a s.-ll-isolated structure with one exposed side
Switch implant
to the measured variables, such as mechanical or chemical Signals, while
the other tide
isenclosed in a dean package Two-sided structures are very robust for operation m envi-
ronments hostile to microelectronic devices, Simple rnechanical devices such as
diaphragm pressure sensors, membranes, and cantilever-beam piezoresistive acoeleratibn
T-gate
sensors are fabricated commercially by this technique Figure 9.35 illustrates fabrfca- ,i
(b)
formation tion process of a simple silicone nibber membrane.
Self-Jipirtl n
implant wittl (O
r-* J
als.
and trade-offs between structures made from bull; and tliin fill
eral differences
T\ pica! dimensions for bulk-mit romacliined sensors are
itcri-
pennits the fabrication of structurally complex devices b) stacking and patterning layers
TTWN or "building blocks"' of thin films, whereas multilayered bulk devices are difficult to con-
gtta
struct Free-Standing and movable parts can be fabricated using sacrificial layers. Figure
9.36 illustrates bow sacrificial etching techniques can l>e used to create an electrostatic
Ohiiuc contacts micromotor with w ell-defined, submic ron tolerance between the rotor and the center hub.
SUN.
Contact Mas (0
Si-.N,
(b)
TiPdAu
Silicone
rubber
Second-level Pohirakle
interconnects
(e)
Switch loud
Figure 934 Fabrication process for M ESFET direct-coupled FET logic ( DCFL)
with active
Figure 9.35
p^ing.
Fabrication pro*
W KOH
t ample dhcene rubber membrane
etching. (c)Sufc*ne rubber
spin coating. t«fl
(p
Nitride re^^^oV'il on back rid
Note that the n" source and drain regions are self-aligned to the gate."
loads
9.5 MEMS Technology < 217
A" example of the LIGA process is shown in Figure 9.37. An x-ray resist, ranging
from 300 u,n to more dun 500 u„, ,„ thick**, Is
Patterned 1st pojyjjloag h>vr
,
deputed on a *b*Xe
tnca ly conducive surface. Lithographic patterning
an eke? wS
is done with extended
exposure from
Mihstwtc WgWycomnuted K-ray radiation through an x-ray mask, as
Pj.vMV.itcd
NiIiconlft> vr
shown Figured. A flower-
Pa(t«m«-<l3rdp<»l> Shaped trench structure is formed in the thick resist
after developer treatment Fi« <) Th
Dimple* patterned on
PSC i — >
I
PSC removal
Hub anchor
(a)
phosphorite***
Figure 9.36 (a) Sacrificial process flow for an electrostatic micromotor. PSG.
1 '
li,j«vi»«ii.imJ<Uxl
pListtc stniclurr
' '
S hm, can used to electroplate many metal 10. Deposit 0.5 u.n of polv silicon.
v. . ;-! -n:- pUmg bLe replica,.
11. Dope- the polysilicon with phosphorus using POCl v
»o create threeKh.nens.onaI
^SdWtartlrfvm^ 12. Etch the polv silicon in the areas outside the gate region
«n.ctnres as thick as
bulk-micromachined devices, while retaining die same degree of
13. Implant arsenic to form the source/drain regions.
However, the initial synchratrao radiation
fetal ffaUrtfc is surface mtaomachinlng.
separation steps may result ... degradation of 14. Drive in the source/drain As implant lor 10 minutes at 1000°C dry Or
process is a very costly step, and
the ...old in
the original mold insert 15. Open contact holes in the gate, source, and drain regions.
TITLE NMOS Polysilicon Gate-Deck 3 COMMENT Etch polysilicon and oxide over source/drain regions
COMMENT Source/drain regions Polysilicon
ETCH
COMMENT Initialize silicon substrate Oxide Thickness-0. 07
ETCH
INITIALIZE Structur-nmosacti vei ni t str .
9.7 SUMMARY
This chapter considered processing technologies for pasM\ e components, active devices,
lCs. and MEMS. Three major IC technologies based on the bipolar transistor, the MOS-
FET, and the MESFETvvcre discussed in detail. It appears that the MOSFETwill Ik-
the dominant technology at least until 2014 because of its superior performance com-
pared with the bipolar transistor. For 100-nin CMOS technology, a good candidate is the
combination ol an SOI substrate with interconnections using Cu and low-& materials.
MEMS is still an emerging field. MEMS has adopted the lithographic and etching
technologies fr IC fabrication. Specialized etching technicjues have also been devel-
oped for MEMS: bulk micromachining using an orientation-dependent etc hing process,
surface micromachining using sacrifica) layers, and the UGA process using x-ra\ lithog-
REFERENCES
1. Fch a detailed discussion an l< process lirtegrnrJon, seeC v UuandW V Lee, Troeew Integration,* hi
C.Y. Cli.mu. Hid S \l S/.- K.k. VLSI TrchmJoffj. McCr.w-lliH NewYork 1996.
3. T. II. Lee, Thr Design of CMOS BadkhFnqima/ Integrated Cirvuitt. Cambridge University Press,
6 G P Lrtal, An Ads.uRt-d HighPerlonnance Trenoh-lsolat.-d Sclf-AUgtted Bi|*.U Technology." /£ ££ SECTION 9.3: MOSFET TECHNOLOGY
Trans Electron Den Ices. 34i 10). 2246 (1987).
•7. In NMOS processing,
7 W I- Bode | C C Tui. ^iid R- D Pliimmor. Bdt . Q*ki Reference Manual far Sanlcoiutucior
the starting material u , Ul lk,, m> , ,.
X
utniul, ,
S R W lluiif. "Menon Design ""I Technology." in M J
H.nws and D V Morgan. Eds.. Large Scale >
gateoride of 25
uw
(a) Brtimate the
doping po-nie along a ordinate
ihrZS Sb« „ £ ,
»
^.endinda, to ,h rijl
mroufpt the channel region <>r the source region 1
9 V K Stomu, &-mKvi M/«rf.w Memories— Technology. Testing, ami Reliability. IEEE, Nov York. 1997.
8. (a Why b <1<K,, ori.-ntation preferr. in NMOS fabrication?
^
,1
I„ Ul,.„ are ll„ d.sadvan-
Chip Cards—Hie IEEE Tech Dig Elecinm DnUlt
10. I' H.»i.umi Application Resolution." Int. Meet . U to a Bcld oxick Is used in NMOS devt es? c WhaJ problem, occux 3
p 15(1997) poKsihcon gates used ,o, gate lengths less than 3 J.,n?< Ian , the. arterial be m.I.s,,
11 R. D
Rung H Moiiiom'. and Y. Nagukuho. "Deep Trench ImiIuUoii CMOS Dnws," IEEE Tech Dig. u ed for porysflkon? (d) How is
. lelf^digned gate obtained and whal are lt> ...K.,,,,,,, ,?
Int Electron. Devkrt Meet p. 237 ( 1982). ,
(e) What purpose does P-glass seiM-?
12 D M Brcm. M Chew, and M. I'riinl)h'>. Trends In Advanced CMOS Process Tt-chnology." Proc •9. For a lloating-gate nonvolatiK- im-mory.
J. the lower insulator has | feteM
IEEE, p 1 646 (1986). BKl mn
OOnM Oil d I
is 10 t uck The insulator al„ve the lloa.ing gate
Down
h;cs , tlieleciric «mrt«nl d 10 1
13 II lligui-hi. et al . "Performance and Structure of Sc aled Bi|x>l.ir Devices Merge with is ioo nm
thk* u the currenl density hi the lower i.,s,.lato.s is
J give,, \*v] = of:, where
GMOSFETi.- /£££ Wi Int Electron Dti ic, » Meet p 604(1984). o= 10- S/em, and the current in the other insulator is ncgl.gihK
small Bnd the Ihn shold
M A Hulks and R Murphy. "Homogeneous Field-Effect Transistors." in S. M. S»\ voltage shift of the device caused by a voltage of 10 V
II A. Ed.. High-Speed apphed to the trol g.„, for(,) 0 ZS
SrminHuiuctor Dexica. Wil.-y. New York. 1991). Us. and (I.) a Sufficiently long rime that/fa the Imvcr insulator Int. m.es n. gl.g.hlv small
15. II. P Stagk rt il CaAs Low Power Integrated Circuits for .. High Speed Digital Signal Processor." 10. Draw a complete st. p-l.v-st.
p set of masks for the CMOS Inverter shown in Figure 9.23.
/£££ from E/fffron Dei- ices. '»«. 240 IMS Pay particular attention to the cross section shown in Figure 9.23c for your scale.
16. C II Majtr.uigclo .uid W C Tang. "S«-miaindurtor M
St-n«jr Tttlinolin^. in S S/.-. F.d ,
Ml. A O.-v tin, digital CMOS technology hits 5-Jlm-widc transistors. The minimum wire ssidth
.We, -,./-,. f,., V,,.,.rv Uil. %. N.-w York. 1994 is and the metallization layer
i
Jim, consists of L-jim-thick aluminum Assume is
dial ji
17. L S. Fan. Y. C Tai. and R S. Mulli r. "IC-Processcd Electrostatic Micromotors." in IEEE Int Electron 400 eurA -s ,/ is 10 nm. \'
|l „ is 3.3 V. and the threshold voltage >s 0.6 V I'mallv. assume
Dei ire Meet, p 666 (1988). that the maximum voltage drop that can lie tolerated is 0.1 V when Urn k>ss s,-, .. 1 . |
anel Tclnnvrator* Workshop. Hvonnis. MA. Nov 1987 12. Plot the cross-s, t tional v iews of a twin-lul> CMOS stnicture of the following stages .,t
20. C P Ho and S K Hansen. SVI'REM II U sers Manual. Stanford University. 1983 priK-essing: (a) n-tub implant. (b)/>-tub implant, (c) twin-tub drive-in. (dl nonselective p'
source drain implant e selective n source drain implant using photoresist as mask and
I'
1
14. What is the boron [vnetration pniblem in />' polwiluwn PM< ISP HoWWOuU \>>u • liiuni.it>' it'
Asterisks denote difficult problems
15. To obtain a ginnl inteifat ial property, a buffered layer is usiulK deposited between the
SECTION high-A material and substrate. Calculate the effective oxide thickness If the stacked gate
9.1: PASSIVE COMPONENTS
dielectric structure is (a) a buffered nitride of 0.5 nm and (b) a Ta O, of 10 nm.
1. For a shed resistance of kft/Q find the maximum resistance thatI
can be fabricated on a
x 2,5 mm chip using 2-um lines with 4-Um pitch (i t-., distance Ix tuecn 16. Describe the disadvantages of LOCOS technology and the advantages of shallow-trench
2.5
the tenters
->f the
-
p.n.illi
isolation technology.
2. Design .. m.,sk set for ., 5-pF MOS capacitor The oxide thickness is 30 nm. Assume that SECTION 9.4: MESFET TECHNOLOGY
the minimum windmv size is um and the maximum registration errors are 2 Um.
2 x 10
17. W hat is the purjxise of the polvimide used in Figure 9.34/?
3. Draw a complete stcp-by-step set of masks for the spiral inductor with three turns on a
substrate IS. W hat is the reason that it is difficult to make bipolar transistors and MOSFKTs in CaAs?
4. Design a 10-nll square spiral inductor in which the total length of the interconneet is SECTION 9.C: PROCESS SIMULATION
350 Jim: tin spat ing between turns is 2 Jim.
•19. Use SUPHKM to simulate the bipolar process described in Section 9 2.1. Plot the doping
russ set ti",,s Iron, tin- top of the base contact,
MICTION !).2: HIPOIAK TECIINOLOGJ profiles along the following vertical t a
(b) from the top of the emitter Contact, and id from the top of the collector contact.
3. Draw the cm mt diagram and device cross section of a clamped
transistor.
•20. Use SUPKEM to simulate the CMOS process described bv FSgUW B 2a riot the doping
IdentiK the purpose
6. ,,f the following steps in self-aligned
dtmhle-pol^ilicon bi(x>lar struc- profiles along the following vertical cross Sections: (a) through the PMOS source drain
ture: (a) undoped polysilicon in trench in Figure 9.13a. (b) the PMOS gate region, through the NMOS sounx- dr.un rt^ions.
polv I in Figure 9.13/>. and regions, (b) through the (c)
id the polv 2 in Figure 9. 1.3//.
and (d) through the NMOS gate region.
10.1 Electrical Testing < 227
prodm is \s illustrated in Figure 10.1. a manufacturing operation can he viewed fabrication process. In addition, electrical testing of the final product is cnicial to
is|,« «l ensure
graphic.JN as .1 s\>triu with raw materials and supplies serving as its inputs .mil finished quality. These concepts are discussed in more- detail in the following subsections.
commercial products serving .is outputs In integrated circuit manufacturing, input mate-
rials include vmieonductoi wafers, insulators, dopants, and metals. The outputs are the
10.1.1 Test Structures
|( s ihcnwhi s Tin- txpes of processes that arise in IC manufacturing, whic h have l>een
the subjects of previous chapters in this text, include oxidation and deposition processes, To assess the impact of the presence ol delects On seinicouduetui wafers 1 .ois. il l>\ par-
photolithography etching, and doping implantation and/or diffusion bcles contamination, or other sources, special)) designed test structures are used These
However, before finished It s cm Ix- put to their intended use in \arious commer- Structures, also known as process control monitors P< iMsi. include single transistors, sin-
1 i.tl eleetrome s\ stems and products (such as computers, cellular phones, and digital eam- gle lines ol conducting material, MOS capacitors, and interconnect monitors. Prcxluct
1. in 1. several other key processes must take place. These include elect ri- .J testing and wafers typically contain several PCMs distributed across the surface, either in die sites
packaging Testing ls necessary to yield high-quality products. Quality rt -mires confor- or in the SCribe lines between die (see Fig. 10.2).'
mance of all products to a set of specifications and the reduction of any > a: ability in the Process quality can be checked at various stages <>| manufacturing through in-line
manufacturing prrnvss Maintaining quality often involves the us< oi » i u< il process measurements on PCM structures. Three typical interconnect lest structures are shown
control \ desfamed experiment i.s an extremely useful tool for discovering key variables 1:1 Figure 10.3.' Using such test structures, measurements are performed to assess the
diat influence qu.dity characteristics Statistic.il experimental design is a pov\< .ful approach presence ol defects, which can he inferred l>\ the presence ol short c ircuits or Open cir-
for systematically varying controllable process conditions and determining their Impact I nits using simple resistance measurements. For example, the meander structure fadl-
on output parameters measure quality that nates the detection of open circuits through increased eud-to-end resistance of the
A key metric that can be used to evaluate any manufacturing process is cost, and
cost is directly impacted by yield Yield refers to the proportion of inanui •ctured prod-
ni ts that perform as required by a set of specifications. Yield is inverselv proportional to
ufacturing by tisiiiix the latest developments in computer hardware and software technology
to enhance expensive manufacturing methods
Tliis chapter describes each of these concepts. Specifically, it discusses the follow-
ing topics:
(» (b) (c)
1
Figure 10.3 Basic lest Structured fi* tatejOOBBBCl layers. (a) Meander structure. (/>) Double.
comb structure. If) Coiiib-inetuidcr-comb structure
meander Tlic double-comb structure can likewise be used to detect shorts, since
anv
extra conducting material bridging the twocoinl* will reduce the resLst;uicc Ivtween
combs Figure 10.4 Example of hwo-dime-nsional voltage s| „, p|„, f„ r -
., |>,pol.,r |f,
The O >mh-incandei-comb structure combines the capabilities of the
-:u;:ii(H .ii»tI\
other
two structures ami permits the detection of both shorts and opens. Various
combinations
(/Widths ol lines and spaces in these test structures allow the collection of Statistics on
defects of VnlOUl sizes. Word U-
(metal thai)
Functional testing at the completion of manufacturing is the final arbiter of process qual-
ity and yield. The purpose of final testing is to ensure that
all products perform to the
specifications tor which they were designed. For integrated circuits, the test
process
<lejH iul> a great deal on whether the chip tested is
a logic or memory device. In either
case, automated test equipment ATE is used
to apply a measurement
(
)
stimulus to the
chip and record the results. The major functions of the ATE are input pattern genera-
tion, pattern application, and output response detection.'
During each functional test cycle, input vectors are sent through the
chip by the ATE
m a timed sequence. Output responses are read and compared ui
t |, eq;. < ted results
Single obO
...ri f.ul
I Ins sequence repeated for each input pattern. It is often necessary to
is
perform such •'leakage)
tests at various supply voltages and op-rating tcmtM-ratures
to ensure d-viee operation
at all potential regimes. The number and sequence of failures in the output signature
an- indicative of manufacturing process faults.
Test results may be expressed in a variety of
ways.1 Two examples are shown in Figures Figure 10.5 ( .'ell map showing examples of failure patterns and defect typei
10 4 and 10.O. Figure 10.4 shows a two-dimensional plot
called a Amoo plot for a hypo-
thetical bipolar product In a shrnOO plot,
the outlined Shaded region is where the device
ls ...tended to operate, while
the blank area outside represents die failure
region. Another
typical test .utput is the cell map
, shown in Figure 10.5. Cell maps are very useful in iden-
MfMng and isolating dev.ee failures, particularly ...
n.emon array*. In addition, the pat-
terns generated m the cell map may
Ik- compiled, catalogued, and
later compared with
a library of existing defect types, thereby
aiding in the diagnosis of faults.
10.2 PACKAGING
Looseh defined, the term parkagfng
refers to the set of technologies and processes that
OOUneCt ICs wit), electron,, sw, ms A . useful analogy Ls to consider an electronic prod-
•at as the human body. Like the body, these- products
have br.un.s." which are analo-
gous ,o I(_s hlec tron.c pac kaging provides the-
-nervous svstem" Ls well as the "skeletal .
Overall, vU-i Ironic sv stems consist «>l several levels ot packaging, each with distuu -
live SPBIflfinlttwm><vtion devices. Figure 10.7 depicts packaging hierarchy' LevelO this
Folknving functional testing, individual ICs (or cbcv) must he separated from the sub-
ot 'plastic or
ceramic, with the latter called the CerDIR Tin CerDEP consists
This is essentially the first step in the packaging process. In a common method
strate.
ol a DIP
Constructed of two pieces of sandwiched ceramic with leads protruding from
that has been used for mam years, the substrate wafer ismounted on a holder and scribed between
the ceramic plates.
m both tin- x and tj directions using a diamond scribe. This is done along scribe borders
In the 1970s and 1960s, surface mount packog/a were developed in response to
~'i to 2"><) pui m width that an- formed around the periphery of the dice during fabrica-
need for higher-densit) Interconned than the DIP approac h could provide In contrast
;i
tion These borders are aligned with the crystal planes of the substrate if jxissible. After
to DIPs. the leads of a surface-mounted package do not penetrate the printed circuit board
scribing, the wafer is removed from the holder and placed upside-down on a soft sup-
(PCB) upon which it is mounted This means that the package can be mounted on both
port. A roller is then used to apply pressure, fracturing the wafer along the scribe lines.
sides of the board, thereby allowing higher density. One example of such a package is
11ns must be accomplished with minimal damage to the individual die.
the quad flatpack. or QFP (Pig. 10.9 1, which has leads on all lour sides to further increase
More modern die separation processes use a diamond saw rather than a diamond
the number of input/output (I/O) connections
scrilx- In this pnxrdure. the wafer is attached to an adhesive sheet ol tnvlar film. The
More recently, the need for greater and greater numbers of I/O onnections lias led (
saw is then used to either scribe the wafer or to cut complete!) through it. After sepa-
to the dev elopment of pin grid arrav PC :.\ and ball grid array (BC A) packages FigS. 10.10
i
ration, the dice .ire removed from the mylar. The separated dice are then ready to be
and 10:1 1, respectively), P< \s iave an I/O density ol about 600, and BCAs can have
! !
\022 Package Types •:ween leads lx-comcs tighter, the manufacturing yield decreases rapidly. The B( .\ ;illows
higher density and takes up less space than the QFP. but its manufac turing process is
There are a number of approaches to the packaging of single ICs. The dual in-line pack-
inherently more expensive.
age, or DIP (Fig 10S>. is the package most jx-ople envision when thev think of inte-
mted circuits. The DIP was developed in tlie 1960s, quickly became the primary package
for ICs. anil has long dominated the electronics packaging market. The DIP can be made
'
ibp of the IC die itself, often take the fonn of miniaturized ball grid arrays. They are
designed to be flip-chip mounted (see Section 10.2.3) using convx-ntional equipment and
M.K1. r reflow CSPs are typically manufactured in a process that creates external power
rfB&aJ I < >o»nta< :s and encapsulates the finished silicon the prioi to dicing tlx- wafer.
Fssentiuilv. ("SIS provide an interconnection framework for ICs so that before dicing,
each die has all external electrical contacts, encapsulation of the fin-
the functions (e.g..
Idtfdafllooa Oi aCOfflm&tfOlial lulK packaged l< Two essential features of this approach
'
.ire that the leads and intcqxiser laver i.m added laver on the IC used to provide elec-
tru-.J functioiiahtx and mtvhanic.il stability » are flexible enough st> that the pat kaged device
is compliant to the and bum-in. and the package can accom-
test fixture for full testing
modate the vertical nonplanaritv and thermal expansion and contraction of the underly-
ing printed circuit board during assembly and operation.
10 2 3 Attachment Methodologies
An IC must be mounted and bonded to a package, and that package must be attached
to a printed circuit hoard before the IC can used in an electronic system. Methods
!*• t lnp i.H
(c)
of attaching ICs are referred to as Level I packaging. The technique used to bond a bare
on the ultimate electrical, mechanical, and ther-
die to a package has a significant c fleet Figure 10.13 Illustration of (//wire. >/> llip-eliip .and -
tape-automated landing.'
mal properties of the electronic system being manufactured. Chip-to-package intercon-
nection is generally accomplished by either wire bonding, tape-automated Ixmding. or
flip-chip boniling (see Fig. 10.13).
pads fat ing upward The Au or Al wires are then attached between the pads and sub-
Wire Bonding Strate USing ultrasonic, thennosonic. or thennocompression Ixmding
'
Although automated,
Wire bonding is the method and is still the dominant technique for
oldest attachment this process is still time-consuming since each wire must be attached individually
chips with fewer than 200 I/O connections. Wire bonding requires connecting gold or In the thermocompnsslon technique I
Fig. 10.14). a fine wire (15-75 um diameter
aluminum wires between chip bonding pads and contact points on the package. ICs are i f rom a spool through a heated capillary. A small hydrogen torch or electric spark
first attached to the substrate using a thermally conductive adhesive, with their bonding '.in :i melts the end of the wire, forming a ball. The ball is then positioned over the chip
inding pad, the capillary is lowered, and the ball deforms into I nail bead" due to pres-
sure and heat from the capillary. (The substrate is maintained at a temperature of 150°C
to 2<M) C. and the bonding interface temperature ranges from 2S0°C to 350°C). Next,
the capillaryis raised, and wire is fed from the spool and positioned over the package
substrate. The bond to the package is a wedge bond produced b) deforming the wire
ith the edge of the capillary. The capillary is then raised and the
wire is broken neai
ther-
of the w ire: in addition, m.mv cpoxies Cannot withstand the temperatures needed in
moCOmpreSSion bonding, dtmsonic bonding r. presents a lower-temperature alternative
that relies combination of pressure and rapid mechanical vibration to form bonds
on a
(Fig. 10.15). In this approach, the wireis led from a spool through a hole in the bond-
ing tool, which is then lowered into position as an ultrasonic vibration at 20 to 60 kHz
tool is raised
causes the metal to deform and Bow (even at room temperature) As the
alter the bond formed, a clamp pulls and breaks the wire.
to the package is
Tape-Automated Bonding
Tape-automated bonding (TAB) was developed In the early 1970s and is often used to
bond packages to printed c ircuit boards. In TAB. chips are fust mounted on a flexible
polymer tape (usuall) rjoryimlde) containing repeated
copper bterconnection patterns
(Fig. 10.16). Hie copper
leads are defined by lithograph) and etching, and the lead pat-
tern can Contain hundreds of connections. After aligning the I( pads to metal intercon- .
nection stripes on the tape, attachment takes place In therma ompression (Fig. IO.ITi.
W (b)
Gold bumps art- formed on either side <>l the die or tape and are used to bond the die
to the leads on the tape.
A benefit of TAB is that all bonds are formed simultaneously, which significant])
Improves manufacturing throughput. However, unless all the leads are coplanar. relia-
bility problems can result, TAB also requires multilayer solder bumps with complex met-
allurgy. Gem-rally, these humps use gold or copper as the primarv constituent, with titanium
atively expensive.
Flip-Chip Bonding
l'lif>-cliip banding is a direct inten onnection approach in which the IC is mounted upside-
down onto a module or printed circuit board. Electrical connections are made via sol-
der bumps (or solderless materials such as epoxies or conductive adhesfves) located over
the surface of the chip. Since bumps can l>e located anywhere on the chip, flip-chip bond-
(c) (0 ensures that the interconnect distance between the chip and package is minimized.
Figure 10.14 Thennocoinpression bonding process.' («) Cold win- in .1 capillar) Ball forma- Hie VO density is by the minimum distance between adjacent bond pads.
limited only
tion. <<-) Bonding (</) Win- loop and edge bonding. (<•) Wirt- broken at edge. Geometry of In flip-chip processing, chips are placed face down on the module substrate so that
(J)
hdl-wedge bond. pads on the chip are aligned with those on the substrate (Fig. 10.18). A solder rellow
I
process is then used to simultaneously form all the required connections, thereby dras-
improving throughput compared with wire bonding. However, the bump fabrica-
11)
I .idled onto the bond pads to form the solderless bumps, which are then cured. The
polymer is stenciled onto the bond pads of the
substrate Alignment is then
ie organic
,
implished, and the final bond is formed by appKing pressure
and heat to the humps.
(d) (e)
3
Figure 10.15 UltrUotlic bonding process. (a i Tool glides wire to the package, lit Pressure and
ultrasonic energy form bond, ir and r/i T<x»I feeds win- and repositions above the IC. (e) Wire
broken bond. Figure 10.16 Tape-automated bonding
at
—
10.3 Statistical Process Control < 237
of these tools is the control chart. The control chart was developed by Dr. Walter Shewhart
of Bell Telephone Laboratories in the 1920s." For this reason, control charts are also often
referred to as Shewhart control charts.
A control chart is an online SPC technique that is used to detect the occurrence of
shifts in process performance so that investigation and corrective action may be under-
taken to bring an incorrectly behaving manufacturing process back under control. A typ-
ical control chart is shown in Figure 10.19. This chart is a graphical display of a
quality
characteristic that has been measured from a sample versus the sample number or time.
The chart consists of (a) a center line, which represents the mean value of the charac-
teristic corresponding to an in-control state; (b) an upper control limit (UCL); and (c)a
lower control limit (LCL). The control limits are selected such that if the process is under
statistical control, nearly all the sample points will plot between them. If the variance
of the quality characteristic is <r and the standard deviation of the characteristic is o. then
the control limits are typically set at ±3o from the center line. Points that plot outside
of the control limits are interpreted as evidence that the process is out of control.
(."enter line
i '
i t i 1 1—— ————— —
1 1 1 1 1 1 ' 1
'
Suppose an IC manufacturer wants to establish a defect density chart. Twcnt) different samples
limits is given by
of size ri - 5 wafers are inspected, and a total of 183 delects are found Set up the li-eliart for tin-
Centerline = c (2)
»
LCL = r-3Vc SOLUTION We estimate u using
;;: 3
from an obsened average
that r is known. (Note:
,
number of defects in a sample
*, ,.,
if these calculations yield a negative value
ui «h to 0) . *
for the
r
t
(c).
«,
LCL.
UCL=c+3#
UCL = M+3j- = 3.64
Center hue = c (3)
LCL = c-3VF
LCL =»7- 3^=0.02 M
EXAMPLE 1
,- = -= 1.48 continuous variables such as this can provide more Information regarding manufactur-
than attribute control charts like the 0- and H-charts.
ing process performance
When attempting to control continuous variables, it is Important to control both
limits can be found from Eq. 3 the
for the cchart. The upper and lower
control
This is the center line
bec ause shifts or drifts in
as follows: mean and variance of the quality characteristic. This is true
significant misprocessing. Control ol the mean
cither of these parameters can result in
UCL=c+3V? =5.13
variance- can be monitored using the standard
dela-
is achieved using an v-chart. and
number of defects
Suppose WC would like to set up a control chart for the average n n N
among the » samples, then
ov*r a sample size of n products. If there were c total defects
7)
the average number of defects per sample is
:
s --i-t(.v,-s) >
tt = - < 4>
ol sue n The square root of the sample-
n wherv X( . t x„ are observations in a san.pl.-
2 O 7Q7U
(8)
3 1 t VS./..)
that If a ijiiahh tharai tenstie is normallv distributed with a known mean u and standard 5 n 'i ii h i
.tion a thenx is also nonnally distributed with mean p. and Standard deviation af\/ti 6 U.U5I5
Tkui the Center hue and control limits for the v-chart are 7 U.y.">y4
8
9 u.yoy.j
10 fl O.707
11 ii07#D<t
o.y Cl
Center line = 5 (g)
12 fl G77C
13 n Q7Q.I
LCL»f-3.P U.U<»4
14
15
Since O is unknown, it must also 1m- estimated by analyzing past data ( button must 10
be applied in doing so since s itself cannot be used directly as the estimate U-causesis
17
not an unbiast-d esti mator of a I The term unbiased refers to the situation in w hich the
18
expected \alue ot"the < vtimator is equal to the parameter being estimated ^
Instead i actu- 19
al!-. ( stmi.trs, s ulirriw- is ., statistical parameter that dependent on the sample is
size 20 ()
;
IS',' 1
see Table 10.1 ). For m samples of size n, the average sample standard deviation is
21
_ 1
22
s = ~5>- (10) 23
m ,.i
0.9887
24 0.9892
It turns out that the statistic v / r, is. in fact, an unbias ed estimator of 25 0.9896
o.
U addition, the standard deviation of.9 is o^l -c] n >25 4(«-l)
. Using this information, the con-
trol limits for the s-chart can be set
'-4,-3
up as follows:
UCL = f + 3-JT^F
Center line =s (H)
LCL =
SOLUTION The value for c, for n = 5 ( found in Table 10. 1 ) is 0.94. The upper and lower control
limits for x can be found from Eq. 12 as follows:
When s/c4 is used to estimate a. the limits or. the ctn-responflingt-chart may be defined as
UCL=.f + -^- = 4.14nm
3 c,vn
UCL = .v+
Center line =
c 4 V/i
x
LCL=? —^- = 3.88 Jim
^2)
LCL = x —?L c 4 V/J
The upper and lower control limits for s can be found from Eq. 1 1 as follows:
UCL = .? + 3— JT^y = 0. 19 pm
EXAMPLE 3 c.
Suppose X-- and blurts are to be established to control linewidth IX-L = .?-3-v/T^T -0
for a lithography process.
B» fc'^rfton. Twenty-
5 fcnertdths are measured. Suppose the grand average for the
UB Boa is 4 01 um. If , = 0.09 mm. what are the control limits for the ,-chart?
Son. Since the LCL is (slightly) negative, we automatically set it to zero.
142 * Chapter 10 IC Manufacturing
10.4 Statistical Experimental Des.gn < 243
on process a produd quality, or both. This approach is useful for comparing methods,
deducing dependencies, and creating models to predict effects.
process control and experimental design are dosel) interrelated Both tech-
Statistical
(13)
niques can be used to reduce variabilit> However. SPC is a passive approach in which a
where the statement ll„:p /i, is called the null hypothesis, and II,: // * p, is called the
process is monitored and (Lit.i collected, whereas experimental design requires active inter-
alternative hypothesis. To perform a hypothesis test, we select a random sample from a
ventiOn In perforating tests on the prtxvss under different conditions. Experimental design
population compute an appropriate test statistic, and then either accept
i .hi also U' Inneficial in implementing SPC since designed experiments mav help toiden- or reject the duU
optimum hypothesis. For the yield experiment, the hypothesis test can be represented as
titv the most influential process variables, as well as their settings.
ing sections illustrate the use of experimental design methods in IC fabrication. To evaluate this hv potliesis. a rVW statistic is required. The appropriate- test Statistic
two batches
thevield
of ]o
iLita in Table 1 0 2 obtained from an
wafers were labricated using a standard
IC: manufacturing process
method (Method A) and a mod-
in which
'"
—n—
— —
s nr I
\"v
+
r
"„
<l5)
ified method Method B' The Question to be answered from the e.xp i .'. n ut is what evi-
where i/
v
and (/„ are the sample means of the yields for each method, nA and n„ are the
dence if any) does the data collected provide that Method B is realiv letter than
number of trials in each sample (10 each in this case), and
Method A?
tins Question, we examine the average yields for each process. The mod-
lb answer
j?
K-l)s;+K-l)5-
method Method B) gave an average yield that was 1.30% higher than the standard
ified
method However, due to the considerable variability in the individual test results, it niiglit
not be coned to immediate!) conclude that Method B is superior to Method A. In fact. which is referred to as the pooled estimate of the common variance of the two processes.
[he demoninator of Eq. 16 is called the number of degrees offreedom for the hypoth-
esis test. The values of the sample variances are calculated using K<| 7: = 2.9«> and
s„ = 3.65. Using Eqs. 16 and IS then gives values of s. - 3.30 and/ 0.88, respectively
TABLE 10.2 Yield Data from a Hypothetical IC
Manufacturing Process
We can use Appendix K to determine the probability of computing a given statis- I
Yield <<*> Meld (%) the likelihood of computing at statistic with nA n B -2- 18 degrees of freedom equal
to O.SS is 0.1 ()">. The value 0. 1 ')5 is the statistical signif'icanci
of the hypothesis test This
1 89.7 S4.7
means that there is only a 19.5 i
r
chaiuv that the observed difference between the mean
2 81.4 86.1
due to pure chance. In Other words, we can be 80.5% confident that Method B
3 845 yields is
83.2
4 84 S is really superior to Method A
91.9
5 87.3 86.3
6 79.7 79.3 10.4.2 Analysis of Variance
7 85.1 86.2
how we might use hypothesis testing to compare two dis-
8 81.7 The previous example shows
891 applications to Ik- able to
9 tributions. However, it Often important in LC manufacturing
is
83.7 83.7
Ik- interested iO determining wl.a h
10 845 88.5
compare several distributions. Moreover, we might also ;
and allows us to compare different sets of pro- Kach sum ol squares has un associated number of degrees ol freedom required for
builds on the iilt-a of hypothesis U-stint-
computation
its h.- degrees <>1 Greedom for the withm-treatment. betwcen4re«tmerri
I
OeOOOlKbkini |.e,.tiealments),t*wtf^^
variation in quality.
and total sums of squares, respectively, are
in a st.UistK-uIK significant
IhM illustrated bv example In the following discussion,
\\, A \ pro. i dure is
vR = N-k
represents hypothetical delect densities measured
oonsfifa fjbe data in Table 10.3, which VT m*-& (21)
using four different sets of process recipes (labeled 1 through 4).
,,„ w ifers fabricated
v„ = .V-l
lWAUieu»ofANOVA.we«illdetenninewl,ethei thediscrejK.nciesMjmi. recipes
oJ the via diameters within the
I e treatments Is truly greater than the variation
indi- The final quantity needed to Cany out analysis of variance is the pooled estimate ol
vidual groups of Mas processed with the same recipe.
the variance quantified by each Sum of squares. This quantity, known as the ikiiiii \quaiv,
4 in this case Note that the sample size n sum of squares to its associated number of degrees of freedom. The
fcbethe Dumber of treatments (k the ratio of the
-
is
s i±h-y.?
Sums of Squares v, N-k
Tbperfon W('\ \ sevemlk.-\ parameters must be computed. These parameters, called
between different treatments.
sums of squares, serve to quantify deviations within and
Let y„represent
rtfa treatment
the ith obscrvat.on
Ls
for
given by
the fth tnatment. Hie sum of squares within the
sl = h. =
v,
^— k - 1
(22)
= ii(» ->)
s,
py n -y,Y (17)
depicted in Table 10.4. The ANOVA table that corresponds to the delect densitv data In
To quantify the deviations of the treatment averages from the grand average, we use the Table 10.3 is Table 10.5. Note that in both the Sum of Squares and Degrees of
show n in
between-treatmcnt sum of squares, which is given by Freedom columns, the values for between and within treatments add up to give the cor-
responding This additiv e property of the sum of squares arises from the alge-
total value.
braic identity
/.i
Finally, the total sum of squares for all the data about the grand average is
XX(.v. -.?)' =X«.(s -?)' X2>. -»)' e»
/•I M M '•' -«
or equivalentfy,
sD = s r + S„
62 63 6S 56
60 67 66 62 TABLE 10.4 General Format of the ANOVA Table
63 71 71 60 Sum of Degrees of Mean Square
59 64 67 61 Squares Freedom
Source ol Variation
65 68 63
Between treatments Sr v i
k-i «i
66 68 6-1
v„ = 23 lis
i So .340
we can be 99.9954* sure that a*al differences exist among the four different processes of a cube.
in our example.
techniques are employed in manufacturing to systematically and effkientlv explore the 2 + d2 = 110.96
suc h as yield) The unifying feature in statistically designed experiments is -hat all fac- 4 + + r/ 4 = 255.82
tors are varied simultaneously, asopposed to the more traditional "one-variable-at-a-time" 5 + d,- 94.14
technique. A properly designed experiment can minimize the number of experimental 6 + + <i„ = 145.92
runs that would otherwise be required if this approach or random sampling were used. + + d. = 286.71
Factorial experimental designs are of great practical importance for IC in umfacturing B + + + 0\ 340,52
tively are used together in every possible combination. Thus, a full two-level is the average deposition
rate when the pres-
factorial the main effect for pressure. ,/
experiment with n fac tors requires 2 experimental runs. The various fa< tor lev el com-
when- P is
deposition rate (D) in angstroms per minute. The highest and lowest
levels of each fac-
effect Z < variable in a tw<, level factorial
or
two averages of the response (ty).
tor are represented by the + and - signs, respectively. The (2o)
display of lev e ls depicted in
Main effect = y.-y.
the first three columns of this table is called a design
matrix.
10.4 Statistical Experimental Design < 249
iN.i mt. -rifled in quantifying how two or more factors interact For exam-
\\, u,
3 entries by the I W,„ Column entries. In general, .he
pie. suppose that the pressure elleet is much greater at high temperatua>s than it is at
remand™ first divisor will be 2 md the
low temperatures A iiummim- of tliix interaction is provided by the difference between
the average pressure effect with temperature high and the average pressure effect with
temperature 1<a\ B\ convention, half of tills difference is called the pnsstin-btj-tctnperature
U ^
locating the plus signs in the design matrix.
Although the Yates algorithm provides 9
relatively straightforward methodology
I,),,^,,
arede„edbv
interaction, or svmbolic.illv. the /' x T interaction. This interaction may also be thought for
computing experimental effects, it should be pointed out
one-hall the difference in the average temperature effects at the two levels of pres. thai mode,-,, analysis of statis-
Cif as tical experiments is accomplished almost
exclusively by Commercially axailahle statisti-
sure Mathematically, this is
cal software pac kages,
a few of the more common packages Include hs
i SAS and
P*T = dn .-dn _ = l/4[(r/, f dt + r/ 5 + dj - (d. + d, + d, + rf.) J = 6.89 (26)
Mnutab rhesep«*ages completely alienate the neevssity of
^forming am tcdioushand
calculations.
The I' • l Idd FxF interactions an- obtained in a similar fashion. Finally, we might also be
interested m the interaction of ;J1 three factors, denoted as the pn-ssure-by-tcin^ature-by Fractional Factorial Designs
flmt rati' or d^fxTxr" interaction. Tliis interactk>n defines the average difference between
A disadvantage of the two-level factorial design is that the number of experimental
am two-factor interaction at the high and low levels of the third fac tor It is given by runs
UK .eases exponentially with the number of factors. To alleviate this < ©n< ^.fractional
r"xrxF = r/TO..-</ m . = -5.88 ( 27 ) factorial designs are constructed by Systematically eliminating some
of the runs in a full
factorial design. For example, a half frac tional design with n factors requires '
It is important to note that the main effect of any factor can Ik- individually interpreted onlv 2
runs. Full or fractional two-level factorial designs c an be used to estimate the
only if there is no evidence that the factor interacts with other factors. main effects
of individual factors as well as the interaction effects between factors. However,
the) an- '
processes ran lead to deformations or iionconformitiei where V is the functional yield The critical area the area
Uni .bditx i» K2 WUUiacturing is in whirl, a defect occurring
process disturbances olten result in or unintentional has a high probability of resulting in a fault. For example, if particle 3 m Figure 10.21
ta finished
products. Such :
is
Hie presence of such large enough and conductive, it has (alien into an area in which it
J ^^^Btdbnpworconfomianct-ofeli^minepiwlui-ts. causes 0 short between
b defined as the percentage ofdevfc^ the two metal lines bridges. The relationship between the
In the uiamn%*uringyield
it
yield, defect density, and
i uiisis .in mtined
a nominal performance specification. critical an-., is complex It depends on the circuit
geometry, the density of photolitho-
or cfaCUta that tneet
Yield c categorized .ls eithcr/m.<ri<W or parametric f unctjonal yield is deter
m 1h- graphic patterns, the Dumber of photolithography steps used in the manufacturing pro-
functional products. Often referred to as hard yield, the cess, and other factors. \ lew ol the more common models that attempt to quantif) this
mined In the pro,, irtion ol futt)
The development of models to estimate the functional yield of ICs is fundamental to man. il there are three circuits (CI. C2, and C3) and three defei I types such as Ml metal
and crvstallographie Haws. This is illustrated by Figure 10.21. Thus, the probability that a circuit will contain zero defects of any type is
holes, scratches,
models are usualiv presented as a function of the average number of defects
Yield
per unit area (D„) and the critical area (A, of the electronic system. In other words.
)
I M1M2.M3 15 M3 M2M1
2 M1M2M3 16 M1M2 M3
3 M1M2M3 17 M1M3 M2
4 M1M2 M3 IS M2M3 Ml
M1M3 M2 19 Ml M2M3
5
M2M3 Ml 20 M2 M1M3
6
M3 21 M3 M2M1
7 M1M2
M2 22 Ml M2 M3
8 M1M3
Ml 23 Ml M3 M2
9 M2M3
M2M3 24 M2 Ml M3
10 Ml
M1M3 25 M2 M3 Ml
11 M2
M2M1 26 M3 Ml M2
12 M3
M3 M2 Ml
13 Ml M2M3 27
14 M2 M1M3
Figure 10.21 Various ways in which dust particles can interfere with interconnect mask patterns
:
For \ circuits to
>'
this
-J
becomes
= cxp(-A.A) (32)
^ *"1PT
(37)
V = exp( -Afi^f = exp(-NAJ>a ) Murphy later believed that a Gaussian distribution would !>, ., better reflection of the
(33)
true defed density distribution than the delta function. However, since he was unable
provides a reasonably
The Poisson model is simple and relatively easy to derive. Ii
to integrate the yield integral with a Gaussian function substituted knflD), he approxi-
good estimate of vield when the ritical area is small. However,
c if D„ is calculated
based mated it using the triangular function shown in Figure 10.22r. This function results in
oo trnaH-arca circuits using the same />„ for large-area yield computations results in a the yield expression
OVeri) pessimistic compared with actual measured data.
yield estimate thai Is
(38)
Murphvs Yield Integral 21) A
B. T. Murph) first proposed thai the value of the delect density (/)) should not be con-
The triangular Murphy yield model is widely used today in industry to determine die
ll
"
Instead, bfi reasoned that /) must be simimed over all circuits and substrates using
effect of manufacturing process defect density.
a normalized probability denstt) function, / 1) The Meld can then be calculated using
H. H. Seeds was the first to verify Murphvs predictions. However. Seeds theorized
the integral
that high yields were caused by a large population of low defect densities (which are not
high enough to cause faults) and a small proportion of high defect densities (i.e., Iiigh enough
Y= )e^f{D)dD (34)
to cause faults). He therefore proposed the exponential density function given by
o
Various forms offiD) form the basis for the differences between many analytical yield
models. The Poisson model assumes that ft D) is a delta function, that is,
j{D) = 6(D-D0 ) (35) and shown in Figure 10.22r/. This function implies that the probability of observing a low
di A density is sigmficantiv higher than that of observing a high defect deusitv
where D0 is the average defect density as before (see Fig. 10.22a). Using this density func-
Murphy and integrating
Substituting this exponential function in the integral yields
tion, the yield is determined from Eq. 34 to be
KD Y ,= ! (40)
lr— = ]e f(D)dD= exp(-/M>0 ) (36)
o
Although the Seeds model is simple, its yield predictions for large-area substrates are
as shown before.
too optimistic. Therefore, this model has not been widely used.
Okabe, Nagata. and Slumada recognized the physical nature of defect distributions
/ID) f(D) and proposed the gamma probability, deusitv function.
" 1
Stapper has likewise developed
and applied yield models using the gamma density function.
1
is given by
- D*
D0
l
f(D) = \r(aW\
l
e- (41)
D0 D0 2D„
w here and p are two parameters of the distribution, and Ha) is the gamma function.
tt
The yield model derived by substituting Eq. 41 into Murphy 's integral
is
/(D)
1/D„
Y =f. + ^r (42)
the threshold voltage of the transistor, in this equation, e is a runc&n ol the th* kneai
of the oxide (d), and v, function ol the oxide thicknesi as well as the doping in the
is a
channel or =/(C... \', ). Both of these dimensions are subject to manufacturing pro-
cess variations. They Can thus be < haraeten/ed as varying according to normal distribu-
tions withmeans u and u_ and standard deviations o and 0 respec tiu-k see Fig. 10.24).
Using the Monte ( brio approach, we can estimate the parametric yield ol M< ISFFTs
produced by a given manufacturing process within a certain range of saturation drain cur-
rents by computing the value ol / for even, possible combination of C and V The
T
Figure 1023 ProUbftt) dearftj function for the p I dWribulloa result of these computations is a final performance distribution like the one shown in
Figure 10.24/>. This probability density function can then used to compute the pro-
Im-
portion of transistors having a given range ol drive currents. For example, if we wanted
to compute- the percentage of MOSFETs manufactured that would have a value of
between two and we would evaluate the integral
K = Umfl + ^0 "
= cxp(-AA) (43)
limits a h.
b
v = Iim I+ AA-
)""=.»_ (44)
to estimate the fractionof manufactured parts with any range of performance Estimation
[ of parametric- yield is useful for circuit designers because it helps identify the limits of
the manufacturing process to facilitate' and encourage design for manufacturabilitv
[f the critical area and defect density are
known (or can Im- accuratel) measured), the
Deprive binomial model is an excellent general-purpose yield predictor that can be used
for a variety of IC manufacturing processes.
tn varying levels of system performance. These variations result from the fluctuation of
numerous physical and environmental parameters (hnewidths. film thicknesses, ambi-
ent humiditv. etc which in turn manilest themselves as variations in final system per-
.
fonuance Mich as speed or noise level). These performance variations 1< ad to "soft " faults u. Mi
and are characterized by the parametric yield of the manufacturing process. Parametric (•)
\ield is a measure of the quality of functioning systems, whereas functional yield mea-
sures the proportion of functioning units produced by the manufacturing process. /w
A common method Monte Carlo simulation In
used to evaluate parametric yii -Id is
the Monte Carlo approach, a large number of pseudo-random sets of values for circuit
or system parameters are generated according to an assumed probability distribution (usu-
ally the normal distribution) based on sample means and standard deviations extracted
from measured data. For each set of parameters, a simulation is perf ormed to obtain infor-
mation about the predic ted beha\iorof a circuit or system. The overall performance dis-
tribution is then extracted from the set of simulation results.
To illustrate the Monte Carlo technique, consider as a performance metric the drive
current of an n-channel MOSFET in saturation (/,,.) It tan he show,, that 1 *
hm'(^jfK,-VT f (45)
(b)
where / is the width of the device. L is its length. /i„ is the electron mobility in the chan- Figure 10.24 (a I
Normal probability density functions for C,. and Vr (/;) Overall probablltt)
nel. C. is the oxide capacitance [XT unit area. V, is the applied gate voltage, and V is density function for
T
6 *• Chapter 10 IC Manufacturing
References < 257
The CF.M standard is used in both semiconductor manufacturing and printed circuit lx»ard
20 years ago. This has led to the
of inaptitude more than a comparable
facility rise of a
assembly. This standard is based on the semiconductor equipment
communications ifeh-
lan>e contract manufacturing industry. dard (SECS) protocol.
As a result of ristog costs, the challenge before manuiacturers today is to offset such
amount of technological innovation in the fabri-
This type of IC-CIM architecture has great flexibility, allowing extension and adap
fauge capita! investment
with a greater
now to make use o| the latest
tation to meet constantly changing requirements. Over the past several years, powerful,
cation pr.xvss. In other words, the objective
is
develop,
flexible, and cost-effective information systems based on models such as this have Ix-come
r»nputerhatdvmreand software technology to enhance manufacturing methods
ments In
an integral part of the IC manufacturing enterprise.
effect, this eflbrt in computer-integrated
that have become prohibitively expensive. In
!( "-( MM is aimed at optimizing the ct)st-eilecti\eness
numuftuturing of integrated circuits >
of electronics manufacturing in the same manner in which computer-aided design (CAD) f> 10.7 SUMMARY
has dramatically affected the economics of circuit design.
This chapter provided an overview of the relevant issues in IC manufacturing. This included
Under the overall beading of reducing manufacturing cost, several suhtasks have been
a des< riptiou of electrical testing and basic pac kaging proc esses, as well as a presenta-
identified These include increasing fabrication yield, reducing product cycle time, main-
tion of statistical process control, statistical experimental design,
and \ield modeling. The
taining consistent levels of product quality and performance, and improving the reliabil-
chapter concluded with a brief introduction to IC-CIM systems. In IC manufacturing,
ity of processing equipment. Since fabrication processes often consist of hundreds of
process and equipment reliability directly influence throughput yield, and ultimately cost.
sequential steps, yield loss may potentially occur at every step. Consequently, maintaining
.
Over the next several years, significant enhancement of manufacturing operations will
product quality in an electronics manufacturing facility requires the strict control of liter-
be required to reach projected targets for future generations of microelectronic devices,
.dlv hundreds or even thousands The interdependent issues of high
ol process variables.
packages, and systems.
yield, high quality, and low cycle time can addressed by the developm. -nt ofsever.il crit-
l>e
equipment commuiucation. data acquisition and storage, process/equipmi nt modeling, and REFERENCES
re.d-time process control, to name a few. Tlie emphasis of each of these acti'.ities is to increase
: Pineda (k- Gysvz and D. Pradhan. Integrated ClmiU Manufaeturalrility. IK! I. l'rr-v IV. ,i.,v..,; N) I'm
throughput and reduce yield loss by preventing potential misprocessing. but each presents
2. A Undzberg, Ui<n>,-h,t,,,„>,, Manufacturing Diagnottia Handbook, Van Nostrand Rdnbold, Ne»
significant engineering challenges in its effective implementation and deployment
York. 1993.
A block diagram of a typical modem IC-CIM system is shown in Figure I0.25. Tins
3. R Tummala. Ed.. FuuiLmr„i„h ,./ A/irrmyW.-rm Packaejng. McGraw-Hill. New York. 2001.
diagram outlines many of the key features required for efficient manufacturing operations."
I \\ Brown .Kill •mini Electronic Packaging, IEEE Press. New York, 1999.
5. R. Jaeger. Introduction lo Microelectronic Fabrication, 2nd Ed.. Prentice-Hall, Upper Saddle Riwr. NJ,
2002.
6r planning Business svstt* m Design systems 6. D. Montgomery Introduction to Statistical Quality Control. Wiley, New York. 19S5.
control Marketing. ->a!i- IV'i.1-,. \iiiiiiLtn>ii
t j Pineda de Cyvez and D Pradhan, Integrated i 'ktttU Manufacturablliti/, IEEE Press. Nov York, vr<->
S B Murphy, "Coct-Size Opumaof Monolithic Integrated Circuits." /'w IEEE, 52,(12), 1537-1545
(1964).
Local Area Network 9. R. Seeds. "Yield and Cost Analysis «.f Bipolar LSI." IEEE Int Electron Dnicct Meet Washington. DC. .
October 1967.
Equipment Data Transport Test data 10 T Okal*-. M Nagata and S. Shimada '
\nal»is ..I Yield ol Integrate! Circuits ..ml I NtfW K\nr.-sM,.i,
control control for tfae Yield." in C. Strapper. Ed Defect and Fault Tolerance in VLSI System. Vol 2. Plenum Press. New
collection .
11. C. Stappcr. "Pact tad Fiction in Yield Modeling.- tffcrMfccl ronks ) . 210. 129-151 H9S9).
Processing 12 S Sa\ Semiconductor Dikes Physics and Tcchwlogy. 2nd Ed Wiles New .
York. 2002
Anahtical Transport Final test
njuipment equipment si
systems systems 13. D. Hodges. L Row.-. andC Spnooe, Compoter Integrated Manufacturing ..i V i Pi tings oJ
the Utfa IEEE/CIIMT Intenuitional Electronics Manufacturing T.-clmologs Symposium. September 1980,
Figure 10.25 Two-level CIM architecture. pp. 1-0.
158 Chapter 10 IC Manufacturing
PROBLEMS
Asterisks denote difficult prvbUtm.
MOSFETs using sample sizes of H = 10. It is known that the process normally dis-
tributed |l »
" v O - "
0.10 V. Find the (jester
is
olwervat.ons of sample size 10. These samples yielded a grand average of 0.734 V and an
axTrage5.ofO.125V.
7 + 45 come from the device level, material level, and system level, as discussed in the follow-
+ + + ing sections.
'4. Consider the throughputs (i.e.. wafers processed per hour) of five different manufacturing 11.1 CHALLENGES FOR INTEGRATION
processes (labelled A to E in the following table). For each process data wc collected on
Figure 11.1 shows the trends of power supply voltage (V im ). threshold voltage (VT ). and
three different dates. Perform an analysis of variance to determine whether the processes
and processing dates are significantly different.
•
iteoodde thickness (d) versus channel length for CMOS logic technology. :
From this fig-
in-, one can sec that the gate oxide thickness will soon approach the tunncling-cum-nt
limit of 2 nm. \', scaling will slow down because of the nonscalable V (i.e.. to a mini-
DAY A B C D B
r
mum V, of about 0.3 V due to subthreshold leakage and circuit noise immunity). Some
1 509 512 532 .506 509 challenges ol the l SO-nin technology and bevond are shown in Figure 11.2. '
The most
2 505 507 542 520 519 stringent requirements are detailed in the following subsections.
3 465 472 49S 483 475
NMOS transistors in order to achieve a functional yield of 95%. Assume the gate of each Year of the first 1997 1999 2002 2005 2006 2011 2014
device is 10 um wide and 1 Urn long.
product shipment
6. Use Murphy's yield integral to derive Eqs. 37. 38. and 40.
Feature size (nm) 250 ISO 130 100 70 50 35
7. Suppose the probability density function of the defect density 8G G
for a given interconnect DRAM size (bit) 256M 1 c 64
manufacturing process is given by
W afer size (mm) 200 300 300 300 300 300 450
Gate oxide (nm) 3-1 1.9-2.5 1.3-1.7 0.9-1.1 <1.0
/ID) = -100D 10 0SDS0.1
Junction depth (nm) 50-100 42-70 25-43 20-33 15-40
If the critical area for this interconnect Ls 100 em*, calculate the functional yield we can
DRAM, dynamic random access memory.
expect for the process over the range of defect densities from 0.05 to 0.1 cm' 1 .
Sour,, International Technolopj Rnadmap for Semiconductors. Semiconductor Industry Association. San Jose.
CA. 1999.
259
11.1 Challenges for Integration « 261
As the gate length shrinks below 130 nm, the oxide equivalent thickness of the gate dielec-
tric must be reduced around 2 nm to maintain performance-. However, if onlv Si() with i
a dielectric constant of 3.9) is used, the leakage through the gate becomes very high because
1
of direc t tunneling. For this reason, thicker lrigh-A" dielectric materials that have lower
lc;ikage current are needed. ( Candidates for the short term are silicon nitride (with a dielec-
tric constant of 7). Ta.O,, (25). and T\0 2 (60-100).
Silicide-related technology has become an integral part of subinicron devices for reduc-
ing the parasitic resistance to improve device and circuit performance. The conventional
Ti-silicide process has been widely used in 350- to 250-nm technology. However, the sheet
I .. ! I 1 i I i i i i
l
resistance of a TiSL, line increases with decreasing linewidth. which limits the use of TiSi.
002 005 0.1 02 0.5 1
100-nm CMOS applications and beyond. CoSK or NiSi processes will replace TiSij for
in
MOSFET channel length (Uin 1
Figure 11.1 Trends d powei wppl) voltage threshold voltage v.. and gate oxide thickness
versus channel length for CMOS logic technologies. Points are collected from data puhlished
(1
2
11.1.4 New Materials for Interconnection
Oyer recent wars.
To achieve lugh-speed operation, die RC time delay of the intercoimeetion must be reduced
Interlcvol dielectrics: Figure 8.14 showed the delay as a function of feature size.' It is obvious that gate delay
kiw-Jc materials for high speed decreases as the channel length decreases. Meanwhile, the delay resulting from Inter-
connect increases significantly as the size decreases. This causes the total delay time to
Metal interconnection: DilTusion harrier:
as the dimension of the device size scales down to 250 nm. Consequently,
both
copper is needed for kjw resistance CAT) metal for good confonnal deposition increase
high-conductivity metals, such as Cu. and lovv-dielectric-constant (low-fc) insulators. Such
as organic (polyimide) or inorganic (F-doped oxide) materials, offer major performance
gains. Cu exhibits superior performance because of its high conductivity 1 .7 utt-cm com- (
romigration.
pared with 2.7 ufl-cm for Al) and is 10 to 100 times more resistant to elect
shows decrease compared with
The ch-lav using Cu and the low-* material a significant
CPU
I
line
is a
DSP PLD 1 DSP
DSC
Control
Ms
Section 9 2 2 mentioned the
isolation of SOI wafers. Recently.
SOI technology Lis received J honk
\
„ iJit w
rfattentioa Tne advantages
structure
implex
well and isolation processes. In addition, shallow junc- uuuuuuuuuuuuuuuu
M1)t ,„,.,) ,]„.
through tie SOI 111... thickness. There is no risk of nonuni- Hoard components Virtual components
Hou ire directly obtained
be the physical thickness when the bigM! 5 hematic cross section of an embedded DRAM, including the DRAM cells and the logic
Fa m equivalent endde thickness of l 5 am, what will
materials nitride = Ta,0 5 (25). or TiO, (80) are used? CMOS devices. 7
Some processing steps are modified as a compromise. The trench-type
SOLUTION Fa nitride,
feHfc:
^ = l-5(^) = 2.69nm
Using the same calculation, we obtain 9.62 DDI for Ta; 0, and 10 77 run for TiO..
11.2 SYSTEM-ON-A-CHIP
Increased component density and improved fabrication technology have helped the real-
ization of the systnn-on-ti-, hip (SOC). that is. an IC chip that contains a complete elec-
tronic system. Designers can build all the circuitry needed for a complete electronic system,
such as a camera, radio, television, or personal computer (PC), on a single chip. Figure 11.3
show s an SOC application lor a PCs motherboard. Components (11 chips in this case)
once found on boards become virtual components on the chip at the right.' Figure 11.4 Schematic cross section of the embedded DRAM including DHAM cells at.
There arc two obstacles in the realization of the SOC. The first is the huge complexity MOSFETs. There is no height difference in the trench capacitor cell because of the DRAM cell
of the design. Since the component board is presently designed by different companies Structure. Ml to A/5 are metal interconnections, and VI to VI We u.i holes.
'
11.3 SUMMARY
Because of the rapid reduction in feature length, IC technology will .soon reach its prac-
List of Symbols
tical limit as the channel length is reduced to about 20 inn. W hat [Cs will Ik- beyond
CMOS is a key question being asked by research scientists. Major candidates include inno-
vative deuces based on quantum mechanical effects, because when the lateral dimen-
sion is reduced to below LOO urn, electronic structures will exhibit nonclassic.il behavior
depending on the materials and the temperature of operation. The operation of such M inlxil Description
UnM
devices will be on the scale of single-electron transport. This approach has been demon-
a Lattice constant
strated by the stade-eleetipn memory cell. The realization of such systems with trillions A
c Speed of light in vacuum
of components will be a major c hallenge beyond CMOS. s cm/s
C Capacitance F
D Diffusion coefficient em'/s
REFERENCES E Energy eV
Electric field V/cm
1. Internatknuil TeehivJogj Rutitlmap for Semiconductors. Semiconductor Industry Association. San Jose. 1999.
Xowak. "CMOS D.-\iu% IxUv 0 um low Will IVrli.rii.unoe Co?" IEEE Tech
/ Frequency lizfcps)
2. Y. T«ur and E. J.
1 I Hittfi
h Planck constant Js
DiR Int Electron Dnues Heel p. 215 ( 1997).
.
1 Current A
3. L. Petrn. "I» thr O.IS |lm Node Just a Roadside Attraction?" SrrofcW. Int. 22 46 < 1999)
J Current density A/cm'
4 M T Bohr. -Interconnect Scaling—Hie Real Liiniter to High Performance ULSI." IEEE Tech Dig. Int.
k Boltzmann constant J/K
Electron Device* Meet, p. 241 (1996).
I Length cm or um
5. E Leobandung, et aL. "Scalability of SOI Technology into 0.13 Um 2 V CMOS Generation." /£££ Int.
Electron Devices Sleet., p. 403 (1998).
1
Ml,, Electron rest mass h
n Refractive index
6 B. Martin. "Electronic Design Automation." IEEE Sfiectr. 36. 61 (1999)
n Density of free electrons cm" 1
7. H. Iihiuchi. e< aL. "Embedded DRAM Technologies." IEEE Tech Die, Int Electron Device* Meet., p. 33 Intrinsic carrier concentration cm 0
(1997). Density of free holes cm"
P
8. S. Luryi. J.
Xu. and A. Zaslas^ky. Eds.. Future TreiuL in Microelectronics. Wiley New York. 1999. P Pressure Pa
thermally grown SiO. 0.5 um thick. The length and width of the runner are em and
1 T Absolute temperature K
The 10 1
Q-cm. What the RC Carrier velocity em's
I (4m. respectively. resistivity of the runner is (b) will lie V
time constant for a polysilicon runner (fl t = 30 Q/h) of identical dimension'^ V Voltage V
cv,. n «
r/tni
Permittivity in vacuum
2. Why do we need multiple oxide thicknesses for a system-on-a-chip? *
Semiconductor permittivity F/cm
3. Normally we need a buffered layer placed l>etwcen a high-fc Ta.O. and the .silicon sub-
F/cm
Insulator permittivity
strate. Calculate the effective oxide thickness (EOT) whenthe stacked gate dielectric is
Dielectric constant
Ta.0, (it = 25) with a thickness of 75 A on a buffered nitride layer (k - 7 and a thickness
A Wavelength Um or nm
of 10 A). Also calculate EOT for a buffered oxide layer (k = 3.9 and a thickness of 5 A).
Frequency of light Hz
V
Permeability in vacuum ll/cm
A)
Electron mobility
CfliWs
ft
Hole mobility
cmWs
Resistivity
Q-cm
P
Ohm n
Q
265
1
^^Appen d i x B
International System
of Units (SI Units)
Length* Meter m
in
MkM
riwf k'
rv !
i m
1< i„i
i' r' .mi
•
1 1 1
kc
KS
S. , (
c
Temperature Kelvin K
( im»nt
VII IC III
'i Ainry*ri'
/\iui/i ic A
iifnt
1l<1i^iii iiiti*n<itv
mil uaiiy ' 'illiiti la Cd
H ,n ] rad
Frequency Hertz Hz 1/s
- I.6xI0- ,9 J).
267
Appendix C
Unit Prefixes*
VI „li; n |,,
.Multiple
Prefix Symbol
L0»« en E
10 15 peta P
10'*
ten T
10"
Pga G
10°
1
...ega
M
10 kilo k
10*
becto h
10 deb da
io-« deci d
10* ccnti c
io- J miOj m
10"«
micro H
io-» nano n
io-'« pico
P
10" (etntb f
10-'"
atto a
• Adopted by International Committee on V 'eights and Measures. (Compound prefixes should not be wed,
e g.. not \x\i but p.)
^^Appendix D
Greek Alphabet
Kappa K K
Lamlxla n
)
A
Mu M
\'u V N
Xi
E
Omicron o 0
Pi n n
Rho P p
Sigma a z
Tau X T
Upsilon V Y
Phi 0 <t>
Chi X X
Psi V
( >m«-«a 0) n
271
^^Appendix E
Physical Constants
Angstrom unit A 10 A nm » HP 1 um 7
» 1 - 10 cm - lO^m
Avogadro constant •v. 6.02214 x 10 n
Bohr radius 0 52917 A
Boltzmann constant Jb 1 .38066 x 10 *»J/K (R/NJ
27. J
Appendix F
Properties of Si
and GaAs at 300 K
Properties Si CaAs
thermal expansion.
AL/Lxr(°C-')
Melting point (°C) 1412 1240
Minority -carrier lifetime (s) 3x 10- -10-*
Mobility (cmWs)
1450 9200
fa (electrons)
(holes) 505 320
fa
Specific heat (J/g -°C) 0.7 0.35
^ApjDendix G
Some Properties of
the Error Function
(curirfiiurf/.i
1 1 . 3
5
278 Append* G Some Properties of the Error Function
Appendix G. Some Properties of the Error Function < 279
(continued I
(cunt inual)
rrfdr)
w rrf\u-) erfla) erf(a)
erfM
It' 10 erf{w) w «rf(u,) w erf(u>)
0929 734 1.74 0.9S6 135 2.21 0 998 224 2.67 0.999 841
1 .28
3.14 0.999 991 03 3.36 0 999 997 civ }
iS 0.999 999 55
175 0.956 672 2 22 0.99S 30S 2.68 0 999 849 i
3.80 0.999999 923
1*9 0.931 899
0.999 991 60
3.15 3.37 0 909
> i.j.i 99S
ii^ -7(1
i^'i
1 o co
•i.5y 0.999 99?) 61
1.76 0957 190 2.23 0.998 35S 2.69 0999 858 1 3.81 0 999 999 929
1.30 0 934 008 0.999 992 14
3.16 3.38 0 999 QQK 9A7 0 999 999 644
t 1 it i( i « i
\ i < i
382
•
1.41 0 953 852 1.85 0.992 156 2.34 0.999 065 2.80 0.999 925
3.27 0.999 996 24 OOO QOQ t\ (tflA A/V» nHA
3.49 0.999 999 201 i u.yyy
II
yyy QAK
mj O flO
o.y.j 0.999 999 9
0.992 479
1
9
143 0.956 S57 1.90 0 992 790 2.36 0.999 155 2.82 0.999 933
1
continual
Appendix H
Basic Kinetic
Theory of Gases
PV = RT = N n kT (1)
the pressure is lowered. Eq. 1 is valid for most vac uum processes. We can use Eq. 1 to
calculate the molecular concentration n (the number of molecules per unit volume i:
16 3
= 7.25 x 10
j molecules/cm (2a)
where P is in Pa. The density pd of a gas is given by the produc t of its molecular weight
and its concentration:
p,,
= Molecular weight x (3)
f-^J
The gas molecules are in constant motion and their velocities are temperature depen-
dent The distribution of velocities is described by the Maxwell-Boltzmann distribution
law. which states that for a given speed v.
4 ( m f , ( mv 2
\
where m is the mass of a molecule. Tliis equation states that if there are n molecules in
the volume, there will be (In molecules having a speed between v and v + dv. The- ,i\.t-
(5)
2N1
2S2 Appendix H. Bas.c Kinetic Theory of Gases
thai Is bow manv molecules impinge on a unit area per unit time. To obtain this param- Appendix I
obtained by using
ol integrated circuits. SUPREM can predict the results of oxidation, deposition, etching,
Tlie relationship between the impingement rat.- and the gas pressure is
diffusion, epitaxial growth, and ion implantation processes. SUPREM III models the
Eq. 2: changes to the semiconductor structure that result from these processes
in one dimen-
vl sion. The primary results are the thicknesses of various
0 = P(2mnkT)- (9) layers and the distribution of impu-
rities within those layers. The program can also
determine certain material properties,
such as the sheet resistance of diffused regions in silicon layers.
= 2.64xI0 JO
(
Jut) To run SUPREM. an input deck must Im- provided This' file contains a series
of state-
ments and comments. The deck begins with a TITLE statement, which is
when' P is the pressure in Pa and M is the molecular weight. merely a com-
ment repeated on each page of the program output. The next command. INITIALIZE,
is
a control statement that sets the substrate type, orientation, and doping.
This command
can also be used to specify the thickness of the region to he simulated and
establish a grid.
\lter the substrate and materials are established, a series of statements
used to specify is
(he sequence of process steps as they occur. Finally, the output
of the simulation can be
printed or plotted using PRINT or PLOT Statements, respectively. Simulation ends with
a
STOP statement. Several COMMENT statements will typically appear throughout the deck.
A description ol a lew commonly used SUPREM statements is provided in Table
1. 1
V'/i.-s tahl.- no means complete. To obtain the complete SUPREM software pack-
is I,,/
Ruilding 2
Fax: 40S-727-5297
www.silvaco.com
COMMENT <text>
None PLOT specifies that impurity PLOT <Paraaeters> Cm1n-<n>
comment Outouts character string to Active
concentrations or results of Cmax-<n>
label an input sequence Arsenic
Alu-iru- electrical calculations versus
Deposits specified material DEPOSITION <J*Jterial> Boron
deposition depth into the substrate
Thickness-<n> Temperature-<n> Nitride arc-
on top of current structure Chemical
Oxide to be plotted
* Net
Polyslllcon
Phosphorus
Silicon
Grin (cm-1 )
C.Phosphor (cm"*)
o«x (car*)
C. Arsenic (cm"3 ) PRINT Outputs information about PRINT <Parameters> Arsenic
C. Boron (cm"1 ) the structure being simulated
Boron
Thickness (urn) and coefficients used
Chemical
Temperature (°C)
Concentration
DIFFUSION Time-<n> Arsenic
DIFFUSION Models high-temperature Layers
Temperature-<n> <Oopant> Boron
diffusion in oxidizing and Net
<Ambient> Dry02 Phosphorus
DQOacidbing ambienLs
Nitrogen sAVtrlLt Saves the current structure SAVEFILE <Feature> Filename -<Text> Structure
Phosphorus being processed, the
Wet02 V\^.
( '( i if m llllf IUCU,
K H IIIA Kcinc
H !II l\. used
Solidsol or lx>th
HCI% (%) STOP Terminates simulation STOP <Text> None
T.Rate (°C/min) TITLE Inputs a character string to TITLE <Texr> None
Temperature (°C) lal>el the following input
Time (minutes)
Energy (keV)
INITIALIZE Sets up initial coefficients INITIALIZE <Structure> <Substrate> <iee>
and structure to be used in <Dopant> Concentration—:n> <ne>
the simulation <111>
INITIALIZE Structure-<f7 7e/ja/»e> Silicon
Arsenic
Boron
Phosphorus
Concentration (cm"3 )
(continual)
Appendix J
Running PROLITH
variOUS options from the View menu or by clicking the corresponding toolbar button for
the window. In each window, parameters may be entered bv marking or clearing
check-
boxes or option buttons, entering values in text boxes, selecting files or other values from
lists, and so forth. Many parameter windows,
such as the Resist parameters w indow, for
example, provide instant graphical views of the information entered.
After input parameters have been entered. PROLITH displays simulation results from
the Graphs menu. PROLITH can produce graphs simulating formation of a mask fea-
ture by an optical projec tion system, exposure of photoresist using this image, or devel-
opment ol the exposed photoresist. The following options from the Graphs menu (or
corresponding toolbar buttons) are available to displav suc h simulations:
• Exposed htttent Image: The latent image before post-exposure bake (PEB)
• PEB htttGnl Image: The latent image alter post -exposure bake
• Develop Time Contours: Contours of constant develop time as a function of
position in the resist
plete PROLITH software package and its associated doeumentat.ou. contact Appendix K
FINLE Technologies. Inc.
Austin. TX 78716
Phone. 512-327-3781 Percentage Points of
Fax: 512-327-1510
www.finle.com
the t Distribution
0.40 0.25 0.10 0.08 0.02.5 0.01 0.005 0.0025 0.00] 0.0005
1 0.325 1.000 3.078 6.314 12.706 31.821 63.657 127.32 318.31 636.62
<7
II iv) 0.816 1 886 2.920 4.303 6.965 9.925 14.089 23.326 31598
J yj.it i U.(fo 1.638 2.353 3.182 4.541 5.841 7.453 10.213 12.924
•1 0.2 1 1 0.(41 1.533 2.132 2.776 3.747 4.604 5.598 7.173 8.610
5 0.267 0.727 1.476 2.015 2.571 3.365 4.032 4.773 5.893 6.869
6 0.265 0.727 1.440 1.943 2.447 3.143 3.707 4.317 5.208 5.959
7 0.263 0.711 1.415 1.895 2.365 3.499 4.019 4.785 5.408
8 0.262 0.706 1.397 1,860 2.306 2.896 3.355 3.833 4.501 5.041
9 0.261 0.703 1.383 1.833 2.262 2.821 3.250 3.690 4.297 4.781
10 0.260 0.700 1.372 1.812 2.228 2.764 3.169 3.581 4.144 4.587
11 0260 0.697 1.363 1.796 2.201 2.718 3.106 3.497 4.025 4.437
12 0.259 0.695 1.356 1.782 2.179 2.681 3.055 3.428 3.930 4.318
13 0.259 0.694 1.350 1.771 2.160 2.650 3.012 3.372 3.852 4.221
14 0.258 0.692 1.345 1.761 2 145 2.624 2.SJT7 3.326 3.787 4.140
15 0.258 0 691 1.341 1.753 2.131 2.602 2947 3.286 3.733 4.073
16 0.258 0.690 1.337 1.746 2.120 2.5S3 2.921 3.252 3.686 4.015
17 0 257 0.6S9 1.333 1.740 2.110 2 567 2 S9S 3.222 3.646 3.965
IS 0.257 ()(>SS 1.330 1.734 2.101 2.552 2.878 3.197 3.610 3.922
19 0.257 ()(>SS 1.328 1.729 2.093 2.539 2.861 3.174 3.579 3.883
20 0.257 0.687 1.325 1.725 2.086 2.52S 2S-J.5 3.153 3.552 3.850
21 0.257 0.6S6 1.323 1.721 2080 2518 2.831 3.135 3.527 3.819
22 0.256 0.686 1.321 1.717 2.074 2.508 2.819 3.119 3.505 3.792
[continued!
2X9
Percentag. Pomts of the t D.stnbut.on
* App**x K
1706
70S 2060
2.056
2.485
2 479
2
Ltn^^pc™**- r™,
ffa*, C..bnd«J-
Mb m.f* «—-
*~ » "» 1866
«* >• « * * s *™» •»•' " 0
- •
I mm
-CTCJ-N
mm «mm m** mm 22222
—— — — — ———
fflSSI I
3338 S5593 ?,2!22 22222 BSSSS 222:2 22222
—
?-m §S8P 8§iH SSPP
s*?a «w* mm
r-'-i'N — — — — — — — — —
— » sssss ° 55333 oiS**^ ----- SS2SS 33533 33223
at
sss
m*%
o«ei<N
M
stsfess
— ————
s«3s
wif)
——— §g§§S
—— — —
22222 mm «si M9SS
fijffij §2§§§ 3S3a3
s
*
pil
PSS
IIISI
ISIIS 25333
HISS S5s65
MM SSSSg
53SS! 12525
MSB M
a
.<s2£
-
s^s*
----- ----<- -
— - 5--^ SB8 9BS9 !SBIa2 222:: 2:222 S5B9 222:2
22222 22222 22S22 22222 22222 P2I 0888 SaSBS 12222 §5222 ::!25 SSBS
1- HS§
SS08
^2
J
m 355*3 8338 22222 22222 55233 22222 p§s 12.52,2
009 001
Slf.2! 22222 22222 22:2!
i
m 2222! 2222! 22222 22222 22222 22:2:
f: sms
xsjicco
ssfsas S3$S2 222§s sssss sssss ss?5«
c-iooieioi oieioi<Nc4 eieie-ioiei <n<nci — — — — — ——— — -—
—
m 22222 22222 22222 22222 22222 2:222
ssas ^SSSoi ssass as!22= ggggs
w^oic-ic-i eicieioiei cioicicic.
sssss.
c*«moj- —
ss^-u
—
m 222!! 22222 2222S 22222 22222 32222
3338
?S3=
^c^cieici oioiMcici
SSS3g£ 2=2=5 SS'cSi
§§§§5 »2
ggS.S.^
ci^iw^oj elo<c4e>loS wmn<n«m ^m
ooieiae*
S||M
cic.c
00 222!! 22222 22222 22222 22222 22222 ^SS-f eieieioid cl-Soidcj
m mm mm mm mm sssss mm I
c =
£22'
i^ =-;z'£:; c^fig? 2^2:: 5 = SV:= =;-;-;7 .^su
»
'C-r-rnn ^ricioci ckrki^! ",",r,2£ 22Z!2Z I
w »
-----
OS SKI |g52* <c-r-r«« oci^ioioi eJ^Melc, cicicic.ci
da «
c>
M„M ^--b
22213
S3SS
srtQst; 3">s*S
23SI
-----
SS9
£8883-
8 5»c9«
a '--?=:
~s
e-r-r--
£S?55S
i.-----
§8s^s
Hci^eld c4o4o4o4^
.2p: = -<-:
cic.ciri-i
aasss sss^?.
SefefolS '.kk'H
;,r,n£2
cicicicici
22<£^2
eieioioioi
sgfesja
£^-3^
oi-i-2-
-p;;
8 ,£i£ ^USJS
Lc SSSSS SE5^ 822='= 33353 jgnjj -2.-* •ein-rnn
72^1
rtnoici^i
3^5 = 2
c.^ioiejw ci^lo.^ci
££::i gSa8lS
-Jf£ 5SriSS SSa33 aS«3S ^icic-icici
|P SiS3§
"
*tt
fiOfcBC
iS::v=
=2235 £253?;
sSsSa 33323 3333*
22222 SSSSS
— |a
Z
fiSS*
= KU5cf,V:
<& >r>'T'Tn
^2jx2?.
^-^2C
nnnciri
?iS^«2 ggSIW
?5V!:r!
cieieicici
SS8tSa
cici<Nc4ci
,-2«^'22
moimmm
=?iU'a =
cicicin —
£^:-?;
?22=s 53353 s?|S2i *,<>—- !:r:,=-'i3 SSfeRS?
-
ses assays 333oid ^ci^ad (CiO'T'Tco ortrtHrt <*>ei*jei©i oioicici«s e4eieie4o« oitsoj^ici
2358
9
-'2-2 jgSSSS r-S^-r, 2'5c-^^
<:£<22 ggSPJS RXM9 SfcSgjg 8§858]
wdoiold ^d — y ^:io-r — — H«co«« cocoeiotei
75r-,2r-
-Ncicicici
<'i'i22
ciciricici
fe*88|S
oleieleiot
235* 55353 3ole<ofoJ eiefeielei
3"
_u.:r ua^|:p- SSSSS 3859$ 8*2283 ^saja (58892 ssssr, aagga sfessss pess^ s«=22
-iir^r, "OW'T-r-f cortrtopj rjcoortoi cieieicici eiciwoioi MelalelM
$3538 §3355 SSci*i*i S22^
l
5*893 8?i££'5 r^'^2
83*88 SSSSg ggttg ems* aosi'TSi
c2,°8iS?a
<0»0-r-r-r ««««« ««««« o©«oi<m<^
';V5,'-r-
<nokninoJ <n<nci<n
- -
— vol-
s£ — —
c - ;5r^-
(d WjM) W) 10 -r -r -r -r
u'.'r-r-frt
— — — — — -r
c^c-;«e*ei
-r ————
cicicicj-
—————
-cl'/
— — 0«
-r
5s2l mz mm m% 'mm mm mm
-cco-r «St^o« £-222 22222 93835 51188 888§>
-wrt-r wici^o =-2J2Z 12£L:£2 isSSS 22?^
JOJBUIUIOUJQ 04} JOj UIOJXMJ j JO
— —
296 - App^d«LP.rc.nt.Q.Po.nt$oHhef0.stnbution
=52* - - . mm oioieicici
32325 ci—
• ---
S £3 S
= 2*2 3! i ~ in iff -r mm aaaaa SSS Advanced Isolation technology, 207-208
Aluminum, 144
(CBE).
CCD.
vee Chemical beam epitaxy (CBE)
see Charge-coupled device (CCD)
etching. HH
83333
———
cici
C-chart. see Defec-t chart (C-chart
metallization. 169-173 CD. tee Critical dimension (CD)
Ammonium fluoride (NH«F), 87 Cell projection. 75
Amorphous silic-a. 43 Central processing unit (CPU). 203
8.
- ** « Analysis of variance (ANOVA) CF. see Correction factor (CF)
table. 245-246 Chanstop. tee p+ channel stop
= s=? 33333 £3333
CtcjclCICJ ci ci ci — — technique. 243-24-1 Charge-coupled device (CCD), 5
~ jcJCKN'M
.- r c.
Annealing Chemical-amplified resist (CAB). 70
— B «« — boron and phosphorus. 134 Chemical beam epitaxy (CBE). 152
225=
ft$S*S &33SS
««««« S2SS ssgsg aaass rapid thermal, 135-136 Chemical etchants. 85
— « ANOVA. see Analysis of variance (ANOVA) Chemical etching. 92
ci — — f; w /* ^ -l-i-
4J ; — .
x
i
Anisotropic etch profiles. 92 Chemical mechanical polishing (CMP),
cj rt ci oi c» cicicjcic) ci ci ci ci ci 8.
APCVD. Atmospheric pressure CVD 100. 173-175
(APCVD) Chemical vapor deposition (CVD). 14. 50,
I Cl CI <N CJ Area defect. 34 88. 145. 16S
gifts Aspect ratio-dependent etching. 98 for gallium arsenide. 147
33S23 rtrtcicl — sgsss r. 7 X-- ATE, see Automated test equipment (ATE) metalorganic. 147-148
Jo cirte*5C5« cicieici-4
Atmospheric pressure CVD (APCVD), 145 for silicon, 145-147
237
Attributes. silicon oxides and dioxide, 156
72225 83333 SJ222S Automated test equipment (ATE). 228 TiN. 169
c-jcicicici
= 1
- J 4-1."
Automobile industry. 1 tungsten, 169
Chip scale package (CSP). 232
£272'- rtcicici -i
C J" - - Ball grid array (BCA). 231 Clean room, importance for lithographv.
Barium strontium tttanate (BST), 164 60-62
=* 'i ? $3sss = 537!: BGA. see Ball grid array (BCA) Close proximity printing, 62
l-5 -r — -r
- }C0»<9< rtrtcici-i
BiCMOS technology. 210-211 Clustered plasma processing. 97
!£U2U5
i
— C — i
-
33333
Bipolar technology. 1S8-195 CMOS see Complementary MOSFET
aoet-ttiA 4-1 Ift
33353 Bipolar transistor. 5. 189 CMOS)
$5&2 Blanket etches. 85 CMP. see Chemical mechanical polishing
C -TCI 33323 Boron, conventional annealing of, 134-135 (CMP)
bae'r-sote i- irt t -r -r-r--r- Bow. 32 Cobalt silicide, 176
Bridgman technique, 6. 30-31 Comb-meander-comb structure. 22S
8£=?53 {{:53Sj
— -r- - - BST see Barium strontium titanate (BST) Complementary MOSFET (CMOS 8
i"5
Buffered HF solution (BHF). 88 196
— — r: 4- -j:
Buffered oxide etch (BOE). see Buffered technology, 203-205
= '- =5 33385 $55833 t« r? —a i
-
<>f
capacitor. 1S5-1S7
G-hne, 65 Ughth doped drain I.DD MOSFKT 138 Metal, films 1-1 il 1 1 1
inductor, 187-188
Grain boundary. 34 I in. ..1 rate constant. 46-17 Metallization, 14. 167-177. LM
monolitluc. 7
Cunti du>de v,r Transferred-electron Line defect. 34 M.tal-nitride-oxi(l.-s,Mnicoii(hKlor
pattern transfer. 70-71
duxle (TED) Lithographic, galvanofonnung. abforiiiuug (MNOS), 201
resistor. 184-185
(LICA). 2 15-2 IS Metalorganic chemical sapor deposition
[ntevconnections, 14
HDP mv High-density plasma tHDP) Lithographic methods MO( VD). 8. 147-148
Interconnect metal etching. 99-101
Heteroepitaxy. 144. 152 comparison SO SIof. Metalorganic moleciilai beam epitaxy
Interface delects. 1.54
Hrterojunction bipolar transistor. 2 next-generation, 73-80 MOMBE), 152
4 [nteriayer dielectric (ILD), 173 Lithography process.
Heterostructure laser. 6 5. Metal-oxide-seiiiicondiu tor lield-i lt.-i 1
M EMS)
distribution. 2-5— 1 26
HMDS see HexamethxI-disila/ane 1
Low-dieleetric-coiistant materials. 162-164 212-214
HMDS) stopping. 127-130 Lower control limit (LCL). 237 technology, 212-214
Homoepitaxv. 144. 152 Ion beam Low pressure chemical vapor deposition Micromachining. surface and bulk. 215
HP. S6 lithography. 79 -SO (LPCVD).
Hvdrolluoric acid 1
101. 145. 155, 162 Minimum dexice dimension, 259
Hypothesis test. 243 sputtering. 167 LPCVD. see Low pressure chemical vapor Minimum feature length, see Minimum
Ion implantation. 70 deposition (LPCVD) dexice dimension
IC-CIM. see Computer-integrated damage and annealing. 131-136 LSI. see Large-scale integration (LSI) MMICs. see Monolithic microwave
manufacturing of integrated and diffusion. 14 integrated circuits MMICs)
intuits (IC-CIM) range of. 125-131 Magnetically enhanced reactive ion etching MNOS s.v Mctal-nitridi-oxide-
IC man u Picturing technology. 80-81 related processes. 136-140 (MERIE),90 semiconductor (MNOS)
ICP source, see Inductively coup!e<l simulation. 140-141 Magnetron sputtering. 168 Mobile ionic charges. 54
plasma (ICP) source Isolation technology, advanced. 207-208 Main effect. 247 MOCVD. see Mctalorganic chemical vapor
computer-integrated, 256-257 Lattice disorder. 131 Medium scale integration (MSI). 184 Monte Carlo simulation, 254
electrical testing, 227-228 Lattice- matched epitaxy, 152-153 Memory devices, 199-203 MOSFE T. see Metal-oxide-semiconductor
packaging. 228-236 LCL. see Lower control limit (LCD MEMS, see Microelectromechanical field-effect transistor (MOSFET
MSI Medium scale integration MSI
statistical experimentation design, Lead zirconium titanate (PZT). 164 systems (MEMS) see i
242-249 Level 1 packaging. 232 MERIE. see Magnetically enhanced MIT see Mean time to failure (MTF)
statistical process control. 237-241 Liftoff technique. 70-71 reactive ion etching (MERIE) Multiple implantation and masking.
yield. 250-255 L1GA. see Lithographic, galvanofonnung. MESFET. see Metal semiconductor field- 136-138
Integrated circuits (ICs). 182 (MESFET) Murphy's yield integral. 252-254
1. 7. abformung(LIGA) efTed transistor
302 » tote*
Index •* 303
41, 196. jpchtane] MOSPET (PMGS), 196, i^T. Polycrystallme silicon (EGS). 18. 41. 144.
n-dunnr! MOSFfcT NMOS), |
S.
Reactive reactor technology. 93
203-205, 208 see also Polysilicou
197. 203-205 Reacrtor. 93
V-.'ive photoresist. (>V(W 75 p* channel stop. 191-192 Poly-glycidvl methacrvlate-eo-ethvl-
Rectifying metal-semiconductor barriers
"> PCMs. see Process control monitors acrylate (COP). 75
Neutral vacancy. 1 1
144
25
(PCMs) Polymers. 68. 75
Neutron irradiation. Redistribution diffusion, see Drive-in
PECVD. see Plasma-enhanced chemical
to-ynw»to Bthognphk methods.
vapor deposition (PECVD)
Pory-rnethyl methacrylatQ |
PMMA), 75. 79 diffusion
73-81 I'oKsilimn. 144 Refilled trench. 205
PGA. see Pin grid array (PGA) capacitor. 201
WWc*dd(HN(V.87 Registration. 62
P-glass flow process. 160. 196
N.uKxmfoniiAl step coverage. 159-160 deposition, 165-167 Resistance-heated oxidation furnace. 41
Nonvolatile memory device. 201-202 Phase, 26-27 electrode. 201 Resistivity. 113, 114
semiconductor memory PhttSe diagram. 27 etching, 98-99
Nonvolatile Resistors. 185
-NVSMI. 5.203 Phase-shifting mask (FSM), ~-l
silicon nitride and. SS Resolution
bipolar transistor. 180
Phosphorus 75
Hp a Positive photoresist. 67-6S, defined. 62
conventional annealing of. 134-135 Power limitations. 261-262
n» poKsjlictMi. 194 enhancement techniques, 72
diffusion profiles. 117, 1 IS POwer supply voltage. 259-260
n-tvpe dopants. 106 Resonant tunneling diode (RTD). 5
\\s\l «v Nomolatilf st-micondllCtar Photolithography p* polvsilicon, 194 Retrograde well, see Twin well
memory (NYSM> defined, 60 gate. 20S RIE. see Reactive ion etching RIE) I
quality. 53-54 PMM \ RAM. tee Random access memory (RAM materials, 2
thickness characterization. 54 PMOS. see ^-channel MOSFET iPMOS) Random access memory (RAM). 199 process technologies. 5-8
trapped charges. 54 p-n junction. 7. 14 Range (R). 125 Semiconductor Equipment and Materials
Point defect, 34 Rapid thermal annealing (RTA). 134, Institute (SEMIX 32
Packaging, integrated circuit Poisson (Ustrihution. 23S 135-136 Separation lis implanted oxygen (SIMOX
levels of. 228-230 Poisson yield model, 251-252 Raster scan system, 74-75 140. 193
types of. 230-232 Poly 1. see p* rx)l>*ihcon Reactive ion beam etching. 90 Shadow printing. 62-63. 78
Parabolic rate constant. 46. 47 Poly 2. see n + polvsilicon Reactix.- ion etching (WE), 90. 94-95, 173 Shallow trench isolation. 207
Parametric yield. 250, 254-255 Polv-butene-1 sulfone (PBS). 75 Reactive plasma etclung Sheet resistance. 113-114
Pattern transfer. Integrated circuit. 70-71 Polycide gate etching. 98-99 applications. 97-101 Shewhart control charts, tee ( Sontrol charts
PBS. m Polv-butene-1 sulfone (PBS) Polycide process. 175 techniques. 93-94 Shmoo plot, see Two-dimensional plot
Indox « 305
Sfea. «*v Stbmn dioxide »SK>.) Sputtering. 16S Titanium nitride (TIN), chemical
vapor Ultralhiiinude. 2(A
SAodr 144 SH \M we Statu random access Humors deposition (CVD), 100
Upper oontrol (Ucu.
tuntuboo. 261 MUM rrans|«Tred-ele<-tron diode (TED),
5
limit 2.37