SABC 1610 LM (Microcontroller)

Da ta S h e e t , V 2 .0 , J a n .
2 0 0 1
C161K
C161O
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r s t o p t h i n k i n g .
Edition 2001-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
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Da ta S h e e t , V 2 .0 , J a n . 2 0 0 1
C161K
C161O
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r s t o p t h i n k i n g .
C161K/O
Revision History: 2001-01 V2.0

Previous Version: 03.97 (Preliminary)
09.96 (Advance Information)
Page Subjects (major changes since last revision)
All Converted to Infineon layout
All C161V removed
2 Ordering Codes and Cross-Reference replaced with Derivative Synopsis
5-8 Open drain functionality described for P2, P3, P6
8 Bidirectional reset introduced
19 Figure updated
28, 29 Revised description of Absolute Max. Ratings and Operating Conditions
32 - 56 Specifications for reduced supply voltage introduced
35 Reduced power consumption
36, 37 Clock Generation Modes added
38, 39 Description of External Clock Drive improved
41 - 56 Standard 25-MHz timing introduced (timing granularity 2 ns)
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16-Bit Single-Chip Microcontroller C161K/O
C166 Family
C161K/O
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via prescaler or via direct clock input
• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM) on C161O,
1 KByte IRAM on C161K
• On-Chip Peripheral Modules
– Two Multi-Functional General Purpose Timer Units with 5 Timers on C161O,
one Timer Unit with 3 Timers on C161K
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
• Up to 4 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Four Programmable Chip-Select Signals on C161O,
two Chip-Select Signals on C161K
• Idle and Power Down Modes
• Programmable Watchdog Timer
• Up to 63 General Purpose I/O Lines
• Power Supply: the C161K/O can operate from a 5 V or a 3 V power supply
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 80-Pin MQFP Package (0.65 mm pitch)
Data Sheet 1 V2.0, 2001-01

C161K
C161O
This document describes several derivatives of the C161 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
Table 1 C161K/O Derivative Synopsis

Derivative1) Max. Oper. Operating IRAM Nr of Ext. CAP
Frequency Voltage [KB] CSs Intr. IN
SAF-C161K-LM 20 MHz 4.5 to 5.5 V 1 2 4 ---
SAB-C161K-LM 20 MHz 4.5 to 5.5 V 1 2 4 ---
SAF-C161K-L25M 25 MHz 4.5 to 5.5 V 1 2 4 ---
SAB-C161K-L25M 25 MHz 4.5 to 5.5 V 1 2 4 ---
SAF-C161K-LM3V 20 MHz 3.0 to 3.6 V 1 2 4 ---
SAB-C161K-LM3V 20 MHz 3.0 to 3.6 V 1 2 4 ---
SAF-C161O-LM 20 MHz 4.5 to 5.5 V 2 4 7 Yes
SAB-C161O-LM 20 MHz 4.5 to 5.5 V 2 4 7 Yes
SAF-C161O-L25M 25 MHz 4.5 to 5.5 V 2 4 7 Yes
SAB-C161O-L25M 25 MHz 4.5 to 5.5 V 2 4 7 Yes
SAF-C161O-LM3V 20 MHz 3.0 to 3.6 V 2 4 7 Yes
SAB-C161O-LM3V 20 MHz 3.0 to 3.6 V 2 4 7 Yes
1)
This Data Sheet is valid for devices starting with and including design step HA.
For simplicity all versions are referred to by the term C161K/O throughout this document.
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the C161K/O please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet 2 V2.0, 2001-01

C161K
C161O
Introduction
The C161K/O is a derivative of the Infineon C166 Family of full featured single-chip
CMOS microcontrollers. It combines high CPU performance (up to 12.5 million
instructions per second) with peripheral functionality and enhanced IO-capabilities. The
C161K/O is especially suited for cost sensitive applications.
VDD VSS
Port 0
XTAL1
16 Bit
XTAL2
RSTIN Port 1
16 Bit
RSTOUT
Port 2
NMI 7 Bit
EA
C161
Port 3
12 Bit
ALE
RD Port 4
6 Bit
WR/WRL
Port 5 Port 6
2 Bit 4 Bit
MCL02949
Figure 1 Logic Symbol
Data Sheet 3 V2.0, 2001-01

C161K
C161O
Pin Configuration MQFP Package

(top view)
P5.15/T2EUD
P5.14/T4EUD
P2.15/EX7IN
P2.14/EX6IN
P2.13/EX5IN
P2.12/EX4IN
P2.11/EX3IN
P2.10/EX2IN
P2.9/EX1IN
P1H.7/A15
P1H.6/A14
P6.3/CS3
P6.2/CS2
P6.1/CS1
P6.0/CS0
RSTOUT
RSTIN
NMI
VDD
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VSS 1 60 P1H.5/A13
XTAL1 2 59 P1H.4/A12
XTAL2 3 58 P1H.3/A11
VDD 4 57 P1H.2/A10
P3.2/CAPIN 5 56 P1H.1/A9
P3.3/T3OUT 6 55 P1H.0/A8
P3.4/T3EUD 7 54 P1L.7/A7
P3.5/T4IN 8 53 P1L.6/A6
P3.6/T3IN 9 52 P1L.5/A5
P3.7/T2IN 10 51 P1L.4/A4
P3.8/MRST 11
C161K/O 50 P1L.3/A3
P3.9/MTSR 12 49 P1L.2/A2
P3.10/TxD0 13 48 P1L.1/A1
P3.11/RxD0 14 47 P1L.0/A0
P3.12/BHE/WRH 15 46 P0H.7/AD15
P3.13/SCLK 16 45 P0H.6/AD14
P4.0/A16 17 44 P0H.5/AD13
P4.1/A17 18 43 P0H.4/AD12
P4.2/A18 19 42 P0H.3/AD11
P4.3/A19 20 41 P0H.2/AD10
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
VSS
VDD
VDD
EA
RD
ALE
P4.4/A20
P4.5/A21
WR/WRL
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
P0H.0/AD8
P0H.1/AD9
MCP04858
Figure 2
Note: The marked signals are only available in the C161O.
Please also refer to the detailed description below (shaded lines).
Data Sheet 4 V2.0, 2001-01

C161K
C161O
Table 2 Pin Definitions and Functions

Symbol Pin Input Function
Num Outp.
XTAL1 2 I XTAL1: Input to the oscillator amplifier and input
to the internal clock generator
XTAL2 3 O XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
P3 IO Port 3 is a 12-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The Port 3 pins serve for following
alternate functions:
P3.2 5 I CAPIN GPT2 Register CAPREL Capture Input
This alternate input is only available in the C161O.
P3.3 6 O T3OUT GPT1 Timer T3 Toggle Latch Output
P3.4 7 I T3EUD GPT1 Timer T3 External Up/Down Control Input
P3.5 8 I T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp
P3.6 9 I T3IN GPT1 Timer T3 Count/Gate Input
P3.7 10 I T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp
P3.8 11 I/O MRST SSC Master-Receive/Slave-Transmit Inp./Outp.
P3.9 12 I/O MTSR SSC Master-Transmit/Slave-Receive Outp./Inp.
P3.10 13 O TxD0 ASC0 Clock/Data Output (Async./Sync.)
P3.11 14 I/O RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
P3.12 15 O BHE External Memory High Byte Enable Signal,
O WRH External Memory High Byte Write Strobe
P3.13 16 I/O SCLK SSC Master Clock Output / Slave Clock Input
impedance state. Port 4 can be used to output the segment
address lines:
P4.0 17 O A16 Least Significant Segment Address Line
P4.1 18 O A17 Segment Address Line
P4.5 24 O A21 Most Significant Segment Address Line
Data Sheet 5 V2.0, 2001-01

C161K
C161O
Table 2 Pin Definitions and Functions (cont’d)

Num Outp.
RD 25 O External Memory Read Strobe. RD is activated for every
external instruction or data read access.
WR/ 26 O External Memory Write Strobe. In WR-mode this pin is
WRL activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a 16-
bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.
ALE 27 O Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
EA 28 I External Access Enable pin. A low level at this pin during and
after Reset forces the C161K/O to begin instruction
execution out of external memory. A high level forces
execution out of the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
PORT0 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L
P0L.0-7 29-36 and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
P0H.0-7 39-46 is put into high-impedance state. In case of an external bus
configuration, PORT0 serves as the address (A) and
address/data (AD) bus in multiplexed bus modes and as the
data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 – D7
P0H.0 – P0H.7: I/O D8 – D15
Multiplexed bus modes:
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7
P0H.0 – P0H.7: A8 – A15 AD8 – AD15
PORT1 IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L
P1L.0-7 47-54 and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
P1H.0-7 55-62 is put into high-impedance state. PORT1 is used as the 16-
bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
Data Sheet 6 V2.0, 2001-01

C161K
C161O

Num Outp.
RSTIN 65 I/O Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C161K/O.
An internal pullup resistor permits power-on reset using only
a capacitor connected to VSS. A spike filter suppresses input
pulses < 10 ns. Input pulses >100 ns safely pass the filter.
The minimum duration for a safe recognition should be
100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
Note: To let the reset configuration of PORT0 settle a reset
duration of ca. 1 ms is recommended.
RST 66 O Internal Reset Indication Output. This pin is set to a low level
OUT when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI 67 I Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C161K/O to go into
power down mode. If NMI is high, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
P6.0 68 O CS0 Chip Select 0 Output
These chip select outputs are only available in the C161O.
Data Sheet 7 V2.0, 2001-01

C161K
C161O

Num Outp.
pull or open drain drivers. The following Port 2 pins serve for
alternate functions:
P2.9 72 I EX1IN Fast External Interrupt 1 Input
76 I EX5IN Fast External Interrupt 5 Input
These external interrupts are only available in the C161O.
P5 I Port 5 is a 2-bit input-only port with Schmitt-Trigger char. The
pins of Port 5 also serve as timer inputs:
VDD 4, 22, – Digital Supply Voltage:
37, 64 + 5 V or + 3 V during normal operation and idle mode.
≥ 2.5 V during power down mode.
VSS 1, 21, – Digital Ground.
38, 63
Note: The following behavioral differences must be observed when the bidirectional
reset is active:
• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.
• The reset indication flags always indicate a long hardware reset.
• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap
loader may be activated when P0L.4 is low.
• Pin RSTIN may only be connected to external reset devices with an open drain output
driver.
• A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet 8 V2.0, 2001-01

C161K
C161O
Functional Description
The architecture of the C161K/O combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C161K/O.
Note: All time specifications refer to a CPU clock of 25 MHz
(see definition in the AC Characteristics section).
ProgMem C166-Core IRAM

16
Dual Port
Data
32 16 Internal
Internal Instr. / Data CPU Data RAM
ROM 1/2 Kbyte
Area
16
PEC Osc XTAL

External Instr. / Data
Interrupt Controller 16-Level

Priority WDT
16
Interrupt Bus
On-Chip XBUS (16-Bit Demux)
Peripheral Data Bus

16
ASC0 SSC GPT1 GPT2

(USART) (SPI)
T2
8 EBC T3
Port 4
T4
XBUS Control 8
Port 2
External Bus T5
8 Control BRGen BRGen T6
Port 6
Port 0 Port 1 Port 3 Port 5
16 16 15 6
MCB04323_1ko
Figure 3 Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).
Data Sheet 9 V2.0, 2001-01

C161K
C161O
Memory Organization
The memory space of the C161K/O is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 MBytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.
The C161K/O is prepared to incorporate on-chip program memory (not in the ROM-less
derivatives, of course) for code or constant data. The internal ROM area can be mapped
either to segment 0 or segment 1.
On-chip Internal RAM (IRAM) is provided (1 KByte in the C161K, 2 KBytes in the
C161O) as a storage for user defined variables, for the system stack, general purpose
register banks and even for code. A register bank can consist of up to 16 wordwide (R0
to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers
(GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the
microcontroller.
Data Sheet 10 V2.0, 2001-01

C161K
C161O
External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:
– 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 2 or 4 external CS signals (1 or 3 windows plus default, depending on the device)
can be generated in order to save external glue logic. The C161K/O offers the possibility
to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is
switched off and the CS signals are directly generated from the address. The unlatched
CS mode is enabled by setting CSCFG (SYSCON.6).
For applications which require less than 4 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an
address space of 4 MBytes is used.
Data Sheet 11 V2.0, 2001-01

C161K
C161O
Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161K/O’s instructions can be
executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16
bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
CPU 16
Internal
SP MDH RAM
STKOV MDL R15
STKUN
Exec. Unit Mul/Div-HW
Instr. Ptr. Bit-Mask Gen General
R15
Instr. Reg.
32 ALU Purpose
4-Stage (16-bit)
ROM Pipeline Registers
Barrel - Shifter
PSW R0
SYSCON Context Ptr.
BUSCON 0 16
R0
BUSCON 1 ADDRSEL 1
BUSCON 2 ADDRSEL 2
BUSCON 3 ADDRSEL 3
BUSCON 4 ADDRSEL 4
Data Page Ptr. Code Seg. Ptr.
MCB02147
Figure 4 CPU Block Diagram
Data Sheet 12 V2.0, 2001-01

C161K
C161O
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C161K/O instruction set which
includes the following instruction classes:
– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet 13 V2.0, 2001-01

C161K
C161O
Interrupt System
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C161K/O is capable of reacting very fast to the
occurrence of non-deterministic events.
The architecture of the C161K/O supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C161K/O has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 3 shows all of the possible C161K/O interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
Data Sheet 14 V2.0, 2001-01

C161K
C161O
Table 3 C161K/O Interrupt Nodes

Source of Interrupt or Request Enable Interrupt Vector Trap
PEC Service Request Flag Flag Vector Location Number
External Interrupt 1 CC9IR CC9IE CC9INT 00’0064H 19H
External Interrupt 2 CC10IR CC10IE CC10INT 00’0068H 1AH
External Interrupt 3 CC11IR CC11IE CC11INT 00’006CH 1BH
External Interrupt 4 CC12IR CC12IE CC12INT 00’0070H 1CH
External Interrupt 5 CC13IR CC13IE CC13INT 00’0074H 1DH
External Interrupt 6 CC14IR CC14IE CC14INT 00’0078H 1EH
External Interrupt 7 CC15IR CC15IE CC15INT 00’007CH 1FH
GPT1 Timer 2 T2IR T2IE T2INT 00’0088H 22H
GPT1 Timer 3 T3IR T3IE T3INT 00’008CH 23H
GPT2 CAPREL Reg. CRIR CRIE CRINT 00’009CH 27H
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8H 2AH
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011CH 47H
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACH 2BH
ASC0 Error S0EIR S0EIE S0EINT 00’00B0H 2CH
SSC Transmit SCTIR SCTIE SCTINT 00’00B4H 2DH
SSC Receive SCRIR SCRIE SCRINT 00’00B8H 2EH
SSC Error SCEIR SCEIE SCEINT 00’00BCH 2FH
Note: The shaded interrupt nodes are only available in the C161O, not in the C161K.
Data Sheet 15 V2.0, 2001-01

C161K
C161O
The C161K/O also provides an excellent mechanism to identify and to process

exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 4 Hardware Trap Summary

Exception Condition Trap Trap Vector Trap Trap
Flag Vector Location Number Priority
Reset Functions: –
– Hardware Reset RESET 00’0000H 00H III
– Software Reset RESET 00’0000H 00H III
– W-dog Timer Overflow RESET 00’0000H 00H III
Class A Hardware Traps:
– Non-Maskable Interrupt NMI NMITRAP 00’0008H 02H II
– Stack Overflow STKOF STOTRAP 00’0010H 04H II
– Stack Underflow STKUF STUTRAP 00’0018H 06H II
Class B Hardware Traps:
– Undefined Opcode UNDOPC BTRAP 00’0028H 0AH I
– Protected Instruction PRTFLT BTRAP 00’0028H 0AH I
Fault
– Illegal Word Operand ILLOPA BTRAP 00’0028H 0AH I
Access
– Illegal Instruction ILLINA BTRAP 00’0028H 0AH I
Access
– Illegal External Bus ILLBUS BTRAP 00’0028H 0AH I
Access
Reserved – – [2CH – [0BH – –
3CH] 0FH]
Software Traps – – Any Any Current
– TRAP Instruction [00’0000H – [00H – CPU
00’01FCH] 7FH] Priority
in steps
of 4H
Data Sheet 16 V2.0, 2001-01

C161K
C161O
General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-
flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components, or may be used internally to clock timers
T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet 17 V2.0, 2001-01

C161K
C161O
T2EUD U/D
Interrupt
fCPU 2n : 1 T2 GPT1 Timer T2
Request
Mode
T2IN Control
Reload
Capture
Interrupt
fCPU n
2 :1 Request
Toggle FF
T3
T3IN Mode GPT1 Timer T3 T3OTL T3OUT
Control
U/D
T3EUD Other
Timers
Capture
Reload
T4IN T4
Mode
Control Interrupt
fCPU 2n : 1 GPT1 Timer T4
Request
T4EUD U/D
MCT02141
n = 3 … 10
Figure 5 Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock. The count direction (up/down) for each timer is programmable by software.
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5. The overflows/underflows of timer
T6 can cause a reload from the CAPREL register. The CAPREL register may capture
the contents of timer T5 based on an external signal transition on the corresponding port
pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This
allows the C161K/O to measure absolute time differences or to perform pulse
multiplication without software overhead.
Data Sheet 18 V2.0, 2001-01

C161K
C161O
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
Note: Block GPT2 is only available in the C161O, not in the C161K.
fCPU 2n : 1
T5
Mode U/D
Control
Interrupt
GPT2 Timer T5
Request
Clear
Capture
T3
Interrupt
MUX
Request
CAPIN
GPT2 CAPREL
CT3
Interrupt
Request
GPT2 Timer T6 T6OTL T6OUT

T6
fCPU 2n : 1 Mode U/D
Control Other
Timers
MCB02938
n=2…9
Figure 6 Block Diagram of GPT2
Data Sheet 19 V2.0, 2001-01

C161K
C161O
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 781 kBaud and
half-duplex synchronous communication at up to 3.1 MBaud (@ 25 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 6.25 MBaud
(@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception, and error handling three
separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet 20 V2.0, 2001-01

C161K
C161O
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value
(stored in WDTREL) in order to allow further variation of the monitored time interval.
Each time it is serviced by the application software, the high byte of the Watchdog Timer
is reloaded. Thus, time intervals between 20 µs and 336 ms can be monitored
(@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).
Parallel Ports
The C161K/O provides up to 63 I/O lines which are organized into six input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of three I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A21/19/17 … A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.
Port 6 provides optional chip select signals.
Port 3 includes alternate functions of timers, serial interfaces, and the optional bus
control signal BHE/WRH.
Port 5 is used for timer control signals.
Data Sheet 21 V2.0, 2001-01

C161K
C161O
Instruction Set Summary

Table 5 lists the instructions of the C161K/O in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 5 Instruction Set Summary

Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2/4
ADDC(B) Add word (byte) operands with Carry 2/4
SUB(B) Subtract word (byte) operands 2/4
SUBC(B) Subtract word (byte) operands with Carry 2/4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2/4
OR(B) Bitwise OR, (word/byte operands) 2/4
XOR(B) Bitwise XOR, (word/byte operands) 2/4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR, AND/OR/XOR direct bit with direct bit 4
BXOR
BCMP Compare direct bit to direct bit 4
BFLDH/L Bitwise modify masked high/low byte of bit-addressable 4
direct word memory with immediate data
CMP(B) Compare word (byte) operands 2/4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2/4
PRIOR Determine number of shift cycles to normalize direct 2
word GPR and store result in direct word GPR
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
Data Sheet 22 V2.0, 2001-01

C161K
C161O
Table 5 Instruction Set Summary (cont’d)

Mnemonic Description Bytes
MOV(B) Move word (byte) data 2/4
MOVBS Move byte operand to word operand with sign extension 2/4
MOVBZ Move byte operand to word operand. with zero extension 2/4
JMPA, JMPI, Jump absolute/indirect/relative if condition is met 4
JMPR
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI, Call absolute/indirect/relative subroutine if condition is met 4
CALLR
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call 4
absolute subroutine
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and update 4
register with word operand
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct 2
word register from system stack
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2/4
EXTS(R) Begin EXTended Segment (and Register) sequence 2/4
NOP Null operation 2
Data Sheet 23 V2.0, 2001-01

C161K
C161O
Special Function Registers Overview

The following table lists all SFRs which are implemented in the C161K/O in alphabetical
order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column
“Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Note: The shaded registers are only available in the C161O, not in the C161K.
Table 6 C161K/O Registers, Ordered by Name

Name Physical 8-Bit Description Reset
Address Addr. Value
ADDRSEL1 FE18H 0CH Address Select Register 1 0000H
ADDRSEL2 FE1AH 0DH Address Select Register 2 0000H
ADDRSEL3 FE1CH 0EH Address Select Register 3 0000H
ADDRSEL4 FE1EH 0FH Address Select Register 4 0000H
BUSCON0 b FF0CH 86H Bus Configuration Register 0 0XX0H
BUSCON1 b FF14H 8AH Bus Configuration Register 1 0000H
BUSCON2 b FF16H 8BH Bus Configuration Register 2 0000H
BUSCON3 b FF18H 8CH Bus Configuration Register 3 0000H
BUSCON4 b FF1AH 8DH Bus Configuration Register 4 0000H
CAPREL FE4AH 25H GPT2 Capture/Reload Register 0000H
CC10IC b FF8CH C6H EX2IN Interrupt Control Register 0000H
CC11IC b FF8EH C7H EX3IN Interrupt Control Register 0000H
CC12IC b FF90H C8H EX4IN Interrupt Control Register 0000H
CC13IC b FF92H C9H EX5IN Interrupt Control Register 0000H
CC14IC b FF94H CAH EX6IN Interrupt Control Register 0000H
CC15IC b FF96H CBH EX7IN Interrupt Control Register 0000H
CC9IC b FF8AH C5H EX1IN Interrupt Control Register 0000H
CP FE10H 08H CPU Context Pointer Register FC00H
CRIC b FF6AH B5H GPT2 CAPREL Interrupt Ctrl. Reg. 0000H
CSP FE08H 04H CPU Code Seg. Pointer Reg. (read only) 0000H
Data Sheet 24 V2.0, 2001-01

C161K
C161O
Table 6 C161K/O Registers, Ordered by Name (cont’d)

Address Addr. Value
DP0H b F102H E 81H P0H Direction Control Register 00H
DP0L b F100H E 80H P0L Direction Control Register 00H
DP1H b F106H E 83H P1H Direction Control Register 00H
DP1L b F104H E 82H P1L Direction Control Register 00H
DP2 b FFC2H E1H Port 2 Direction Control Register 0000H
DP3 b FFC6H E3H Port 3 Direction Control Register 0000H
DP4 b FFCAH E5H Port 4 Direction Control Register 00H
DP6 b FFCEH E7H Port 6 Direction Control Register 00H
DPP0 FE00H 00H CPU Data Page Pointer 0 Reg. (10 bits) 0000H
EXICON b F1C0H E E0H External Interrupt Control Register 0000H
IDCHIP F07CH E 3EH Identifier 05XXH
IDMANUF F07EH E 3FH Identifier 1820H
IDMEM F07AH E 3DH Identifier 0000H
IDMEM2 F076H E 3BH Identifier 0000H
IDPROG F078H E 3CH Identifier 0000H
MDC b FF0EH 87H CPU Multiply Divide Control Register 0000H
MDH FE0CH 06H CPU Multiply Divide Reg. – High Word 0000H
MDL FE0EH 07H CPU Multiply Divide Reg. – Low Word 0000H
ODP2 b F1C2H E E1H Port 2 Open Drain Control Register 0000H
ODP3 b F1C6H E E3H Port 3 Open Drain Control Register 0000H
ODP6 b F1CEH E E7H Port 6 Open Drain Control Register 00H
ONES b FF1EH 8FH Constant Value 1’s Register (read only) FFFFH
P0H b FF02H 81H Port 0 High Reg. (Upper half of PORT0) 00H
P0L b FF00H 80H Port 0 Low Reg. (Lower half of PORT0) 00H
P1H b FF06H 83H Port 1 High Reg. (Upper half of PORT1) 00H
P1L b FF04H 82H Port 1 Low Reg.(Lower half of PORT1) 00H
P2 b FFC0H E0H Port 2 Register 0000H
Data Sheet 25 V2.0, 2001-01

C161K
C161O

Address Addr. Value
P3 b FFC4H E2H Port 3 Register 0000H
P4 b FFC8H E4H Port 4 Register (8 bits) 00H
P5 b FFA2H D1H Port 5 Register (read only) XXXXH
P6 b FFCCH E6H Port 6 Register (8 bits) 00H
PECC0 FEC0H 60H PEC Channel 0 Control Register 0000H
PECC5 FECAH 65H PEC Channel 5 Control Register 0000H
PECC6 FECCH 66H PEC Channel 6 Control Register 0000H
PECC7 FECEH 67H PEC Channel 7 Control Register 0000H
PSW b FF10H 88H CPU Program Status Word 0000H
RP0H b F108H E 84H System Startup Config. Reg. (Rd. only) XXH
S0BG FEB4H 5AH Serial Channel 0 Baud Rate Generator 0000H
Reload Register
S0CON b FFB0H D8H Serial Channel 0 Control Register 0000H
S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Ctrl. Reg 0000H
S0RBUF FEB2H 59H Serial Channel 0 Receive Buffer Reg. XXH
(read only)
S0RIC b FF6EH B7H Serial Channel 0 Receive Interrupt 0000H
Control Register
S0TBIC b F19CH E CEH Serial Channel 0 Transmit Buffer 0000H
Interrupt Control Register
S0TBUF FEB0H 58H Serial Channel 0 Transmit Buffer 00H
Register (write only)
S0TIC b FF6CH B6H Serial Channel 0 Transmit Interrupt 0000H
Control Register
SP FE12H 09H CPU System Stack Pointer Register FC00H
SSCBR F0B4H E 5AH SSC Baudrate Register 0000H
SSCCON b FFB2H D9H SSC Control Register 0000H
Data Sheet 26 V2.0, 2001-01

C161K
C161O

Address Addr. Value
SSCEIC b FF76H BBH SSC Error Interrupt Control Register 0000H
SSCRB F0B2H E 59H SSC Receive Buffer XXXXH
SSCRIC b FF74H BAH SSC Receive Interrupt Control Register 0000H
SSCTB F0B0H E 58H SSC Transmit Buffer 0000H
SSCTIC b FF72H B9H SSC Transmit Interrupt Control Register 0000H
STKOV FE14H 0AH CPU Stack Overflow Pointer Register FA00H
STKUN FE16H 0BH CPU Stack Underflow Pointer Register FC00H
1)
SYSCON b FF12H 89H CPU System Configuration Register 0XX0H
T2 FE40H 20H GPT1 Timer 2 Register 0000H
T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000H
T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000H
TFR b FFACH D6H Trap Flag Register 0000H
WDT FEAEH 57H Watchdog Timer Register (read only) 0000H
2)
WDTCON b FFAEH D7H Watchdog Timer Control Register 00XXH
ZEROS b FF1CH 8EH Constant Value 0’s Register (read only) 0000H
1)
The system configuration is selected during reset.
2) The reset value depends on the indicated reset source.
Data Sheet 27 V2.0, 2001-01

C161K
C161O
Absolute Maximum Ratings
Table 7 Absolute Maximum Rating Parameters

Parameter Symbol Limit Values Unit Notes
min. max.
Storage temperature TST -65 150 °C –
Junction temperature TJ -40 150 °C under bias
Voltage on VDD pins with VDD -0.5 6.5 V –
respect to ground (VSS)
Voltage on any pin with VIN -0.5 VDD + 0.5 V –
respect to ground (VSS)
Input current on any pin – -10 10 mA –
during overload condition
Absolute sum of all input – – |100| mA –
currents during overload
condition
Power dissipation PDISS – 1.5 W –
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet 28 V2.0, 2001-01

C161K
C161O
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C161K/O. All parameters specified in the following sections refer to
these operating conditions, unless otherwise noticed.
Table 8 Operating Condition Parameters

Parameter Symbol Limit Values Unit Notes
min. max.
Standard VDD 4.5 5.5 V Active mode,
digital supply voltage fCPUmax = 25 MHz
(5 V versions) 2.51) 5.5 V Power Down mode
Reduced VDD 3.0 3.6 V Active mode,
digital supply voltage fCPUmax = 20 MHz
(3 V versions) 2.51) 3.6 V Power Down mode
Digital ground voltage VSS 0 V Reference voltage
Overload current IOV – ±5 mA Per pin2)3)
Absolute sum of overload Σ|IOV| – 50 mA 3)
currents
External Load CL – 100 pF –
Capacitance
Ambient temperature TA 0 70 °C SAB-C161K/O …
-40 85 °C SAF-C161K/O …
-40 125 °C SAK-C161K/O …
1)
Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.
2)
Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
3)
Not 100% tested, guaranteed by design and characterization.
Data Sheet 29 V2.0, 2001-01

C161K
C161O
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C161K/
O and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C161K/O will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the C161K/O.
DC Characteristics (Standard Supply Voltage Range)

(Operating Conditions apply)1)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Input low voltage (TTL, VIL SR -0.5 0.2 VDD V –
all except XTAL1) - 0.1
Input low voltage XTAL1 VIL2 SR -0.5 0.3 VDD V –
Input high voltage (TTL, VIH SR 0.2 VDD VDD + V –
all except RSTIN and XTAL1) + 0.9 0.5
Input high voltage RSTIN VIH1 SR 0.6 VDD VDD + V –
(when operated as input) 0.5
Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD + V –
0.5
Output low voltage VOL CC – 0.45 V IOL = 2.4 mA
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT,
RSTIN2))
Output low voltage VOL1 CC – 0.45 V IOL = 1.6 mA
(all other outputs)
Output high voltage3) VOH CC 2.4 – V IOH = -2.4 mA
(PORT0, PORT1, Port 4, ALE, 0.9 VDD – V IOH = -0.5 mA
RD, WR, BHE, RSTOUT)
Output high voltage3) VOH1 CC 2.4 – V IOH = -1.6 mA
(all other outputs) 0.9 VDD – V IOH = -0.5 mA
Input leakage current (Port 5) IOZ1 CC – ±200 nA 0 V < VIN < VDD
Input leakage current (all other) IOZ2 CC – ±500 nA 0.45 V < VIN < VDD
RSTIN inactive current4) IRSTH5) – -10 µA VIN = VIH1
Data Sheet 30 V2.0, 2001-01

C161K
C161O
DC Characteristics (Standard Supply Voltage Range) (cont’d)

min. max.
RSTIN active current 4)
IRSTL6)
-100 – µA VIN = VIL
RD/WR inact. current7) IRWH5) – -40 µA VOUT = 2.4 V
RD/WR active current7) IRWL6) -500 – µA VOUT = VOLmax
ALE inactive current7) IALEL5) – 40 µA VOUT = VOLmax
ALE active current7) IALEH6) 500 – µA VOUT = 2.4 V
Port 6 inactive current7) IP6H5) – -40 µA VOUT = 2.4 V
Port 6 active current7) IP6L6) -500 – µA VOUT = VOL1max
PORT0 configuration current7) IP0H5) – -10 µA VIN = VIHmin
IP0L6) -100 – µA VIN = VILmax
XTAL1 input current IIL CC – ±20 µA 0 V < VIN < VDD
Pin capacitance8) CIO CC – 10 pF f = 1 MHz
(digital inputs/outputs) TA = 25 °C
1)
Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2)
Valid in bidirectional reset mode only.
3)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
4) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.
5) The maximum current may be drawn while the respective signal line remains inactive.
6) The minimum current must be drawn in order to drive the respective signal line active.
7)
This specification is valid during Reset and during Adapt-mode.
8)
Data Sheet 31 V2.0, 2001-01

C161K
C161O
DC Characteristics (Reduced Supply Voltage Range)

min. max.
Input low voltage (TTL, VIL SR -0.5 0.8 V –
all except XTAL1)
Input low voltage XTAL1 VIL2 SR -0.5 0.3 VDD V –
Input high voltage (TTL, VIH SR 1.8 VDD + V –
all except RSTIN and XTAL1) 0.5
Input high voltage RSTIN VIH1 SR 0.6 VDD VDD + V –
(when operated as input) 0.5
Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD + V –
0.5
Output low voltage VOL CC – 0.45 V IOL = 1.6 mA
RD, WR, BHE, RSTOUT,
RSTIN2))
Output low voltage VOL1 CC – 0.45 V IOL = 1.0 mA
(all other outputs)
Output high voltage3) VOH CC 0.9 VDD – V IOH = -0.5 mA
RD, WR, BHE, RSTOUT)
Output high voltage3) VOH1 CC 0.9 VDD – V IOH = -0.25 mA
(all other outputs)
Input leakage current (Port 5) IOZ1 CC – ±200 nA 0 V < VIN < VDD
Input leakage current (all other) IOZ2 CC – ±500 nA 0.45 V < VIN < VDD
RSTIN inactive current4) IRSTH5) – -10 µA VIN = VIH1
RSTIN active current4) IRSTL6) -100 – µA VIN = VIL
RD/WR inact. current7) IRWH5) – -10 µA VOUT = 2.4 V
RD/WR active current7) IRWL6) -500 – µA VOUT = VOLmax
ALE inactive current7) IALEL5) – 20 µA VOUT = VOLmax
ALE active current7) IALEH6) 500 – µA VOUT = 2.4 V
Port 6 inactive current7) IP6H5) – -10 µA VOUT = 2.4 V
Port 6 active current7) IP6L6) -500 – µA VOUT = VOL1max
Data Sheet 32 V2.0, 2001-01

C161K
C161O
DC Characteristics (Reduced Supply Voltage Range) (cont’d)

min. max.
PORT0 configuration current 7) 5)
IP0H – -5 µA VIN = VIHmin
IP0L6) -100 – µA VIN = VILmax
XTAL1 input current IIL CC – ±20 µA 0 V < VIN < VDD
Pin capacitance8) CIO CC – 10 pF f = 1 MHz
(digital inputs/outputs) TA = 25 °C
1)
Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2)
Valid in bidirectional reset mode only.
3)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
4)
These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.
5)
The maximum current may be drawn while the respective signal line remains inactive.
6) The minimum current must be drawn in order to drive the respective signal line active.
7) This specification is valid during Reset and during Adapt-mode.
8)
Data Sheet 33 V2.0, 2001-01

C161K
C161O
Power Consumption C161K/O (Standard Supply Voltage Range)

(Operating Conditions apply)
min. max.
Power supply current (active) IDD5 – 15 + mA RSTIN = VIL
with all peripherals active 1.8 × fCPU fCPU in [MHz]1)
Idle mode supply current IIDX5 – 2+ mA RSTIN = VIH1
Power-down mode supply IPDO5 – 50 µA VDD = VDDmax2)
current
1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 7.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD - 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.
Power Consumption C161K/O (Reduced Supply Voltage Range)

min. max.
Power supply current (active) IDD3 – 3+ mA RSTIN = VIL
Idle mode supply current IIDX3 – 1+ mA RSTIN = VIH1
Power-down mode supply IPDO3 – 30 µA VDD = VDDmax2)
current
1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 7.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2)
This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD - 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.
Data Sheet 34 V2.0, 2001-01

C161K
C161O
I
mA
100 IDD5max
80
IDD5typ
IDD3max
60
IDD3typ
40
IIDX5max
20
IIDX3max
IIDX5typ
IIDX3typ
0
0 10 20 30 40 MHz fCPU
MCD04860
Figure 7 Supply/Idle Current as a Function of Operating Frequency
Data Sheet 35 V2.0, 2001-01

C161K
C161O
AC Characteristics
Definition of Internal Timing
The internal operation of the C161K/O is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 8).
Direct Clock Drive
fOSC
TCL
fCPU
TCL
Prescaler Operation
fOSC
TCL
fCPU
TCL MCT04826
Figure 8 Generation Mechanisms for the CPU Clock

The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate fCPU. This influence must
be regarded when calculating the timings for the C161K/O.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 9 associates the combinations of these three bits with the respective clock
generation mode.
Data Sheet 36 V2.0, 2001-01

C161K
C161O
Table 9 C161K/O Clock Generation Modes

CLKCFG CPU Frequency External Clock Notes
(P0H.7-5) fCPU = fOSC × F Input Range
0 X X fOSC × 1 1 to 25 MHz Direct drive1)
1 X X fOSC / 2 2 to 50 MHz CPU clock via prescaler
1)
The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 1XXB) the CPU clock is derived
from the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of fOSC for any TCL.
Direct Drive
When direct drive is configured (CLKCFG = 0XXB) the CPU clock is directly driven from
the internal oscillator with the input clock signal.
The frequency of fCPU directly follows the frequency of fOSC so the high and low time of
fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fOSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCLmin = 1/fOSC × DCmin (DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated
so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin therefore has to
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/fOSC.
Data Sheet 37 V2.0, 2001-01

C161K
C161O
AC Characteristics
Table 10 External Clock Drive XTAL1 (Standard Supply Voltage Range)

Parameter Symbol Direct Drive Prescaler Unit
1:1 2:1
min. max. min. max.
Oscillator period tOSC SR 40 – 20 – ns
1) 2)
High time t1 SR 20 – 6 – ns
Low time1) t2 SR 202) – 6 – ns
Rise time1) t3 SR – 10 – 6 ns
Fall time1) t4 SR – 10 – 6 ns
1) The clock input signal must reach the defined levels VIL2 and VIH2.
2) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in
direct drive mode depends on the duty cycle of the clock input signal.
Table 11 External Clock Drive XTAL1 (Reduced Supply Voltage Range)

Parameter Symbol Direct Drive Prescaler Unit
1:1 2:1
min. max. min. max.
Oscillator period tOSC SR 50 – 25 – ns
High time1) t1 SR 252) – 8 – ns
Low time1) t2 SR 252) – 8 – ns
Rise time1) t3 SR – 10 – 6 ns
Fall time1) t4 SR – 10 – 6 ns
1)
The clock input signal must reach the defined levels VIL2 and VIH2.
2)
The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in
direct drive mode depends on the duty cycle of the clock input signal.
Data Sheet 38 V2.0, 2001-01

C161K
C161O
t1 t3 t4
VIH2
0.5 VDD
VIL
t2
t OSC
MCT02534
Figure 9 External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 40 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
Data Sheet 39 V2.0, 2001-01

C161K
C161O
Testing Waveforms
2.4 V
1.8 V 1.8 V
Test Points
0.8 V 0.8 V
0.45 V
’ ’
AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’.
’ ’
Timing measurements are made at VIH min for a logic 1’ and VIL max for a logic 0’.
MCA04414
Figure 10 Input Output Waveforms
VLoad + 0.1 V VOH - 0.1 V

Timing
Reference
Points
VLoad - 0.1 V VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA).
MCA00763
Figure 11 Float Waveforms
Data Sheet 40 V2.0, 2001-01

C161K
C161O
Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Table 12 Memory Cycle Variables

Description Symbol Values
ALE Extension tA TCL × <ALECTL>
Memory Cycle Time Waitstates tC 2TCL × (15 - <MCTC>)
Memory Tristate Time tF 2TCL × (1 - <MTTC>)
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Multiplexed Bus (Standard Supply Voltage Range)

ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock Variable CPU Clock Unit
= 25 MHz 1 / 2TCL = 1 to 25 MHz
min. max. min. max.
ALE high time t5 CC 10 + tA – TCL - 10 – ns
+ tA
Address setup to ALE t6 CC 4 + tA – TCL - 16 – ns
+ tA
Address hold after ALE t7 CC 10 + tA – TCL - 10 – ns
+ tA
ALE falling edge to RD, t8 CC 10 + tA – TCL - 10 – ns
WR (with RW-delay) + tA
ALE falling edge to RD, t9 CC -10 + tA – -10 + tA – ns
WR (no RW-delay)
Address float after RD, t10 CC – 6 – 6 ns
WR (with RW-delay)
Address float after RD, t11 CC – 26 – TCL + 6 ns
WR (no RW-delay)
RD, WR low time t12 CC 30 + tC – 2TCL - 10 – ns
(with RW-delay) + tC
Data Sheet 41 V2.0, 2001-01

C161K
C161O
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)

= 25 MHz 1 / 2TCL = 1 to 25 MHz
min. max. min. max.
(no RW-delay) + tC
RD to valid data in t14 SR – 20 + tC – 2TCL - 20 ns
(no RW-delay) + tC
ALE low to valid data in t16 SR – 40 + tA – 3TCL - 20 ns
+ tC + tA + tC
Address to valid data in t17 SR – 50 + 2tA – 4TCL - 30 ns
+ tC + 2tA + tC
Data hold after RD t18 SR 0 – 0 – ns
rising edge
Data float after RD t19 SR – 26 + tF – 2TCL - 14 ns
+ tF
Data valid to WR t22 CC 20 + tC – 2TCL - 20 – ns
+ tC
Data hold after WR t23 CC 26 + tF – 2TCL - 14 – ns
+ tF
ALE rising edge after RD, t25 CC 26 + tF – 2TCL - 14 – ns
WR + tF
Address hold after RD, t27 CC 26 + tF – 2TCL - 14 – ns
WR + tF
ALE falling edge to CS1) t38 CC -4 - tA 10 - tA - 4 - tA 10 - tA ns
1)
CS low to Valid Data In t39 SR – 40 + tC – 3TCL - 20 ns
+ 2tA + tC + 2 tA
CS hold after RD, WR1) t40 CC 46 + tF – 3TCL - 14 – ns
+ tF
ALE fall. edge to RdCS, t42 CC 16 + tA – TCL - 4 – ns
WrCS (with RW delay) + tA
ALE fall. edge to RdCS, t43 CC -4 + tA – -4 – ns
WrCS (no RW delay) + tA
Data Sheet 42 V2.0, 2001-01

C161K
C161O
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)

= 25 MHz 1 / 2TCL = 1 to 25 MHz
min. max. min. max.
Address float after RdCS, t44 CC – 0 – 0 ns
WrCS (with RW delay)
Address float after RdCS, t45 CC – 20 – TCL ns
WrCS (no RW delay)
RdCS to Valid Data In t46 SR – 16 + tC – 2TCL - 24 ns
(with RW delay) + tC
(no RW delay) + tC
RdCS, WrCS Low Time t48 CC 30 + tC – 2TCL - 10 – ns
(no RW delay) + tC
Data valid to WrCS t50 CC 26 + tC – 2TCL - 14 – ns
+ tC
Data hold after RdCS t51 SR 0 – 0 – ns
Data float after RdCS t52 SR – 20 + tF – 2TCL - 20 ns
+ tF
Address hold after t54 CC 20 + tF – 2TCL - 20 – ns
RdCS, WrCS + tF
Data hold after WrCS t56 CC 20 + tF – 2TCL - 20 – ns
+ tF
1)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet 43 V2.0, 2001-01

C161K
C161O
AC Characteristics
Multiplexed Bus (Reduced Supply Voltage Range)

= 20 MHz 1 / 2TCL = 1 to 20 MHz
min. max. min. max.
+ tA
+ tA
Address hold after ALE t7 CC 15 + tA – TCL - 10 – ns
+ tA
ALE falling edge to RD, t9 CC -10 + tA – -10 + tA – ns
WR (no RW-delay)
Address float after RD, t10 CC – 6 – 6 ns
WR (with RW-delay)
Address float after RD, t11 CC – 31 – TCL + 6 ns
WR (no RW-delay)
(no RW-delay) + tC
(no RW-delay) + tC
ALE low to valid data in t16 SR – 45 + tA – 3TCL - 30 ns
+ tC + tA + tC
Address to valid data in t17 SR – 57 + 2tA – 4TCL - 43 ns
+ tC + 2tA + tC
rising edge
Data Sheet 44 V2.0, 2001-01

C161K
C161O
Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)

= 20 MHz 1 / 2TCL = 1 to 20 MHz
min. max. min. max.
Data float after RD t19 SR – 36 + tF – 2TCL - 14 ns
+ tF
+ tC
Data hold after WR t23 CC 36 + tF – 2TCL - 14 – ns
+ tF
ALE rising edge after RD, t25 CC 36 + tF – 2TCL - 14 – ns
WR + tF
Address hold after RD, t27 CC 36 + tF – 2TCL - 14 – ns
WR + tF
ALE falling edge to CS1) t38 CC -8 - tA 10 - tA -8 - tA 10 - tA ns
CS low to Valid Data In1) t39 SR – 47+ tC – 3TCL - 28 ns
+ 2tA + tC + 2 tA
CS hold after RD, WR1) t40 CC 57 + tF – 3TCL - 18 – ns
+ tF
ALE fall. edge to RdCS, t42 CC 19 + tA – TCL - 6 – ns
WrCS (with RW delay) + tA
ALE fall. edge to RdCS, t43 CC -6 + tA – -6 – ns
WrCS (no RW delay) + tA
Address float after RdCS, t44 CC – 0 – 0 ns
WrCS (with RW delay)
Address float after RdCS, t45 CC – 25 – TCL ns
WrCS (no RW delay)
(no RW delay) + tC
(no RW delay) + tC
Data Sheet 45 V2.0, 2001-01

C161K
C161O
Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)

= 20 MHz 1 / 2TCL = 1 to 20 MHz
min. max. min. max.
+ tC
+ tF
Address hold after t54 CC 30 + tF – 2TCL - 20 – ns
RdCS, WrCS + tF
Data hold after WrCS t56 CC 30 + tF – 2TCL - 20 – ns
+ tF
1)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
Data Sheet 46 V2.0, 2001-01

C161K
C161O
t5 t16 t25
ALE
t38 t39 t40
CSxL
t17 t27
A21-A16
(A15-A8) Address
BHE, CSxE
t6 t54
t7 t19
Read Cycle t18
BUS Address Data IN
t8 t10
t14
t12
RD `
t42 t44 t51

t46 t52
t48
RdCSx
Write Cycle t23
BUS Address Data OUT
t8 t10
t22 t56
t12
WR, WRL,
WRH
t42 t44
t50
t48
WrCSx
MCT04861
Figure 12 External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Normal ALE
Data Sheet 47 V2.0, 2001-01

C161K
C161O
t5 t16 t25
ALE
t38
t39 t40
CSxL
t17 t27
A21-A16
(A15-A8) Address
BHE, CSxE
t6 t7 t54
t19
Read Cycle t18
BUS Address Data IN
t8 t10
t14
t12
RD
t42 t4 t51
t46 t52
t48
RdCSx
Write Cycle t23
t8 t10
t22 t56
t12
WR, WRL,
WRH
t42 t44
t50
t48
WrCSx
MCT04862

Multiplexed Bus, With Read/Write Delay, Extended ALE
Data Sheet 48 V2.0, 2001-01

C161K
C161O
t5 t16 t25
ALE
t38 t39 t40
CSxL
t17 t27
A21-A16
(A15-A8) Address
BHE, CSxE
t6 t54
t7 t19
Read Cycle t18
BUS Address Data IN
t9 t11
t15
t13
RD
t43 t45 t51

t47 t52
t49
RdCSx
Write Cycle t23
t9 t11 t22 t56

t13
WR, WRL,
WRH
t43 t45 t50
t49
WrCSx
MCT04863

Multiplexed Bus, No Read/Write Delay, Normal ALE
Data Sheet 49 V2.0, 2001-01

C161K
C161O
t5 t16 t25
ALE
t38
t39 t40
CSxL
t17 t27
A21-A16
(A15-A8) Address
BHE, CSxE
t6 t7 t54
t19
Read Cycle t18
BUS Address Data IN
t9 t11
t15
t13
RD
t43 t45
t47 t51
t49 t52
RdCSx
Write Cycle t23
t9 t11 t22 t56

t13
WR, WRL,
WRH
t43 t45 t50
t49
WrCSx
MCT04864

Multiplexed Bus, No Read/Write Delay, Extended ALE
Data Sheet 50 V2.0, 2001-01

C161K
C161O
AC Characteristics
Demultiplexed Bus (Standard Supply Voltage Range)

= 25 MHz 1 / 2TCL = 1 to 25 MHz
min. max. min. max.
+ tA
+ tA
ALE falling edge to RD, t9 CC -10 + tA – -10 – ns
WR (no RW-delay) + tA
(no RW-delay) + tC
(no RW-delay) + tC
ALE low to valid data in t16 SR – 40 + – 3TCL - 20 ns
tA + tC + tA + tC
Address to valid data in t17 SR – 50 + – 4TCL - 30 ns
2 tA + tC + 2tA + tC
rising edge
Data float after RD rising t20 SR – 26 + – 2TCL - 14 ns
edge (with RW-delay1)) 2 tA + tF1)
+ 22tA
+ tF1)
Data float after RD rising t21 SR – 10 + – TCL - 10 ns
edge (no RW-delay1)) 2 tA + tF1)
+ 22tA
+ tF1)
Data Sheet 51 V2.0, 2001-01

C161K
C161O
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)

= 25 MHz 1 / 2TCL = 1 to 25 MHz
min. max. min. max.
+ tC
Data hold after WR t24 CC 10 + tF – TCL - 10 – ns
+ tF
ALE rising edge after t26 CC -10 + tF – -10 + tF – ns
RD, WR
Address hold after WR2) t28 CC 0 + tF – 0 + tF – ns
CS low to Valid Data In3) t39 SR – 40 + – 3TCL - 20 ns
tC + 2tA + tC + 2tA
CS hold after RD, WR3) t41 CC 6 + tF – TCL - 14 – ns
+ tF
ALE falling edge to t42 CC 16 + tA – TCL - 4 – ns
RdCS, WrCS (with RW- + tA
delay)
ALE falling edge to t43 CC -4 + tA – -4 – ns
RdCS, WrCS (no RW- + tA
delay)
(no RW-delay) + tC
(no RW-delay) + tC
+ tC
Data Sheet 52 V2.0, 2001-01

C161K
C161O
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)

= 25 MHz 1 / 2TCL = 1 to 25 MHz
min. max. min. max.
(with RW-delay)1) + 2tA + tF
1)
Data float after RdCS t68 SR – 0 + tF – TCL - 20 ns

(no RW-delay)1) + 2tA + tF
1)
Address hold after t55 CC -6 + tF – -6 + tF – ns

RdCS, WrCS
Data hold after WrCS t57 CC 6 + tF – TCL - 14 – ns
+ tF
1)
RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2)
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
Data Sheet 53 V2.0, 2001-01

C161K
C161O
AC Characteristics
Demultiplexed Bus (Reduced Supply Voltage Range)

= 20 MHz 1 / 2TCL = 1 to 20 MHz
min. max. min. max.
+ tA
+ tA
ALE falling edge to RD, t9 CC -10 + tA – -10 – ns
WR (no RW-delay) + tA
(no RW-delay) + tC
(no RW-delay) + tC
ALE low to valid data in t16 SR – 45 + – 3TCL - 30 ns
tA + tC + tA + tC
Address to valid data in t17 SR – 57 + – 4TCL - 43 ns
2 tA + tC + 2tA + tC
rising edge
Data float after RD rising t20 SR – 36 + – 2TCL - 14 ns
edge (with RW-delay1)) 2 tA + tF1)
+ 22tA
+ tF1)
Data float after RD rising t21 SR – 15 + – TCL - 10 ns
edge (no RW-delay1)) 2 tA + tF1)
+ 22tA
+ tF1)
Data Sheet 54 V2.0, 2001-01

C161K
C161O
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)

= 20 MHz 1 / 2TCL = 1 to 20 MHz
min. max. min. max.
+ tC
Data hold after WR t24 CC 15 + tF – TCL - 10 – ns
+ tF
ALE rising edge after t26 CC -12 + tF – -12 + tF – ns
RD, WR
Address hold after WR2) t28 CC 0 + tF – 0 + tF – ns
CS low to Valid Data In3) t39 SR – 47 + – 3TCL - 28 ns
tC + 2tA + tC + 2tA
CS hold after RD, WR3) t41 CC 9 + tF – TCL - 16 – ns
+ tF
ALE falling edge to t42 CC 19 + tA – TCL - 6 – ns
RdCS, WrCS (with RW- + tA
delay)
ALE falling edge to t43 CC -6 + tA – -6 – ns
RdCS, WrCS (no RW- + tA
delay)
(no RW-delay) + tC
(no RW-delay) + tC
+ tC
Data Sheet 55 V2.0, 2001-01

C161K
C161O
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)

= 20 MHz 1 / 2TCL = 1 to 20 MHz
min. max. min. max.
(with RW-delay)1) + 2tA + tF
1)
Data float after RdCS t68 SR – 5 + tF – TCL - 20 ns

(no RW-delay)1) + 2tA + tF
1)
Address hold after t55 CC -16 + tF – -16 + tF – ns

RdCS, WrCS
Data hold after WrCS t57 CC 9 + tF – TCL - 16 – ns
+ tF
1)
RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2)
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
Data Sheet 56 V2.0, 2001-01

C161K
C161O
t5 t16 t26
ALE
t38 t39 t41
CSxL
t17 t28
A21-A16
A15-A0 Address
BHE, CSxE
t6 t55
t20
Read Cycle t18
BUS
(D15-D8) Data IN
D7-D0
t8 t14
t12
RD
t42 t46 t51

t48 t53
RdCSx
Write Cycle t24

BUS
(D15-D8) Data OUT
D7-D0
t8 t22 t57
t12
WR, WRL,
WRH
t42 t50
t48
WrCSx
MCT04865

Demultiplexed Bus, With Read/Write Delay, Normal ALE
Data Sheet 57 V2.0, 2001-01

C161K
C161O
t5 t16 t26
ALE
t38
t39 t41
CSxL
t17 t28
A21-A16
A15-A0 Address
BHE, CSxE
t6 t55
t20
Read Cycle
t18
BUS
(D15-D8) Data IN
D7-D0
t8 t14
t12
RD
t42 t46 t51

t48 t53
RdCSx
Write Cycle
t24
BUS
(D15-D8) Data OUT
D7-D0
t8 t22 t57
t12
WR, WRL,
WRH
t42 t50
t48
WrCSx
MCT04866

Demultiplexed Bus, With Read/Write Delay, Extended ALE
Data Sheet 58 V2.0, 2001-01

C161K
C161O
t5 t16 t26
ALE
t38 t39 t41
CSxL
t17 t28
A21-A16
A15-A0 Address
BHE, CSxE
t6 t55
t21
Read Cycle t18
BUS
(D15-D8) Data IN
D7-D0
t9 t15
t13
RD
t43 t47 t51

t49 t68
RdCSx
Write Cycle t24

BUS
(D15-D8) Data OUT
D7-D0
t22 t57
t9 t13
WR, WRL,
WRH
t43 t50
t49
WrCSx
MCT04867

Demultiplexed Bus, No Read/Write Delay, Normal ALE
Data Sheet 59 V2.0, 2001-01

C161K
C161O
t5 t16 t26
ALE
t38
t39 t41
CSxL
t17 t28
A21-A16
A15-A0 Address
BHE, CSxE
t6 t55
t21
Read Cycle
t18
BUS
(D15-D8) Data IN
D7-D0
t9 t15
t13
RD
t43 t47 t51

t49 t68
RdCSx
Write Cycle
t24
BUS
(D15-D8) Data OUT
D7-D0
t9 t22 t57
t13
WR, WRL,
WRH
t43 t50
t49
WrCSx
MCT04868

Demultiplexed Bus, No Read/Write Delay, Extended ALE
Data Sheet 60 V2.0, 2001-01

C161K
C161O
Package Outlines
P-MQFP-80-1 (SMD)
(Plastic Metric Quad Flat Package)
2.45 max
0.25 min
0.15 +0.08
-0.02
-0.05
2 +0.1
H
7˚max
0.65 0.88
0.3 ±0.08
C 0.1
12.35 0.12 M A-B D C 80x
17.2 0.2 A-B D 80x
14 1) 0.2 A-B D H 4x
D
A B
17.2
14 1)
80
1
Index Marking 0.6x45˚
1) Does not include plastic or metal protrusions of 0.25 max per side
GPR05249
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device Dimensions in mm
Data Sheet 61 V2.0, 2001-01

Infineon goes for Business Excellence
“Business excellence means intelligent approaches and clearly

defined processes, which are both constantly under review and
ultimately lead to good operating results.
Better operating results and business excellence mean less
idleness and wastefulness for all of us, more professional
success, more accurate information, a better overview and,
thereby, less frustration and more satisfaction.”
Dr. Ulrich Schumacher
http://www.infineon.com
Published by Infineon Technologies AG

SABC 1610 LM (Microcontroller)

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Da ta S h e e t , V 2 .0 , J a n .

Revision History: 2001-01 V2.0

We Listen to Your Comments

Data Sheet 1 V2.0, 2001-01

Table 1 C161K/O Derivative Synopsis

Data Sheet 2 V2.0, 2001-01

Figure 1 Logic Symbol

Data Sheet 3 V2.0, 2001-01

Pin Configuration MQFP Package

Data Sheet 4 V2.0, 2001-01

Table 2 Pin Definitions and Functions

Data Sheet 5 V2.0, 2001-01

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 6 V2.0, 2001-01

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 7 V2.0, 2001-01

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 8 V2.0, 2001-01

ProgMem C166-Core IRAM

PEC Osc XTAL

Interrupt Controller 16-Level

Peripheral Data Bus

ASC0 SSC GPT1 GPT2

Port 0 Port 1 Port 3 Port 5

Figure 3 Block Diagram

Data Sheet 9 V2.0, 2001-01

Data Sheet 10 V2.0, 2001-01

External Bus Controller

Data Sheet 11 V2.0, 2001-01

Central Processing Unit (CPU)

Data Page Ptr. Code Seg. Ptr.

Figure 4 CPU Block Diagram

Data Sheet 12 V2.0, 2001-01

Data Sheet 13 V2.0, 2001-01

Data Sheet 14 V2.0, 2001-01

Table 3 C161K/O Interrupt Nodes

Data Sheet 15 V2.0, 2001-01

The C161K/O also provides an excellent mechanism to identify and to process

Table 4 Hardware Trap Summary

Data Sheet 16 V2.0, 2001-01

General Purpose Timer (GPT) Unit

Data Sheet 17 V2.0, 2001-01

Figure 5 Block Diagram of GPT1

Data Sheet 18 V2.0, 2001-01

GPT2 Timer T6 T6OTL T6OUT

Figure 6 Block Diagram of GPT2

Data Sheet 19 V2.0, 2001-01

Data Sheet 20 V2.0, 2001-01

Data Sheet 21 V2.0, 2001-01

Instruction Set Summary

Table 5 Instruction Set Summary

Data Sheet 22 V2.0, 2001-01

Table 5 Instruction Set Summary (cont’d)

Data Sheet 23 V2.0, 2001-01

Special Function Registers Overview

Table 6 C161K/O Registers, Ordered by Name

Data Sheet 24 V2.0, 2001-01

Table 6 C161K/O Registers, Ordered by Name (cont’d)

Data Sheet 25 V2.0, 2001-01

Table 6 C161K/O Registers, Ordered by Name (cont’d)